74FCT3244PYG8

74FCT3244/A 3.3V CMOS OCTAL BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS OCTAL BUFFER/LINE DRIVER 74FCT3244/A DESCRIPTION: FEATURES: • 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ±0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range μW typ. static) • CMOS power levels (0.4μ • Rail-to-Rail output swing for increased noise margin • Available in QSOP, SOIC, SSOP, and TSSOP packages The FCT3244/A octal buffer/line drivers are built using advanced dual metal CMOS technology. These high-speed, low-power buffers are designed to be used as memory data and address drivers, clock drivers, and bus-oriented transmitter/receivers. The three-state controls are designed to operate these devices in a dual-nibble or single-byte mode. All inputs are designed with hysteresis for improved noise margin. FUNCTIONAL BLOCK DIAGRAM 1OE 1 1A1 2 18 1A2 4 16 1A3 6 14 1A4 8 12 2OE 19 9 2A2 13 7 2A3 15 5 2A4 17 3 INDUSTRIAL TEMPERATURE RANGE 1 Feb.11.20 1Y2 1Y3 1Y4 11 2A1 1Y1 2Y1 2Y2 2Y3 2Y4 74FCT3244/A 3.3V CMOS OCTAL BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION 1OE Vcc 1A 1 1 2 20 19 2OE 2Y 4 3 18 1Y1 1 A2 4 17 2A 4 2Y 3 5 16 1Y 2 1A3 6 7 15 14 2A 3 8 13 2A 2 9 10 12 11 1Y 4 2Y 2 1A 4 2Y 1 GND Symbol Description VTERM(2) Max Terminal Voltage with Respect to GND –0.5 to +4.6 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to +7 V VTERM(4) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –60 to +60 mA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. Input terminals. 4. Outputs and I/O terminals. 1Y 3 2A 1 TOP VIEW CAPACITANCE (TA = +25°C, F = 1.0MHz) Package Type Package Code Order Code QSOP PCG20 QG SOIC PSG20 SOG TSSOP PGG20 PGG SSOP PYG20 PYG Parameter(1) Symbol Conditions Typ. Max. Input Capacitance VIN = 0V 3.5 6 pF COUT Output Capacitance VOUT = 0V 4 8 pF NOTE: 1. This parameter is measured at characterization but not tested. Pin Names Description xOE 3–State Output Enable Inputs (Active LOW) xAx Data Inputs xYx 3-State Outputs FUNCTION TABLE(1) Inputs xOE Outputs xAx xYx L L L L H H H X Z NOTE: 1. H = HIGH Voltage Level X = Don’t Care L = LOW Voltage Level Z = High Impedance 2 Unit CIN PIN DESCRIPTION Feb.11.20 Unit 74FCT3244/A 3.3V CMOS OCTAL BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40°C to +85°C, VCC = 2.7V to 3.6V Symbol VIH Parameter Input HIGH Level (Input pins) Test Conditions(1) Guaranteed Logic HIGH Level Input HIGH Level (I/O pins) VIL Input LOW Level Guaranteed Logic LOW Level Min. 2 Typ.(2) — Max. 5.5 2 — Vcc+0.5 –0.5 — 0.8 V µA Unit V (Input and I/O pins) IIH VI = 5.5V — — ±1 VI = VCC — — ±1 Input LOW Current (Input pins) VI = GND — — ±1 Input LOW Current (I/O pins) VI = GND — — ±1 VO = VCC — — ±1 VO = GND — — ±1 Input HIGH Current (Input pins) VCC = Max. Input HIGH Current (I/O pins) IIL IOZH High Impedance Output Current IOZL (3-State Output pins) VCC = Max. µA VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V IODH Output HIGH Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) –36 –60 –110 mA IODL Output LOW Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) VOH Output HIGH Voltage VCC = Min. IOH = –0.1mA VIN = VIH or VIL VCC = 3V 50 90 200 mA VCC–0.2 — — V IOH = –3mA 2.4 3 — IOH = –8mA 2.4(5) 3 — IOL = 0.1mA — — 0.2 IOL = 16mA — 0.2 0.4 IOL = 24mA — 0.3 0.55 0.3 0.5 VIN = VIH or VIL VOL Output LOW Voltage VCC = Min. VIN = VIH or VIL VCC = 3V IOL = 24mA V VIN = VIH or VIL IOS Short Circuit Current(4) VCC = Max., VO = GND(3) –60 –135 –240 mA VH Input Hysteresis — — 150 — mV ICCL ICCH ICCZ Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 0.1 10 µA NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient and maximum loading. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC - 0.6V at rated current. 3 Feb.11.20 74FCT3244/A 3.3V CMOS OCTAL BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Test Conditions(1) Typ.(2) Symbol Parameter Min. Max. Unit ICC Quiescent Power Supply Current VCC = Max. VIN = VCC - 0.6V — 2 30 μA ICCD Dynamic Power Supply Current(4) VCC = Max. Outputs Open xOE = GND VIN = VCC VIN = GND — 60 85 μA/ MHz VCC = Max. Outputs Open fI = 10MHz VIN = VCC VIN = GND — 0.6 0.9 mA 50% Duty Cycle xOE = GND VIN = VCC - 0.6V VIN = GND — 0.6 0.9 VCC = Max. Outputs Open fI = 2.5MHz VIN = VCC VIN = GND — 1.2 1.7(5) 50% Duty Cycle xOE = GND VIN = VCC - 0.6V VIN = GND — 1.2 1.8(5) One Input Toggling 50% Duty Cycle Total Power Supply Current(6) IC One Bit Toggling Eight Bits Toggling NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Per TTL driven input. All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ΔICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICC, ICCH, and ICCZ) ΔICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for register devices (zero for non-register devices) NCP = Number of clock inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi SWITCHING CHARACTERISTICS OVER OPERATING RANGE(1) 74FCT3244 Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay xAx to xYx Output Enable Time Condition(2) CL = 50pF RL = 500Ω Output Disable Time 74FCT3244A Max. 4.8 Min.(3) 1.5 Max. 6.5 Min.(3) 1.5 Unit ns 1.5 8 1.5 6.2 ns 1.5 7 1.5 5.6 ns NOTES: 1. Propagation Delays and Enable/Disable times are with VCC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays and Enable/ Disable times should be degraded by 20%. 2. See test circuit and waveforms. 3. Minimum limits are guaranteed but not tested on Propagation Delays. 4 Feb.11.20 74FCT3244/A 3.3V CMOS OCTAL BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS 6v Open V CC 500Ω SWITCH POSITION GND V OUT VIN Pulse Generator D.U.T. 50pF RT 500Ω CL tH tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tSU tH Switch 6V Disable High Enable High GND All Other Tests Open DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Test Circuits for All Outputs DATA INPUT Test Open Drain Disable Low Enable Low 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V 3V 1.5V 0V Pulse Width Set-Up, Hold, and Release Times ENABLE DISABLE 3V CONTROL INPUT SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH tPHL tPZL 3V 1.5V 0V VOH 1.5V VOL OUTPUT NORMALLY LOW tPLZ 3V 1.5V tPZH OUTPUT NORMALLY HIGH 3V 1.5V 0V OPPOSITE PHASE INPUT TRANSITION SWITCH 6V Propagation Delay SWITCH GND 1.5V 0V 3V 0.3V VOL tPHZ 0.3V VOH 1.5V 0V 0V Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; ZO ≤ 50Ω; tF ≤ 2.5ns; tR ≤ 2.5ns. 3. If Vcc is below 3V, input voltage swings should be adjusted not to exceed Vcc. 5 Feb.11.20 74FCT3244/A 3.3V CMOS OCTAL BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION XX FCT Temp. Range X Family XXXX Device Type XX Package X X Blank 8 Tube Tape and Reel G Green SO PY Q PG Small Outline IC (PSG20) Shrink Small Outline Package (PYG20) Quarter-size Small Outline Package (PCG20) Thin Shrink Small Outline Package (PGG20) 244 244A Octal Buffer/Line Driver 3 3.3 Volt 74 -40°C to +85°C Orderable Part Information Speed (ns) A Orderable Part ID 74FCT3244APGG Speed (ns) Pkg. Code Pkg. Type Temp. Grade Pkg. Code Pkg. Type Temp. Grade PGG20 TSSOP I 74FCT3244PGG PGG20 TSSOP I PGG20 TSSOP I Orderable Part ID 74FCT3244APGG8 PGG20 TSSOP I 74FCT3244PGG8 74FCT3244APYG PYG20 SSOP I 74FCT3244PYG PYG20 SSOP I 74FCT3244APYG8 PYG20 SSOP I 74FCT3244PYG8 PYG20 SSOP I 74FCT3244AQG PCG20 QSOP I 74FCT3244QG PCG20 QSOP I 74FCT3244AQG8 PCG20 QSOP I 74FCT3244QG8 PCG20 QSOP I 74FCT3244ASOG PSG20 SOIC I 74FCT3244SOG PSG20 SOIC I 74FCT3244ASOG8 PSG20 SOIC I 74FCT3244SOG8 PSG20 SOIC I Datasheet Document History 09/30/2009 08/31/2011 07/31/2017 Pg. 6 Pg. 6 Pgs. 2, 6 05/23/2018 02/11/2020 Pg. 6 Pgs. 1-7 Updated the ordering information by removing the "IDT" notation and non RoHS part. Added PGG to ordering information. Added table under pin configuration diagram with detailed package information. Updated the ordering information diagram adding Tube, Tape and Reel. Added new table of orderable part information. Updated new table of orderable part information. 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