74LVC16374APVG

IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT IDT74LVC16374A EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: The LVC16374A 16-bit edge-triggered D-type flip-flop is built using advanced dual metal CMOS technology. This high-speed, low-power register is ideal for use as a buffer register for data synchronization and storage. The Output Enable (OE) and clock (CLK) controls are organized to operate this device as two 8-bit registers or one 16-bit register with common clock. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. All pins of the LVC16374A can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/ 5V supply system. The LVC16374A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range μ W typ. static) • CMOS power levels (0.4μ • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in TSSOP package DRIVE FEATURES: • High Output Drivers: ±24mA • Reduced system switching noise APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM 1OE 1CLK 1D1 1 48 47 D C 2 2OE 24 2CLK 25 2D1 36 D 13 C 1Q1 2Q1 TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE AUGUST 2015 1 © 2015 Integrated Device Technology, Inc. DSC-4752/6 IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description Max Unit VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V 1OE 1 48 1CLK TSTG Storage Temperature –65 to +150 °C 1Q1 2 47 1D1 IOUT DC Output Current –50 to +50 mA Continuous Clamp Current, VI < 0 or VO < 0 –50 mA Continuous Current through each VCC or GND ±100 mA 1Q2 3 46 1D2 IIK IOK GND 4 45 GND ICC ISS 1Q3 5 44 1D3 1Q4 6 VCC 7 42 VCC 1Q5 8 41 1D5 1Q6 9 40 1D6 GND 10 39 GND 1Q7 11 38 1D7 CIN Input Capacitance VIN = 0V 4.5 6 pF COUT Output Capacitance VOUT = 0V 6.5 8 pF CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF 43 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1D4 CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Symbol Conditions Typ. Max. 1Q8 12 37 1D8 2Q1 13 36 2D1 2Q2 14 35 2D2 GND 15 34 GND 2Q3 16 33 2D3 2Q4 17 32 2D4 18 xDx Data Inputs VCC 31 VCC xCLK Clock Inputs 2Q5 19 30 2D5 xOE 3-State Output Enable Inputs (Active LOW) 29 2D6 3-State Outputs 2Q6 20 xQx GND 21 28 GND 2Q7 22 27 2D7 2Q8 23 26 2D8 2OE 24 25 2CLK Unit NOTE: 1. As applicable to the device type. PIN DESCRIPTION Pin Names Description FUNCTION TABLE(EACH FLIP-FLOP)(1) Inputs TSSOP TOP VIEW Outputs xDx xCLK xOE xQx X L H Z X H H Z L ↑ L L H ↑ L H L H L Q(2) H L L Q(2) NOTES: 1. H = HIGH Voltage Level X = Don’t Care L = LOW Voltage Level Z = High-Impedance 2. Output level before the indicated steady-state input conditions were established. 2 IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 μA IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 μA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 μA VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ΔICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 — — 10 mV μA 3.6 ≤ VIN ≤ 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND — — — — 10 500 μA IIH IIL Quiescent Power Supply Current Variation NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. OUTPUT DRIVE CHARACTERISTICS Symbol VOH Test Conditions(1) Parameter Output HIGH Voltage VCC = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V IOH = – 6mA VCC = 2.3V IOH = – 12mA VCC = 2.7V VCC = 3V VOL Output LOW Voltage Min. Max. Unit VCC – 0.2 — V 2 — 1.7 — 2.2 — 2.4 — VCC = 3V IOH = – 24mA 2.2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. 3 IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance per Flip-Flop Outputs enabled CPD Power Dissipation Capacitance per Flip-Flop Outputs disabled Test Conditions Typical Unit CL = 0pF, f = 10Mhz 58 pF 24 SWITCHING CHARACTERISTICS(1) VCC = 2.7V Symbol Parameter fMAX tPLH Propagation Delay tPHL xCLK to xQx tPZH Output Enable Time VCC = 3.3V ± 0.3V Min. Max. Min. Max. Unit 150 — 150 — MHz — 4.9 1.5 4.5 ns — 5.3 1.5 4.6 ns — 6.1 1.5 5.5 ns tPZL xOE to xQx tPHZ Output Disable Time tPLZ xOE to xQx tSU Set-up Time HIGH or LOW, xDx to xCLK 1.9 — 1.9 — ns tH Hold Time HIGH or LOW, xDx after xCLK 1.1 — 1.1 — ns xCLK Pulse Width HIGH or LOW 3.3 — 3.3 — ns Output Skew(2) — — — 500 ps tW tSK(o) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF Pulse (1, 2) Generator VIN DISABLE tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500 CL DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Switch VLOAD TIMING INPUT Disable High Enable High GND ASYNCHRONOUS CONTROL All Other Tests Open SYNCHRONOUS CONTROL tSK (x) tPLH2 VOH VT VOL tH tREM tSU tH LOW-HIGH-LOW PULSE VT tW HIGH-LOW-HIGH PULSE VT LVC Link tPHL2 Pulse Width tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V Set-up, Hold, and Release Times VOH VT VOL OUTPUT 2 VOH VOH-VHZ 0V VT 0V LVC Link VIH VT 0V tSK (x) tPHZ Enable and Disable Times DATA INPUT tPHL1 VLOAD/2 VOL+VLZ VOL NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION Open Drain Disable Low Enable Low tPLZ VLOAD/2 VT LVC Link NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. Test VIH VT 0V CONTROL INPUT Test Circuit for All Outputs OUTPUT 1 VIH VT 0V ENABLE GND VOUT tPLH1 tPHL Propagation Delay LVC Link INPUT tPLH LVC Link D.U.T. RT tPHL OPPOSITE PHASE INPUT TRANSITION Open 500 tPLH OUTPUT VLOAD VCC VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION LVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74LVC16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION X LVC XX Bus-Hold Temp. Range XX Family XX XXXX Device Type Package X Blank 8 Tube or Tray Tape and Reel PAG Thin Shrink Small Outline Package - Green 374A 16-Bit Edge-Triggered D-Type Flip-Flop with 3-State Outputs, 5 Volt Tolerant I/O 16 Double-Density, ±24mA Blank No Bus-hold 74 -40°C to +85°C DATASHEET DOCUMENT HISTORY 08/20/2015 Pg. 6 Updated the ordering information by removing SSOP, TVSOP, non RoHS parts and adding Tape and Reel information. 6 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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