7641

REJ09B0336-0200 8 7641 Group User's Manual RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 7600 SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). Rev. 2.00 Revision date: Aug 28, 2006 www.renesas.com Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 2. 3. 4. 5. 6. 7. 8. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http:// www.renesas.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. B EFORE USING THIS MANUAL This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. Chapter 3 also includes necessary information for systems development. You must refer to that chapter. 1. Organization q C HAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. q C HAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of relevant registers. q C HAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer, such as the electrical characteristics, the notes, and the list of registers. ✽ For the mask ROM confirmation form, the ROM programming confirmation form, and the mark specifications, refer to the “Renesas Technology” Homepage (http://www.renesas.com/en/rom). 2. Structure of register The figure of each register structure describes its functions, contents at reset, and attributes as follows : (Note 2) Bits b7 b6 b5 b4 b3 b2 b1 b0 0 Bit attributes (Note 1) Contents immediately after reset release CPU mode register (CPUM) [Address : 3B16] B 0 1 2 3 4 5 6 7 Stack page selection bit Name Processor mode bits b1 b0 Function 0 0 : Single-chip mode 01: 1 0 : Not available 11: 0 : 0 page 1 : 1 page At reset RW 0 0 0 0 0 1 ✽ ✽ ✕ ✕ Nothing arranged for these bits. These are write disabled bits. When these bits are read out, the contents are “0.” Fix this bit to “0.” Main clock (XIN-XOUT) stop bit Internal system clock selection bit 0 : Operating 1 : Stopped 0 : XIN-XOUT selected 1 : XCIN-XCOUT selected : Bit in which nothing is arranged : Bit that is not used for control of the corresponding function Note 1:. Contents immediately after reset release 0....... “0” at reset release 1....... “1” at reset release ?....... Undefined at reset release ✽.......Contents determined by option at reset release Note 2: Bit attributes......... The attributes of control register bits are classified into 3 bytes : read-only, writeonly and read and write. In the figure, these attributes are represented as follows : R....... Read ...... Read enabled ✕.......Read disabled W......Write ..... Write enabled ✕...... Write disabled 3. Supplementation For details of development support tools, refer to the “Renesas Technology” Homepage (http://www.renesas.com). Table of contents 7641 Group Table of contents CHAPTER 1 HARDWARE DESCRIPTION ................................................................................................................................... 2 FEATURES ........................................................................................................................................ 2 APPLICATION ................................................................................................................................... 2 PIN CONFIGURATION ..................................................................................................................... 3 FUNCTIONAL BLOCK ..................................................................................................................... 4 PIN DESCRIPTION ........................................................................................................................... 5 PART NUMBERING .......................................................................................................................... 7 GROUP EXPANSION ....................................................................................................................... 8 Memory Type ............................................................................................................................... 8 Memory Size ................................................................................................................................ 8 Packages ...................................................................................................................................... 8 FUNCTIONAL DESCRIPTION ......................................................................................................... 9 Central Processing Unit (CPU) ................................................................................................. 9 Memory ....................................................................................................................................... 13 I/O Ports ..................................................................................................................................... 15 Interrupts .................................................................................................................................... 21 Timers ......................................................................................................................................... 25 Serial I/O .................................................................................................................................... 29 UART1, UART2 ......................................................................................................................... 33 DMAC .......................................................................................................................................... 39 USB Function ............................................................................................................................. 44 Master CPU Bus Interface ....................................................................................................... 60 Count Source Generator .......................................................................................................... 65 Frequency Synthesizer ............................................................................................................. 67 Reset Circuit .............................................................................................................................. 69 Clock Generating Circuit .......................................................................................................... 71 Processor Mode ......................................................................................................................... 75 FLASH MEMORY MODE ............................................................................................................... 81 NOTES ON PROGRAMMING ...................................................................................................... 108 USAGE NOTES ............................................................................................................................. 111 DATA REQUIRED FOR MASK ORDERS ................................................................................. 112 FUNCTIONAL DESCRIPTION SUPPLEMENT .......................................................................... 113 CHAPTER 2 APPLICATION 2.1 I/O port ........................................................................................................................................ 2 2.1.1 Memory map ...................................................................................................................... 2 2.1.2 Related registers ............................................................................................................... 3 2.1.3 Key-on wake-up interrupt application example ............................................................. 7 2.1.4 Terminate unused pins ..................................................................................................... 9 2.1.5 Notes on I/O port ............................................................................................................ 10 2.1.6 Termination of unused pins ........................................................................................... 11 2.2 Timer .......................................................................................................................................... 12 2.2.1 Memory map .................................................................................................................... 12 2.2.2 Related registers ............................................................................................................. 13 2.2.3 Timer application examples ........................................................................................... 20 2.2.4 Notes on timer ................................................................................................................. 37 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 1 of 13 Table of contents 7641 Group 2.3 Serial I/O ................................................................................................................................... 38 2.3.1 Memory map .................................................................................................................... 38 2.3.2 Related registers ............................................................................................................. 39 2.3.3 Serial I/O connection examples .................................................................................... 42 2.3.4 Serial I/O application examples .................................................................................... 44 2.3.5 Notes on serial I/O ......................................................................................................... 51 2.4 UART ......................................................................................................................................... 52 2.4.1 Memory map .................................................................................................................... 52 2.4.2 Related registers ............................................................................................................. 53 2.4.3 UART transfer data format ............................................................................................ 60 2.4.4 Transfer bit rate .............................................................................................................. 61 2.4.5 Operation of transmitting and receiving ....................................................................... 64 2.4.6 UART application example............................................................................................. 66 2.4.7 Notes on UART ............................................................................................................... 77 2.5 DMAC ......................................................................................................................................... 79 2.5.1 Memory map .................................................................................................................... 79 2.5.2 Related registers ............................................................................................................. 80 2.5.3 DMAC operation description .......................................................................................... 88 2.5.4 DMAC arbitration ............................................................................................................. 92 2.5.5 Transfer time .................................................................................................................... 92 2.5.6 DMAC application example ............................................................................................ 95 2.5.7 Notes on DMAC .............................................................................................................. 99 2.6 USB .......................................................................................................................................... 100 2.7 Frequency synthesizer ........................................................................................................ 101 2.7.1 Memory map .................................................................................................................. 101 2.7.2 Related registers ........................................................................................................... 102 2.7.3 Functional description ................................................................................................... 105 2.7.4 Notes on frequency synthesizer .................................................................................. 107 2.8 Master CPU bus interface .................................................................................................. 108 2.8.1 Memory map .................................................................................................................. 108 2.8.2 Related registers ........................................................................................................... 109 2.8.3 Functional description ................................................................................................... 111 2.8.4 Operation description .................................................................................................... 113 2.8.5 Master CPU bus interface application example ........................................................ 114 2.8.6 Notes on master CPU bus interface .......................................................................... 115 2.9 Special count source generator (SCSG) ......................................................................... 116 2.9.1 Memory map .................................................................................................................. 116 2.9.2 Related registers ........................................................................................................... 117 2.9.3 Functional description ................................................................................................... 119 2.10 External devices connection ........................................................................................... 120 2.10.1 Memory map ................................................................................................................ 120 2.10.2 Related registers ......................................................................................................... 121 2.10.3 Functional description ................................................................................................. 122 2.10.4 Slow memory wait ....................................................................................................... 123 2.10.5 HOLD function ............................................................................................................. 126 2.10.6 Expanded data memory access ................................................................................ 127 2.10.7 External devices connection example ...................................................................... 128 2.10.8 Notes on external devices connection ..................................................................... 132 2.11 Reset ..................................................................................................................................... 134 2.11.1 Connection example of reset IC ............................................................................... 134 2.11.2 Notes on reset ............................................................................................................. 134 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 2 of 13 Table of contents 7641 Group 2.12 Clock generating circuit ................................................................................................... 135 2.12.1 Memory map ................................................................................................................ 135 2.12.2 Related registers ......................................................................................................... 136 2.12.3 Stop mode .................................................................................................................... 139 2.12.4 Wait mode .................................................................................................................... 140 2.12.5 Clock generating circuit application examples ........................................................ 141 CHAPTER 3 APPENDIX 3.1 Electrical characteristics ........................................................................................................ 2 3.1.1 Absolute maximum ratings ............................................................................................... 2 3.1.2 Recommended operating conditions (In Vcc = 5 V) .................................................... 3 3.1.3 Electrical characteristics (In Vcc = 5 V) ........................................................................ 4 3.1.4 Recommended Operating Conditions (In Vcc = 3 V) ................................................ 10 3.1.5 Electrical Characteristics (In Vcc = 3 V) ..................................................................... 11 3.2 Standard characteristics ....................................................................................................... 23 3.2.1 Power source current standard characteristics ........................................................... 23 3.2.2 Port standard characteristics ......................................................................................... 24 3.3 Notes on use ........................................................................................................................... 27 3.3.1 Notes on interrupts ......................................................................................................... 27 3.3.2 Notes on serial I/O ......................................................................................................... 28 3.3.3 Notes on UART ............................................................................................................... 29 3.3.4 Notes on DMAC .............................................................................................................. 31 3.3.5 Notes on USB .................................................................................................................. 32 3.3.6 Notes on frequency synthesizer .................................................................................... 36 3.3.7 Notes on master CPU bus interface ............................................................................ 36 3.3.8 Notes on external devices connection ......................................................................... 36 3.3.9 Notes on timer ................................................................................................................. 38 3.3.10 Notes on Stop mode .................................................................................................... 39 3.3.11 Notes on reset ............................................................................................................... 39 3.3.12 Notes on I/O port .......................................................................................................... 39 3.3.13 Notes on programming ................................................................................................. 40 3.3.14 Termination of unused pins ......................................................................................... 42 3.3.15 Notes on CPU rewrite mode for flash memory version .......................................... 43 3.4 Countermeasures against noise ......................................................................................... 44 3.4.1 Shortest wiring length ..................................................................................................... 44 3.4.2 Connection of bypass capacitor across Vss line and Vcc line ................................ 45 3.4.3 Oscillator concerns .......................................................................................................... 46 3.4.4 Setup for I/O ports .......................................................................................................... 47 3.4.5 Providing of watchdog timer function by software ..................................................... 48 3.5 Control registers ..................................................................................................................... 49 3.6 Package outline ...................................................................................................................... 92 3.7 Machine instructions ............................................................................................................. 94 3.8 List of instruction code ...................................................................................................... 105 3.9 SFR memory map ................................................................................................................. 106 3.10 Pin configuration ................................................................................................................ 107 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 3 of 13 List of figures 7641 Group List of figures CHAPTER 1 HARDWARE Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 1 M37641M8-XXXFP, M37641F8FP pin configuration ......................................................... 3 2 M37641M8-XXXHP, M37641F8HP pin configuration ........................................................ 3 3 Functional block diagram ...................................................................................................... 4 4 Part numbering ....................................................................................................................... 7 5 Memory expansion plan ........................................................................................................ 8 6 7600 series CPU register structure .................................................................................... 9 7 Register push and pop at interrupt generation and subroutine call ............................ 10 8 Structure of CPU mode register ........................................................................................ 12 9 Memory map diagram ......................................................................................................... 13 10 Memory map of special function register (SFR) ........................................................... 14 11 Structure of port control and port P2 pull-up control registers ................................... 15 12 Port block diagram (1) ...................................................................................................... 17 13 Port block diagram (2) ...................................................................................................... 18 14 Port block diagram (3) ...................................................................................................... 19 15 Port block diagram (4) ...................................................................................................... 20 16 Interrupt control ................................................................................................................ 21 17 Structure of interrupt-related registers ............................................................................ 23 18 Connection example when using key input interrupt and port P2 block diagram ... 24 19 Timer block diagramn ....................................................................................................... 25 20 Structure of timer X mode register ................................................................................. 26 21 Structure of timer Y mode register ................................................................................. 27 22 Structure of timer 123 mode register ............................................................................. 28 23 Structure of serial I/O control registers 1, 2 ................................................................. 29 24 Block diagram of serial I/O .............................................................................................. 30 25 Serial I/O timing ................................................................................................................. 31 26 UARTx (x = 1, 2) block diagram .................................................................................... 33 27 UARTx transmit timing (CTS function enabled) ............................................................ 34 28 UARTx transmit timing (CTS function disbled) ............................................................. 35 29 UARTx transmit timing (RTS function enabled) .......................................................... 35 30 Structure of UART related registers ............................................................................... 38 31 DMACx (x = 0, 1) block diagram .................................................................................... 39 32 Structure of DMACx related register ............................................................................. 40 33 Timing chart for cycle steal transfer caused by hardware-related transfer request ............................................................................................................................................ 42 34 Timing chart for cycle steal transfer caused by software trigger transfer request .. 42 35 Timing chart for burst transfer caused by hardware-related transfer request .......... 43 36 USB FCU (USB Function Control Unit) block ............................................................... 44 37 Structure of USB control register .................................................................................... 48 38 Structure of USB address register .................................................................................. 49 39 Structure of USB power management register ............................................................. 49 40 Structure of USB interrupt status register 1 ................................................................ 50 41 Structure of USB interrupt status register 2 ................................................................ 51 42 Structure of USB interrupt enable register 1 ............................................................... 52 43 Structure of USB interrupt enable register 2 ............................................................... 52 44 Structure of USB frame number registers ..................................................................... 53 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 4 of 13 List of figures 7641 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Structure of USB frame number registers ..................................................................... 53 Structure of USB endpoint 0 IN control register ........................................................... 54 Structure of USB endpoint x (x = 1 to 4) IN control register ..................................... 55 Structure of USB endpoint x (x = 1 to 4) OUT control register ................................. 56 Structure of USB endpoint x IN max. packet size register ......................................... 57 Structure of USB endpoint x OUT max. packet size register ..................................... 57 Structure of USB endpoint x (x = 0 to 4) OUT write count registers ....................... 58 Structure of USB endpoint x (x = 0 to 4) FIFO register ............................................. 58 Structure of USB endpoint FIFO mode register ............................................................ 59 Interrupt request circuit of data bus buffer .................................................................... 60 Structure of master CPU bus interface related registers ............................................ 61 Master CPU bus interface block diagram ...................................................................... 62 Special count source generator block diagram ............................................................. 65 Structure of special count source generator mode register ........................................ 66 Frequency synthesizer block diagram ............................................................................ 67 Structure of frequency synthesizer control register ...................................................... 68 Reset circuit example ....................................................................................................... 69 Reset sequence ................................................................................................................. 69 Internal status at reset ..................................................................................................... 70 Ceramic resonator or quartz-crystal oscillator external circuit .................................... 71 External clock input circuit ............................................................................................... 71 Structure of clock control register ................................................................................... 72 Clock generating circuit block diagram .......................................................................... 73 State transitions of clock .................................................................................................. 74 Memory maps in processor modes other than single-chip mode ............................... 75 Structure of CPU mode register A .................................................................................. 76 Structure of CPU mode register B .................................................................................. 76 Software wait timing diagram .......................................................................................... 77 RDY wait timing diagram .................................................................................................. 77 Extended RDY wait (software wait plus RDY input anytime wait) timing diagram .. 78 Hold function timing diagram ........................................................................................... 79 STA ($ zz), Y instruction sequence when EDMA enabled .......................................... 80 LDA ($ zz), Y instruction sequence when EDMA enabled and T flag = “ 0 ” ............ 80 LDA ($ zz), Y instruction sequence when EDMA enabled and T flag = “ 1 ” ............ 80 Block diagram of built-in flash memory .......................................................................... 82 Structure of flash memory control register .................................................................... 83 CPU rewrite mode set/release flowchart ........................................................................ 84 Program flowchart .............................................................................................................. 86 Erase flowchart .................................................................................................................. 87 Full status check flowchart and remedial procedure for errors .................................. 89 Structure of ROM code protect control .......................................................................... 90 ID code store addresses .................................................................................................. 91 Pin connection diagram in standard serial I/O mode (1) ............................................ 95 Pin connection diagram in standard serial I/O mode (2) ............................................ 96 Timing for page read ........................................................................................................ 98 Timing for reading status register ................................................................................... 98 Timing for clear status register ....................................................................................... 99 Timing for page program .................................................................................................. 99 Timing for block erasing ................................................................................................. 100 Timing for erase all blocks ............................................................................................ 100 Timing for download ........................................................................................................ 101 Timing for version information output ........................................................................... 102 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 5 of 13 List of figures 7641 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 97 Timing for Boot ROM area output ................................................................................ 102 98 Timing for ID check ......................................................................................................... 103 99 ID code storage addresses ............................................................................................ 103 100 Full status check flowchart and remedial procedure for errors .............................. 106 101 Example circuit application for standard serial I/O mode ........................................ 107 102 Passive components near LPF pin ............................................................................. 111 103 Peripheral circuit ............................................................................................................ 111 104 Timing chart after interrupt occurs .............................................................................. 113 105 Time up to execution of interrupt processing routine .............................................. 113 CHAPTER 2 APPLICATION Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.1.1 Memory map of registers related to I/O port .............................................................. 2 2.1.2 Structure of Port Pi register .......................................................................................... 3 2.1.3 Structure of Port P4, Port P7 registers ....................................................................... 3 2.1.4 Structure of Port Pi direction register (i = 0, 1, 2, 3, 5, 6, 8) ................................. 4 2.1.5 Structure of Port P4 direction, Port P7 direction registers ....................................... 4 2.1.6 Structure of Port control register .................................................................................. 5 2.1.7 Structure of Port P2 pull-up control register ............................................................... 5 2.1.8 Structure of Interrupt request register C ..................................................................... 6 2.1.9 Structure of Interrupt control register C ....................................................................... 6 2.1.10 Registers setting ............................................................................................................ 7 2.1.11 Connection diagram ...................................................................................................... 8 2.1.12 Control procedure .......................................................................................................... 8 2.2.1 Memory map of registers relevant to timers ............................................................. 12 2.2.2 Structure of Timer i (i=1, 2, 3) .................................................................................... 13 2.2.3 Structure of Timer 123 mode register ........................................................................ 13 2.2.4 Structure of Timer X (low-order, high-order) ............................................................. 14 2.2.5 Structure of Timer X mode register ............................................................................ 15 2.2.6 Structure of Timer Y (low-order, high-order) ............................................................. 16 2.2.7 Structure of Timer Y mode register ............................................................................ 17 2.2.8 Structure of Interrupt request register B .................................................................... 18 2.2.9 Structure of Interrupt request register C ................................................................... 18 2.2.10 Structure of Interrupt control register B ................................................................... 19 2.2.11 Structure of Interrupt control register C ................................................................... 19 2.2.12 Timers connection and setting of division ratios .................................................... 21 2.2.13 Related registers setting ............................................................................................ 22 2.2.14 Control procedure ........................................................................................................ 23 2.2.15 Peripheral circuit example .......................................................................................... 24 2.2.16 Timers connection and setting of division ratios .................................................... 24 2.2.17 Relevant registers setting .......................................................................................... 25 2.2.18 Control procedure ........................................................................................................ 26 2.2.19 How to measure frequency ........................................................................................ 27 2.2.20 Related registers setting ............................................................................................ 28 2.2.21 Control procedure ........................................................................................................ 29 2.2.22 Timers connection and setting of division ratios .................................................... 30 2.2.23 Relevant registers setting .......................................................................................... 31 2.2.24 Control procedure (1) ................................................................................................. 32 2.2.25 Control procedure (2) ................................................................................................. 33 2.2.26 Circuit example ............................................................................................................ 34 2.2.27 Related registers setting ............................................................................................ 35 2.2.28 Control procedure ........................................................................................................ 36 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 6 of 13 List of figures 7641 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.3.1 Memory map of registers related to serial I/O ......................................................... 38 2.3.2 Structure of Serial I/O shift register ........................................................................... 39 2.3.3 Structure of Serial I/O control register 1 ................................................................... 39 2.3.4 Structure of Serial I/O control register 2 ................................................................... 40 2.3.5 Structure of Interrupt request register C ................................................................... 41 2.3.6 Structure of Interrupt control register C ..................................................................... 41 2.3.7 Serial I/O connection examples (1) ............................................................................ 42 2.3.8 Serial I/O connection examples (2) ............................................................................ 43 2.3.9 Connection diagram ...................................................................................................... 44 2.3.10 Timing chart ................................................................................................................. 44 2.3.11 Registers setting for transmitter ................................................................................ 45 2.3.12 Setting of serial I/O transmission data .................................................................... 45 2.3.13 Control procedure of transmitter ............................................................................... 46 2.3.14 Connection diagram .................................................................................................... 47 2.3.15 Registers setting for SPI compatible mode ............................................................. 48 2.3.16 Control procedure of SPI compatible mode in slave ............................................. 49 2.3.17 Control procedure of SPI compatible mode in master .......................................... 50 2.4.1 Memory map of registers related to UART ............................................................... 52 2.4.2 Structure of UARTx (x = 1, 2) mode register ........................................................... 53 2.4.3 Structure of UARTx (x = 1, 2) control register ......................................................... 54 2.4.4 Structure of UARTx (x = 1, 2) status register .......................................................... 55 2.4.5 Structure of UARTx (x = 1, 2) RTS control register ................................................ 55 2.4.6 Structure of UARTx (x = 1, 2) baud rate generator ................................................ 56 2.4.7 Structure of UARTx (x = 1, 2) transmit/receive buffer registers 1, 2 ................... 57 2.4.8 Structure of Interrupt request register A .................................................................... 58 2.4.9 Structure of Interrupt request register B .................................................................... 58 2.4.10 Structure of Interrupt control register A ................................................................... 59 2.4.11 Structure of Interrupt control register B ................................................................... 59 2.4.12 UART transfer data format ........................................................................................ 60 2.4.13 Connection diagram .................................................................................................... 66 2.4.14 Timing chart ................................................................................................................. 66 2.4.15 Registers setting for transmitter ................................................................................ 67 2.4.16 Registers setting for receiver (1) .............................................................................. 68 2.4.17 Registers setting for receiver (2) .............................................................................. 69 2.4.18 Control procedure of transmitter ............................................................................... 70 2.4.19 Control procedure of receiver .................................................................................... 71 2.4.20 Connection diagram .................................................................................................... 73 2.4.21 Registers setting related to UART address mode .................................................. 74 2.4.22 Control procedure (1) ................................................................................................. 75 2.4.22 Control procedure (2) ................................................................................................. 76 2.5.1 Memory map of registers related to DMAC .............................................................. 79 2.5.2 Structure of DMAC index and status register ........................................................... 80 2.5.3 Structure of DMAC channel x (x = 0, 1) mode register 1 ...................................... 81 2.5.4 Structure of DMAC channel 0 mode register 2 ........................................................ 83 2.5.5 Structure of DMAC channel 1 mode register 2 ........................................................ 84 2.5.6 Structure of DMAC channel x source registers Low, High ..................................... 85 2.5.7 Structure of DMAC channel x destination registers Low, High .............................. 85 2.5.8 Structure of DMAC channel x transfer count registers Low, High ......................... 86 2.5.9 Structure of Interrupt request register A .................................................................... 87 2.5.10 Structure of Interrupt control register A ................................................................... 87 2.5.11 Transfer mode overview ............................................................................................. 88 2.5.12 Basic operation of registers transferring .................................................................. 89 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 7 of 13 List of figures 7641 Group Fig. 2.5.13 Timing chart for cycle steal transfer caused by hardware-related transfer request ..................................................................................................................................... 93 Fig. 2.5.14 Timing chart for cycle steal transfer caused by software trigger transfer request ..................................................................................................................................... 93 Fig. 2.5.15 Timing chart for burst transfer caused by hardware-related transfer request .... 94 Fig. 2.5.16 Setting of relevant registers (1) ................................................................................ 96 Fig. 2.5.17 Setting of relevant registers (2) ................................................................................ 97 Fig. 2.5.18 Control procedure ........................................................................................................ 98 Fig. 2.7.1 Memory map of registers related to frequency synthesizer .................................. 101 Fig. 2.7.2 Structure of CPU mode register A ........................................................................... 102 Fig. 2.7.3 Structure of Frequency synthesizer control register .............................................. 102 Fig. 2.7.4 Structure of Frequency synthesizer multiply register 1 ......................................... 103 Fig. 2.7.5 Structure of Frequency synthesizer multiply register 2 ......................................... 103 Fig. 2.7.6 Structure of Frequency synthesizer divide register ................................................ 104 Fig. 2.7.7 Block diagram for frequency synthesizer circuit ..................................................... 105 Fig. 2.7.8 Frequency synthesizer multiply register 2 setting example .................................. 105 Fig. 2.7.9 Frequency synthesizer multiply register 1 setting example .................................. 106 Fig. 2.7.10 Frequency synthesizer divide register setting example ....................................... 106 Fig. 2.8.1 Memory map of registers related to master CPU bus interface .......................... 108 Fig. 2.8.2 Structure of Data bus buffer register x (x = 0, 1) ................................................. 109 Fig. 2.8.3 Structure of Data bus buffer status register x (x = 0, 1) ...................................... 109 Fig. 2.8.4 Structure of Data bus buffer control register 0 ...................................................... 110 Fig. 2.8.5 Structure of Data bus buffer control register 1 ...................................................... 110 Fig. 2.8.6 Connection example .................................................................................................... 112 Fig. 2.8.7 Setting of relevant registers ...................................................................................... 114 Fig. 2.8.8 Control procedure ........................................................................................................ 115 Fig. 2.9.1 Memory map of registers related to special count source generator .................. 116 Fig. 2.9.2 Structure of Special count source generator 1 ....................................................... 117 Fig. 2.9.3 Structure of Special count source generator 2 ....................................................... 117 Fig. 2.9.4 Structure of Special count source mode register ................................................... 118 Fig. 2.10.1 Memory map of registers related to external devices connection ..................... 120 Fig. 2.10.2 Structure of CPU mode register A ......................................................................... 121 Fig. 2.10.3 Structure of CPU mode register B ......................................................................... 121 Fig. 2.10.4 Software wait timing example ................................................................................. 123 Fig. 2.10.5 RDY wait timing example ......................................................................................... 124 Fig. 2.10.6 Extended RDY wait (software wait plus RDY input anytime wait) timing example .................................................................................................................................... 125 Fig. 2.10.7 Hold function timing diagram ................................................................................. 126 Fig. 2.10.8 Connection example of memory access up to 256 Kbytes ................................ 127 Fig. 2.10.9 External ROM and RAM example ........................................................................... 128 Fig. 2.10.10 RDY function use example .................................................................................... 129 Fig. 2.10.11 Read cycle (OE access, SRAM) ........................................................................... 130 Fig. 2.10.12 Read cycle (OE access, EPROM) ........................................................................ 130 Fig. 2.10.13 Write cycle (W control, SRAM) ............................................................................. 131 Fig. 2.11.1 RAM backup system ................................................................................................. 134 Fig. 2.12.1 Memory map of registers related to clock generating circuit ............................. 135 Fig. 2.12.2 Structure of CPU mode register A ......................................................................... 136 Fig. 2.12.3 Structure of Clock control register .......................................................................... 136 Fig. 2.12.4 Structure of Frequency synthesizer control register ............................................ 137 Fig. 2.12.5 Structure of Frequency synthesizer multiply register 1 ....................................... 137 Fig. 2.12.6 Structure of Frequency synthesizer multiply register 2 ....................................... 138 Fig. 2.12.7 Structure of Frequency synthesizer divide register .............................................. 138 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 8 of 13 List of figures 7641 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.12.8 Connection diagram .................................................................................................. 141 2.12.9 Status transition diagram during power failure ..................................................... 141 2.12.10 Setting of relevant registers .................................................................................. 142 2.12.11 Control procedure ................................................................................................... 143 2.12.12 Structure of clock counter ...................................................................................... 144 2.12.13 Initial setting of relevant registers ........................................................................ 145 2.12.14 Setting of relevant registers after detecting power failure ................................ 146 2.12.15 Control procedure (1) ............................................................................................. 147 2.12.16 Control procedure (2) ............................................................................................. 148 CHAPTER 3 APPENDIX Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.1.8 3.1.9 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 3.5.7 3.5.8 3.5.9 Circuit for measuring output switching characteristics (1) ...................................... 16 Circuit for measuring output switching characteristics (2) ...................................... 16 Timing diagram (1) ........................................................................................................ 17 Timing diagram (2) ........................................................................................................ 18 Timing diagram (3) ........................................................................................................ 18 Timing diagram (4) ........................................................................................................ 19 Timing diagram (5) ........................................................................................................ 20 Timing diagram (6); Memory expansion and microprocessor modes .................... 21 Timing diagram (7); Memory expansion and microprocessor modes .................... 22 Power source current standard characteristics (Ta = 25 ° C) ................................. 23 CMOS output port P-channel side characteristics (Ta = 25 ° C) ............................ 24 CMOS output port P-channel side characteristics (Ta = 70 ° C) ............................ 24 CMOS output port N-channel side characteristics (Ta = 25 ° C) ........................... 25 CMOS output port N-channel side characteristics (Ta = 70 ° C) ........................... 25 Port P20– P2 7 a t pull-up characteristics (Ta = 25 ° C) .............................................. 26 Port P20– P2 7 a t pull-up characteristics (Ta = 70 ° C) .............................................. 26 Sequence of setting external interrupt active edge ................................................. 27 Circuit example for the proper positions of the peripheral components ............. 33 Passive components near LPF pin ........................................................................... 33 Insulation connector connection ................................................................................ 33 Initialization of processor status register ................................................................... 40 Sequence of PLP instruction execution ..................................................................... 41 Stack memory contents after PHP instruction execution ........................................ 41 Wiring for the RESET pin ............................................................................................ 44 Wiring for clock I/O pins .............................................................................................. 44 Bypass capacitor across the Vss line and the Vcc line .......................................... 45 Wiring for a large current signal line ......................................................................... 46 Wiring for signal lines where potential levels change frequently ........................... 46 VSS pattern on the underside of an oscillator ......................................................... 47 Setup for I/O ports ........................................................................................................ 47 Watchdog timer by software ........................................................................................ 48 Structure of CPU mode register A ............................................................................. 49 Structure of CPU mode register B ............................................................................. 49 Structure of Interrupt request register A .................................................................... 50 Structure of Interrupt request register B .................................................................... 50 Structure of Interrupt request register C ................................................................... 51 Structure of Interrupt control register A ..................................................................... 51 Structure of Interrupt control register B ..................................................................... 52 Structure of Interrupt control register C ..................................................................... 52 Structure of Port Pi ....................................................................................................... 53 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 9 of 13 List of figures 7641 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.5.10 3.5.11 3.5.12 3.5.13 3.5.14 3.5.15 3.5.16 3.5.17 3.5.18 3.5.19 3.5.20 3.5.21 3.5.22 3.5.23 3.5.24 3.5.25 3.5.26 3.5.27 3.5.28 3.5.29 3.5.30 3.5.31 3.5.32 3.5.33 3.5.34 3.5.35 3.5.36 3.5.37 3.5.38 3.5.39 3.5.40 3.5.41 3.5.42 3.5.43 3.5.44 3.5.45 3.5.46 3.5.47 3.5.48 3.5.49 3.5.50 3.5.51 3.5.52 3.5.53 3.5.54 3.5.55 3.5.56 3.5.57 3.5.58 3.5.59 Structure of Port P4, Port P7 .................................................................................... 53 Structure of Port Pi direction register ...................................................................... 54 Structure of Port P4, Port P7 direction registers ................................................... 54 Structure of Port control register .............................................................................. 55 Structure of Interrupt polarity select register .......................................................... 55 Structure of Port P2 pull-up control register ........................................................... 56 Structure of USB control register ............................................................................. 56 Structure of Clock control register ............................................................................ 57 Structure of Timer X ................................................................................................... 57 Structure of Timer Y ................................................................................................... 58 Structure of Timer i .................................................................................................... 58 Structure of Timer X mode register ......................................................................... 59 Structure of Timer Y mode register ......................................................................... 60 Structure of Timer 123 mode register ...................................................................... 61 Structure of Serial I/O shift register ......................................................................... 61 Structure of Serial I/O control register 1 ................................................................. 62 Structure of Serial I/O control register 2 ................................................................. 62 Structure of Special count source generator 1 ....................................................... 63 Structure of Special count source generator 2 ....................................................... 63 Structure of Special count source mode register ................................................... 64 Structure of UARTx (x = 1, 2) mode register ......................................................... 64 Structure of UARTx (x = 1, 2) baud rate generator .............................................. 65 Structure of UARTx (x = 1, 2) status register ........................................................ 65 Structure of UARTx (x = 1, 2) control register ....................................................... 66 Structure of UARTx (x = 1, 2) transmit/receive buffer registers 1, 2 ................. 67 Structure of UARTx (x = 1, 2) RTS control register .............................................. 68 Structure of DMAC index and status register ......................................................... 69 Structure of DMAC channel x (x = 0, 1) mode register 1 .................................... 70 Structure of DMAC channel 0 mode register 2 ...................................................... 71 Structure of DMAC channel 1 mode register 2 ...................................................... 72 Structure of DMAC channel x (x = 0, 1) source registers Low, High ................. 73 Structure of DMAC channel x (x = 0, 1) destination registers Low, High ......... 73 Structure of DMAC channel x (x = 0, 1) transfer count registers Low, High .... 74 Structure of Data bus buffer register x (x = 0, 1) ................................................. 75 Structure of Data bus buffer status register x (x = 0, 1) ..................................... 75 Structure of Data bus buffer control register 0 ...................................................... 76 Structure of Data bus buffer control register 1 ...................................................... 76 Structure of USB address register ........................................................................... 77 Structure of USB power management register ....................................................... 77 Structure of USB interrupt status register 1 ........................................................... 78 Structure of USB interrupt status register 2 ........................................................... 79 Structure of USB interrupt enable register 1 .......................................................... 80 Structure of USB interrupt enable register 2 .......................................................... 80 Structure of USB frame nmber registers Low, High .............................................. 81 Structure of USB endpoint index register ................................................................ 82 Structure of USB endpoint x (x = 0 to 4) IN control register .............................. 83 Structure of USB endpoint x (x = 1 to 4) OUT control register .......................... 84 Structure of USB endpoint x (x = 0 to 4) IN max. packet size register ............ 84 Structure of USB endpoint x (x = 0 to 4) OUT max. packet size register ........ 85 Structure of USB endpoint x (x = 0 to 4) OUT write count registers Low, High ...................................................................................................................................... 86 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 10 of 13 List of figures 7641 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.5.60 3.5.61 3.5.62 3.5.63 3.5.64 3.5.65 3.5.66 3.5.67 Structure Structure Structure Structure Structure Structure Structure Structure of of of of of of of of USB endpoint FIFO mode register ..................................................... 87 USB endpoint x (x = 0 to 4) FIFO register ....................................... 87 Flash memory control register ............................................................. 88 Frequency synthesizer control register .............................................. 89 Frequency synthesizer multiply register 1 ......................................... 89 Frequency synthesizer multiply register 2 ......................................... 90 Frequency synthesizer divide register ................................................ 90 ROM code protect control register ..................................................... 91 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 11 of 13 List of tables 7641 Group List of tables CHAPTER 1 HARDWARE Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 1 Pin description (1) .............................................................................................................. 5 2 Pin description (2) .............................................................................................................. 6 3 Support products ................................................................................................................ 8 4 Push and pop instructions of accumulator or processor status register .................. 10 5 Set and clear instructions of each bit of processor status register .......................... 11 6 List of I/O port function ................................................................................................... 16 7 Interrupt vector addresses and priority ......................................................................... 22 8 Function description of control I/O pins of master CPU bus interface ..................... 64 9 Port functions in memory expansion mode and microprocessor mode ......... 75 10 Summary of M37641F8 (flash memory version) ........................................................ 81 11 List of software commands (CPU rewrite mode) ....................................................... 86 12 Definition of each bit in status register (SRD) ........................................................... 88 13 Description of pin function (Standard Serial I/O Mode) ............................................ 94 14 Software commands (Standard serial I/O mode) ....................................................... 97 15 Definition of each bit of status register (SRD) ........................................................ 104 16 Definition of each bit of status register 1 (SRD1) ................................................... 105 17 Bits of which state might be changed owing to software write ............................. 109 CHAPTER 2 APPLICATION Table 2.1.1 Termination of unused pins ........................................................................................ 9 Table 2.4.1 Setting examples of baud rate generator values and transfer bit rate values ( φ = 1 2 MHz)) ............................................................................................................. 61 Table 2.4.2 Setting examples of SCSG1, SCSG2 and baud rate generator values and transfer bit rate values ( φ = 1 2 MHz)) .................................................................................. 63 Table 2.4.3 Error flags set condition and how to clear error flags ......................................... 65 Table 2.5.1 Address directions and examples of transfer result (1) ....................................... 90 Table 2.5.2 Address directions and examples of transfer result (2) ....................................... 91 Table 2.5.3 Priority to use bus ..................................................................................................... 92 Table 2.8.1 Bus control signal and data bus state-RD/WR separate type ........................... 111 Table 2.8.2 Bus control signal and data bus state-R/W type ................................................ 111 Table 2.12.1 State in Stop mode ................................................................................................ 139 Table 2.12.2 State in Wait mode ................................................................................................ 140 CHAPTER 3 APPENDIX Table 3.1.1 Absolute maximum ratings ........................................................................................ 2 Table 3.1.2 Recommended operating conditions (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) ............................................................................. 3 Table 3.1.3 Electrical characteristics (1) (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted) ............................................................................................. 4 Table 3.1.4 Electrical characteristics (2) (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted) ............................................................................................. 5 Table 3.1.5 Timing requirements (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted) .......................................................................................................... 6 Table 3.1.6 Master CPU bus interface (MBI; RD, WR separate type) (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) ....................................... 7 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 12 of 13 List of tables 7641 Group Table 3.1.7 Master CPU bus interface (MBI; R/W type) (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) ................................................................ 7 Table 3.1.8 Timing requirements and switching characteristics in memory expansion and microprocessor modes (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) ............................................................................................ 8 Table 3.1.9 Recommended operating conditions (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) .............................................................................. 10 Table 3.1.10 Electrical characteristics (1) (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) ................................................................. 11 Table 3.1.11 Electrical characteristics (2) (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) ......................................................................................... 12 Table 3.1.12 Timing requirements (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted) ...................................................................................................... 13 Table 3.1.13 Master CPU bus interface (MBI; RD, WR separate type) (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) ........................................... 14 Table 3.1.14 Master CPU bus interface (MBI; R/W type) (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) ............................................................. 14 Table 3.1.15 Timing requirements and switching characteristics in memory expansion and microprocessor modes (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted) ...................................................................................................... 15 Table 3.3.1 Bits of which state might be changed owing to software write ......................... 35 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 13 of 13 C HAPTER 1 HARDWARE DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION FUNCTIONAL BLOCK PIN DESCRIPTION PART NUMBERING GROUP EXPANSION FUNCTIONAL DESCRIPTION FLASH MEMORY MODE NOTES ON PROGRAMMING USAGE NOTES DATA REQUIRED FOR MASK ORDERS FUNCTIONAL DESCRIPTION SUPPLEMENT HARDWARE 7641 Group DESCRIPTION DESCRIPTION The 7641 group is the 8-bit microcomputer based on the 7600 series core (740 family core compatible) technology. The 7641 group is designed for PC peripheral devices, including the USB, DMAC, Serial I/O, UART, Timer, Master CPU bus interface and so on. q Power source voltage At 24 MHz oscillation frequency, φ = 12 MHz ......... 4.15 to 5.25 V At 24 MHz oscillation frequency, φ = 6 MHz ........... 3.00 to 3.60 V q Program/Erase voltage .................................. VCC = 4.50 V to 5.25 V, or 3.00 V to 3.60 V .................................................................. VPP = 4.50 V to 5.25 V At 24 MHz oscillation frequency, φ = 6 MHz (See Table 10.) q Memory size Flash ROM .................................................................... 32 Kbytes RAM ............................................................................. 2.5 Kbytes qFlash memory mode ....................................................... 3 modes Parallel I/O mode Standard serial I/O mode CPU rewrite mode q Programming method ....................... Programming in unit of byte q Erasing method Batch erasing Block erasing q Program/Erase control by software command qCommand number ................................................... 6 commands q Number of times for programming/erasing ............................. 100 qROM code protection Available in parallel I/O mode and standard serial I/O mode q Operating temperature range (at programming/erasing) .............. ...................................................................... Normal temperature FEATURES (a half of IN FIFO), this condition never occurs. When IN_PKT_RDY = “1” and TX_NOT_EPT = “1”, IN FIFO holds two packets in double buffer mode and one packet in single packet mode. In single packet mode, when the IN_PKT_RDY bit is set to “1” by software, the TX_NOT_EPT flag is set to “1” as well. During double buffer mode, if you want to load two packets sequentially, you must set the IN_PKT_RDY bit to “1” each time a packet is loaded. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 45 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION USB Reception Endpoint 0 to Endpoint 4 have OUT (receive) FIFOs individually. Each endpoint’s FIFO is configured in following way: Endpoint 0: 16-byte Endpoint 1: Mode 0: 800-byte Mode 1: 1024-byte Mode 2: 2048-byte Mode 3: 0-byte Mode 4: 1280-byte Mode 5: 1168-byte Endpoint 2: Mode 0: 32-byte Mode 1: 128-byte Endpoint 3: 16-byte Endpoint 4: 16-byte When Endpoint 1 or Endpoint 2 is used for data receive, the OUT FIFO size can be selected. Endpoint 1 and Endpoint 2 have programmable IN-FIFOs size; 6 modes for Endpoint 1, and 2 modes for Endpoint 2. Each mode can be selected by the USB endpoint FIFO mode selection register (address 005F16). Data transmitted from the host-PC is stored in Endpoint x FIFO (006016 to 006416). Every time the data is stored in the FIFO, the internal OUT FIFO write pointer is increased by 1. When one complete data packet is stored, the OUT_PKT_RDY flag is set to “1” and the number of received data packets is stored in USB Endpoint x OUT write count registers (Low and High). When the AUTO_CLR bit is “1” and the received data is read out from the OUT FIFO, the OUT_PKT_RDY flag is cleared to “0”. When the AUTO_CLR bit is “1”, the OUT_PKT_RDY flag will not be cleared automatically by the FIFO read; it must be cleared by software. (The AUTO-CLR bit function is not applicable in Endpoint 0.) When MAXP size ≤ (a half of OUT FIFO size), the OUT_FIFO can receive 2 packets (double buffer). At this time, the OUT_ FIFO status can be checked by the OUT_PKT_RDY flag. When the FIFO holds two packets and one packet is read from the FIFO, the OUT_PKT_RDY flag is not cleared even if it is set to “0”. (The flag returns from “0” to “1” in one φ cycle after the read-out). During double buffer mode, the USB Endpoint x OUT write count registers (Low and High) holds the number of previously received packets. This count register is updated after reading out one of packets in the OUT FIFO and clearing the OUT_PKT_RDY flag to “0”. TOGGLE Initialization In order to initialize the data toggle sequence bit of the endpoint, in other words, resetting the next data packet to DATA0; set the ISO/TOGGLE_INT bit to “1” and then clear back to “0”. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 46 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION USB Interrupts The USB FCU has two interrupts, USB Function Interrupt and USB SOF (Start Of Frame) Interrupt. qUSB Function Interrupt (USBF-INT) The USBF-INT is usable for the USB data flow control and power management. The USBF-INT request occurs at data transmit/receive completion, overrun/underrun, reset, or receiving suspend/ resume signal. To enable this interrupt, the USB function interrupt enable bit in the interrupt control register A (address 000516) and the respective bit in the USB interrupt enable registers 1 and 2 (addresses 0005416 and 0005516) must be set to “1”. When setting bit 7 in USB interrupt enable register 2 to “1”, the suspend interrupt and the resume interrupt are enabled. Endpoint x (x = 0 to 4) IN interrupt request occurs when the USB Endpoint x IN interrupt status flag (INTST 0, 2, 4, 6, 8) of USB interrupt status registers 1 and 2 (addresses 005216 and 005316) is “1”. The USB Endpoint x IN interrupt status flag is set to “1” when the respective endpoint IN_PKT_RDY bit is “1”. Endpoint x (x = 0 to 4) OUT interrupt request occurs when the USB endpoint x OUT interrupt status flag (INTST3, 5, 7, 9) in USB interrupt status registers 1 and 2 is set to “1”. The USB Endpoint x OUT interrupt status flag is set to “1” when the respective endpoint OUT_PKT_RDY flag is “1”. The overrun/underrun interrupt request occurs when the USB overrun/underrun interrupt status flag (INTST12) in USB interrupt status register 2 is set to “1”. This flag is set to “1” when the FIFO data overruns or underruns in isochronous transfer mode. The USB reset interrupt request occurs when the USB reset interrupt status flag (INTST13) in USB interrupt status register 2 is set to “1”. This flag is set when the SE0 is detected on the D+/D- line for at least 2.5 µs. When this situation happens, all USB internal registers (addresses 005016 to 005F16), except this flag, are initialized to the default state at reset. The USB reset interrupt is always enabled. The suspend/resume interrupt request occurs when either the USB resume signal interrupt status flag (INTST14) or the USB suspend signal interrupt status flag (INTST15) in USB interrupt status register 2 is set to “1”. The bits in both interrupt status registers 1 and 2 can be cleared by writing “1” to each bit. qUSB SOF interrupt The USB SOF interrupt is usable in isochronous transfers. This interrupt request occurs when an SOF packet is received. To enable a USB SOF interrupt, set the USB SOF interrupt enable bit of interrupt control register A to “1”. Suspend/Resume Functions If no bus activity is detected on the D+/D- line for at least 3 ms, the USB suspend signal detect flag (SUSPEND) of the USB power control register (address 005116) and the USB suspend signal interrupt status flag of USB interrupt status register 2 are set to “1” and the suspend interrupt request occurs. The following procedure must be executed after pushing the internal registers (A, X, Y ) to memories during the suspend interrupt process routine. (1) Clear all bits of USB interrupt status register 1 (address 005216) and USB interrupt status register 2 (address 005316) to “0”. (2) Set the USB clock enable bit to “0”. (After disabling the USB clock, do not write to any of the USB internal registers (addresses 005016 to 006416), except for the USB control register (address 001316), clock control register (address 001F16), and frequency synthesizer control register (address 006C16). (3) Set the frequency synthesizer enable bit to “0”. (4) Set the USB line driver current control bit to “1”. (Always keep the USB line driver current control bit set to “0” during USB function operations. When operating at Vcc = 3.3 V, this bit does not need to be set.) (5) Keep total drive current at 500 µA or less. (6) Disable the timer 1 interrupt. (7) Disable the timer 2 interrupt. (Disable all the other external interrupts.) (8) Set the timer 1 interrupt request bit to “0”. (9) Set the timer 2 interrupt request bit to “0”. (10) Set the interrupt disable flag (I) to “0”. (11) Execute the STP instruction. At this point, the MCU will be in stop mode (suspend mode). Before executing the STP instruction, make sure to set the USB function interrupt request bit (bit 0 at address 000216) to “0” and the USB function interrupt enable bit (bit 0 at address 000516) to “1”. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 47 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION The USB suspend detect signal flag goes to “0” when the USB resume signal detect flag (RESUME) is set to “1”. During suspend mode, if the clock operation is started up with a process (remote wake-up) other than the resume interrupt process (for example; reset or timer), make sure to clear the USB suspend detect signal flag to “0” when you set the USB remote wake-up bit to “1”. When the USB FCU is in suspend mode and detects a non-idle signal on the D+/D- line, the USB resume detect flag and the USB resume signal interrupt status flag both go to “1” and a resume interrupt request occurs. At this point, pull the internal registers (A, X, Y) in this interrupt process routine. Take the following procedure in the USB resume interrupt process. (1) Set the USB line driver current control bit to “0”. (When operating at Vcc = 3.3 V, this bit does not need to be set.) (2) Set the frequency synthesizer enable bit to “1” and set a 2 ms to 5 ms wait. (3) Check the frequency synthesizer lock status bit. If “0”, it must be checked again after a 0.1 ms wait. (4) Enable the USB clock. Set the USB resume signal interrupt status flag to “0” after the wake-up sequence process. The USB resume detect flag goes to “0” at the same time. When the clock operation is started up with a remote wake-up, set the USB remote wake-up bit to “1” after the wake-up sequence process. (keep it set to “1” for a minimum of 10 ms and maximum of 15 ms). By doing this, the MCU will send a resume signal to the host CPU and let it know that the suspend state has been released. After that, set the USB remote wake-up bit and the USB suspend detection flag to “0”, because the USB suspend detection flag is not automatically cleared to “0” with a remote wake-up. [USB Control Register] USBC When using the USB function, the USB enable bit must be set to “1”. The USB line driver supply bit must be set to “0” (DC-DC converter is disabled) when operating at Vcc = 3.3V. In this condition, the setting of the USB line driver current control bit has no effect on USB operations. When the USB artificial SOF enable bit is set to “ 1 ” , the MCU judges that a SOF packet is received within 250 ns from a frame starting if an SOF packet is destroyed owing to some cause. b7 b0 0 USB control register (address 001316) USBC Reserved bit (“0” at read/write) USB default state selection bit (USBC1) 0: In default state after power-on/reset 1: In default state after USB reset signal received USB artificial SOF enable bit (USBC2) 0: Artificial SOF disabled 1: Artificial SOF enabled USB line driver current control bit (USBC3) 0: High current mode 1: Low current mode USB line driver supply enable bit (USBC4) (Note 1) 0: Line driver disabled 1: Line driver enabled USB clock enable bit (USBC5) 0: 48 MHz clock to the USB block disabled 1: 48 MHz clock to the USB block enabled USB SOF port select bit (USBC6) 0: SOF output disabled 1: SOF output enabled USB enable bit (USBC7) 0: USB block disabled (Note 2) 1: USB block enabled Notes 1: When using the MCU in Vcc = 3.3 V, set this bit to “0” and disable the built-in DC-DC converter 2: Setting this bit to 0” causes the contents of all USB registers to have the values at reset. Fig. 37 Structure of USB control register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 48 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION [USB Address Register] USBA The USB address register maintains the USB function control unit address assigned by the host computer. When receiving the SET_ADDRESS, keep it in this register. The values of this register are “0” when the device is not yet configured. The values of this register are also set to “0” when the USB block is disabled (bit 7 of USB control register is set to “ 0 ” ). In addition, no matter what value is written to this register, it will have no effect on the set value. b7 b0 0 USB address register (address 005016) USBA Programmable function address (FUNAD0 to 6)) This register maintains the 7-bit USB function control unit address assigned by the host CPU. Reserved bit (“0” at read/write) Fig. 38 Structure of USB address register [USB Power Management Register] USBPM The USB power management register is used for power management in the USB FCU. This register needs to be set only when using the remote wake-up to resume the MCU from suspend mode. b7 b0 00000 USB power management register (address 005116) USBPM USB suspend detection flag (SUSPEND) (Read only) 0: No USB suspend detected 1: USB suspend detected USB resume detection flag (RESUME) (Read only) 0: No USB resume signa detected 1: USB resume signal detected USB remote wake-up bit (WAKEUP) 0: End of remote resume signal 1: Transmitting of remote resume signal (only when SUSPEND = “1”) Reserved bit (“0” at read/write) Fig. 39 Structure of USB power management register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 49 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION [USB Interrupt Status Registers 1 and 2] USBIS1, USBIS2 The USB interrupt status registers are used to indicate the condition that caused a USB function interrupt to be generated. Each status flag and bit can be cleared to “0” by writing “1” to the corresponding bit. Make sure to write to/read from the USB interrupt status register 1 first and then USB interrupt status register 2. When an IN token is received during an isochronous transfer, and the IN FIFO is empty, an underrun error occurs and INTST12 and IN_CSR2 are set to “1”. When an OUT token is received and the OUT FIFO is full, an overrun error occurs and INTST12 and OUT_CSR2 are set to “1”. Underruns and overruns are not detected by the CPU in bulk transfers and normal interrupt transfers, however in this case, the MCU will send a NAK signal to the host CPU. b7 b0 0 USB interrupt status register 1 (address 005216) USBIS1 USB endpoint 0 interrupt status flag (INTST0) 0: Except the following conditions 1: Set at any one of the following conditions: • A packet data of endpoint 0 is successfully received • A packet data of endpoint 0 is successfully sent • DATA_END bit of endpoint 0 is cleared to “0” • FORCE_STALL bit of endpoint 0 is set to “1” • SETUP_END bit of endpoint 0 is set to “1”. Reserved bit (“0” at read/write) USB endpoint 1 IN interrupt status flag (INTST2) 0: Except the following conditions 1: Set at which of the following conditions: • A packet data of endpoint 1 is successfully sent • UNDER_RUN bit of endpoint 1 is set to “1”. USB endpoint 1 OUT interrupt status flag (INTST3) 0: Except the following conditions 1: Set at any one of the following conditions: • A packet data of endpoint 1 is successfully received • OVER_RUN bit of endpoint 1 is set to “1” • FORCE_STALL bit of endpoint 1 is set to “1”. USB endpoint 2 IN interrupt status flag (INTST4) 0: Except the following conditions 1: Set at which of the following conditions: • A packet data of endpoint 2 is successfully sent • UNDER_RUN bit of endpoint 2 is set to “1”. USB endpoint 2 OUT interrupt status flag (INTST5) 0: Except the following conditions 1: Set at any one of the following conditions: • A packet data of endpoint 2 is successfully received • OVER_RUN bit of endpoint 2 is set to “1” • FORCE_STALL bit of endpoint 2 is set to “1”. USB endpoint 3 IN interrupt status flag (INTST6) 0: Except the following conditions 1: Set at which of the following conditions: • A packet data of endpoint 3 is successfully sent • UNDER_RUN bit of endpoint 3 is set to “1”. USB endpoint 3 OUT interrupt status flag (INTST7) 0: Except the following conditions 1: Set at any one of the following conditions: • A packet data of endpoint 3 is successfully received • OVER_RUN bit of endpoint 3 is set to “1” • FORCE_STALL bit of endpoint 3 is set to “1”. Fig. 40 Structure of USB interrupt status register 1 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 50 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION b7 b0 00 USB interrupt status register 2 (address 005316) USBIS2 USB endpoint 4 IN interrupt status flag (INTST8) 0: Except the following conditions 1: Set at which of the following conditions: • A packet data of endpoint 4 is successfully sent • UNDER_RUN bit of endpoint 4 is set to “1”. USB endpoint 4 OUT interrupt status flag (INTST9) 0: Except the following conditions 1: Set at any one of the following conditions: • A packet data of endpoint 4 is successfully received • OVER_RUN bit of endpoint 4 is set to “1” • FORCE_STALL bit of endpoint 4 is set to “1”. Reserved bit (“0” at read/write) USB overrun/underrun interrupt status flag (INTST12) 0: Except the following condition 1: Set at an occurrence of overrun/underrun (for isochronous data transfer) USB reset interrupt status flag (INTST13) 0: Except the following condition 1: Set at receiving of USB reset signal USB resume signal interrupt status flag (INTST14) 0: Except the following condition 1: Set at receiving of resume signal USB suspend signal interrupt status flag (INTST15) 0: Except the following condition 1: Set at receiving of suspend signal Fig. 41 Structure of USB interrupt status register 2 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 51 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION [USB Interrupt Enable Registers 1 and 2] USBIE1, USBIE2 The USB interrupt enable registers are used to enable the USB function interrupt. Upon reset, all USB interrupts except the USB suspend and USB resume interrupts are enabled. b7 b0 0 USB interrupt enable register 1 (address 005416) USBIE1 USB endpoint 0 interrupt enable bit (INTEN0) 0: Disabled 1: Enabled Reserved bit (“0” at read/write) USB endpoint 1 IN interrupt enable bit (INTEN2) 0: Disabled 1: Enabled USB endpoint 1 OUT interrupt enable bit (INTEN3) 0: Disabled 1: Enabled USB endpoint 2 IN interrupt enable bit (INTEN4) 0: Disabled 1: Enabled USB endpoint 2 OUT interrupt enable bit (INTEN5) 0: Disabled 1: Enabled USB endpoint 3 IN interrupt enable bit (INTEN6) 0: Disabled 1: Enabled USB endpoint 3 OUT interrupt enable bit (INTEN7) 0: Disabled 1: Enabled Fig. 42 Structure of USB interrupt enable register 1 b7 b0 01 00 USB interrupt enable register 2 (address 005516) USBIE2 USB endpoint 4 IN interrupt enable bit (INTEN8) 0: Disabled 1: Enabled USB endpoint 4 OUT interrupt enable bit (INTEN9) 0: Disabled 1: Enabled Reserved bit (“0” at read/write) USB overrun/underrun interrupt enable bit (INTEN12) 0: Disabled 1: Enabled Reserved bit (“1” at read/write) Reserved bit (“0” at read/write) USB suspend/resume interrupt enable bit (INTEN15) 0: Disabled 1: Enabled Fig. 43 Structure of USB interrupt enable register 2 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 52 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION [USB Frame Number Registers Low and High ] USBSOFL, USBFOFH These 11-bit registers contain the frame number of the SOF token received from the host computer. These are read-only registers. [USB Endpoint Index Register] USBINDEX This register specifies the accessible endpoint. It serves as an index to endpoint-specific USB Endpoint x IN Control Register, USB Endpoint x OUT Control Register, USB Endpoint x IN Max. Packet Size Register, USB Endpoint x OUT Max. Packet Size Register, USB Endpoint x OUT Write Count Register, and USB FIFO Mode Selection Register (x = 0 to 4). b7 b0 USB frame number register Low (address 005616) USBSOFL Low-order 8 bits of SOF token b7 b0 USB frame number register High (address 005716) USBSOFH High-order 3 bits of SOF token Reserved bit (“0” at read) Fig. 44 Structure of USB frame number registers b7 b0 000 USB endpoint index register (address 005816) USBINDEX Endpoint index bit (EPINDEX) b2b1b0 0 0 0: Endpoint 0 0 0 1: Endpoint 1 0 1 0: Endpoint 2 0 1 1: Endpoint 3 1 0 0: Endpoint 4 1 0 1: Not used 1 1 0: Not used 1 1 1: Not used Reserved bit (“0” at read/write) AUTO_FLUSH bit (AUTO_FL) 0: Auto FIFO flush disabled 1: Auto FIFO flush enabled ISO_UPDATE bit (ISO_UPD) 0: ISO_UPDATE disabled 1: ISO_UPDATE enabled Fig. 45 Structure of USB frame number registers Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 53 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION [USB Endpoint 0 IN Control Register ] IN_CSR This register contains the control and status information of the endpoint 0. This USB FCU sets the OUT_PKT_RDY flag to “1” upon having received a data packet in the OUT FIFO. When reading its one data packet from the OUT FIFO, be sure to set this flag to “0”. After a SETUP token is received, the MCU is in the “decode wait state ” u ntil the OUT_PKT_RDY flag is cleared. If the OUT_PKT_RDY flag is not cleared (indicating that the host request has not been successfully decoded), the USB FCU keep returning a NAK to the host for all IN/OUT tokens. Set the IN_PKT_RDY bit to “ 1 ” a fter the data packet has been written to the IN FIFO. If this bit is set to “1” even though nothing has been written to the IN FIFO, a “0” length data (NULL packet) is sent to the host. The SEND_STALL bit is for sending a STALL to the host if an unsupported request is received by the USB FCU. This bit must be set to “1”. When the OUT_PKT_RDY flag is set to “0” for request reception, the USB FCU transmits a STALL signal to the Host CPU. Perform the following three processes simultaneously: • Set SEND_STALL bit to “1” • Set DATA_END bit to “1” • Set OUT_PKT_RDY flag to “0” by setting SERVICED_OUT _PKT_RDY bit to “1”. Note that if “ 0 ” i s written to the SEND_STALL bit before the CLEAR_FEATURE (endpoint STALL) request has been received, the next STALL will not be generated. The DATA_END bit informs the USB FCU of the completion of the process indicated in the SETUP packet. Set this bit to “1” when the process requested in the SETUP packet is completed. (Control Read Transfer: set this bit after writing all of the requested data to the FIFO; Control Write Transfer: set this bit to “1” after reading all of the requested data from the FIFO.) When this bit is “1”, the host request is ignored and a STALL is returned. After the status phase process is completed, the USB FCU automatically clears it to “0”. b7 b0 USB endpoint 0 IN control register (address 005916) IN_CSR OUT_PKT_RDY flag (IN0CSR0) 0: Except the following condition (Cleared to “0” by writing “1” into SERVICED_OUT_PKT_RDY bit) 1: End of a data packet reception IN_PKT_RDY bit (IN0CSR1) 0: End of a data packet transmission 1: Write “1” at completion of writing a data packet into IN FIFO. SEND_STALL bit (IN0CSR2) 0: Except the following condition 1: Transmitting STALL handshake signal DATA_END bit (IN0CSR3) 0: Except the following condition (Cleared to “0” after completion of status phase) 1: Write “1” at completion of writing or reading the last data packet to/from FIFO. FORCE_STALL flag (IN0CSR4) 0: Except the following condition 1: Protocol error detected SETUP_END flag (IN0CSR5) (Note ) 0: Except the following condition (Cleared to “0” by writing “1” into SERVICED_SETUP_END bit) 1: Control transfer ends before the specific length of data is transferred during the data phase. SERVICED_OUT_PKT_RDY bit (IN0CSR6) Writing “1” to this bit clears OUT_PKT_RDY flag to “0”. SERVICED_SETUP_END bit (IN0CSR7) Writing “1” to this bit clears SETUP_END flag to “0”. Note: If this bit is set to “0”, stop accessing the FIFO to serve the previous setup transaction. Fig. 46 Structure of USB endpoint 0 IN control register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 54 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION [USB Endpoint x (x = 1 to 4) IN Control Register] IN_CSR This register contains the control and status information of the respective IN Endpoints 1 to 4. Set the IN_PKT_RDY bit to “1” after the data packet has been written to the IN FIFO. This bit is cleared to “0” when the data transfer is completed. In a bulk IN transfer, this bit is cleared when an ACK signal is received from the host. If an ACK signal is not received, this bit (and the TX_NOT_EMPTY bit) remains as “1”. This same data packet is sent after the next IN token is received. The FLUSH bit is for flushing the data in the IN FIFO. b7 b0 USB endpoint x IN control register (address 005916) IN_CSR INT_PKT_RDY bit (INXCSR0) 0: End of a data packet transmission (Note 1) 1: Write “1” at completion of writing a data packet into IN FIFO. (Note 3) UNDER_RUN flag (INXCSR1) (In isochronous data transfer) 0: No FIFO underrun (Note 2) 1: FIFO underrun occurred (Note 1) (USB overrun/underrun interrupt status flag is set to “0”.) SEND_STALL bit (INXCSR2) (Note 2) 0: Except the following condition 1: Transmitting STALL handshake signal ISO/TOGGLE_INIT bit (INXCSR3) (Note 2) 0: Except the following condition 1: Initializing to endpoint used for isochronous transfer; Initializing the data toggle sequence bit INTPT bit (INXCSR4) (Note 2) 0: Except the following condition 1: Initializing to endpoint used for interrupt transfer, rate feedback TX_NOT_EPT flag (INXCSR5) (Note 1) 0: Empty in IN FIFO 1: Full in IN FIFO FLUSH bit (INXCSR6) 0: Except the following condition (Note 1) 1: Flush FIFO. (Note 2) AUTO_SET bit (INXCSR7) (Note 2) 0: AUTO_SET disabled 1: AUTO_SET enabled (Note 4) Notes 1: This bit is automatically set to “1” or cleared to “0”. 2: The user must program to “1” or “0”. 3: When AUTO_SET bit is “0”, the user must set to “1”. When AUTO_SET bit is “1”, this bit is automatically set to “1”. 4: To use the AUTO_SET function for an IN transfer when the AUTO_SET bit is set to “1”, set the FIFO to single buffer mode. Fig. 47 Structure of USB endpoint x (x = 1 to 4) IN control register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 55 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION [USB Endpoint x (x = 1 to 4) OUT Control Register] OUT_CSR This register contains the information and status of the respective OUT endpoints 1 to 4. In the endpoint 0, all bits are reserved and cannot be used (they will all be read out as “0”). The USB FCU sets the OUT_PKT_RDY flag to “1” after a data packet has been received into the OUT FIFO. After reading the data packet in the OUT FIFO, clear this flag to “0”. However, if there is still data in the OUT FIFO, the flag cannot be cleared even by writing “0” by software. b7 b0 USB endpoint x OUT control register (address 005A16) OUT_CSR OUT_PKT_RDY flag (OUTXCSR0) 0: Except the following condition (Note 3) 1: End of a data packet reception (Note 2) OVER RUN flag (OUTXCSR1) (In isochronous data transfer) 0: No FIFO overrun (Note 2) 1: FIFO overrun occurred (Note 1) SEND_STALL bit (OUTXCSR2) (Note 2) 0: Except the following condition 1: Transmitting STALL handshake signal ISO/TOGGLE_INIT bit (OUTXCSR3) (Note 2) 0: Except the following condition 1: Initializing to endpoint used for isochronous transfer; Enabling reception of DATA0 and DATA1 as PID (Initializing the toggle) FORCE_STALL flag (OUTXCSR4) 0: Except the following condition (Note 2) 1: Protocol error detected (Note 1) DATA_ERR flag (OUTXCSR5) 0: Except the following condition (Note 2) 1: CRC or bit stuffing error detected in transferring isochronous data (Note 1) FLUSH bit (OUTXCSR6) 0: Except the following condition (Note 1) 1: Flush FIFO. (Note 2) AUTO_CLR bit (OUTXCSR7) (Note 2) 0: AUTO_CLR disabled 1: AUTO_CLR enabled Notes 1: This bit is automatically set to “1” or cleared to “0”. 2: The user must program to “1” or “0”. 3: When AUTO_CLR bit is “0”, the user must clear to “0”. When AUTO_CLR bit is “1”, this bit is automatically cleared to “0”. Fig. 48 Structure of USB endpoint x (x = 1 to 4) OUT control register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 56 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION [USB Endpoint x (x = 0 to 4) IN Max. Packet Size Register] IN_MAXP This register specifies the maximum packet size (MAXP) of an endpoint x IN packet. The value set for endpoint 1 is the number of transmitted bytes divided by 8, and the value set for endpoints 0, 2, 3, and 4 is the actual number of transmitted bytes. The CPU can change these values using the SET_DESCRIPTOR command. The initial value for endpoints 0, 2, 3 and 4 is 8, and the initial value for endpoint 1 is 1. [USB Endpoint x (x = 0 to 4) OUT Max. Packet Size Register] OUT_MAXP This register specifies the maximum packet size (MAXP) of an Endpoint x OUT packet. The value set for endpoint 1 is the number of received bytes divided by 8, and the value set for endpoints 0, 2, 3, and 4 is the actual number of received bytes. The CPU can change these values using the SET_DESCRIPTOR command. The initial value for endpoints 0, 2, 3, and 4 is 8, and the initial value for endpoint 1 is 1. When using the endpoint 0, both USB endpoint x IN max. packet size register (IN _MAXP) and USB endpoint x OUT max. packet size register (OUT_MAXP) are set to the same value. Changing one register ’s value effectively changes the value of the other register as well. b7 b0 USB endpoint x IN max. packet size register (address 005B16) IN_MAXP The maximum packet size (MAXP) of endpoint x IN is contained. MAXP = n for endpoints 0, 2, 3, 4 MAXP = n ✕ 8 for endpoint 1 “n” is a written value into this register. Fig. 49 Structure of USB endpoint x IN max. packet size register b7 b0 USB endpoint x OUT max. packet size register (address 005C16) OUT_MAXP The maximum packet size (MAXP) of endpoint x OUT is contained. MAXP = n for endpoints 0, 2, 3, 4 MAXP = n ✕ 8 for endpoint 1 “n” is a written value into this register. Fig. 50 Structure of USB endpoint x OUT max. packet size register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 57 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION [USB endpoint x (x = 0 to 4) OUT Write Count Registers (Low and High)] WRT_CNTRL, WRT_CNTH These registers contain the number of bytes in the endpoint x OUT FIFO. These are read-only registers. These two registers must be read after the USB FCU has received a packet of data from the host. When reading these registers, the lower byte must be read first, then the higher byte. When the OUT FIF0 is in double buffer mode, the CPU first reads the received number of bytes of the former data packet. The next CPU read can obtain that of the new data packet. b7 b0 USB endpoint x OUT write count register Low (address 005D16) WRT_CNTL Low-order 8 bits of the number of bytes in endpoint x OUT FIFO b7 b0 USB endpoint x OUT write count register High (address 005E16) WRT_CNTH High-order 2 bits of the number of bytes in endpoint x OUT FIFO Not used (“0” at read) Fig. 51 Structure of USB endpoint x (x = 0 to 4) OUT write count registers [USB Endpoint x (x = 0 to 4) FIFO Register] USBFIFOx These registers are the USB IN (transmit) and OUT (receive) FIFO data registers. Write data to the corresponding register, and read data from the corresponding register. When the maximum packet size is equal to or less than half the FIFO size, these registers function in double buffer mode and can hold two packets of data. When the IN_PKT_RDY bit is “0” and the TX_NOT_EMPTY bit is “1”, these bits indicate that one packet of data is stored in the IN FIFO. When the OUT FIFO is in double buffer mode, the OUT_PKT_RDY flag remains as “1” after the first packet of data is read out (it actually goes to “0” and returns to “1” after one φ cycle). b7 b0 USB endpoint x FIFO register (addresses 006016, 006116, 006216, 006316, 006416,) USBFIFOx Endpoint x IN/OUT FIFO Fig. 52 Structure of USB endpoint x (x = 0 to 4) FIFO register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 58 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION [USB Endpoint FIFO Mode Selection Register] USBFIFOMR This register determines IN/OUT FIFO size mode for endpoint 1 or endpoint 2. This register is invalid when using endpoint 0, 3, or 4. b7 b0 0000 USB endpoint FIFO mode register (address 005F16) USBFIFOMR FIFO size selection bit (Note) For endpoint 1 b3b2b1b0 0 0 0: IN 512-byte, OUT 800-byte 0 0 1: IN 1024-byte, OUT 1024-byte X 0 1 0: IN 0-byte, OUT 2048-byte X 0 1 1: IN 2048-byte, OUT 0-byte X 1 0 0: IN 768-byte, OUT 1280-byte X 1 0 1: IN 880-byte, OUT 1168-byte X X For endpoint 2 0 X X X : IN 32-byte, OUT 32-byte 1 X X X : IN 128-byte, OUT 128-byte Reserved bit (“0” at read/write) Note: The value set into “x” is invalid. Fig. 53 Structure of USB endpoint FIFO mode register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 59 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION MASTER CPU BUS INTERFACE The 7641 group internally has a 2-byte bus interface which control signals from the host CPU side can operate (slave mode). This bus interface allows the 7641 group to be directly connected with a R/W type of CPU bus or a RD and WR separated type of CPU bus. Figure 56 shows the block diagram of master CPU bus interface function. The data bus buffer function I/O pins (P52 – P5 7, P6, P72–P74) also function as the normal I/O ports. When the Master CPU Bus Interface Enable bit of Data Bus Buffer Control Register (bit 6 of address 004A16) is “0”, these pins become the normal I/O ports. When it is “1”, these pins become the master CPU bus interface function pins. Additionally, when using the master CPU bus interface function, set port P6 to input mode by setting “0016” into its port direction register (address 001516). The selection of either the single data bus buffer mode, which uses 1 byte: data bus buffer 0 only, or the double data bus buffer mode, which uses 2 bytes: data bus buffer 0 and data bus buffer 1, is performed by the Data Bus Buffer Function Select Bit of Data Bus Buffer Control Register 1 (bit 7 of address 004E16). Port P72 becomes S1 input pin in the double data bus buffer mode. When data is written from the host CPU side, an input buffer full interrupt occurs. When data is read from the host CPU, an output buffer empty interrupt occurs. The 7641 group shares two input buffer full interrupt requests and two output buffer empty interrupt requests as shown in Figure 54, respectively. The 7641 group can also operate the master CPU bus interface connecting with the Built-in DMAC. This could transfer a large amount of data fast. An input signal level of data bus buffer function input pins can be selected between a CMOS level and a TTL level. Set it using the Master CPU Bus Input Level Select Bit of Port Control Register (address 001016) . Input buffer full flag 0 IBF0 Rising edge detection circuit Rising edge detection circuit One-shot pulse generating circuit One-shot pulse generating circuit Input buffer full interrupt request signal IBF Input buffer full flag 1 IBF1 Output buffer full flag 0 OBF0 Output buffer full flag 1 OBF1 OBE0 Rising edge detection circuit Rising edge detection circuit One-shot pulse generating circuit One-shot pulse generating circuit Output buffer empty interrupt request signal OBE OBE1 IBF0 IBF1 IBF Interrupt request is set at this rising edge OBF0 (OBE0) OBF1 (OBE1) OBE Interrupt request is set at this rising edge Fig. 54 Interrupt request circuit of data bus buffer Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 60 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION b7 b0 b7 b0 Data bus buffer status register 0 (address 004916) DBBS0 Output buffer full flag (OBF0) 0: Buffer empty 1: Buffer full Input buffer full flag (IBF0) 0: Buffer empty 1: Buffer full User definable flag (U2) This flag can be defined by user freely. A0 flag (A00) This flag indicates the condition of A0 status when the IBF0 flag is set. User definable flag (U4–U7) This flag can be defined by user freely. 0 Data bus buffer control register 0 (address 004A16) DBBC0 OBF0 output enable bit 0: P52 functions as I/O port. 1: P52 functions as OBF0 output pin. IBF0 output enable bit 0: P53 functions as I/O port. 1: P53 functions as IBF0 output pin. IBF0 interrupt select bit 0: Occurrence due to data write (A0 = “0”) or command write (A0 = “1”) 1: Occurrence due to command write (A0 = “1”) Output buffer 0 empty interrupt disable bit 0: Enabled 1: Disabled Input buffer 0 full interrupt disable bit 0: Enabled 1: Disabled Reserved bit (“0” at read/write) Master CPU bus interface enable bit 0: P54 to P57, P60 to P67 function as I/O ports. 1: P54 to P57, P60 to P67 function as master CPU bus interface function pins. Bus interface type select bit 0: RD, WR separate type bus 1: R/W type bus b7 b0 b7 b0 Data bus buffer status register 1 (address 004D16) DBBS1 Output buffer full flag (OBF1) 0: Buffer empty 1: Buffer full Input buffer full flag (IBF1) 0: Buffer empty 1: Buffer full User definable flag (U2) This flag can be defined by user freely. A0 flag (A01) This flag indicates the condition of A0 status when the IBF1 flag is set. User definable flag (U4–U7) This flag can be defined by user freely. 00 Data bus buffer control register 1 (address 004E16) DBBC1 OBF1 output enable bit 0: P74 functions as I/O port. 1: P74 functions as OBF1 output pin. IBF1 output enable bit 0: P73 functions as port I/O pin. 1: P73 functions as IBF1 output pin. IBF1 interrupt select bit 0: Occurrence due to data write (A0 = “0”) or command write (A0 = “1”) 1: Occurrence due to command write (A0 = “1”) Output buffer 1 empty interrupt disable bit 0: Enabled 1: Disabled Input buffer 1 full interrupt disable bit 0: Enabled 1: Disabled Reserved bit (“0” at read/write) Data bus buffer function select bit 0 : Single data bus buffer mode (P72 functions as I/O port.) 1 : Double data bus buffer mode (P72 functions as S1 input pin.) Fig. 55 Structure of master CPU bus interface related registers Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 61 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION Data bus buffer control register 1 b7 (address 004E16) b6 b5 b4 b3 b2 b1 b0 P74/OBF1 P73/IBF1 P55/A0 P72/S1 P56/R P57/W U7 U6 U5 U4 A01 U2 IBF1 OBF1 P60/DQ0 Output data bus buffer register 1 (address 004C16) P61/DQ1 P62/DQ2 System bus P63/DQ3 Input data bus buffer register 1 (address 004C16) RD DBBSTS1 DBB1 P64/DQ4 RD DBB0 Input data bus buffer register 0 P65/DQ5 (address 004816) WR DBBSTS0 P66/DQ6 Output data bus buffer register 0 (address 004816) U7 P57/W P56/R P54/S0 P55/A0 P53/IBF0 P52/OBF0 U6 U5 U4 A00 U2 IBF0 OBF0 P67/DQ7 Data bus buffer control register 0 b7 (address 004A16) b6 b5 b4 b3 b2 b1 b0 Fig. 56 Master CPU bus interface block diagram Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 62 of 113 Internal data bus WR HARDWARE 7641 Group FUNCTIONAL DESCRIPTION [Data Bus Buffer Status Register 0, 1 (DBBS0, DBBS1)] 004916, 004D16 The data bus buffer status registers 0, 1 consist of eight bits each. Bits 0, 1, and 3 are read-only bits and indicate the status of the data bus buffer. Bits 2, 4, 5, 6, and 7 are user definable flags which can be programed, and can be read/written. The host CPU can only read this register when the A0 pin is set to “H”. •Bit 0: Output buffer full flag OBF0, OBF1 When writing data to the output data bus buffer, this flag is set to “1”. When reading the output data bus buffer from the host CPU, this flag is cleared to “0”. •Bit 1: Input buffer full flag IBF0, IBF1 When writing data from the host CPU to the input data bus buffer, this flag is set to “1”. When reading the input data bus buffer from the slave CPU side, this flag is are cleared to “0”. •Bit 3: A0 flag A00, A01 When writing data from the host CPU to the input data bus buffer, the level of the A0 pin is latched. [Input Data Bus Buffer Registers 0, 1 (DBBIN 0 , DBBIN 1 )] 004816, 004C16 Data on the data bus is latched to DBBIN0 or DBBIN1 by writing request from the host CPU. Data of DBBINs can be read from the Data Bus Buffer Registers (address 0048 16 o r 004C16) on the SFR area. [Output Data Bus Buffer Registers 0, 1 (DBBOUT 0 , DBBOUT1)] 004816, 004C16 When writing data to the Data Bus Buffer Registers (address 004816 or 004C16) on the SFR area, data is set to DBBOUT0 or DBBOUT1. Data of DBBOUTs is output onto the data bus by performing the reading request from the host CPU when the A0 pin is set to “L”. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 63 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION Table 8 Function description of control I/O pins of master CPU bus interface OBF0 output enable bit 1 0 — IBF0 output enable bit 0 1 — OBF1 output enable bit 0 0 — IBF1 output enable bit 0 0 — Input/ Output Pin Name Functions P52/OBF0 P53/IBF0 P54/S0 OBF0 IBF0 S0 Output Output Input Status output signal. OBF0 signal is output. Status output signal. IBF0 signal is output. Chip select input. This is used for selecting the data bus buffer, which is selected at “L” level. Address input. This is used for selecting DBBSTS and DBBOUT when the host CPU reads. This is used for distinguishing command from data when the host CPU writes. This is a timing signal for reading data from the data bus buffer to the host CPU. This is a timing signal for writing data to the data bus buffer by the host CPU. Chip select input. This is used for selecting the data bus buffer, which is selected at “L” level. Status output signal. IBF1 signal is output. Status output signal. OBF1 signal is output. P55/A0 A0 — — — — Input P56/R (E) P57/W (R/W) P72/S1 R (E) W (R/W) S1 — — — — — — — — — — — — Input Input Input P73/IBF1/HLDA P74/OBF1 IBF1 OBF1 0 0 0 0 0 1 1 0 Output Output Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 64 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION COUNT SOURCE GENERATOR The 7641 Group has a built-in special count source generator, SCSG. This generator consists of two 8-bit timers: SCSG1 and SCSG2. The output of the special count source generator can be used as a clock source for the timer X, serial I/O and two UARTs. The SCSG output is Clock SCSGCLK. The frequency is calculated as follows: SCSGCLK = φ ✕ {n1 / (n1+1)} ✕ {1 / (n2+1)} n1: value set to SCSG1 n2: value set to SCSG2 If the SCSG1 Count Stop Bit (SCSGM1) is set to “ 1 ” , or Timer SCSG1 is set to “0”, the SCSG1 count stops. When this happens, the count source for Timer SCSG2 becomes φ. SCSG Operation Timers SCSG1 and SCSG2 are both down count timers. When the count reaches “0”, an underflow occurs at the next count source rising edge and the contents of the corresponding timer latch are loaded to the timer. The division ratio of each SCSG-x timer is given by 1 / (n+1), where “n” is the value set to the SCSG-x timer. The output of Timer SCSG1 is ANDed with the original clock (φ) to make a count source for Timer SCSG2. Data Write Control When the SCSG1 Data Write Control Bit or SCSG2 Data Write Control Bit is set to “0”, and data is written to the SCSG-x timer; the data is written to the corresponding latch and timer at the same time. When that bit is set to “1”, the data is only written to the latch. SCSG1 count stop bit SCSGCLK output control bit SCSG1 Timer Reload Latch φ SCSG1 Timer (8) SCSG1 data write control bit SCSG1 count stop bit SCSG1 count stop bit SCSG2 data write control bit SCSGCLK output control bit SCSG2 Timer Reload Latch SCSG2 Timer (8) SCSGCLK output control bit SCSGCLK Fig. 57 Special count source generator block diagram Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 65 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION b7 b0 0000 Special count source mode register (address 002F16) SCSGM SCSG1 data write control bit 0: Writing data into both Timer latch and Timer simultaneously 1: Writing data into only Timer latch SCSG1 count stop bit 0: Count start 1: Count stop SCSG2 data write control bit 0: Writing data into both Timer latch and Timer simultaneously 1: Writing data into only Timer latch SCSGCLK output control bit 0: SCSGCLK output disabled (SCSG1 and SCSG2 counts stop) 1: SCSGCLK output enabled Reserved bits (“0” at read/write) Fig. 58 Structure of special count source generator mode register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 66 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION FREQUENCY SYNTHESIZER (PLL) The frequency synthesizer generates the 48 MHz clock required by fUSB and fSYN, which are multiples of the external input reference f(XIN). Figure 59 shows the block diagram for the frequency synthesizer circuit. The Frequency Synthesizer Input Bit selects either f(X IN ) or f(XCIN) as an input clock fIN for the frequency synthesizer. The Frequency Synthesizer Multiply Register 2 (FSM2: address 006E16) divides fIN to generate fPIN, where fPIN = fIN / 2(n + 1), n: value set to FSM2. When the value of Frequency Synthesizer Multiply Register 2 is set to 255, the division is not performed and fPIN will equal fIN. fVCO is generated according to the contents of Frequency Synthesizer Multiply Register 1 (FSM1: address 006D16), where fVCO = fPIN ✕ {2(n + 1)}, n: value set to FSM1. Set the value of FSM1 so that the value of fVCO is 48 MHz. fSYN is generated according to the contents of the Frequency Synthesizer Divide Register (FSD: address 006F16), where fSYN = fVCO / 2(m + 1), m: value set to FSD. When the value of the Frequency Synthesizer Divide Register is set to 255, the division is not performed and fSYN becomes invalid. [Frequency Synthesizer Control Register] FSC Setting the Frequency Synthesizer Enable Bit (FSE) to “1” enables the frequency synthesizer. When the Frequency Synthesizer Lock Status Bit (LS) is “1” in the frequency synthesizer enabled, this indicates that fSYN and fVCO have correct frequencies. sNotes Make sure to connect a low-pulse filter to the LPF pin when using the frequency synthesizer. In addition, please refer to “Programming Notes: Frequency Synthesizer ” w hen recovering from a Hardware Reset. fVCO fIN Prescaler fPIN Frequency Multiplier Frequency synthesizer lock status bit Frequency Divider fSYN fUSB FSM2 (address 006E16) FSM1 (address 006D16) FSC (address 006C16) FSD (address 006F16) Data Bus Fig. 59 Frequency synthesizer block diagram Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 67 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION b7 b0 0 00 Frequency synthesizer control register (address 006C16) FSC Frequency synthesizer enable bit (FSE) 0: Disabled 1: Enabled Fix to “00”. Frequency synthesizer input bit (FIN) 0: f(XIN) 1: f(XCIN) Reserved bit (“0” at read/write) LPF current control (CHG1, CHG0) (Note) b6b5 0 0: Not available 0 1: Low current 1 0: Intermediate current (recommended) 1 1: High current Frequency synthesizer lock status bit 0: Unlocked 1: Locked Note: Bits 6 and 5 are set to (bit 6, bit 5) = (1, 1) at reset. When using the frequency synthesizer, we recommend to set to (bit 6, bit 5) = (1, 0) after locking the frequency synthesizer. Fig. 60 Structure of frequency synthesizer control register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 68 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an “L” level for 20 cycles or more of φ. Then the RESET pin is returned to an “H” level, and reset is released. They must be performed when the power source voltages are between 3.00 V and 3.60 V or 4.15 V and 5.25 V. After the reset is completed, the program starts from the address contained in address FFFA 16 ( high-order byte) and address FFFB16 (low-order byte). After oscillation has restarted, the timers 1 and 2 secures waiting time for the internal clock φ oscillation stabilized automatically by setting the timer 1 to “FF16 ” and timer 2 to “01 16”. The internal clock φ retains “H” level until Timer 2’s underflow and it cannot be supplied until the underflow. The pins state during reset are follows: •When CNVss = “H” Ports P0, P1, P33 to P37 : Outputting Pins other than above mentioned ports : Inputting •When CNVss = “L” All pins : Inputting. Poweron RESET VCC Power source voltage 0V Reset input voltage 0V (Note) 0.2VCC Note : Reset release voltage ; Vcc = 3.00 or 4.15 V RESET VCC Power source voltage detection circuit Fig. 61 Reset circuit example φ RESET Internal reset Address ? ? ? ? FFFA FFFB ADH,L Reset address from the vector table. Data ? ? ? ? ADL ADH SYNC XIN: 512 clock cycles Notes: The question marks (?) indicate an undefined state that depends on the previous state. Fig. 62 Reset sequence Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 69 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION Address Register contents (1) (2) (3) (4) (5) (6) (7) (8) (9) CPU mode register A (CPUA) CPU mode register B (CPUB) Interrupt request register A (IREQA) Interrupt request register B (IREQB) Interrupt request register C (IREQC) Interrupt control register A (ICONA) Interrupt control register B (ICONB) Interrupt control register C (ICONC) Address Register contents (48) UART1 status register (U1STS) (49) UART1 control register (U1CON) (50) UART1 RTS control register (U1RTSC) (51) UART2 mode register (U2MOD) (52) UART2 status register (U2STS) (53) UART2 control register (U2CON) (54) UART2 RTS control register (U2RTSC) (55) DMAC index and status register (DMAIS) (56) DMAC channel x mode register 1 (DMAx1) (57) DMAC channel x mode register 2 (DMAx2) (58) DMAC channel x source register Low (DMAxSL) (59) DMAC channel x source register High (DMAxSH) (60) DMAC channel x destination register Low (DMAxDL) (61) DMAC channel x destination register High (DMAxDH) 003216 0 0 0 0 0 0 1 1 003316 0016 000016 0 0 0 0 1 1 0 0 000116 1 0 0 0 0 0 1 1 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001F16 002016 002116 002216 002316 002416 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 FF16 FF16 FF16 FF16 FF16 003616 1 0 0 0 0 0 0 0 003816 0016 003A16 0 0 0 0 0 0 1 1 003B16 0016 003E16 1 0 0 0 0 0 0 0 003F16 004016 004116 004216 004316 004416 004516 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 FF16 Port P0 (P0) (10) Port P0 direction register (P0D) (11) Port P1 (P1) (12) Port P1 direction register (P1D) (13) Port P2 (P2) (14) Port P2 direction register (P2D) (15) Port P3 (P3) (16) Port P3 direction register (P3D) (17) Port control register (PTC) (18) Interrupt polarity select register (IPOL) (19) Port P2 pull-up control register (PUP2) (20) USB control register (USBC) (21) Port P6 (P6) (22) Port P6 direction register (P6D) (23) Port P5 (P5) (24) Port P5 direction register (P5D) (25) Port P4 (P4) (26) Port P4 direction register (P4D) (27) Port P7 (P7) (28) Port P7 direction register (P7D) (29) Port P8 (P8) (30) Port P8 direction register (P8D) (31) Clock control register (CCR) (32) Timer XL (TXL) (33) Timer XH (TXH) (34) Timer YL (TYL) (35) Timer YH (TYH) (36) Timer 1 (T1) (37) Timer 2 (T2) (38) Timer 3 (T3) (39) Timer X mode register (TXM) (40) Timer Y mode register (TYM) (41) Timer 123 mode register (T123M) (42) Serial I/O control register 1 (SIOCON1) (43) Serial I/O control register 2 (SIOCON2) (62) DMAC channel x transfer count register Low (DMAxCL) 004616 (63) DMAC channel x transfer count register High (DMAxCH) 004716 (64) Data bus buffer register 0 (DBB0) (65) Data bus buffer status register 0 (DBBS0) (66) Data bus buffer control register 0 (DBBC0) (67) Data bus buffer register 1 (DBB1) (68) Data bus buffer status register 1 (DBBS1) (69) Data bus buffer control register 1 (DBBC1) (70) USB address register (USBA) 004816 004916 004A16 004C16 004D16 004E16 005016 (71) USB power management register (USBPM) 005116 (72) USB interrupt status register 1 (USBIS1) (73) USB interrupt status register 2 (USBIS2) (74) USB interrupt enable register 1 (USBIE1) (75) USB interrupt enable register 2 (USBIE2) (76) USB frame number register Low (USBSOFL) (77) USB frame number register High (USBSOFH) (78) USB endpoint index register (USBINDEX) 005216 005316 005416 005516 0 0 1 1 0 0 1 1 005616 005716 005816 0016 0016 0016 0016 0016 (79) USB endpoint x IN control register (IN_CSR) 005916 (80) USB endpoint x OUT control register (OUT_CSR) 005A16 (81) USB endpoint x IN max. packet size register (IN_MAXP) 005B16 0 0 0 0 1 0 0 0 (Note 1) (82) USB endpoint x OUT max. packet size register (OUT_MAXP) 005C16 0 0 0 0 1 0 0 0 (Note 1) (83) USB endpoint x OUT write count register Low (WRT_CNTL) 005D16 0016 0016 0016 002516 0 0 0 0 0 0 0 1 002616 002716 002816 002916 FF16 0016 0016 0016 (84) USB endpoint x OUT write count register High (WRT_CNTH) 005E16 (85) USB endpoint FIFO mode register (USBFIFOMR) (86) Flash memory control register (FMCR) (Note 3) 005F16 006A16 0 0 0 0 0 0 0 1 006C16 0 1 1 0 0 0 0 0 006D16 006E16 006F16 FFC916 (PS) (PCH) (PCL) FF16 FF16 FF16 FF16 ✕✕✕✕✕ 1 ✕✕ FFFB16 contents FFFA16 contents (87) Frequency synthesizer control register (FSC) (88) Frequency synthesizer multiply register 1 (FSM1) (89) Frequency synthesizer multiply register 2 (FSM2) (90) Frequency synthesizer divide register (FSM2) (91) ROM code protect control register (ROMCP) (Note 3) 002B16 0 1 0 0 0 0 0 0 002C16 0 0 0 1 1 0 0 0 FF16 FF16 0016 0016 (44) Special count source generator 1 (SCSG1) 002D16 (45) Special count source generator 2 (SCSG2) 002E16 (46) Special count source mode register (SCSGM) 002F16 (47) UART1 mode register (U1MOD) 003016 (92) Processor status register (93) Program counter X : Not fixed Notes 1: When using the endpoint 1, this contents are “0116”. 2: Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. 3: The flash memory control register and the ROM code protect control register exists in the flash memory version only. Fig. 63 Internal status at reset Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 70 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION CLOCK GENERATING CIRCUIT The 7641 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. (An external feed-back resistor may be needed depending on conditions.) However, an external feed-back resistor is needed between XCIN and XCOUT. When using an external clock, input the clocks to the XIN or XCIN pin and leave the XOUT or XCOUT pin open. Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. XCIN Rf XCOUT Rd CCOUT XIN XOUT Rd (Note) CCIN CI N COUT Frequency Control The internal system clock can be selected among f SYN, f(XIN), f(XIN)/2, and f(XCIN). The internal clock φ is half the frequency of internal system clock. (1) fSYN clock This is made by the frequency synthesizer. f(XIN) or f(XCIN) can be selected as its input clock. See also section “FREQUENCY SYNTHESIZER”. Note : Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feedback resistor between XIN and XOUT following the instruction. (2) f(XIN) clock The frequency of internal system clock is the frequency of XIN pin. Fig. 64 Ceramic resonator or quartz-crystal oscillator external circuit (3) f(XIN)/2 clock The frequency of internal system clock is half the frequency of XIN pin. (4) f(XCIN) clock The frequency of internal system clock is the frequency of XCIN pin. XCIN XCOUT Open XIN XOUT Open sNote If you switch the oscillation between XIN - XOUT and XCIN - XCOUT, stabilize both XIN and XCIN oscillations. The sufficient time is required for the XCIN oscillation to stabilize, especially immediately after power on and at returning from the stop mode. External oscillation circuit VCC VSS External oscillation circuit VCC VSS Fig. 65 External clock input circuit Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 71 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION (5) Low power dissipation mode • The low power dissipation operation can be realized by stopping the main clock X IN w hen using f(X CIN) as the internal system clock. To stop the main clock, set the Main Clock (X IN-X OUT) Stop Bit of the CPU mode register A to “1”. • The low power dissipation operation can be realized by disabling the reversed amplifier when inputting external clocks to the XIN pin or XCIN pin. To disable the reversed amplifier, set the XCOUT Oscillation Drive Disable Bit (CCR5) or XOUT Oscillation Drive Disable Bit (CCR6) of the clock control register to “1”. (2) Wait mode If the WIT instruction is executed, the internal clock φ stops at “H” level, but the oscillator does not stop. The internal clock φ restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the internal clock φ is restarted. Set the Interrupt Enable Bit to be used to release the wait mode to enabled (“1”) and the Interrupt Disable Flag (I) to “0”. Oscillation Control (1) Stop mode If the STP instruction is executed, the internal clock φ stops at “H” level, and XIN and XCIN oscillators stop. Then the timer 1 is set to “FF16” and the internal clock φ divided by 8 is automatically selected as its count source. Additionally, the timer 2 is set to “0116” and the timer 1 ’s output is automatically selected as its count source. Set the Timer 1 and Timer 2 Interrupt Enable Bits to disabled (“0”) before executing the STP instruction. When using an external interrupt to release the stop mode, set the Interrupt Enable Bit to be used to enabled (“1”) and the Interrupt Disable Flag (I) to “0”. Oscillator restarts at reset or when an external interrupt including USB resume interrupts is received, but the internal clock φ r emains at “H” until the timer 2 underflows. The internal clock φ is supplied for the first time when the timer 2 underflows. Therefore make sure not to set the Timer 1 Interrupt Request Bit and Timer 2 Interrupt Request Bit to “1” before the STP instruction stops the oscillator. b7 b0 00000 Clock control register (address 001F16) CCR Reserved bits (“0” at read/write) Fix to “0”. XCOUT oscillation drive disable bit (CCR5) 0: XCOUT oscillation drive is enabled. (When XCIN oscillation is enabled.) 1: XCOUT oscillation drive is disabled. XOUT oscillation drive disable bit (CCR6) 0: XOUT oscillation drive is enabled. (When XIN oscillation is enabled.) 1: XOUT oscillation drive is disabled. XIN divider select bit (CCR7) Valid when CPMA6, CPMA7 = “00” 0: f(XIN)/2 is used for the system clock. 1: f(XIN) is used for the system clock. Fig. 66 Structure of clock control register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 72 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION P1HATRSTB P2LATRSTB DQ PIN1 DQ PIN2 DQ PIN1 DQ P2+ RQ S PIN1 DQ T DQ RESET T R TR T R TR RESET P2+ STP instruction P2LATRSTB P2 peripheral P1 peripheral P2 peripheral T Oscillator count-down timer 1 to 2 STP instruction RQ RQ STP instruction DQ T S S P1HATRSTB P1 peripheral RQ WI T instruction PIN2 DQ T P2 out SQ R Internal clock φ Interrupt request Interrupt disable flag l RESET S P1 out S Delay R QB P2+ P2LATRSTB STP instruction DQ T P2 OSCSTP XOSCSTP Main clock (XIN-XOUT) stop bit P1 P1HATRSTB XCOSCSTP XOD Sub-clock (XCIN-XCOUT) stop bit PIN1, PIN2 XCOD Slow memory wait select bit Slow memory wait mode select bit RDY XIN drive select bit External clock select bit f(XIN) f(XCIN) XDOSCSTP XCDOSCSTP Slow memory wait P1+, P2+ LPF XOSCSTP 1/2 LPF XCOSCSTP fEXT Frequency synthesizer input bit fIN fSYN Internal system clock select bit Main clock (XIN-XOUT) stop bit Sub-clock (XCIN-XCOUT) stop bit 1/2 USB 48 MHz clock output Frequency synthesizer Frequency synthesizer LPF enable bit XIN XOUT XCIN XCOUT Fig. 67 Clock generating circuit block diagram Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 73 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION Reset (Note 2) φ = f(XIN/4) (Note 3) XIN clock oscillating, XCIN clock stopped, Frequency synthesizer clock stopped, CPMA = 0C, FSC = 60 φ = f(XIN/4) (Note 3) φ = f(PLL)/2 STOP WAIT FSC0 “0”←→“1” XIN clock oscillating, XCIN clock stopped, Frequency synthesizer clock oscillating, (Note 4) CPMA = 0C, FSC = 41 CPMA6 “0”←→“1” XIN clock oscillating, XCIN clock stopped, Frequency synthesizer clock oscillating, CPMA = 4C, FSC = 41 WAIT CPMA4 “1”←→“0” φ = f(XIN/4) (Note 3) XIN clock oscillating, XCIN clock oscillating, Frequency synthesizer clock stopped, CPMA = 1C, FSC = 60 (Note 2) STOP WAIT FSC0 “0”←→“1” φ = f(XIN/4) (Note 3) XIN clock oscillating, XCIN clock oscillating, Frequency synthesizer clock oscillating, (Note 4) CPMA = 1C, FSC = 41 CPMA6 “0”←→“1” φ = f(PLL)/2 XIN clock oscillating, XCIN clock oscillating, Frequency synthesizer clock oscillating, CPMA = 5C, FSC = 41 WAIT CPMA7 “1”←→“0” φ = f(XCIN/2) XIN clock oscillating, XCIN clock oscillating, Frequency synthesizer clock stopped, CPMA = 9C, FSC = 60 (Note 2) STOP WAIT FSC0 “0”←→“1” φ = f(XCIN/2) XIN clock oscillating, XCIN clock oscillating, Frequency synthesizer clock oscillating, (Note 4) CPMA = 9C, FSC = 41 CPMA6 “0”←→“1” φ = f(PLL)/2 XIN clock oscillating, XCIN clock oscillating, Frequency synthesizer clock oscillating, CPMA = DC, FSC = 41 WAIT CPMA5 “1”←→“0” φ = f(XCIN/2) (Note 5) (Note 2) STOP WAIT XIN clock stopped, XCIN clock oscillating, Frequency synthesizer clock stopped, CPMA = BC, FSC = 68 FSC0 “0”←→“1” φ = f(XCIN/2) XIN clock stopped, XCIN clock oscillating, Frequency synthesizer clock oscillating, (Note 4) CPMA = BC, FSC = 49 CPMA6 “0”←→“1” φ = f(PLL)/2 XIN clock stopped, XCIN clock oscillating, Frequency synthesizer clock oscillating, CPMA = FC, FSC = 49 WAIT Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2 : In Stop mode, though the frequency synthesizer is not automatically disabled, the oscillator which sends clocks to the frequency synthesizer stops. Set the system clock and disable the frequency synthesizer before execution of the STP instruction. 3 : φ = f(XIN)/2 can be also used by setting the XIN divider select bit (CCR7) to “1”. Then this diagram also applies to that case. 4 : The frequency synthesizer’s input can be selected between XIN input and XCIN input regardless of the system clock. This diagram assumes the frequency synthesizer’s input to be the system clock. Enable the oscillator to be used for the frequency synthesizer’s input before enabling the frequency synthesizer. 5 : Select the XCIN input as the frequency synthesizer’s input by setting the frequency synthesizer input bit (FSC3) to “1” before stopping XIN oscillation. Remarks : This diagram assumes that: •Stack page is page 1 •In single-chip mode (Depending on the CPU mode register A) •φ expresses the internal clock. Fig. 68 State transitions of clock Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 74 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION PROCESSOR MODE Single-chip mode, memory expansion mode, and microprocessor mode which is only in the mask ROM version can be selected by using the Processor Mode Bits of CPU mode register A (bits 0 and 1 of address 000016). In the memory expansion mode and microprocessor mode, a memory can be expanded externally via ports P0 to P3. In these modes, ports P0 to P3 lose their I/O port functions and become bus pins. The port direction registers corresponding to those ports become external memory areas. M37641M8 000016 000816 001016 007016 Internal RAM SFR area 000016 000816 001016 007016 SFR area SFR area SFR area Internal RAM Table 9 Port functions in memory expansion mode and microprocessor mode Port Name Port P0 Port P1 Port P2 Port P3 Function Outputs low-order 8 bits of address. Outputs high-order 8 bits of address. Operates as I/O pins for data D7 to D0 (including instruction code). P30 is the RDY input pin. P31 and P32 function only as output pins P33 is the DMAOUT output pin. P34 is the φOUT output pin. P35 is the SYNCOUT output pin. P36 is the WR output pin, and P37 is the RD output pin. P40 is the EDMA pin. 047016 047016 800016 Internal ROM FFFF16 FFFF16 Memory expansion mode Microprocessor mode The shaded areas are external areas. Port P4 (1) Single-chip mode Select this mode by resetting the MCU with CNVSS connected to VSS. M37641F8 000016 SFR area (2) Memory expansion mode Select this mode by setting the Processor Mode Bits (b1, b0) to “01” in software with CNVSS connected to VSS. This mode enables external memory expansion while maintaining the validity of the internal ROM. 000816 001016 007016 Internal RAM SFR area (3) Microprocessor mode Select this mode by resetting the MCU with CNVSS connected to VCC, or by setting the Processor Mode Bits (b1, b0) to “10” in software with CNVSS connected to VSS. In the microprocessor mode, the internal ROM is no longer valid and an external memory must be used. Do not set this mode in the flash memory version. 0A7016 100016 Reserved area 800016 Internal ROM FFFF16 Memory expansion mode The shaded areas are external areas. Fig. 69 Memory maps in processor modes other than singlechip mode Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 75 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION b7 b0 1 CPU mode register A (address 000016) CPMA Processor mode bits b1b0 0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Microprocessor mode (Note 1) 1 1: Not available Stack page select bit 0: Page 0 1: Page 1 Fix to “1”. Sub-clock (XCIN-XCOUT) control bit 0: Stopped 1: Oscillating Main clock (XIN-XOUT) control bit 0: Oscillating 1: Stopped Internal system clock select bit (Note 2) 0: External clock (XIN-XOUT or XCIN-XCOUT) 1: fSYN External clock select bit 0: XIN-XOUT 1: XCIN-XCOUT Notes 1: This is not available in the flash memory version. 2: When (CPMA 6, 7) = (0, 0), the internal system clock can be selected between f(XIN) or f(XIN)/2 by CCR7. The internal clock φ is the internal system clock divided by 2. Fig. 70 Structure of CPU mode register A b7 b0 10 CPU mode register B (address 000116) CPMB Slow memory wait select bits b1b0 0 0: No wait 0 1: One-time wait 1 0: Two-time wait 1 1: Three-time wait Slow memory wait mode select bits b3b2 0 0: Software wait 0 1: Not available 1 0: RDY wait 1 1: Software wait plus RDY input anytime wait Expanded data memory access bit 0: EDMA output disabled 1: EDMA output enabled HOLD function enable bit 0: HOLD function disabled 1: HOLD function enabled Resereved bit (“0” at read/write) Fix to “1”. Fig. 71 Structure of CPU mode register B Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 76 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION Slow Memory Wait The 7641 Group is equipped with the slow memory wait function (Software wait, RDY wait, and Extended RDY wait: software wait plus RDY input anytime wait) for easier interfacing with external devices that have long access times. The slow memory wait function can be enabled in the memory expansion mode and microprocessor mode. The appropriate wait mode is selected by setting bits 0 to 3 of CPU mode register B (address 000116). This function can extend the read cycle or write cycle only for access to an external memory. However, this wait function cannot be enabled for access to addresses 000816 to 000F16. (2) RDY wait RDY Wait is selected by setting “ 10 ” t o the Slow Memory Wait Mode Select Bits of CPU mode register B (address 000116). When a fixed time of “L” is input to the RDY pin at the beginning of a read/write cycle (before φ cycle falls), the MCU goes to the RDY state. The read/write cycle can then be extended by one to three φ cycles. The number of φ cycles to be added can be selected by the Slow Memory Wait Bits. (3) Software wait + Extended RDY wait Extended RDY Wait is selected by setting “ 11 ” t o the Slow Memory Wait Mode Select Bits of CPU mode register B (address 000116). The read/write cycle can be extended when a fixed time of “L” is input to the RDY pin at the beginning of a read/write cycle (before φ cycle falls). The RDY pin state is checked continually at each fall of φ cycle until the RDY pin goes to “H”. When “H” is input to the RDY pin, the wait is released within 1, 2, or 3 φ cycles (as selected with the Slow Memory Wait Bits). (1) Software wait The software wait is selected by setting “00” to the Slow Memory Wait Mode Select Bits of CPU mode register B (address 000116). Read/write cycles (“L” width of RD pin/WR pin) can be extended by one to three φ cycles. The number of cycles to be extended can be selected with the Slow Memory Wait Select Bits. When the software wait function is selected, the RDY pin status becomes invalid. X IN φ OUT ADOUT RD WR No wait CPMB = 0016 1-cycle software wait CPMB = 0116 2-cycle software wait CPMB = 0216 3-cycle software wait CPMB = 0316 Note: This diagram assumes φ = XIN/2. Fig. 72 Software wait timing diagram XIN φ OUT ADOUT RD WR RDY No wait CPMB = 0816 1-cycle RDY wait CPMB = 0916 2-cycle RDY wait CPMB = 0A16 3-cycle RDY wait CPMB = 0B16 tsu tsu tsu tsu tsu tsu Note: This diagram assumes φ = XIN/2. Fig. 73 RDY wait timing diagram Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 77 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION XIN φOUT ADOUT RD WR tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu RDY No wait CPMB = 0C16 1-cycle extended RDY wait CPMB = 0D16 2-cycle extended RDY wait CPMB = 0E16 XIN φOUT ADOUT RD WR tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu RDY 2-cycle extended RDY wait CPMB = 0E16 3-cycle extended RDY wait CPMB = 0F16 Note: This diagram assumes φ = XIN/2. Fig. 74 Extended RDY wait (software wait plus RDY input anytime wait) timing diagram Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 78 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION HOLD Function The HOLD function is used for systems that consist of external circuits that access MCU buses without use of the CPU (Central Processing Unit). The HOLD function is used to generate the timing in which the MCU will relinquish the bus from the CPU to the external circuits. To use the HOLD function, set the HOLD function Enable Bit of CPU mode register B (address 000116) to “1”. This function can be used with both the HOLD pin and the HLDA pin. The HOLD signal is a signal from an external circuit requesting the MCU to relinquish use of the bus. When “L” level is input, the MCU goes to the HOLD state and remains so while the pin is at “L”. The oscillator does not stop oscillating during the HOLD state, therefore allowing the internal peripheral functions to operate during this time. When the MCU relinquishes use of the bus, “L” level is output from the HLDA pin. The MCU makes ports P0 and P1 (address buses) and port P2 (data bus) tri-state outputs and holds port P37 (RD pin) and port P36 (WR pin) “H” level. Port P34 (φ OUT pin) continues to oscillate. This function is not valid when the MCU is using the IBF1 function with the HLDA pin. Expanded Data Memory Access In Expanded Data Memory Access Mode, the MCU can access a data area larger than 64 Kbytes with the LDA ($zz), Y (indirect Y) instruction and the STA ($zz), Y (indirect Y) instruction. To use this mode, set the Expanded Data Memory Access Bit of CPU mode register B (address 000116) to “1”. In this case, port P40 (EDMA pin) goes “L” level during the read/write cycle of the LDA or STA instruction. The determination of which bank to access is done by using an I/ O port to represent expanded addresses exceeding address bus AB15. For example, when accessing 4 banks, use two I/O ports to represent address buses AB16 and AB17. XIN φ OUT RD, W R ADDROUT DATAIN/OUT tsu(HOLD-φ) HOLD HLDA td(φ-HLDAL) td(φ-HLDAH) th(φ-HOLD) Note: This diagram assumes φ = XIN/2. Fig. 75 Hold function timing diagram Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 79 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION φ SYNCOUT RD WR Address Data EDMA PC PC +1 Op code BAL, 00 BAL BAL+1, 00 ADL + Y, ADH ADL + Y, ADH + C PC + 2 Next Op code ADL ADH Invalid Data Fig. 76 STA ($ zz), Y instruction sequence when EDMA enabled φ SYNCOUT RD WR Address Data EDMA PC PC +1 Op code BAL, 00 BAL BAL+1, 00 ADL + Y, ADH ADL + Y, ADH + C PC + 2 Next Op code ADL ADH Invalid Data Fig. 77 LDA ($ zz), Y instruction sequence when EDMA enabled and T flag = “0” φ SYNCOUT RD WR Address Data EDMA Fig. 78 LDA ($ zz), Y instruction sequence when EDMA enabled and T flag = “1” PC PC +1 Op code BAL, 00 BAL BAL+1, 00 ADL + Y, ADH ADL + Y, ADH + C X, 00 Invalid PC + 2 Data Next Op code ADL ADH Invalid Data Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 80 of 113 HARDWARE 7641 Group FLASH MEMORY MODE FLASH MEMORY MODE The M37641F8FP/HP (flash memory version) has an internal new DINOR (DIvided bit line NOR) flash memory that can be rewritten with a single power source when VCC is 5 V, and 2 power sources when VPP is 5 V and VCC is 3.3 V in the CPU rewrite and standard serial I/O modes. For this flash memory, three flash memory modes are available in which to read, program, and erase: the parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and the CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). Summary Table 10 lists the summary of the M37641F8 (flash memory version). This flash memory version has some blocks on the flash memory as shown in Figure 79 and each block can be erased. The flash memory is divided into User ROM area and Boot ROM area. In addition to the ordinary User ROM area to store the MCU operation control program, the flash memory has a Boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user ’s application system. This Boot ROM area can be rewritten in only parallel I/O mode. Table 10 Summary of M37641F8 (flash memory version) Item Power source voltage (For Program/Erase) VPP voltage (For Program/Erase) Flash memory mode Specifications Vcc = 3.00 – 3.60 V, 4.50 – 5.25 V (f(XIN) = 24 MHz, φ = 6 MHz) (Note 1) VPP = 4.50 – 5.25 V 3 modes; Flash memory can be manipulated as follows: (1) CPU rewrite mode: Manipulated by the Central Processing Unit (CPU) (2) Parallel I/O mode: Manipulated using an external programmer (Note 2) (3) Standard serial I/O mode: Manipulated using an external programmer (Note 2). Erase block division User ROM area Boot ROM area See Figure 79. 1 block (4 Kbytes) (Note 3) Byte program Batch erasing/Block erasing Program/Erase control by software command 6 commands 100 times Available in parallel I/O mode and standard serial I/O mode Program method Erase method Program/Erase control method Number of commands Number of program/Erase times ROM code protection Notes 1: After programming/erasing at Vcc = 3.0 to 3.6 V, the MCU can operate only at Vcc = 3.0 to 3.6 V. After programming/erasing at Vcc = 4.5 to 5.25 V or programming/erasing with the exclusive external equipment flash programmer, the MCU can operate at both Vcc = 3.0 to 3.6 V and 4.15 to 5.25 V. 2: In the parallel I/O mode or the standard serial I/O mode, use the exclusive external equipment flash programmer which supports the 7641 Group (flash memory version). 3: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be rewritten in only parallel I/O mode. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 81 of 113 HARDWARE 7641 Group FLASH MEMORY MODE (1) CPU Rewrite Mode In CPU rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the User ROM area shown in Figure 79 can be rewritten; the Boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the User ROM area and each block area. The control program for CPU rewrite mode can be stored in either User ROM or Boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to internal RAM area to be executed before it can be executed. Microcomputer Mode and Boot Mode The control program for CPU rewrite mode must be written into the User ROM or Boot ROM area in parallel I/O mode beforehand. (If the control program is written into the Boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 79 for details about the Boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNV SS pin low. In this case, the CPU starts operating using the control program in the User ROM area. When the microcomputer is reset by pulling the P36 (CE) pin high, the P81 (SCLK) pin high, the CNVSS pin high, the CPU starts operating using the control program in the Boot ROM area. This mode is called the “Boot” mode. Block Address Block addresses refer to the maximum address of each block. These addresses are used in the block erase command. Parallel I/O mode User ROM area 800016 Block 2 : 16 Kbytes C00016 E00016 FFFF16 Block 1 : 8 Kbytes Block 0 : 8 Kbytes BSEL = “L” F00016 FFFF16 Boot ROM area 4 Kbytes BSEL = “H” CPU rewrite mode, standard serial I/O mode User ROM area 800016 Block 2 : 16 Kbytes C00016 E00016 FFFF16 Block 1 : 8 Kbytes Block 0 : 8 Kbytes F00016 FFFF16 Boot ROM area 4 Kbytes User area / Boot area select bit = “0” User area / Boot area select bit = “1” Notes 1: The Boot ROM area can be rewritten in only parallel I/O mode. (Access to any other areas is inhibited.) 2: To specify a block, use the maximum address in the block. Fig. 79 Block diagram of built-in flash memory Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 82 of 113 HARDWARE 7641 Group FLASH MEMORY MODE Outline Performance (CPU Rewrite Mode) CPU rewrite mode is usable in the single-chip, memory expansion or Boot mode. The only User ROM area can be rewritten in CPU rewrite mode. In CPU rewrite mode, the CPU erases, programs and reads the internal flash memory by executing software commands. This rewrite control program must be transferred to a memory such as the internal RAM before it can be executed. The MCU enters CPU rewrite mode by applying 4.50 V to 5.25 V to the CNVSS pin and setting “1” to the CPU Rewrite Mode Select Bit (bit 1 of address 006A16). Software commands are accepted once the mode is entered. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Figure 80 shows the flash memory control register. Bit 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase operations, it is “0” (busy). Otherwise, it is “1” (ready). Bit 1 is the CPU Rewrite Mode Select Bit. When this bit is set to “1”, the MCU enters CPU rewrite mode. Software commands are accepted once the mode is entered. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly. Therefore, use the control program in a memory other than internal flash memory for write to bit 1. To set this bit to “ 1 ” , it is necessary to write “0” and then write “1” in succession. The bit can be set to “0” by only writing “0”. Bit 2 is the CPU Rewrite Mode Entry Flag. This flag indicates “1” in CPU rewrite mode, so that reading this flag can check whether CPU rewrite mode has been entered or not. Bit 3 is the flash memory reset bit used to reset the control circuit of internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU Rewrite Mode Select Bit is “1”, setting “1” for this bit resets the control circuit. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession. To release the reset, it is necessary to set this bit to “0”. Bit 4 is the User Area/Boot Area Select Bit. When this bit is set to “1”, Boot ROM area is accessed, and CPU rewrite mode in Boot ROM area is available. In Boot mode, this bit is set to “1” automatically. Reprogramming of this bit must be in a memory other than internal flash memory. Figure 81 shows a flowchart for setting/releasing CPU rewrite mode. b7 b0 Flash memory control register (address 006A16) FMCR RY/BY status flag 0: Busy (being programmed or erased) 1: Ready CPU rewrite mode select bit (Note 2) 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) CPU rewrite mode entry flag 0: Normal mode 1: CPU rewrite mode Flash memory reset bit (Note 3) 0: Normal operation 1: Reset User ROM area / Boot ROM area select bit (Note 4) 0: User ROM area accessed 1: Boot ROM area accessed Reserved bits (Indefinite at read/ “0” at write) Notes 1: The contents of flash memory control register are “XXX00001” just after reset release. 2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. If it is not this procedure, this bit will not be set to ”1”. Additionally, it is required to ensure that no interrupt will be generated during that interval. Use the control program in the area except the built-in flash memory for write to this bit. 3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently after setting bit 3 to “1”. 4: Use the control program in the area except the built-in flash memory for write to this bit. Fig. 80 Structure of flash memory control register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 83 of 113 HARDWARE 7641 Group FLASH MEMORY MODE Start Single-chip mode, Memory expansion mode or Boot mode Set CPU mode registers A, B (Note 2) Transfer CPU rewrite mode control program to memory other than internal flash memory Jump to control program transferred in memory other than internal flash memory (Subsequent operations are executed by control program in this memory) Setting Set CPU rewrite mode select bit to “1” (by writing “0” and then “1” in succession) Check CPU rewrite mode entry flag Using software command execute erase, program, or other operation Execute read array command or reset flash memory by setting flash memory reset bit (by writing “1” and then “0” in succession) (Note 3) Released Write “0” to CPU rewrite mode select bit End Notes 1: When starting the MCU in the single-chip mode or memory expansion mode, supply 4.5 V to 5.25 V to the CNVss pin until checking the CPU rewrite mode entry flag. 2: Set the main clock as follows depending on the XIN divider select bit of clock control register (bit 7 of address 001F16): When XIN divider select bit = “0” (φ = f(XIN)/4), the main clock is 24 MHz or less When XIN divider select bit = “1” (φ = f(XIN)/2), the main clock is 12 MHz or less. 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute the read array command or reset the flash memory. Fig. 81 CPU rewrite mode set/release flowchart Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 84 of 113 HARDWARE 7641 Group FLASH MEMORY MODE Notes on CPU Rewrite Mode The below notes applies when rewriting the flash memory in CPU rewrite mode. qOperation speed During CPU rewrite mode, set the internal clock φ to 6 MHz or less using the XIN Divider Select Bit (bit 7 of address 001F16). qInstructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during CPU rewrite mode . qInterrupts inhibited against use The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. qReset Reset is always valid. When CNVSS is “H” at reset release, the program starts from the address stored in addresses FFFA16 and FFFB16 of the boot ROM area in order that CPU may start in boot mode. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 85 of 113 HARDWARE 7641 Group FLASH MEMORY MODE Software Commands (CPU Rewrite Mode) Table 11 lists the software commands. After setting the CPU Rewrite Mode Select Bit of the flash memory control register to “1”, execute a software command to specify an erase or program operation. Each software command is explained below. qRead Array Command (FF16) The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the contents of the specified address are read out at the data bus (DB0 to DB7). The read array mode is retained intact until another command is written. qRead Status Register Command (7016) The read status register mode is entered by writing the command code “7016” in the first bus cycle. The contents of the status register are read out at the data bus (DB0 t o DB 7) by a read in the second bus cycle. The status register is explained in the next section. qClear Status Register Command (5016) This command is used to clear the bits SR4 and SR5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code “5016” in the first bus cycle. qProgram Command (4016) Program operation starts when the command code “4016” is written in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and verification) will start. Whether the write operation is completed can be confirmed by _____ reading the status register or the RY/BY Status Flag of the flash memory control register. When the program starts, the read status register mode is entered automatically and the contents of the status register is read at the data bus (DB 0 t o DB 7 ). The status register bit 7 (SR7) is set to “0” at the same time the write operation starts and is returned to “ 1 ” u pon completion of the write operation. In this case, the read status register mode remains active until the next command is written. ____ The RY/BY Status Flag is “0” (busy) during write operation and “1” (ready) when the write operation is completed as is the status register bit 7. At program end, program results can be checked by reading bit 4 (SR4) of the status register. Start Write 4016 Write Write address Write data Status register read SR7 = 1 ? or RY/BY = 1 ? YES NO S R4 = 0 ? YES Program completed NO Program error Fig. 82 Program flowchart Table 11 List of software commands (CPU rewrite mode) Command Read array Read status register Clear status register Program Erase all blocks Block erase Cycle number 1 2 1 2 2 2 Mode Write Write Write Write Write Write First bus cycle Data Address (DB0 to DB7) X (Note 4) Second bus cycle Data Mode Address (DB0 to DB7) FF16 7016 5016 4016 2016 2016 Write Write Write BA WA (Note 2) X (Note 3) X X X X X Read X SRD (Note 1) WD (Note 2) 2016 D016 Notes 1: SRD = Status Register Data 2: WA = Write Address, WD = Write Data 3: BA = Block Address to be erased (Input the maximum address of each block.) 4: X denotes a given address in the User ROM area . Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 86 of 113 HARDWARE 7641 Group FLASH MEMORY MODE qErase All Blocks Command (2016/2016) By writing the command code “2016” in the first bus cycle and the confirmation command code “2016” in the second bus cycle that follows, the operation of erase all blocks (erase and erase verify) starts. Whether the erase all blocks command is terminated can be con____ firmed by reading the status register or the RY/BY Status Flag of flash memory control register. When the erase all blocks operation starts, the read status register mode is entered automatically and the contents of the status register can be read out at the data bus (DB0 to DB 7). The status register bit 7 (SR7) is set to “0” at the same time the erase operation starts and is returned to “1” upon completion of the erase operation. In this case, the read status register mode remains active until another command is written. ____ The RY/BY Status Flag is “0” during erase operation and “1” when the erase operation is completed as is the status register bit 7 (SR7). After the erase all blocks end, erase results can be checked by reading bit 5 (SRS) of the status register. For details, refer to the section where the status register is detailed. qBlock Erase Command (2016/D016) By writing the command code “2016” in the first bus cycle and the confirmation command code “D016” and the blobk address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. Whether the block erase operation is completed can be confirmed ____ by reading the status register or the RY/BY Status Flag of flash memory control register. At the same time the block erase operation starts, the read status register mode is automatically entered, so that the contents of the status register can be read out. The status register bit 7 (SR7) is set to “0” at the same time the block erase operation starts and is returned to “1” upon completion of the block erase operation. In this case, the read status register mode remains active until the read array command (FF16) is written. ____ The RY/BY Status Flag is “0” during block erase operation and “1” when the block erase operation is completed as is the status register bit 7. After the block erase ends, erase results can be checked by reading bit 5 (SRS) of the status register. For details, refer to the section where the status register is detailed. Start Write 2016 Write 2016/D016 Block address 2016:Erase all blocks command D016:Block erase command Status register read SR7 = 1 ? or RY/BY = 1 ? NO YES NO SR5 = 0 ? Erase error YES Erase completed Fig. 83 Erase flowchart Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 87 of 113 HARDWARE 7641 Group FLASH MEMORY MODE Status Register (SRD) The status register shows the operating status of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways: (1) By reading an arbitrary address from the User ROM area after writing the read status register command (7016) (2) By reading an arbitrary address from the User ROM area in the period from when the program starts or erase operation starts to when the read array command (FF16) is input. Also, the status register can be cleared by writing the clear status register command (5016). After reset, the status register is set to “8016”. Table 12 shows the status register. Each bit in this register is explained below. •Sequencer status (SR7) The sequencer status indicates the operating status of the flash memory. This bit is set to “0” (busy) during write or erase operation and is set to “1” when these operations ends. After power-on, the sequencer status is set to “1” (ready). •Erase status (SR5) The erase status indicates the operating status of erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”. •Program status (SR4) The program status indicates the operating status of write operation. When a write error occurs, it is set to “1”. The program status is set to “0” when it is cleared. If “ 1 ” i s written for any of the SR5 and SR4 bits, the program, erase all blocks, and block erase commands are not accepted. Before executing these commands, execute the clear status register command (5016) and clear the status register. Also, if any commands are not correct, both SR5 and SR4 are set to “1”. Table 12 Definition of each bit in status register (SRD) Symbol SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved Definition “1” Ready Terminated in error Terminated in error - “0” Busy Terminated normally Terminated normally - Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 88 of 113 HARDWARE 7641 Group FLASH MEMORY MODE Full Status Check By performing full status check, it is possible to know the execution results of erase and program operations. Figure 84 shows a full status check flowchart and the action to be taken when each error occurs. Read status register SR4 = 1 and SR5 = 1 ? NO SR5 = 0 ? YES SR4 = 0 ? YES YES Command sequence error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should an erase error occur, the block in error cannot be used. NO Erase error NO Program error Should a program error occur, the block in error cannot be used. End (erase, program) Note: When one of SR5 and SR4 is set to “1”, none of the read aray, the program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands. Fig. 84 Full status check flowchart and remedial procedure for errors Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 89 of 113 HARDWARE 7641 Group FLASH MEMORY MODE Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of internal flash memory from being read out or rewritten easily, this MCU incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode. qROM Code Protect Function (in Pararell I/O Mode) The ROM code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the ROM code protect control (address FFC916 ) in parallel I/O mode. Figure 85 shows the ROM code protect control (address FFC916). (This address exists in the User ROM area.) If one or both of the pair of ROM Code Protect Bits is set to “0”, the ROM code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. The ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default. If both of the two ROM Code Protect Reset Bits are set to “00”, the ROM code protect is turned off, so that the contents of internal flash memory can be read out or modified. Once the ROM code protect is turned on, the contents of the ROM Code Protect Reset Bits cannot be modified in parallel I/O mode. Use the serial I/O or CPU rewrite mode to rewrite the contents of the ROM Code Protect Reset Bits. b7 b0 1 1 ROM code protect control (address FFC916) (Note 1) ROMCP Reserved bits (“1” at read/write) ROM code protect level 2 set bits (ROMCP2) (Notes 2, 3) b3b2 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled ROM code protect reset bits (Note 4) b5b4 0 0: Protect removed 0 1: Protect set bits effective 1 0: Protect set bits effective 1 1: Protect set bits effective ROM code protect level 1 set bits (ROMCP1) (Note 2) b7b6 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled Notes 1: This area is on the ROM in the mask ROM version. 2: When ROM code protect is turned on, the internal flash memory is protected against readout or modification in parallel I/O mode. 3: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc. also is inhibited. 4: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, since these bits cannot be modified in parallel I/O mode, they need to be rewritten in standard serial I/O mode or CPU rewrite mode. Fig. 85 Structure of ROM code protect control Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 90 of 113 HARDWARE 7641 Group FLASH MEMORY MODE ID Code Check Function (in Standard serial I/O mode) Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the programmer is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID code consists of 8-bit data, and its areas are FFC216 to FFC816. Write a program which has had the ID code preset at these addresses to the flash memory. Address FFC216 FFC316 FFC416 FFC516 FFC616 FFC716 FFC816 FFC916 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ROM code protect control Interrupt vector area Fig. 86 ID code store addresses Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 91 of 113 HARDWARE 7641 Group FLASH MEMORY MODE (2) Parallel I/O Mode Parallel I/O mode is the mode which parallel output and input software command, address, and data required for the operations (read, program, erase, etc.) to a built-in flash memory. Use the exclusive external equipment flash programmer which supports the 7641 Group (flash memory version). Refer to each programmer maker ’s handling manual for the details of the usage. User ROM and Boot ROM Areas In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 79 can be rewritten. Both areas of flash memory can be operated on in the same way. Program and block erase operations can be performed in the user ROM area. The user ROM area and its block is shown in Figure 79. The boot ROM area is 4 Kbytes in size. It is located at addresses F00016 through FFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the Boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory. Therefore, using the device in standard serial I/O mode, you do not need to write to the boot ROM area. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 92 of 113 HARDWARE 7641 Group FLASH MEMORY MODE (3) Standard serial I/O Mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. This mode requires the exclusive external equipment (flash programmer). The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU rewrite mode), rewrite data input and so forth. The standard serial I/O mode is started by connecting “H” to the P36 (CE) pin and “H” to the P81 (SCLK) pin and “H” to the CNVSS pin (apply 4.5 V to 5.25 V to Vpp from an external source), and releasing the reset operation. (In the ordinary microcomputer mode, set CNVss pin to “L” level.) This control program is written in the Boot ROM area when the product is shipped from Mitsubishi. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the Boot ROM area is rewritten in parallel I/O mode. Figures 87 and 88 show the pin connections for the standard serial I/O mode. In standard serial I/O mode, serial data I/O uses the four serial I/O pins SCLK, SRXD, STXD and SRDY (BUSY). The SCLK pin is the transfer clock input pin through which an external transfer clock is input. The STXD pin is for CMOS output. The SRDY (BUSY) pin outputs “L” level when ready for reception and “H” level when reception starts. Serial data I/O is transferred serially in 8-bit units. In standard serial I/O mode, only the User ROM area shown in Figure 79 can be rewritten. The Boot ROM area cannot. In standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, commands sent from the peripheral unit (programmer) are not accepted unless the ID code matches. Outline Performance (Standard Serial I/O Mode) In standard serial I/O mode, software commands, addresses and data are input and output between the MCU and peripheral units (flash programer, etc.) using 4-wire clock-synchronized serial I/O. In reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the SCLK pin, and are then input to the MCU via the SRXD pin. In transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the STXD pin. The STXD pin is for CMOS output. Transfer is in 8-bit units with LSB first. When busy, such as during transmission, reception, erasing or program execution, the SRDY (BUSY) pin is “H” level. Accordingly, always start the next transfer after the SRDY (BUSY) pin is “L” level. Also, data and status registers in a memory can be read after inputting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following explains software commands, status registers, etc. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 93 of 113 HARDWARE 7641 Group FLASH MEMORY MODE Table 13 Description of pin function (Standard Serial I/O Mode) Pin name VCC,VSS CNVSS RESET X IN XOUT AVCC, AVSS LPF Ext.Cap Signal name Power supply input CNVSS Reset input Clock input Clock output Analog power supply input LPF 3.3 V line power supply input I/O Function Apply 4.50 V – 5.25 V for 5 V version or 3.00 V – 3.60 V for 3 V version to the VCC pin. Apply 0 V to the Vss pin. I I This controls the MCU operating mode. Connect this pin to VPP (= 4.50 V – 5.25 V To reset, input “L” level for 20 cycles or longer clocks of φ. Connect a ceramic or crystal resonator between the XIN and XOUT pins. When inputting an externally derived clock, input it from XIN and leave XOUT open. Apply 4.50 V – 5.25 V for 5 V version or 3.00 V – 3.60 V for 3 V version to the AVCC pin. Apply 0 V to the AVss pin. O I Loop filter for the frequency synthesizer. When this pin is not used, leave this open. Power supply input pin for 3.3 V USB line driver. When this pin is not used, input “H” level. USB D+ signal port. When this pin is not used, input “H” level. USB D- signal port. When this pin is not used, input “L” level. When these ports are not used, input “L” or “H” level, or leave them open in output mode. USB D+ USB D- USB D+ USB D- I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O O I I O I/O P00 to P07 P10 to P17 P20 to P27 I/O port P0 I/O port P1 I/O port P2 P30 to P35, P37 I/O port P3 P36 P40 to P44 P50 to P57 P60 to P67 P70 to P74 P80 P81 P 82 P83 P84 to P87 CE input I/O port P4 I/O port P5 I/O port P6 I/O port P7 BUSY output SCLK input SRXD input STXDoutput I/O port P8 Input “H” level. When these ports are not used, input “L” or “H” level, or leave them open in output mode. This is a BUSY output pin. This is a serial clock input pin. This is a serial data input pin. This is a serial data output pin. When these ports are not used, input “L” or “H” level, or leave them open in output mode. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 94 of 113 HARDWARE 7641 Group FLASH MEMORY MODE 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 P20/DB0{DB0} P21/DB1{DB1} P22/DB2{DB2} P23/DB3{DB3} P24/DB4{DB4} P25/DB5{DB5} P26/DB6{DB6} P27/DB7{DB7} P00/AB0{AB0} P01/AB1{AB1} P02/AB2{AB2} P03/AB3{AB3} P04/AB4{AB4} P05/AB5{AB5} P06/AB6{AB6} P07/AB7{AB7} P10/AB8{AB8} P11/AB9{AB9} P12/AB10{AB10} P13/AB11{AB11} P14/AB12{AB12} P15/AB13{AB13} P16/AB14{AB14} P17/AB15{AB15} P74/OBF1 P73/IBF1/HLDA P72/S1 P71/HOLD P70/SOF USB D+ USB DExt.Cap VSS VCC P67/DQ7 P66/DQ6 P65/DQ5 P64/DQ4 P63/DQ3 P62/DQ2 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 M37641F8FP 33 32 31 30 29 28 27 26 25 P30/RDY P31 P32 P33/DMAOUT P34/φOUT P35/SYNCOUT P36/WR P37/RD P80/UTXD2/SRDY P81/URXD2/SCLK P82/CTS2/SRXD P83/RTS2/STXD P84/UTXD1 P85/URXD1 P86/CTS1 P87/RTS1 CE BUSY SCLK SRXD STXD 19 20 21 22 23 8 9 10 11 12 13 14 15 16 17 18 24 1 2 3 4 5 6 7 VSS CE VCC Note: It is necessary to apply Vcc only when reset is released. RESET VPP Mode setup method Signal Value 4.5 to 5.25 V CNVSS VCC (Note) SCLK VSS → VCC RESET Fig. 87 Pin connection diagram in standard serial I/O mode (1) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 95 of 113 P61/DQ1 P60/DQ0 P57/W/(R/W) P56/R(E) P55/A0 P54/S0 P53/IBF0 P52/OBF0 CNVSS RESET P51/TOUT/XCOUT P50/XCIN VSS XIN XOUT VCC AVCC LPF AVSS P44/CNTR1 P43/CNTR0 P42/INT1 P41/INT0 P40/EDMA VCC Connect to oscillator circuit. Package outline: PRQP0080GB-A HARDWARE 7641 Group FLASH MEMORY MODE 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 P21/DB1 P20/DB0 P74/OBF1 P73/IBF1/HLDA P72/S1 P71/HOLD P70/SOF USB D+ USB DExt.Cap VSS VCC P67/DQ7 P66/DQ6 P65/DQ5 P64/DQ4 P63/DQ3 P62/DQ2 P61/DQ1 P60/DQ0 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 44 43 42 41 P22/DB2{DB2} P23/DB3{DB3} P24/DB4{DB4} P25/DB5{DB5} P26/DB6{DB6} P27/DB7{DB7} P00/AB0{AB0} P01/AB1{AB1} P02/AB2{AB2} P03/AB3{AB3} P04/AB4{AB4} P05/AB5{AB5} P06/AB6{AB6} P07/AB7{AB7} P10/AB8{AB8} P11/AB9{AB9} P12/AB10{AB10} P13/AB11{AB11} P14/AB12{AB12} P15/AB13{AB13} M37641F8HP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P16/AB14{AD14} P17/AB15{AD15} P30/RDY P31 P32 P33/DMAOUT P34/φOUT P35/SYNCOUT P36/WR P37/RD P80/UTXD2/SRDY P81/URXD2/SCLK P82/CTS2/SRXD P83/RTS2/STXD P84/UTXD1 P85/URXD1 P86/CTS1 P87/RTS1 P40/EDMA P41/INT0 CE BUSY SCLK SRXD STXD P57/W/(R/W) P56/R(E) P55/A0 P54/S0 P53/IBF0 P52/OBF0 CNVSS RESET P51/TOUT/XCOUT P50/XCIN VSS XIN XOUT VCC AVCC LPF AVSS P44/CNTR1 P43/CNTR0 P42/INT1 VSS VCC Mode setup method Signal Value 4.5 to 5.25 V CNVSS VCC (Note) SCLK VSS → VCC RESET VCC CE Note: It is necessary to apply Vcc only when reset is released. Connect to oscillator circuit. RESET VPP Package outline: PLQP0080KB-A Fig. 88 Pin connection diagram in standard serial I/O mode (2) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 96 of 113 HARDWARE 7641 Group FLASH MEMORY MODE Software Commands (Standard Serial I/O Mode) Table 14 lists software commands. In standard serial I/O mode, erase, program and read are controlled by transferring software Table 14 Software commands (Standard serial I/O mode) Control command 1st byte transfer FF16 1 Page read 4116 2 3 4 5 6 7 Page program Block erase Erase all blocks Read status register Clear status register ID code check 2016 A716 7016 5016 F516 FA16 8 Download function Address (low) Size (low) Address (middle) Size (high) 2nd byte Address (middle) Address (middle) Address (middle) D016 SRD output SRD1 output 3rd byte Address (high) Address (high) Address (high) commands via the SRXD pin. Software commands are explained here below. 4th byte Data output Data input D016 5th byte Data output Data input 6th byte Data output Data input ..... Data output to 259th byte Data input to 259th byte When ID is not verified Not acceptable Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Address (high) Checksum ID size Data input ID1 To required number of times Version data output Data output To ID7 Acceptable Not acceptable FB16 9 10 Version data output function Boot ROM area output function FC16 Version data output Address (middle) Version data output Address (high) Version data output Data output Version data output Data output Version data output to 9th byte Data output to 259th byte Acceptable Not acceptable Notes1: Shading indicates transfer from the internal flash memory microcomputer to a programmer. All other data is transferred from an external equipment (programmer) to the internal flash memory microcomputer. 2: SRD refers to status register data. SRD1 refers to status register 1 data. 3: All commands can be accepted for the products of which boot ROM area is totally blank. 4: Address low is AB0 to AB7; Address middle is AB8 to AB15; Address high is AB16 to AB23. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 97 of 113 HARDWARE 7641 Group FLASH MEMORY MODE qPage Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the “FF16” command code with the 1st byte. (2) Transfer addresses AB8 to AB15 and AB16 to AB23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (DB0 to DB7) for the page (256 bytes) specified with addresses AB8 to AB23 will be output sequentially from the smallest address first synchronized with the fall of the clock. SCLK SRXD FF16 AB8 to AB16 to AB15 AB23 STXD data0 data255 SRDY (BUSY) Fig. 89 Timing for page read qRead Status Register Command This command reads status information. When the “70 16” command code is transferred with the 1st byte, the contents of the status register (SRD) with the 2nd byte and the contents of status register 1 (SRD1) with the 3rd byte are read. SCLK SRXD 7016 STXD SRD output SRD1 output SRDY (BUSY) Fig. 90 Timing for reading status register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 98 of 113 HARDWARE 7641 Group FLASH MEMORY MODE qClear Status Register Command This command clears the bits (SR3 to SR5) which are set when the status register operation ends in error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared. When the clear status register operation ends, the SRDY (BUSY) signal changes from “H” to “L” level. SCLK SRXD 5016 STXD SRDY (BUSY) Fig. 91 Timing for clear status register qPage Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the “4116” command code with the 1st byte. (2) Transfer addresses AB8 to AB15 and AB16 to AB23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (DB0 to DB7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. When reception setup for the next 256 bytes ends, the SRDY (BUSY) signal changes from “ H ” t o “ L ” l evel. The result of the page program can be known by reading the status register. For more information, see the section on the status register. SCLK SRXD 4116 AB8 to AB16 to data0 AB15 AB23 data255 STXD SRDY (BUSY) Fig. 92 Timing for page program Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 99 of 113 HARDWARE 7641 Group FLASH MEMORY MODE qBlock Erase Command This command erases the contents of the specifided block. Execute the block erase command as explained here following. (1) Transfer the “2016” command code with the 1st byte. (2) Transfer addresses AB8 to AB15 and AB16 to AB23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code “D016 ” with the 4th byte. With the verify command code, the erase operation will start for the specifided block in the flash memory. Set the addresses AB8 to AB23 to the maximum address of the specified block. When block erasing ends, the SRDY (BUSY) signal changes from “H” to “L” level. The result of the erase operation can be known by reading the status register. For more information, see the section on the status register. SCLK SRXD 2016 AB8 to AB15 AB16 to AB23 D016 STXD SRDY(BUSY) Fig. 93 Timing for block erasing qErase All Blocks Command This command erases the contents of all blocks. Execute the erase all blocks command as explained here following. (1) Transfer the “A716” command code with the 1st byte. (2) Transfer the verify command code “D0 16” with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. When erase all blocks end, the SRDY (BUSY) signal changes from “ H ” t o “ L ” l evel. The result of the erase operation can be known by reading the status register. SCLK SRXD A716 D016 STXD SRDY (BUSY) Fig. 94 Timing for erase all blocks Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 100 of 113 HARDWARE 7641 Group FLASH MEMORY MODE qDownload Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the “FA16” command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM. SCLK SRXD FA16 Data size Data size (low) (high) Check sum Program data STXD Program data SRDY (BUSY) Fig. 95 Timing for download Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 101 of 113 HARDWARE 7641 Group FLASH MEMORY MODE qVersion Information Output Command This command outputs the version information of the control program stored in the Boot ROM area. Execute the version information output command as explained here following. (1) Transfer the “FB16” command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters. SCLK SRXD FB16 STXD ‘V ’ ‘E’ ‘R’ ‘X’ SRDY (BUSY) Fig. 96 Timing for version information output qBoot ROM Area Output Command This command reads the control program stored in the Boot ROM area in page (256 bytes) unit. Execute the Boot ROM area output command as explained here following. (1) Transfer the “FC16” command code with the 1st byte. (2) Transfer addresses AB8 to AB15 and AB16 to AB23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (DB0 to DB7) for the page (256 bytes) specified with addresses AB8 to AB23 will be output sequentially from the smallest address first synchronized with the fall of the clock. SCLK SRXD FC16 A B 8 to A B 15 AB 1 6 to A B 23 STXD data0 data255 SRDY(BUSY) Fig. 97 Timing for Boot ROM area output Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 102 of 113 HARDWARE 7641 Group FLASH MEMORY MODE qID Code Check This command checks the ID code. Execute the boot ID check command as explained here following. (1) Transfer the “F516” command code with the 1st byte. (2) Transfer addresses AB0 to AB7, AB8 to AB15 and AB16 to AB23 (“0016”) of the 1st byte of the ID code with the 2nd and 3rd respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) Transfer the ID code with the 6th byte onward, starting with the 1st byte of the code. SCLK SRXD F516 C216 FF16 0016 ID size ID1 ID7 STXD SRDY (BUSY) Fig. 98 Timing for ID check qID Code When the flash memory is not blank, the ID code sent from the serial programmer and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the serial programmer is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses FFC216 to FFC816. Write a program into the flash memory, which already has the ID code set for these addresses. Address FFC216 FFC316 FFC416 FFC516 FFC616 FFC716 FFC816 FFC916 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ROM code protect control Interrupt vector area Fig. 99 ID code storage addresses Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 103 of 113 HARDWARE 7641 Group FLASH MEMORY MODE qStatus Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status register command (70 16 ). Also, the status register is cleared by writing the clear status register command (5016). Table 15 lists the definition of each status register bit. After releasing the reset, the status register becomes “8016”. •Sequencer status (SR7) The sequencer status indicates the operating status of the the flash memory. After power-on and recover from deep power down mode, the sequencer status is set to “1” (ready). This status bit is set to “0” (busy) during write or erase operation and is set to “1” upon completion of these operations. •Erase status (SR5) The erase status indicates the operating status of erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”. •Program status (SR4) The program status indicates the operating status of write operation. If a program error occurs, it is set to “1”. When the program status is cleared, it is set to “0”. Table 15 Definition of each bit of status register (SRD) Definition SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved “1” Ready Terminated in error Terminated in error - “0” Busy Terminated normally Terminated normally - Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 104 of 113 HARDWARE 7641 Group FLASH MEMORY MODE qStatus Register 1 (SRD1) The status register 1 indicates the status of serial communications, results from ID checks and results from check sum comparisons. It can be read after the status register (SRD) by writing the read status register command (7016). Also, status register 1 is cleared by writing the clear status register command (5016). Table 16 lists the definition of each status register 1 bit. This register becomes “0016” when power is turned on and the flag status is maintained even after the reset. •Boot update completed bit (SR15) This flag indicates whether the control program was downloaded to the RAM or not, using the download function. •Check sum consistency bit (SR12) This flag indicates whether the check sum matches or not when a program, is downloaded for execution using the download function. •ID code check completed bits (SR11 and SR10) These flags indicate the result of ID code checks. Some commands cannot be accepted without an ID code check. •Data reception time out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the received data is discarded and the MCU returns to the command wait state. Table 16 Definition of each bit of status register 1 (SRD1) SRD1 bits SR15 (bit7) SR14 (bit6) SR13 (bit5) SR12 (bit4) SR11 (bit3) SR10 (bit2) Status name Boot update completed bit Reserved Reserved Checksum match bit ID code check completed bits Definition “1” Update completed Match 00 01 10 11 Not verified Verification mismatch Reserved Verified Normal operation “0” Not Update Mismatch SR9 (bit1) SR8 (bit0) Data reception time out Reserved Time out Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 105 of 113 HARDWARE 7641 Group FLASH MEMORY MODE Full Status Check Results from executed erase and program operations can be known by running a full status check. Figure 100 shows a flowchart of the full status check and explains how to remedy errors which occur. Read status register SR4 = 1 and SR5 = 1 ? NO SR5 = 0 ? YES SR4 = 0 ? YES YES Command sequence error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should an erase error occur, the block in error cannot be used. NO Erase error NO Program error Should a program error occur, the block in error cannot be used. End (Erase, program) Note: When one of SR5 to SR4 is set to “1” , none of the page read, program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands. Fig. 100 Full status check flowchart and remedial procedure for errors Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 106 of 113 HARDWARE 7641 Group FLASH MEMORY MODE Example Circuit Application for Standard Serial I/O Mode Figure 101 shows a circuit application for the standard serial I/O mode. Control pins will vary according to a programmer, therefore see a programmer manual for more information. Clock input BUSY output Data input Data output SCLK SRDY (BUSY) SRXD STXD P36/WR (CE) M37641F8 VPP power source input CNVss Notes 1: Control pins and external circuitry will vary according to a programmer. For more information, see the programmer manual. 2: In this example, the Vpp power supply is supplied from an external source (programmer). To use the user’s power source, connect to 4.5 V to 5.25 V. Fig. 101 Example circuit application for standard serial I/O mode Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 107 of 113 HARDWARE 7641 Group NOTES ON PROGRAMMING NOTES ON PROGRAMMING Processor Status Register •The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. •To reference the contents of the processor status register (PS), execute the P HP i nstruction once then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its original status. A NOP instruction must be executed after every PLP instruction. •A SEI instruction must be executed before every PLP instruction. A NOP instruction must be executed before every CLI instruction. Ports •When the data register (port latch) of an I/O port is modified with the bit managing instruction (SEB, CLB instructions) the value of the unspecified bit may be changed. •In standby state (the stop mode by executing the STP instruction, and the wait mode by executing the W IT i nstruction) for lowpower dissipation, do not make input levels of an I/O port “undefined”, especially for I/O ports of the P-channel and the Nchannel open-drain. Pull-up (connect the port to Vcc) or pull-down (connect the port to Vss) these ports through a resistor. When determining a resistance value, note the following points: (1) External circuit (2) Variation of output levels during the ordinary operation When using built-in pull-up or pull-down resistor, note on varied current values. (1) When setting as an input port : Fix its input level (2) When setting as an output port : Prevent current from flowing out to external BRK Instruction It can be detected that the BRK instruction interrupt event or the least priority interrupt event by referring the stored B flag state. Refer to the stored B flag state in the interrupt routine. Decimal Calculations When decimal mode is selected, the values of the V flags are invalid. The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be initialized to “1” before each calculation. Serial I/O Do not write to the serial I/O shift register during a transfer when in SPI compatible mode. UART •The all error flags PER, FER, OER and SER are cleared to “0” when the UARTx status register is read, at the hardware reset or initialization by setting the Transmit Initialization Bit. These flags are also cleared to “0” by execution of bit test instructions such as BBC and BCS. •The transmission interrupt request bit is set and the interrupt request is generated by setting the transmit enable bit to “1” even when selecting timing that either of the following flags is set to “1” as timing where the transmission interrupt is generated: (1) Transmit buffer empty flag is set to “1” (2) Transmit complete flag is set to “1”. Therefore, when the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as the following sequence: (1) Transmit enable bit is set to “1” (2) Transmit interrupt request bit is set to “0” (3) Transmit interrupt enable bit is set to “1”. •Do not update a value of UARTx baud rate generator in the condition of transmission enabled or reception enabled. Disable transmission and reception before updating the value. If the former data remains in the UARTx transmit buffer registers 1 and 2 when transmission is enabled, an undefined data might be output. •The receive buffer full interrupt request is not generated if receive errors are detected at receiving. Multiplication and Division Instructions •The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. Timers •If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). •P51/XCOUT/TOUT pin cannot function as an I/O port when XCIN XCOUT is oscillating. When XCIN - XCOUT oscillation is not used or X COUT oscillation drive is disabled, this pin can function as the TOUT output pin of the timer 1 or 2. When using the TOUT output function and f(XCIN) divided by 2 is used as the timer 1 count source (bit 2 of T123M = “1”), disable XCOUT oscillation drive (bit 5 of CCR = “1”). Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 108 of 113 HARDWARE 7641 Group NOTES ON PROGRAMMING •If a character bit length is 7 bits, bit 7 of the UARTx transmit/receive buffer register 1 and bits 0 to 7 of the UARTx transmit/ receive buffer register 2 are ignored at transmitting; they are invalid at receiving. If a character bit length is 8 bits, bits 0 to 7 of the UARTx transmit/ receive buffer register 2 are ignored at transmitting; they are invalid at receiving. If a character bit length is 9 bits, bits 1 to 7 of the UARTx transmit/ receive buffer register 2 are ignored at transmitting; they are “0” at receiving. •The IN_PKT_RDY Bit can be set by software even when using the AUTO_SET function. •When writing to USB-related registers, set the USB Clock Enable Bit to “1”, then perform the write after four φ cycle waits. •When using the MCU at Vcc = 3.3V, set the USB Line Driver Supply Enable Bit to “0” (line driver disable). Note that setting the USB Line Driver Current Control Bit (USBC3) doesn’t affect the USB operation. •Read one packet data from the OUT FIFO before clearing the OUT_PKT_RDY Flag. If the OUT_PKT_RDY Flag is cleared while one packet data is being read, the internal read pointer cannot operate normally. •Use the AUTO_FLUSH Bit (bit 6 of address 0058 16 ) in double buffer mode. •Use the transfer instructions such as LDA and STA to set the registers: USB interrupt status registers 1, 2 (addresses 0052 16, 0053 16); USB endpoint 0 IN control register (address 0059 16 ); USB endpoint x IN control register (address 0059 16); USB endpoint x OUT control register (address 005A 16). Do not use the read-modify-write instructions such as the SEB or the CLB instruction. When writing to bits shown by Table 32 using the transfer instruction such as LDA or STA, a value which never affect its bit state is required. Take the following sequence to change these bits contents: (1) Store the register contents onto a variable or a data register. (2) Change the target bit on the variable or the data register. Simultaneously mask the bit so that its bit state cannot be changed. (See to Table 39.) (3) Write the value from the variable or the data register to the register using the transfer instruction such as LDA or STA. •To use the AUTO_SET function for an IN transfer when the AUTO_SET bit is set to 1, set the FIFO to single buffer mode. USB •When the USB Reset Interrupt Status Flag is kept at “1”, all other flags in the USB internal registers (addresses 005016 to 005F16) will return to their reset status. However, the following registers are not affected by the USB reset: USB control register (address 0013 16 ), Frequency synthesizer control register (address 006C16), Clock control register (address 001F16), and USB endpoint-x FIFO register (addresses 006016 to 006416). •When not using the USB function, set the USB Line Driver Supply Enable Bit of the USB control register (address 001316) to “1” for power supply to the internal circuits (at Vcc = 5V). •When using an isochronous transfer, set the FLUSH Bit (bit 6 of address 005916 and bit 6 of address 005A16) as follows: IN FIFO: use AUTO_FLUSH Bit (bit 6 of address 005816) OUT FIFO: when OUT_PKT_RDY Bit is “1”, set FLUSH Bit to “1” •When the USB SOF Port Select Bit is “1”, the reference pulse of 83.3 ns ( φ = 12 MHz) is output from the P70/SOF pin and synchronized with the SOF packet. Table 17 Bits of which state might be changed owing to software write Register name Bit name USB endpoint 0 IN control register IN_PKT_RDY (b1) DATA_END (b3) FORCE_STALL (b4) USB endpoint x (x = 1 to 4) IN control register IN_PKT_RDY (b0) UNDER_RUN (b1) USB endpoint x (x = 1 to 4) OUT control register OUT_PKT_RDY (b0) OVER_RUN (b1) FORCE_STALL (b4) DATA_ERR (b5) Value not affecting state (Note) “0” “0” “1” “0” “1” “1” “1” “1” “1” Note: Writing this value will not change the bit state, because this value cannot be written to the bit by software. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 109 of 113 HARDWARE 7641 Group NOTES ON PROGRAMMING Frequency Synthesizer •The frequency synthesizer and DC-DC converter must be set up as follows when recovering from a Hardware Reset: (1) Enable the frequency synthesizer after setting the frequency synthesizer related registers (addresses 006C16 to 006F16). Then wait for 2 ms. (2) Check the Frequency Synthesizer Lock Status Bit. If “0”, wait for 0.1 ms and then recheck. (3) When using the USB built-in DC-DC converter, set the USB Line Driver Supply Enable Bit of the USB control register to “1”. This setting must be done 2 ms or more after the setup described in step (1). The USB Line Driver Current Control Bit must be set to “0” at this time. (When Vcc = 3.3V, the setting explained in this step is not necessary.) (4) After waiting for (C + 1) ms so that the external capacitance pin (Ext. Cap. pin) can reach approximately 3.3 V, set the USB Clock Enable Bit to “1”. At this time, “C” equals the capacitance ( µ F) of the capacitor connected to the Ext. Cap. pin. For example, if 2.2 µF and 0.1 µF capacitors are connected to the Ext. Cap. in parallel, the required wait will be (2.3 + 1) ms. (5) After enabling the USB clock, wait for 4 or more φ cycles, and then set the USB Enable Bit to “1”. •Bits 6 and 5 of the frequency synthesizer control register (address 006C16) are initialized to “ 11 ” a fter reset release. Make sure to set bits 6 and 5 to “10” after the Frequency Synthesizer Lock Status Bit goes to “1”. •When using the frequency synthesized clock function, we recommend using the fastest frequency possible of f(XIN) or f(XCIN) as an input clock for the PLL. Owing to the PLL mechanism, the PLL controls the speed of multiplied clocks from the source clock. As a result, when the source clock input is lower, the generated clock becomes less stable. This is because more multipliers are needed and the speed control is very rough. Higher source clock input generates a stabler clock, as less multipliers are needed and the speed control is more accurate. However, if the input clock frequency is relatively high, the PLL clock generator can quickly lock-up the output clock to the source and make the output clock very stable. •Set the value of frequency synthesizer multiply register 2 (FSM2) so that the fPIN is 1 MHZ or higher. •When setting the DMAC channel x enable bit (bit 7 of address 004116) to “1”, be sure simultaneously to set the DMAC channel x transfer initiation source capture register reset bit (bit 6 of address 004116) to “1”. If this is not performed, an incorrect data will be transferred at the same time when the DMAC is enabled. Memory Expansion Mode & Microprocessor Mode •In both memory expansion mode and microprocessor mode, use the LDM instruction or STA instruction to write to port P3 (address 000E16). When using the Read-Modify-Write instruction (SEB instruction, CLB instruction) you will need to map a memory that the CPU can read from and write to. • In the memory expansion mode, if the internal and external memory areas overlap, the internal memory becomes the valid memory for the overlapping area. When the CPU performs a read or a write operation on this overlapped area, the following things happen: (1) Read The CPU reads out the data in the internal memory instead of in the external memory. Note that, since the CPU will output a proper read signal, address signal, etc., the memory data at the respective address will appear on the external data bus. (2) Write The CPU writes data to both the internal and external memories. •The wait function is serviceable at accessing an external memory. Stop Mode •When the STP instruction is executed, bit 7 of the clock control register (address 001F16) goes to “0”. To return from stop mode, reset CCR7 to “1”. •When using fSYN (set Internal System Clock Select Bit (CPMA6) to “1”) as the internal system clock, switch CPMA6 to “0” before executing the STP instruction. Reset CPMA6 after the system returns from Stop Mode and the frequency synthesizer has stabilized. CPMA6 does not need to be switched to “0” when using the WIT instruction. •When the STP instruction is being executed, all bits except bit 4 of the timer 123 mode register (address 002916) are initialized to “0”. It is not necessary to set T123M1 (Timer 1 Count Stop Bit) to “0” before executing the STP instruction. After returning from Stop Mode, reset the timer 1 (address 0024 16 ), timer 2 (address 002516), and the timer 123 mode register (address 002916). DMA •In the memory expansion mode and microprocessor mode, the DMAOUT pin outputs “H” during a DMA transfer. • Do not access the DMAC-related registers by using a DMAC transfer. The destination address data and the source address data will collide in the DMAC internal bus. •When using the USB FIFO as the DMA transfer source, make sure that, if you use the AUTO_SET function, short packet data does not get mixed in with the transfer data. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 110 of 113 HARDWARE 7641 Group USAGE NOTES USAGE NOTES Oscillator Connection Notice The built-in feedback register (1 M Ω) and the dumping resistor (400 Ω) is internally connected between pins XIN and XOUT. AVss and AVcc Pin Treatment Notice (Noise Elimination) An insulation connector (Ferrite Beads) must be connected between AVss and Vss pins and between AVcc and Vcc pins. Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. U S B Tr a n s c e i v e r Elimination) Tr e a t m e n t (Noise Power Supply Pins Treatment Notice Please connect 0.1 µF and 4.7 µF capacitors in parallel between pins Vcc and Vss, and pins AVss and AVcc. These capacitors must be connected as close as possible between the DC supply and GND pins, and also the analog supply pin and corresponding GND pin. Wiring patterns for these supply and GND pins must be wider than other signal patterns. These filter capacitors should not be placed near the LPF pins as they will cause noise problems •The Full-Speed USB2.0 specification requires a driver -impedance 28 to 44 Ω. (Refer to Clause 7.1.1.1 Full-speed (12 Mb/s) Driver Characteristics in the USB specification.) In order to meet the USB specification impedance requirements, connect a resistor (27 Ω to 33 Ω recommended) in series to the USB D+ pin and the USB Dpin. In addition, in order to reduce the ringing and control the falling/rising timing of USB D+/D- and a crossover point, connect a capacitor between the USB D+/D- pins and the Vss pin if necessary. The values and structure of those peripheral elements depend on the impedance characteristics and the layout of the printed circuit board. Accordingly, evaluate your system and observe waveforms before actual use and decide use of elements and the values of resistors and capacitors. •Connect a capacitor between the Ext. Cap. pin and the Vss pin. The capacitor should have a 2.2 µF capacitor (Tantalum capacitor) and a 0.1 µF capacitor (ceramic capacitor) connected in parallel. Figure 103 for the proper positions of the peripheral components. R e s e t P i n Tr e a t m e n t N o t i c e ( N o i s e Elimination) If the reset input signal rises very slowly, we recommend attaching a capacitor, such as a 1000 pF ceramic capacitor with excellent high frequency characteristics, between the RESET pin and the Vss pin. Please note the following two issues for this capacitor connection. (1) Capacitor wiring pattern must be as short as possible (within 20 mm). (2) The user must perform an application level operation test. XIN Frequency Synthesizer USBC5 enable DC-DC converter current mode enable lock LS enable FSE Note 1 Ext. Cap. USBC4 USBC3 2.2 µF 0.1 µF USB Clock (48 MHz) USB FCU enable USB transceiver enable D+ USBC7 USBC7 Note 2 D- LPF Pin Treatment Notice All passive components must be located as close as possible to the LPF pin. Notes 1: In Vcc = 3.3 V, connect to Vcc. In Vcc =5 V, do not connect the external DC-DC converter to the Ext. Cap pin. 2: The resistors values depend on the layout of the printed circuit board. Fig.103 Peripheral circuit LPF pin 1 kΩ 680 pF •In Vcc = 3.3 V operation, connect the Ext. Cap. pin directly to the Vcc pin in order to supply power to the USB transceiver. In addition, you will need to disable the DC-DC converter in this operation (set bit 4 of the USB control register to “0”.) If you are using the bus powered supply in Vcc = 3.3 V operation, the DCDC converter must be placed outside the MCU. •In Vcc = 5 V operation, do not connect the external DC-DC converter to the Ext. Cap. pin. Use the built-in DC-DC converter by enabling the USB line driver. •Make sure the USB D+/D- lines do not cross any other wires. Keep a large GND area to protect the USB lines. Also, make sure you use a USB specification compliant connecter for the connection. 0.1 µF AVSS pin Fig. 102 Passive components near LPF pin Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 111 of 113 1.5 kΩ HARDWARE 7641 Group USAGE NOTES USB Communication In applications requiring high-reliability, we recommend providing the system with protective measures such as USB function initialization by software or USB reset by the host to prevent USB communication from being terminated unexpectedly, for example due to external causes such as noise. • At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins. Electric Characteristic Differences Between Mask ROM and Flash Memory Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and Flash Memory version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with the Flash Memory version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version. Clock Input/Output Pin Wiring (Noise Elimination) (1) Make the wiring for the input/output pins as short as possible. (2) Make the wiring across the grounding lead of the capacitor which is connected to an oscillator and the Vss pin of the MCU as short as possible (within 20 mm) (3) Make sure to isolate the oscillation Vss pattern from other patterns for oscillation circuit-use only. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: 1. Mask ROM Order Confirmation Form 2. Mark Specification Form 3. Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk. For the mask ROM confirmation and the mark specifications, refer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com). Oscillator Wiring (Noise Elimination) (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines, including USB signal lines, where a current larger than the tolerance of current value flows. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. Terminate Unused Pins (1) Output ports : Open (2) Input ports : Connect each pin to Vcc or Vss through each resistor of 1 kΩ to 10 kΩ. Ports that permit the selecting of a built-in pull-up or pull-down resistor can also use this resistor. As for pins whose potential affects to operation modes such as pins CNVss, INT or others, select the Vcc pin or the Vss pin according to their operation mode. (3) I/O ports : • Set the I/O ports for the input mode and connect them to Vcc or Vss through each resistor of 1 kΩ to 10 kΩ. Ports that permit the selecting of a built-in pull-up or pull-down resistor can also use this resistor. Set the I/O ports for the output mode and open them at “L” or “H”. • When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. • Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 112 of 113 HARDWARE 7641 Group FUNCTIONAL DESCRIPTION SUPPLEMENT Timing After Interrupt The interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently in execution. Figure 104 shows a timing chart after an interrupt occurs, and Figure 105 shows the time up to execution of the interrupt processing routine. φ SYNC RD WR Address bus Data bus PC Not used S, SPS S-1, SPS S-2, SPS BL AL BH AL, AH AH PCH P CL PS SYNC : CPU operation code fetch cycle (This is an internal signal which cannot be observed from the external unit.) BL, BH : Vector address of each interrupt AL, AH : Jump destination address of each interrupt SPS : “0016” or “0116” Fig. 104 Timing chart after interrupt occurs Interrupt request occurs Interrupt operation starts Main routine Waiting time for pipeline postprocessing Push onto stack vector fetch Interrupt processing routine 0 to 16 cycles 2 cycles 5 cycles 7 to 23 cycles (f(φ) = 12 MHz, 0.583 µs to 1.92 µs) Fig. 105 Time up to execution of interrupt processing routine Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 113 of 113 T HIS PAGE IS BLANK FOR REASONS OF LAYOUT. C HAPTER 2 APPLICATION 2.1 I/O port 2.2 Timer 2.3 Serial I/O 2.4 UART 2.5 DMAC 2.6 USB 2.7 Frequency synthesizer 2.8 Master CPU bus interface 2.9 Special count source generator 2.10 External devices connection 2.11 Reset 2.12 Clock generating circuit APPLICATION 7641 Group 2.1 I/O port 2.1 I/O port This paragraph explains the registers setting method and the notes related to the I/O port. 2.1.1 Memory map Address 000416 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001216 Interrupt request register C (IREQC) Interrupt control register C (ICONC) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port control register (PTC) Port P2 pull-up control register (PUP2) 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 Port P6 (P6) Port P6 direction register (P6D) Port P5 (P5) Port P5 direction register (P5D) Port P4 (P4) Port P4 direction register (P4D) Port P7 (P7) Port P7 direction register (P7D) Port P8 (P8) Port P8 direction register (P8D) Fig. 2.1.1 Memory map of registers related to I/O port Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 2 of 148 APPLICATION 7641 Group 2.1 I/O port 2.1.2 Related registers Port Pi b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (i = 0, 1, 2, 3, 5, 6, 8) (Pi : addresses 0816, 0A16, 0C16, 0E16, 1616, 1416, 1C16) b 0 Port Pi0 1 Port Pi1 2 Port Pi2 3 Port Pi3 4 Port Pi4 5 Port Pi5 6 Port Pi6 7 Port Pi7 Name Functions qIn output mode Write •••••••• Port latch Read •••••••• Port latch qIn input mode Write •••••••• Port latch Read •••••••• Value of pin At reset R W 0 0 0 0 0 0 0 0 Fig. 2.1.2 Structure of Port Pi register Port P4, Port P7 b7 b6 b5 b4 b3 b2 b1 b0 Port P4, Port P7 (P4, P7 : addresses 1816, 1A16) b Name Functions qIn output mode Write •••••••• Port latch Read •••••••• Port latch qIn input mode Write •••••••• Port latch Read •••••••• Value of pin At reset R W 0 0 0 0 0 0 Port P40 or Port P70 1 Port P41 or Port P71 2 Port P42 or Port P72 3 Port P43 or Port P73 4 Port P44 or Port P74 5 Nothing is arranged for these bits. These are write disable bits. When Undefined ✕ ✕ 6 these bits are read out, the contents are undefined. Undefined ✕ ✕ Undefined ✕ ✕ 7 Fig. 2.1.3 Structure of Port P4, Port P7 registers Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 3 of 148 APPLICATION 7641 Group 2.1 I/O port Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (i = 0, 1, 2, 3, 5, 6, 8) (PiD : addresses 0916, 0B16, 0D16, 0F16, 1716, 1516, 1D16) b Name Functions 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode At reset R W 0 0 0 0 0 0 0 0 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ 0 Port Pi direction register 1 2 3 4 5 6 7 Fig. 2.1.4 Structure of Port Pi direction register (i = 0, 1, 2, 3, 5, 6, 8) Port P4, P7 direction registers b7 b6 b5 b4 b3 b2 b1 b0 Port P4 direction register, Port P7 direction register (P4D, P7D : addresses 1916, 1B16) b Name Functions 0 : Port P40 or P70 input mode 1 : Port P40 or P70 output mode 0 : Port P41 or P71 input mode 1 : Port P41 or P71 output mode 0 : Port P42 or P72 input mode 1 : Port P42 or P72 output mode 0 : Port P43 or P73 input mode 1 : Port P43 or P73 output mode 0 : Port P44 or P74 input mode 1 : Port P44 or P74 output mode At reset R W 0 0 0 0 0 ✕ ✕ ✕ ✕ ✕ 0 Port P4 direction register Port P7 direction register 1 2 3 4 5 Nothing is arranged for these bits. These are write disable bits. When Undefined ✕ ✕ 6 these bits are read out, the contents are undefined. Undefined ✕ ✕ Undefined ✕ ✕ 7 Fig. 2.1.5 Structure of Port P4 direction, Port P7 direction registers Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 4 of 148 APPLICATION 7641 Group 2.1 I/O port Port control register b7 b6 b5 b4 b3 b2 b1 b0 Port control register (PTC : address 1016) b 0 1 2 3 4 5 6 7 Name Port P0 to P3 slew rate control bit (Note 1) Port P4 slew rate control bit (Note 1) Port P5 slew rate control bit (Note 1) Port P6 slew rate control bit (Note 1) Port P7 slew rate control bit (Note 1) Port P8 slew rate control bit (Note 1) Port P2 input level select bit Master CPU bus input level select bit Functions 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Reduced VIHL level input (Note 2) 1 : CMOS level input 0 : CMOS level input 1 : TTL level input At reset R W 0 0 0 0 0 0 0 0 Notes 1: The slew rate function can reduce di/dt by modifying an internal buffer structure. 2: The characteristics of VIHL level is basically the same as that of TTL level. But, its switching center point is a little higher than TTL’s. Fig. 2.1.6 Structure of Port control register Port P2 pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Port P2 pull-upt control register (PUP2 : address 1216) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 Port P20 pull-up control bit 0 : Disabled 1 : Enabled 1 Port P21 pull-up control bit 0 : Disabled 1 : Enabled 2 Port P22 pull-up control bit 0 : Disabled 1 : Enabled 3 Port P23 pull-up control bit 0 : Disabled 1 : Enabled 4 Port P24 pull-up control bit 0 : Disabled 1 : Enabled 5 Port P25 pull-up control bit 0 : Disabled 1 : Enabled 6 Port P26 pull-up control bit 0 : Disabled 1 : Enabled 7 Port P27 pull-up control bit 0 : Disabled 1 : Enabled Fig. 2.1.7 Structure of Port P2 pull-up control register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 5 of 148 APPLICATION 7641 Group 2.1 I/O port Interrupt request register C b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register C (IREQC : address 0416) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 ✽ ✽ ✽ ✽ ✽ ✽ ✽ 0 Timer 3 interrupt request bit 1 CNTR0 interrupt request bit 2 CNTR1 interrupt request bit 3 Serial I/O interrupt request bit 4 Input buffer full interrupt request bit 5 Output buffer empty interrupt request bit 6 Key input interrupt request bit 7 Fix this bit to “0”. ✽: “0” can be set by software, but “1” cannot be set. Fig. 2.1.8 Structure of Interrupt request register C Interrupt control register C b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt control register C (ICONC : address 0716) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 Timer 3 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 1 CNTR0 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 2 CNTR1 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 3 Serial I/O interrupt enable bit 4 Input buffer full interrupt enable bit 5 Output buffer empty interrupt enable bit 6 Key input interrupt enable bit 7 Fix this bit to “0”. 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Fig. 2.1.9 Structure of Interrupt control register C Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 6 of 148 APPLICATION 7641 Group 2.1 I/O port 2.1.3 Key-on wake-up interrupt application example Outline : Key-on wake-up is realized, using internal pull-up resistors. Figure 2.1.10 shows the registers setting; Figure 2.1.11 shows a connection diagram; Figure 2.1.12 shows the control procedure. Port P2 direction register (address 0D16) b7 b0 P2D 00000 Input mode Port P2 pull-up control register (address 1216) b7 b0 PUP2 11111 Port P20 to P24 pull-up enabled Port control register (address 1016) b7 b0 PTC 0 VIHL level Interrupt request register C (address 0416) b7 b0 IREQC 00 Key input interrupt request bit Interrupt control register C (address 0716) b7 b0 ICONC 01 Key input interrupt: Enabled Fig. 2.1.10 Registers setting Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 7 of 148 APPLICATION 7641 Group 2.1 I/O port 7641 group P 20 P2i (i : 0 to 4) P 21 Key ON P 22 P 23 P 24 Fig. 2.1.11 Connection diagram RESET q X: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization P2D (address 0D16) PUP2 (address 1216) PTC (address 1016) Power down process IREQC,bit6 (address 0416) ICONC,bit6 (address 0716) WIT Process continued Fig. 2.1.12 Control procedure Rev.2.00 Aug 28, 2006 REJ09B0336-0200 .... XXX000002 XXX111112 X0XXXXXX2 •Set to input mode •Pull-up enabled •Reduced VIHL level ..... ..... 0 1 •Set key input interrupt request bit to “0” •Key input interrupt enabled Key input interrupt routine Key input interrupt process ..... RTI ..... page 8 of 148 APPLICATION 7641 Group 2.1 I/O port 2.1.4 Terminate unused pins Table 2.1.1 Termination of unused pins Termination P0, P1, P2, P3, P4, P5, • Set to the input mode and connect each to V CC or VSS through a resistor of 1 k Ω to 10 k Ω. P6, P7, P8 • S et to the output mode and open at “ L ” o r “ H ” o utput state. Pins/Ports name HOLD, RDY CNVSS AVSS AVCC XOUT USB D+ USB DExt. Cap. SOF Connect to Vcc (DC-DC converter disabled) when the USB function is not used. Open Connect to Vcc through a resistor (pull-up). Connect to Vcc or Vss. Connect to Vss (GND). Connect to Vcc. Open (only when using external clock) Open Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 9 of 148 APPLICATION 7641 Group 2.1 I/O port 2.1.5 Notes on I/O port (1) Notes in standby state In standby state ✽1 f or low-power dissipation, do not make input levels of an I/O port “ undefined ” . Pull-up (connect the port to V CC ) or pull-down (connect the port to V SS ) these ports through a resistor. When determining a resistance value, note the following points: • E xternal circuit • V ariation of output levels during the ordinary operation When using built-in pull-up resistor, note on varied current values: • W hen setting as an input port : Fix its input level • When setting as an output port : Prevent current from flowing out to external q Reason The potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an I/O port are “ undefined ” . This may cause power source current. ✽ 1 standby state: stop mode by executing S TP i nstruction wait mode by executing W IT i nstruction (2) Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction✽2, the value of the unspecified bit may be changed. q R eason The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an I/O port, the following is executed to all bits of the port latch. • As for bit which is set for input port: The pin state is read in the CPU, and is written to this bit after bit managing. • As for bit which is set for output port: The bit value is read in the CPU, and is written to this bit after bit managing. Note the following: •Even when a port which is set as an output port is changed for an input port, its port latch holds the output data. • As for a bit of which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. ✽ 2 Bit managing instructions: S EB a nd C LB i nstructions (3) Pull-up control When using port P2, which includes a pull-up resistor, as an output port, its port pull-up control is invalidated, that is, pull-up cannot be enabled. q R eason Pull-up/pull-down control is valid only when each direction register is set to the input mode. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 10 of 148 APPLICATION 7641 Group 2.1 I/O port 2.1.6 Termination of unused pins (1) Terminate unused pins ➀ I /O ports : • Set the I/O ports for the input mode and connect them to V CC o r V SS t hrough each resistor of 1 k Ω t o 10 k Ω . Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/O ports for the output mode and open them at “L” or “H”. • When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. • Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. ➁ T he AVss pin when not using the A/D converter : • When not using the A/D converter, handle a power source pin for the A/D converter, AVss pin as follows: AVss: Connect to the Vss pin. (2) Termination remarks ➀ I /O ports : Do not open in the input mode. q R eason • The power source current may increase depending on the first-stage circuit. • An effect due to noise may be easily produced as compared with proper termination ➁ a nd shown on the above. ➁ I /O ports : When setting for the input mode, do not connect to V CC o r V SS d irectly. q R eason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and V CC ( or V SS). ➂ I /O ports : When setting for the input mode, do not connect multiple ports in a lump to V CC o r VSS t hrough a resistor. q R eason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. • At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 11 of 148 APPLICATION 7641 Group 2.2 Timer 2.2 Timer This paragraph explains the registers setting method and the notes related to the timers. 2.2.1 Memory map Address 000316 000416 000616 000716 Interrupt request register B (IREQB) Interrupt request register C (IREQC) Interrupt control register B (ICONB) Interrupt control register C (ICONB) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 Timer XL (TXL) Timer XH (TXH) Timer YL (TYL) Timer YH (TYH) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer X mode register (TXM) Timer Y mode register (TYM) Timer 123 mode register (T123M) Fig. 2.2.1 Memory map of registers relevant to timers Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 12 of 148 APPLICATION 7641 Group 2.2 Timer 2.2.2 Related registers (1) 8-bit timer Timer i (i = 1 to 3) b7 b6 b5 b4 b3 b2 b1 b0 Timer 1, Timer 2, Timer 3 (T1, T2, T3: addresses 2416, 2516, 2616) b 0 1 2 3 4 5 6 7 Functions qTimer i’s count value is set through this register. qTimer 1 and Timer 2 Writing operation depends on the timers 1, 2 write control bit. When it is “0”, the values are simultaneously written into their latches and counters. When it is “1”, the values are written into only their latches. qTimer 3 The values are simultaneously written into their latches and counters. qWhen reading this register’s address, its timer’s count values are read out. qThe timer causes an underflow at the count pulse following the count where the timer contents reaches “0016”. Then The contents of latches are automatically reloaded into the timer. At reset R W (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) Note: Timer 1 and Timer 3’s values are “FF16”. Timer 2 ’s value are “0116”. Fig. 2.2.2 Structure of Timer i (i=1, 2, 3) Timer 123 mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer 123 mode register (T123M : address 2916) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 TOUT factor select bit 1 2 3 4 5 6 7 0 : Timer 1 output 1 : Timer 2 output 0 : Count start Timer 1 count stop bit 1 : Count stop Timer 1 count source 0:φ/8 select bit 1 : f(XCIN) / 2 Timer 2 count source 0 : Timer 1 output select bit 1:φ 0 : Timer 1 output Timer 3 count source 1:φ/8 select bit TOUT output active edge 0 : Start at “H” output switch bit 1 : Start at “L” output TOUT output control bit 0 : TOUT output disabled 1 : TOUT output enabled Timers 1, 2 write control bit 0 : Write value in latch and counter 1 : Write value in latch only Fig. 2.2.3 Structure of Timer 123 mode register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 13 of 148 APPLICATION 7641 Group 2.2 Timer (2) 16-bit timer Timer X (low, high) b7 b6 b5 b4 b3 b2 b1 b0 Timer XL, Timer XH (TXL, TXH: addresses 2016, 2116) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qTimer X’s count value is set through this register. qWriting operation depends on the timer X write control bit. When it is “0”, the values are simultaneously written into timer X 1 latch and counter. 2 When it is “1”, the values are written into only timer X latch. qTimer X is a down-count timer. 3 qWhen reading this register’s address, the timer X’s count value is read out. 4 5 6 7 Notes 1: Read and write operation to timer X must be performed for both high and low-order bytes. 2: When reading timer X, read the high-order byte first and then the low-order byte. 3: When writing to timer X, write the low-order byte first and then the high-order byte. 4: Do not read this register during the write operation, or do not write during the read operation. Fig. 2.2.4 Structure of Timer X (low-order, high-order) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 14 of 148 APPLICATION 7641 Group 2.2 Timer Timer X mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register (TXM : address 2716) b Name Functions 0 : Write value in latch and counter 1 : Write value in latch only b2b1 At reset R W 0 0 0 0 0 0 0 0 0 Timer X write control bit 1 Timer X count source select bits 2 3 Timer X internal clock select bit 4 Timer X operating mode bits 00:φ/8 0 1 : φ / 16 1 0 : φ / 32 1 1 : φ / 64 0 : φ / n (n = 8, 16, 32, 64) 1 : SCSGCLK (Special Count Source Generator) b5b4 0 0 : Timer mode 0 1 : Pulse output mode 5 1 0 : Event counter mode 1 1 : Pulse width measurement mode 6 CNTR0 active edge switch This function depends on the timer X operating mode. (See below.) bit 0 : Count start 7 Timer X count stop bit 1 : Count stop Function of CNTR0 active edge switch bit Timer X operating mode Pulse output mode Event counter mode Pulse width measurement mode Interrupt CNTR0 active edge switch bit 0 : Starts at “H” output 1 : Starts at “L” output 0 : Counts at rising edge 1 : Counts at falling edge 0 : Measures “H” pulse width 1 : Measures “L” pulse width 0 : Falling edge active 1 : Rising edge active Fig. 2.2.5 Structure of Timer X mode register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 15 of 148 APPLICATION 7641 Group 2.2 Timer Timer Y (low, high) b7 b6 b5 b4 b3 b2 b1 b0 Timer YL, Timer YH (TYL, TYH: addresses 2216, 2316) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qTimer Y’s count value is set through this register. qTimer Y is a down-count timer. 1 qWhen reading this register’s address, the timer Y’s count value is read out. 2 3 4 5 6 7 Notes 1: Read and write operation to timer X must be performed for both high and low-order bytes. 2: When reading timer X, read the high-order byte first and then the low-order byte. 3: When writing to timer X, write the low-order byte first and then the high-order byte. 4: Do not read this register during the write operation, or do not write during the read operation. Fig. 2.2.6 Structure of Timer Y (low-order, high-order) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 16 of 148 APPLICATION 7641 Group 2.2 Timer Timer Y mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer Y mode register (TYM : address 2816) b Name Functions 0 : Write value in latch and counter 1 : Write value in latch only 0 : TYOUT output disabled 1 : TYOUT output enabled b3b2 At reset R W 0 0 0 0 0 0 Timer Y write control bit 1 Timer Y output control bit 2 Timer Y count source select bits 3 4 Timer Y operating mode bits 00:φ/8 0 1 : φ / 16 1 0 : φ / 32 1 1 : φ / 64 b5b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 5 1 1 : Pulse width HL continuously measurement mode 6 CNTR1 active edge switch This function depends on the timer Y operating mode. (See below.) bit 0 : Count start 7 Timer Y count stop bit 1 : Count stop 0 0 0 Function of CNTR1 active edge switch bit CNTR1 active edge switch bit 0 : Measures between falling edges Period measurement mode 1 : Measures between rising edges 0 : Counts at rising edge Event counter mode 1 : Counts at falling edge 0 : Starts at “H” output TYOUT output 1 : Starts at “L” output Interrupt 0 : Falling edge active 1 : Rising edge active Timer Y operating mode Fig. 2.2.7 Structure of Timer Y mode register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 17 of 148 APPLICATION 7641 Group 2.2 Timer (3) 8-bit timer, 16-bit timer Interrupt request register B b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register B (IREQB : address 0316) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ 0 UART1 summing error interrupt request bit 1 UART2 receive buffer full interrupt request bit 2 UART2 transmit interrupt request bit 3 UART2 summing error interrupt request bit 4 Timer X interrupt request bit 5 Timer Y interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit 0 : No interrupt request issued 6 Timer 1 interrupt request 1 : Interrupt request issued bit 0 : No interrupt request issued 7 Timer 2 interrupt request bit 1 : Interrupt request issued ✽: “0” can be set by software, but “1” cannot be set. Fig. 2.2.8 Structure of Interrupt request register B Interrupt request register C b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register C (IREQC : address 0416) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 ✽ ✽ ✽ ✽ ✽ ✽ ✽ 0 Timer 3 interrupt request bit 1 CNTR0 interrupt request bit 2 CNTR1 interrupt request bit 3 Serial I/O interrupt request bit 4 Input buffer full interrupt request bit 5 Output buffer empty interrupt request bit 6 Key input interrupt request bit 7 Fix this bit to “0”. ✽: “0” can be set by software, but “1” cannot be set. Fig. 2.2.9 Structure of Interrupt request register C Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 18 of 148 APPLICATION 7641 Group 2.2 Timer Interrupt control register B b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register B (ICONB : address 0616) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 0 0 0 0 0 0 UART1 summing error interrupt enable bit 1 UART2 receive buffer full interrupt enable bit 2 UART2 transmit interrupt enable bit 3 UART2 summing error interrupt enable bit 4 Timer X interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 5 Timer Y interrupt enable 1 : Interrupt enabled bit 6 Timer 1 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 7 Timer 2 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled Fig. 2.2.10 Structure of Interrupt control register B Interrupt control register C b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt control register C (ICONC : address 0716) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 Timer 3 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 1 CNTR0 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 2 CNTR1 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 3 Serial I/O interrupt enable bit 4 Input buffer full interrupt enable bit 5 Output buffer empty interrupt enable bit 6 Key input interrupt enable bit 7 Fix this bit to “0”. 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Fig. 2.2.11 Structure of Interrupt control register C Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 19 of 148 APPLICATION 7641 Group 2.2 Timer 2.2.3 Timer application examples (1) Basic functions and uses [Function 1] Control of event interval (Timer 1 to Timer 3, Timer X and Y: Timer mode) When a certain time, by setting a count value to each timer, has passed, the timer interrupt request occurs. • Generating of an output signal timing • Generating of a wait time [Function 2] Control of cyclic operation (Timer 1 to Timer 3, Timer X and Y: Timer mode) The value of the timer latch is automatically written to the corresponding timer each time the timer underflows, and each timer interrupt request occurs in cycles. • Generating of cyclic interrupts • Clock function (measurement of 1 s); see “ (2) Timer application example 1 ” • Control of a main routine cycle [Function 3] Output of rectangular waveform (Timer 1, Timer 2, Timer X: Pulse output mode; Timer Y: TY OUT o utput) The output levels of the TOUT, CNTR0 and CNTR1 pins are inverted each time the timer underflows. • Piezoelectric buzzer output; see “ (3) Timer application example 2 ” • Generating of the remote control carrier waveforms [Function 4] Count of external pulses (Timer X, Timer Y: Event counter mode) External pulses input to the CNTR0 pin and CNTR1 pin are respectively counted as the timer count source (in the event counter mode). • Frequency measurement; see “ (4) Timer application example 3 ” • Division of external pulses •Generating of interrupts due to a cycle using external pulses as the count source; count of a reel pulse [Function 5] Measurement of external pulse width 1 (Timer X: Pulse width measurement mode) The “ H ” o r “ L ” l evel width of external pulses input to CNTR0 p in is measured. •Measurement of external pulse frequency (measurement of pulse width of FG pulse✽ for a motor); see “ (5) Timer application example 4 ” • Measurement of external pulse duty (when the frequency is fixed) FG pulse ✽: Pulse used for detecting the motor speed to control the motor speed. [Function 6] Measurement of external pulse width 2 (Timer Y: Period measurement mode) The external pulse width input to CNTR1 p in is measured. • Measurement of phase control signal; see “ (6) Timer application example 5 ” Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 20 of 148 APPLICATION 7641 Group 2.2 Timer (2) Timer application example 1: Clock function (measurement of 1 s) Outline : The input clock is divided by the timer so that the clock can count up at 1 s intervals. Specifications: • The clock f(X CIN) = 32 kHz is divided by the timer. • The timer 2 interrupt request bit is checked in main routine, and if the interrupt request is issued, the clock is counted up. • The timer 1 interrupt occurs every 10 ms to execute processing of other interrupts. Figure 2.2.12 shows the timers connection and setting of division ratios; Figure 2.2.13 shows the related registers setting; Figure 2.2.14 shows the control procedure. Timer 1 f(XCIN) 32 kHz 1/2 1/160 Timer 2 1/100 Timer 2 interrupt request bit 0/1 1s 0/1 10 m s 0 : No interrupt request issued 1 : Interrupt request issued Timer 1 interrupt request bit Fig. 2.2.12 Timers connection and setting of division ratios Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 21 of 148 APPLICATION 7641 Group 2.2 Timer CPU mode register A (address 0016) b7 b0 CPMA 10111 Processor mode bits Stack page select bit Sub-clock (XCIN-XCOUT): Oscillating Main clock (XIN-XOUT): Stopped Internal system clock: XCIN-XCOUT Timer 123 mode register (address 2916) b7 b0 T123M 00 010 Timer 1 count: In progress Timer 1 count source: f(XCIN) / 2 Timer 2 count source: Timer 1’s underflow TOUT output disabled Timers 1, 2 write control: Written at the same time Timer 1 (address 2416) b7 b0 T1 9F16 Timer 2 (address 2516) b7 b0 Set “division ratio – 1”. [ T1 = 159 (9F16), T2 = 99 (6316) ] T2 6316 Interrupt control register B (address 0616) b7 b0 ICONB 01 Timer 1 interrupt: Enabled Timer 2 interrupt: Disabled Interrupt request register B (address 0316) b7 b0 IREQB Timer 1 interrupt request Timer 2 interrupt request Fig. 2.2.13 Related registers setting Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 22 of 148 APPLICATION 7641 Group 2.2 Timer RESET q X: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization SEI •All interrupts disabled (address 0016) (address 2916) (address 2416) (address 2516) (address 0316) (address 0616) (address 2916), bit1 10111XXX2 00XX011X2 9 F1 6 6316 00XXXXXX2 01XXXXXX2 0 ..... ..... T1 T2 IREQB ICONB T123M CLI ..... •Interrupts enabled Clock is stopped ? N Y •Judgment whether time is not set or time is being set IREQB (address 0316), bit7 ? 1 0 •Confirmation that 1 s has passed (Check of Timer 2 interrupt request bit) IREQB (address 0316), bit7 •Interrupt request bit cleared (Clear it by software when not using the interrupt.) ..... ..... •Setting of Interrupt request bits of Timers 1 and 2 to “0” •Timer 1 interrupt enabled, Timer 2 interrupt disabled •Timer count start •Setting “Division ratio – 1” to Timers 1 and 2 CPMA T123M •Connection of Timers 1 and 2 ✽ 0 Clock count up Second to Year •Clock count up Main processing (Note) T2 IREQB (address 2516) (address 0316), bit7 6316 0 ..... •Adjust the main processing so that all processing in the loop ✽ will be processed within 1 s interval. •Set Timers again when starting clock from 0 s after end of clcok setting. •Do not set Timer 1 again because Timer 1 is used to generate the interrupt at 10 ms intervals. Note : Perform procedure for end of clock setting only when end of clock setting. Fig. 2.2.14 Control procedure Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 23 of 148 APPLICATION 7641 Group 2.2 Timer (3) Timer application example 2: Piezoelectric buzzer output Outline: The rectangular waveform output function of the timer is applied for a piezoelectric buzzer output. Specifications: •The rectangular waveform, dividing the clock f(X IN) = 4.19 MHz (2 22 Hz) into about 2 kHz (2048 Hz), is output from the P43/CNTR 0 p in. • The level of the P4 3/CNTR 0 p in is fixed to “ H ” w hile a piezoelectric buzzer output stops. Figure 2.2.15 shows a peripheral circuit example, and Figure 2.2.16 shows the timers connection and setting of division ratios. Figure 2.2.17 shows the related registers setting, and Figure 2.2.18 shows the control procedure. The “H” level is output while a piezoelectric buzzer output stops. CNTR0 output P43/CNTR0 244 µs 244 µs Set a division ratio so that the underflow output period of the timer X can be 244 µs. 7641 Group PiPiPi..... Fig. 2.2.15 Peripheral circuit example Count source selection φ/8 f(XIN) 4.19 MHz 1/2 1/8 Timer X 1/64 Fixed 1/2 P43/CNTR0 Fig. 2.2.16 Timers connection and setting of division ratios Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 24 of 148 APPLICATION 7641 Group 2.2 Timer Clock control register (address 1F16) b7 b0 CCR 1 00000 System clock: f(XIN) CPU mode register A (address 0016) b7 b0 CPMA 000 1 Processor mode bits Stack page select bit Main clock (XIN-XOUT): Oscillating Internal system clock: f(XIN) Port P4 (address 1816) b7 b0 P4 0116 Set an initial value. Port P4 direction register (address 1916) b7 b0 P4D 1 Set to output mode. Timer X mode register (address 2716) b7 b0 TXM 10010000 Timer X write control: Written at the same time Timer X count source: φ / 8 Timer X internal clock: φ / n Pulse output mode Pulse output: Start from “H” output Timer X count: Stopped Timer XL (low) (address 2016) b7 b0 TXL 3F16 Timer XH (high) (address 2116) b7 b0 Set “division ratio – 1” = 63 (3F16) TXH 0016 Interrupt control register B (address 0616) b7 b0 ICONB 0 Timer X interrupt: Disabled Fig. 2.2.17 Relevant registers setting Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 25 of 148 APPLICATION 7641 Group 2.2 Timer RESET q X: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization SEI CCR CPMA P4 P4D TMX TXL TXH ICONB (address 1F16), bit7 (address 0016) (address 1816), bit3 (address 1916), bit3 (address 2716) (address 2016) (address 2116) (address 0616), bit4 1 00001XXX2 1 1 100100002 3F16 0016 0 •All interrupts disabled •φ = f(XIN)/2 •Port P43/CNTR0 s tate setting at buzzer output stopped; “H” level output •Timer X interrupt disabled •CNTR0 output stopped; Buzzer output stopped •Interrupts enabled Main processing Output unit Piezoelectric buzzer request ? Yes Stop of piezoelectric buzzer output Fig. 2.2.18 Control procedure Rev.2.00 Aug 28, 2006 REJ09B0336-0200 .... . CLI No TXM TXL TXH (address 2716), bit7 (address 2016) (address 2116) 1 3F16 0016 •Processing buzzer request, generated during main processing, in output unit TXM (address 2716), bit7 0 Start of piezoelectric buzzer output page 26 of 148 APPLICATION 7641 Group 2.2 Timer (4) Timer application example 3: Frequency measurement Outline : The pulse frequency input to P4 4/CNTR1 p in is measured by measuring the event number within a fixed term. Specifications: • The pulse is input to the P4 4/CNTR 1 p in and counted by the timer Y. •A count value of timer Y is read out at 1 ms intervals, which is the timer 2 interrupt interval. As the result, the frequency can be calculated. (This example is in f(X IN) = 24 MHz and φ = f (X IN)/4.) • The input event number must be “ FFFF 16” w ithin 1 ms. Figure 2.2.19 shows how to measure the frequency; Figure 2.2.20 shows the related registers setting; Figure 2.2.21 shows the control procedure. Timer 2 interrupt request bit Input pulse ..... X times Start of timer Y count X times 1 ms Stop of timer Y count Note: Frequency = kHz Fig. 2.2.19 How to measure frequency Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 27 of 148 APPLICATION 7641 Group 2.2 Timer CPU mode register A (address 0016) b7 b0 CPMA 000 1 Processor mode bits Stack page select bit Main clock (XIN-XOUT): Oscillating Internal system clock: f(XIN) Clock control register (address 1F16) b7 b0 CCR 0 00000 System clock: f(XIN)/2 Timer 123 mode register (address 2916) b7 b0 T123M 0 001 Timer 1 count: Stopped (Set to “0” after initialization.) Timer 1 count source: φ / 8 Timer 2 count source: Timer 1’s underflow Timers 1, 2 write control: Written at the same time Timer Y mode register (address 2816) b7 b0 TYM 1010 00 Timer Y write control: Written at the same time TYOUT output: Disabled Event counter mode Count at rising edge of CNTR1 Timer Y count: Stopped (Set to “0” after initialization.) Timer 1 (address 2416) b7 b0 T1 4A16 Set “division ratio – 1” = 74 (4A16) Timer 2 (address 2516) b7 b0 T2 0916 Set “division ratio – 1” = 9 (0916) Timer YL (low) (address 2216) b7 b0 TYL FF16 Timer YH (high) (address 2316) b7 b0 Set an initial value. TYH FF16 Interrupt control register B (address 0616) b7 b0 ICONB 10 0 Timer X interrupt: Disabled Timer 1 interrupt: Disabled Timer 2 interrupt: Enabled Port P4 direction register (address 1916) b7 b0 P4D 0 Set to input mode. Fig. 2.2.20 Related registers setting Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 28 of 148 APPLICATION 7641 Group 2.2 Timer RESET q X: This bit is not used here. Set it to “0” or “1” arbitrary. Initialization SEI CPMA (address 0016) CCR (address 1F16),bit7 T123M (address 2916) TYM (address 2816) (address 2416) T1 (address 2516) T2 TYL (address 2216) TYH (address 2316) ICONB (address 0616) IREQB (address 0316) P4D (address 1916),bit4 TYM (address 2816),bit7 T123M (address 2916),bit1 CLI ..... ..... •All interrupts disabled 000X1XXX2 0 0XXX001X2 1010XX002 74 9 FF16 FF16 10X0XXXX2 000000002 0 0 0 •φ = f(XIN)/4 •Event counter mode •Set division ratio so that Timer 2 interrupt will occur at 1 ms intervals. •Timer 2 interrupt enabled, Timer Y interrupt disabled •Set P44/CNTR1 pin to input mode. •Start of Timer Y count •Start of Timer 1 count •Interrupts enabled Timer 2 interrupt process routine T123M (address 2916),bit1 1 •Stop of Timer 1 count CLT (Note 1) CLD (Note 2) Push registers to stack Note 1: When using Index X mode flag (T) Note 2: When using Decimal mode flag (D) •Pushing registers used in interrupt process routine TYM (address 2816),bit7 1 •Stop of Timer Y count (“FFFF16”) – (Timer Y count value) •Input event numbers of P44/CNTR1 pin for 1 ms. TYL TYH (address 2216) (address 2316) FF16 FF16 •Set the low-order and then high-order byte. TYM (address 2816),bit7 0 •Start of Timer Y count Pop registers •Popping registers pushed to stack T123M (address 2916),bit1 0 •Start of Timer 1 count RTI Fig. 2.2.21 Control procedure Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 29 of 148 APPLICATION 7641 Group 2.2 Timer (5) Timer application example 4: Measurement of FG pulse width for motor Outline : The timer X counts the “ H ” l evel width of the pulses input to the P4 3/CNTR 0 p in. Specifications : • The timer X counts the “ H ” l evel width of the FG pulse input to the P43/CNTR0. When f(XIN) = 24 MHz and φ = 6 MHz, the count source is 10.6 µs, which is obtained by dividing the φ b y 64. Measurement can be made up to 1 s in the range of FFFF 16 t o 0000 16. Figure 2.2.22 shows the timers connection and setting of division ratio; Figure 2.2.23 shows the related registers setting; Figures 2.2.24 and 2.2.25 show the control procedure. CCR7 f(XIN) = 24.0 MHz 1/2 1/2 Timer X count source selection φ / 64 1/64 Timer X 1/65536 Timer X interrupt request bit 0/1 700 ms Fig. 2.2.22 Timers connection and setting of division ratios Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 30 of 148 APPLICATION 7641 Group 2.2 Timer Clock control register (address 1F16) b7 b0 CCR 0 00000 System clock: f(XIN)/2 CPU mode register A (address 0016) b7 b0 CPMA 000 1 Processor mode bits Stack page select bit Main clock (XIN-XOUT): Oscillating Internal system clock: f(XIN) Port P4 direction register (address 1916) b7 b0 P4D 0 Set to intput mode. Timer X mode register (address 2716) b7 b0 TXM 10110110 Timer X write control: Written at the same time Timer X count source: φ / 64 Timer X internal clock: φ / n Pulse width measurement mode Measuring “H” pulse Timer X count: Stopped (Set to “1” after initialization.) Timer XL (low) (address 2016) b7 b0 TXL FF16 Timer XH (high) (address 2116) b7 b0 Set 65535 (FFFF16) before start of measuring pulse width. TXH FF16 Interrupt control register B (address 0616) b7 b0 ICONB 1 Timer X interrupt: Enabled Interrupt control register C (address 0716) b7 b0 ICONC 1 CNTR0 interrupt: Enabled Fig. 2.2.23 Relevant registers setting Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 31 of 148 APPLICATION 7641 Group 2.2 Timer RESET q X: This bit is not used here. Set it to “0” or “1” arbitrary. Initialization SEI CCR CPMA P4D TXM TXL TXH ICONB IREQB ICONC IREQC TXM •All interrupts disabled 0 000X1XXX2 0 101101102 FF16 FF16 1 000000002 1 000000002 0 CLI Timer X interrupt process routine (Note 1) Fig. 2.2.24 Control procedure (1) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 ..... (address 1716),bit7 (address 0016) (address 1916),bit3 (address 2716) (address 2016) (address 2116) (address 0616),bit4 (address 0316) (address 0716),bit1 (address 0416) (address 2716),bit7 •Set ting P43/CNTR0 pin to input mode •Timer X: Pulse width measurement mode (Measuring “H” pulse width of input pulses from CNTR0 pin) •Setting Timer X count value •Timer X interrupt: Enabled •CNTR0 interrupt: Enabled •Timer X count start ..... •Interrupts enabled CLT (Note 2) CLD (Note 3) Push registers to stack Notes 1: Timer X interrupt also occurs owing to factors other than measurement level.(CNTR2 input = “L” in this application) Process it by software as error proccesing is performed for measurement level as necessary . CNTR2 input level can be checked by reading the contents of sharing port P83 register. 2: When using Index X mode flag (T) 3: When using Decimal mode flag (D) •Pus hing regis ters u sed in in terrupt process routine Error processing Pop registers •Popping registers pushed to stack RTI page 32 of 148 APPLICATION 7641 Group 2.2 Timer CNTR0 interrupt process routine CLT (Note 1) CLD (Note 2) Push registers to stack Notes 1: When using Index X mode flag (T) 2: When using Decimal mode flag (D) •Pushing registers used in interrupt process routine (A) Measurement result (high-order 8 bits) (A) Measurement result (low-order 8 bits) TXL (address 2016) TXH (address 2116) TXH (A) TXL (A) FF16 FF16 •Count value read and storing it to RAM Read the high-order and then low-order byte. Write to the low-order and then high-order byte. Pop registers •Popping registers pushed to stack RTI Note : The f irst value bec omes invalid d epending on s tart timing of Time X cou nt sh own by the f ollo win g fig ure . Pro ce ss it b y s of twar e a s ne ce ss ar y. [ Example 1] • Start Timer X count when CNTR0 input level is “L”. (CNTR0 input level can be checked by reading the contents of sharing port P43 register. FFFF16 T1 T2 000016 T1 value: Valid CNTR0 Count start of Timer X T2 value: Valid CNTR0 interrupt CNTR0 interrupt [ Example 2] • Start Timer X count when CNTR0 input level is “H”. Invalidate the first CNTR0 interrupt after start of Timer X count. FFFF16 T1 T2 000016 T1 value: Invalid CNTR0 Count start of CNTR0 interrupt Timer X CNTR0 interrupt T2 value: Valid Fig. 2.2.25 Control procedure (2) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 33 of 148 APPLICATION 7641 Group 2.2 Timer (6) Timer application example 5: Adjustment of phase control signal Outline: A phase control signal is adjusted in the period measurement mode. Specifications: • To control the phase of the load, a phase control signal is output to the load. • The pulse width of feedback signal input from the load is measured and a phase control signal for the load is adjusted. Figure 2.2.26 shows the circuit example; Figure 2.2.27 shows the related registers setting; Figure 2.2.28 shows the control procedure. 7641 group P44/CNTR1 Load Port VA C Fig. 2.2.26 Circuit example Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 34 of 148 APPLICATION 7641 Group 2.2 Timer Clock control register (address 1F16) b7 b0 CCR 00000 System clock selection CPU mode register A (address 0016) b7 b0 CPMA 000 1 Processor mode bits Stack page select bit Main clock (XIN-XOUT): Oscillating Internal system clock: f(XIN) Timer Y mode register (address 2816) b7 b0 TYM 11011100 Timer Y write control: Written at the same time TYOUT output: Disabled Timer Y count source: φ / 64 Period measurement mode Measuring period from rising to rising edge of CNTR1 Timer Y count: Stopped (Set to “0” after initialization.) Port P4 direction register (address 1916) b7 b0 P4D 0 Set to intput mode. Timer YL (low) (address 2216) b7 b0 TYL FF16 Timer YH (high) (address 2316) b7 b0 Set an initial value. TYH FF16 Interrupt control register B (address 0616) b7 b0 ICONB 1 Timer Y interrupt: Enabled Interrupt control register C (address 0716) b7 b0 ICONC 1 CNTR1 interrupt: Enabled Fig. 2.2.27 Related registers setting Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 35 of 148 APPLICATION 7641 Group 2.2 Timer RESET q X: This bit is not used here. Set it to “0” or “1” arbitrary. Initialization SEI CCR (address 1F16) CPMA (address 0016) TYM (address 2816) P4D (address 1916),bit4 (address 2216) TYL TYH (address 2316) IREQB (address 0316),bit5 IREQC (address 0416),bit2 ICONB (address 0616),bit5 ICONC (address 0716),bit2 TYM (address 2816),bit7 CLI •All interrupts disabled XXX000002 000X10002 1101XXX02 0 FF16 FF16 0 0 1 1 0 Main processing Phase control process Error processing Notes 1: When using Index X mode flag (T) 2: When using Decimal mode flag (D) Fig. 2.2.28 Control procedure Rev.2.00 Aug 28, 2006 REJ09B0336-0200 ..... •Setting P44/CNTR1 pin to input mode •Setting Timer X count value (Set to the low-order and then high-order byte.) •Clearing Timer Y interrupt request bit •Clearing CNTR1 interrupt request bit •Timer Y interrupt: Enabled •CNTR1 interrupt: Enabled •Timer Y count start •Interrupts enabled ..... ..... Timer Y interrupt process routine CNTR1 interrupt process routine CLT (Note 1) CLD (Note 2) Push registers to stack CLT (Note 1) CLD (Note 2) Push registers to stack Read Timer Y (The high-order first and then low-order byte) ..... Pop registers RTI Pop registers RTI page 36 of 148 APPLICATION 7641 Group 2.2 Timer 2.2.4 Notes on timer (1) Read/Write for timer • The timer division ratio is : 1 / (n + 1) (n = “ 0 ” t o “ 255 ” w ritten into the timer) •Read and write operation on 16-bit timer (Timers X and Y) must be performed for both high and loworder bytes. •When reading the 16-bit timer (Timers X and Y), read the high-order byte first and then the low-order byte. When writing to the 16-bit timer, write the low-order byte first and then the high-order byte. • Do not read the 16-bit timer during the write operation, or do not write to it during the read operation. • When the value is loaded only in the latch, the value is loaded in the timer at the count pulse following the count where the timer reaches “ 00 16” . • In the timers 1 to 3, switching of the count sources of timers 1 to 3 does not affect the values of reload latches. However, that may make count operation started. Therefore, write values again in the order of timers 1, 2 and then timer 3 after their count sources have been switched. •In the timer mode (for timers X, Y, 1 to 3), event counter mode (for timers X, Y), pulse output mode (for timers X, Y, 1, 2), the timer current count value can be read out by reading the timer. •In the pulse width measurement mode (for timer X), period measurement mode (for timer Y), pulse width HL continuously measurement mode (for timer Y), the measured timer value is stored into the internal temporary register. When reading the timer, the value of internal temporary register is read out. The contents of internal temporary register is updated after the next measurement. (2) Pulse output • When using the pulse output mode of timer X, set bit 3 of port P4 direction register to “ 1 ” ( output mode). •When using the TYOUT output of timer Y, set bit 4 of port P4 direction register to “1” (output mode). •When using the TOUT output of timer 1 or timer 2, set bit 1 of port P5 direction register to “1” (output mode). • The T OUT o utput pin is shared with the X COUT p in. Accordingly, when using f(X CIN)/2 as the timer 1 count source (bit 2 of timer 123 mode register = “ 0 ” ), XCOUT o scillation drive must be disabled (bit 5 of clock control register = “ 1 ” ) to input clocks from the X CIN p in. • The P5 1/X COUT/TOUT p in cannot function as an ordinary I/O port while XCIN-XCOUT i s oscillating. When XCIN-X COUT o scillation is stopped or XCOUT o scillation drive is disabled, this can be used as the TOUT output pin of timer 1 or 2. (3) Pulse input • When using the timer X in the event counter or pulse width measurement mode, set bit 3 of port P4 direction register to “ 0 ” ( input mode). •When using the timer Y in the period measurement, event counter or pulse width HL continuously measurement mode, set bit 4 of port P4 direction register to “ 0 ” ( input mode). (4) Interrupt In the timer Y’s pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR 1 pin input signal regardless of the setting of CNTR1 active edge switch bit of timer Y mode register. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 37 of 148 APPLICATION 7641 Group 2.3 Serial I/O 2.3 Serial I/O This paragraph explains the registers setting method and the notes related to the serial I/O. 2.3.1 Memory map Address 000416 000716 Interrupt request register C (IREQC) Interrupt control register C (ICONC) 002A16 002B16 002C16 Serial I/O shift register (SIOSHT) Serial I/O control register 1 (SIOCON1) Serial I/O control register 2 (SIOCON2) Fig. 2.3.1 Memory map of registers related to serial I/O Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 38 of 148 APPLICATION 7641 Group 2.3 Serial I/O 2.3.2 Related registers Serial I/O shift register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O shift register (SIOSHT: address 2A16) b Functions At reset R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 qAt transmitting Writing transmitted data to this register starts transmitting operation. 1 2 qAt receiving Read received data through this register. 3 4 5 6 7 Fig. 2.3.2 Structure of Serial I/O shift register Serial I/O control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O control register 1 (SIOCON1 : address 2B16) b Name b2b1b0 Functions 0 0 0 : Internal clock divided by 2 0 0 1 : Internal clock divided by 4 0 1 0 : Internal clock divided by 8 0 1 1 : Internal clock divided by 16 1 0 0 : Internal clock divided by 32 1 0 1 : Internal clock divided by 64 1 1 0 : Internal clock divided by 128 1 1 1 : Internal clock divided by 256 At reset R W 0 0 Internal synchronous clock select bits (Note) 1 2 3 Serial I/O port select bit 0 0 0 : I/O port 1 : STXD, SCLK signal output 0 : I/O port 4 SRDY output select bit 1 : SRDY signal output 5 Transfer direction select bit 0 : LSB first 1 : MSB first 6 Synchronous clock select 0 : External clock 1 : Internal clock bit 0 : CMOS output 7 STXD output channel 1 : N-channel open drain output control bit Note: The source of serial I/O internal synchronous clock can be selected by I/O control register 2 0 0 0 1 0 bit 1 of serial Fig. 2.3.3 Structure of Serial I/O control register 1 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 39 of 148 APPLICATION 7641 Group 2.3 Serial I/O Serial I/O control register 2 b7 b6 b5 b4 b3 b2 b1 b0 000 Serial I/O control register 2 (SIOCON2 : address 2C16) b Name Functions 0 : Normal serial I/O mode 1 : SPI compatible mode (Note) 0:φ 1 : SCSGCLK 0 : SRXD input disabed 1 : SRXD input enabed 0 : SCLK starting at “L” 1 : SCLK starting at “H” 0 : Serial transfer starting at falling edge of SRDY 1 : Serial transfer starting after a half cycle of SCLK passed at falling edge of SRDY At reset R W 0 0 0 1 1 0 SPI mode select bit 1 Serial I/O internal clock select bit 2 SRXD input enable bit 3 Clock polarity select bit (CPoL) 4 Clock phase select bit (CPha) 0 5 Fix these bits to “0”. 0 6 7 0 Note: To set the slave mode, also set bit 4 of serial I/O control register 1 to “1”. Fig. 2.3.4 Structure of Serial I/O control register 2 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 40 of 148 APPLICATION 7641 Group 2.3 Serial I/O Interrupt request register C b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register C (IREQC : address 0416) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 ✽ ✽ ✽ ✽ ✽ ✽ ✽ 0 Timer 3 interrupt request bit 1 CNTR0 interrupt request bit 2 CNTR1 interrupt request bit 3 Serial I/O interrupt request bit 4 Input buffer full interrupt request bit 5 Output buffer empty interrupt request bit 6 Key input interrupt request bit 7 Fix this bit to “0”. ✽: “0” can be set by software, but “1” cannot be set. Fig. 2.3.5 Structure of Interrupt request register C Interrupt control register C b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt control register C (ICONC : address 0716) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 Timer 3 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 1 CNTR0 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 2 CNTR1 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 3 Serial I/O interrupt enable bit 4 Input buffer full interrupt enable bit 5 Output buffer empty interrupt enable bit 6 Key input interrupt enable bit 7 Fix this bit to “0”. 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Fig. 2.3.6 Structure of Interrupt control register C Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 41 of 148 APPLICATION 7641 Group 2.3 Serial I/O 2.3.3 Serial I/O connection examples (1) Control of peripheral IC equipped with CS pin Figure 2.3.7 shows connection examples of a peripheral IC equipped with the CS pin. (1) Only transmission (Using the SRXD pin as an I/O port) Port SCLK STXD (2) Transmission and reception CS CLK DATA Port SCLK STXD SRXD 7641 group CS CLK IN OUT Peripheral IC (E 2 PROM etc.) 7641 group Peripheral IC (OSD controller etc.) (3) Transmission and reception (When connecting SRXD with STXD) (When connecting IN with OUT in peripheral IC) Port SCLK STXD SRXD CS CLK IN OUT (4) Connection of plural IC Port SCLK STXD SRXD Port 7641 group CS CLK IN OUT Peripheral IC 1 7641 group✽1 Peripheral IC✽2 (E2 PROM etc.) ✽1: ✽2: Select an N-channel open-drain output for STXD pin output control. Use the OUT pin of peripheral IC which is an N-channel opendrain output and becomes high impedance during receiving data. CS CLK IN OUT Peripheral IC 2 Notes : “Port” means an output port controlled by software. Fig. 2.3.7 Serial I/O connection examples (1) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 42 of 148 APPLICATION 7641 Group 2.3 Serial I/O (2) Connection with microcomputer Figure 2.3.8 shows connection examples with another microcomputer. (1) Selecting internal clock (2) Selecting external clock SCLK STXD SRXD 7641 group CLK IN OUT Microcomputer SCLK STXD SRXD 7641 group CLK IN OUT Microcomputer (3) Using SRDY signal output function (Selecting an external clock) SRDY SCLK STXD SRXD 7641 group RDY CLK IN OUT Microcomputer Fig. 2.3.8 Serial I/O connection examples (2) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 43 of 148 APPLICATION 7641 Group 2.3 Serial I/O 2.3.4 Serial I/O application example (1) Output of serial data (control of peripheral IC) Outline : Serial communication is performed, connecting port to CS pin of peripheral IC. To perform reception, it needs to write dummy data into serial I/O shift register. Figure 2.3.9 shows a connection diagram, and Figure 2.3.10 shows a timing chart. P31 P81/SCLK P83/STXD CS CLK DATA CS CLK DATA 7641 group Peripheral IC Fig. 2.3.9 Connection diagram Specifications : • Synchronous clock frequency : 187.5 kHz (f(XIN) = 24 MHz ) • Transfer direction : LSB first • Serial I/O interrupt is not used. • Port P31 is connected to the CS pin (“L” active) of the peripheral IC for transmission control; the output level of port P31 i s controlled by software. CS CLK DATA DATA0 DATA1 DATA2 DATA3 Fig. 2.3.10 Timing chart Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 44 of 148 APPLICATION 7641 Group 2.3 Serial I/O Figure 2.3.11 shows the registers setting for the transmitter, and Figure 2.3.12 shows a setting of serial I/O transmission data. Serial I/O control register 1 (Address : 2B16) b7 b0 SIOCON1 01001100 Internal synchronous clock : Internal clock/32 STXD, SCLK output selected SRDY output selected LSB first Synchronous clock : Internal clock STXD pin : CMOS output Serial I/O control register 2 (Address : 2C16) b7 b0 SIOCON2 00011100 Normal serial I/O mode Serial I/O internal clock : φ SRXD input enabled Port P3 (Address : 0E16) b7 b0 P3 1 Set P31 output level to “H”. Port P3 direction register (Address : 0F16) b7 b0 P3D 1 Set P31 to output mode. Interrupt control register C (Address : 0716) b7 b0 ICONC 0 Serial I/O interrupt : Disabled Fig. 2.3.11 Registers setting for transmitter Serial I/O shift register (Address : 2A16) b7 b0 SIOSHT Set a transmission data. Confirm that transmission of the previous data is completed (Serial I/O interrupt request bit is “1”) before writing data. Fig. 2.3.12 Setting of serial I/O transmission data Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 45 of 148 APPLICATION 7641 Group 2.3 Serial I/O When the registers are set as shown in Figure 2.3.13, the serial I/O can transmit 1-byte data by writing data into the serial I/O shift register. Thus, after setting the CS signal to “L”, write the transmission data to the serial I/O shift register by each 1 byte, and return the CS signal to “H” when all required data have been transmitted. Figure 2.3.13 shows a control procedure of transmitter. RESET Initialization SIOCON1 SIOCON2 P3 P3D IREQC ICONC CLI q x: This bit is not used here. Set it to “0” or “1” arbitrarily. SIOSHT (Address : 2A16) .... (Address : 2B16) 010011002 (Address : 2C16) 000111002 (Address : 0E16), bit1 1 (Address : 0F16), bit1 1 (Address : 0416), bit3 0 (Address : 0716), bit3 0 •Serial I/O set •CS signal output port set (“H” level output) •Serial I/O interrupt request bit set to “0” •Serial I/O interrupt disabled .... P3 (Address : 0E16), bit1 0 •CS signal output level to “L” set Transmission data •Transmission data write (Start of transmit 1-byte data) IREQC (Address : 0416), bit3? 1 0 •Judgment of completion of transmitting 1-byte data IREQC (Address : 0416), bit3 0 N Complete to transmit all data? Y •Return the CS signal output level to “H” when transmission of all data is completed •Use any of RAM area as a counter for counting the number of transmitted bytes •Judgment of completion of transmitting all data P3 (Address : 0E16), bit1 1 Fig. 2.3.13 Control procedure of transmitter Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 46 of 148 APPLICATION 7641 Group 2.3 Serial I/O (2) Serial communication using SPI compatible mode q Explanation of SPI compatible mode Setting the SPI mode select bit (bit 0 of SIOCON2) to “ 1 ” p uts the serial I/O in SPI compatible mode. The synchronous clock select bit (bit 6 of SIOCON1) determines whether the serial I/O is an SPI master or slave. When the external clock is selected (“0”), the serial I/O is in slave mode; when the internal clock is selected ( “ 1 ” ), the serial I/O is in master mode. In SPI compatible mode the SRXD pin functions as a MISO (Master In/Slave Out) pin and the STXD pin functions as a MOSI (Master Out/Slave In) pin. In slave mode the transmit data is output from the MISO pin and the receive data is input from the MISO pin. The SRDY pin functions as the chip-select signal input pin from an external. In master mode the transmit data is output from the MOSI pin and the receive data is input from the MISO pin. The SRDY pin functions as the chip-select signal output pin to an external. q Slave mode operation In slave mode of SPI compatible mode 4 types of clock polarity and clock phase can be usable by bits 3 and 4 of serial I/O control register 2. If the SRDY pin is held “ H ” , the shift clock is inhibited, the serial I/O counter is set to “ 7 ” . If the SRDY pin is held “ L ” , then the shift clock will start. Make sure during transfer to maintain the SRDY input at “ L ” a nd not to write data to the serial I/O counter. Outline : Serial communication is performed between 7641 group MCUs, using SPI compatible mode. Specifications : • Synchronous clock frequency : 187.5 kHz (f(X IN) = 24 MHz ) • Transfer direction : LSB first Figure 2.3.14 shows a connection diagram; Figure 2.3.15 shows the registers setting for SPI compatible mode; Figures 2.3.16 and 2.3.17 show a control procedure of SPI compatible mode. Slave unit P80/UTXD2/SRDY P81/URXD2/SCLK P82/CTS2/MISO P83/RTS2/MOSI 7641 group Fig. 2.3.14 Connection diagram Master unit CS CLK DATA DATA P80/UTXD2/SRDY P81/URXD2/SCLK P82/CTS2/MISO P83/RTS2/MOSI 7641 group Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 47 of 148 APPLICATION 7641 Group 2.3 Serial I/O qSlave Unit Serial I/O control register 1 (Address : 2B16) b7 b0 SIOCON1 00011 STXD, SCLK output selected SRDY output selected LSB first Synchronous clock : External clock STXD pin : CMOS output Serial I/O control register 2 (Address : 2C16) b7 b0 SIOCON2 000111 1 SPI compatible mode SRXD input enabled SCLK starting at “H” Serial transfer starting afer a half cycle of SCLK passed at falling edge of SRDY Interrupt control register C (Address : 0716) b7 b0 ICONC 0 Serial I/O interrupt : Disabled qMaster Unit Serial I/O control register 1 (Address : 2B16) b7 b0 SIOCON1 01001100 Internal synchronous clock : Internal clock/32 STXD, SCLK output selected No SRDY output LSB first Synchronous clock : Internal clock STXD pin : CMOS output Serial I/O control register 2 (Address : 2C16) b7 b0 SIOCON2 00011100 SPI compatible mode Serial I/O internal clock : φ SRXD input enabled SCLK starting at “H” Serial transfer starting afer a half cycle of SCLK passed at falling edge of SRDY Interrupt control register C (Address : 0716) b7 b0 ICONC 0 Serial I/O interrupt : Disabled Fig. 2.3.15 Registers setting for SPI compatible mode Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 48 of 148 APPLICATION 7641 Group 2.3 Serial I/O Slave Unit RESET Initialization SIOCON1 (Address : 2B16) SIOCON2 (Address : 2C16) IREQC ICONC CLI q x: This bit is not used here. Set it to “0” or “1” arbitrarily. SIOSHT (Address : 2A16) Read out received data from SIOSHT (Address : 2A16) Fig. 2.3.16 Control procedure of SPI compatible mode in slave Rev.2.00 Aug 28, 2006 REJ09B0336-0200 .... 00011XXX2 000111X12 0 0 •Serial I/O set .... (Address : 0416), bit3 (Address : 0716), bit3 •Serial I/O interrupt request bit set to “0” •Serial I/O interrupt disabled .... Transmission data •Transmission data write (Do not set data during data reception.) IREQC (Address : 0416), bit3? 1 0 •Judgment of completion of receiving 1-byte data •Transmission/Reception starts owing to “L” input to P80/UTXD2/SRDY pin or shift clock input. IREQC (Address : 0416), bit3 0 page 49 of 148 APPLICATION 7641 Group 2.3 Serial I/O Master Unit RESET Initialization SIOCON1 SIOCON2 IREQC ICONC CLI .... .... q x: This bit is not used here. Set it to “0” or “1” arbitrarily. (Address : 2B16) 010111012 (Address : 2C16) 000111012 (Address : 0416), bit3 0 (Address : 0716), bit3 0 •Serial I/O set •Serial I/O interrupt request bit set to “0” •Serial I/O interrupt disabled SIOSHT (Address : 2A16) Transmission data •Transmission data write (Start of transmit 1-byte data) •Then P80/UTXD2/SRDY pin set to “L” IREQC (Address : 0416), bit3? 1 Read out received data from SIOSHT (Address : 2A16) 0 •Judgment of completion of transmitting 1-byte data •“L” output from P80/UTXD2/SRDY pin IREQC (Address : 0416), bit3 0 N Complete to transmit all data? Y •Use any of RAM area as a counter for counting the number of transmitted bytes •Judgment of completion of transmitting all data Fig. 2.3.17 Control procedure of SPI compatible mode in master Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 50 of 148 APPLICATION 7641 Group 2.3 Serial I/O 2.3.5 Notes on serial I/O (1) Clock When the external clock is selected as the transfer clock, its transfer clock needs to be controlled by the external source because the serial I/O shift register will keep being shifted while transfer clock is input even after transfer completion. (2) Reception When the external clock is selected as the transfer clock for reception, the receiving operation will start owing to the shift clock input even if write operation to the serial I/O shift register (SIOSHT) is not performed. The serial I/O interrupt request also occurs at completion of receiving. However, we recommend to write dummy data in the serial I/O shift register. Because this will cause followings and improve transfer reliability. • Write to SIOSHT puts the SRDY pin to “ L ” . This enables shift clock output of an external device. • Write to SIOSHT clears the internal serial I/O counter. Note: Do not read the serial I/O shift register which is shifting. Because this will cause incorrect-data read. (3) STXD output •When the internal clock is selected as the transfer clock, the STXD pin goes a high-impedance state after transfer completion. • When the external clock is selected as the transfer clock, the STXD pin does not go a highimpedance state after transfer completion. (4) SPI compatible mode • When using the SPI compatible mode, set the SRDY select bit to “ 1 ” ( SRDY signal output). • When the external clock is selected in SPI compatible mode, the SRXD pin functions as a data output pin and the STXD pin functions as a data input pin. •Do not write to the serial I/O shift register (SIOSHT) during a transfer as slave when in SPI compatible mode. • Master operation of SPI compatible mode requires the timings: -From write operation to the SIOSHT to SRDY pin put to “ L ” Requires 2 cycles of internal clock φ + 2 c ycles of serial I/O synchronous clock + 35 ns -From SRDY pin put to “ L ” t o SCLK switch Requires 35 ns -From the last pulse of SCLK to SRDY pin put to “ H ” Requires 35 ns. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 51 of 148 APPLICATION 7641 Group 2.4 UART 2.4 UART This paragraph explains the registers setting method and the notes related to the UART. 2.4.1 Memory map Address 000216 000316 000516 000616 003016 003116 003216 003316 003416 003516 003616 Interrupt request register A (IREQA) Interrupt request register B (IREQB) Interrupt control register A (ICONA) Interrupt control register B (ICONB) UART1 mode register (U1MOD) UART1 baud rate generator (U1BRG) UART1 status register (U1STS) UART1 control register (U1CON) UART1 transmit/receive buffer register 1 (U1TRB1) UART1 transmit/receive buffer register 2 (U1TRB2) UART1 RTS control register (U1RTSC) 003816 003916 003A16 003B16 003C16 003D16 003E16 UART2 mode register (U2MOD) UART2 baud rate generator (U2BRG) UART2 status register (U2STS) UART2 control register (U2CON) UART2 transmit/receive buffer register 1 (U2TRB1) UART2 transmit/receive buffer register 2 (U2TRB2) UART2 RTS control register (U2RTSC) Fig. 2.4.1 Memory map of registers related to UART Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 52 of 148 APPLICATION 7641 Group 2.4 UART 2.4.2 Related registers UARTx mode register b7 b6 b5 b4 b3 b2 b1 b0 UARTx (x = 1, 2) mode register (UxMOD : addresses 3016, 3816) b Name Functions 0:φ 1 : SCSGCLK output b2b1 At reset R W 0 0 0 0 0 0 0 0 0 UART clock select bit (CLK) 1 UART clock prescaling select bits (PS) 2 3 Stop bit length select bit (STB) 4 Parity select bit (PMD) 5 Parity enable bit (PEN) 6 UART character length select bit (LE1, 0) 7 0 0 : UART clock divided by 1 0 1 : UART clock divided by 8 1 0 : UART clock divided by 32 1 1 : UART clock divided by 256 0 : 1 stop bit 1 : 2 stop bits 0 : Even parity 1 : Odd parity 0 : Parity checking disabled 1 : Parity checking enabled b7b6 0 0 : 7 bits 0 1 : 8 bits 1 0 : 9 bits 1 1 : Not available Fig. 2.4.2 Structure of UARTx (x = 1, 2) mode register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 53 of 148 APPLICATION 7641 Group 2.4 UART UARTx control register b7 b6 b5 b4 b3 b2 b1 b0 UARTx (x = 1, 2) control register (UxCON : addresses 3316, 3B16) b Name Functions 0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled 0 : No action 1 : Initializing (Note 1) 0 : No action 1 : Initializing (Note 2) 0 : Interrupt when transmit buffer has emptied 1 : Interrupt when transmit shift operation is completed 0 : CTS function disabled (Note 3) 1 : CTS function enabled 0 : RTS function disabled (Note 4) 1 : RTS function enabled 0 : Address mode disabled 1 : Address mode enabled At reset R W 0 0 0 0 0 0 Transmit enable bit (TEN) 1 Receive enable bit (REN) 2 Transmit initialization bit (TIN) 3 Receive initialization bit (RIN) 4 Transmit interrupt source select bit (TIS) 5 CTS function enable bit (CTS_SEL) 6 RTS function enable bit (RTS_SEL) UART address mode 7 enable bit (AME) 0 0 0 Notes 1: When setting the TIN bit to “1”, the TEN bit is set to “0” and the UARTx status register will be set to “0316” after the data has been transmitted. To retransmit, set the TEN bit to “1” and set a data to the transmit buffer register again. The TIN bit will be cleared to “0” one cycle later after the TIN bit has been set to “1”. 2: Setting the RIN bit to “1” suspends the receiving operation and will set all of the REN, RBF and the receive error flags (PER, FER, OER, SER) to “0”. The RIN bit will be cleared to “0” one cycle later after the RIN bit has been set to “1”. 3: When CTS function is disabled (CTS_SEl = “0”), pins P82 and P86 can be used as ordinary I/O ports. 4: When RTS function is disabled (RTS_SEl = “0”), pins P83 and P87 can be used as ordinary I/O ports. Fig. 2.4.3 Structure of UARTx (x = 1, 2) control register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 54 of 148 APPLICATION 7641 Group 2.4 UART UARTx status register b7 b6 b5 b4 b3 b2 b1 b0 UARTx (x = 1, 2) status register (UxSTS : addresses 3216, 3A16) b Name Functions At reset R W 1 1 0 0 0 0 0 0 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ 0 Transmit complete flag (TCM) 1 Transmit buffer empty flag (TBE) 2 Receive buffer full flag (RBF) 3 4 5 6 7 0 : Transmit shift in progress 1 : Transmit shift completed 0 : Buffer full 1 : Buffer empty 0 : Buffer empty 1 : Buffer full 0 : No error Parity error flag (PER) 1 : Parity error Framing error flag (FER) 0 : No error 1 : Framing error 0 : No error Overrun error flag (OER) 1 : Overrun error Summing error flag (SER) 0 : (PER) U (FER) U (OER) = 0 1 : (PER) U (FER) U (OER) = 1 Nothing is arranged for this bit. This is a write disable bit. When this bit is read out, the contents are “0”. Fig. 2.4.4 Structure of UARTx (x = 1, 2) status register UARTx RTS control register b7 b6 b5 b4 b3 b2 b1 b0 0000 UARTx (x = 1, 2) RTS control register (UxRTSC : addresses 3616, 3E16) b Name Functions At reset R W 0 0 0 0 0 0 Fix these bits to “0”. 1 2 3 4 RTS assertion delay count select bits (RTS) b7b6b5b4 5 6 7 0 0 0 0 : No delay; Assertion immediately 0 0 0 1 : 8-bit term assertion at “H” 0 0 1 0 : 16-bit term assertion at “H” 0 0 1 1 : 24-bit term assertion at “H” 0 1 0 0 : 32-bit term assertion at “H” 0 1 0 1 : 40-bit term assertion at “H” 0 1 1 0 : 48-bit term assertion at “H” 0 1 1 1 : 56-bit term assertion at “H” 1 0 0 0 : 64-bit term assertion at “H” 1 0 0 1 : 72-bit term assertion at “H” 1 0 1 0 : 80-bit term assertion at “H” 1 0 1 1 : 88-bit term assertion at “H” 1 1 0 0 : 96-bit term assertion at “H” 1 1 0 1 : 104-bit term assertion at “H” 1 1 1 0 : 112-bit term assertion at “H” 1 1 1 1 : 120-bit term assertion at “H” 0 0 1 Fig. 2.4.5 Structure of UARTx (x = 1, 2) RTS control register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 55 of 148 APPLICATION 7641 Group 2.4 UART UARTx baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 UARTx (x = 1, 2) baud rate generator (UxBRG: addresses 3116, 3916) b Functions At reset R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 qThe UxBRG determines the baud rate for transfer. 1 qThis is a 8-bit counter with its reload register. This generator divides the frequency of the count source by 1/(n + 1), where “n” is the 2 value written to the UxBRG. 3 4 5 6 7 Fig. 2.4.6 Structure of UARTx (x = 1, 2) baud rate generator Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 56 of 148 APPLICATION 7641 Group 2.4 UART UARTx transmit/receive buffer registers 1, 2 b7 b6 b5 b4 b3 b2 b1 b0 UARTx (x = 1, 2) transmit/receive buffer register 1 (UxTRB1: addresses 3416, 3C16) b 0 1 2 3 4 5 6 Functions The transmit buffer register and the receive buffer register are located at the same address. Writing a transmitting data and reading a received data are performed through the UxTRB. This is its low-order byte. •At write The data is written into the transmit buffer register. It is not done into the receive buffer register. •At read The contents of receive buffer register is read. If a character bit length is 7 bits, the MSB of received data is invalid. At reset R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 Note that the contents of transmit buffer register cannot be read. b7 b6 b5 b4 b3 b2 b1 b0 UARTx (x = 1, 2) transmit/receive buffer register 2 (UxTRB2: addresses 3516, 3D16) b Functions At reset R W 0 The transmit buffer register and the receive buffer register are located Undefined at the same address. Writing a transmitting data and reading a received data are performed through the UxTRB. This is its highorder byte. •At write The data is written into the transmit buffer register. It is not done into the receive buffer register. •At read The contents of receive buffer register is read. If a character bit length is 9 bits, the received high-order 7 bits of UxTRB2 are “0” Note that the contents of transmit buffer register cannot be read. If a character bit length is 7 or 8 bits, the received contents of UxTRB2 are invalid. 1 Nothing is arranged for this bit. This is a write disable bit. When this Undefined 2 bit is read out, the contents are “0”. Undefined 3 Undefined 4 Undefined 5 Undefined 6 Undefined 7 Undefined ✕ ✕ ✕ ✕ ✕ ✕ ✕ Fig. 2.4.7 Structure of UARTx (x = 1, 2) transmit/receive buffer registers 1, 2 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 57 of 148 APPLICATION 7641 Group 2.4 UART Interrupt request register A b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register A (IREQA : address 0216) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ 0 USB function interrupt request bit 1 USB SOF interrupt request 0 : No interrupt request issued bit 1 : Interrupt request issued 0 : No interrupt request issued 2 INT0 interrupt request bit 1 : Interrupt request issued 3 INT1 interrupt request bit 4 DMAC0 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 5 DMAC1 interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit 6 UART1 receive buffer full 0 : No interrupt request issued 1 : Interrupt request issued interrupt request bit 7 UART1 transmit interrupt 0 : No interrupt request issued request bit 1 : Interrupt request issued ✽: “0” can be set by software, but “1” cannot be set. Fig. 2.4.8 Structure of Interrupt request register A Interrupt request register B b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register B (IREQB : address 0316) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ 0 UART1 summing error interrupt request bit 1 UART2 receive buffer full interrupt request bit 2 UART2 transmit interrupt request bit 3 UART2 summing error interrupt request bit 4 Timer X interrupt request bit 5 Timer Y interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit 6 Timer 1 receive buffer full 0 : No interrupt request issued 1 : Interrupt request issued interrupt request bit 7 Timer 2 transmit interrupt 0 : No interrupt request issued request bit 1 : Interrupt request issued ✽: “0” can be set by software, but “1” cannot be set. Fig. 2.4.9 Structure of Interrupt request register B Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 58 of 148 APPLICATION 7641 Group 2.4 UART Interrupt control register A b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register A (ICONA : address 0516) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 0 0 0 0 0 0 USB function interrupt enable bit 1 USB SOF interrupt enable 0 : Interrupt disabled bit 1 : Interrupt enabled 0 : Interrupt disabled INT0 interrupt enable bit 2 1 : Interrupt enabled 3 INT1 interrupt enable bit 4 DMAC0 interrupt enable bit 5 DMAC1 interrupt enable bit 6 UART1 receive buffer full interrupt enable bit 7 UART1 transmit interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Fig. 2.4.10 Structure of Interrupt control register A Interrupt control register B b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register B (ICONB : address 0616) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 0 0 0 0 0 0 UART1 summing error interrupt enable bit 1 UART2 receive buffer full interrupt enable bit 2 UART2 transmit interrupt enable bit 3 UART2 summing error interrupt enable bit 4 Timer X interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 5 Timer Y interrupt enable 1 : Interrupt enabled bit 6 Timer 1 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 7 Timer 2 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled Fig. 2.4.11 Structure of Interrupt control register B Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 59 of 148 APPLICATION 7641 Group 2.4 UART 2.4.3 UART transfer data format Figure 2.4.12 shows the UART transfer data format. 1ST-9DATA-1SP ST LSB MSB SP 1ST-8DATA-1SP ST LSB MSB SP 1ST-7DATA-1SP ST LSB MSB SP 1ST-9DATA-1PAR-1SP ST LSB MSB PAR SP 1ST-8DATA-1PAR-1SP ST LSB MSB PAR SP 1ST-7DATA-1PAR-1SP UART ST LSB MSB PAR SP 1ST-9DATA-2SP ST LSB MSB 2SP 1ST-8DATA-2SP ST LSB MSB 2SP 1ST-7DATA-2SP ST LSB MSB 2SP 1ST-9DATA-1PAR-2SP ST LSB MSB PAR 2SP 1ST-8DATA-1PAR-2SP ST LSB MSB PAR 2SP 1ST-7DATA-1PAR-2SP ST LSB MSB PAR 2SP Fig. 2.4.12 UART transfer data format Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 60 of 148 APPLICATION 7641 Group 2.4 UART 2.4.4 Transfer bit rate UART1 and UART2 can use either internal clock φ or SCSGCLK (Special Count Source Generator output) as its clock. (1) Setting examples using internal clock φ Table 2.4.1 shows setting examples of the baud rate generator (BRG) values and transfer bit rate values. Table 2.4.1 Setting examples of baud rate generator values and transfer bit rate values (φ = 12 MHz)) φ /1 ( Note 1 ) BRG setting Transfer value 00 (00 16) 01 (01 16) 02 (02 16) 03 (03 16) 04 (04 16) 05 (05 16) 06 (06 16) 07 (07 16) 08 (08 16) 09 (09 16) 10 (0A 16) 11 (0B 16) 12 (0C 16) 13 (0D 16) 14 (0E 16) 15 (0F 16) ○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○ φ/8 ( Note 1 ) BRG setting Transfer bit rate (bps) value φ /32 ( Note 1 ) BRG setting Transfer bit rate (bps) value φ /32 ( Note 1 ) BRG setting Transfer bit rate (bps) bit rate (bps) value 750,000.0 375,000.0 250,000.0 187,500.0 150,000.0 125,000.0 107,142.9 93,750.0 83,333.3 75,000.0 68,181.8 65,250.0 57,692.3 53,571.4 50,000.0 46,875.0 ○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○ 00 (00 16) 01 (01 16) 02 (02 16) 03 (03 16) 04 (04 16) 05 (05 16) 06 (06 16) 07 (07 16) 08 (08 16) 09 (09 16) 10 (0A 16) 11 (0B 16) 12 (0C 16) 13 (0D 16) 14 (0E 16) 15 (0F 16) ○○○○○○○○○○○○○○○○○○ 93,750.0 46,875.0 31,250.0 23,437.5 18,750.0 15,625.0 13,392.8 11,718.7 10,416.6 9,375.0 8,522.7 7,812.5 7,211.5 6,696.4 6,250.0 5,859.3 ○○○○○○○○○○○○○○○○○○ 00 (00 16) 01 (01 16) 02 (02 16) 03 (03 16) 04 (04 16) 05 (05 16) 06 (06 16) 07 (07 16) 08 (08 16) 09 (09 16) 10 (0A 16) 11 (0B 16) 12 (0C 16) 13 (0D 16) 14 (0E 16) 15 (0F 16) ○○○○○○○○○○○○○ 23,437.5 11,718.7 7,812.5 5,859.4 4,687.5 3,906.3 3,348.2 2,929.7 2,604.2 2,343.7 2,130.6 1,953.1 1,802.8 1,674.1 1,562.5 1,464.8 ○○○○○○○○○○○○○ 00 (00 16) 01 (01 16) 02 (02 16) 03 (03 16) 04 (04 16) 05 (05 16) 06 (06 16) 07 (07 16) 08 (08 16) 09 (09 16) 10 (0A 16) 11 (0B 16) 12 (0C 16) 13 (0D 16) 14 (0E 16) 15 (0F 16) ○○ 2,929.7 1,464.8 976.6 732.4 585.9 488.3 418.5 366.2 325.5 292.9 266.3 244.1 225.3 209.2 195.3 183.1 ○○ 253 (FD 16) 254 (FE 16) 255 (FF 16) 2,952.7 2,941.1 2,929.7 253 (FD16) 254 (FE 16) 255 (FF 16) 369.0 367.6 366.2 253 (FD 16) 254 (FE 16) 255 (FF 16) 92.2 91.9 91.6 253 (FD 16) 254 (FE 16) 255 (FF 16) 11.5 11.4 11.4 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 61 of 148 APPLICATION 7641 Group 2.4 UART Notes 1: S elect the UART clock prescaling with bits 1 and 2 of UARTx mode register. 2: E quation of transfer bit rate: Transfer bit rate (bps) = fi ✽ (BRG setting value + 1) ✕ 1 6 ✽ : fi is selectable among φ /1, φ /8, φ /32, and φ/256 with bits 1 and 2 of UARTx mode register. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 62 of 148 APPLICATION 7641 Group 2.4 UART (2) Setting examples using SCSGCLK output Table 2.4.2 shows setting examples of the SCSG1, SCSG2 and the baud rate generator (BRG) values and transfer bit rate values. Table 2.4.2 Setting examples of SCSG1, SCSG2 and baud rate generator values and transfer bit rate values (φ = 1 2 MHz)) Transfer bit rate (bps) ( Note 1) 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 14400 19200 28800 31250 38400 57600 115200 Special Count Source Generator SCSG1 setting value ( Note 3 ) bypassed bypassed 78 (4E16) 172 (AC 16) bypassed bypassed 24 (18 16) bypassed 24 (18 16) bypassed 24 (18 16) 24 (18 16) 24 (18 16) 24 (18 16) 24 (18 16) 24 (18 16) 35 (23 16) 24 (18 16) bypassed 35 (23 16) bypassed 11 (0B16) SCSG2 setting value 149 (95 16) 99 (63 16) 67 (43 16) 55 (37 16) 49 (31 16) 24 (18 16) 11 (0B 16) 24 (18 16) 19 (13 16) 24 (18 16) 19 (13 16) 19 (13 16) 14 (0E6) 19 (13 16) 14 (0E6) 09 (09 16) 00 (00 16) 00 (00 16) bypassed 00 (00 16) bypassed 00 (00 16) UART clock SCSGCLK prescaling (Hz) (Note 4 ) ( Note 2) 1/1 80000.00 1/1 120000.00 174236.78 213047.07 240000.00 480000.00 960000.00 480000.00 576000.00 480000.00 576000.00 576000.00 768000.00 576000.00 768000.00 1152000.00 11666666.66 11520000.00 12000000.00 11666666.66 12000000.00 11000000.00 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 BRG setting value 99 (63 16) 99 (63 16) 98 (62 16) 98 (62 16) 99 (63 16) 99 (63 16) 99 (63 16) 24 (18 16) 19 (13 16) 14 (0E 6) 14 (0E 6) 9 (09 16) 9 (09 16) 4 (04 16) 4 (04 16) 4 (04 16) 37 (25 16) 24 (18 16) 23 (17 16) 18 (12 16) 12 (0C 16) 5 (05 16) Real rate (bps) 50.00 75.00 110.00 134.50 150.00 300.00 600.00 1200.00 1800.00 2000.00 2400.00 3600.00 4800.00 7200.00 9600.00 14400.00 19188.60 28800.00 31250.00 38377.19 57692.31 114583.33 Notes 1: E quation of transfer bit rate: Transfer bit rate (bps) = fi✽ (BRG setting value + 1) ✕ 1 6 ✽ : fi is selectable among SCSGCLK/1, SCSGCLK/8, SCSGCLK/32, and SCSGCLK/256 with bits 1 and 2 of UARTx mode register. 2: S elect the UART clock prescaling with bits 1 and 2 of UARTx mode register. 3: T he internal clock φ i s used as the SCSG2 count source when the SCSG1 count stop bit is “ 1 ” or the SCSG1 timer set value is “ 00 16” . 4: E quation of SCSGCLK frequency: SCSGCLK (MHz) = φ ✕ SCSG1 setting value ✕ (SCSG1 setting value + 1) 1 (SCSG2 setting value + 1) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 63 of 148 APPLICATION 7641 Group 2.4 UART 2.4.5 Operation of transmitting and receiving (1) Transmit operation • The transmit buffer empty flag (TBE) is set to “ 0 ” w hen the low-order byte of transmitted data is written into the UARTx (x = 1, 2) transmit buffer register 1 in the condition of transmission enabled. When using 9-bit character length, set the data into the UARTx transmit buffer register 2 (high-order byte) first before the UARTx transmit buffer register 1 (low-order byte). •If the transmit shift register is empty in the condition of CTS function disabled, the transmitted data which is written into the UARTx (x = 1, 2) transmit buffer register 1 will be transferred to the transmit shift register at the same time. When the TBE flag becomes “ 1 ” , the following data can be set to the UARTx (x = 1, 2) transmit buffer. At this point, the UART transmit interrupt request occurs when the transmit interrupt source select bit (TIS) is “ 0 ” . • When the CTS function is enabled, the transmitted data is not transferred to the transmit shift register until “ L ” i s input to the CTSx pin (P8 6/CTS 1, P82/CTS 2/SRXD). •The data is transmitted with the LSB first format. Once the transmission starts, it continues until the last bit has been transmitted even though clearing the transmit enable bit (TEN) to “ 0 ” ( disabled) or inputting “ H ” t o the CTSx pin. • After completion of the last bit transmitting, if the TBE flag is “ 1 ” , or the TEN bit is “ 0 ” ( disabled) or “ H ” i s input to the CTSx pin, the transmit complete flag (TCM) goes to “ 1 ” . At this point, the UARTx transmit interrupt request occurs when the TIS bit is “ 1 ” . (2) Receive operation • The data is received with the LSB first format in the condition of reception enabled. •When the stop bit is detected, the received data is transferred from the receive shift register to the UARTx (x = 1, 2) receive buffer register. At the same time, if there is no error, the receive buffer full flag (RBF) is set to “ 1 ” a nd the UARTx receive buffer full interrupt request occurs. •If receive errors occur, the corresponding error flags of UARTx status register are set to “1” and the UARTx summing error interrupt request occurs. • The receive buffer full flag (RBF) is set to “ 0 ” w hen the contents of UARTx receive buffer register 1 is read out. Then when the RTS function is disabled, the following data can be received. When using 9-bit character length, read the data from the UARTx receive buffer register 2 (highorder byte) first before the UARTx receive buffer register 1 (low-order byte). •When the RTS function is enabled, the RTS assertion delay count is specified by the UARTx RTS control register. The delay time from the reception of the last stop bit to the start bit is selectable. The RTSx pin (P87/RTS1, P83/RTS2/STXD) outputs “H” during the delayed time. After that, the RTSx pin outputs “ L ” a nd a reception is enabled. •If the start bit is detected in the term of “H” assertion of RTS, its assertion count is suspended and the RTSx pin remains “ H ” o utput. After receiving the last stop bit, the count is resumed. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 64 of 148 APPLICATION 7641 Group 2.4 UART (3) Countermeasure for errors Three errors can be detected at reception. Each error is detected simultaneously when the data is transferred from the receive shift register to the receive buffer register. If receive errors occur, the corresponding error flags of UARTx status register are set to “ 1 ” . When any one of errors occurs, the summing error flag is set to “ 1 ” a nd the UARTx summing error interrupt request bit is also set to “ 1 ” . If a receive error occurs, the reception does not set the UARTx receive buffer full interrupt request bit to “ 1 ” . If receive errors occur, initialize the error flags and the UARTx receive buffer register and then retransmit the data. Table 2.4.3 shows the error flags set condition and how to clear error flags. Table 2.4.3 Error flags set condition and how to clear error flags Error flag Overrun flag (OER) Error flag set condition How to clear error flag •If the previous data in the receive buffer register • Reading UARTx status register is not read before the current receive operation •Hardware reset is completed. •Setting the receive initialization bit •If any one of error flags is “1” for the previous (RIN) to “ 1 ” data and the current receive operation is completed. F r a m i n g e r r o r f l a g • When the number of stop bit of the received (FER) data does not correspond with the selection with the stop bit length select bit (STB). Parity error flag (PER) •When the sum total of 1s of received data and the parity does not correspond with the selection with the parity select bit (PMD). Summing error flag • When any one of the PER, FER and OER is (SER) set to “ 1 ” . Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 65 of 148 APPLICATION 7641 Group 2.4 UART 2.4.6 UART application example (1) Data output (control of peripheral IC) Outline : Data is transmitted and received, using the UART. Figure 2.4.13 shows a connection diagram, and Figure 2.4.14 shows a timing chart. Transmitting side P84/UTXD1 P85/URXD1 P86/CTS1 Receiving side P80/UTXD2/SRDY P81/URXD2/URXD2 RTS2 7641 group (UART1 use) 7641 group (UART2 use) Fig. 2.4.13 Connection diagram Specifications : • Transmitter: UART1 is used. • Receiver: UART2 is used. • Transfer bit rate : 9600 bps ( φ = f (XIN )/4 = 4 MHz divided by 416) • Data format: 1ST-9DATA-2ST • Use of CTS and RTS functions • 2-byte data is transferred from the transmitting side to the receiving side at intervals of 10 ms generated by the timer. P86/CTS1 P84/UTXD1 ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2) ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2) ST D0 ••• 10 ms Fig. 2.4.14 Timing chart Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 66 of 148 APPLICATION 7641 Group 2.4 UART Figure 2.4.15 shows the registers setting for the transmitter, and Figures 2.4.16 and 2.4.17 show the registers setting for the receiver. Transmitting side UART1 mode register (Address : 3016) b7 b0 U1MOD 100 0000 UART clock : φ UART clock prescaling : φ/1 Stop bit length : 1 stop bit Parity checking disabled Character length : 9 bits UART1 control register (Address : 3316) b7 b0 U1CON 001 101 Transmit enabled Receive disabled Transmit initializing CTS function enabled RTS function disabled UART address mode disabled UART1 baud rate generator (Address : 3116) b7 b0 U1BRG 1916 Interrupt control register A (Address : 0516) b7 b0 ICONA 0 UART1 transmit interrupt disabled UART1 transmit/receive buffer register 2 (Address : 3516) b7 b0 U1TRB2 high-order 1 bit of transmitting data set UART1 transmit/receive buffer register 1 (Address : 3416) b7 b0 U1TRB1 low-order 8 bits of transmitting data set UART1 status register (Address : 3216) b7 b0 Write data to high-order address first, then to low-order address. U1STS Transmit complete flag Transmit buffer empty flag Fig. 2.4.15 Registers setting for transmitter Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 67 of 148 APPLICATION 7641 Group 2.4 UART Receiving side UART2 mode register (Address : 3816) b7 b0 U2MOD 100 0000 UART clock : φ UART clock prescaling : φ/1 Stop bit length : 1 stop bit Parity checking disabled Character length : 9 bits UART2 control register (Address : 3B16) b7 b0 U2CON 010 1 10 Transmit disabled Receive enabled Receive initializing CTS function disabled RTS function enabled UART address mode disabled UART2 RTS control register (Address : 3E16) b7 b0 U2RTS 00000000 No delay; Assertion immediately Interrupt control register B (Address : 0616) b7 b0 ICONB 0 0 UART2 receive buffer full interrupt disabled UART2 summing error interrupt disabled UART2 baud rate generator (Address : 3916) b7 b0 U2BRG 1916 Fig. 2.4.16 Registers setting for receiver (1) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 68 of 148 APPLICATION 7641 Group 2.4 UART UART2 transmit/receive buffer register 2 (Address : 3D16) b7 b0 U2TRB2 high-order 1 bit of receiving data read UART2 transmit/receive buffer register 1 (Address : 3C16) b7 b0 U2TRB1 low-order 8 bits of receiving data read UART2 status register (Address : 3A16) b7 b0 Read data from high-order address first, then from low-order address. U2STS Receive buffer full flag Parity error flag Framing error flag Overrun error flag Summing error flag Fig. 2.4.17 Registers setting for receiver (2) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 69 of 148 APPLICATION 7641 Group 2.4 UART Figure 2.4.18 shows a control procedure of transmitter, and Figure 2.4.19 shows a control procedure of receiver. RESET q x: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization U1BRG U1CON U1CON U1MOD U1CON U1CON ..... ..... (Address : 3116) (Address : 3316), bit2 (Address : 3316), bit4 (Address : 3016) (Address : 3316), bit5 (Address : 3316), bit1 1916 12 x 100x00002 1 1 0 • φ as UART clock, Clock prescaling 1/1, 1 stop bit, Parity checking disabled, 9-bit character length • CTS function enabled • UART1 transmit interrupt disabled ICONA (Address : 0516), bit7 CLI 10 ms pass ? Y U1TRB2 (Add. : 3516) U1TRB1 (Add. : 3416) N • An interval of 10 ms generated by Timer The first byte of a transmission data • Transmission data write Transmit buffer empty flag is set to “0” by this writing. Transmission starts owing to “L” input to CTS pin. • Judgment of transferring data from Transmit buffer register to Transmit shift register (Transmit buffer empty flag) U1STS (Address : 3216), bit1? 1 U1TRB2 (Add. : 3516) U1TRB1 (Add. : 3416) 0 The second byte of a transmission data • Transmission data write Transmit buffer empty flag is set to “0” by this writing. U1STS (Address : 3216), bit1? 1 0 • Judgment of transferring data from Transmit buffer register to Transmit shift register (Transmit buffer empty flag) U1STS (Address : 3216), bit0? 1 0 • Judgment of shift completion of Transmit shift register (Transmit complete flag) Fig. 2.4.18 Control procedure of transmitter Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 70 of 148 APPLICATION 7641 Group 2.4 UART RESET q x: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization U2BRG U2CON U2MOD U2CON U2RTS ..... ..... (Address : 3916) (Address : 3B16), bit3 (Address : 3816) (Address : 3B16), bit6 (Address : 3E16) 1916 12 100x00002 12 0016 xxxx0x0x2 • φ as UART clock, Clock prescaling 1/1, 1 stop bit, Parity checking disabled, 9-bit character length • RTS function enabled • No delay of RTS • UART2 receive interrupt disabled • UART2 summing error interrupt disabled ICONB (Address : 0616) CLI U2CON (Address : 3B16), bit1 12 • Reception starts. U2STS (Address : 3A16), bit2? 1 0 • Judgment of completion of receiving (Receive buffer full flag) Read out a received data from U2TRB2 (Add. : 3D16), U2TRB1 (Add. : 3C16) • Reception of the first byte data Receive buffer full flag is set to “0” by reading data. 1 • Judgment of an error flag U2STS (Address : 3A16), bit6? 0 U2STS (Address : 3A16), bit2? 1 0 • Judgment of completion of receiving (Receive buffer full flag) • Reception of the second byte data Receive buffer full flag is set to “0” by reading data. Read out a received data from U2TRB2 (Add. : 3D16), U2TRB1 (Add. : 3C16) U2STS (Address : 3A16), bit2? 0 1 • Judgment of an error flag Processing for error U2CON (Address : 3B16), bit1 02 U2CON (Address : 3B16) U2CON (Address : 3B16) 010x10002 010x10102 • Countermeasure for a bit slippage Fig. 2.4.19 Control procedure of receiver Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 71 of 148 APPLICATION 7641 Group 2.4 UART (2) UART address mode qOperation explanation The UART address mode is intended for use to communicate between the specified MCUs in a multi-MCU environment. The UART address mode can be used in either an 8-bit or 9-bit character length. An address is identified by the MSB of the incoming data being “1”. The bit is “0” for nonaddress data. When the MSB of the incoming data is “ 0 ” i n the UART address mode, the Receive Buffer Full Flag is set to “1”, but the Receive Buffer Full Interrupt Request Bit is not set to “1”. When the MSB of the incoming data is “1”, normal receive operation is performed. In the UART address mode an overrun error is not detected for reception of the 2nd and onward bytes. An occurrence of framing error or parity error sets the Summing Error Interrupt Request Bit to “ 1 ” a nd the data is not received independent of its MSB contents. Usage of UART address mode is explained as follows: (1) Set the UART Address Mode Enable Bit to “ 1 ” . (2) Sends the address data of a slave MCU first from a host MCU to all slave MCUs. The MSB of address data must be “ 1 ” a nd the remaining 7 bits specify the address. (3) The all slave MCUs automatically check for the received data whether its stop bit is valid or not, and whether the parity error occurs or not (when the parity enabled). If these errors occur, the Framing Error Flag or Parity Error Flag and the Summing Error Flag are set to “1”. Then, the Summing Error Interrupt Request Bit is also set to “ 1 ” . (4) When received data has no error, the all slave MCUs must judge whether the address of the received address data matches with their own addresses by a program. After the MSB being “ 1 ” i s received, the UART Address Mode Enable Bit is automatically set to “ 0 ” ( disabled). (5) The UART Address Mode Enable Bit of the slave MCUs which have be judged that the address does not match with them must be set to “1” (enabled) again by a program to disable reception of the following data. (6) Transmit the data of which MSB is “0” from the host MCU. The slave MCUs disabling the UART address mode receive the data, and their Receive Buffer Full Flags and the Receive Buffer Full Interrupt Request Bits are set to “ 1 ” . For the other slave MCUs enabling the UART address mode, their Receive Buffer Full Flag are set to “ 1 ” , but their Receive Buffer Full Interrupt Request Bits are not set to “ 1 ” . (7) An overrun error cannot be detected after the first data has been received in UART Address Mode. Accordingly, even if the slave MCUs does not read the received data and the next data has been received, an overrun error does not occur. Thus, a communication between a host MCU and the specified MCU can be realized. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 72 of 148 APPLICATION 7641 Group 2.4 UART q UART address mode application example Outline : The slave CPU (B) receives the data from the host CPU, using the UART address mode. Specifications : • UART1 is used. • Transfer bit rate : 9600 bps •Data format: 1ST-8DATA-2ST • Use of port P3 1 f or communication control Figure 2.4.20 shows a connection diagram; Figure 2.4.21 shows the registers setting related to UART address mode; Figures 2.4.22 and 2.4.23 show the control procedures. Host CPU UxTXD Port A P84/URXD1 P31 B P84/URXD1 P31 C P84/URXD1 P31 Slave CPU : 7641 Group (Address : 0116) Slave CPU : 7641 Group (Address : 0216) Slave CPU : 7641 Group (Address : 0316) Fig. 2.4.20 Connection diagram Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 73 of 148 APPLICATION 7641 Group 2.4 UART UART1 mode register (Address : 3016) b7 b0 U1MOD 010 0000 UART clock : φ UART clock prescaling : φ/1 Stop bit length : 1 stop bit Parity checking disabled Character length : 8 bits UART1 control register (Address : 3316) b7 b0 U1CON 100 1 10 Transmit disabled Receive enabled Receive initializing CTS function disabled RTS function disabled UART address mode enabled UART1 baud rate generator (Address : 3116) b7 b0 U1BRG 1916 UART1 transmit/receive buffer register 1 (Address : 3416) b7 b0 U1TRB1 Receiving data read Port P3 direction register (Address : 0F16) b7 b0 P3D 0 Input mode Interrupt control register A (Address : 0516) b7 b0 ICONA 1 UART1 receive buffer full interrupt enabled Interrupt control register B (Address : 0616) b7 b0 ICONB 1 UART1 summing error interrupt disabled UART1 status register (Address : 3216) b7 b0 U1STS Receive buffer full flag Parity error flag Framing error flag Overrun error flag Summing error flag Fig. 2.4.21 Registers setting related to UART address mode Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 74 of 148 APPLICATION 7641 Group 2.4 UART RESET q x: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization U1BRG U1CON U1CON U1MOD U1CON P3D ICONA ICONB ..... ..... (Address : 3116) (Address : 3316), bit2 (Address : 3316), bit4 (Address : 3016) (Address : 3316), bit5 (Address : 0F16), bit1 (Address : 0516), bit6 (Address : 0616), bit0 1916 12 x 010x00002 0 0 1 1 • φ as UART clock, Clock prescaling 1/1, 1 stop bit, Parity checking disabled, 8-bit character length • Port P31 to input mode • UART1 receive interrupt enabled • UART1 summing error interrupt enabled CLI U1CON (Address : 3316), bit1 12 • Reception starts. Main process 0 P3 (Address : 0E16), bit1? 1 U1CON (Address : 3316) U1CON (Address : 3316) 010x10002 010x10102 • Countermeasure for a bit slippage UART1 summing error interrupt routine CLT (Note 1) CLD (Note 2) Push registers to stack Note 1: When using Index X mode flag (T) Note 2: When using Decimal mode flag (D) •Push registers used in interrupt process routine Error process Pop registers RTI Fig. 2.4.22 Control procedure (1) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 75 of 148 APPLICATION 7641 Group 2.4 UART Slave CPU (B) receiving side RESET CLT (Note 1) CLD (Note 2) Push registers to stack q x: This bit is not used here. Set it to “0” or “1” arbitrarily. Note 1: When using Index X mode flag (T) Note 2: When using Decimal mode flag (D) •Push registers used in interrupt process routine • Data reception Receive buffer full flag is set to “0” by reading data. 0 : Data reception Read out a received data from U1TRB1 (Address : 3416) MSB of received data? 1 : Address reception Yes : Address of Slave CPU (B) Low-order 7 bits of received data = 0216? Store received data No : Address other than Slave CPU (B)’s U1CON (Address : 3316), bit7 1 • Address mode enabled Pop registers RTI Fig. 2.4.22 Control procedure (2) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 76 of 148 APPLICATION 7641 Group 2.4 UART 2.4.7 N otes on UART (1) Receive •When any one of errors occurs, the summing error flag is set to “1” and the UARTx summing error interrupt request bit is also set to “ 1 ” . If a receive error occurs, the reception does not set the UARTx receive buffer full interrupt request bit to “ 1 ” . •If the receive enable bit (REN) is set to “0” (disabled) while a data is being received, the receiving operation will stop after the data has been received. •Setting the receive initialization bit (RIN) to “1” resets the UARTx RTS control register (UxRTS) to “ 80 16” . After setting the RIN bit to “ 1 ” , set this UxRTS. (2) Transmit •Once the transmission starts, it continues until the last bit has been transmitted even though clearing the transmit enable bit (TEN) to “0” (disabled) or inputting “H” to the CTSx pin. After completion of the current transmission, the transmission is disabled. •The transmit complete flag (TCM) is changed from “1” to “0” later than 0.5 to 1.5 clocks of the shift clock. Accordingly, take it in consideration to transmit data confirming the TCM flag after the data is written into the transmit buffer register. (3) Register settings • If updating a value of UARTx baud rate generator while the data is being transmitted or received, be sure to disable the transmission and reception before updating. If the former data remains in the UARTx transmit buffer registers 1 and 2 at retransmission, an undefined data might be output. •The all error flags PER, FER, OER and SER are cleared to “0” when the UARTx status register is read, at the hardware reset or initialization by setting the Transmit Initialization Bit. These flags are also cleared to “ 0 ” b y execution of bit test instructions such as B BC a nd B CS . • The transmit buffer empty flag (TBE) is set to “ 0 ” w hen the low-order byte of transmitted data is written into the UARTx (x = 1, 2) transmit buffer register 1. When using 9-bit character length, set the data into the UARTx transmit buffer register 2 (high-order byte) first before the UARTx transmit buffer register 1 (low-order byte). • The receive buffer full flag (RBF) is set to “ 0 ” w hen the contents of UARTx receive buffer register 1 is read out. When using 9-bit character length, read the data from the UARTx receive buffer register 2 (high-order byte) first before the UARTx receive buffer register 1 (low-order byte). • If a character bit length is 7 bits, bit 7 of the UARTx transmit/receive buffer register 1 and bits 0 to 7 of the UARTx transmit/receive buffer register 2 are ignored at transmitting; they are invalid at receiving. If a character bit length is 8 bits, bits 0 to 7 of the UARTx transmit/receive buffer register 2 are ignored at transmitting; they are invalid at receiving. If a character bit length is 9 bits, bits 1 to 7 of the UARTx transmit/receive buffer register 2 are ignored at transmitting; they are “ 0 ” a t receiving. • The reset cannot affect the contents of baud rate generator. (4) UART address mode • When the MSB of the incoming data is “ 0 ” i n the UART address mode, the receive buffer full flag (RBF) is set to “ 1 ” , but the receive buffer full interrupt request bit is not set to “ 1 ” . •An overrun error cannot be detected after the first data has been received in UART address mode. • The UART address mode can be used in either an 8-bit or 9-bit character length. 7-bit character length cannot be used. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 77 of 148 APPLICATION 7641 Group 2.4 UART (5) CTS function When the CTS function is enabled, the transmitted data is not transferred to the transmit shift register until “L” is input to the CTSx pin (P86/CTS 1, P8 2/CTS2/SRXD). As the result, do not set the following data to the transmit buffer register. (6) RTS function •If the start bit is detected in the term of “H” assertion of RTS, its assertion count is suspended and the RTSx pin remains “ H ” o utput. After receiving the last stop bit, the count is resumed. •Setting the receive initialization bit (RIN) to “1” resets the UARTx RTS control register (UxRTS) to “ 80 16” . After setting the RIN bit to “ 1 ” , set this UxRTS. (7) Interrupt •When setting the transmit initialization bit (TIN) to “1”, both the transmit buffer empty flag (TBE) and the transmit complete flag (TCM) are set to “ 1 ” , so that the transmit interrupt request occurs independent of its interrupt source. After setting the transmit initialization bit (TIN) to “1”, clear the transmit interrupt request bit to “ 0 ” b efore setting the transmit enable bit (TEN) to “ 1 ” . •The transmit interrupt request bit is set and the interrupt request is generated by setting the transmit enable bit (TIN) to “1” even when selecting timing that either of the following flags is set to “1” as timing where the transmission interrupt is generated: (1) Transmit buffer empty flag is set to “ 1 ” (2) Transmit complete flag is set to “ 1 ” . Therefore, when the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as the following sequence: (1) Transmit enable bit is set to “ 1 ” (2) Transmit interrupt request bit is set to “ 0 ” (3) Transmit interrupt enable bit is set to “ 1 ” . Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 78 of 148 APPLICATION 7641 Group 2.5 DMAC 2.5 DMAC This paragraph explains the registers setting method and the notes related to the DMAC. 2.5.1 Memory map Address 000216 000516 003F16 004016 004116 004216 004316 004416 004516 004616 004716 Interrupt request register A (IREQA) Interrupt control register A (ICONA) DMAC index and status register (DMAIS) DMAC channel x mode register 1 (DMAx1) DMAC channel x mode register 2 (DMAx2) DMAC channel x source register Low (DMAxSL) DMAC channel x source register High (DMAxSH) DMAC channel x destination register Low (DMAxDL) DMAC channel x destination register High (DMAxDH) DMAC channel x transfer count register Low (DMAxCL) DMAC channel x transfer count register High (DMAxCH) Fig. 2.5.1 Memory map of registers related to DMAC Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 79 of 148 APPLICATION 7641 Group 2.5 DMAC 2.5.2 Related registers (1) DMAC index and status register • DMAC channel x (x = 0, 1) count register underflow flag (DxUF) When the corresponding transfer count register Low (address 46 16) underflows, this DxUF flag is set to “ 1 ” . Writing “ 0 ” i nto this flag clears it. • DMAC channel x (x = 0, 1) suspend flag (DxSFI) When an interrupt routine is processed during any DMA operation, the transfer operation is suspended and the DMAC automatically sets the corresponding DxSFI flag to “ 1 ” . As soon as the CPU completes the interrupt operation, the DMAC clears the DxSFI flag to “0” and resumes the original operation from the point where it was suspended. • DMAC transfer suspend control bit (DTSC) This bit specifies the transfer mode which can be suspended by an interrupt process. • DMAC register reload disable bit (DRLDD) If the DRLDD bit is “1”, when the DMAC channel x transfer count register underflows, the DMAC channel x source registers and destination registers are disabled from being reloaded from their latches. • Channel index bit (DCI) The related registers of channels 1 and 2 are assigned on the same SFR addresses. This DCI bit specifies the accessible channel. DMAC index and status register b7 b6 b5 b4 b3 b2 b1 b0 0 DMAC index and status register (DMAIS : address 3F16) b 0 1 2 3 4 Name DMAC channel 0 count register underflow flag (D0UF) DMAC channel 0 suspend flag (D0SFI) (Note 1) DMAC channel 1 count register underflow flag (D1UF) DMAC channel 1 suspend flag (D1SFI) (Note 1) DMAC transfer suspend control bit (DTSC) (Note 2) Functions 0 : No underflow 1 : Underflow generated 0 : Not suspended 1 : Suspended 0 : No underflow 1 : Underflow generated 0 : Not suspended 1 : Suspended 0 :Suspending only burst transfers during interrupt process 1 : Suspending both burst and cycle steal transfers during interrupt process 0 :Enabling reload of source and destination registers of both channels 1 : Disabling reload of source and destination registers of both channels 0 : Channel 0 accessible 1 : Channel 1 accessible Accessed registers: Mode register, At reset R W 0 0 0 0 0 ✽ ✕ ✽ ✕ 5 DMAC register reload disable bit (DRLDD) (Note 3) 6 Fix this bit to “0”. 7 Channel index bit (DCI) 0 0 0 source register, destination register, transfer count register. ✽: “0” can be set by software, but “1” cannot be set. Notes 1: Suspended by an interrupt. 2: Transfer suspended during interrupt process 3: This settings affect the source and destination registers of both channels. Fig. 2.5.2 Structure of DMAC index and status register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 80 of 148 APPLICATION 7641 Group 2.5 DMAC (2) DMAC channel x (x = 0, 1) mode register 1 • DMAC channel x source register increment/decrement selection bit (DxSRID) • DMAC channel x source register increment/decrement enable bit (DxSRCE) • DMAC channel x destination register increment/decrement selection bit (DxDRID) • DMAC channel x destination register increment/decrement enable bit (DxDRCE) These bits select that the DMAC channel X source registers and destination registers are either decreased or increased by 1 after transfer completion. • DMAC channel x data write control bit (DxDWC) The DxDWC bit controls write operation to the following registers and their latches: Low and High bytes of DMAC channel x source registers, destination registers and transfer count registers. When the DxDWC bit is “0”, data is simultaneously written into each latch and register. When this bit is “ 1 ” , data is written only into their latches. • DMAC channel x disable after count register underflow enable bit (DxDAUE) When the DxDAUE bit is “1”, after the DMAC channel x transfer count register Low underflows the corresponding channel x is disabled. The DMAC channel x enable bit (DxCEN, bit 7 of DMAxM2) goes to “ 0 ” a t the same time. • DMAC channel x register reload bit (DxRLD) Writing “1” to the DxRLD bit can update the DMAC channel x source registers, destination registers and transfer count registers with the values in their respective latches. It can be performed at anytime. This bit is fixed to “ 0 ” a t read. • DMAC channel x transfer mode selection bit (DxTMS) The DxTMS bit selects the transfer mode. DMAC channel x mode register 1 (x = 0, 1) b7 b6 b5 b4 b3 b2 b1 b0 DMAC channel x mode register 1 (DMAxM1 : address 4016) (Note 1) b Name Functions 0 : Increment after transfer 1 : Decrement after transfer 0 : Disabled (No change after transfer) 1 : Enabled 0 : Increment after transfer 1 : Decrement after transfer 0 : Disabled (No change after transfer) 1 : Enabled At reset R W 0 0 : Writing data in reload latches and 0 registers 1 : Writing data in reload latches only 5 DMAC channel x disable after 0 : Channel x enabled after count 0 register underflow count register underflow 1 : Channel x disabled after count enable bit (DxDAUE) register underflow DMAC channel x register 0 : Not reloaded 6 0 (Note 2) 1 : Source, destination, and transfer reload bit (DxRLD) count registers contents of channel x to be reloaded 0 : Cycle steal transfer mode 7 DMAC channel x transfer 0 mode selection bit (DxTMS) 1 : Burst transfer mode Notes 1: Channels 1 and 2 share this register. The channel selection which can use this register depends on channel index bit, bit 7 of DMAC index and status register. 2: These bits’ contents are “0” at read. 0 DMAC channel x source register increment/decrement selection bit (DxSRID) 1 DMAC channel x source register increment/decrement enable bit (DxSRCE) 2 DMAC channel x destination register increment/decrement selection bit (DxDRID) 3 DMAC channel x destination register increment/decrement enable bit (DxDRCE) 4 DMAC channel x data write control bit (DxDWC) 0 0 0 Fig. 2.5.3 Structure of DMAC channel x (x = 0, 1) mode register 1 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 81 of 148 APPLICATION 7641 Group 2.5 DMAC (3) DMAC channel x (x = 0, 1) mode register 2 • DMAC channel x software transfer trigger bit (DxSWT) Writing “1” to the DxSWT bit can generate a transfer request as a software trigger. If all of DMACx hardware transfer request source bits (DxHR) are “0”, the software trigger is only transfer request factor. This bit is fixed to “ 0 ” a t read. • DMAC channel x USB and master CPU bus interface enable bit (DxUMIE) When both USB and master CPU bus interface is used as a hardware transfer request source, set the DxUMIE bit to “ 1 ” . When not that the master CPU bus interface is used, but that the USB is only used, set the DxUMIE bit to “ 0 ” ( disabled). • DMAC channel x transfer initiation source capture register reset bit (DxCRR) Writing “1” to the DxCRR bit can reset the transfer initiation source capture register. The request of the transfer initiation source is latched asynchronously and it is sampled into the transfer initiation source capture register at a rising edge of φ . This bit is fixed to “ 0 ” a t read. • DMAC channel x enable bit (DxCEN) The DMAC channel x is enabled by setting this bit to “ 1 ” . When clearing this to “ 0 ” , the DMA transfer is finished. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 82 of 148 APPLICATION 7641 Group 2.5 DMAC DMAC channel 0 mode register 2 b7 b6 b5 b4 b3 b2 b1 b0 DMAC channel 0 mode register 2 (DMA0M2 : address 4116) (Note 1) b Name Functions At reset R W 0 0 DMAC channel 0 hardware b3b2b1b0 0 0 0 0 : Not used transfer request source 0 0 0 1 : UART1 receive interrupt bits (D0HR) 0 0 1 0 : UART1 transmit interrupt 0 0 1 1 : Timer Y interrupt 0 1 0 0 : INT0 interrupt 0 1 0 1 : USB endpoint 1 IN_PKT_RDY signal (falling edge active) 0 1 1 0 : USB endpoint 2 IN_PKT_RDY 1 signal (falling edge active) 0 1 1 1 : USB endpoint 3 IN_PKT_RDY signal (falling edge active) 1 0 0 0 : USB endpoint 1 OUT_PKT_RDY signal (rising edge active) 1 0 0 1 : USB endpoint 1 2 OUT_FIFO_NOT_EMPTY signal (rising edge active) 1 0 1 0 : USB endpoint 2 OUT_PKT_RDY signal (rising edge active) 1 0 1 1 : USB endpoint 3 OUT_PKT_RDY signal (rising edge active) 3 1 1 0 0 : Master CPU bus interface OBE0 signal (rising edge active) 1 1 0 1 : Master CPU bus interface IBF0 signal, data (rising edge active) 1 1 1 0 : Serial I/O transmit/receive interrupt 1 1 1 1 : CNTR1 interrupt 4 DMAC channel 0 software 0 : No action 1 : Request of channel 0 transfer by transfer trigger (D0SWT) writing “1” 5 DMAC channel 0 USB and 0 : Disabled master CPU bus interface 1 : Enabled enable bit (D0UMIE) 6 DMAC channel 0 transfer 0 : No action 1 : Reset of channel 0 capture register by initiation source capture writing “1” register reset bit (D0CRR) 0 : Channel 0 disabled 7 DMAC channel 0 enable 1 : Channel 0 enabled (Note 3) bit (D0CEN) 0 0 0 0 (Note 2) 0 0 (Note 2) 0 Notes 1: DMAC channel 0 mode register 2 and DMAC channel 1 mode register 2 are assigned at the same address 4116. The accessible register depends on channel index bit, bit 7 of DMAC index and status register. 2: These bits’ contents are “0” at read. This bit is automatically cleared to “0” after writing “1”. 3: When setting this bit to “1”, simultaneously set the DMAC channel 0 transfer initiation source capture register reset bit (bit 6 of DMA0M2) to “1”. Fig. 2.5.4 Structure of DMAC channel 0 mode register 2 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 83 of 148 APPLICATION 7641 Group 2.5 DMAC DMAC channel 1 mode register 2 b7 b6 b5 b4 b3 b2 b1 b0 DMAC channel 1 mode register 2 (DMA1M2 : address 4116) (Note 1) b Name Functions At reset R W 0 0 DMAC channel 1 hardware b3b2b1b0 0 0 0 0 : Not used transfer request source 0 0 0 1 : UART2 receive interrupt bits (D1HR) 0 0 1 0 : UART2 transmit interrupt 0 0 1 1 : Timer X interrupt 0 1 0 0 : INT1 interrupt 0 1 0 1 : USB endpoint 1 IN_PKT_RDY signal (falling edge active) 0 1 1 0 : USB endpoint 2 IN_PKT_RDY 1 signal (falling edge active) 0 1 1 1 : USB endpoint 4 IN_PKT_RDY signal (falling edge active) 1 0 0 0 : USB endpoint 1 OUT_PKT_RDY signal (rising edge active) 1 0 0 1 : USB endpoint 1 2 OUT_FIFO_NOT_EMPTY signal (rising edge active) 1 0 1 0 : USB endpoint 2 OUT_PKT_RDY signal (rising edge active) 1 0 1 1 : USB endpoint 4 OUT_PKT_RDY signal (rising edge active) 3 1 1 0 0 : Master CPU bus interface OBE1 signal (rising edge active) 1 1 0 1 : Master CPU bus interface IBF1 signal, data (rising edge active) 1 1 1 0 : Timer 1 interrupt 1 1 1 1 : CNTR0 interrupt 4 DMAC channel 1 software 0 : No action 1 : Request of channel 1 transfer by transfer trigger (D1SWT) writing “1” 5 DMAC channel 1 USB and 0 : Disabled master CPU bus interface 1 : Enabled enable bit (D1UMIE) 6 DMAC channel 1 transfer 0 : No action 1 : Reset of channel 1 capture register by initiation source capture writing “1” register reset bit (D1CRR) 0 : Channel 1 disabled 7 DMAC channel 1 enable 1 : Channel 1 enabled (Note 3) bit (D1CEN) 0 0 0 0 (Note 2) 0 0 (Note 2) 0 Notes 1: DMAC channel 0 mode register 2 and DMAC channel 1 mode register 2 are assigned at the same address 4116. The accessible register depends on channel index bit, bit 7 of DMAC index and status register. 2: These bits’ contents are “0” at read. This bit is automatically cleared to “0” after writing “1”. 3: When setting this bit to “1”, simultaneously set the DMAC channel 1 transfer initiation source capture register reset bit (bit 6 of DMA1M2) to “1”. Fig. 2.5.5 Structure of DMAC channel 1 mode register 2 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 84 of 148 APPLICATION 7641 Group 2.5 DMAC DMAC channel x source registers Low, High b7 b6 b5 b4 b3 b2 b1 b0 DMAC channel x source registers Low, High (DMAxSL,DMAxSH : addresses 4216, 4316) b Functions At reset R W 0 qThis is a 16-bit register with a latch. 0 1 0 2 qThis register indicates the source address for data transfer. 0 3 0 4 0 5 0 6 0 7 0 Notes 1: DMAC channel x source registers low, high of channels 0 and 1 are assigned at the same addresses. The accessible register depends on channel index bit, bit 7 of DMAC index and status register. 2: Write data into the lower bytes first, and then the higher bytes. 3: Read the contents from the higher bytes first, and then the lower bytes. Fig. 2.5.6 Structure of DMAC channel x source registers Low, High DMAC channel x destination registers Low, High b7 b6 b5 b4 b3 b2 b1 b0 DMAC channel x destination registers Low, High (DMAxDL,DMAxDH : addresses 4416, 4516) b Functions At reset R W 0 qThis is a 16-bit register with a latch. 0 1 0 2 qThis register indicates the destination address for data transfer. 0 3 0 4 0 5 0 6 0 7 0 Notes 1: DMAC channel x destination registers low, high of channels 0 and 1 are assigned at the same addresses. The accessible register depends on channel index bit, bit 7 of DMAC index and status register. 2: Write data into the lower bytes first, and then the higher bytes. 3: Read the contents from the higher bytes first, and then the lower bytes. Fig. 2.5.7 Structure of DMAC channel x destination registers Low, High Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 85 of 148 APPLICATION 7641 Group 2.5 DMAC DMAC channel x transfer count registers Low, High b7 b6 b5 b4 b3 b2 b1 b0 DMAC channel x transfer count registers Low (DMAxCL : address 4616) b 0 1 2 3 4 5 6 7 b7 b6 b5 b4 b3 b2 b1 b0 Functions qThis is the lower 8-bit register with a latch. Set the lower 8 bits of transfer numbers. qThis register indicates the remaining transfer numbers while transfer is continuing. qThis contents are decreased by 1 at every transfer operation. qWhen this register underflows, the DMAC interrupt request bit and the count register underflow flag (Note 2) are set to “1”. At reset R W 0 0 0 0 0 0 0 0 DMAC channel x transfer count registers High (DMAxCH : address 4716) b Functions At reset R W 0 qThis is the higher 8-bit register with a latch. Set the higher 8 bits of 0 transfer numbers. 1 0 2 qThis register indicates the remaining transfer numbers while 0 transfer is continuing. 3 0 qThis contents are decreased by 1 at every transfer operation. 4 0 5 0 6 0 7 0 Notes 1: DMAC channel x transfer count registers low, high of channels 0 and 1 are assigned at the same addresses 4616 and 4716. The accessible channel depends on channel index bit, bit 7 of DMAC index and status register. 2: Channel 0 used: Bit 0 of DMAC index and status register Channel 1 used: Bit 2 of DMAC index and status register 3: Write data into the lower byte first, and then the higher byte. 4: Read the contents from the higher byte first, and then the lower byte. Fig. 2.5.8 Structure of DMAC channel x transfer count registers Low, High Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 86 of 148 APPLICATION 7641 Group 2.5 DMAC Interrupt request register A b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register A (IREQA : address 0216) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ 0 USB function interrupt request bit 1 USB SOF interrupt request 0 : No interrupt request issued bit 1 : Interrupt request issued 0 : No interrupt request issued 2 INT0 interrupt request bit 1 : Interrupt request issued 3 INT1 interrupt request bit 4 DMAC0 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 5 DMAC1 interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit 6 UART1 receive buffer full 0 : No interrupt request issued 1 : Interrupt request issued interrupt request bit 7 UART1 transmit interrupt 0 : No interrupt request issued request bit 1 : Interrupt request issued ✽: “0” can be set by software, but “1” cannot be set. Fig. 2.5.9 Structure of Interrupt request register A Interrupt control register A b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register A (ICONA : address 0516) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 0 0 0 0 0 0 USB function interrupt enable bit 1 USB SOF interrupt enable 0 : Interrupt disabled bit 1 : Interrupt enabled 0 : Interrupt disabled 2 INT0 interrupt enable bit 1 : Interrupt enabled 3 INT1 interrupt enable bit 4 DMAC0 interrupt enable bit 5 DMAC1 interrupt enable bit 6 UART1 receive buffer full interrupt enable bit 7 UART1 transmit interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Fig. 2.5.10 Structure of Interrupt control register A Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 87 of 148 APPLICATION 7641 Group 2.5 DMAC 2.5.3 DMAC operation description The DMAC transfers data using the bus without use of the CPU. The DMAC consists of DMAC0 and DMAC1, which have the same function each. There are two transfer modes: Burst transfer mode or Cycle steal transfer mode. • Burst transfer mode Once a DMA transfer request is accepted, an entire batch of data is transferred. The right to use bus is not returned to the CPU until the transfer of all data has been completed. The DMAC transfers the number of bytes data specified by the transfer count register for each request. The count register is a 16-bit counter; the maximum number of data is 65,536 bytes per one request. • Cycle steal mode The DMAC transfers one byte of data for each request. If one byte transfer has been completed and then a DMA transfer request is not generated, the right to use bus is returned to the CPU. Figure 2.5.11 shows the transfer mode overview. s Burst transfer mode DMACx request is accepted. ➔ DMACx (x = 0, 1) (Transfer of entire batch of data) CPU Right to use bus CPU s Cycle steal transfer mode DMAC0 request is accepted. DMAC0 request is accepted. DMAC1 request is accepted. ➔ ➔ ➔ CPU Right to use bus CPU DMAC0 (One-byte transfer) CPU DMAC0 DMAC1 (One-byte transfer)(One-byte transfer) Fig. 2.5.11 Transfer mode overview (1) Priority The DMAC places a higher priority on Channel-0 transfer requests than on Channel-1 transfer requests. If a channel-0 transfer request occurs during a channel-1 burst transfer operation, the DMAC completes the next transfer source and destination read/write operation first, and then starts the channel-0 transfer operation. As soon as the channel-0 transfer is completed, the DMAC resumes the channel1 transfer operation. (2) Transfer request acceptance A transfer request is confirmed at every rising of φ . After that a channel priority and a right to use the bus is judged. A software trigger and/or a hardware factor can be selected as a transfer request source. The DMAC channel x hardware transfer request source bits (DxHR) selects a hardware factor. Writing “ 1 ” t o the DMAC channel x software transfer trigger bit (DxSWT) can generate a transfer request as a software trigger. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 88 of 148 APPLICATION 7641 Group 2.5 DMAC (3) DMA execution The selected channel transfers one byte of data from the address indicated by its source register (address 4216 or 4316) into the address indicated by its destination register (address 4416 or 4516) with at 2 cycles of φ . The operataion of the source registers and destination registers after transfer completion can be selected between decreased/increased by 1 and no change with bits 0 to 3 in the DMAC channel x mode register 1. When the transfer count register underflows, the source registers and destination registers are reloaded from their latches when the DMAC register reload disable bit (DRLDD) is “0”. If the DRLDD bit is set to “ 1 ” , a reload is disabled. A read/write must be performed to the source registers, destination registers and transfer count registers as follows: Read from each higher byte first, then the lower byte Write to each lower byte first, then the higher byte. (1) Read cycle DMAC DMAxSL, DMAxSH DMAxSL, DMAxSH latch ➂ DMAxDL, DMAxDH DMAxDL, DMAxDH latch DMAxCL, DMAxCH DMAxCL, DMAxCH latch Temporary register Transfer destination Decrementer Incrementer/ Decrementer Memory ➀Transfer source address is specified. ➁Contents of DMAxCL, DMAxCH are updated by Decrementer. ➂Contents of DMAxSL, DMAxSH are updated by Incrementer/Decrementer. ➃Data is read from memory and retained in Temporary register. ➀ Transfer source ➃ ➁ (2) Write cycle DMAC DMAxSL, DMAxSH DMAxSL, DMAxSH latch ➅ DMAxDL, DMAxDH DMAxDL, DMAxDH latch DMAxCL, DMAxCH DMAxCL, DMAxCH latch Temporary register Incrementer/ Decrementer Transfer source Memory ➄Transfer destination address is specified. ➅Contents of DMAxDL, DMAxDH are updated by Incrementer/Decrementer. ➆Contents of temporary register is written into memory. ➄ Decrementer ➆ Transfer destination Note: The temporary register is an internal use register, so that it cannot be read out or written into by program. Fig. 2.5.12 Basic operation of registers transferring Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 89 of 148 APPLICATION 7641 Group 2.5 DMAC Figure 2.5.12 shows the basic operation of registers transferring. Tables 2.5.1 and 2.5.2 shows the address directions and examples of transfer result. Table 2.5.1 Address directions and examples of transfer result (1) Address direction Source Fixed Destination Fixed Data arrangement on transfer source memory Transfer sequence Data arrangement on transfer destination memory (Ttransfer result) * Data Data * Fixed Forward * Data 1 to 6 ➀ ➁ ➂ ➃ ➄ ➅ Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 * Fixed Backward ➅ * Data 1 to 6 ➄ ➃ ➂ ➁ ➀ Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 * Forward Fixed * Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 ➀ ➁ ➂ ➃ ➄ ➅ Data 1 to 6 * Forward Forward * Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 ➀ ➁ ➂ ➃ ➄ ➅ Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 * Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 90 of 148 APPLICATION 7641 Group 2.5 DMAC Table 2.5.2 Address directions and examples of transfer result (2) Address direction Source Forward Destination Backward Data arrangement on transfer source memory Transfer sequence Data arrangement on transfer destination memory (Ttransfer result) * Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 ➀ ➁ ➂ ➃ ➄ ➅ Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 * Backward Fixed Data 6 Data 5 Data 4 Data 3 Data 2 ➅ ➄ ➃ ➂ ➁ ➀ Data 1 to 6 * * Backward Forward Data 1 Data 6 Data 5 Data 4 Data 3 Data 2 ➅ ➄ ➃ ➂ ➁ ➀ Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 * * Backward Backward Data 1 Data 1 6 Data 2 5 Data 3 4 Data 4 3 Data 5 2 ➅ ➄ ➃ ➂ ➁ ➀ Data 1 6 Data 2 5 Data 3 4 Data 4 3 Data 5 2 Data 6 1 * Data 6 1 * (4) Transfer suspension Writing “0” to the DMAC channel x enable bit (DxCEN) can compulsorily suspend the transfer being executed. The suspended transfer can be resumed by writing “ 1 ” t o the DxCEN bit. When an interrupt request, which is enabled, occurs during any DMA operation, the transfer operation is suspended and the interrupt process routine is initiated. During the interrupt operation, the DMAC automatically sets the corresponding DMAC channel x suspend flag to “1”. When the DMAC transfer suspend control bit (DTSC) is “ 1 ” , the transfer is suspended in both burst transfer and cycle steal transfer modes during an interrupt process; when the DTSC bit is “0”, it is suspended in only burst transfer mode. The suspended transfer due to the interrupt can also be resumed during its interrupt process routine by writing “ 1 ” t o the DxCEN bit. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 91 of 148 APPLICATION 7641 Group 2.5 DMAC 2.5.4 DMAC arbitration The DMA transfer request is accepted at a rising of φ . If the bus is not released 1 cycle of φ l ater than the transfer request acceptance, the DMAC will wait for the bus released. When the bus is released, the DMAC has a right to use the bus and starts the DMA transfer unless a request of the right to use the bus having priority over the DMAC occurs. Table 2.5.3 shows the priority to use the bus. Table 2.5.3 Priority to use bus Priority 1 (Higher) 2 3 4 (Lower) Factor requesting right to use bus Hold request via HOLD pin DMAC CPU data access CPU instruction access 2.5.5 Transfer time One-byte transfer of the cycle steal transfer mode requires the time calculated by the following equation: Time (T) = A + B + C A: This means the time from the occurrence of DMA transfer source request to sampling it. It needs 1 cycle of φ a t the maximum. The sampling is asynchronously performed. B: This means the delay time to sample the DMA transfer source request. It needs 1 cycle of φ a t the maximum. C: This means the time to transfer data. It needs 2 cycles of φ . Figures 2.5.13 to 2.5.15 show the timing chart for DMA transfer. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 92 of 148 APPLICATION 7641 Group 2.5 DMAC φ OUT SYNCOUT RD WR LDA $zz STA $zz ADL1, 00 PC + 2 85 DMA transfer DMA source add. DMA destination add. STA $zz (last 2 cycles) PC + 3 ADL2, 00 Next instruction PC + 4 Op code 3 Address Data DMAOUT (Port P33) Transfer request source (“L” active) Transfer request source sampling Reset of transfer request source sampling PC A5 PC + 1 ADL1 Data DMA data DMA data ADL2 Data Fig. 2.5.13 Timing chart for cycle steal transfer caused by hardware-related transfer request φ OUT SYNCOUT RD WR LDM #$90, $41 1 cycle 1 cycle 1 cycle instruction instruction instruction 42, 00 41 DMA transfer DMA source add. DMA destination add. Next instruction PC + 6 Op code 6 Address Data DMAOUT (Port P33) Transfer request source (“L” active) Transfer request source sampling Reset of transfer request source sampling PC 3C PC + 1 18 PC + 2 PC + 3 90 PC + 4 PC + 5 Op code 2 Op code 3 Op code 4 DMA data DMA data Fig. 2.5.14 Timing chart for cycle steal transfer caused by software trigger transfer request Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 93 of 148 APPLICATION 7641 Group 2.5 DMAC φ OUT SYNCOUT RD WR LDA $zz STA $zz (First cycle) ADL1, 00 PC + 2 85 DMA source add. 1 DMA transfer DMA destination add. 1 DMA source add . 2 STA $zz (Second cycle) DMA destination add. 2 Address Data DMAOUT (Port P33) Transfer request source (“L” active) Transfer request source sampling Reset of transfer request source sampling PC A5 PC + 1 PC + 3 ADL2 ADL1 Data DMA data 1 DMA data 1 DMA data 2 DMA data 2 Fig. 2.5.15 Timing chart for burst transfer caused by hardware-related transfer request Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 94 of 148 APPLICATION 7641 Group 2.5 DMAC 2.5.6 DMAC application example (1) Transfer from external FIFO to USB FIFO Outline: D ata are transferred from external FIFOs to USB FIFOs. Specifications: • A burst transfer is used and 128-byte (128 bytes/packet) continuous transfer is performed. The external FIFO size must be set as 128 bytes of an integral multiple. • If the data is deficient in the external FIFO, the DMAC channel 0 transferring is stopped in the DMAC channel 0 interrupt routine process. The DMA transfer is resumed in the main routine process when the data is sufficient. • To confirm the external FIFO state after completion of 128 bytes transferring, set the DMAC channel x disable after count register underflow enable bit (DxDAUE) to “1”. •USB endpoint 2 IN_PKT_RDY (falling edge) selected as hardware transfer request source. • Master CPU bus interface unused. Figures 2.5.16 and 2.5.17 show a setting of the related registers and Figure 2.5.18 shows a control procedure. If data are transferred from USB FIFOs to external FIFOs as well as this, use USB endpoint 2 OUT_PKT_RDY (rising edge) selected as hardware transfer request source. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 95 of 148 APPLICATION 7641 Group 2.5 DMAC Clock control register (address 1F16) b7 b0 CCR 0 00000 φ = f(XIN)/2 Frequency synthesizer multiply register 1 (address 6D16) b7 b0 FSM1 0016 Frequency synthesizer multiply register 2 (address 6E16) b7 b0 FSM2 FF16 Frequency synthesizer control register (address 6C16) b7 b0 FSC 01000001 Frequency synthesizer enabled f(XIN) selected as frequency synthesizer input USB control register (address 1316) b7 b0 USBC 1 1100 0 “H” current for USB line driver USB line driver enabled USB clock enabled USB block enabled USB endpoint index register (address 5816) b7 b0 USBINDEX 010 Endpoint 2 USB endpoint FIFO mode register (address 5F16) b7 b0 USBFIFOMR 1XXX FIFO size s elec tion bit For endpoint 2 IN 128 bytes, OUT 128 bytes USB endpoint 2 IN max. packet size register (address 5B16) b7 b0 IN_MAXP 128 128 bytes USB endpoint 2 IN control register (address 5916) b7 b0 IN_CSR 1 IN_PKT_RDY bit AUTO_SET bit DMAC index and status register (address 3F16) b7 b0 DMAIS 0 Channel 0 accessible DMAC channel 0 source registers Low, High (addresses 4216, 4316) b7 b0 DMA0SL XX16 b7 b0 External FIFO address (low-order) DMA0SH XX16 External FIFO address (high-order) Fig. 2.5.16 Setting of relevant registers (1) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 96 of 148 APPLICATION 7641 Group 2.5 DMAC DMAC channel 0 destination registers Low, High (addresses 4416, 4516) b7 b0 DMA0DL 6216 USB endpoint 2 FIFO address (low-order) b7 b0 DMA0DH 0016 USB endpoint 2 FIFO address (high-order) DMAC channel 0 transfer count registers Low, High (addresses 4616, 4716) b7 b0 DMA0CL 127 128-byte counts b7 b0 DMA0CH 0 High-order of transfer counter DMAC channel 0 mode register 1 (address 4016) b7 b0 DMA0M1 100 0 0 DMAC channel 0 source register increment/decrement disabled DMAC channel 0 destination register increment/decrement disabled Channel 0 enabled after count register underflow Burst transfer mode selected USB interrupt enable register 1 (address 5416) b7 b0 USBIE1 00 USB endpoint 2 IN interrupt disabled USB endpoint 2 OUT interrupt disabled Interrupt request register A (address 0216) b7 b0 IREQA 0 DMAC0 interrupt request bit USB interrupt control register A (address 0516) b7 b0 ICONA 1 0 USB function interrupt disabled DMAC0 interrupt enabled DMAC channel 0 mode register 2 (address 4116) b7 b0 DMA0M2 11010110 USB endpoint 2 IN_PKT_RDY signal hardware transfer request source Software transfer trigger requesting DMAC channel 0 USB and master CPU bus interface disabled Reset of channel 0 capture register Channel 0 enabled Fig. 2.5.17 Setting of relevant registers (2) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 97 of 148 APPLICATION 7641 Group 2.5 DMAC RESET Initialization SEI CCR (address 1F16) FSM1 (address 6D16) FSM2 (address 6E16) FSD (address 6F16) FSC (address 6C16) USBC (address 1316) USBINDEX (address 5816) USBFIFOMR (address 5F16) IN_MAXP (address 5B16) IN_CSR (address 5916) DMAIS (address 3F16) DMA0SL (address4216) DMA0SH (address 4316) DMA0DL (address4416) DMA0DH (address 4516) DMA0CL (address4616) DMA0CH (address 4716) DMA0M1 (address 4016) USBIE1 (address 5416) IREQA (address 0216) ICONA (address 0516) DMA0M2 (address 4116) CLI q x: This bit is not used here. Set it to “0” or “1” arbitrarily. ..... 0016 0016 FF16 0016 4116 1X1100X02 XX0000102 00001XXX2 8016 1XXXXXXX2 0XXXXX002 XX16 XX16 6216 0016 7F16 0016 100X0X0X2 XX00XXXX2 0016 XXX1XXX02 110101102 •USB initialization •Maximum packet size of 128 bytes •External FIFO for source register •USB FIFO1 for destination register •USB endpoint 2 IN_PKT_RDY as hardware transfer request source •USB endpoint 2 IN and OUT interrupts disabled •DMAC channel 0 USB and master CPU bus interface disabled •After confirming external FIFO state, generate the software transfer trigger request ..... DMAC channel 0 interrupt Note 1: When using Index X mode flag (T) 2: When using Decimal mode flag (D) •Push registers used in interrupt process routine CLT (Note 1) CLD (Note 2) Push registers to stack Y Data is available in external FIFO ? N DMA0M2 (address 4116), bit 7 0 •If a data is deficient, stop the DMA transferring. After all data have been available, resume the transfer. Pop registers R TI Fig. 2.5.18 Control procedure Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 98 of 148 APPLICATION 7641 Group 2.5 DMAC 2.5.7 N otes on DMAC (1) Transfer time • One-byte data transfer requires 2 cycles of φ ( read and write cycles). •To perform DMAC transfer due to the different transfer requests on the same DMAC channel or DMAC transfer between both DMAC channels, 1 cycle of φ o r more is needed before transfer is started. (2) Priority • The DMAC places a higher priority on channel-0 transfer requests than on channel-1 transfer requests. If a channel-0 transfer request occurs during a channel-1 burst transfer operation, the DMAC completes the next transfer source and destination read/write operation first, and then stops the channel-1 transfer operation. The channel-1 transfer operation which has been suspended is automatically resumed from the point where it was suspended so that channel-1 transfer can complete its one-burst transfer unit. This will be performed even if another channel-0 transfer request occurs. • The suspended transfer due to the interrupt can also be resumed during its interrupt process routine by writing “ 1 ” t o the DMAC channel x enable bit (DxCEN). (3) Related registers •A read/write must be performed to the source registers, transfer destination registers and transfer count registers as follows: Read from each higher byte first, then the lower byte Write to each lower byte first, then the higher byte. Note that if the lower byte is read out first, the values are the higher byte ’ s. • Do not access the DMAC-related registers by using a DMAC transfer. The destination address data and the source address data will collide in the DMAC internal bus. •When setting the DMAC channel x enable bit (bit 7 of address 41 16) to “1”, be sure simultaneously to set the DMAC channel x transfer initiation source capture register reset bit (bit 6 of address 41 16) to “ 1 ” . If this is not performed, an incorrect data will be transferred at the same time when the DMAC is enabled. (4) USB transfer One signal among USB endpoint signals 1 to 4 can be selected as the hardware transfer request source. This can realize that transfer between the USB FIFO and the master CPU bus interface input/output buffer is performed effectively. This transfer function is only valid in the cycle steal transfer mode. (5) DMA OUT p in In the memory expansion mode and microprocessor mode, the DMA OUT pin (P3 3/DMAOUT) outputs “ H ” d uring a DMA transfer. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 99 of 148 APPLICATION 7641 Group 2.6 USB 2.6 USB Some application notes are available on the Web site: http://www.renesas.com Please refer to them for explanation and application of USB function. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 100 of 148 APPLICATION 7641 Group 2.7 Frequency synthesizer (PLL) 2.7 Frequency synthesizer This paragraph explains the registers setting method and the notes related to the frequency synthesizer. 2.7.1 Memory map Address 000016 006C16 006D16 006E16 006F16 CPU mode register A (CPMA) Frequency synthesizer control register (FSC) Frequency synthesizer multiply register 1 (FSM1) Frequency synthesizer multiply register 2 (FSM2) Frequency synthesizer divide register (FSD) Fig. 2.7.1 Memory map of registers related to frequency synthesizer Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 101 of 148 APPLICATION 7641 Group 2.7 Frequency synthesizer (PLL) 2.7.2 Related registers CPU mode register A b7 b6 b5 b4 b3 b2 b1 b0 1 CPU mode register A (CPMA : address 0016) b Name b1b0 Functions 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode (Note 1) 1 1 : Not available 0 : Page 0 1 : Page 1 0 : Stopped 1 : Oscillating 0 : Oscillating 1 : Stopped 0 : External clock (XIN-XOUT or XCIN-XCOUT) 1 : fsyn 0 : XIN-XOUT 1 : XCIN-XCOUT At reset R W 0 0 1 1 0 0 0 0 0 Processor mode bits 1 2 Stack page select bit 3 Fix this bit to “1”. 4 Sub-clock (XCIN-XCOUT) stop bit 5 Main clock (XIN-XOUT) stop bit 6 Internal system clock select bit (Note 2) 7 External clock select bit Notes 1: This is not available in the flash memory version. 2: When (CPMA 7, 6) = (0, 0), the internal system clock can be selected between f(XIN) and f(XIN)/2 by CCR7. The internal clock φ is the internal system clock divided by 2. Fig. 2.7.2 Structure of CPU mode register A Frequency synthesizer control register b7 b6 b5 b4 b3 b2 b1 b0 0 00 Frequency synthesizer control register (FSC : address 6C16) b Name 0 : Disabled 1 : Enabled Functions At reset R W 0 0 0 0 0 0 Frequency synthesizer enable bit (FSE) 1 Fix these bits to “0”. 2 3 Frequency synthesizer input bit (FIN) 4 Fix this bit to “0”. 5 LPF current control bit (CHG1, CHG0) (Note) 6 7 Frequency synthesizer lock status bit 0 : f(XIN) 1 : f(XCIN) b1b0 0 0 : Not available 0 1 : Low current 1 0 : Intermediate current (recommended) 1 1 : High current 0 : Unlocked 1 : Locked 1 1 0 Note: Bits 6 and 5 are set to (bit 6, bit 5) = (1, 1) at reset. When using the frequency synthesizer, we recommend to set to (bit 6, bit 5) = (1, 0) after locking the frequency synthesizer. Fig. 2.7.3 Structure of Frequency synthesizer control register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 102 of 148 APPLICATION 7641 Group 2.7 Frequency synthesizer (PLL) Frequency synthesizer multiply register 1 b7 b6 b5 b4 b3 b2 b1 b0 Frequency synthesizer multiply register 1 (FSM1: address 6D16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qfVCO clock is generated by multiplying fPIN clock, which is generated by FSM2, by the contents of this register: 1 2 fVCO = fPIN • {2(n +1)}, n: value set to FSM1. 3 4 5 6 7 Fig. 2.7.4 Structure of Frequency synthesizer multiply register 1 Frequency synthesizer multiply register 2 b7 b6 b5 b4 b3 b2 b1 b0 Frequency synthesizer multiply register 2 (FSM2: address 6E16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qfPIN clock is generated by dividing fIN clock by the contents of this register. 1 Either f(XIN) or f(XCIN) as an input clock fIN for the frequency 2 synthesizer is selectable. 3 4 fPIN = fIN / {2(n +1)}, n: value set to FSM2 5 6 7 Fig. 2.7.5 Structure of Frequency synthesizer multiply register 2 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 103 of 148 APPLICATION 7641 Group 2.7 Frequency synthesizer (PLL) Frequency synthesizer divide register b7 b6 b5 b4 b3 b2 b1 b0 Frequency synthesizer divide register (FSD: address 6F16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qfSYN clock is generated by dividing fVCO clock by the contents of this register: 1 2 fSYN = fVCO / {2(m +1)}, m: value set to FSD 3 4 5 6 7 Fig. 2.7.6 Structure of Frequency synthesizer divide register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 104 of 148 APPLICATION 7641 Group 2.7 Frequency synthesizer (PLL) 2.7.3 Functional description The frequency synthesizer generates the 48 MHz clock required by f USB and fSYN, which are multiples of the external input reference f(XIN) or f(XCIN). To use the frequency synthesizer, set the frequency synthesizer enable bit of frequency synthesizer control register (address 6C 16) to “ 1 ” . The frequency synthesizer input bit selects either f(X IN) or f(XCIN) as an input clock f IN f or the frequency synthesizer. Figure 2.7.7 shows the block diagram for the frequency synthesizer circuit. fVCO fIN Prescaler fPIN Frequency Multiplier Frequency Divider fSYN fUSB FSM2 (address 006E16) FSM1 (address 006D16) Frequency synthesizer lock status bit FSC (address 006C16) FSD (address 006F16) Data Bus Fig. 2.7.7 Block diagram for frequency synthesizer circuit (1) f PIN f IN i s divided by the contents of frequency synthesizer multiply register 2 (FSM2: address 6E 16) to generate f PIN, where f PIN = f IN / 2 (n + 1), n: value set to FSM2. When the value of FSM2 is set to 255, the division is not performed and f PIN w ill equal f IN. Figure 2.7.8 shows the frequency synthesizer multiply register 2 setting example. Note : Be sure to set f PIN t o 1 MHz or more. fPIN 24 MHz 1 MHz 2 MHz 3 MHz 6 MHz 12 MHz FSM2 register set value Decimal 255 11 5 3 1 0 Hexadecimal FF16 0B16 0516 0316 0116 0016 fIN 24.00 MHz 24.00 MHz 24.00 MHz 24.00 MHz 24.00 MHz 24.00 MHz Fig. 2.7.8 Frequency synthesizer multiply register 2 setting example Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 105 of 148 APPLICATION 7641 Group 2.7 Frequency synthesizer (PLL) (2) f VCO f VCO i s generated by multiplying f PIN b y the contents of frequency synthesizer multiply register 1 (FSM1: address 6D 16), where f VCO = f PIN ✕ { 2(n + 1)}, n: value set to FSM1. Set the value of FSM1 so that f VCO w ill be 48 MHz. f VCO i s optimized in the frequency synthesizer to be used as f USB a nd it will be sent into the USB function control unit. While the frequency synthesizer enable bit is “ 0 ” ( disabled), f VCO r etains “ H ” o r “ L ” l evel. Figure 2.7.9 shows the frequency synthesizer multiply register 1 setting example. fPIN 320 kHz 2 MHz 4 MHz 6 MHz 12 MHz 24 MHz FSM1 register set value Decimal 74 11 5 3 1 0 Hexadecimal 4A16 0B16 0516 0316 0116 0016 fVCO 48.00 MHz 48.00 MHz 48.00 MHz 48.00 MHz 48.00 MHz 48.00 MHz Fig. 2.7.9 Frequency synthesizer multiply register 1 setting example (3) f SYN fVCO is divided by the contents of frequency synthesizer divide register (FSD: address 6F16) to generate f SYN, where f SYN = f VCO / 2 (m + 1), m: value set to FSD. When the value of FSD is set to 255, the division is not performed and f SYN b ecomes invalid. fSYN can be used as the internal system clock by setting the internal system clock select bit of CPU mode register A. Figure 2.7.10 shows the frequency synthesizer divide register setting example. When the frequency synthesizer lock status bit is “ 1 ” i n the frequency synthesizer enabled, this indicates that f SYN a nd fVCO h ave correct frequencies. fVCO 48.00 MHz 48.00 MHz FSD register set value Decimal 00 127 Hexadecimal 0016 7F16 fSYN 24.00 MHz 187.5 kHz Fig. 2.7.10 Frequency synthesizer divide register setting example Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 106 of 148 APPLICATION 7641 Group 2.7 Frequency synthesizer (PLL) (4) Recovering from hardware reset The frequency synthesizer and DC-DC converter must be set up as follows when recovering from a Hardware Reset: x Enable the frequency synthesizer after setting the frequency synthesizer related registers (addresses 6C 16 t o 6F 16). Then wait for 2 ms. y C heck the frequency synthesizer lock status bit. If “ 0 ” , wait for 0.1 ms and then recheck. z To use the intermediate current, set the LPF current control bits of frequency synthesizer control register (address 6C 16) to (b6, b5) = “ 10 ” . { When using the USB built-in DC-DC converter, set the USB line driver supply enable bit of the USB control register (address 13 16) to “ 1 ” . This setting must be done 2 ms or more later than the setup described in step x. The USB line driver current control bit must be set to “0” at this time. (When Vcc = 3.3V, the setting explained in this step is not necessary.) | A fter waiting for (C + 1) ms so that the external capacitance pin (Ext. Cap. pin) can reach approximately 3.3 V, set the USB clock enable bit to “1”. At this time, “C” equals the capacitance ( µ F) of the capacitor connected to the Ext. Cap. pin. For example, if 2.2 µ F and 0.1 µ F capacitors are connected to the Ext. Cap. in parallel, the required wait will be (2.3 + 1) ms. } A fter enabling the USB clock, wait for 4 or more φ c ycles, and then set the USB enable bit to “1”. Do not write to any of the USB internal registers (addresses 50 16 t o 64 16) until the USB clock enabled, except for the USB control register (address 13 16), clock control register (address 1F 16), and frequency synthesizer control register (address 6C 16). 2.7.4 N otes on frequency synthesizer •Bits 6 and 5 of the frequency synthesizer control register (address 6C16) are initialized to (b6, b5) = “11” after reset release. Make sure to set bits 6 and 5 to “ 10 ” a fter the frequency synthesizer lock status bit goes to “ 1 ” . •Use the frequency synthesizer output clocks 2 ms to 5 ms later than setting the frequency synthesizer enable bit to “1” (enabled). After that do not change any register values because it might cause output clocks unstabilized temporarily. • Make sure to connect a low-pulse filter to the LPF pin when using the frequency synthesizer. • The frequency synthesizer divide register set value never affects f USB f requency. • When using the f SYN a s an internal system clock, set the frequency synthesizer divide register so that f SYN c ould be 24 MHz or less. • When using the frequency synthesized clock function, we recommend using the fastest frequency possible of f(X IN) or f(X CIN) as an input clock for the PLL. • Set the value of frequency synthesizer multiply register 2 (FSM2) so that the f PIN i s 1 MHZ or higher. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 107 of 148 APPLICATION 7641 Group 2.8 Master CPU bus interface 2.8 Master CPU bus interface This paragraph explains the registers setting method and the notes related to the master CPU bus interface. 2.8.1 Memory map Address 000416 000716 004816 004916 004A16 004C16 004D16 004E16 Interrupt request register C (IREQC) Interrupt control register C (ICONC) Data bus buffer register 0 (DBB0) Data bus buffer status register 0 (DBBS0) Data bus buffer control register 0 (DBBC0) Data bus buffer register 1 (DBB1) Data bus buffer status register 1 (DBBS1) Data bus buffer control register 1 (DBBC1) Fig. 2.8.1 Memory map of registers related to master CPU bus interface Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 108 of 148 APPLICATION 7641 Group 2.8 Master CPU bus interface 2.8.2 Related registers Data bus buffer register x b7 b6 b5 b4 b3 b2 b1 b0 Data bus buffer register x (x = 0, 1) (DBBx: addresses 4816, 4C16) b Functions At reset R W 0 0 0 0 0 0 0 0 0 qA data is latched into this register by a write request from the host CPU. 1 2 3 qWrite an output data into this register. The data is output on to the data bus by a read request from the 4 host CPU. 5 6 7 Fig. 2.8.2 Structure of Data bus buffer register x (x = 0, 1) Data bus buffer status register x b7 b6 b5 b4 b3 b2 b1 b0 Data bus buffer status register x (x = 0, 1) (DBBSx: addresses 4916, 4D16) b Name Functions 0 : Buffer empty 1 : Buffer full 0 : Buffer empty 1 : Buffer full This flag can be defined by user freely. This flag indicates the condition of A0 status when the IBFx flag is set. This flag can be defined by user freely. At reset R W 0 0 0 0 ✕ ✕ ✕ 0 Output buffer full flag (OBFx) 1 Input buffer full flag (IBFx) 2 User definable flag (U2) 3 A0 flag (A0x) 4 User definable flag 5 (U4 to U7) 6 6 7 0 Fig. 2.8.3 Structure of Data bus buffer status register x (x = 0, 1) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 109 of 148 APPLICATION 7641 Group 2.8 Master CPU bus interface Data bus buffer control register 0 b7 b6 b5 b4 b3 b2 b1 b0 0 Data bus buffer control register 0 (DBBC0 : address 4A16) b Name Functions At reset R W 0 0 0 0 OBF0 output enable bit 1 2 3 4 5 6 7 0 : P52 functions as I/O port. 1 : P52 functions as OBF0 output pin. 0 : P53 functions as I/O port. IBF0 output enable bit 1 : P53 functions as IBF0 0 : Occurrence due to data write (A0 = “0”) or IBF0 interrupt select bit command write (A0 = “1”) 1 : Occurrence due to command write (A0 = “1”) Output buffer 0 empty 0 : Enabled interrupt disable bit 1 : Disabled Input buffer 0 full interrupt 0 : Enabled disable bit 1 : Disabled Nothing arranged for this bit. Fix this bit to “0”. Master CPU bus interface Function of P54 to P57, P60 to P67 ; 0 : As I/O ports. enable bit 1 : As master CPU bus interface function pins. Bus interface type select 0 : RD,WR separate type bus bit 1 : R/W type bus 0 0 0 0 0 Fig. 2.8.4 Structure of Data bus buffer control register 0 Data bus buffer control register 1 b7 b6 b5 b4 b3 b2 b1 b0 00 Data bus buffer control register 1 (DBBC0 : address 4E16) b Name Functions 0 : P74 functions as I/O port. 1 : P74 functions as OBF1 output pin. (Note) 0 : P73 functions as I/O port. 1 : P73 functions as IBF1 output pin. (Note) 0 : Occurrence due to data write (A0 = “0”) or command write (A0 = “1”) 1 : Occurrence due to command write (A0 = “1”) At reset R W 0 0 OBF1 output enable bit 1 IBF1 output enable bit 0 2 IBF1 interrupt select bit 0 3 Output buffer 1 empty 0 : Enabled interrupt disable bit 1 : Disabled 4 Input buffer 1 full interrupt 0 : Enabled disable bit 1 : Disabled 5 Nothing arranged for these bits. 6 Fix these bits to “0”. 0 : Single data bus buffer mode(P72 7 Data bus buffer function functions as I/O port.) select bit 1 : Double data bus buffer mode(P72 functions as S1 input pin.) Note: This can be selected when the data bus buffer function select bit is “1”. 0 0 0 0 0 Fig. 2.8.5 Structure of Data bus buffer control register 1 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 110 of 148 APPLICATION 7641 Group 2.8 Master CPU bus interface 2.8.3 Functional description The internal 2-byte bus interface can be controlled by the signals from the host CPU side; it is called the slave mode. This bus interface allows the 7641 group to be directly connected with a R/W type of CPU bus or a RD and WR separate type of CPU bus. Ports P5 2 t o P5 7, P6 0 t o P6 7, P7 2 t o P7 4 b ecome the master CPU bus interface function pins when the master CPU bus interface is enabled. P60 to P67: Function as data I/O pins (DQ 0 to DQ7). (Be sure to set them to input mode by setting the port P6 direction register to “ 0 ” .) P5 2, P74: Function as the status signal OBFx (x = 0, 1). The state of the output buffer DBBx (x = 0, 1) is output. P5 3, P7 3: Function as the status signal IBFx (x = 0, 1). The state of the input buffer DBBx (x = 0, 1) is output. P54, P72: Function as the status signal Sx (x = 0, 1). The chip select signals from the host CPU are input. P5 5: Functions as the status signal A 0. When A 0 i s “ H ” , the host CPU can read the contents of the data bus buffer status register x (x = 0, 1) (addresses 4916, 4D 16). When A 0 is “L”, the contents of data bus buffer register x (x = 0, 1) can be output owing to a read request from the host CPU. When a data is written into the data bus buffer register x (x = 0, 1), if A 0 is “L”, this indicates that its contents are the data; if “ H ” , this indicates that they are the command. P72 to P74 become the master CPU bus interface function pins only when the double data bus buffer mode is used. Tables 2.8.1 and 2.8.2 shows the bus control signal and data bus state; Figure 2.8.6 shows a connection example. Table 2.8.1 Bus control signal and data bus state-RD/WR separate type Sx signal L L L L H RD signal WR signal L L H H – H H L L – A0 s ignal L H L H – Read Read Write Write High-impedance Data bus state Data on data bus Output data DBBSx contents Input data (data) Input data (command) – Table 2.8.2 Bus control signal and data bus state-R/W type Sx signal R/W signal L L L L H H H L L – E signal H H H H – A0 s ignal L H L H – Read Read Write Write High-impedance Data bus state Data on data bus Output data DBBSx contents Input data (data) Input data (command) – Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 111 of 148 APPLICATION 7641 Group 2.8 Master CPU bus interface Host CPU D0 to D7 A A RD WR 7641 group DQ0 to DQ7 Sx Ax R W Host CPU D0 to D7 A A E R/W 7641 group DQ0 to DQ7 Sx Ax E R/W R,W separate type bus R/W type bus Fig. 2.8.6 Connection example (1) Data bus buffer mode The selection of either the single data bus buffer mode or the double data bus buffer mode can be performed by the Data Bus Buffer Function Select Bit. • Single data bus buffer mode The data bus buffer 0 of 1 byte only is used. • Double data bus buffer mode The data bus buffer 0 and data bus buffer 1, totalling 2 bytes, are used. (2) Interrupt • Input buffer full interrupt When the data is input to the data bus buffer register x, the Input Buffer Full Flag (IBFx ; x = 0, 1) is set to “1” and the interrupt request occurs. When the data is read out from the data bus buffer register x, the IBFx flag is cleared to “ 0 ” . • Output buffer empty interrupt When the data is written to the data bus buffer register x, the Output Buffer Full Flag (OBFx ; x = 0, 1) is set to “1”. When the host CPU reads out from the data bus buffer register x, the OBFx flag is cleared to “ 0 ” a nd the output buffer empty interrupt request occurs. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 112 of 148 APPLICATION 7641 Group 2.8 Master CPU bus interface 2.8.4 Operation description (1) Input operation The bus interface input operation is explained as the following: ➀ When the logical OR of Sx (x = 0, 1) and W is “0”, the data bus state is latched into the input data bus buffer register x (x = 0, 1) at the rising of W input signal. ➁ When the data is latched into the input data bus buffer register x, the Input Buffer Full Flag (IBFx ; x = 0, 1) of the data bus buffer status register x (x = 0, 1) is simultaneously set to “ 1 ” . ➂ W hen the IBFx flag is set to “ 1 ” , the input buffer full interrupt request occurs. ➃ A t the timing ➂, the A0 l evel is stored into the A 0 f lag, bit 3 of the data bus buffer status register x. Refer to the A 0 f lag to judge whether the read contents of the input data bus buffer register x are data or a command. (2) Output operation The bus interface output operation is explained as the following: ➀ W riting data to the output data bus buffer register x (x = 0, 1) sets the Output Buffer Full Flag (OBFx ; x = 0, 1) of the data bus buffer status register x to “ 1 ” . ➁ W hen the logical OR of Sx, R and A 0 i s “ 0 ” , the contents of the output data bus buffer register x are output on the data bus and the OBFx flag is simultaneously cleared to “ 0 ” . ➂ A t the rising of the R input signal, the output buffer empty interrupt request occurs. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 113 of 148 APPLICATION 7641 Group 2.8 Master CPU bus interface 2.8.5 Master CPU bus interface application example (1) Data communication with host CPU Outline : The MCU communicates with the host CPU by using the single data bus buffer mode. Figure 2.8.7 shows a setting of the related registers and Figure 2.8.8 shows a control procedure. Data bus buffer control register 0 (address 4A16) b7 b0 DBBC0 00000011 OBF0 output enabled IBF0 output enabled IBF0 interrupt occurrence due to write of data or command Output buffer 0 empty interrupt enabled Input buffer 0 full interrupt enabled Master CPU bus interface disabled (After initialization setting, set this to “1”.) RD, WR separate type bus Data bus buffer control register 1 (address 4E16) b7 b0 DBBC1 00011 00 P74 functions as I/O port. P73 functions as I/O port. Output buffer 1 empty interrupt disabled Input buffer 1 full interrupt disabled Single data bus buffer mode Interrupt control register C (address 0716) b7 b0 ICONC 11 Input buffer full interrupt enabled Output buffer empty interrupt enabled Data bus buffer register 0 (address 4816) b7 b0 DBB0 Data read/write Data bus buffer status register 0 (address 4916) b7 b0 DBBS0 Output buffer full flag Input buffer full flag A0 flag Fig. 2.8.7 Setting of relevant registers Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 114 of 148 APPLICATION 7641 Group 2.8 Master CPU bus interface RESET Initialization DBBC0 (address 4A16) DBBC1 (address 4E16) ICONC(address 0716) DBBC0 (address 4A16),bit6 CLI q x: This bit is not used here. Set it to “0” or “1” arbitrarily. Read Data bus buffer register 0 (command) Note 1: When using Index X mode flag (T) 2: When using Decimal mode flag (D) •Push registers used in interrupt process routine Fig. 2.8.8 Control procedure 2.8.6 N otes on master CPU bus interface Be sure to set port P6 to input mode by setting the port P6 direction register to “0” when the master CPU bus interface is enabled. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 ..... 000000112 00011X002 XX11XXXX2 1 •OBF0, IBF0 output enabled •Output buffer 0 empty interrupt enabled •Input buffer 0 full interrupt enabled •Single data bus buffer mode •Master CPU bus interface enabled ..... Input buffer 0 full interrupt Output buffer 0 empty interrupt CLT (Note 1) CLD (Note 2) Push registers to stack CLT (Note 1) CLD (Note 2) Push registers to stack 0 DBBS0 (address 4916),bit3 ? 1 Write data into Data bus buffer register 0 Read Data bus buffer register 0 (data) Pop registers Pop registers R TI RTI page 115 of 148 APPLICATION 7641 Group 2.9 Special count source generator (SCSG) 2.9 Special count source generator (SCSG) This paragraph explains the registers setting method and the notes related to the special count source generator (SCSG). 2.9.1 Memory map Address 002D16 002E16 002F16 Special count source generator 1 (SCSG1) Special count source generator 2 (SCSG2) Special count source mode register (SCSGM) Fig. 2.9.1 Memory map of registers related to special count source generator Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 116 of 148 APPLICATION 7641 Group 2.9 Special count source generator (SCSG) 2.9.2 Related registers Special count source generator 1 b7 b6 b5 b4 b3 b2 b1 b0 Special count source generator 1 (SCSG1: address 2D16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qThis is a 8-bit down-count timer. The division ratio : 1 / (n1 +1), n1: value set to SCSG1. 1 2 3 4 5 6 7 Fig. 2.9.2 Structure of Special count source generator 1 Special count source generator 2 b7 b6 b5 b4 b3 b2 b1 b0 Special count source generator 2 (SCSG2: address 2E16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qThis is a 8-bit down-count timer. An output from SCSG1 is divided by the contents of SCSG2 to generate SCSGCLK. 1 2 qThe count source, an output from SCSG1, is φ • n1 / (n1 +1). 3 qSCSGCLK frequency: φ • n1 / (n1 +1) • 1 / (n2 +1) n1: value set to SCSG1 4 n2: value set to SCSG2 5 6 7 Fig. 2.9.3 Structure of Special count source generator 2 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 117 of 148 APPLICATION 7641 Group 2.9 Special count source generator (SCSG) Special count source mode register b7 b6 b5 b4 b3 b2 b1 b0 0000 Special count source mode register (SCSGM : address 2F16) b Name Functions 0 : Writing data into both timer latch and timer simultaneously 1 : Writing data into timer latch 0 : Count start 1 : Count stop 0 : Writing data into both timer latch and timer simultaneously 1 : Writing data into timer latch 0 : SCSGCLK output disabled (SCSG1 and SCSG2 counts stop) 1 : SCSGCLK output enabled At reset R W 0 0 SCSG1 data write control bit 1 SCSG1 count stop bit 2 SCSG2 data write control bit 3 SCSGCLK output control bit 4 Fix these bits to “0”. 5 6 7 0 0 0 0 0 0 0 Fig. 2.9.4 Structure of Special count source mode register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 118 of 148 APPLICATION 7641 Group 2.9 Special count source generator (SCSG) 2.9.3 Functional description The special count source generator, SCSG, consists of two 8-bit timers: SCSG1 and SCSG2. The output of the special count source generator can be used as a clock source for the timer X, serial I/O and two UARTs (UART1 and UART2). (1) SCSG1 The SCSG1 is a 8-bit down-count timer. An output from SCSG1 is used as an count source of SCSG2. The division ratio of SCSG1 is given by 1 / (n1 + 1) and the count source of SCSG2 becomes φ ✕ { n1 / (n1 + 1)}. n1: value set to the SCSG1 Writing data to the SCSG1 can be performed anytime. When the SCSG1 data write control bit is set to “0” and data is written to the SCSG1, the data is written to the latch and timer at the same time. When that bit is set to “ 1 ” , the data is only written to the latch. When the count reaches “ 0 ” , an underflow occurs at the next count source rising edge and the contents of the timer latch are loaded to the timer. If the SCSG1 count stop bit is set to “ 1 ” o r the SCSG1 set value is “ 0 ” , this count source φ i s not divided, so that the count source for SCSG2 becomes φ . (2) SCSG2 The SCSG2 is a 8-bit down-count timer. This uses an output from SCSG1 as an count source. The SCSG2 output is Clock SCSGCLK. The frequency is calculated as follows: SCSGCLK = φ ✕ { n1 / (n1+1)} ✕ { 1 / (n2+1)} n1: value set to SCSG1 n2: value set to SCSG2 Writing data to the SCSG2 can be performed anytime. When the SCSG2 data write control bit is set to “0” and data is written to the SCSG2, the data is written to the latch and timer at the same time. When that bit is set to “ 1 ” , the data is only written to the latch. When the count reaches “ 0 ” , an underflow occurs at the next count source rising edge and the contents of the timer latch are loaded to the timer. If the SCSGCLK output control bit is set to “ 0 ” , the SCSG1 and SCSG2 stop their counts and SCSGCLK output is disabled. To use the SCSGCLK, set this bit to “ 1 ” . Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 119 of 148 APPLICATION 7641 Group 2.10 External devices connection 2.10 External devices connection This paragraph explains the registers setting method and the notes related to the external devices connection. 2.10.1 Memory map Address 000016 000116 CPU mode register A (CPMA) CPU mode register B (CPMB) Fig. 2.10.1 Memory map of registers related to external devices connection Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 120 of 148 APPLICATION 7641 Group 2.10 External devices connection 2.10.2 Related registers CPU mode register A b7 b6 b5 b4 b3 b2 b1 b0 1 CPU mode register A (CPMA : address 0016) b Name b1b0 Functions 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode (Note 1) 1 1 : Not available 0 : Page 0 1 : Page 1 0 : Stopped 1 : Oscillating 0 : Oscillating 1 : Stopped 0 : External clock (XIN-XOUT or XCIN-XCOUT) 1 : fsyn 0 : XIN-XOUT 1 : XCIN-XCOUT At reset R W 0 0 1 1 0 0 0 0 0 Processor mode bits 1 2 Stack page select bit 3 Fix this bit to “1”. 4 Sub-clock (XCIN-XCOUT) stop bit 5 Main clock (XIN-XOUT) stop bit 6 Internal system clock select bit (Note 2) 7 External clock select bit Notes 1: This is not available in the flash memory version. 2: When (CPMA 7, 6) = (0, 0), the internal system clock can be selected between f(XIN) and f(XIN)/2 by CCR7. The internal clock φ is the internal system clock divided by 2. Fig. 2.10.2 Structure of CPU mode register A CPU mode register B b7 b6 b5 b4 b3 b2 b1 b0 10 CPU mode register B (CPMB : address 0116) b Name b1b0 Functions 0 0 : No wait 0 1 : One-time wait 1 0 : Two-time wait 1 1 : Three-time wait b3b2 At reset R W 1 1 0 0 0 Slow memory wait select bits 1 2 Slow memory wait mode select bits 3 0 0 : Software wait 0 1 : Not available 1 0 : RDY wait 1 1 : Software wait plus RDY input anytime wait anytime wait 0 : EDMA output disabled 1 : EDMA output enabled 0 : HOLD function disabled 1 : HOLD function enabled 4 Expanded data memory access bit 5 HOLD function enable bit 6 Fix this bit to “0”. 7 Fix this bit to “1”. 0 0 0 1 Fig. 2.10.3 Structure of CPU mode register B Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 121 of 148 APPLICATION 7641 Group 2.10 External devices connection 2.10.3 Functional description This MCU starts its operation in the single-chip mode just after reset. (1) Memory expansion mode This mode is selected by setting “01” to the processor mode bits (b1, b0 of CPMA) in software with CNV SS c onnected to V SS. In this mode, the ports function as follows: Ports P0 and P1 as address buses (AB 0 t o AB 15) Port P2 as data buses (DB0 t o DB 7) ______ ______ Ports P3 3 t o P3 7 a s DMAOUT, φ OUT, SYNCOUT, WR, RD pins respectively. This mode enables external memory expansion while maintaining the validity of the internal ROM. (2) Microprocessor mode This mode is selected by resetting the MCU with CNVSS c onnected to V CC, or by setting “ 10 ” t o the processor mode bits (b1, b0 of CPMA) in software with CNV SS connected to V SS. The function is the same as that of memory expansion mode. In the microprocessor mode, the internal ROM is no longer valid and an external memory must be used. Do not set this mode in the flash memory version. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 122 of 148 APPLICATION 7641 Group 2.10 External devices connection 2.10.4 Slow memory wait The slow memory wait function is for easier interfacing with external devices that have long access times. This can be enabled in the memory expansion mode and microprocessor mode. The wait is effective only to external areas. Access to internal area is always performed without wait. (1) Software wait The software wait is selected by setting “ 00 ” t o the slow memory wait mode select bits (b3, b2 of CPMB). Figure 2.10.4 shows the software wait timing example. > 1 bus cycle φ OUT ADOUT DB IN/OUT RD WR Address Address IN OUT Note : Accessing to internal areas is always performed on this waveform. > 1 bus cycle φ OUT ADOUT DB IN/OUT RD WR Address IN Address OUT Note : This example is the 1-cycle software wait. Refer to Chapter 1 “ Slow Memory Wait in PROCESSOR MODE ” f or 2- and 3-cycle software wait timings. Fig. 2.10.4 Software wait timing example Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 123 of 148 APPLICATION 7641 Group 2.10 External devices connection (2) RDY wait RDY wait is selected by setting “ 10 ” t o the slow memory wait mode select bits (b3, b2 of CPMB). When a fixed time of “L” (tsu) is input to the RDY pin at the beginning of a read/write cycle (before φ c ycle falls), the MCU goes to the RDY state. Then the read/write cycle can be extended by one to three φ cycles. The number of φ cycles to be extended can be selected by the slow memory wait select bits (b1, b0 of CPMB). Even if “ L ” i s input to the RDY pin at the end of waited read/write cycle, the cycle is not extended. When a fixed time of “H” (tsu) is input to the RDY pin at the beginning of a read/write cycle (before φ c ycle falls), the MCU is released from the RDY state. Figure 2.10.5 shows the RDY wait timing example. > 1 bus cycle φ OUT ADOUT DB IN/OUT RD WR Address Address IN OUT > 1 bus cycle φ OUT ADOUT DB IN/OUT RD WR Address IN Address OUT tsu(RDY- φ ) tsu(RDY- φ ) RDY Note : This example is the 1-cycle RDY wait . Refer to Chapter 1 “ Slow Memory Wait in PROCESSOR MODE ” f or 2- and 3-cycle RDY wait timings. Fig. 2.10.5 RDY wait timing example Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 124 of 148 APPLICATION 7641 Group 2.10 External devices connection (3) Software wait + Extended RDY wait Extended RDY wait (software wait plus RDY input anytime wait) is selected by setting “ 11 ” t o the slow memory wait mode select bits (b3, b2 of CPMB). The read/write cycle can be extended when a fixed time (tsu) of “L” is input to the RDY pin at the beginning of a read/write cycle (before φ cycle falls). The RDY pin state is checked continually at each fall of φ cycle until the RDY pin goes to “H” and the cycle keeps being extended. When a fixed time of “ H ” ( tsu) is input to the RDY pin at the beginning of a read/write cycle (before φ cycle falls), the MCU is released from the wait within 1, 2, or 3 φ c ycles as selected with the slow memory wait bits (b1, b0 of CPMB). Figure 2.10.6 shows the extended RDY wait (software wait plus RDY input anytime wait) timing example > 1 bus cycle φ OUT ADOUT DB IN/OUT RD WR Address Address IN OUT > 1 bus cycle φ OUT ADOUT DB IN/OUT RD WR tsu Address IN tsu tsu tsu RDY 1 2 3 4 1. When a fixed time (tsu) of “L” is input to the RDY pin before φ falls, the MCU goes to RDY state. 2. The RDY pin state is checked continually at each fall of φ cycle. 3. The RDY pin is “L” at the φ fall of the end of the current wait time, so that the read/write cycle is extended for one wait once again. 4. When a fixed time (tsu) of “H” is input to the RDY pin before φ falls, the RDY state is released after the current wait time. Note : This example is the 1-cycle extended RDY wait (RD). The 1-cycle extended RDY wait (WR) is the same timing as this. Refer to Chapter 1 “ Slow Memory Wait in PROCESSOR MODE ” f or 2- and 3-cycle extended RDY wait timings. Fig. 2.10.6 Extended RDY wait (software wait plus RDY input anytime wait) timing example Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 125 of 148 APPLICATION 7641 Group 2.10 External devices connection 2.10.5 HOLD function The HOLD function is used for systems that consist of external circuits that access MCU buses without use of the CPU (Central Processing Unit). The HOLD function is used to generate the timing in which the MCU will relinquish the bus from the CPU to the external circuits. To use the HOLD function, set the HOLD function enable bit (b5 of CPMB) to “1”. This can be enabled in the memory expansion mode and microprocessor mode. When “ L ” l evel is input to the HOLD pin, the MCU goes to the HOLD state and remains so while the pin is at “L”. When the MCU relinquishes use of the bus, “L” level is output from the HLDA pin. The MCU puts ports P0 and P1 (address buses) and port P2 (data bus) to tri-state outputs and holds the RD pin (P3 7) and WR pin (P3 6) “ H ” l evel. This will prevent incorrect operations of external devices. Though the clock supply to the CPU halts in HOLD state, the internal peripheral clocks and φ OUT ( P3 4) continues to be supplied. When “ H ” l evel is input to the HOLD pin, “ H ” l evel is output from the HLDA pin and the MCU can use address buses, data bus, signals RD and WR to access to external devices. Figure 2.10.7 shows the Hold function timing diagram. XIN φ OUT RD, WR ADDROUT DATAIN/OUT tsu(HOLD-φ) HOLD HLDA td(φ-HLDAL) td(φ-HLDAH) th(φ-HOLD) Note: This diagram assumes φ = XIN/2. Fig. 2.10.7 Hold function timing diagram Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 126 of 148 APPLICATION 7641 Group 2.10 External devices connection 2.10.6 Expanded data memory access In Expanded Data Memory Access Mode (EDMA mode), the MCU can access a data area larger than 64 Kbytes with the LDA ($zz), Y (indirect Y) instruction and the STA ($zz), Y (indirect Y) instruction. It is only able to store and read data for the expanded data memory area. The access can be performed with T flag = “ 0 ” o r “ 1 ” . (T flag is Index X mode flag.) To use this mode, set the expanded data memory access bit (b4 of CPMB) to “1”. In this case, EDMA pin (port P40) goes “ L ” l evel during the read/write cycle of the LDA or STA instruction. The determination of which bank to access is done by using an I/O port to represent expanded addresses exceeding address bus (AB 15)16. This signal and the port output signal are put together, and it becomes the chip select (selecting a bank, expanded memory). In EDMA mode, the area from addresses 0000 16 t o FFFF 16 c an be accessed. When accessing a bank, follow this procedure (four banks are assumed): - Bank specification (Data output to the port for a bank setup 16 (AB 16), and 16 (AB 17)). The user must setup 16 (AB 16), and 16 (AB 17). __________ - Enabling EDMA output. (Set b4 of CPMB to “ 1 ” .) - Executing LDA ($zz), Y (indirect Y) (In the case of read data of expanded data memory) The data of the address (bank 0) + Y stored in the internal RAM address ($zz) are loaded to the accumulator. Figure 2.10.8 shows a connection example of memory access up to 256 Kbytes. Decoder CS0 7641 group E EDMA P80 P81 DB0 to DB7 AB0 to AB15 RD WR 8 16 CS1 CS2 CS3 74HC139 64K RAM BANK0 64K RAM BANK1 64K RAM BANK2 64K RAM BAN K3 Fig. 2.10.8 Connection example of memory access up to 256 Kbytes Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 127 of 148 APPLICATION 7641 Group 2.10 External devices connection 2.10.7 External devices connection example Connection example for controlling external memory is shown bellow. (1) External memory connection example : No Wait function Outline: I n microprocessor mode the external memory is accessed. Figure 2.10.9 shows the external ROM and RAM example. 7641 Group CNVss RDY 2 AD15 74F04 M5M27C256AK-10 CE AD14 to AD0 15 M5M256BP S P31, P32 5 P4 A0 to A14 EPROM A0 to A14 SRAM 8 P5 DB0 to DB7 8 D0 to D7 DQ1 to DQ8 Memory map 8 P6 5 P7 8 OE OE W 000016 SFR area 000816 External RAM area 001016 SFR area 007016 Internal RAM area 047016 External RAM area P8 RD WR Vcc = 4.15 to 5.25 V 24 MHz 800016 External ROM area FFFF16 Fig. 2.10.9 External ROM and RAM example Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 128 of 148 APPLICATION 7641 Group 2.10 External devices connection (2) External memory connection example : RDY function (one wait) in use Outline: R DY function is used because the external memory has a slow-memory-access speed. Specifications: •In read/write status of the CPU, input “L” to the RDY(P30) pin will cause extension of 1 to 3 φ c ycles on its read/write cycle. • When the slow memory wait select bit (b1, b0) is = “ 01 ” , it is extended by one cycle. ______ ______ • RD/WR signal holds “ L ” l evel during the extended time. • Usable RAM and ROM at f(X IN) = 24 MHz, Vcc = 5 V are given bellow: - OE access time : ta(OE) ≤ 1 07 ns - Data setup time at write : tsu(D) ≤ 1 00 ns - Examples satisfying these specifications: M5M27C256AK-10 (EPROM), M5M5256BP-10 (SRAM) Figure 2.10.10 shows the RDY function use example, and Figures 2.10.11 to 2.10.13 show the read and write cycles. 7641 Group CNVss AD15 74F04 2 M5M27C256AK-10 CE M5M256BP S P31, P32 RDY AD14 to AD0 15 5 P4 A0 to A14 EPROM A0 to A14 SRAM 8 P5 DB0 to DB7 8 D0 to D7 DQ1 to DQ8 Memory map OE W 000016 SFR area 000816 External RAM area 001016 SFR area 007016 Internal RAM area 047016 External RAM area 8 P6 5 P7 8 OE P8 RD WR Vcc = 4.15 to 5.25 V 24 MHz 800016 External ROM area FFFF16 Fig. 2.10.10 RDY function use example Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 129 of 148 APPLICATION 7641 Group 2.10 External devices connection AB0 to AB7 (Port P0) Lower address AB8 to AB14 (Port P1) Upper address S (AB15) OE (RD of 7641) td(AH-RD): 0.5 • 83.33 ns – 28 ns (min.) td(AL-RD): 0.5 • 83.33 ns – 30 ns (min.) DB0 to DB7 (Port P2) twl(RD) (1 + 0.5) • 83.33 ns – 5 ns (min.) ta(OE) 50 ns (max.) tsu(DB-RD) 13 ns (min.) WR “H” level td(AH-RD), td(AL-RD) : AB15-AB8, AB7-AB0 valid time before RD of 7641 group twl(RD) : RD pulse width of 7641 group ta(OE) : Output enable access time of M5M256BP-10 tsu(DB-RD) : Data bus setup time before RD of 7641 group f(XIN) = 24 MHz Vcc = 5 V Fig. 2.10.11 Read cycle (OE access, SRAM) AB0 to AB7 (Port P0) Lower address AB8 to AB14 (Port P1) Upper address CE tPHL 5.8 ns (max.) twl(RD) (1 + 0.5) • 83.33 ns – 5 ns (min.) ta(OE) 50 ns (max.) tsu(DB-RD) 13 ns (min.) OE (RD of 7641) td(AH-RD): 0.5 • 83.33 ns – 28 ns (min.) td(AL-RD): 0.5 • 83.33 ns – 30 ns (min.) DB0 to DB7 (Port P2) WR “H” level td(AH-RD), td(AL-RD) : AB15-AB8, AB7-AB0 valid time before RD of 7641 group twl(RD) : RD pulse width of 7641 group tPHL : Output delay time of 74F04 ta(OE) : Output enable access time of M5M27C256AK-10 tsu(DB-RD) : Data bus setup time before RD of 7641 group f(XIN) = 24 MHz Vcc = 5 V Fig. 2.10.12 Read cycle (OE access, EPROM) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 130 of 148 APPLICATION 7641 Group 2.10 External devices connection AB0 to AB7 (Port P0) Lower address AB8 to AB14 (Port P1) Upper address S (AB15) W (WR of 7641) twl(WR) (1 + 0.5) • 83.33 ns – 5 ns (min.) td(AH-RD): 0.5 • 83.33 ns – 28 ns (min.) td(AL-RD): 0.5 • 83.33 ns – 30 ns (min.) td(WR-DB) 20 ns (max.) DB0 to DB7 (Port P6) tsu(D) 35 ns (min.) OE (RD of 7641) “H” level td(AH-WR), td(AL-WR) : AB15-AB8, AB7-AB0 valid time before WR of 7641 group twl(WR) : WR pulse width of 7641 group td(WR-DB) : Data bus delay time after WR of 7641 group tsu(D) : Data setup time of M5M256BP-10 f(XIN) = 24 MHz Vcc = 5 V Fig. 2.10.13 Write cycle (W control, SRAM) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 131 of 148 APPLICATION 7641 Group 2.10 External devices connection 2.10.8 Notes on external devices connection (1) Rewrite port P3 latch In both memory expansion mode and microprocessor mode, ports P31 and P32 can be used as output ports. We recommend to use the L DM i nstruction or S TA i nstruction to write to port P3 register (address 000E 16). If using the Read-Modify-Write instruction (SEB i nstruction, C LB i nstruction) you will need to map a memory that the CPU can read from and write to. [Reason] The access to address 000E16 i s performed: • Read from external memory • Write to both port P3 latch and external memory. It is because address 000E16 i s assigned on an external area In the memory expansion mode and microprocessor mode. Accordingly, if a Read-Modify-Write instruction is executed to address 000E 16, the external memory contents is read out and after its modification it will be written into both port P3 latch and an external memory. As a result, if an external memory is not allocated in address 000E16 then, the MCU will read an undefined value and write its modified value into the port P3 latch. Therefore port P3 latch value will become undefined. (2) overlap of internal and external memories In the memory expansion mode, if the internal and external memory areas overlap, the internal memory becomes the valid memory for the overlapping area. When the CPU performs a read or a write operation on this overlapped area, the following things happen: •Read The CPU reads out the data in the internal memory instead of in the external memory. Note that, since the CPU will output a proper read signal, address signal, etc., the memory data at the respective address will appear on the external data bus. •Write The CPU writes data to both the internal and external memories. _____ ______ (3) RD, WR pins In the memory expansion mode or microprocessor mode, a read-out control signal is output from the ______ ______ RD ______ (P3 6), and a write-in control signal is output from the WR pin (P3 7). “ L ” l evel is output from pin ______ the RD pin at CPU read-out and from the WR pin at CPU write-in. These signals function for internal access and external access. __________ (4) HLDA pin __________ In spite of enabling the Hold function, the HLDA pin does not function when IBF1 output is enabled in the master CPU bus interface. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 132 of 148 APPLICATION 7641 Group 2.10 External devices connection (5) RDY function When using RDY function in usual connection, it does not operate at 12 MHz of φ o r faster. [Reason] td( φ -AH) + tsu(RDY- φ ) = 31 ns (max.) + 21 ns (min.) = 52 ns. twh ( φ ), twl ( φ ) = 0.5 ✕ 8 3.33 – 5 = 3 6.665 ns Therefore, it becomes 52 ns > 36.665 ns, so that the timing to enter RDY wait does not match. ________ However, if the timings can match owing to RDY pin by “L” fixation and others, the RDY function can be used even at φ = 1 2 MHz. In this situation the slow memory wait always functions. (6) Wait function The Wait function is serviceable at accessing an external memory in the memory expansion mode and microprocessor mode. However, in these modes even if an external memory is assigned to addresses 0008 16 t o 000F 16, the Wait function cannot function to these areas. (7) Processor mode switch Note when the processor mode is switched by setting of the processor mode bits (b1, b0 of CPMA), that will immediately switch the accessible memory from external to internal or from internal to external. If this is done, the first cycle of the next instruction will be operated from the accidental memory. To prevent this problem, follow the procedure below: (a) Duplicate the next instruction at the same address both in internal and external memories. (b) Switch from single-chip mode to memory expansion mode, jump to external memory, and then switch from memory expansion mode to microprocessor mode. (Because in general, the problem will not occur when switching the modes as long as the same memory is accessed after the switch. (c) Load a simple program in RAM that switches the modes, jump to RAM and execute the program, then jump to the location of the code to run after the processor mode has switched. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 133 of 148 APPLICATION 7641 Group 2.11 Reset 2.11 Reset 2.11.1 Connection example of reset IC Figure 2.11.1 shows the system example which switches to the RAM backup mode by detecting a drop of the system power source voltage with the INT interrupt. System power source voltage +5 V + VCC1 RESET VC C RESET VCC2 INT INT VSS V1 GND Cd 7641 Group M62009L, M62009P, M62009FP Fig. 2.11.1 RAM backup system 2.11.2 Notes on reset (1) Connecting capacitor In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the V SS p in. Use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following : • M ake the length of the wiring which is connected to a capacitor as short as possible. • B e sure to verify the operation of application products on the user side. q R eason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may cause a microcomputer failure. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 134 of 148 APPLICATION 7641 Group 2.12 Clock generating circuit 2.12 Clock generating circuit This paragraph explains the registers setting method and the notes related to the clock generating circuit. Besides, two modes to realize less power dissipation due to the CPU and some peripherals halted are explained: Stop mode due to STP instruction, Wait mode due to WIT instruction. 2.12.1 Memory map Address 000016 001F16 006C16 006D16 006E16 006F16 CPU mode register A (CPMA) Clock control register (CCR) Frequency synthesizer control register (FSC) Frequency synthesizer multiply register 1 (FSM1) Frequency synthesizer multiply register 2 (FSM2) Frequency synthesizer divide register (FSD) Fig. 2.12.1 Memory map of registers related to clock generating circuit Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 135 of 148 APPLICATION 7641 Group 2.12 Clock generating circuit 2.12.2 Related registers CPU mode register A b7 b6 b5 b4 b3 b2 b1 b0 1 CPU mode register A (CPMA : address 0016) b Name b1b0 Functions 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode (Note 1) 1 1 : Not available 0 : Page 0 1 : Page 1 0 : Stopped 1 : Oscillating 0 : Oscillating 1 : Stopped 0 : External clock (XIN-XOUT or XCIN-XCOUT) 1 : fsyn 0 : XIN-XOUT 1 : XCIN-XCOUT At reset R W 0 0 1 1 0 0 0 0 0 Processor mode bits 1 2 Stack page select bit 3 Fix this bit to “1”. 4 Sub-clock (XCIN-XCOUT) stop bit 5 Main clock (XIN-XOUT) stop bit 6 Internal system clock select bit (Note 2) 7 External clock select bit Notes 1: This is not available in the flash memory version. 2: When (CPMA 7, 6) = (0, 0), the internal system clock can be selected between f(XIN) and f(XIN)/2 by CCR7. The internal clock φ is the internal system clock divided by 2. Fig. 2.12.2 Structure of CPU mode register A Clock control register b7 b6 b5 b4 b3 b2 b1 b0 00000 Clock control register (CCR : address 1F16) b Name Functions At reset R W 0 0 0 0 0 0 Fix these bits to “0”. 1 2 3 4 5 XCOUT oscillation drive disable bit (CCR5) 6 XOUT oscillation drive disable bit (CCR6) 7 XIN divider select bit (CCR7) (Note) 0 : XCOUT oscillation drive is enabled. (When XCIN oscillation is enabled.) 1 : XCOUT oscillation drive is disabled. 0 : XOUT oscillation drive is enabled. (When XIN oscillation is enabled.) 1 : XOUT oscillation drive is disabled. 0 : f(XIN)/2 is used for the system clock. 1 : f(XIN) is used for the system clock. 0 0 0 Note: This bit is valid when (b7, b6 of CPMA) = “00”. Fig. 2.12.3 Structure of Clock control register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 136 of 148 APPLICATION 7641 Group 2.12 Clock generating circuit Frequency synthesizer control register b7 b6 b5 b4 b3 b2 b1 b0 0 00 Frequency synthesizer control register (FSC : address 6C16) b Name 0 : Disabled 1 : Enabled Functions At reset R W 0 0 0 0 0 0 Frequency synthesizer enable bit (FSE) 1 Fix these bits to “0”. 2 3 Frequency synthesizer input bit (FIN) 4 Fix this bit to “0”. 5 LPF current control bit (CHG1, CHG0) (Note) 6 7 Frequency synthesizer lock status bit 0 : f(XIN) 1 : f(XCIN) b1b0 0 0 : Not available 0 1 : Low current 1 0 : Intermediate current (recommended) 1 1 : High current 0 : Unlocked 1 : Locked 1 1 0 Note: Bits 6 and 5 are set to (bit 6, bit 5) = (1, 1) at reset. When using the frequency synthesizer, we recommend to set to (bit 6, bit 5) = (1, 0) after locking the frequency synthesizer. Fig. 2.12.4 Structure of Frequency synthesizer control register Frequency synthesizer multiply register 1 b7 b6 b5 b4 b3 b2 b1 b0 Frequency synthesizer multiply register 1 (FSM1: address 6D16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qfVCO clock is generated by multiplying fPIN clock, which is generated by FSM2, by the contents of this register: 1 2 fVCO = fPIN • {2(n +1)}, n: value set to FSM1. 3 4 5 6 7 Fig. 2.12.5 Structure of Frequency synthesizer multiply register 1 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 137 of 148 APPLICATION 7641 Group 2.12 Clock generating circuit Frequency synthesizer multiply register 2 b7 b6 b5 b4 b3 b2 b1 b0 Frequency synthesizer multiply register 2 (FSM2: address 6E16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qfPIN clock is generated by dividing fIN clock by the contents of this register. 1 Either f(XIN) or f(XCIN) as an input clock fIN for the frequency 2 synthesizer is selectable. 3 4 fPIN = fIN / {2(n +1)}, n: value set to FSM2 5 6 7 Fig. 2.12.6 Structure of Frequency synthesizer multiply register 2 Frequency synthesizer divide register b7 b6 b5 b4 b3 b2 b1 b0 Frequency synthesizer divide register (FSD: address 6F16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qfSYN clock is generated by dividing fVCO clock by the contents of this register: 1 2 fSYN = fVCO / {2(m +1)}, m: value set to FSD 3 4 5 6 7 Fig. 2.12.7 Structure of Frequency synthesizer divide register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 138 of 148 APPLICATION 7641 Group 2.12 Clock generating circuit 2.12.3 Stop mode The Stop mode is set by executing the STP instruction. In Stop mode, the oscillation of both clocks (XIN– XOUT, X CIN–XCOUT) stop and the internal clock φ stops at the “H” level. The CPU stops and peripheral units stop operating. As a result, power dissipation is reduced. (1) State in Stop mode Table 2.12.1 shows the state in Stop mode. Table 2.12.1 State in Stop mode Item Oscillation CPU Internal clock φ I/O ports Timer UART DMAC Serial I/O USB RAM SFR CPU registers Stopped. Stopped. Stopped at “ H ” l evel. Retains the state at the STP instruction execution. When using internal count source: Stopped. When using external count source: Operating. Stopped. Stopped. When using internal syncronous clock: Stopped. When using external syncronous clock: Operating. Stopped. Retained. Retained (except for Timer 1, Timer 2). Retained: Accumulator, Index register X, Index register Y, Stack pointer, Program counter, Processor status register. State in Stop mode (2) Release of Stop mode The Stop mode is released by a reset input or by the occurrence of an interrupt request. These interrupt sources can be used for restoration: • INT 0, INT 1 •CNTR 0, CNTR1 • Timers X, Y using an external count source • Serial I/Os using an external clock •Key-on wake-up • USB function resume However, when using any of these interrupt requests for restoration from Stop mode, i n order to enable the selected interrupt, set the following conditions before execution of STP instruction. [Necessary register setting] ➀ T imer 1 interrupt enable bit (b6 of ICONB) = “ 0 ” ( interrupt disabled) ➁ T imer 2 interrupt enable bit (b7 of ICONB) = “ 0 ” ( interrupt disabled) ➂ T imer 1 interrupt request bit (b6 of IREQB) = “ 0 ” ( no interrupt request issued) ➃ T imer 2 interrupt request bit (b7 of IREQB) = “ 0 ” ( no interrupt request issued) ➄ Interrupt request bit of interrupt source to be used for restoration = “0” (no interrupt request issued) ➅ I nterrupt enable bit of interrupt source to be used for restoration = “ 1 ” ( interrupts enabled) ➆ I nterrupt disable flag I = “ 0 ” ( interrupt enabled) (3) Notes on STP instruction • Execution of STP instruction clears the timer 123 mode register (address 29 16) except bit 4 to “ 0 ” . •When using fSYN as the internal system clock, switch to f(XIN) or f(XCIN) before execution of STP instruction. • Execution of STP instruction clears bit 7 of clock control register to “ 0 ” ( f(X IN)/2). Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 139 of 148 APPLICATION 7641 Group 2.12 Clock generating circuit 2.12.4 Wait mode The Wait mode is set by execution of the WIT instruction. In Wait mode, oscillation continues, but the internal clock φ s tops at the “ H ” l evel. The CPU stops, but most of the peripheral units continue operating. (1) State in Wait mode Table 2.12.2 shows the state in Wait mode. Table 2.12.2 State in Wait mode Item Oscillation CPU Internal clock φ I/O ports Timer UART DMAC Serial I/O USB RAM SFR CPU registers Oparating. Stopped. Stopped at “ H ” l evel. Retains the state at the WIT instruction execution. Operating. Operating. Stopped. Operating. Operating. Retained. Retained. Retained: Accumulator, Index register X, Index register Y, Stack pointer, Program counter, Processor status register. State in Wait mode (2) Release of wait mode The Wait mode is released by reset input or by the occurrence of an interrupt request. In Wait mode oscillation is continued, so that an instruction can be executed immediately after the Wait mode is released. These interrupt sources can be used for restoration: • INT0, INT1 •CNTR0, CNTR1 •Timers • Serial I/Os •UART •DMAC •Key-on wake-up • Master CPU bus interface •USB function • USB SOF However, when using any of these interrupt requests for restoration from Stop mode, i n order to enable the selected interrupt, set the following conditions before execution of WIT instruction. [Necessary register setting] ➀ Interrupt request bit of interrupt source to be used for restoration = “0” (no interrupt request issued) ➁ I nterrupt enable bit of interrupt source to be used for restoration = “ 1 ” ( interrupts enabled) ➂ I nterrupt disable flag I = “ 0 ” ( interrupt enabled) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 140 of 148 APPLICATION 7641 Group 2.12 Clock generating circuit 2.12.5 Clock generating circuit application examples (1) Status transition during power failure Outline: T he clock is counted up every one second by using the timer interrupt during a power failure. Input port (Note) Power failure detection signal 7641 Group Note: A signal is detected when input to input port, interrupt input pin, or analog input pin. Fig. 2.12.8 Connection diagram Specifications: • Reducing power dissipation as low as possible while maintaining clock function • Clock: f(X IN) = 4.19 MHz, f(X CIN) = 32.768 kHz •Port processing Input port: Fixed to “ H ” o r “ L ” l evel on the external Output port: Fixed to output level that does not cause current flow to the external (Example) When a circuit turns on LED at “ L ” o utput level, fix the output level to “ H ” . I/O port: Input port → F ixed to “ H ” o r “ L ” l evel on the external Output port → O utput of data that does not consume current Figure 2.12.9 shows the status transition diagram during power failure and Figure 2.12.10 shows the setting of relevant registers. Reset released Power failure detected XIN XCIN Internal system clock Middle-speed mode High-speed mode Low-speed mode Change internal system clock to high-speed mode After detection, change internal system clock to low-speed mode and stop oscillating XIN-XOUT XCIN-XCOUT oscillation function selected Fig. 2.12.9 Status transition diagram during power failure Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 141 of 148 APPLICATION 7641 Group 2.12 Clock generating circuit Clock control register (address 1F16) b7 b0 CCR 00000 0 : Middle-speed mode (f(XIN)/2) 1 : High-speed mode (f(XIN)) CPU mode register A (address 0016) b7 b0 CPMA 00011 Sub-clock f(XCIN) oscillating Main-clock f(XIN) oscillating Main-clock f(XIN) selected CPU mode register A (address 0016) b7 b0 CPMA 1 0 1 1 1 Sub-clock f(XCIN) oscillating Main-clock f(XIN) stopped Sub-clock f(XCIN) selected Fig. 2.12.10 Setting of relevant registers Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 142 of 148 APPLICATION 7641 Group 2.12 Clock generating circuit Control procedure: S et the relevant registers in the order shown below to prepare for a power failure. RESET qX: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization CCR (address 1F16) CPMA (address 0016) •••• •••• 100000002 00011XXX2 When selecting main clock f(XIN) (high-speed mode) Detect power failure ? Y CPMA (address 0016), bit 7 CPMA (address 0016), bit5 1 (Note) 1 (Note) N ≈ f(XCIN) (low-speed mode) selected as internal system clock Main clock f(XIN) oscillation stopped Set timer interrupt to occurs every second. Execute WIT instruction. At power failure, clock count is performed during timer interrupt processing (every second). N Return condition from power failure completed ? Y Return processing from power failure Note: Do not switch simultaneously. ≈ Fig. 2.12.11 Control procedure Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 143 of 148 APPLICATION 7641 Group 2.12 Clock generating circuit (2) Counting without clock error during power failure Outline: I t keeps counting without clock error during a power failure. Specifications: • Reducing power consumption as low as possible while maintaining clock function • Clock: f(X IN) = 24 MHz • Sub clock: f(X CIN) = 32.768 kHz • Use of Timer 2 interrupt For the peripheral circuit and the status transition during a power failure, refer to Figures 2.12.8 and 2.12.9. Figure 2.12.12 shows the structure of clock counter, Figures 2.12.13 and 2.12.14 show the setting of relevant registers. Timer 1 interrupt Timer 1 Base counter 1 second counter 1 minute counter f(XIN) = 24 MHz 1/2 1/8 1/255 170 µs 1/245 1/24 1s 1/60 Minute/Time/Day/Month/Year When the system returns from a power failure, add the time taken for the switching processing for the return. Timer 2 interrupt Timer 1 Timer 2 f(XCIN) = 32.768 kHz 1/2 1/3 183 µs 1/228 1/24 : Software timer : Hardware timer Fig. 2.12.12 Structure of clock counter Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 144 of 148 APPLICATION 7641 Group 2.12 Clock generating circuit CPU mode register A (address 0016) b7 b0 CPMA 00011 XCIN-XCOUT oscillating XIN-XOUT oscillating External clock selected as internal system clock f(XIN) selected as external clock; f(XCIN) selected at power failure Clock control register (address 1F16) b7 b0 CCR 1 00000 XIN division: f(XIN) (high-speed mode) Timer 1 (address 2416) b7 b0 T1 254 Set (Division ratio -1); 254 (FE16) Timer 123 mode register (address 2916) b7 b0 T123M 0 000 Timer 1 count: Operating Timer 1 count source: φ/8 Timer 2 count source: Timer 1 output Timer 1, 2 write: Write value in latch and counter Interrupt request register B (address 0316) b7 b0 IREQB 00 Set “0” to timer 1 interrupt request bit Set “0” to timer 2 interrupt request bit Interrupt control register B (address 0616) b7 b0 ICONB 01 Timer 1 interrupt: Enabled Timer 2 interrupt: Disbled Fig. 2.12.13 Initial setting of relevant registers Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 145 of 148 APPLICATION 7641 Group 2.12 Clock generating circuit Timer 123 mode register (address 2916) b7 b0 T123M 0 010 Timer 1 count: Operating Timer 1 count source: f(XCIN)/2 Timer 2 count source: Timer 1 output Timer 1, 2 write: Write value in latch and counter Interrupt control register B (address 0616) b7 b0 ICONB 10 Timer 1 interrupt: Disabled Timer 2 interrupt: Enbled CPU mode register A (address 0016) b7 b0 CPMA 10111 XCIN-XCOUT oscillating XIN-XOUT stopped External clock selected as internal system clock f(XCIN) selected as external clock Timer 1 (address 2416) b7 b0 T1 02 Set (Division ratio -1) (T1 = 2 (0216), T2 = 227 (E216) b0 Timer 2 (address 2516) b7 T2 227 Fig. 2.12.14 Setting of relevant registers after detecting power failure Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 146 of 148 APPLICATION 7641 Group 2.12 Clock generating circuit Control procedure: S et the relevant registers in the order shown below to prepare for a power failure. RESET qX: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization CPMA (address 0016) CCR (address 1F16) T1 (address 2416) T123M (address 2916) IREQB (address 3C16), bit 7, bit 6 Base counter (internal RAM) 1 second counter (internal RAM) ICONB (address 0616), bit 6 •••• 00011XXX2 1XX000002 FE16 0XX0X00X2 0,0 F516 1816 1 When selecting main clock f(XIN) (high-speed mode) Setting for making base and one second counters activate during timer 1 interrupt In the normal power state, these software counters generate one second. •••• CLI Detect power failure ? Y T123M (address 2916), bit 2 ICONB (address 0616), bit 6 CPMA (address 0016), bit 7 CPMA (address 0016), bit 5 IREQB (address 0616), bit 7, bit 6 T1 (address 2416) T2 (address 2516) 1 0 1 (Note) 1 (Note) 0, 0 0216 E216 N ≈ Timer 1 count source: f(XCIN) Timer 1 interrupt: Disabled Internal system clock: f(XCIN) (low-speed mode) Main clock f(XIN): Oscillation stopped Setting for generating timer 2 interrupt every second Generation of one second by hardware timer during power failure ICONB (address 0616), bit 7 1 Execute WIT instruction Timer 2 interrupt: Enabled N Return condition for power failure is satisfied ? Y Return processing from power failure Timer 2 interrupt occurs every second (return from wait mode) ≈ Fig. 2.12.15 Control procedure (1) Note: Do not switch at one time. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 147 of 148 APPLICATION 7641 Group 2.12 Clock generating circuit Timer 2 interrupt routine Push registers to stack etc. •••• Count 1 minute (internal RAM) counter 1 minute counter overflow ? N Y Modify time, day, month, year ≈ RTI Fig. 2.12.16 Control procedure (2) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 148 of 148 C HAPTER 3 APPENDIX 3.1 Electrical characteristics 3.2 Standard characteristics 3.3 Notes on use 3.4 Countermeasures against noise 3.5 Control registers 3.6 Package outline 3.7 Machine instructions 3.8 List of instruction code 3.9 SFR memory map 3.10 Pin configuration APPENDIX 7641 Group 3.1 Electrical characteristics 3.1 Electrical characteristics 3.1.1 Absolute maximum ratings Table 3.1.1 Absolute maximum ratings Symbol VCC AVCC VI Parameter Power source voltage Analog power source voltage AVcc, Ext.Cap Input voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 Input voltage RESET, XIN, XCIN Input voltage CNVSS Mask ROM version Flash memory version Input voltage USB D+, USB D– Output voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87, XOUT, XCOUT, LPF Output voltage USB D+, USB D–, Ext. Cap Power dissipation (Note) Operating temperature Storage temperature Conditions All voltages are based on Vss. Output transistors are cut off. Ratings –0.3 to 6.5 –0.3 to VCC+0.3 –0.3 to VCC+0.3 Unit V V V VI VI VI VO –0.3 to VCC+0.3 –0.3 to Vcc + 0.3 –0.3 to 6.5 –0.5 to 3.8 –0.3 to VCC+0.3 V V V V V VO Pd Topr Tstg Ta = 25°C –0.5 to 3.8 750 –20 to 70 –40 to 125 V mW °C °C Note: The maximum power dissipation depends on the MCU’s power dissipation and the specific heat consumption of the package. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 2 of 108 APPENDIX 7641 Group 3.1 Electrical characteristics 3.1.2 Recommended operating conditions (In Vcc = 5 V) Table 3.1.2 Recommended operating conditions (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted) Symbol VCC AVcc VSS AVSS VIH Power source voltage Analog reference voltage Power source voltage Analog reference voltage “H” input voltage Parameter Limits Min. 4.15 4.15 Typ. 5.0 5.0 0 0 Max. 5.25 VCC Unit V V V V V VIH VIH VIH VIH VIL P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” input voltage (Selecting VIHL level input) P20–P27 “H” input voltage (Selecting TTL level input for MBI input) P54–P57, P60–P67, P72 “H” input voltage RESET, XIN, XCIN, CNVss “H” input voltage USB D+, USB D– “L” input voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” input voltage (Selecting VIHL level input) P20–P27 “L” input voltage (Selecting TTL level input for MBI input) P54–P57, P60–P67, P72 “L” input voltage RESET, XIN, XCIN, CNVss “L” input voltage USB D+, USB D– “H” total peak output current P00–P07, P10–P17, P20–P27, (Note 1) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” total peak output current P00–P07, P10–P17, P20–P27, (Note 1) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” total average output current P00–P07, P10–P17, P20–P27, (Note 1) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” total average output current P00–P07, P10–P17, P20–P27, (Note 1) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” peak output current P00–P07, P10–P17, P20–P27, (Note 2) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” peak output current P00–P07, P10–P17, P20–P27, (Note 2) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” average output current P00–P07, P10–P17, P20–P27, (Note 3) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” average output current P00–P07, P10–P17, P20–P27, (Note 3) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 Timer X input frequency (Note 4) Timer Y input frequency (Note 4) Main clock input frequency (Notes 4, 5) Sub-clock input frequency (Notes 4, 6) 0.8VCC VCC 0.5VCC 2.0 0.8VCC 2.0 0 VCC VCC VCC 3.8 0.2VCC V V V V V VIL VIL VIL VIL ΣIOH(peak) ΣIOL(peak) ΣIOH(avg) ΣIOL(avg) 0 0 0 0.16VCC 0.8 0.2VCC 0.8 –80 V V V V mA 80 mA –40 mA 40 mA IOH(peak) –10 mA IOL(peak) 10 mA IOH(avg) –5.0 mA IOL(avg) 5.0 mA f(CNTR0) f(CNTR1) f(XIN) f(XCIN) 1 32.768 5.0 5.0 24 50/5.0 MHz MHz MHz kHz/MHz Notes 1: The total peak output current is the peak value of the peak currents flowing through all the applicable ports. The total average output current is the average value measured over 100 ms flowing through all the applicable ports. 2: The peak output current is the peak current flowing in each port. 3: The average output current is an average value measured over 100 ms. 4: The duty of oscillation frequency is 50 %. 5: Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins. Its maximum oscillation frequency must be 24 MHz. However, make sure to set φ to 12 MHz or slower. More faster clocks are required as the f(XIN) when using the frequency synthesizer as possible. 6: Connect a ceramic resonator or a quartz-crystal oscillator between the XCIN and XCOUT pins. Its maximum oscillation frequency must be 50 kHz. Input an external clock having 5 MHz frequency (max.) from the XCIN pin. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 3 of 108 APPENDIX 7641 Group 3.1 Electrical characteristics 3.1.3 Electrical characteristics (In Vcc = 5 V) Table 3.1.3 Electrical characteristics (1) ( Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) Symbol VOH Parameter “H” output voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” output voltage USB D+, USB DTest conditions IOH = –10 mA Min. VCC–2.0 Limits Typ. Max. Unit V VOH VOL VOL “L” output voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” output voltage USB D+, USB D- USB+, and USB- pins pull-down via a resistor of 15 kΩ ± 5 % USB+ pin pull-up to Ext. Cap. pin via a resistor of 1.5 kΩ ± 5 % IOL = 10 mA 2.8 3.6 V 2.0 V USB+, and USB- pins pull-down via a resistor of 15 kΩ ± 5 % USB+ pin pull-up to Ext. Cap. pin via a resistor of 1.5 kΩ ± 5 % 0.3 V VT+–VT- VT+–VT- VT+–VTIIH IIH IIH IIH IIL IIL IIL IIL IIL IIL Hysteresis CNTR0, CNTR1, INT0, INT1, RDY, HOLD, P20–P27 Hysteresis URXD1, URXD2 (SCLK), CTS2 (SRXD), SRDY, CTS1 Hysteresis RESET “H” input current P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” input current RESET, CNVSS “H” input current XIN “H” input current XCIN “L” input current P00–P07, P10–P17, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” input current RESET “L” input current CNVSS “L” input current XIN “L” input current XCIN “L” input current P20–P27 0.5 V 0.5 V 0.5 VI = VCC 5.0 V µA 9.0 VI = VSS 5.0 20 5.0 –5.0 µA µA µA µA –9.0 VI = VSS Pull-ups “off” VCC = 5.0 V, VI = VSS Pull-ups “on” When clock is stopped –5.0 –20 –20 –5.0 –5.0 –140 5.25 µA µA µA µA µA µA V –30 2.0 –65 VRAM RAM hold voltage Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 4 of 108 APPENDIX 7641 Group 3.1 Electrical characteristics In Vcc = 5 V Table 3.1.4 Electrical characteristics (2) ( Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) Symbol ICC Parameter Power source current (Output transistor is isolated.) Test conditions Normal mode (Note 1) f(XIN) = 24 MHz, φ = 12 MHz USB operating Frequency synthesizer ON Wait mode (Note 2) f(XIN) = 24 MHz, φ = 12 MHz USB block enabled, USB clock stopped, Frequency synthesizer ON Wait mode (Note 3) f(XCIN) = 32 kHz, φ = 16 kHz USB block disabled Frequency synthesizer OFF USB transceiver DC-DC converter OFF Stop mode USB transceiver DC-DC converter ON Low current mode (USBC3 = “1”) Stop mode USB transceiver DC-DC converter OFF Ta = 25 °C Stop mode USB transceiver DC-DC converter OFF Ta = 70 °C Min. Limits Typ. 40 Max. 90 Unit mA 5.0 11 mA 10 µA 100 250 µA 1.0 µA 10 µA Notes 1: Operating in single-chip mode Clock input from XIN pin (XOUT oscillator stopped) USB operating with USB transceiver DC-DC converter enabled Operating functions: Frequency synthesizer, CPU, two UARTs, DMAC, Timers and Count source generator Disabled functions: Master CPU bus interface and Serial I/O 2: Operating in single-chip mode with Wait mode Clock input from XIN pin (XOUT oscillator stopped) USB suspended due to USB clock stopped with USB transceiver DC-DC converter enabled Operating functions: Frequency synthesizer, Timers and Count source generator Disabled functions: CPU, two UARTs, DMAC, Master CPU bus interface and Serial I/O 3: Operating in single-chip mode with Wait mode XIN - XOUT oscillator stopped Clock input from XCIN pin (XCOUT oscillator stopped) USB stopped, USB clock stopped and USB transceiver DC-DC converter disabled Operating functions: Timers and Count source generator Disabled functions: Frequency synthesizer, CPU, two UARTs, DMAC, Master CPU bus interface and Serial I/O Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 5 of 108 APPENDIX 7641 Group 3.1 Electrical characteristics Timing Requirements In Vcc = 5 V Table 3.1.5 Timing requirements (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(XCIN) tWH(XCIN) tWL(XCIN) tC(INT) tWH(INT) tWL(INT) tC(CNTRI) tWH(CNTRI) tWL(CNTRI) td(φ -TOUT) td(φ -CNTR0) tC(CNTRE0) tWH(CNTRE0) tWL(CNTRE0) td(φ -CNTR1) tC(CNTRE1) tWH(CNTRE1) tWL(CNTRE1) tC(SCLKE) tWH(SCLKE) tWL(SCLKE) tsu(SRXD-SCLKE) th(SCLKE-SRXD) td(SCLKE-STXD) tv(SCLKE-SRDY) tc(SCLKI) tWH(SCLKI) tWL(SCLKI) tsu(SRXD-SCLKI) th(SCLKI-SRXD) td(SCLKI-STXD) Parameter Reset input “L” pulse width Main clock input cycle time (Note) Main clock input “H” pulse width Main clock input “L” pulse width Sub-clock input cycle time Sub-clock input “H” pulse width Sub-clock input “L” pulse width INT0, INT1 input cycle time INT0, INT1 input “H” pulse width INT0, INT1 input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width Timer TOUT delay time Timer CNTR0 delay time (Pulse output mode) Timer CNTR0 input cycle time (Event counter mode) Timer CNTR0 input “H” pulse width (Event counter mode) Timer CNTR0 input “L” pulse width (Event counter mode) Timer CNTR1 delay time (Pulse output mode) Timer CNTR1 input cycle time (Event counter mode) Timer CNTR1 input “H” pulse width (Event counter mode) Timer CNTR1 input “L” pulse width (Event counter mode) Serial I/O external clock input cycle time Serial I/O external clock input “H” pulse width Serial I/O external clock input “L” pulse width Serial I/O input setup time (external clock) Serial I/O input hold time (external clock) Serial I/O output delay time (external clock) Serial I/O SRDY valid time (external clock) Serial I/O internal clock output cycle time Serial I/O internal clock output “H” pulse width Serial I/O internal clock output “L” pulse width Serial I/O input setup time (internal clock) Serial I/O input hold time (internal clock) Serial I/O output delay time (internal clock) Min. 2 41.66 0.4•tc(XIN) 0.4•tc(XIN) 200 0.4•tc(XCIN) 0.4•tc(XCIN) 200 90 90 200 80 80 15 15 200 0.4•tc(CNTRE0) 0.4•tc(CNTRE0) 15 200 0.4•tc(CNTRE1) 0.4•tc(CNTRE1) 400 190 180 15 10 25 26 166.66 0.5•tc(SCLKI) – 5 0.5•tc(SCLKI) – 5 20 5 5 Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: Make sure not to exceed 12 MHz of φ, in other words, tc(φ) ≥ 83.33 ns). For example, set bit 7 of the clock control register (CCR) to “0” in the case of tc(XIN) < 41.66 ns. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 6 of 108 APPENDIX 7641 Group 3.1 Electrical characteristics In Vcc = 5 V Table 3.1.6 Master CPU bus interface (MBI; RD, WR separate type) ( Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) Symbol tsu(S-R) tsu(S-W) th(R-S) th(W-S) tsu(A-R) tsu(A-W) th(R-A) th(W-A) tw(R) tw(W) tsu(D-W) th(W-D) ta(R-D) tv(R-D) tv(R-OBF) td(W-IBF) Parameter S0, S1 setup time for read S0, S1 setup time for write S0, S1 hold time for read S0, S1 hold time for write A0 setup time for read A0 setup time for write A0 hold time for read A0 hold time for write Read pulse width Write pulse width Data input setup time before write Data input hold time after write Data output enable time after read Data output disable time after read OBF output transmission time after read IBF output transmission time after write Min. 0 0 0 0 10 10 0 0 50 50 25 0 10 40 40 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 40 In Vcc = 5 V Table 3.1.7 Master CPU bus interface (MBI; R/W type) ( Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) Symbol tsu(S-E) th(E-S) tsu(A-E) th(E-A) tsu(RW-E) th(E-RW) tw(E) tw(E-E) tsu(D-E) th(E-D) ta(E-D) tv(E-D) tv(E-OBF) td(E-IBF) Parameter S0, S1 setup time S0, S1 hold time A0 setup time A0 hold time R/W setup time R/W hold time Enable pulse width Enable pulse interval Data input setup time before write Data input hold time after write Data output enable time after read Data output disable time after read OBF output transmission time after E inactive IBF output transmission time after E inactive Min. 0 0 10 0 10 10 50 50 25 0 10 40 40 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 40 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 7 of 108 APPENDIX 7641 Group 3.1 Electrical characteristics In Vcc = 5 V Table 3.1.8 Timing requirements and switching characteristics in memory expansion and microprocessor modes (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) Symbol tC(φ) tWH(φ) tWL(φ) td(φ -AH) tv(φ -AH) td(φ -AL) tv(φ -AL) td(φ -WR) tv(φ -WR) td(φ -RD) tv(φ -RD) td(φ -SYNC) tv(φ -SYNC) td(φ -DMA) tv(φ -DMA) tsu(RDY- φ) th(φ -RDY) tsu(HOLD- φ) th(φ -HOLD) td(φ -HLDAL) td(φ -HLDAH) tsu(DB- φ) th(φ -DB) td(φ -DB) tV(φ -DB) td(φ -EDMA) tv(φ -EDMA) tWL(WR) (Note 2) tWL(RD) (Note 2) td(AH-WR) td(AL-WR) tv(WR-AH) tv(WR-AL) td(AH-RD) td(AL-RD) tv(RD-AH) tv(RD-AL) tsu(RDY-WR) th(WR-RDY) tsu(RDY-RD) th(RD-RDY) tsu(DB-RD) th(RD-DB) td(WR-DB) tv(WR-DB) tv(WR-EDMA) tv(RD-EDMA) tr(D+), tr(D-) tf(D+), tf(D-) Parameter φ clock cycle time φ clock “H” pulse width φ clock “L” pulse width AB15–AB8 delay time AB15–AB8 valid time AB7–AB0 delay time AB7–AB0 valid time WR delay time WR valid time RD delay time RD valid time SYNCOUT delay time SYNCOUT valid time DMAOUT delay time DMAOUT valid time RDY setup time RDY hold time HOLD setup time HOLD hold time HOLD “L” delay time HOLD “H” delay time Data bus setup time Data bus hold time Data bus delay time Data bus valid time (Note 1) EDMA delay time EDMA valid time WR pulse width RD pulse width AB15–AB8 valid time before WR AB7–AB0 valid time before WR AB15–AB8 valid time after WR AB7–AB0 valid time after WR AB15–AB8 valid time before RD AB7–AB0 valid time before RD AB15–AB8 valid time after RD AB7–AB0 valid time after RD RDY setup time before WR RDY hold time after WR RDY setup time before RD RDY hold time after RD Data bus setup time before RD Data bus hold time after RD Data bus delay time before WR Data bus valid time after WR (Note 1) EDMA delay time after WR EDMA valid time after RD USB output rise time, CL = 50 pF USB output fall time, CL = 50 pF Min. 83.33 0.5•tc(φ) – 5 0.5•tc(φ) – 5 5 33 5 6 3 6 3 6 4 25 5 21 0 21 0 25 25 7 0 22 13 9 4 0.5•tc(φ) – 5 0.5•tc(φ) – 5 0.5•tc(φ) – 28 0.5•tc(φ) – 30 0 0 0.5•tc(φ) – 28 0.5•tc(φ) – 30 0 0 27 0 27 0 13 0 20 10 2 2 4 4 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 31 20 20 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 8 of 108 APPENDIX 7641 Group 3.1 Electrical characteristics Notes 1: Test conditions: IOHL = ± 5mA, CL = 50 pF 2: twL(RD) = ((n + 0.5) • tc(PHI)) – 5 ns (n = wait number) twL(WR) = ((n + 0.5) • tc(PHI)) – 5 ns (n = wait number) For example, two software waits, PHI = 12 MHz operating twL(RD) = 2.5 • tc(PHI) – 5 ns = 203.33 ns Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 9 of 108 APPENDIX 7641 Group 3.1 Electrical characteristics 3.1.4 Recommended Operating Conditions (In Vcc = 3 V) Table 3.1.9 Recommended operating conditions ( Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) Symbol VCC AVcc VSS AVSS Ext. Cap. VIH Power source voltage Analog reference voltage Power source voltage Analog reference voltage DC-DC converter voltage “H” input voltage Parameter Limits Min. 3.0 3.0 Typ. 3.3 3.3 0 0 3.3 Max. 3.6 VCC Unit V V V V V VIH VIH VIH VIL VIL VIL VIL ΣIOH(peak) ΣIOL(peak) ΣIOH(avg) ΣIOL(avg) IOH(peak) IOL(peak) IOH(avg) IOL(avg) f(CNTR0) f(CNTR1) f(XIN) f(XCIN) P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” input voltage (Selecting VIHL level input) P20–P27 “H” input voltage RESET, XIN, XCIN, CNVss “H” input voltage USB D+, USB D– “L” input voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” input voltage (Selecting VIHL level input) P20–P27 “L” input voltage RESET, XIN, XCIN, CNVss “L” input voltage USB D+, USB D– “H” total peak output current P00–P07, P10–P17, P20–P27, (Note 1) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” total peak output current P00–P07, P10–P17, P20–P27, (Note 1) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” total average output current P00–P07, P10–P17, P20–P27, (Note 1) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” total average output current P00–P07, P10–P17, P20–P27, (Note 1) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” peak output current P00–P07, P10–P17, P20–P27, (Note 2) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” peak output current P00–P07, P10–P17, P20–P27, (Note 2) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” average output current P00–P07, P10–P17, P20–P27, (Note 3) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” average output current P00–P07, P10–P17, P20–P27, (Note 3) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 Timer X input frequency (Note 4) Timer Y input frequency (Note 4) Main clock input frequency (Notes 4, 5) Sub-clock input frequency (Notes 4, 6) 3.0 0.8VCC 3.6 VCC 0.5VCC 0.8VCC 2.0 0 VCC VCC 0.2VCC V V V V V V V V mA mA 0 0 0.16VCC 0.2VCC 0.8 –80 80 mA –40 mA 40 mA –10 mA 10 mA –5.0 mA 5.0 mA 1 32.768 5.0 5.0 24 50/5.0 MHz MHz MHz kHz/MHz Notes 1: The total peak output current is the peak value of the peak currents flowing through all the applicable ports. The total average output current is the average value measured over 100 ms flowing through all the applicable ports. 2: The peak output current is the peak current flowing in each port. 3: The average output current is an average value measured over 100 ms. 4: The duty of oscillation frequency is 50 %. 5: Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins. Its maximum oscillation frequency must be 24 MHz. However, make sure to set φ to 6 MHz or slower. More faster clocks are required as the f(XIN) when using the frequency synthesizer as possible. 6: Connect a ceramic resonator or a quartz-crystal oscillator between the XCIN and XCOUT pins. Its maximum oscillation frequency must be 50 kHz. Input an external clock having 5 MHz (max.) frequency from the XCIN pin. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 10 of 108 APPENDIX 7641 Group 3.1 Electrical characteristics 3.1.5 Electrical Characteristics (In Vcc = 3 V) Table 3.1.10 Electrical characteristics (1) ( Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) Symbol VOH Parameter “H” output voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” output voltage USB D+, USB DTest conditions IOH = –1 mA Min. VCC–1.0 Limits Typ. Max. Unit V VOH VOL VOL “L” output voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” output voltage USB D+, USB D- USB+, and USB- pins pull-down via a resistor of 15 kΩ ± 5 % USB+ pin pull-up to Ext. Cap. pin via a resistor of 1.5 kΩ ± 5 % IOL = 1 mA 2.8 3.6 V 1.0 V USB+, and USB- pins pull-down via a resistor of 15 kΩ ± 5 % USB+ pin pull-up to Ext. Cap. pin via a resistor of 1.5 kΩ ± 5 % 0 0.3 V VT+–VT- VT+–VT- VT+–VTIIH IIH IIH IIH IIL IIL IIL IIL IIL IIL Hysteresis CNTR0, CNTR1, INT0, INT1, RDY, HOLD, P20–P27 Hysteresis URXD1, URXD2 (SCLK), CTS2 (SRXD), SRDY, CTS1 Hysteresis RESET “H” input current P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” input current RESET, CNVSS “H” input current XIN “H” input current XCIN “L” input current P00–P07, P10–P17, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” input current RESET “L” input current CNVSS “L” input current XIN “L” input current XCIN “L” input current P20–P27 0.3 V 0.3 V 0.3 VI = VCC 5.0 V µA 9.0 VI = VSS 5.0 20 5.0 –5.0 µA µA µA µA –9.0 VI = VSS Pull-ups “off” VCC = 3.0 V, VI = VSS Pull-ups “on” When clock is stopped –5.0 –20 –20 –5.0 –5.0 –50 µA µA µA µA µA µA V –10 2.0 –20 VRAM RAM hold voltage Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 11 of 108 APPENDIX 7641 Group 3.1 Electrical characteristics In Vcc = 3 V Table 3.1.11 Electrical characteristics (2) ( Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) Symbol ICC Parameter Power source current (Output transistor is isolated.) Test conditions Normal mode (Note 1) f(XIN) = 24 MHz, φ = 6 MHz USB operating Frequency synthesizer ON Wait mode (Note 2) f(XIN) = 24 MHz, φ = 6 MHz USB block enabled, USB clock stopped, Frequency synthesizer ON Wait mode (Note 3) f(XCIN) = 32 kHz, φ = 16 kHz USB block disabled Frequency synthesizer OFF USB transceiver DC-DC converter OFF Stop mode USB transceiver DC-DC converter OFF Ta = 25 °C Stop mode USB transceiver DC-DC converter OFF Ta = 70 °C Min. Limits Typ. 25 Max. 45 Unit mA 2.5 6 mA 6 µA 1.0 µA 10 µA Notes 1: Operating in single-chip mode Clock input from XIN pin (XOUT oscillator stopped) USB operating with USB transceiver DC-DC converter enabled Operating functions: Frequency synthesizer, CPU, two UARTs, DMAC, Timers and Count source generator Disabled functions: Master CPU bus interface and Serial I/O 2: Operating in single-chip mode with Wait mode Clock input from XIN pin (XOUT oscillator stopped) USB suspended due to USB clock stopped with USB transceiver DC-DC converter enabled Operating functions: Frequency synthesizer, Timers and Count source generator Disabled functions: CPU, two UARTs, DMAC, Master CPU bus interface and Serial I/O 3: Operating in single-chip mode with Wait mode XIN - XOUT oscillator stopped Clock input from XCIN pin (XCOUT oscillator stopped) USB stopped, USB clock stopped and USB transceiver DC-DC converter disabled Operating functions: Timers and Count source generator Disabled functions: Frequency synthesizer, CPU, two UARTs, DMAC, Master CPU bus interface and Serial I/O Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 12 of 108 APPENDIX 7641 Group 3.1 Electrical characteristics Timing Requirements In Vcc = 3 V Table 3.1.12 Timing requirements (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(XCIN) tWH(XCIN) tWL(XCIN) tC(INT) tWH(INT) tWL(INT) tC(CNTRI) tWH(CNTRI) tWL(CNTRI) td(φ -TOUT) td(φ -CNTR0) tC(CNTRE0) tWH(CNTRE0) tWL(CNTRE0) td(φ -CNTR1) tC(CNTRE1) tWH(CNTRE1) tWL(CNTRE1) tC(SCLKE) tWH(SCLKE) tWL(SCLKE) tsu(SRXD-SCLKE) th(SCLKE-SRXD) td(SCLKE-STXD) tv(SCLKE-SRDY) tc(SCLKI) tWH(SCLKI) tWL(SCLKI) tsu(SRXD-SCLKI) th(SCLKI-SRXD) td(SCLKI-STXD) Parameter Reset input “L” pulse width Main clock input cycle time (Note) Main clock input “H” pulse width Main clock input “L” pulse width Sub-clock input cycle time Sub-clock input “H” pulse width Sub-clock input “L” pulse width INT0, INT1 input cycle time INT0, INT1 input “H” pulse width INT0, INT1 input “L” pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width Timer TOUT delay time Timer CNTR0 delay time (Pulse output mode) Timer CNTR0 input cycle time (Event counter mode) Timer CNTR0 input “H” pulse width (Event counter mode) Timer CNTR0 input “L” pulse width (Event counter mode) Timer CNTR1 delay time (Pulse output mode) Timer CNTR1 input cycle time (Event counter mode) Timer CNTR1 input “H” pulse width (Event counter mode) Timer CNTR1 input “L” pulse width (Event counter mode) Serial I/O external clock input cycle time Serial I/O external clock input “H” pulse width Serial I/O external clock input “L” pulse width Serial I/O input setup time (external clock) Serial I/O input hold time (external clock) Serial I/O output delay time (external clock) Serial I/O SRDY valid time (external clock) Serial I/O internal clock output cycle time Serial I/O internal clock output “H” pulse width Serial I/O internal clock output “L” pulse width Serial I/O input setup time (internal clock) Serial I/O input hold time (internal clock) Serial I/O output delay time (internal clock) Min. 2 41.66 0.4•tc(XIN) 0.4•tc(XIN) 200 0.4•tc(XCIN) 0.4•tc(XCIN) 250 110 110 250 110 110 17 16 250 0.4•tc(CNTRE0) 0.4•tc(CNTRE0) 15 250 0.4•tc(CNTRE1) 0.4•tc(CNTRE1) 450 220 190 20 15 34 35 300 0.5•tc(SCLKI) – 5 0.5•tc(SCLKI) – 5 20 5 5 Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: Make sure not to exceed 6 MHz of φ, in other words, tc(φ) ≥ 166.66 ns). Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 13 of 108 APPENDIX 7641 Group 3.1 Electrical characteristics In Vcc = 3 V Table 3.1.13 Master CPU bus interface (MBI; RD, WR separate type) (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) Symbol tsu(S-R) tsu(S-W) th(R-S) th(W-S) tsu(A-R) tsu(A-W) th(R-A) th(W-A) tw(R) tw(W) tsu(D-W) th(W-D) ta(R-D) tv(R-D) tv(R-OBF) td(W-IBF) Parameter S0, S1 setup time for read S0, S1 setup time for write S0, S1 hold time for read S0, S1 hold time for write A0 setup time for read A0 setup time for write A0 hold time for read A0 hold time for write Read pulse width Write pulse width Data input setup time before write Data input hold time after write Data output enable time after read Data output disable time after read OBF output transmission time after read IBF output transmission time after write Min. 0 0 0 0 10 10 0 0 80 80 35 0 10 50 50 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 65 In Vcc = 3 V Table 3.1.14 Master CPU bus interface (MBI; R/W type) ( Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) Symbol tsu(S-E) th(E-S) tsu(A-E) th(E-A) tsu(RW-E) th(E-RW) tw(E) tw(E-E) tsu(D-E) th(E-D) ta(E-D) tv(E-D) tv(E-OBF) td(E-IBF) Parameter S0, S1 setup time S0, S1 hold time A0 setup time A0 hold time R/W setup time R/W hold time Enable pulse width Enable pulse interval Data input setup time before write Data input hold time after write Data output enable time after read Data output disable time after read OBF output transmission time after E inactive IBF output transmission time after E inactive Min. 0 0 10 0 10 10 80 80 35 0 10 50 50 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 65 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 14 of 108 APPENDIX 7641 Group 3.1 Electrical characteristics In Vcc = 3 V Table 3.1.15 Timing requirements and switching characteristics in memory expansion and microprocessor modes (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) Symbol tC(φ) tWH(φ) tWL(φ) td(φ -AH) tv(φ -AH) td(φ -AL) tv(φ -AL) td(φ -WR) tv(φ -WR) td(φ -RD) tv(φ -RD) td(φ -SYNC) tv(φ -SYNC) td(φ -DMA) tv(φ -DMA) tsu(RDY- φ) th(φ -RDY) tsu(HOLD- φ) th(φ -HOLD) td(φ -HLDAL) td(φ -HLDAH) tsu(DB- φ) th(φ -DB) td(φ -DB) tV(φ -DB) td(φ -EDMA) tv(φ -EDMA) tWL(WR) (Note 2) tWL(RD) (Note 2) td(AH-WR) td(AL-WR) tv(WR-AH) tv(WR-AL) td(AH-RD) td(AL-RD) tv(RD-AH) tv(RD-AL) tsu(RDY-WR) th(WR-RDY) tsu(RDY-RD) th(RD-RDY) tsu(DB-RD) th(RD-DB) td(WR-DB) tv(WR-DB) tv(WR-EDMA) tv(RD-EDMA) tr(D+), tr(D-) tf(D+), tf(D-) Parameter φ clock cycle time φ clock “H” pulse width φ clock “L” pulse width AB15–AB8 delay time AB15–AB8 valid time AB7–AB0 delay time AB7–AB0 valid time WR delay time WR valid time RD delay time RD valid time SYNCOUT delay time SYNCOUT valid time DMAOUT delay time DMAOUT valid time RDY setup time RDY hold time HOLD setup time HOLD hold time HOLD “L” delay time HOLD “H” delay time Data bus setup time Data bus hold time Data bus delay time Data bus valid time (Note 1) EDMA delay time EDMA valid time WR pulse width RD pulse width AB15–AB8 valid time before WR AB7–AB0 valid time before WR AB15–AB8 valid time after WR AB7–AB0 valid time after WR AB15–AB8 valid time before RD AB7–AB0 valid time before RD AB15–AB8 valid time after RD AB7–AB0 valid time after RD RDY setup time before WR RDY hold time after WR RDY setup time before RD RDY hold time after RD Data bus setup time before RD Data bus hold time after RD Data bus delay time after WR Data bus valid time after WR (Note 1) EDMA delay time after WR EDMA valid time after RD USB output rise time, CL = 50 pF USB output fall time, CL = 50 pF Min. 166.66 0.5•tc(φ) – 5 0.5•tc(φ) – 5 7 47 7 8 4 8 3 11 4 26 9 35 0 21 0 30 30 9 0 30 15 12 8 0.5•tc(φ) – 6 0.5•tc(φ) – 6 0.5•tc(φ) – 33 0.5•tc(φ) – 35 0 0 0.5•tc(φ) – 33 0.5•tc(φ) – 35 0 0 45 0 45 0 18 0 28 12 3 3 4 4 Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 45 20 20 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 15 of 108 APPENDIX 7641 Group 3.1 Electrical characteristics Notes 1: Test conditions: IOHL = ± 5mA, CL = 50 pF 2: twL(RD) = ((n + 0.5) • tc(PHI)) – 5 ns (n = wait number) twL(WR) = ((n + 0.5) • tc(PHI)) – 5 ns (n = wait number) For example, two software waits, PHI = 12 MHz operating twL(RD) = 2.5 • tc(PHI) – 5 ns = 203.33 ns Measurement output pin 100 pF 1 kΩ Measurement output pin 100 pF CMOS output N-channel open-drain output (Note) Fig. 3.1.1 Circuit for measuring output switching characteristics (1) Note: This diagram applies when bit 7 of the serial I/O control register 1 is “1”. Fig. 3.1.2 Circuit for measuring output switching characteristics (2) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 16 of 108 APPENDIX 7641 Group 3.1 Electrical characteristics q Timing diagram [Interrupt] tC(CNTRI) tWH(CNTRI) tWL(CNTRI) 0.2VCC CNTR0, CNTR1 0.8VCC tC(INT) tWH(INT) tWL(INT) 0.2VCC INT0, INT1 [Input] RESET 0.8VCC tW(RESET) 0.2VCC 0.8VCC tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC XIN 0.8VCC tC(XCIN) tWH(XCIN) tWL(XCIN) 0.2VCC XCIN 0.8VCC [Timer] φ 0.5VCC td(φ – TOUT) TOUT 0.5VCC td(φ – CNTR0,1) CNTR0, CNTR1 0.5VCC tC(CNTRE0,1) tWH(CNTRE0,1) tWL(CNTRE0,1) 0.2VCC CNTR0, CNTR1 0.8VCC Fig. 3.1.3 Timing diagram (1) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 17 of 108 APPENDIX 7641 Group 3.1 Electrical characteristics q Timing diagram [Serial I/O] tC(SCLKE,I) tWL(SCLKE, I) tWH(SCLKE,I) 0.8VCC SCLK 0.2VCC tsu(SRXD – SCLKE, I) th(SCLKE, I – SRXD) SRXD td(SCLKE, I – STXD) 0.8VCC 0.2VCC STXD 0.5VCC tv(SCLKE – SRDY) SRDY 0.8VCC Fig. 3.1.4 Timing diagram (2) tf(D+) tf(D-) tr(D+) tr(D-) 0.9VOH USBD+, USBD- 0.1VOH Fig. 3.1.5 Timing diagram (3) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 18 of 108 APPENDIX 7641 Group 3.1 Electrical characteristics q Timing diagram [Master CPU bus interface: R/W separate mode] tsu(A-R) th(R-A) A0 0.8VCC(2.0V) 0.2VCC(0.8V) tsu(S-R) th(R-S) S0, S1 0.2VCC(0.8V) tw(R) 0.8VCC(2.0V) 0.2VCC(0.8V) R DQ0 to DQ7 0.8VCC 0.2VCC ta(R-D) 0.8VCC 0.2VCC tv(R-D) tv(R-OBF) OBF 0.2VCC tsu(A-W) th(W-A) A0 0.8VCC(2.0V) 0.2VCC(0.8V) tsu(S-W) th(W-S) S0, S1 0.2VCC(0.8V) tw(W) 0.8VCC(2.0V) 0.2VCC(0.8V) W tsu(D-W) th(W-D) 0.8VCC 0.2VCC DQ0 to DQ7 0.8VCC 0.2VCC td(W-IBF) IBF 0.2VCC Note: This timing applies in the case of the master bus input level select bit (PTC7) = “1” (TTL level input) Fig. 3.1.6 Timing diagram (4) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 19 of 108 APPENDIX 7641 Group 3.1 Electrical characteristics q Timing diagram [Master CPU bus interface: R/W mode] tw(E-E) tw(E) 0.8VCC(2.0V) 0.2VCC(0.8V) E 0.2VCC(0.8V) A0 R/W tsu(A-E) 0.8VCC(2.0V) 0.2VCC(0.8V) th(E-A) tsu(S-E) th(E-S) S0, S1 0.2VCC(0.8V) DQ0 to DQ7 DQ0 to DQ7 0.8VCC 0.2VCC ta(E-D) tsu(D-E) 0.8VCC 0.2VCC 0.8VCC 0.2VCC tv(E-D) 0.8VCC 0.2VCC th(E-D) tv(E-OBF) td(E-IBF) OBF, IBF 0.2VCC Note: This timing applies in the case of the master bus input level select bit (PTC7) = “1” (TTL level input) Fig. 3.1.7 Timing diagram (5) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 20 of 108 APPENDIX 7641 Group 3.1 Electrical characteristics tC(φ) tWH(φ) tWL(φ) φ 0.5VCC td(φ-AH) tv(φ-AH) 0.5VCC td(φ-AL) tv(φ-AL) 0.5VCC td(φ-SYNC) tv(φ-SYNC) AB15 to AB8 AB7 to AB0 SYNCOUT 0.5VCC td(φ-WR) td(φ-RD) 0.5VCC td(φ-DMA) tv(φ-WR) tv(φ-RD) RD,WR tv(φ-DMA) n cycles of φ tsu(RDY-φ) th(φ-RDY) DMAOUT 0.5VCC RDY 0.8VCC 0.2VCC tsu(HOLD-φ) th(φ-HOLD) HOLD (at entering) 0.8VCC 0.2VCC td(φ-HLDAL) HLDA tsu(HOLD-φ) th(φ-HOLD) 0.5VCC HOLD (at releasing) 0.8VCC 0.2VCC td(φ-HLDAH) HLDA tsu(DB-φ) 0.5VCC th(φ-DB) DB0 to DB7 td(φ-DB) 0.8VCC 0.2VCC tv(φ-DB) 0.5VCC td(φ-EDMA) tv(φ-EDMA) 0.5VCC DB0 to DB7 0.5VCC EDMA Fig. 3.1.8 Timing diagram (6); Memory expansion and microprocessor modes Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 21 of 108 APPENDIX 7641 Group 3.1 Electrical characteristics tWL(RD) tWL(WR) RD,WR td(AH-RD) td(AH-WR) 0.5VCC tv(RD-AH) tv(WR-AH) AB15 to AB8 0.5VCC td(AL-RD) td(AL-WR) tv(RD-AL) tv(WR-AL) AB7 to AB0 0.5VCC tsu(RDY-WR) th(WR-RDY) tsu(RDY-RD) th(RD-RDY) RDY 0.8VCC 0.2VCC DB0 to DB7 tSU(DB-RD) 0.8VCC 0.2VCC th(RD-DB) DB0 to DB7 td(WR-DB) 0.5VCC tv(WR-DB) tv(WR-EDMA) tv(RD-EDMA) EDMA 0.5VCC Fig. 3.1.9 Timing diagram (7); Memory expansion and microprocessor modes Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 22 of 108 APPENDIX 7641 Group 3.2 Standard characteristics 3.2 Standard characteristics Standard characteristics described below are just examples of the 7641 Group’s characteristics and are not guaranteed. For rated values, refer to “ 3.1 Electrical characteristics ”. 3.2.1 Power source current standard characteristics Figure 3.2.1 shows power source current standard characteristics. Measuring conditions : Ta = 25 °C, normal mode, φ = f(XIN)/2, USB operating, frequency synthesizer circuit connecting 60 55 50 45 Vcc=5.25V 40 35 30 25 20 15 10 5 0 0 3 6 9 12 15 18 21 24 27 30 Vcc=4.15V Vcc=3.6V Vcc=3.3V Vcc=3.0V Vcc=5.0V Icc (mA) XIN ( MHz) Fig. 3.2.1 Power source current standard characteristics (Ta = 25 ° C) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 23 of 108 APPENDIX 7641 Group 3.2 Standard characteristics 3.2.2 Port standard characteristics Figure 3.2.2 to Figure 3.2.7 show port standard characteristics. M37641M8 IOH-VOH characteristics CMOS output port (P-channel drive) [Ta = 25 °C] -100 -90 -80 -70 -60 IOH (mA) Vcc=5.25V Vcc=5.0V Vcc=4.15V Vcc=3.6V Vcc=3.3V -50 -40 -30 -20 Vcc=3.0V -10 0 0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 V OH ( V) Fig. 3.2.2 CMOS output port P-channel side characteristics (Ta = 25 °C) M37641M8 IOH-VOH characteristics CMOS output port (P-channel drive) [Ta = 70 °C] -100 -90 -80 -70 -60 IOH (mA) -50 -40 Vcc=5.25V Vcc=5.0V Vcc=4.15V -30 Vcc=3.6V -20 -10 0 0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 Vcc=3.3V Vcc=3.0V V OH ( V) Fig. 3.2.3 CMOS output port P-channel side characteristics (Ta = 70 °C) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 24 of 108 APPENDIX 7641 Group 3.2 Standard characteristics M37641M8 IOL-VOL characteristics CMOS output port (N-channel drive) [Ta = 25 °C] 100 90 80 70 60 IOL (mA) Vcc=5.25V 50 Vcc=5.0V 40 Vcc=4.15V 30 20 10 0 0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 Vcc=3.6V Vcc=3.3V Vcc=3.0V V OL ( V) Fig. 3.2.4 CMOS output port N-channel side characteristics (Ta = 25 °C) M37641M8 IOL-VOL characteristics CMOS output port (N-channel drive) [Ta = 70 °C] 100 90 80 70 60 IOL (mA) 50 40 30 20 10 0 0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 Vcc=4.15V Vcc=3.6V Vcc=3.3V Vcc=3.0V Vcc=5.25V Vcc=5.0V 5.4 6 V OL ( V) Fig. 3.2.5 CMOS output port N-channel side characteristics (Ta = 70 °C) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 25 of 108 APPENDIX 7641 Group 3.2 Standard characteristics M37641M8 Port P20–P27 IIL-VIL characteristics (at pull-up) [Ta = 25 °C] -100 -90 -80 Vcc=5.25V -70 Vcc=5.0V -60 IIL(µA) -50 Vcc=4.15V -40 Vcc=3.6V -30 Vcc=3.3V Vcc=3.0V -20 -10 0 0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 VIL(V) Fig. 3.2.6 Port P20–P27 at pull-up characteristics (Ta = 25 °C) M37641M8 Port P20–P27 IIL-VIL characteristics (at pull-up) [Ta = 70 °C] -100 -90 -80 -70 Vcc=5.25V -60 Vcc=5.0V IIL(µA) -50 -40 Vcc=4.15V -30 Vcc=3.6V Vcc=3.3V -20 Vcc=3.0V -10 0 0 0.6 1.2 1.8 2.4 3 3.6 4.2 4.8 5.4 6 VIL(V) Fig. 3.2.7 Port P20–P27 at pull-up characteristics (Ta = 70 °C) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 26 of 108 APPENDIX 7641 Group 3.3 Notes on use 3.3 Notes on use 3.3.1 Notes on interrupts (1) When setting external interrupt active edge When setting the external interrupt active edge (INT 0, INT1, CNTR0, CNTR1), the interrupt request bit may be set to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. • Interrupt polarity select register (address 001116) • Timer X mode register (address 0027 16) • Timer Y mode register (address 0028 16) Set the above listed registers or bits as the following sequence. Set the corresponding interrupt enable bit to “0” (disabled) . ↓ Set the interrupt edge select bit (active edge switch bit) to “1”. ↓ NOP (one or more instructions) ↓ Set the corresponding interrupt request bit to “0” (no interrupt request issued). ↓ Set the corresponding interrupt enable bit to “1” (enabled). Fig. 3.3.1 Sequence of setting external interrupt active edge Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 27 of 108 APPENDIX 7641 Group 3.3 Notes on use 3.3.2 Notes on serial I/O (1) Clock When the external clock is selected as the transfer clock, its transfer clock needs to be controlled by the external source because the serial I/O shift register will keep being shifted while transfer clock is input even after transfer completion. (2) Reception When the external clock is selected as the transfer clock for reception, the receiving operation will start owing to the shift clock input even if write operation to the serial I/O shift register (SIOSHT) is not performed. The serial I/O interrupt request also occurs at completion of receiving. However, we recommend to write dummy data in the serial I/O shift register. Because this will cause followings and improve transfer reliability. • Write to SIOSHT puts the SRDY pin to “ L ” . This enables shift clock output of an external device. • Write to SIOSHT clears the internal serial I/O counter. Note: Do not read the serial I/O shift register which is shifting. Because this will cause incorrect-data read. (3) STXD output •When the internal clock is selected as the transfer clock, the STXD pin goes a high-impedance state after transfer completion. • When the external clock is selected as the transfer clock, the STXD pin does not go a highimpedance state after transfer completion. (4) SPI compatible mode • When using the SPI compatible mode, set the SRDY select bit to “ 1 ” ( SRDY signal output). • When the external clock is selected in SPI compatible mode, the SRXD pin functions as a data output pin and the STXD pin functions as a data input pin. •Do not write to the serial I/O shift register (SIOSHT) during a transfer as slave when in SPI compatible mode. • Master operation of SPI compatible mode requires the timings: -From write operation to the SIOSHT to SRDY pin put to “ L ” Requires 2 cycles of internal clock φ + 2 c ycles of serial I/O synchronous clock + 35 ns -From SRDY pin put to “ L ” t o SCLK switch Requires 35 ns -From the last pulse of SCLK to SRDY pin put to “ H ” Requires 35 ns. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 28 of 108 APPENDIX 7641 Group 3.3 Notes on use 3.3.3 N otes on UART (1) Receive •When any one of errors occurs, the summing error flag is set to “1” and the UARTx summing error interrupt request bit is also set to “1”. If a receive error occurs, the reception does not set the UARTx receive buffer full interrupt request bit to “1”. •If the receive enable bit (REN) is set to “0” (disabled) while a data is being received, the receiving operation will stop after the data has been received. •Setting the receive initialization bit (RIN) to “1” resets the UARTx RTS control register (UxRTS) to “80 16”. After setting the RIN bit to “1”, set this UxRTS. (2) Transmit •Once the transmission starts, it continues until the last bit has been transmitted even though clearing the transmit enable bit (TEN) to “0” (disabled) or inputting “H” to the CTSx pin. After completion of the current transmission, the transmission is disabled. •The transmit complete flag (TCM) is changed from “1” to “0” later than 0.5 to 1.5 clocks of the shift clock. Accordingly, take it in consideration to transmit data confirming the TCM flag after the data is written into the transmit buffer register. (3) Register settings •If updating a value of UARTx baud rate generator while the data is being transmitted or received, be sure to disable the transmission and reception before updating. If the former data remains in the UARTx transmit buffer registers 1 and 2 at retransmission, an undefined data might be output. •The all error flags PER, FER, OER and SER are cleared to “0” when the UARTx status register is read, at the hardware reset or initialization by setting the Transmit Initialization Bit. These flags are also cleared to “0” by execution of bit test instructions such as B BC a nd B CS . •The transmit buffer empty flag (TBE) is set to “0” when the low-order byte of transmitted data is written into the UARTx (x = 1, 2) transmit buffer register 1. When using 9-bit character length, set the data into the UARTx transmit buffer register 2 (high-order byte) first before the UARTx transmit buffer register 1 (low-order byte). •The receive buffer full flag (RBF) is set to “0” when the contents of UARTx receive buffer register 1 is read out. When using 9-bit character length, read the data from the UARTx receive buffer register 2 (high-order byte) first before the UARTx receive buffer register 1 (low-order byte). •If a character bit length is 7 bits, bit 7 of the UARTx transmit/receive buffer register 1 and bits 0 to 7 of the UARTx transmit/receive buffer register 2 are ignored at transmitting; they are invalid at receiving. If a character bit length is 8 bits, bits 0 to 7 of the UARTx transmit/receive buffer register 2 are ignored at transmitting; they are invalid at receiving. If a character bit length is 9 bits, bits 1 to 7 of the UARTx transmit/receive buffer register 2 are ignored at transmitting; they are “0” at receiving. •The reset cannot affect the contents of baud rate generator. (4) UART address mode •When the MSB of the incoming data is “0” in the UART address mode, the receive buffer full flag (RBF) is set to “1”, but the receive buffer full interrupt request bit is not set to “1”. •An overrun error cannot be detected after the first data has been received in UART address mode. •The UART address mode can be used in either an 8-bit or 9-bit character length. 7-bit character length cannot be used. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 29 of 108 APPENDIX 7641 Group 3.3 Notes on use (5) Receive error flag •The all error flags PER, FER, OER and SER are cleared to “0” when the UARTx status register is read, at the hardware reset or initialization by setting the Transmit Initialization Bit. Accordingly, note that these flags are also cleared to “0” by execution of bit test instructions such as BBC and BBS, not only LDA. (6) CTS function •When the CTS function is enabled, the transmitted data is not transferred to the transmit shift register until “L” is input to the CTSx pin (P86/CTS1, P8 2/CTS 2/SRXD). As the result, do not set the following data to the transmit buffer register. (7) RTS function •If the start bit is detected in the term of “H” assertion of RTS, its assertion count is suspended and the RTSx pin remains “H” output. After receiving the last stop bit, the count is resumed. •Setting the receive initialization bit (RIN) to “1” resets the UARTx RTS control register (UxRTS) to “80 16”. After setting the RIN bit to “1”, set this UxRTS. (8) Interrupt •When setting the transmit initialization bit (TIN) to “1”, both the transmit buffer empty flag (TBE) and the transmit complete flag (TCM) are set to “1”, so that the transmit interrupt request occurs independent of its interrupt source. After setting the transmit initialization bit (TIN) to “1”, clear the transmit interrupt request bit to “0” before setting the transmit enable bit (TEN) to “1”. •The transmit interrupt request bit is set and the interrupt request is generated by setting the transmit enable bit (TIN) to “1” even when selecting timing that either of the following flags is set to “1” as timing where the transmission interrupt is generated: (1) Transmit buffer empty flag is set to “1” (2) Transmit complete flag is set to “1”. Therefore, when the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as the following sequence: (1) Transmit enable bit is set to “1” (2) Transmit interrupt request bit is set to “0” (3) Transmit interrupt enable bit is set to “1”. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 30 of 108 APPENDIX 7641 Group 3.3 Notes on use 3.3.4 N otes on DMAC (1) Transfer time • One-byte data transfer requires 2 cycles of φ ( read and write cycles). •To perform DMAC transfer due to the different transfer requests on the same DMAC channel or DMAC transfer between both DMAC channels, 1 cycle of φ o r more is needed before transfer is started. (2) Priority • The DMAC places a higher priority on channel-0 transfer requests than on channel-1 transfer requests. If a channel-0 transfer request occurs during a channel-1 burst transfer operation, the DMAC completes the next transfer source and destination read/write operation first, and then stops the channel-1 transfer operation. The channel-1 transfer operation which has been suspended is automatically resumed from the point where it was suspended so that channel-1 transfer can complete its one-burst transfer unit. This will be performed even if another channel-0 transfer request occurs. • The suspended transfer due to the interrupt can also be resumed during its interrupt process routine by writing “ 1 ” t o the DMAC channel x enable bit (DxCEN). (3) Related registers •A read/write must be performed to the source registers, transfer destination registers and transfer count registers as follows: Read from each higher byte first, then the lower byte Write to each lower byte first, then the higher byte. Note that if the lower byte is read out first, the values are the higher byte ’ s. • Do not access the DMAC-related registers by using a DMAC transfer. The destination address data and the source address data will collide in the DMAC internal bus. •When setting the DMAC channel x enable bit (bit 7 of address 41 16) to “1”, be sure simultaneously to set the DMAC channel x transfer initiation source capture register reset bit (bit 6 of address 41 16) to “ 1 ” . If this is not performed, an incorrect data will be transferred at the same time when the DMAC is enabled. (4) USB transfer One signal among USB endpoint signals 1 to 4 can be selected as the hardware transfer request source. This can realize that transfer between the USB FIFO and the master CPU bus interface input/output buffer is performed effectively. This transfer function is only valid in the cycle steal transfer mode. (5) DMA OUT p in In the memory expansion mode and microprocessor mode, the DMA OUT pin (P3 3/DMAOUT) outputs “ H ” d uring a DMA transfer. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 31 of 108 APPENDIX 7641 Group 3.3 Notes on use 3.3.5 N otes on USB (1) USB reception •When reading the USB endpoint x (x = 0 to 4) OUT write count registers, the lower byte must be read first, and then the higher byte. •When the OUT FIFO contains 2-data packets in the endpoints 1 to 4 used, one-data packet will still remain in the OUT FIFO even after the data of the OUT max. packet size has been read. In this case the OUT_PKT_RDY flag is not cleared even if it is set to “0”. (The flag returns from “0” to “1” 83 ns later (Vcc = 5 V, f(X IN) = 24 MHz) than the clearing.) •Read one packet data from the OUT FIFO before clearing the OUT_PKT_RDY flag. If the OUT_PKT_RDY flag is cleared while one-data packet is being read, the internal read pointer cannot operate normally. (2) USB transmission •The IN FIFO status can be checked by monitoring the IN_PKT_RDY bit and the TX_NOT_EPT flag. •When NULL packet transmission is required in the endpoints 1 to 4 used, perform it under the conditions of the IN_PKT_RDY bit set to “1” and no data in FIFO. (3) External circuit •Connect a capacitor between the Ext. Cap. pin and the Vss pin. The capacitor should have a 2.2 µF capacitor (Tantalum capacitor) and a 0.1 µF capacitor (ceramic capacitor) connected in parallel. Additionally, connect a 1.5 k Ω ( ± 5 % ) resistor between the Ext. Cap. pin and the D+ pin. •The Full-Speed USB2.0 specification requires a driver -impedance 28 to 44 Ω . (Refer to Clause 7.1.1.1 Full-speed (12 Mb/s) Driver Characteristics in the USB specification.) In order to meet the USB specification impedance requirements, connect a resistor (27 to 33 Ω recommended) in series to the USB D+ pin and the USB D- pin. In addition, in order to reduce the ringing and control the falling/rising timing of USB D+/D- and a crossover point, connect a capacitor between the USB D+/D- pins and the Vss pin if necessary. The values and structure of those peripheral elements depend on the impedance characteristics and the layout of the printed circuit board. Accordingly, evaluate your system and observe waveforms before actual use and decide use of elements and the values of resistors and capacitors. Figure 3.3.2 shows the circuit example for the proper positions of the peripheral components. •In Vcc = 3.3 V operation, connect the Ext. Cap. pin directly to the Vcc pin in order to supply power to the USB transceiver. In addition, you will need to disable the DC-DC converter in this operation (set bit 4 of the USB control register to “0”.) If you are using the bus powered supply in Vcc = 3.3 V operation, the DC-DC converter must be placed outside the MCU. •In Vcc = 5 V operation, do not connect the external DC-DC converter to the Ext. Cap. pin. Use the built-in DC-DC converter by enabling the USB line driver. •Make sure the USB D+/D- lines do not cross any other wires. Keep a large GND area to protect the USB lines. Also, make sure you use a USB specification compliant connecter for the connection. •All passive components must be located as close as possible to the LPF pin. Figure. 3.3.3 shows the passive components near LPF pin •An insulation connector (Ferrite Beads) must be connected between AVss and Vss pins and between AVcc and Vcc pins. (See Figure 3.3.4.) (4) USB Communication •In applications requiring high-reliability, we recommend providing the system with protective measures such as USB function initialization by software or USB reset by the host to prevent USB communication from being terminated unexpectedly, for example due to external causes such as noise. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 32 of 108 APPENDIX 7641 Group 3.3 Notes on use M37641 USBC5 enable enable FSE LS USBC4 USBC3 Ext. Cap. Note 1 XIN Frequency Synthesizer DC-DC converter current mode enable lock USB Clock (48 MHz) USB FCU enable USB transceiver D+ enable See the circuit example below. USBC7 USBC7 D- (1) Vcc = 5 V (Using built-in DC-DC converter) 5V M37641 Vcc Ext. Cap. 2.2 µF 0.1 µF 1.5 kΩ (2) Vcc = 3.3 V (Not using built-in DC-DC converter) 3.3 V M37641 Vcc Ext. Cap. 2.2 µF 0.1 µF 1.5 kΩ AVcc C2 C4 AVss Decoupling Capacitors •Capacitor C1, C2: 0.1 µF C3, C4: 4.7 µF Vcc D+ DNote 2 D+ DNote 2 Notes 1: In Vcc = 3.3 V, connect to Vcc. In Vcc =5 V, do not connect the external DC-DC converter to the Ext. Cap pin. 2: The resistors values depend on the layout of the printed circuit board. Fig. 3.3.2 Circuit example for the proper positions of the peripheral components Ferrite Beads LPF pin Vcc 1 kΩ 680 pF C3 C1 0.1 µF AVSS pin Vss Fig. 3.3.3 Passive components near LPF pin Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 33 of 108 Fig. 3.3.4 Insulation connector connection APPENDIX 7641 Group 3.3 Notes on use (5) Registers and bits •When using the endpoint 0, use the USB endpoint 0 IN max. packet size register for transmission and reception (IN packet size and OUT packet size). •When not using the USB endpoint x (x = 0 to 4) IN max. packet size register and USB endpoint x OUT max. packet size register, set them to “0”. •To write to/read from the USB interrupt status registers 1 and 2, perform it for the USB interrupt status register 1 first and then the register 2. •To read from the USB endpoint x (x = 0 to 4) OUT write count registers Low and High, the lower byte must be read first, then the higher byte. •Make sure the index indicated by the USB endpoint index register is correct when accessing the registers: USB endpoint x (x = 0 to 4) IN control register, USB endpoint x OUT control register, USB endpoint x IN max. packet size register, USB endpoint x OUT max. packet size register, USB endpoint x (x = 0 to 4) OUT write count registers Low and High, USB endpoint FIFO mode register. •When the USB reset interrupt status flag is kept at “1”, all other flags in the USB internal registers (addresses 0050 16 t o 005F 16) will return to their reset status. However, the following registers are not affected by the USB reset: USB control register (address 001316), Frequency synthesizer control register (address 006C16), Clock control register (address 001F16), and USB endpoint x FIFO register (addresses 0060 16 t o 0064 16). •When not using the USB function, set the USB line driver supply enable bit of the USB control register (address 0013 16) to “1” for power supply to the internal circuits (at Vcc = 5 V). •The IN_PKT_RDY Bit can be set by software even when using the AUTO_SET function. •Do not write to USB-related registers (addresses 005016 to 006416) except the USBC, CCR and FSC until the USB clock is enabled. •When the MCU is in the USB-suspend state, the USB enable bit is kept “1”; the USB block is enabled. To write to USB-related registers (addresses 0050 16 t o 0064 16) except the USBC, CCR and FSC after returning from the USB-suspend state; after enabling the USB clock, wait for 4 or more φ c ycles and then set those registers. •When using the MCU at Vcc = 3.3V, set the USB line driver supply enable bit to “0” (line driver disable). Note that setting the USB line driver current control bit (USBC3) doesn’t affect the USB operation. •Setting the FLUSH bit to “1” eliminates the data in IN FIFO and OUT FIFO. If there are 2 or moredata packets in them, the oldest data is eliminated. The FLUSH bit setting also affects the IN_PKT_RDY bit or the OUT_PKT_RDY flag. •If the FLUSH bit is set to “1” while transmission/reception is being performed, the data might be corrupted. When receiving, setting the FLUSH bit must be done while the OUT_PKT_RDY flag is “1”. When transmitting in the isochronous transfer mode, use the AUTO_FLUSH function. •Use the AUTO_FLUSH bit (bit 6 of address 58 16) in the double buffer mode. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 34 of 108 APPENDIX 7641 Group 3.3 Notes on use •Use the transfer instructions such as L DA a nd S TA t o set the registers: USB interrupt status registers 1, 2 (addresses 005216, 005316); USB endpoint 0 IN control register (address 005916); USB endpoint x IN control register (address 0059 16); USB endpoint x OUT control register (address 005A 16). Do not use the read-modify-write instructions such as the S EB o r the C LB i nstruction. When writing to bits shown by Table 32 using the transfer instruction such as LDA or STA, a value which never affect its bit state is required. Take the following sequence to change these bits contents: (1) Store the register contents onto a variable or a data register. (2) Change the target bit on the variable or the data register. Simultaneously mask the bit so that its bit state cannot be changed. (See to Table 3.3.1.) (3) Write the value from the variable or the data register to the register using the transfer instruction such as L DA o r S TA. •To use the AUTO_SET function for an IN transfer when the AUTO_SET bit is set to 1, set the FIFO to single buffer mode. Table 3.3.1 Bits of which state might be changed owing to software write Register name USB endpoint 0 IN control register Bit name IN_PKT_RDY (b1) DATA_END (b3) FORCE_STALL (b4) IN_PKT_RDY (b0) UNDER_RUN (b1) OUT_PKT_RDY (b0) OVER_RUN (b1) FORCE_STALL (b4) DATA_ERR (b5) Value not affecting state (Note) “0” “0” “1” “0” “1” “1” “1” “1” “1” USB endpoint x (x = 1 to 4) IN control register USB endpoint x (x = 1 to 4) OUT control register Note: Writing this value will not change the bit state, because this value cannot be written to the bit by software. (6) Others •When the USB SOF Port Select Bit is “1”, the reference pulse of 83.3 ns ( φ = 1 2 MHz) is output from the P7 0/SOF pin and synchronized with the SOF packet. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 35 of 108 APPENDIX 7641 Group 3.3 Notes on use 3.3.6 N otes on frequency synthesizer •Bits 6 and 5 of the frequency synthesizer control register (address 006C16) are initialized to (b6, b5) = “11” after reset release. Make sure to set bits 6 and 5 to “ 10 ” a fter the frequency synthesizer lock status bit goes to “ 1 ” . • Use the frequency synthesizer output clocks 2 ms to 5 ms later than setting the frequency synthesizer enable bit to “ 1 ” ( enabled). After that do not change any register values because it might cause output clocks unstabilized temporarily. • Make sure to connect a low-pulse filter to the LPF pin when using the frequency synthesizer. • The frequency synthesizer divide register set value never affects f USB f requency. •When using the f SYN as an internal system clock, set the frequency synthesizer divide register so that f SYN could be 24 MHz or less. •When using the frequency synthesized clock function, we recommend using the fastest frequency possible of f(X IN) or f(X CIN) as an input clock for the PLL. • Set the value of frequency synthesizer multiply register 2 (FSM2) so that the f PIN i s 1 MHZ or higher. 3.3.7 N otes on master CPU bus interface Be sure to set port P6 to input mode by setting the port P6 direction register to “0” when the master CPU bus interface is enabled. 3.3.8 Notes on external devices connection (1) Rewrite port P3 latch In both memory expansion mode and microprocessor mode, ports P31 and P32 can be used as output ports. We recommend to use the L DM i nstruction or S TA i nstruction to write to port P3 register (address 000E 16). If using the Read-Modify-Write instruction (SEB i nstruction, C LB i nstruction) you will need to map a memory that the CPU can read from and write to. [Reason] The access to address 000E16 i s performed: • Read from external memory • Write to both port P3 latch and external memory. It is because address 000E16 i s assigned on an external area In the memory expansion mode and microprocessor mode. Accordingly, if a Read-Modify-Write instruction is executed to address 000E 16, the external memory contents is read out and after its modification it will be written into both port P3 latch and an external memory. As a result, if an external memory is not allocated in address 000E16 then, the MCU will read an undefined value and write its modified value into the port P3 latch. Therefore port P3 latch value will become undefined. (2) overlap of internal and external memories In the memory expansion mode, if the internal and external memory areas overlap, the internal memory becomes the valid memory for the overlapping area. When the CPU performs a read or a write operation on this overlapped area, the following things happen: •Read The CPU reads out the data in the internal memory instead of in the external memory. Note that, since the CPU will output a proper read signal, address signal, etc., the memory data at the respective address will appear on the external data bus. •Write The CPU writes data to both the internal and external memories. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 36 of 108 APPENDIX 7641 Group 3.3 Notes on use _____ ______ (3) RD, WR pins In the memory expansion mode or microprocessor mode, a read-out control signal is output from the ______ ______ RD ______ (P3 6), and a write-in control signal is output from the WR pin (P3 7). “ L ” l evel is output from pin ______ the RD pin at CPU read-out and from the WR pin at CPU write-in. These signals function for internal access and external access. __________ (4) HLDA pin __________ In spite of enabling the Hold function, the HLDA pin does not function when IBF 1 output is enabled in the master CPU bus interface. (5) RDY function When using RDY function in usual connection, it does not operate at 12 MHz of φ o r faster. [Reason] td( φ -AH) + tsu(RDY- φ ) = 31 ns (max.) + 21 ns (min.) = 52 ns. twh ( φ ), twl ( φ ) = 0.5 ✕ 8 3.33 – 5 = 3 6.665 ns Therefore, it becomes 52 ns > 36.665 ns, so that the timing to enter RDY wait does not match. ________ However, if the timings can match owing to RDY pin by “L” fixation and others, the RDY function can be used even at φ = 1 2 MHz. In this situation the slow memory wait always functions. (6) Wait function The Wait function is serviceable at accessing an external memory in the memory expansion mode and microprocessor mode. However, in these modes even if an external memory is assigned to addresses 0008 16 t o 000F 16, the Wait function cannot function to these areas. (7) Processor mode switch Note when the processor mode is switched by setting of the processor mode bits (b1, b0 of CPMA), that will immediately switch the accessible memory from external to internal or from internal to external. If this is done, the first cycle of the next instruction will be operated from the accidental memory. To prevent this problem, follow the procedure below: (a) Duplicate the next instruction at the same address both in internal and external memories. (b) Switch from single-chip mode to memory expansion mode, jump to external memory, and then switch from memory expansion mode to microprocessor mode. (Because in general, the problem will not occur when switching the modes as long as the same memory is accessed after the switch. (c) Load a simple program in RAM that switches the modes, jump to RAM and execute the program, then jump to the location of the code to run after the processor mode has switched. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 37 of 108 APPENDIX 7641 Group 3.3 Notes on use 3.3.9 Notes on timer (1) Read/Write for timer • The timer division ratio is : 1 / (n + 1) (n = “ 0 ” t o “ 255 ” w ritten into the timer) •Read and write operation on 16-bit timer (Timers X and Y) must be performed for both high and loworder bytes. •When reading the 16-bit timer (Timers X and Y), read the high-order byte first and then the low-order byte. When writing to the 16-bit timer, write the low-order byte first and then the high-order byte. • Do not read the 16-bit timer during the write operation, or do not write to it during the read operation. • When the value is loaded only in the latch, the value is loaded in the timer at the count pulse following the count where the timer reaches “ 00 16” . • In the timers 1 to 3, switching of the count sources of timers 1 to 3 does not affect the values of reload latches. However, that may make count operation started. Therefore, write values again in the order of timers 1, 2 and then timer 3 after their count sources have been switched. •In the timer mode (for timers X, Y, 1 to 3), event counter mode (for timers X, Y), pulse output mode (for timers X, Y, 1, 2), the timer current count value can be read out by reading the timer. •In the pulse width measurement mode (for timer X), period measurement mode (for timer Y), pulse width HL continuously measurement mode (for timer Y), the measured timer value is stored into the internal temporary register. When reading the timer, the value of internal temporary register is read out. The contents of internal temporary register is updated after the next measurement. (2) Pulse output • When using the pulse output mode of timer X, set bit 3 of port P4 direction register to “ 1 ” ( output mode). •When using the TYOUT output of timer Y, set bit 4 of port P4 direction register to “1” (output mode). •When using the TOUT output of timer 1 or timer 2, set bit 1 of port P5 direction register to “1” (output mode). • The T OUT o utput pin is shared with the X COUT p in. Accordingly, when using f(X CIN)/2 as the timer 1 count source (bit 2 of timer 123 mode register = “ 0 ” ), X COUT o scillation drive must be disabled (bit 5 of clock control register = “ 1 ” ) to input clocks from the X CIN p in. • The P51/X COUT/TOUT p in cannot function as an ordinary I/O port while X CIN-X COUT i s oscillating. When XCIN-XCOUT o scillation is stopped or X COUT o scillation drive is disabled, this can be used as the TOUT output pin of timer 1 or 2. (3) Pulse input • When using the timer X in the event counter or pulse width measurement mode, set bit 3 of port P4 direction register to “ 0 ” ( input mode). •When using the timer Y in the period measurement, event counter or pulse width HL continuously measurement mode, set bit 4 of port P4 direction register to “ 0 ” ( input mode). (4) Interrupt In the timer Y’s pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR 1 pin input signal regardless of the setting of CNTR 1 active edge switch bit of timer Y mode register. (5) At STP instruction executed When the STP instruction is executed or Reset occurs, the timer 1 is set to “ FF16” a nd the internal clock φ divided by 8 is automatically selected as its count source. Additionally, the timer 2 is set to “0116” and the timer 1’s output is automatically selected as its count source. When the STP instruction is being executed, all bits except bit 4 of the timer 123 mode register (address 0029 16) are initialized to “ 0 ” . It is not necessary to set T123M1 (timer 1 count stop bit) to “ 0 ” b efore executing the S TP Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 38 of 108 APPENDIX 7641 Group 3.3 Notes on use instruction. After returning from Stop mode, reset the timer 1 (address 0024 16), timer 2 (address 002516), and the timer 123 mode register (address 0029 16). 3.3.10 Notes on Stop mode • When the STP instruction is executed, bit 7 of the clock control register (address 001F 16) goes to “ 0 ” . To return from stop mode, reset CCR7 to “ 1 ” . •When using f SYN (set internal system clock select bit (CPMA6) to “1”) as the internal system clock, switch CPMA6 to “0” before executing the STP instruction. Reset CPMA6 after the system returns from Stop Mode and the frequency synthesizer has stabilized. CPMA6 does not need to be switched to “ 0 ” w hen using the W IT i nstruction. •When the STP instruction is executed or Reset occurs, the timer 1 is set to “FF16” and the internal clock φ d ivided by 8 is automatically selected as its count source. Additionally, the timer 2 is set to “ 01 16” a nd the timer 1 ’ s output is automatically selected as its count source. When the S TP instruction is being executed, all bits except bit 4 of the timer 123 mode register (address 0029 16) are initialized to “ 0 ” . It is not necessary to set T123M1 (timer 1 count stop bit) to “ 0 ” b efore executing the STP instruction. After returning from Stop mode, reset the timer 1 (address 002416), timer 2 (address 002516), and the timer 123 mode register (address 0029 16). 3.3.11 Notes on reset (1) Connecting capacitor In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the V SS p in. Use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following : • M ake the length of the wiring which is connected to a capacitor as short as possible. • B e sure to verify the operation of application products on the user side. q R eason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may cause a microcomputer failure. 3.3.12 Notes on I/O port (1) Notes in standby state In standby state ✽1 f or low-power dissipation, do not make input levels of an I/O port “ undefined ” . Pull-up (connect the port to V CC ) or pull-down (connect the port to V SS ) these ports through a resistor. When determining a resistance value, note the following points: • E xternal circuit • V ariation of output levels during the ordinary operation When using built-in pull-up resistor, note on varied current values: • W hen setting as an input port : Fix its input level • When setting as an output port : Prevent current from flowing out to external q Reason The potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an I/O port are “ undefined ” . This may cause power source current. ✽1 standby state: stop mode by executing S TP i nstruction wait mode by executing W IT i nstruction Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 39 of 108 APPENDIX 7641 Group 3.3 Notes on use (2) Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction✽2, the value of the unspecified bit may be changed. q R eason The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an I/O port, the following is executed to all bits of the port latch. • As for bit which is set for input port: The pin state is read in the CPU, and is written to this bit after bit managing. • As for bit which is set for output port: The bit value is read in the CPU, and is written to this bit after bit managing. Note the following: •Even when a port which is set as an output port is changed for an input port, its port latch holds the output data. • As for a bit of which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. ✽ 2 Bit managing instructions: S EB a nd C LB i nstructions (3) Pull-up control When using port P2, which includes a pull-up resistor, as an output port, its port pull-up control is invalidated, that is, pull-up cannot be enabled. q R eason Pull-up/pull-down control is valid only when each direction register is set to the input mode. 3.3.13 Notes on programming (1) Processor status register ➀ Initializing of processor status register Flags which affect program execution must be initialized after a reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations. q Reason After a reset, the contents of the processor status register (PS) are undefined except for the I flag which is “ 1 ” . Reset ↓ Initializing of flags ↓ Main program Fig. 3.3.5 Initialization of processor status register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 40 of 108 APPENDIX 7641 Group 3.3 Notes on use ➁ How to reference the processor status register To reference the contents of the processor status register (PS), execute the PHP instruction once then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its original status. A N OP i nstruction should be executed after every P LP i nstruction. Be sure to execute the SEI instruction before the PLP instruction. If executing the CLI instruction, do it after the N OP i nstruction PLP instruction execution ↓ NOP (S) (S)+1 Stored PS Fig. 3.3.6 Sequence of PLP instruction execution Fig. 3.3.7 Stack memory contents after PHP instruction execution (2) BRK Instruction It can be detected that the B RK i nstruction interrupt event or the least priority interrupt event by referring the stored B flag state. Refer to the stored B flag state in the interrupt routine. (3) Decimal Calculations When decimal mode is selected, the values of the V flags are invalid. The carry flag (C) is set to “ 1 ” i f a carry is generated as a result of the calculation, or is cleared to “ 0 ” i f a borrow is generated. To determine whether a calculation has generated a carry, the C flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be initialized to “ 1 ” b efore each calculation. (4) Multiplication and Division Instructions The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. (5) Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 41 of 108 APPENDIX 7641 Group 3.3 Notes on use 3.3.14 Termination of unused pins (1) Terminate unused pins ➀ I /O ports : • S et the I/O ports for the input mode and connect them to V CC o r V SS t hrough each resistor of 1 k Ω t o 10 k Ω . Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/O ports for the output mode and open them at “ L ” o r “ H ” . • W hen opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. • Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. (2) Termination remarks ➀ I /O ports : Do not open in the input mode. q Reason • T he power source current may increase depending on the first-stage circuit. • A n effect due to noise may be easily produced as compared with proper termination ➁ a nd shown on the above. ➁ I /O ports : When setting for the input mode, do not connect to V CC o r V SS d irectly. q Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and V CC ( or V SS ). ➂ I /O ports : When setting for the input mode, do not connect multiple ports in a lump to V CC o r VSS t hrough a resistor. q Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. • At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 42 of 108 APPENDIX 7641 Group 3.3 Notes on use 3.3.15 Notes on CPU rewrite mode for flash memory version The below notes applies when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the internal clock φ t o 6 MHz or less using the X IN d ivider select bit (bit 7 of address 001F 16). (2) Instructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during CPU rewrite mode . (3) Interrupts inhibited against use The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. (4) Reset Reset is always valid. When CNV SS i s “ H ” a t reset release, the program starts from the address stored in addresses FFFA 16 a nd FFFB16 o f the boot ROM area in order that CPU may start in boot mode. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 43 of 108 APPENDIX 7641 Group 3.4 Countermeasures against noise 3.4 Countermeasures against noise Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 3.4.1 Shortest wiring length The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm). q Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise Reset circuit VSS N.G. RESET VSS Reset circuit VSS RESET VSS O.K. Fig. 3.4.1 Wiring for the RESET pin (2) Wiring for clock input/output pins • M ake the length of wiring which is connected to clock I/O pins as short as possible. • M ake the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the V SS p in of a microcomputer as short as possible. • S eparate the VSS p attern only for oscillation from other VSS p atterns. q Reason If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the V SS level of a microcomputer and the V SS l evel of an oscillator, the correct clock will not be input in the microcomputer. Noise XIN XOUT VSS N.G. XIN XOUT VSS O.K. Fig. 3.4.2 Wiring for clock I/O pins Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 44 of 108 APPENDIX 7641 Group 3.4 Countermeasures against noise 3.4.2 Connection of bypass capacitor across V SS l ine and V CC line Connect an approximately 0.1 µ F bypass capacitor across the V SS l ine and the V CC l ine as follows: • C onnect a bypass capacitor across the V SS p in and the VCC p in at equal length. • C onnect a bypass capacitor across the V SS p in and the V CC p in with the shortest possible wiring. • U se lines with a larger diameter than other signal lines for V SS l ine and V CC l ine. • C onnect the power source wiring via a bypass capacitor to the V SS p in and the V CC p in. In use of the 7641 group it is recommended to connect 0.1 µ F and 4.7 µF capacitors in parallel between pins Vcc and Vss, and pins AVss and AVcc. However, their capacitors must not be allocated near the LPF pin. VCC VCC VSS VSS N.G. O.K. VSS (AVSS) 4.7 µS 0.1 µS VCC (AVCC) Fig. 3.4.3 Bypass capacitor across the V SS l ine and the V CC l ine Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 45 of 108 APPENDIX 7641 Group 3.4 Countermeasures against noise 3.4.3 Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. q Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. Microcomputer Mutual inductance M Large current GND XIN XOUT VSS Fig. 3.4.4 Wiring for a large current signal line (2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. q Reason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. N.G. Do not cross CNTR XIN XOUT VSS Fig. 3.4.5 Wiring for signal lines where potential levels change frequently Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 46 of 108 APPENDIX 7641 Group 3.4 Countermeasures against noise (3) Oscillator protection using VSS p attern As for a two-sided printed circuit board, print a V SS pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the V SS p attern to the microcomputer V SS p in with the shortest possible wiring. Besides, separate this V SS p attern from other V SS p atterns. An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example XIN XOUT VSS Separate the VSS line for oscillation from other VSS lines Fig. 3.4.6 V SS p attern on the underside of an oscillator 3.4.4 Setup for I/O ports Setup I/O ports using hardware and software as follows: • C onnect a resistor of 100 Ω o r more to an I/O port in series. • A s for an input port, read data several times by a program for checking whether input levels are equal or not. • As for an output port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods. • R ewrite data to direction registers at fixed periods. Note: W hen a direction register is set for i nput port again at fixed periods, a several-nanosecond short pulse may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise pulse. O.K. Noise Data bus Direction register N.G. Port latch I/O port pins Noise Fig. 3.4.7 Setup for I/O ports Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 47 of 108 APPENDIX 7641 Group 3.4 Countermeasures against noise 3.4.5 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. • Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N+1 ≥ ( Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. • Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set. • Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents do not change after interrupt processing. • D ecrements the SWDT contents by 1 at each interrupt processing. • D etermines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count). • D etects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less. Main routine (SWDT) ← N CLI Main processing ≠N (SWDT) =N? N Interrupt processing routine (SWDT) ← (SWDT)—1 Interrupt processing >0 RTI Return Main routine errors (SWDT) ≤0? ≤0 Interrupt processing routine errors Fig. 3.4.8 Watchdog timer by software Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 48 of 108 APPENDIX 7641 Group 3.5 Control registers 3.5 Control registers CPU mode register A b7 b6 b5 b4 b3 b2 b1 b0 1 CPU mode register A (CPMA : address 0016) b Name b1b0 Functions 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode (Note 1) 1 1 : Not available 0 : Page 0 1 : Page 1 0 : Stopped 1 : Oscillating 0 : Oscillating 1 : Stopped 0 : External clock (XIN-XOUT or XCIN-XCOUT) 1 : fsyn 0 : XIN-XOUT 1 : XCIN-XCOUT At reset R W 0 0 1 1 0 0 0 0 0 Processor mode bits 1 2 Stack page select bit 3 Fix this bit to “1”. 4 Sub-clock (XCIN-XCOUT) stop bit 5 Main clock (XIN-XOUT) stop bit 6 Internal system clock select bit (Note 2) 7 External clock select bit Notes 1: This is not available in the flash memory version. 2: When (CPMA 7, 6) = (0, 0), the internal system clock can be selected between f(XIN) and f(XIN)/2 by CCR7. The internal clock φ is the internal system clock divided by 2. Fig. 3.5.1 Structure of CPU mode register A CPU mode register B b7 b6 b5 b4 b3 b2 b1 b0 10 CPU mode register B (CPMB : address 0116) b Name b1b0 Functions 0 0 : No wait 0 1 : One-time wait 1 0 : Two-time wait 1 1 : Three-time wait b3b2 At reset R W 1 1 0 0 0 Slow memory wait select bits 1 2 Slow memory wait mode select bits 3 0 0 : Software wait 0 1 : Not available 1 0 : RDY wait 1 1 : Software wait plus RDY input anytime wait anytime wait 0 : EDMA output disabled 1 : EDMA output enabled 0 : HOLD function disabled 1 : HOLD function enabled 4 Expanded data memory access bit 5 HOLD function enable bit 6 Fix this bit to “0”. 7 Fix this bit to “1”. 0 0 0 1 Fig. 3.5.2 Structure of CPU mode register B Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 49 of 108 APPENDIX 7641 Group 3.5 Control registers Interrupt request register A b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register A (IREQA : address 0216) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ 0 USB function interrupt request bit 1 USB SOF interrupt request 0 : No interrupt request issued bit 1 : Interrupt request issued 0 : No interrupt request issued 2 INT0 interrupt request bit 1 : Interrupt request issued 3 INT1 interrupt request bit 4 DMAC0 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 5 DMAC1 interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit 6 UART1 receive buffer full 0 : No interrupt request issued 1 : Interrupt request issued interrupt request bit 7 UART1 transmit interrupt 0 : No interrupt request issued request bit 1 : Interrupt request issued ✽: “0” can be set by software, but “1” cannot be set. Fig. 3.5.3 Structure of Interrupt request register A Interrupt request register B b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register B (IREQB : address 0316) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ 0 UART1 summing error interrupt request bit 1 UART2 receive buffer full interrupt request bit 2 UART2 transmit interrupt request bit 3 UART2 summing error interrupt request bit 4 Timer X interrupt request bit 5 Timer Y interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit 6 Timer 1 receive buffer full 0 : No interrupt request issued 1 : Interrupt request issued interrupt request bit 7 Timer 2 transmit interrupt 0 : No interrupt request issued request bit 1 : Interrupt request issued ✽: “0” can be set by software, but “1” cannot be set. Fig. 3.5.4 Structure of Interrupt request register B Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 50 of 108 APPENDIX 7641 Group 3.5 Control registers Interrupt request register C b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register C (IREQC : address 0416) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 ✽ ✽ ✽ ✽ ✽ ✽ ✽ 0 Timer 3 interrupt request bit 1 CNTR0 interrupt request bit 2 CNTR1 interrupt request bit 3 Serial I/O interrupt request bit 4 Input buffer full interrupt request bit 5 Output buffer empty interrupt request bit 6 Key input interrupt request bit 7 Fix this bit to “0”. ✽: “0” can be set by software, but “1” cannot be set. Fig. 3.5.5 Structure of Interrupt request register C Interrupt control register A b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register A (ICONA : address 0516) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 0 0 0 0 0 0 USB function interrupt enable bit 1 USB SOF interrupt enable 0 : Interrupt disabled bit 1 : Interrupt enabled 0 : Interrupt disabled 2 INT0 interrupt enable bit 1 : Interrupt enabled 3 INT1 interrupt enable bit 4 DMAC0 interrupt enable bit 5 DMAC1 interrupt enable bit 6 UART1 receive buffer full interrupt enable bit 7 UART1 transmit interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Fig. 3.5.6 Structure of Interrupt control register A Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 51 of 108 APPENDIX 7641 Group 3.5 Control registers Interrupt control register B b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register B (ICONB : address 0616) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 0 0 0 0 0 0 UART1 summing error interrupt enable bit 1 UART2 receive buffer full interrupt enable bit 2 UART2 transmit interrupt enable bit 3 UART2 summing error interrupt enable bit 4 Timer X interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 5 Timer Y interrupt enable 1 : Interrupt enabled bit 6 Timer 1 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 7 Timer 2 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled Fig. 3.5.7 Structure of Interrupt control register B Interrupt control register C b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt control register C (ICONC : address 0716) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 Timer 3 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 1 CNTR0 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 2 CNTR1 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 3 Serial I/O interrupt enable bit 4 Input buffer full interrupt enable bit 5 Output buffer empty interrupt enable bit 6 Key input interrupt enable bit 7 Fix this bit to “0”. 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Fig. 3.5.8 Structure of Interrupt control register C Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 52 of 108 APPENDIX 7641 Group 3.5 Control registers Port Pi b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (i = 0, 1, 2, 3, 5, 6, 8) (Pi : addresses 0816, 0A16, 0C16, 0E16, 1616, 1416, 1C16) b 0 Port Pi0 1 Port Pi1 2 Port Pi2 3 Port Pi3 4 Port Pi4 5 Port Pi5 6 Port Pi6 7 Port Pi7 Name Functions qIn output mode Write •••••••• Port latch Read •••••••• Port latch qIn input mode Write •••••••• Port latch Read •••••••• Value of pin At reset R W 0 0 0 0 0 0 0 0 Fig. 3.5.9 Structure of Port Pi Port P4, Port P7 b7 b6 b5 b4 b3 b2 b1 b0 Port P4, Port P7 (P4, P7 : addresses 1816, 1A16) b Name Functions qIn output mode Write •••••••• Port latch Read •••••••• Port latch qIn input mode Write •••••••• Port latch Read •••••••• Value of pin At reset R W 0 0 0 0 0 0 Port P40 or Port P70 1 Port P41 or Port P71 2 Port P42 or Port P72 3 Port P43 or Port P73 4 Port P44 or Port P74 5 Nothing is arranged for these bits. These are write disable bits. When Undefined ✕ ✕ 6 these bits are read out, the contents are undefined. Undefined ✕ ✕ Undefined ✕ ✕ 7 Fig. 3.5.10 Structure of Port P4, Port P7 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 53 of 108 APPENDIX 7641 Group 3.5 Control registers Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (i = 0, 1, 2, 3, 5, 6, 8) (PiD : addresses 0916, 0B16, 0D16, 0F16, 1716, 1516, 1D16) b Name Functions 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode At reset R W 0 0 0 0 0 0 0 0 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ 0 Port Pi direction register 1 2 3 4 5 6 7 Fig. 3.5.11 Structure of Port Pi direction register Port P4, P7 direction registers b7 b6 b5 b4 b3 b2 b1 b0 Port P4 direction register, Port P7 direction register (P4D, P7D : addresses 1916, 1B16) b Name Functions 0 : Port P40 or P70 input mode 1 : Port P40 or P70 output mode 0 : Port P41 or P71 input mode 1 : Port P41 or P71 output mode 0 : Port P42 or P72 input mode 1 : Port P42 or P72 output mode 0 : Port P43 or P73 input mode 1 : Port P43 or P73 output mode 0 : Port P44 or P74 input mode 1 : Port P44 or P74 output mode At reset R W 0 0 0 0 0 ✕ ✕ ✕ ✕ ✕ 0 Port P4 direction register Port P7 direction register 1 2 3 4 5 Nothing is arranged for these bits. These are write disable bits. When Undefined ✕ ✕ 6 these bits are read out, the contents are undefined. Undefined ✕ ✕ Undefined ✕ ✕ 7 Fig. 3.5.12 Structure of Port P4, Port P7 direction registers Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 54 of 108 APPENDIX 7641 Group 3.5 Control registers Port control register b7 b6 b5 b4 b3 b2 b1 b0 Port control register (PTC : address 1016) b 0 1 2 3 4 5 6 7 Name Port P0 to P3 slew rate control bit (Note 1) Port P4 slew rate control bit (Note 1) Port P5 slew rate control bit (Note 1) Port P6 slew rate control bit (Note 1) Port P7 slew rate control bit (Note 1) Port P8 slew rate control bit (Note 1) Port P2 input level select bit Master CPU bus input level select bit Functions 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Reduced VIHL level input (Note 2) 1 : CMOS level input 0 : CMOS level input 1 : TTL level input At reset R W 0 0 0 0 0 0 0 0 Notes 1: The slew rate function can reduce di/dt by modifying an internal buffer structure. 2: The characteristics of VIHL level is basically the same as that of TTL level. But, its switching center point is a little higher than TTL’s. Fig. 3.5.13 Structure of Port control register Interrupt polarity select register b7 b6 b5 b4 b3 b2 b1 b0 000000 Interrupt polarity select register (IPOL : address 1116) b Name Functions 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active At reset R W 0 0 0 0 0 0 0 0 0 INT0 interrupt edge select bit 1 INT1 interrupt edge select bit 2 Fix these bits to “0”. 3 4 5 6 7 Fig. 3.5.14 Structure of Interrupt polarity select register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 55 of 108 APPENDIX 7641 Group 3.5 Control registers Port P2 pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Port P2 pull-upt control register (PUP2 : address 1216) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 Port P20 pull-up control bit 0 : Disabled 1 : Enabled 1 Port P21 pull-up control bit 0 : Disabled 1 : Enabled 2 Port P22 pull-up control bit 0 : Disabled 1 : Enabled 3 Port P23 pull-up control bit 0 : Disabled 1 : Enabled 4 Port P24 pull-up control bit 0 : Disabled 1 : Enabled 5 Port P25 pull-up control bit 0 : Disabled 1 : Enabled 6 Port P26 pull-up control bit 0 : Disabled 1 : Enabled 7 Port P27 pull-up control bit 0 : Disabled 1 : Enabled Fig. 3.5.15 Structure of Port P2 pull-up control register USB control register b7 b6 b5 b4 b3 b2 b1 b0 0 USB control register (USBC : address 1316) b Name Functions At reset R W 0 0 0 Fix this bit to “0”. 1 USB default state selection 0 : In default state after power-on/reset bit (USBC1) 1 : In default state after USB reset signal received 2 USB artificial SOF enable 0 : Artificial SOF disabled 1 : Artificial SOF enabled bit (USBC2) 3 USB line driver current control bit (USBC3) 4 USB line driver supply enable bit (USBC4) (Note 1) 5 USB clock enable bit (USBC5) 6 USB SOF port select bit (USBC6) USB enable bit (USBC7) 7 0 : High current mode 1 : Low current mode 0 : Line driver disabled 1 : Line driver enabled 0 : 48 MHz clock to the USB block disabled 1 : 48 MHz clock to the USB block enabled 0 : SOF output disabled 1 : SOF output enabled 0 : USB block disabled (Note 2) 1 : USB block enabled 0 0 0 0 0 0 Notes 1: When using the MCU in Vcc = 3.3 V, set this bit to “0” and disable the built-in DCDC converter. 2: Setting this bit to 0” causes the contents of all USB registers to have the values at reset. Fig. 3.5.16 Structure of USB control register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 56 of 108 APPENDIX 7641 Group 3.5 Control registers Clock control register b7 b6 b5 b4 b3 b2 b1 b0 00000 Clock control register (CCR : address 1F16) b Name Functions At reset R W 0 0 0 0 0 0 Fix these bits to “0”. 1 2 3 4 5 XCOUT oscillation drive disable bit (CCR5) 6 XOUT oscillation drive disable bit (CCR6) 7 XIN divider select bit (CCR7) (Note) 0 : XCOUT oscillation drive is enabled. (When XCIN oscillation is enabled.) 1 : XCOUT oscillation drive is disabled. 0 : XOUT oscillation drive is enabled. (When XIN oscillation is enabled.) 1 : XOUT oscillation drive is disabled. 0 : f(XIN)/2 is used for the system clock. 1 : f(XIN) is used for the system clock. 0 0 0 Note: This bit is valid when (b7, b6 of CPMA) = “00”. Fig. 3.5.17 Structure of Clock control register Timer X (low, high) b7 b6 b5 b4 b3 b2 b1 b0 Timer XL, Timer XH (TXL, TXH: addresses 2016, 2116) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qTimer X’s count value is set through this register. qWriting operation depends on the timer X write control bit. When it is “0”, the values are simultaneously written into timer X 1 latch and counter. 2 When it is “1”, the values are written into only timer X latch. qTimer X is a down-count timer. 3 qWhen reading this register’s address, the timer X’s count value is read out. 4 5 6 7 Notes 1: Read and write operation to timer X must be performed for both high and low-order bytes. 2: When reading timer X, read the high-order byte first and then the low-order byte. 3: When writing to timer X, write the low-order byte first and then the high-order byte. 4: Do not read this register during the write operation, or do not write during the read operation. Fig. 3.5.18 Structure of Timer X Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 57 of 108 APPENDIX 7641 Group 3.5 Control registers Timer Y (low, high) b7 b6 b5 b4 b3 b2 b1 b0 Timer YL, Timer YH (TYL, TYH: addresses 2216, 2316) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qTimer Y’s count value is set through this register. qTimer Y is a down-count timer. 1 qWhen reading this register’s address, the timer Y’s count value is read out. 2 3 4 5 6 7 Notes 1: Read and write operation to timer X must be performed for both high and low-order bytes. 2: When reading timer X, read the high-order byte first and then the low-order byte. 3: When writing to timer X, write the low-order byte first and then the high-order byte. 4: Do not read this register during the write operation, or do not write during the read operation. Fig. 3.5.19 Structure of Timer Y Timer i (i = 1 to 3) b7 b6 b5 b4 b3 b2 b1 b0 Timer 1, Timer 2, Timer 3 (T1, T2, T3: addresses 2416, 2516, 2616) b 0 1 2 3 4 5 6 7 Functions qTimer i’s count value is set through this register. qTimer 1 and Timer 2 Writing operation depends on the timers 1, 2 write control bit. When it is “0”, the values are simultaneously written into their latches and counters. When it is “1”, the values are written into only their latches. qTimer 3 The values are simultaneously written into their latches and counters. qWhen reading this register’s address, its timer’s count values are read out. qThe timer causes an underflow at the count pulse following the count where the timer contents reaches “0016”. Then The contents of latches are automatically reloaded into the timer. At reset R W (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) Note: Timer 1 and Timer 3’s values are “FF16”. Timer 2 ’s value are “0116”. Fig. 3.5.20 Structure of Timer i Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 58 of 108 APPENDIX 7641 Group 3.5 Control registers Timer X mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register (TXM : address 2716) b Name Functions 0 : Write value in latch and counter 1 : Write value in latch only b2b1 At reset R W 0 0 0 0 0 0 0 0 0 Timer X write control bit 1 Timer X count source select bits 2 3 Timer X internal clock select bit 4 Timer X operating mode bits 00:φ/8 0 1 : φ / 16 1 0 : φ / 32 1 1 : φ / 64 0 : φ / n (n = 8, 16, 32, 64) 1 : SCSGCLK (Special Count Source Generator) b5b4 0 0 : Timer mode 0 1 : Pulse output mode 5 1 0 : Event counter mode 1 1 : Pulse width measurement mode 6 CNTR0 active edge switch This function depends on the timer X operating mode. (See below.) bit 0 : Count start 7 Timer X count stop bit 1 : Count stop Function of CNTR0 active edge switch bit Timer X operating mode Pulse output mode Event counter mode Pulse width measurement mode Interrupt CNTR0 active edge switch bit 0 : Starts at “H” output 1 : Starts at “L” output 0 : Counts at rising edge 1 : Counts at falling edge 0 : Measures “H” pulse width 1 : Measures “L” pulse width 0 : Falling edge active 1 : Rising edge active Fig. 3.5.21 Structure of Timer X mode register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 59 of 108 APPENDIX 7641 Group 3.5 Control registers Timer Y mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer Y mode register (TYM : address 2816) b Name Functions 0 : Write value in latch and counter 1 : Write value in latch only 0 : TYOUT output disabled 1 : TYOUT output enabled b3b2 At reset R W 0 0 0 0 0 0 Timer Y write control bit 1 Timer Y output control bit 2 Timer Y count source select bits 3 4 Timer Y operating mode bits 00:φ/8 0 1 : φ / 16 1 0 : φ / 32 1 1 : φ / 64 b5b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 5 1 1 : Pulse width HL continuously measurement mode 6 CNTR1 active edge switch This function depends on the timer Y operating mode. (See below.) bit 0 : Count start 7 Timer Y count stop bit 1 : Count stop 0 0 0 Function of CNTR1 active edge switch bit CNTR1 active edge switch bit 0 : Measures between falling edges Period measurement mode 1 : Measures between rising edges 0 : Counts at rising edge Event counter mode 1 : Counts at falling edge 0 : Starts at “H” output TYOUT output 1 : Starts at “L” output Interrupt 0 : Falling edge active 1 : Rising edge active Timer Y operating mode Fig. 3.5.22 Structure of Timer Y mode register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 60 of 108 APPENDIX 7641 Group 3.5 Control registers Timer 123 mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer 123 mode register (T123M : address 2916) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 TOUT factor select bit 1 2 3 4 5 6 7 0 : Timer 1 output 1 : Timer 2 output 0 : Count start Timer 1 count stop bit 1 : Count stop Timer 1 count source 0:φ/8 select bit 1 : f(XCIN) / 2 Timer 2 count source 0 : Timer 1 output select bit 1:φ 0 : Timer 1 output Timer 3 count source 1:φ/8 select bit TOUT output active edge 0 : Start at “H” output switch bit 1 : Start at “L” output TOUT output control bit 0 : TOUT output disabled 1 : TOUT output enabled Timers 1, 2 write control bit 0 : Write value in latch and counter 1 : Write value in latch only Fig. 3.5.23 Structure of Timer 123 mode register Serial I/O shift register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O shift register (SIOSHT: address 2A16) b Functions At reset R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 qAt transmitting Writing transmitted data to this register starts transmitting operation. 1 2 qAt receiving Read received data through this register. 3 4 5 6 7 Fig. 3.5.24 Structure of Serial I/O shift register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 61 of 108 APPENDIX 7641 Group 3.5 Control registers Serial I/O control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O control register 1 (SIOCON1 : address 2B16) b Name b2b1b0 Functions 0 0 0 : Internal clock divided by 2 0 0 1 : Internal clock divided by 4 0 1 0 : Internal clock divided by 8 0 1 1 : Internal clock divided by 16 1 0 0 : Internal clock divided by 32 1 0 1 : Internal clock divided by 64 1 1 0 : Internal clock divided by 128 1 1 1 : Internal clock divided by 256 At reset R W 0 0 Internal synchronous clock select bits (Note) 1 2 3 Serial I/O port select bit 0 0 0 : I/O port 1 : STXD, SCLK signal output 0 : I/O port 4 SRDY output select bit 1 : SRDY signal output Transfer direction select bit 0 : LSB first 5 1 : MSB first 6 Synchronous clock select 0 : External clock 1 : Internal clock bit 0 : CMOS output 7 STXD output channel 1 : N-channel open drain output control bit Note: The source of serial I/O internal synchronous clock can be selected by I/O control register 2 0 0 0 1 0 bit 1 of serial Fig. 3.5.25 Structure of Serial I/O control register 1 Serial I/O control register 2 b7 b6 b5 b4 b3 b2 b1 b0 000 Serial I/O control register 2 (SIOCON2 : address 2C16) b Name Functions 0 : Normal serial I/O mode 1 : SPI compatible mode (Note) 0:φ 1 : SCSGCLK 0 : SRXD input disabed 1 : SRXD input enabed 0 : SCLK starting at “L” 1 : SCLK starting at “H” 0 : Serial transfer starting at falling edge of SRDY 1 : Serial transfer starting after a half cycle of SCLK passed at falling edge of SRDY At reset R W 0 0 0 1 1 0 SPI mode select bit 1 Serial I/O internal clock select bit 2 SRXD input enable bit 3 Clock polarity select bit (CPoL) 4 Clock phase select bit (CPha) 0 5 Fix these bits to “0”. 0 6 7 0 Note: To set the slave mode, also set bit 4 of serial I/O control register 1 to “1”. Fig. 3.5.26 Structure of Serial I/O control register 2 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 62 of 108 APPENDIX 7641 Group 3.5 Control registers Special count source generator 1 b7 b6 b5 b4 b3 b2 b1 b0 Special count source generator 1 (SCSG1: address 2D16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qThis is a 8-bit down-count timer. The division ratio : 1 / (n1 +1), n1: value set to SCSG1. 1 2 3 4 5 6 7 Fig. 3.5.27 Structure of Special count source generator 1 Special count source generator 2 b7 b6 b5 b4 b3 b2 b1 b0 Special count source generator 2 (SCSG2: address 2E16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qThis is a 8-bit down-count timer. An output from SCSG1 is divided by the contents of SCSG2 to generate SCSGCLK. 1 2 qThe count source, an output from SCSG1, is φ • n1 / (n1 +1). 3 qSCSGCLK frequency: φ • n1 / (n1 +1) • 1 / (n2 +1) n1: value set to SCSG1 4 n2: value set to SCSG2 5 6 7 Fig. 3.5.28 Structure of Special count source generator 2 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 63 of 108 APPENDIX 7641 Group 3.5 Control registers Special count source mode register b7 b6 b5 b4 b3 b2 b1 b0 0000 Special count source mode register (SCSGM : address 2F16) b Name Functions 0 : Writing data into both timer latch and timer simultaneously 1 : Writing data into timer latch 0 : Count start 1 : Count stop 0 : Writing data into both timer latch and timer simultaneously 1 : Writing data into timer latch 0 : SCSGCLK output disabled (SCSG1 and SCSG2 counts stop) 1 : SCSGCLK output enabled At reset R W 0 0 SCSG1 data write control bit 1 SCSG1 count stop bit 2 SCSG2 data write control bit 3 SCSGCLK output control bit 4 Fix these bits to “0”. 5 6 7 0 0 0 0 0 0 0 Fig. 3.5.29 Structure of Special count source mode register UARTx mode register b7 b6 b5 b4 b3 b2 b1 b0 UARTx (x = 1, 2) mode register (UxMOD : addresses 3016, 3816) b Name Functions 0:φ 1 : SCSGCLK output b2b1 At reset R W 0 0 0 0 0 0 0 0 0 UART clock select bit (CLK) 1 UART clock prescaling select bits (PS) 2 3 Stop bit length select bit (STB) 4 Parity select bit (PMD) 5 Parity enable bit (PEN) 6 UART character length select bit (LE1, 0) 7 0 0 : UART clock divided by 1 0 1 : UART clock divided by 8 1 0 : UART clock divided by 32 1 1 : UART clock divided by 256 0 : 1 stop bit 1 : 2 stop bits 0 : Even parity 1 : Odd parity 0 : Parity checking disabled 1 : Parity checking enabled b7b6 0 0 : 7 bits 0 1 : 8 bits 1 0 : 9 bits 1 1 : Not available Fig. 3.5.30 Structure of UARTx (x = 1, 2) mode register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 64 of 108 APPENDIX 7641 Group 3.5 Control registers UARTx baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 UARTx (x = 1, 2) baud rate generator (UxBRG: addresses 3116, 3916) b Functions At reset R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 qThe UxBRG determines the baud rate for transfer. 1 qThis is a 8-bit counter with its reload register. This generator divides the frequency of the count source by 1/(n + 1), where “n” is the 2 value written to the UxBRG. 3 4 5 6 7 Fig. 3.5.31 Structure of UARTx (x = 1, 2) baud rate generator UARTx status register b7 b6 b5 b4 b3 b2 b1 b0 UARTx (x = 1, 2) status register (UxSTS : addresses 3216, 3A16) b Name Functions At reset R W 1 1 0 0 0 0 0 0 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ 0 Transmit complete flag (TCM) 1 Transmit buffer empty flag (TBE) 2 Receive buffer full flag (RBF) 3 4 5 6 7 0 : Transmit shift in progress 1 : Transmit shift completed 0 : Buffer full 1 : Buffer empty 0 : Buffer empty 1 : Buffer full 0 : No error Parity error flag (PER) 1 : Parity error Framing error flag (FER) 0 : No error 1 : Framing error 0 : No error Overrun error flag (OER) 1 : Overrun error Summing error flag (SER) 0 : (PER) U (FER) U (OER) = 0 1 : (PER) U (FER) U (OER) = 1 Nothing is arranged for this bit. This is a write disable bit. When this bit is read out, the contents are “0”. Fig. 3.5.32 Structure of UARTx (x = 1, 2) status register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 65 of 108 APPENDIX 7641 Group 3.5 Control registers UARTx control register b7 b6 b5 b4 b3 b2 b1 b0 UARTx (x = 1, 2) control register (UxCON : addresses 3316, 3B16) b Name Functions 0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled 0 : No action 1 : Initializing (Note 1) 0 : No action 1 : Initializing (Note 2) 0 : Interrupt when transmit buffer has emptied 1 : Interrupt when transmit shift operation is completed 0 : CTS function disabled (Note 3) 1 : CTS function enabled 0 : RTS function disabled (Note 4) 1 : RTS function enabled 0 : Address mode disabled 1 : Address mode enabled At reset R W 0 0 0 0 0 0 Transmit enable bit (TEN) 1 Receive enable bit (REN) 2 Transmit initialization bit (TIN) 3 Receive initialization bit (RIN) 4 Transmit interrupt source select bit (TIS) 5 CTS function enable bit (CTS_SEL) 6 RTS function enable bit (RTS_SEL) 7 UART address mode enable bit (AME) 0 0 0 Notes 1: When setting the TIN bit to “1”, the TEN bit is set to “0” and the UARTx status register will be set to “0316” after the data has been transmitted. To retransmit, set the TEN bit to “1” and set a data to the transmit buffer register again. The TIN bit will be cleared to “0” one cycle later after the TIN bit has been set to “1”. 2: Setting the RIN bit to “1” suspends the receiving operation and will set all of the REN, RBF and the receive error flags (PER, FER, OER, SER) to “0”. The RIN bit will be cleared to “0” one cycle later after the RIN bit has been set to “1”. 3: When CTS function is disabled (CTS_SEl = “0”), pins P82 and P86 can be used as ordinary I/O ports. 4: When RTS function is disabled (RTS_SEl = “0”), pins P83 and P87 can be used as ordinary I/O ports. Fig. 3.5.33 Structure of UARTx (x = 1, 2) control register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 66 of 108 APPENDIX 7641 Group 3.5 Control registers UARTx transmit/receive buffer registers 1, 2 b7 b6 b5 b4 b3 b2 b1 b0 UARTx (x = 1, 2) transmit/receive buffer register 1 (UxTRB1: addresses 3416, 3C16) b 0 1 2 3 4 5 6 Functions The transmit buffer register and the receive buffer register are located at the same address. Writing a transmitting data and reading a received data are performed through the UxTRB. This is its low-order byte. •At write The data is written into the transmit buffer register. It is not done into the receive buffer register. •At read The contents of receive buffer register is read. If a character bit length is 7 bits, the MSB of received data is invalid. At reset R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 Note that the contents of transmit buffer register cannot be read. b7 b6 b5 b4 b3 b2 b1 b0 UARTx (x = 1, 2) transmit/receive buffer register 2 (UxTRB2: addresses 3516, 3D16) b Functions At reset R W 0 The transmit buffer register and the receive buffer register are located Undefined at the same address. Writing a transmitting data and reading a received data are performed through the UxTRB. This is its highorder byte. •At write The data is written into the transmit buffer register. It is not done into the receive buffer register. •At read The contents of receive buffer register is read. If a character bit length is 9 bits, the received high-order 7 bits of UxTRB2 are “0” Note that the contents of transmit buffer register cannot be read. If a character bit length is 7 or 8 bits, the received contents of UxTRB2 are invalid. 1 Nothing is arranged for this bit. This is a write disable bit. When this Undefined 2 bit is read out, the contents are “0”. Undefined 3 Undefined 4 Undefined 5 Undefined 6 Undefined 7 Undefined ✕ ✕ ✕ ✕ ✕ ✕ ✕ Fig. 3.5.34 Structure of UARTx (x = 1, 2) transmit/receive buffer registers 1, 2 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 67 of 108 APPENDIX 7641 Group 3.5 Control registers UARTx RTS control register b7 b6 b5 b4 b3 b2 b1 b0 0000 UARTx (x = 1, 2) RTS control register (UxRTSC : addresses 3616, 3E16) b Name Functions At reset R W 0 0 0 0 0 0 Fix these bits to “0”. 1 2 3 4 RTS assertion delay count select bits (RTS) b7b6b5b4 5 6 7 0 0 0 0 : No delay; Assertion immediately 0 0 0 1 : 8-bit term assertion at “H” 0 0 1 0 : 16-bit term assertion at “H” 0 0 1 1 : 24-bit term assertion at “H” 0 1 0 0 : 32-bit term assertion at “H” 0 1 0 1 : 40-bit term assertion at “H” 0 1 1 0 : 48-bit term assertion at “H” 0 1 1 1 : 56-bit term assertion at “H” 1 0 0 0 : 64-bit term assertion at “H” 1 0 0 1 : 72-bit term assertion at “H” 1 0 1 0 : 80-bit term assertion at “H” 1 0 1 1 : 88-bit term assertion at “H” 1 1 0 0 : 96-bit term assertion at “H” 1 1 0 1 : 104-bit term assertion at “H” 1 1 1 0 : 112-bit term assertion at “H” 1 1 1 1 : 120-bit term assertion at “H” 0 0 1 Fig. 3.5.35 Structure of UARTx (x = 1, 2) RTS control register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 68 of 108 APPENDIX 7641 Group 3.5 Control registers DMAC index and status register b7 b6 b5 b4 b3 b2 b1 b0 0 DMAC index and status register (DMAIS : address 3F16) b Name Functions 0 : No underflow 1 : Underflow generated 0 : Not suspended 1 : Suspended 0 : No underflow 1 : Underflow generated 0 : Not suspended 1 : Suspended 0 :Suspending only burst transfers during interrupt process 1 : Suspending both burst and cycle steal transfers during interrupt process 0 :Enabling reload of source and destination registers of both channels 1 : Disabling reload of source and destination registers of both channels 0 : Channel 0 accessible 1 : Channel 1 accessible Accessed registers: Mode register, At reset R W 0 0 0 0 0 ✽ 0 DMAC channel 0 count register underflow flag (D0UF) 1 DMAC channel 0 suspend flag (D0SFI) (Note 1) 2 DMAC channel 1 count register underflow flag (D1UF) 3 DMAC channel 1 suspend flag (D1SFI) (Note 1) 4 DMAC transfer suspend control bit (DTSC) (Note 2) ✕ ✽ ✕ 5 DMAC register reload disable bit (DRLDD) (Note 3) 6 Fix this bit to “0”. 7 Channel index bit (DCI) 0 0 0 source register, destination register, transfer count register. ✽: “0” can be set by software, but “1” cannot be set. Notes 1: Suspended by an interrupt. 2: Transfer suspended during interrupt process 3: This settings affect the source and destination registers of both channels. Fig. 3.5.36 Structure of DMAC index and status register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 69 of 108 APPENDIX 7641 Group 3.5 Control registers DMAC channel x mode register 1 (x = 0, 1) b7 b6 b5 b4 b3 b2 b1 b0 DMAC channel x mode register 1 (DMAxM1 : address 4016) (Note 1) b Name Functions 0 : Increment after transfer 1 : Decrement after transfer 0 : Disabled (No change after transfer) 1 : Enabled 0 : Increment after transfer 1 : Decrement after transfer 0 : Disabled (No change after transfer) 1 : Enabled At reset R W 0 0 : Writing data in reload latches and 0 registers 1 : Writing data in reload latches only DMAC channel x disable after 0 : Channel x enabled after count 5 0 register underflow count register underflow 1 : Channel x disabled after count enable bit (DxDAUE) register underflow DMAC channel x register 0 : Not reloaded 0 6 (Note 2) 1 : Source, destination, and transfer reload bit (DxRLD) count registers contents of channel x to be reloaded 0 : Cycle steal transfer mode 7 DMAC channel x transfer 0 mode selection bit (DxTMS) 1 : Burst transfer mode Notes 1: Channels 1 and 2 share this register. The channel selection which can use this register depends on channel index bit, bit 7 of DMAC index and status register. 2: These bits’ contents are “0” at read. 0 DMAC channel x source register increment/decrement selection bit (DxSRID) 1 DMAC channel x source register increment/decrement enable bit (DxSRCE) 2 DMAC channel x destination register increment/decrement selection bit (DxDRID) 3 DMAC channel x destination register increment/decrement enable bit (DxDRCE) DMAC channel x data 4 write control bit (DxDWC) 0 0 0 Fig. 3.5.37 Structure of DMAC channel x (x = 0, 1) mode register 1 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 70 of 108 APPENDIX 7641 Group 3.5 Control registers DMAC channel 0 mode register 2 b7 b6 b5 b4 b3 b2 b1 b0 DMAC channel 0 mode register 2 (DMA0M2 : address 4116) (Note 1) b Name Functions At reset R W 0 0 DMAC channel 0 hardware b3b2b1b0 0 0 0 0 : Not used transfer request source 0 0 0 1 : UART1 receive interrupt bits (D0HR) 0 0 1 0 : UART1 transmit interrupt 0 0 1 1 : Timer Y interrupt 0 1 0 0 : INT0 interrupt 0 1 0 1 : USB endpoint 1 IN_PKT_RDY signal (falling edge active) 0 1 1 0 : USB endpoint 2 IN_PKT_RDY 1 signal (falling edge active) 0 1 1 1 : USB endpoint 3 IN_PKT_RDY signal (falling edge active) 1 0 0 0 : USB endpoint 1 OUT_PKT_RDY signal (rising edge active) 1 0 0 1 : USB endpoint 1 2 OUT_FIFO_NOT_EMPTY signal (rising edge active) 1 0 1 0 : USB endpoint 2 OUT_PKT_RDY signal (rising edge active) 1 0 1 1 : USB endpoint 3 OUT_PKT_RDY signal (rising edge active) 3 1 1 0 0 : Master CPU bus interface OBE0 signal (rising edge active) 1 1 0 1 : Master CPU bus interface IBF0 signal, data (rising edge active) 1 1 1 0 : Serial I/O transmit/receive interrupt 1 1 1 1 : CNTR1 interrupt 4 DMAC channel 0 software 0 : No action 1 : Request of channel 0 transfer by transfer trigger (D0SWT) writing “1” 5 DMAC channel 0 USB and 0 : Disabled master CPU bus interface 1 : Enabled enable bit (D0UMIE) 6 DMAC channel 0 transfer 0 : No action 1 : Reset of channel 0 capture register by initiation source capture writing “1” register reset bit (D0CRR) 0 : Channel 0 disabled 7 DMAC channel 0 enable 1 : Channel 0 enabled (Note 3) bit (D0CEN) 0 0 0 0 (Note 2) 0 0 (Note 2) 0 Notes 1: DMAC channel 0 mode register 2 and DMAC channel 1 mode register 2 are assigned at the same address 4116. The accessible register depends on channel index bit, bit 7 of DMAC index and status register. 2: These bits’ contents are “0” at read. This bit is automatically cleared to “0” after writing “1”. 3: When setting this bit to “1”, simultaneously set the DMAC channel 0 transfer initiation source capture register reset bit (bit 6 of DMA0M2) to “1”. Fig. 3.5.38 Structure of DMAC channel 0 mode register 2 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 71 of 108 APPENDIX 7641 Group 3.5 Control registers DMAC channel 1 mode register 2 b7 b6 b5 b4 b3 b2 b1 b0 DMAC channel 1 mode register 2 (DMA1M2 : address 4116) (Note 1) b Name Functions At reset R W 0 0 DMAC channel 1 hardware b3b2b1b0 0 0 0 0 : Not used transfer request source 0 0 0 1 : UART2 receive interrupt bits (D1HR) 0 0 1 0 : UART2 transmit interrupt 0 0 1 1 : Timer X interrupt 0 1 0 0 : INT1 interrupt 0 1 0 1 : USB endpoint 1 IN_PKT_RDY signal (falling edge active) 0 1 1 0 : USB endpoint 2 IN_PKT_RDY 1 signal (falling edge active) 0 1 1 1 : USB endpoint 4 IN_PKT_RDY signal (falling edge active) 1 0 0 0 : USB endpoint 1 OUT_PKT_RDY signal (rising edge active) 1 0 0 1 : USB endpoint 1 2 OUT_FIFO_NOT_EMPTY signal (rising edge active) 1 0 1 0 : USB endpoint 2 OUT_PKT_RDY signal (rising edge active) 1 0 1 1 : USB endpoint 4 OUT_PKT_RDY signal (rising edge active) 3 1 1 0 0 : Master CPU bus interface OBE1 signal (rising edge active) 1 1 0 1 : Master CPU bus interface IBF1 signal, data (rising edge active) 1 1 1 0 : Timer 1 interrupt 1 1 1 1 : CNTR0 interrupt 4 DMAC channel 1 software 0 : No action 1 : Request of channel 1 transfer by transfer trigger (D1SWT) writing “1” 5 DMAC channel 1 USB and 0 : Disabled master CPU bus interface 1 : Enabled enable bit (D1UMIE) 6 DMAC channel 1 transfer 0 : No action 1 : Reset of channel 1 capture register by initiation source capture writing “1” register reset bit (D1CRR) 0 : Channel 1 disabled 7 DMAC channel 1 enable 1 : Channel 1 enabled (Note 3) bit (D1CEN) 0 0 0 0 (Note 2) 0 0 (Note 2) 0 Notes 1: DMAC channel 0 mode register 2 and DMAC channel 1 mode register 2 are assigned at the same address 4116. The accessible register depends on channel index bit, bit 7 of DMAC index and status register. 2: These bits’ contents are “0” at read. This bit is automatically cleared to “0” after writing “1”. 3: When setting this bit to “1”, simultaneously set the DMAC channel 1 transfer initiation source capture register reset bit (bit 6 of DMA1M2) to “1”. Fig. 3.5.39 Structure of DMAC channel 1 mode register 2 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 72 of 108 APPENDIX 7641 Group 3.5 Control registers DMAC channel x source registers Low, High b7 b6 b5 b4 b3 b2 b1 b0 DMAC channel x source registers Low, High (DMAxSL,DMAxSH : addresses 4216, 4316) b Functions At reset R W 0 qThis is a 16-bit register with a latch. 0 1 0 2 qThis register indicates the source address for data transfer. 0 3 0 4 0 5 0 6 0 7 0 Notes 1: DMAC channel x source registers low, high of channels 0 and 1 are assigned at the same addresses. The accessible register depends on channel index bit, bit 7 of DMAC index and status register. 2: Write data into the lower bytes first, and then the higher bytes. 3: Read the contents from the higher bytes first, and then the lower bytes. Fig. 3.5.40 Structure of DMAC channel x (x = 0, 1) source registers Low, High DMAC channel x destination registers Low, High b7 b6 b5 b4 b3 b2 b1 b0 DMAC channel x destination registers Low, High (DMAxDL,DMAxDH : addresses 4416, 4516) b Functions At reset R W 0 qThis is a 16-bit register with a latch. 0 1 0 2 qThis register indicates the destination address for data transfer. 0 3 0 4 0 5 0 6 0 7 0 Notes 1: DMAC channel x destination registers low, high of channels 0 and 1 are assigned at the same addresses. The accessible register depends on channel index bit, bit 7 of DMAC index and status register. 2: Write data into the lower bytes first, and then the higher bytes. 3: Read the contents from the higher bytes first, and then the lower bytes. Fig. 3.5.41 Structure of DMAC channel x (x = 0, 1) destination registers Low, High Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 73 of 108 APPENDIX 7641 Group 3.5 Control registers DMAC channel x transfer count registers Low, High b7 b6 b5 b4 b3 b2 b1 b0 DMAC channel x transfer count registers Low (DMAxCL : address 4616) b 0 1 2 3 4 5 6 7 b7 b6 b5 b4 b3 b2 b1 b0 Functions qThis is the lower 8-bit register with a latch. Set the lower 8 bits of transfer numbers. qThis register indicates the remaining transfer numbers while transfer is continuing. qThis contents are decreased by 1 at every transfer operation. qWhen this register underflows, the DMAC interrupt request bit and the count register underflow flag (Note 2) are set to “1”. At reset R W 0 0 0 0 0 0 0 0 DMAC channel x transfer count registers High (DMAxCH : address 4716) b Functions At reset R W 0 qThis is the higher 8-bit register with a latch. Set the higher 8 bits of 0 transfer numbers. 1 0 2 qThis register indicates the remaining transfer numbers while 0 transfer is continuing. 3 0 qThis contents are decreased by 1 at every transfer operation. 4 0 5 0 6 0 7 0 Notes 1: DMAC channel x transfer count registers low, high of channels 0 and 1 are assigned at the same addresses 4616 and 4716. The accessible channel depends on channel index bit, bit 7 of DMAC index and status register. 2: Channel 0 used: Bit 0 of DMAC index and status register Channel 1 used: Bit 2 of DMAC index and status register 3: Write data into the lower byte first, and then the higher byte. 4: Read the contents from the higher byte first, and then the lower byte. Fig. 3.5.42 Structure of DMAC channel x (x = 0, 1) transfer count registers Low, High Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 74 of 108 APPENDIX 7641 Group 3.5 Control registers Data bus buffer register x b7 b6 b5 b4 b3 b2 b1 b0 Data bus buffer register x (x = 0, 1) (DBBx: addresses 4816, 4C16) b Functions At reset R W 0 0 0 0 0 0 0 0 0 qA data is latched into this register by a write request from the host CPU. 1 2 3 qWrite an output data into this register. The data is output on to the data bus by a read request from the 4 host CPU. 5 6 7 Fig. 3.5.43 Structure of Data bus buffer register x (x = 0, 1) Data bus buffer status register x b7 b6 b5 b4 b3 b2 b1 b0 Data bus buffer status register x (x = 0, 1) (DBBSx: addresses 4916, 4D16) b Name Functions 0 : Buffer empty 1 : Buffer full 0 : Buffer empty 1 : Buffer full This flag can be defined by user freely. This flag indicates the condition of A0 status when the IBFx flag is set. This flag can be defined by user freely. At reset R W 0 0 0 0 ✕ ✕ ✕ 0 Output buffer full flag (OBFx) 1 Input buffer full flag (IBFx) 2 User definable flag (U2) 3 A0 flag (A0x) 4 User definable flag 5 (U4 to U7) 6 6 7 0 Fig. 3.5.44 Structure of Data bus buffer status register x (x = 0, 1) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 75 of 108 APPENDIX 7641 Group 3.5 Control registers Data bus buffer control register 0 b7 b6 b5 b4 b3 b2 b1 b0 0 Data bus buffer control register 0 (DBBC0 : address 4A16) b Name Functions At reset R W 0 0 0 0 OBF0 output enable bit 1 2 3 4 5 6 7 0 : P52 functions as I/O port. 1 : P52 functions as OBF0 output pin. 0 : P53 functions as I/O port. IBF0 output enable bit 1 : P53 functions as IBF0 0 : Occurrence due to data write (A0 = “0”) or IBF0 interrupt select bit command write (A0 = “1”) 1 : Occurrence due to command write (A0 = “1”) Output buffer 0 empty 0 : Enabled interrupt disable bit 1 : Disabled Input buffer 0 full interrupt 0 : Enabled disable bit 1 : Disabled Nothing arranged for this bit. Fix this bit to “0”. Master CPU bus interface Function of P54 to P57, P60 to P67 ; 0 : As I/O ports. enable bit 1 : As master CPU bus interface function pins. Bus interface type select 0 : RD,WR separate type bus bit 1 : R/W type bus 0 0 0 0 0 Fig. 3.5.45 Structure of Data bus buffer control register 0 Data bus buffer control register 1 b7 b6 b5 b4 b3 b2 b1 b0 00 Data bus buffer control register 1 (DBBC0 : address 4E16) b Name Functions 0 : P74 functions as I/O port. 1 : P74 functions as OBF1 output pin. (Note) 0 : P73 functions as I/O port. 1 : P73 functions as IBF1 output pin. (Note) 0 : Occurrence due to data write (A0 = “0”) or command write (A0 = “1”) 1 : Occurrence due to command write (A0 = “1”) At reset R W 0 0 OBF1 output enable bit 1 IBF1 output enable bit 0 2 IBF1 interrupt select bit 0 3 Output buffer 1 empty 0 : Enabled interrupt disable bit 1 : Disabled Input buffer 1 full interrupt 0 : Enabled 4 disable bit 1 : Disabled 5 Nothing arranged for these bits. 6 Fix these bits to “0”. 0 : Single data bus buffer mode(P72 7 Data bus buffer function functions as I/O port.) select bit 1 : Double data bus buffer mode(P72 functions as S1 input pin.) Note: This can be selected when the data bus buffer function select bit is “1”. 0 0 0 0 0 Fig. 3.5.46 Structure of Data bus buffer control register 1 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 76 of 108 APPENDIX 7641 Group 3.5 Control registers USB address register b7 b6 b5 b4 b3 b2 b1 b0 0 USB address register (USBA : address 5016) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 This register maintains the 7-bit USB function control unit address assigned by the host CPU. 1 2 3 4 5 6 7 Nothing arranged for this bit. Fix this bit to “0”. Fig. 3.5.47 Structure of USB address register USB power management register b7 b6 b5 b4 b3 b2 b1 b0 00000 USB power management register (USBPM : address 5116) b Name Functions 0 : No USB suspend detected 1 : USB suspend detected (Note 1) 0 : No USB resume signal detected 1 : USB resume signal detected 0 : End of remote resume signal 1 : Transmitting of remote resume signal (only when SUSPEND = “1”) (Note 2) At reset R W 0 0 0 ✕ ✕ 0 USB suspend detection flag (SUSPEND) 1 USB resume detection flag (RESUME) 2 USB remote wake-up bit (WAKEUP) 3 Nothing arranged for this bit. Fix these bits to “0”. 4 5 6 7 0 0 0 0 0 Notes 1: This bit is cleared when the WAKEUP bit is “1”. 2: When the SUSPEND bit is “1”, set this bit to “1” and keep “1” for 10 ms to 15 ms. Fig. 3.5.48 Structure of USB power management register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 77 of 108 APPENDIX 7641 Group 3.5 Control registers USB interrupt status register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 USB interrupt status register 1 (USBIS1 : address 5216) b Name Functions 0 : Except the following conditions 1 : Set at any one of the following conditions: • A packet data of endpoint 0 is successfully received • A packet data of endpoint 0 is successfully sent • DATA_END bit of endpoint 0 is cleared to “0” • FORCE_STALL bit of endpoint 0 is set to “1” • SETUP_END bit of endpoint 0 is set to “1”. At reset R W 0 ✽ 0 USB endpoint 0 interrupt status flag (INTST0) 1 Nothing arranged for this bit. Fix this bit to “0”. 2 USB endpoint 1 IN 0 : Except the following conditions interrupt status flag 1 : Set at which of the following (INTST2) conditions: • A packet data of endpoint 1 is successfully sent • UNDER_RUN bit of endpoint 1 is set to “1”. 0 : Except the following conditions 3 USB endpoint 1 OUT 1 : Set at any one of the following interrupt status flag conditions: (INTST3) • A packet data of endpoint 1 is successfully received • OVER_RUN bit of endpoint 1 is set to “1” • FORCE_STALL bit of endpoint 1 is set to “1”. 0 : Except the following conditions 4 USB endpoint 2 IN interrupt status flag 1 : Set at which of the following (INTST4) conditions: • A packet data of endpoint 2 is successfully sent • UNDER_RUN bit of endpoint 2 is set to “1”. 0 : Except the following conditions 5 USB endpoint 2 OUT 1 : Set at any one of the following interrupt status flag conditions: (INTST5) • A packet data of endpoint 2 is successfully received • OVER_RUN bit of endpoint 2 is set to “1” • FORCE_STALL bit of endpoint 2 is set to “1”. 0 : Except the following conditions 6 USB endpoint 3 IN interrupt status flag 1 : Set at which of the following (INTST6) conditions: • A packet data of endpoint 3 is successfully sent • UNDER_RUN bit of endpoint 3 is set to “1”. 0 : Except the following conditions 7 USB endpoint 3 OUT 1 : Set at any one of the following interrupt status flag conditions: (INTST7) • A packet data of endpoint 3 is successfully received • OVER_RUN bit of endpoint 3 is set to “1” • FORCE_STALL bit of endpoint 3 is set to “1”. ✽: “0” can be set by software, but “1” cannot be set. To clear the bit set to “1”, write “1” to the bit. 0 0 ✽ 0 ✽ 0 ✽ 0 0 ✽ 0 ✽ 0 0 ✽ Fig. 3.5.49 Structure of USB interrupt status register 1 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 78 of 108 APPENDIX 7641 Group 3.5 Control registers USB interrupt status register 2 b7 b6 b5 b4 b3 b2 b1 b0 00 USB interrupt status register 2 (USBIS2 : address 5316) b Name Functions At reset R W 0 ✽ 0 : Except the following conditions 1 : Set at which of the following conditions: • A packet data of endpoint 4 is successfully sent • UNDER_RUN bit of endpoint 4 is set to “1”. 0 : Except the following conditions 1 USB endpoint 4 OUT 1 : Set at any one of the following interrupt status flag conditions: (INTST9) • A packet data of endpoint 4 is successfully received • OVER_RUN bit of endpoint 4 is set to “1” • FORCE_STALL bit of endpoint 4 is set to “1”. 2 Nothing arranged for these bits. Fix these bist to “0”. 3 0 : Except the following conditions 4 USB overrun/underrun 1 : Set at an occurrence of overrun / interrupt status flag underrun (for isochronous data (INTST12) transfer) 5 USB reset interrupt status flag (INTST13) 6 USB resume signal interrupt status flag (INTST14) 7 USB suspend signal interrupt status flag (INTST15) 0 : Except the following conditions 1 : Set at receiving of USB reset signal 0 : Except the following conditions 1 : Set at receiving of resume signal 0 : Except the following conditions 1 : Set at receiving of suspend signal 0 USB endpoint 4 IN interrupt status flag (INTST8) 0 ✽ 0 0 0 ✽ 0 0 ✽ ✽ 0 ✽ ✽: “0” can be set by software, but “1” cannot be set. To clear the bit set to “1”, write “1” to the bit. Fig. 3.5.50 Structure of USB interrupt status register 2 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 79 of 108 APPENDIX 7641 Group 3.5 Control registers USB interrupt enable register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 USB interrupt enable register 1 (USBIE1 : address 5416) b Name Functions At reset R W 1 1 1 1 1 1 1 1 0 USB endpoint 0 interrupt enable bit (INTEN0) 1 2 3 4 5 6 7 0 : Disabled 1 : Enabled Nothing arranged for this bit. Fix this bit to “0”. USB endpoint 1 IN interrupt 0 : Disabled 1 : Enabled enable bit (INTEN2) USB endpoint 1 OUT inter- 0 : Disabled 1 : Enabled rupt enable bit (INTEN3) USB endpoint 2 IN interrupt 0 : Disabled 1 : Enabled enable bit (INTEN4) USB endpoint 2 OUT inter- 0 : Disabled 1 : Enabled rupt enable bit (INTEN5) USB endpoint 3 IN interrupt 0 : Disabled 1 : Enabled enable bit (INTEN6) USB endpoint 3 OUT inter- 0 : Disabled 1 : Enabled rupt enable bit (INTEN7) Fig. 3.5.51 Structure of USB interrupt enable register 1 USB interrupt enable register 2 b7 b6 b5 b4 b3 b2 b1 b0 01 00 USB interrupt enable register 2 (USBIE2 : address 5516) b Name Functions At reset R W 1 1 0 0 1 1 0 0 0 USB endpoint 4 IN interrupt 0 : Disabled enable bit (INTEN8) 1 : Enabled 1 USB endpoint 4 OUT inter- 0 : Disabled 1 : Enabled rupt enable bit (INTEN9) 2 Nothing arranged for these bits. Fix these bits to “0”. 3 0 : Disabled 4 USB overrun/underrun interrupt enable bit (INTEN12) 1 : Enabled 5 Nothing arranged for this bit. Fix this bit to “1”. 6 Nothing arranged for this bit. Fix this bit to “0”. 0 : Disabled 7 USB suspend/resume interrupt enable bit (INTEN15) 1 : Enabled Fig. 3.5.52 Structure of USB interrupt enable register 2 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 80 of 108 APPENDIX 7641 Group 3.5 Control registers USB frame number register Low b7 b6 b5 b4 b3 b2 b1 b0 USB frame number register Low (USBSOFL : address 5616) b 0 FN0 1 FN1 2 FN2 3 FN3 4 FN4 5 FN5 6 FN6 7 FN7 Name Functions Contains the low-order 8 bits of SOF token frame number. At reset R W 0 0 0 0 0 0 0 0 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ USB frame number register High b7 b6 b5 b4 b3 b2 b1 b0 USB frame number register High (USBSOFH : address 5716) b 0 FN8 1 FN9 2 FN10 Name Functions Contains the high-order 3 bits of SOF token frame number. At reset R W 0 0 0 0 0 0 0 0 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ 3 Nothing is arranged for these bits. These are write disable bits. When these bits are read out, the contents are “0”. 4 5 6 7 Fig. 3.5.53 Structure of USB frame nmber registers Low, High Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 81 of 108 APPENDIX 7641 Group 3.5 Control registers USB endpoint index register b7 b6 b5 b4 b3 b2 b1 b0 000 USB endpoint index register (USBINDEX : address 5816) b Name b2b1b0 Functions 0 0 0 : Endpoint 0 0 0 1 : Endpoint 1 0 1 0 : Endpoint 2 0 1 1 : Endpoint 3 1 0 0 : Endpoint 4 1 0 1 : Not used 1 1 0 : Not used 1 1 1 : Not used At reset R W 0 0 Endpoint index bit (EPINDEX) 1 2 0 0 0 0 0 0 0 3 Nothing arranged for these bits. Fix these bist to 4 5 0 : Auto FIFO flush disabled 6 AUTO_FLUSH bit 1 : Auto FIFO flush enabled (AUTO_FL) (Note) 0 : ISO_UPDATE disabled ISO_UPDATE bit 7 1 : ISO_UPDATE enabled (ISO_UPD) (Note) Note: This bit is valid for an isochronous transfer. Fig. 3.5.54 Structure of USB endpoint index register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 82 of 108 APPENDIX 7641 Group 3.5 Control registers USB endpoint 0 IN control register b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint 0 IN control register (IN_CSR : address 5916) b Name Functions 0 : Except the following condition (Cleared to “0” by writing “1” into SERVICED_OUT_PKT_RDY bit) 1 : End of a data packet reception 0 : End of a data packet transmission 1 : Write “1” at completion of writing a data packet into IN FIFO. 0 : Except the following condition 1 : Transmitting STALL handshake signal At reset R W 0 0 OUT_PKT_RDY flag (IN0CSR0) ✽2 1 IN_PKT_RDY bit (IN0CSR1) ✽1 0 2 SEND_STALL bit (IN0CSR2) ✽3, ✽4 3 DATA_END bit (IN0CSR3) 0 : Except the following condition ✽1 (Cleared to “0” after completion of status phase) 1 : Write “1” at completion of writing or reading the last data packet to/from FIFO. 0 : Except the following condition 4 FORCE_STALL flag (IN0CSR4) ✽2, ✽3 1 : Protocol error detected 0 : Except the following condition 5 SETUP_END flag (Cleared to “0” by writing “1” into (IN0CSR5) (Note 1) ✽2 SERVICED_SETUP_END bit) 1 : Control transfer ends before the specific length of data is transferred during the data phase. 6 SERVICED_OUT_PKT_R 0 : Except the following condition DY bit (IN0CSR6) 1 : Writing “1” to this bit clears OUT_ PKT_RDY flag to “0”. 7 SERVICED_SETUP_END 0 : Except the following condition bit (IN0CSR7) 1 : Writing “1” to this bit clears SETUP_ END flag to “0”. 0 0 0 0 0 0 USB endpoint 1, 2, 3, 4 IN control register b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint 1, 2, 3, 4 IN control register (IN_CSR : address 5916) b Name Functions 0 : End of a data packet transmission 1 : Write “1” at completion of writing a data packet into IN FIFO. (Note 2) At reset R W 0 0 INT_PKT_RDY bit (INXCSR0) ✽1 1 UNDER_RUN flag 0 : No FIFO underrun (INXCSR1) (In isochronous 1 : FIFO underrun occurred data transfer) ✽2, ✽3 (USB overrun/underrun interrupt status flag is set to “1”.) 2 SEND_STALL bit (INXCSR2) ✽3, ✽4 3 ISO/TOGGLE_INIT bit (INXCSR3) ✽3, ✽4 0 : Except the following condition 1 : Transmitting STALL handshake signal 0 : Except the following condition 1 : Initializing to endpoint used for isochronous transfer; Initializing the data toggle sequence bit 0 : Except the following condition 1 : Initializing to endpoint used for interrupt transfer, rate feedback 0 : Empty in IN FIFO 1 : Full in IN FIFO 0 : Except the following condition 1 : Flush FIFO 0 : AUTO_SET disabled 1 : AUTO_SET enabled (Note 3) 0 0 0 4 INTPT bit (INXCSR4) 0 5 TX_NOT_EPT flag (INXCSR5) ✽1, ✽2 6 FLUSH bit (INXCSR6) ✽1, ✽4 7 AUTO_SET bit (INXCSR7) ✽3, ✽4 0 0 0 ✕ ✽ 1: This bit is automatically cleared to “0”. ✽ 2: This bit is automatically set to “1”. ✽ 3: The user must program to “0”. ✽ 4: The user must program to “1”. Notes 1: If this bit is set to “1”, stop accessing the FIFO to serve the previous setup transaction. 2: When AUTO_SET bit is “0”, the user must set to “1”. When AUTO_SET bit is “1”, this bit is automatically set to “1”. Additionally, when writing to other bits of this register, write “0” to this bit. 3: To use the AUTO_SET function for an IN transfer when the AUTO_SET bit is set to “1”, set the FIFO to single buffer mode. Fig. 3.5.55 Structure of USB endpoint x (x = 0 to 4) IN control register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 83 of 108 APPENDIX 7641 Group 3.5 Control registers USB endpoint x OUT control register b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint x OUT control register (OUT_CSR : address 5A16) b Name Functions 0 : Except the following condition (Note) 1 : End of a data packet reception 0 : No FIFO overrun 1 : FIFO overrun occurred At reset R W 0 0 0 OUT_PKT_RDY flag (OUTXCSR0) ✽4 1 OVER RUN flag (OUTXCSR1) (In isochronous data transfer) ✽2, ✽3 2 SEND_STALL bit (OUTXCSR2) ✽3, ✽4 3 ISO/TOGGLE_INIT bit (OUTXCSR3) ✽3, ✽4 0 : Except the following condition 1 : Transmitting STALL handshake signal 0 : Except the following condition 1 : Initializing to endpoint used for isochronous transfer; Enabling reception of DATA0 and DATA1 as PID (Initializing the toggle) 0 : Except the following condition 1 : Protocol error detected 0 : Except the following condition 1 : CRC or bit stuffing error detected in transferring isochronous data 0 0 4 FORCE_STALL flag (OUTXCSR4) ✽2, ✽3 5 DATA_ERR flag (OUTXCSR5) ✽2, ✽3 0 0 0 0 : Except the following condition 6 FLUSH bit (OUTXCSR6) ✽1, ✽4 1 : Flush FIFO 7 AUTO_SET bit 0 : AUTO_SET disabled 0 (OUTXCSR7) ✽3, ✽4 1 : AUTO_SET enabled ✽ 1: This bit is automatically cleared to “0”. ✽ 2: This bit is automatically set to “1”. ✽ 3: The user must program to “0”. ✽ 4: The user must program to “1”. Note : When AUTO_CLR bit is “0”, the user must set to “0”. When AUTO_CLR bit is “1”, this bit is automatically set to “0”. Fig. 3.5.56 Structure of USB endpoint x (x = 1 to 4) OUT control register USB endpoint x IN max. packet size register b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint x IN max. packet size register (IN_MAXP: address 5B16) b Functions At reset R W (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) 0 The maximum packet size (MAXP) of endpoint x IN is contained. 1 qMAXP = n for endpoints 0, 2, 3, 4 2 qMAXP = n ✕ 8 for endpoint 1 “n” is a written value into this register. 3 4 5 6 7 Note: The value is “0816” in the endpoint 1 used. The value is “0116” in the endpoint 0, 2, 3 or 4 used. Fig. 3.5.57 Structure of USB endpoint x (x = 0 to 4) IN max. packet size register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 84 of 108 APPENDIX 7641 Group 3.5 Control registers USB endpoint x OUT max. packet size register b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint x OUT max. packet size register (OUT_MAXP: address 5C16) b Functions At reset R W (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) 0 The maximum packet size (MAXP) of endpoint x OUT is contained. 1 qMAXP = n for endpoints 0, 2, 3, 4 2 qMAXP = n ✕ 8 for endpoint 1 “n” is a written value into this register. 3 4 5 6 7 Note: The value is “0816” in the endpoint 0, 2, 3 or 4 used. The value is “0116” in the endpoint 1 used. Fig. 3.5.58 Structure of USB endpoint x (x = 0 to 4) OUT max. packet size register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 85 of 108 APPENDIX 7641 Group 3.5 Control registers USB endpoint x OUT write count register Low b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint x OUT write count register Low (WRT_CNTL : address 5D16) b Name Functions At reset R W 0 0 0 0 0 0 0 0 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ 0 Contains the low-order 8 bits of the number of bytes in endpoint x OUT FIFO. 1 2 3 4 5 6 7 USB endpoint x OUT write count register High b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint x OUT write count register High (WRT_CNTH : address 5E16) b Name Functions At reset R W 0 0 0 0 0 0 0 0 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ 0 Contains the high-order 2 bits of the number of bytes in endpoint x OUT FIFO. 1 2 Nothing is arranged for these bits. These are write disable bits. When these bits are read out, the contents are “0”. 3 4 5 6 7 Fig. 3.5.59 Structure of USB endpoint x (x = 0 to 4) OUT write count registers Low, High Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 86 of 108 APPENDIX 7641 Group 3.5 Control registers USB endpoint FIFO mode register b7 b6 b5 b4 b3 b2 b1 b0 0000 USB endpoint FIFO mode register (USBFIFOMR : address 5F16) b Name For endpoint 1 b4b2b1b0 Functions ✕ 0 0 0 : IN 512-byte, OUT 800-byte ✕ 0 0 1 : IN 1024-byte, OUT 1024-byte ✕ 0 1 0 : IN 0-byte, OUT 2048-byte ✕ 0 1 1 : IN 2048-byte, OUT 0-byte ✕ 1 0 0 : IN 768-byte, OUT 1280-byte ✕ 1 0 1 : IN 880-byte, OUT 1168-byte For endpoint 2 At reset R W 0 0 FIFO size selection bit (Note) 1 0 2 0 3 b4b2b1b0 0 ✕ ✕ ✕ : IN 32-byte, OUT 32-byte 1 ✕ ✕ ✕ : IN 128-byte, OUT 128-byte 0 4 Nothing arranged for these bits. Fix these bits to “0”. 5 6 7 Note: The value set into “x” is invalid. 0 0 0 0 Fig. 3.5.60 Structure of USB endpoint FIFO mode register USB endpoint x FIFO register b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint x FIFO register (USBFIFOx: addresses 6016, 6116, 6216, 6316, 6416) b Functions At reset R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 qThis is Endpoint x IN/OUT FIFO. 1 qWrite a data to be transmitted into this IN FIFO. 2 qRead a received data from this OUT FIFO. 3 4 5 6 7 Fig. 3.5.61 Structure of USB endpoint x (x = 0 to 4) FIFO register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 87 of 108 APPENDIX 7641 Group 3.5 Control registers Flash memory control register b7 b6 b5 b4 b3 b2 b1 b0 Flash memory control register (FMCR : address 6A16) b Name Functions 0 : Busy (being programmed or erased) 1 : Ready 0 : Normal mode (Software commands invalid) 1 : CPU rewrite mode (Software commands acceptable) 0 : Normal mode 1 : CPU rewrite mode At reset R W 1 0 0 RY/BY status flag (FLCA0) 1 CPU rewrite mode select bit (FLCA1) (Note 2) 2 CPU rewrite mode entry flag (FLCA2) 0 ✕ 0 : Normal operation 3 Flash memory reset bit (FLCA3) (Note 3) 1 : Reset 0 : Interrupt disabled 4 User ROM area / Boot ROM area select bit 1 : Interrupt enabled (FLCA4) (Note 4) 5 Indefinite at read. Write “0” at write. 5 6 5 7 0 0 0 0 0 Notes 1: The contents of flash memory control register are “XXX00001” just after reset release. In the mask ROM version this area is reserved, so that do not write any data to this address. 2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. If it is not this procedure, this bit will not be set to ”1”. Additionally, it is required to ensure that no interrupt will be generated during that interval. Use the control program in the area except the built-in flash memory for write to this bit. 3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently after setting bit 3 to “1”. 4: Use the control program in the area except the built-in flash memory for write to this bit. Fig. 3.5.62 Structure of Flash memory control register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 88 of 108 APPENDIX 7641 Group 3.5 Control registers Frequency synthesizer control register b7 b6 b5 b4 b3 b2 b1 b0 0 00 Frequency synthesizer control register (FSC : address 6C16) b Name 0 : Disabled 1 : Enabled Functions At reset R W 0 0 0 0 0 0 Frequency synthesizer enable bit (FSE) 1 Fix these bits to “0”. 2 3 Frequency synthesizer input bit (FIN) 4 Fix this bit to “0”. 5 LPF current control bit (CHG1, CHG0) (Note) 6 7 Frequency synthesizer lock status bit 0 : f(XIN) 1 : f(XCIN) b1b0 0 0 : Not available 0 1 : Low current 1 0 : Intermediate current (recommended) 1 1 : High current 0 : Unlocked 1 : Locked 1 1 0 Note: Bits 6 and 5 are set to (bit 6, bit 5) = (1, 1) at reset. When using the frequency synthesizer, we recommend to set to (bit 6, bit 5) = (1, 0) after locking the frequency synthesizer. Fig. 3.5.63 Structure of Frequency synthesizer control register Frequency synthesizer multiply register 1 b7 b6 b5 b4 b3 b2 b1 b0 Frequency synthesizer multiply register 1 (FSM1: address 6D16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qfVCO clock is generated by multiplying fPIN clock, which is generated by FSM2, by the contents of this register: 1 2 fVCO = fPIN • {2(n +1)}, n: value set to FSM1. 3 4 5 6 7 Fig. 3.5.64 Structure of Frequency synthesizer multiply register 1 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 89 of 108 APPENDIX 7641 Group 3.5 Control registers Frequency synthesizer multiply register 2 b7 b6 b5 b4 b3 b2 b1 b0 Frequency synthesizer multiply register 2 (FSM2: address 6E16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qfPIN clock is generated by dividing fIN clock by the contents of this register. 1 Either f(XIN) or f(XCIN) as an input clock fIN for the frequency 2 synthesizer is selectable. 3 4 fPIN = fIN / {2(n +1)}, n: value set to FSM2 5 6 7 Fig. 3.5.65 Structure of Frequency synthesizer multiply register 2 Frequency synthesizer divide register b7 b6 b5 b4 b3 b2 b1 b0 Frequency synthesizer divide register (FSD: address 6F16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qfSYN clock is generated by dividing fVCO clock by the contents of this register: 1 2 fSYN = fVCO / {2(m +1)}, m: value set to FSD 3 4 5 6 7 Fig. 3.5.66 Structure of Frequency synthesizer divide register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 90 of 108 APPENDIX 7641 Group 3.5 Control registers ROM code protect control register b7 b6 b5 b4 b3 b2 b1 b0 11 ROM code protect control register (ROMCP : address FFC916) (Note 1) b Name Functions At reset R W 1 1 1 1 1 1 1 1 0 Fix these bits to “1”. 1 2 ROM code protect level 2 set bits (ROMCP2) (Notes 2, 3) 3 4 ROM code protect reset bits (ROMCR) (Note 4) 5 6 ROM code protect level 1 set bits (ROMCP1) (Note 2) 7 b3b2 0 0 : Protect enabled 0 1 : Protect enabled 1 0 : Protect enabled 1 1 : Protect disabled b5b4 0 0 : Protect removed 0 1 : Protect set bits effective 1 0 : Protect set bits effective 1 1 : Protect set bits effective b7b6 0 0 : Protect enabled 0 1 : Protect enabled 1 0 : Protect enabled 1 1 : Protect disabled Notes 1: This area is on the ROM in the mask ROM version. 2: When ROM code protect is turned on, the internal flash memory is protected against readout or modification in parallel I/O mode. 3: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc. also is inhibited. 4: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, since these bits cannot be modified in parallel I/O mode, they need to be rewritten in standard serial I/O mode or CPU rewrite mode. Fig. 3.5.67 Structure of ROM code protect control register Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 91 of 108 APPENDIX 7641 Group 3.6 Package outline 3.6 Package outline PRQP0080GB-A JEITA Package Code P-QFP80-14x20-0.80 RENESAS Code PRQP0080GB-A Previous Code 80P6N-A MASS[Typ.] 1.6g HD *1 D 41 64 65 NOTE) 1. HE E * *2" ZE *2 * INCLUDE TRIM OFFSET. 80 25 Dimension in Millimeters Symbol 1 ZD 24 Index mark F c D E A2 D HE A A1 bp c L Detail F Min Nom 19.8 13.8 14.0 2.8 22.5 22.8 16.5 16.8 0.1 0 0.3 0.35 0.13 0.15 0° 0.65 0.8 0.8 1.0 0.6 Max 14.2 23.1 17.1 3.05 0.2 0.2 10 ° 0.10 A *3 A1 e y bp A2 y ZD ZE L 0.4 0.8 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 92 of 108 APPENDIX 7641 Group 3.6 Package outline PLQP0080KB-A JEITA Package Code P-LQFP80-12x12-0.50 RENESAS Code PLQP0080KB-A Previous Code 80P6Q-A MASS[Typ.] 0.5g HD *1 D 41 NOTE) 1. DIMENSIONS "*1" AND "*2" 0 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 1 *2 HE E c1 Reference Dimension in Millimeters Symbol Terminal cross section D E A HD E 20 F A1 p b1 c c1 e x y ZD ZE L L1 L L1 Detail F Min Nom Max 11.9 12.0 12.1 11.9 12.0 12.1 1.4 13.8 14.0 14.2 13.8 14.0 14.2 1.7 0.1 0.2 0 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0° 10 ° 0.5 0.08 0.08 1.25 1.25 0.3 0.5 0.7 1.0 ZE A2 A Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 93 of 108 A1 c APPENDIX 7641 Group 3.7 Machine instructions 7641 Group APPENDIX 3.7 Machine instructions 3.7 Machine instructions Addressing mode Symbol Function Details IMP OP n ADC (Note 1) (Note 7) When T = 0 A←A+M+C When T = 1 M(X) ← M(X) + M + C When T = 0, this instruction adds the contents M, C, and A; and stores the results in A and C. When T = 1, this instruction adds the contents of M(X), M and C; and stores the results in M(X) and C. When T=1, the contents of A remain unchanged, but the contents of status flags are changed. M(X) represents the contents of memory where is indicated by X. When T = 0, this instruction transfers the contents of A and M to the ALU which performs a bit-wise AND operation and stores the result back in A. When T = 1, this instruction transfers the contents M(X) and M to the ALU which performs a bit-wise AND operation and stores the results back in M(X). When T = 1, the contents of A remain unchanged, but status flags are changed. M(X) represents the contents of memory where is indicated by X. This instruction shifts the content of A or M by one bit to the left, with bit 0 always being set to 0 and bit 7 of A or M always being contained in C. This instruction tests the designated bit i of M or A and takes a branch if the bit is 0. The branch address is specified by a relative address. If the bit is 1, next instruction is executed. This instruction tests the designated bit i of the M or A and takes a branch if the bit is 1. The branch address is specified by a relative address. If the bit is 0, next instruction is executed. This instruction takes a branch to the appointed address if C is 0. The branch address is specified by a relative address. If C is 1, the next instruction is executed. This instruction takes a branch to the appointed address if C is 1. The branch address is specified by a relative address. If C is 0, the next instruction is executed. This instruction takes a branch to the appointed address when Z is 1. The branch address is specified by a relative address. If Z is 0, the next instruction is executed. This instruction takes a bit-wise logical AND of A and M contents; however, the contents of A and M are not modified. The contents of N, V, Z are changed, but the contents of A, M remain unchanged. This instruction takes a branch to the appointed address when N is 1. The branch address is specified by a relative address. If N is 0, the next instruction is executed. This instruction takes a branch to the appointed address if Z is 0. The branch address is specified by a relative address. If Z is 1, the next instruction is executed. 24 3 2 2C 4 3 IMM # OP n 69 2 A # OP n 2 BIT, A, R BIT, A # OP n ZP BIT, ZP, R BIT, ZP # OP n 2 # ZP, X OP n 75 4 ZP, Y # OP n 2 ABS # OP n 6D 4 ABS, X # OP n 3 7D 5 Addressing mode ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 N N Processor status register 6 V V 5 T • 4 B • 3 D • 2 I • 1 Z Z 0 C C # OP n 65 3 # OP n 3 79 5 # OP n 3 # OP n 61 6 # OP n 2 71 6 # OP n 2 ASL C← 7 0 ←0 BBC Ai or Mi = 0? BBS Ai or Mi = 1? BCC (Note 5) (Note 9) BCS (Note 5) (Note 9) BEQ (Note 5) (Note 8) C = 0? C = 1? Z = 1? BIT A M BMI (Note 5) (Note 8) BNE (Note 5) (Note 8) N = 1? Z = 0? Rev.2.00 Aug 28, 2006 REJ09B0336-0200 V When T = 1 M(X) ← M(X) V AND (Note 1) When T = 0 A←A M M 29 2 2 25 3 2 35 4 2 2D 4 3 3D 5 3 39 5 3 21 6 2 31 6 2 N • • • • • Z • 0A 1 1 06 5 2 16 6 2 0E 6 3 1E 7 3 N • • • • • Z C 13 4 2 + 20i (Note 4) 17 5 3 + 20i (Note 6) • • • • • • • • 03 4 2 + 20i (Note 4) 07 5 3 + 20i (Note 6) • • • • • • • • 90 2 2 • • • • • • • • B0 2 2 • • • • • • • • F0 2 2 • • • • • • • • V M7 M6 • • • • Z • 30 2 2 • • • • • • • • D0 2 2 • • • • • • • • page 94 of 108 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 95 of 108 APPENDIX 7641 Group 3.7 Machine instructions 7641 Group APPENDIX 3.7 Machine instructions Addressing mode Symbol Function Details IMP OP n BPL (Note 5) (Note 8) N = 0? This instruction takes a branch to the appointed address if N is 0. The branch address is specified by a relative address. If N is 1, the next instruction is executed. This instruction branches to the appointed address. The branch address is specified by a relative address. When the BRK instruction is executed, the CPU pushes the current PC contents onto the stack. The BADRS designated in the interrupt vector table is stored into the PC. 00 7 1 IMM # OP n A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n # ZP, X OP n ZP, Y # OP n ABS # OP n ABS, X # OP n Addressing mode ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n 2 # 7 Processor status register 6 V • 5 T • 4 B • 3 D • 2 I • 1 Z • 0 C • # OP n # OP n # OP n # OP n # OP n 10 2 N • BRA (Note 6) BRK PC ← PC ± offset 80 3 2 • • • • • • • • B←1 (PC) ← (PC) + 2 M(S) ← PCH S←S–1 M(S) ← PCL S←S–1 M(S) ← PS S←S–1 I← 1 PCL ← ADL PCH ← AD H V = 0? • • • 1 • 1 • • BVC (Note 5) This instruction takes a branch to the appointed address if V is 0. The branch address is specified by a relative address. If V is 1, the next instruction is executed. This instruction takes a branch to the appointed address when V is 1. The branch address is specified by a relative address. When V is 0, the next instruction is executed. This instruction clears the designated bit i of A or M. This instruction clears C. 18 1 1 1B + 20i 1 1 1F + 20i 5 2 50 2 2 • • • • • • • • BVS (Note 5) V = 1? 70 2 2 • • • • • • • • CLB CLC Ai or Mi ← 0 C←0 D←0 I←0 T←0 V←0 When T = 0 A–M When T = 1 M(X) – M • • • • • • • • • • • • • • • 0 CLD CLI CLT CLV CMP (Note 3) This instruction clears D. This instruction clears I. This instruction clears T. This instruction clears V. When T = 0, this instruction subtracts the contents of M from the contents of A. The result is not stored and the contents of A or M are not modified. When T = 1, the CMP subtracts the contents of M from the contents of M(X). The result is not stored and the contents of X, M, and A are not modified. M(X) represents the contents of memory where is indicated by X. This instruction takes the one’s complement of the contents of M and stores the result in M. This instruction subtracts the contents of M from the contents of X. The result is not stored and the contents of X and M are not modified. This instruction subtracts the contents of M from the contents of Y. The result is not stored and the contents of Y and M are not modified. This instruction subtracts 1 from the contents of A or M. D8 1 58 2 12 1 B8 1 1 1 1 1 C9 2 2 C5 3 2 • • • • D5 4 2 CD 4 3 DD 5 3 D9 5 3 C1 6 2 D1 6 2 N • • • 0 • • • 0 • • • • • • • 0 • • • • • 0 • • • • • • • Z • • • • C COM CPX M←M X–M __ 44 5 E0 2 2 E4 3 2 2 N EC 4 3 N • • • • • • • • • • Z Z • C CPY Y–M C0 2 2 C4 3 2 CC 4 3 N • • • • • Z C DEC A ← A – 1 or M←M–1 1A 1 1 C6 5 2 D6 6 2 CE 6 3 DE 7 3 N • • • • • Z • Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 96 of 108 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 97 of 108 APPENDIX 7641 Group 3.7 Machine instructions 7641 Group APPENDIX 3.7 Machine instructions Addressing mode Symbol Function Details IMP OP n DEX DEY X←X–1 Y←Y–1 A ← (M(zz + X + 1), M(zz + X )) / A M(S) ← one's complement of Remainder S←S–1 When T = 0 – A ←A VM When T = 1 – M(X) ← M(X) V M This instruction subtracts one from the current CA 1 contents of X. This instruction subtracts one from the current contents of Y. This instruction divides the 16-bit data in M(zz+(X)) (low-order byte) and M(zz+(X)+1) (high-order byte) by the contents of A. The quotient is stored in A and the one's complement of the remainder is pushed onto the stack. When T = 0, this instruction transfers the contents of the M and A to the ALU which performs a bit-wise Exclusive OR, and stores the result in A. When T = 1, the contents of M(X) and M are transferred to the ALU, which performs a bitwise Exclusive OR and stores the results in M(X). The contents of A remain unchanged, but status flags are changed. M(X) represents the contents of memory where is indicated by X. This instruction adds one to the contents of A or M. This instruction adds one to the contents of X. This instruction adds one to the contents of Y. This instruction jumps to the address designated by the following three addressing modes: Absolute Indirect Absolute Zero Page Indirect Absolute E8 1 C8 1 1 1 4C 3 3 49 2 2 45 3 2 88 1 IMM # OP n 1 1 A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n # ZP, X OP n ZP, Y # OP n ABS # OP n ABS, X # OP n Addressing mode ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 Processor status register 6 V • • 5 T • • • 4 B • • • 3 D • • • 2 I • • • 1 Z Z Z Z 0 C • • C # OP n # OP n # OP n # OP n # OP n N N N DIV E2 16 2 NV EOR (Note 1) 55 4 2 4D 4 3 5D 5 3 59 5 3 41 6 2 51 6 2 N • • • • • Z • INC INX INY JMP A ← A + 1 or M←M+1 X←X+1 Y←Y+1 If addressing mode is ABS PCL ← ADL PCH ← AD H If addressing mode is IND PCL ← M (ADH, AD L) PCH ← M (ADH, ADL + 1) If addressing mode is ZP, IND PCL ← M(00, ADL) PCH ← M(00, AD L + 1) M(S) ← PCH S←S–1 M(S) ← PCL S←S–1 After executing the above, if addressing mode is ABS, PCL ← ADL PCH ← AD H if addressing mode is SP, PCL ← ADL PCH ← FF If addressing mode is ZP, IND, PCL ← M(00, ADL) PCH ← M(00, AD L + 1) When T = 0 A←M When T = 1 M(X) ← M 3A 1 1 E6 5 2 F6 6 2 EE 6 3 FE 7 3 N N • • • • • • • • • • Z Z • • N 6C 5 3 B2 4 2 • • • • • • • • • • • Z • • • JSR This instruction stores the contents of the PC in the stack, then jumps to the address designated by the following addressing modes: Absolute Special Page Zero Page Indirect Absolute 20 6 3 02 7 2 22 5 2 • • • • • • • • LDA (Note 2) When T = 0, this instruction transfers the contents of M to A. When T = 1, this instruction transfers the contents of M to (M(X)). The contents of A remain unchanged, but status flags are changed. M(X) represents the contents of memory where is indicated by X. This instruction loads the immediate value in M. This instruction loads the contents of M in X. This instruction loads the contents of M in Y. A9 2 2 A5 3 2 B5 4 2 AD 4 3 BD 5 3 B9 5 3 A1 6 2 B1 6 2 N • • • • • Z • LDM LDX LDY M ← nn X←M Y←M 3C 4 A2 2 A0 2 2 2 A6 3 A4 3 3 2 2 B4 4 2 B6 4 2 AE 4 AC 4 3 3 BC 5 3 BE 5 3 • N N • • • • • • • • • • • • • • • • Z Z • • • Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 98 of 108 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 99 of 108 APPENDIX 7641 Group 3.7 Machine instructions 7641 Group APPENDIX 3.7 Machine instructions Addressing mode Symbol Function Details IMP OP n LSR 0→ 7 0 →C This instruction shifts either A or M one bit to the right such that bit 7 of the result always is set to 0, and the bit 0 is stored in C. This instruction multiply Accumulator with the memory specified by the Zero Page X address mode and stores the high-order byte of the result on the Stack and the low-order byte in A. This instruction adds one to the PC but does EA 1 no other operation. When T = 0, this instruction transfers the contents of A and M to the ALU which performs a bit-wise “OR”, and stores the result in A. When T = 1, this instruction transfers the contents of M(X) and the M to the ALU which performs a bit-wise OR, and stores the result in M(X). The contents of A remain unchanged, but status flags are changed. M(X) represents the contents of memory where is indicated by X. This instruction pushes the contents of A to the memory location designated by S, and decrements the contents of S by one. This instruction pushes the contents of PS to the memory location designated by S and decrements the contents of S by one. This instruction increments S by one and stores the contents of the memory designated by S in A. This instruction increments S by one and stores the contents of the memory location designated by S in PS. This instruction shifts either A or M one bit left through C. C is stored in bit 0 and bit 7 is stored in C. This instruction shifts either A or M one bit right through C. C is stored in bit 7 and bit 0 is stored in C. This instruction rotates 4 bits of the M content to the right. This instruction increments S by one, and stores the contents of the memory location designated by S in PS. S is again incremented by one and stores the contents of the memory location designated by S in PC L. S is again incremented by one and stores the contents of memory location designated by S in PCH. This instruction increments S by one and stores the contents of the memory location designated by S in PCL. S is again incremented by one and the contents of the memory location is stored in PC H . PC is incremented by 1. 48 3 1 1 09 2 2 05 3 2 15 4 2 0D 4 3 1D 5 3 19 5 IMM # OP n A # OP n 4A 1 BIT, A # OP n 1 ZP # OP n 46 5 BIT, ZP # OP n 2 # ZP, X OP n 56 6 ZP, Y # OP n 2 ABS # OP n 4E 6 ABS, X # OP n 3 5E 7 Addressing mode ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 Processor status register 6 V • 5 T • 4 B • 3 D • 2 I • 1 Z Z 0 C C # OP n 3 # OP n # OP n # OP n # OP n N 0 MUL M(S) • A ← A ✽ M(zz + X) S←S–1 62 14 2 N • • • • • Z • NOP ORA (Note 1) PC ← PC + 1 When T = 0 A←AVM When T = 1 M(X) ← M(X) V M • 01 6 2 11 6 2 N • • • • • • • • • • • Z • • 3 PHA M(S) ← A S←S–1 • • • • • • • • PHP M(S) ← PS S←S–1 S←S+1 A ← M(S) S←S+1 PS ← M(S) • 08 3 1 • • • • • • • PLA N 68 4 1 • • • • • Z • PLP 28 4 1 (Value saved in stack) ROL 7 ← 0 ←C ← 2A 1 1 26 5 2 36 6 2 2E 6 3 3E 7 3 N • • • • • Z C ROR 7 C→ 0 → 6A 1 1 66 5 2 76 6 2 6E 6 3 7E 7 3 N • • • • • Z C RRF 7 → S←S+1 PS ← M(S) S←S+1 PCL ← M(S) S←S+1 PCH ← M(S) 0 → 82 8 2 • • • • • • • • RTI (Value saved in stack) 40 6 1 RTS S←S+1 PCL ← M(S) S←S+1 PCH ← M(S) (PC) ← (PC) + 1 • 60 6 1 • • • • • • • Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 100 of 108 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 101 of 108 APPENDIX 7641 Group 3.7 Machine instructions 7641 Group APPENDIX 3.7 Machine instructions Addressing mode Symbol Function Details IMP OP n SBC (Note 1) (Note 7) When T = 0 _ A←A–M–C When T = 1 _ M(X) ← M(X) – M – C When T = 0, this instruction subtracts the value of M and the complement of C from A, and stores the results in A and C. When T = 1, the instruction subtracts the contents of M and the complement of C from the contents of M(X), and stores the results in M(X) and C. A remain unchanged, but status flag are changed. M(X) represents the contents of memory where is indicated by X. This instruction sets the designated bit i of A or M. This instruction sets C. This instruction set D. 38 1 F8 1 78 2 32 1 1 1 IMM # OP n E9 2 A # OP n 2 BIT, A # OP n ZP # OP n E5 3 BIT, ZP # OP n 2 # ZP, X OP n F5 4 ZP, Y # OP n 2 ABS # OP n ED 4 ABS, X # OP n 3 FD 5 Addressing mode ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 Processor status register 6 V V 5 T • 4 B • 3 D • 2 I • 1 Z Z 0 C C # OP n 3 F9 5 # OP n 3 # OP n E1 6 # OP n 2 F1 6 # OP n 2 N N SEB SEC SED Ai or Mi ← 1 C←1 D←1 I←1 T←1 M←A 0B + 20i 1 1 0F + 20i 5 2 • • • • • • • • • • • • • • • • 1 • • • • • • • • • • • 1 • • • • • • • 1 • • • • • • • • • • • 1 • • • • • SEI SET STA STP This instruction set I. This instruction set T. This instruction stores the contents of A in M. The contents of A does not change. This instruction resets the oscillation control F/ F and the oscillation stops. Reset or interrupt input is needed to wake up from this mode. 1 1 85 3 2 95 4 2 8D 4 3 9D 5 3 99 5 3 81 6 2 91 6 2 • • 42 2 1 STX M←X M←Y X←A Y←A M = 0? X←S A←X S←X A←Y This instruction stores the contents of X in M. The contents of X does not change. This instruction stores the contents of Y in M. The contents of Y does not change. This instruction stores the contents of A in X. AA 1 The contents of A does not change. This instruction stores the contents of A in Y. The contents of A does not change. This instruction tests whether the contents of M are “0” or not and modifies the N and Z. This instruction transfers the contents of S in BA 1 X. This instruction stores the contents of X in A. This instruction stores the contents of X in S. This instruction stores the contents of Y in A. The WIT instruction stops the internal clock but not the oscillation of the oscillation circuit is not stopped. CPU starts its function after the Timer X over flows (comes to the terminal count). All registers or internal memory contents except Timer X will not change during this mode. (Of course needs VDD). 8A 1 9A 1 98 1 1 1 1 1 A8 1 1 1 86 3 84 3 2 2 94 4 96 4 2 2 8E 4 8C 4 3 3 • • • • • • • • • • • • • • • • STY TAX TAY TST TSX N N 64 3 2 N N N • • • • • • • • • • • • • • • • • • • • • • • • • Z Z Z Z Z • • • • • TXA TXS TYA WIT • N • • • • • • • • • • • • • • • • • Z • • • • C2 2 1 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 102 of 108 Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 103 of 108 APPENDIX 7641 Group 3.7 Machine instructions Notes 1 2 3 4 5 : : : : : 6: 7: 8: 9: The number of cycles “n” is increased by 3 when T is 1. The number of cycles “n” is increased by 2 when T is 1. The number of cycles “n” is increased by 1 when T is 1. The number of cycles “n” is increased by 2 when branching has occurred. The number of cycles “n” is increased by 1 when branching to the same page has occurred. The number of cycles “n” is increased by 2 when branching to the other page has occurred. The number of cycles “n” is increased by 1 when branching to the other page has occurred. V flag is invalid in decimal operation mode. When this instruction is executed immediately after executing DEX, DEY, INX, INY, TAX, TSX, TXA, TYA, DEC, INC, ASL, LSR, ROL, or ROR instructions, the number of cycles “n” becomes “3”. Furthermore, the number of cycles “n” is increased by 1 (number of cycles “n” is “4”) when branching to the same page has occurred. The number of cycles “n” is increased by 2 (number of cycles “n” is “5”) when branching to the other page has occurred. When this instruction is executed immediately after executing ASL, LSR, ROL, or ROR instructions, the number of cycles “n” becomes “3”. Furthermore, the number of cycles “n” is increased by 1 (number of cycles “n” is “4”) when branching to the same page has occurred. The number of cycles “n” is increased by 2 (number of cycles “n” is “5”) when branching to the other page has occurred. Symbol Contents Implied addressing mode Immediate addressing mode Accumulator or Accumulator addressing mode Accumulator bit addressing mode Accumulator bit relative addressing mode Zero page addressing mode Zero page bit addressing mode Zero page bit relative addressing mode Zero page X addressing mode Zero page Y addressing mode Absolute addressing mode Absolute X addressing mode Absolute Y addressing mode Indirect absolute addressing mode Zero page indirect absolute addressing mode Indirect X addressing mode Indirect Y addressing mode Relative addressing mode Special page addressing mode Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag X-modified arithmetic mode flag Overflow flag Negative flag + – ✽ / V V – V – ← X Y S PC PS PCH PCL ADH ADL FF nn zz M M(X) M(S) M(ADH, ADL) Symbol Contents Addition Subtraction Multiplication Division Logical OR Logical AND Logical exclusive OR Negation Shows direction of data flow Index register X Index register Y Stack pointer Program counter Processor status register 8 high-order bits of program counter 8 low-order bits of program counter 8 high-order bits of address 8 low-order bits of address FF in Hexadecimal notation Immediate value Zero page address Memory specified by address designation of any addressing mode Memory of address indicated by contents of index register X Memory of address indicated by contents of stack pointer Contents of memory at address indicated by ADH and ADL, in ADH is 8 high-order bits and ADL is 8 low-order bits. Contents of address indicated by zero page ADL Bit i (i = 0 to 7) of accumulator Bit i (i = 0 to 7) of memory Opcode Number of cycles Number of bytes IMP IMM A BIT, A BIT, A, R ZP BIT, ZP BIT, ZP, R ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP C Z I D B T V N M(00, ADL) Ai Mi OP n # Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 104 of 108 APPENDIX 7641 Group 3.8 List of instruction code 3.8 List of instruction code D3 – D0 Hexadecimal notation 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 D7 – D4 0 1 2 3 4 5 ORA ZP ORA ZP, X AND ZP AND ZP, X EOR ZP EOR ZP, X ADC ZP ADC ZP, X STA ZP STA ZP, X LDA ZP LDA ZP, X CMP ZP CMP ZP, X SBC ZP SBC ZP, X 6 ASL ZP ASL ZP, X ROL ZP ROL ZP, X LSR ZP LSR ZP, X ROR ZP ROR ZP, X STX ZP STX ZP, Y LDX ZP LDX ZP, Y DEC ZP DEC ZP, X INC ZP INC ZP, X 7 BBS 0, ZP BBC 0, ZP BBS 1, ZP BBC 1, ZP BBS 2, ZP BBC 2, ZP BBS 3, ZP BBC 3, ZP BBS 4, ZP BBC 4, ZP BBS 5, ZP BBC 5, ZP BBS 6, ZP BBC 6, ZP BBS 7, ZP BBC 7, ZP 8 9 ORA IMM ORA ABS, Y AND IMM AND ABS, Y EOR IMM EOR ABS, Y ADC IMM ADC ABS, Y — STA ABS, Y LDA IMM LDA ABS, Y CMP IMM CMP ABS, Y SBC IMM SBC ABS, Y A ASL A DEC A ROL A INC A LSR A — ROR A — B SEB 0, A CLB 0, A SEB 1, A CLB 1, A SEB 2, A CLB 2, A SEB 3, A CLB 3, A SEB 4, A CLB 4, A SEB 5, A CLB 5, A SEB 6, A CLB 6, A SEB 7, A CLB 7, A C D ORA ABS E ASL ABS F SEB 0, ZP 0000 BRK BBS ORA JSR IND, X ZP, IND 0, A ORA IND, Y AND IND, X AND IND, Y EOR IND, X EOR IND, Y CLT JSR SP SET BBC 0, A BBS 1, A BBC 1, A BBS 2, A BBC 2, A BBS 3, A BBC 3, A BBS 4, A BBC 4, A BBS 5, A — PHP — 0001 1 BPL JSR ABS BMI — BIT ZP — COM ZP — TST ZP — STY ZP STY ZP, X LDY ZP LDY ZP, X CPY ZP — CPX ZP — CLC — BIT ABS ASL CLB ORA ABS, X ABS, X 0, ZP AND ABS ROL ABS SEB 1, ZP 0010 2 PLP 0011 3 SEC ROL CLB LDM AND ZP ABS, X ABS, X 1, ZP JMP ABS — JMP IND — STY ABS — LDY ABS EOR ABS LSR ABS SEB 2, ZP 0100 4 RTI STP PHA 0101 5 BVC — CLI LSR CLB EOR ABS, X ABS, X 2, ZP ADC ABS ROR ABS SEB 3, ZP 0110 6 RTS MUL ADC IND, X ZP, X ADC IND, Y STA IND, X STA IND, Y LDA IND, X — RRF ZP — LDX IMM PLA 0111 7 BVS SEI ROR CLB ADC ABS, X ABS, X 3, ZP STA ABS STA ABS, X LDA ABS STX ABS — LDX ABS SEB 4, ZP CLB 4, ZP SEB 5, ZP 1000 8 BRA DEY TXA 1001 9 BCC LDY IMM BCS CPY IMM BNE CPX IMM BEQ TYA TXS 1010 A TAY TAX 1011 B JMP BBC LDA IND, Y ZP, IND 5, A CMP IND, X CMP IND, Y WIT BBS 6, A BBC 6, A BBS 7, A BBC 7, A CLV TSX LDX CLB LDY LDA ABS, X ABS, X ABS, Y 5, ZP CPY ABS — CPX ABS — CMP ABS DEC ABS SEB 6, ZP 1100 C INY DEX 1101 D — CLD — DEC CLB CMP ABS, X ABS, X 6, ZP SBC ABS INC ABS SEB 7, ZP 1110 E DIV SBC IND, X ZP, X SBC IND, Y — INX NOP 1111 F SED — INC CLB SBC ABS, X ABS, X 7, ZP : 3-byte instruction : 2-byte instruction : 1-byte instruction Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 105 of 108 APPENDIX 7641 Group 3.9 SFR memory map 3.9 SFR memory map 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 CPU mode register A (CPUA) CPU mode register B (CPUB) Interrupt request register A (IREQA) Interrupt request register B (IREQB) Interrupt request register C (IREQC) Interrupt control register A (ICONA) Interrupt control register B (ICONB) Interrupt control register C (ICONC) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port control register (PTC) Interrupt polarity select register (IPOL) Port P2 pull-up control register (PUP2) USB control register (USBC) Port P6 (P6) Port P6 direction register (P6D) Port P5 (P5) Port P5 direction register (P5D) Port P4 (P4) Port P4 direction register (P4D) Port P7 (P7) Port P7 direction register (P7D) Port P8 (P8) Port P8 direction register (P8D) Resereved (Note 1) Clock control register (CCR) Timer XL (TXL) Timer XH (TXH) Timer YL (TYL) Timer YH (TYH) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer X mode register (TXM) Timer Y mode register (TYM) Timer 123 mode register (T123M) Serial I/O shift register (SIOSHT) Serial I/O control register 1 (SIOCON1) Serial I/O control register 2 (SIOCON2) Special count source generator 1 (SCSG1) Special count source generator 2 (SCSG2) Special count source mode register (SCSGM) UART1 mode register (U1MOD) UART1 baud rate generator (U1BRG) UART1 status register (U1STS) UART1 control register (U1CON) UART1 transmit/receive buffer register 1 (U1TRB1) UART1 transmit/receive buffer register 2 (U1TRB2) UART1 RTS control register (U1RTSC) Resereved (Note 1) 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 UART2 mode register (U2MOD) UART2 baud rate generator (U2BRG) UART2 status register (U2STS) UART2 control register (U2CON) UART2 transmit/receive buffer register 1 (U2TRB1) UART2 transmit/receive buffer register 2 (U2TRB2) UART2 RTS control register (U2RTSC) DMAC index and status register (DMAIS) DMAC channel x mode register 1 (DMAx1) DMAC channel x mode register 2 (DMAx2) DMAC channel x source register Low (DMAxSL) DMAC channel x source register High (DMAxSH) DMAC channel x destination register Low (DMAxDL) DMAC channel x destination register High (DMAxDH) DMAC channel x transfer count register Low (DMAxCL) DMAC channel x transfer count register High (DMAxCH) Data bus buffer register 0 (DBB0) Data bus buffer status register 0 (DBBS0) Data bus buffer control register 0 (DBBC0) Resereved (Note 1) Data bus buffer register 1 (DBB1) Data bus buffer status register 1 (DBBS1) Data bus buffer control register 1 (DBBC1) Resereved (Note 1) USB address register (USBA) USB power management register (USBPM) USB interrupt status register 1 (USBIS1) USB interrupt status register 2 (USBIS2) USB interrupt enable register 1 (USBIE1) USB interrupt enable register 2 (USBIE2) USB frame number register Low (USBSOFL) USB frame number register High (USBSOFH) USB endpoint index register (USBINDEX) USB endpoint x IN control register (IN_CSR) USB endpoint x OUT control register (OUT_CSR) USB endpoint x IN max. packet size register (IN_MAXP) USB endpoint x OUT max. packet size register (OUT_MAXP) USB endpoint x OUT write count register Low (WRT_CNTL) USB endpoint x OUT write count register High (WRT_CNTH) USB endpoint FIFO mode register (USBFIFOMR) USB endpoint 0 FIFO (USBFIFO0) USB endpoint 1 FIFO (USBFIFO1) USB endpoint 2 FIFO (USBFIFO2) USB endpoint 3 FIFO (USBFIFO3) USB endpoint 4 FIFO (USBFIFO4) Resereved (Note 1) Resereved (Note 1) Resereved (Note 1) Resereved (Note 1) Resereved (Note 1) Flash memory control register (FMCR) (Note 2) Resereved (Note 1) Frequency synthesizer control register (FSC) Frequency synthesizer multiply register 1 (FSM1) Frequency synthesizer multiply register 2 (FSM2) Frequency synthesizer divide register (FSD) FFC916 ROM code protect control register (ROMCP) (Note 3) Notes 1: Do not write any data to this addresses, because these areas are reserved. 2: This area is reserved in the mask ROM version. 3: This area is on the ROM in the mask ROM version. Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 106 of 108 APPENDIX 7641 Group 3.10 Pin configuration 3.10 Pin configuration 60 59 58 57 56 55 54 53 52 51 50 49 48 64 63 62 61 47 46 45 44 43 42 41 P20/DB0 P21/DB1 P22/DB2 P23/DB3 P24/DB4 P25/DB5 P26/DB6 P27/DB7 P00/AB0 P01/AB1 P02/AB2 P03/AB3 P04/AB4 P05/AB5 P06/AB6 P07/AB7 P10/AB8 P11/AB9 P12/AB10 P13/AB11 P14/AB12 P15/AB13 P16/AB14 P17/AB15 P74/OBF1 P73/IBF1/HLDA P72/S1 P71/HOLD P70/SOF USB D+ USB DExt.Cap VSS VCC P67/DQ7 P66/DQ6 P65/DQ5 P64/DQ4 P63/DQ3 P62/DQ2 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 M37641M8-XXXFP M37641F8FP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P30/RDY P31 P32 P33/DMAOUT P34/φ OUT P35/SYNCOUT P36/WR P37/RD P80/UTXD2/SRDY P81/URXD2/SCLK P82/CTS2/SRXD P83/RTS2/STXD P84/UTXD1 P85/URXD1 P86/CTS1 P87/RTS1 20 21 22 23 10 11 12 13 14 15 16 17 18 P61/DQ1 P60/DQ0 P57/W/(R/W) P56/R(E) P55/A0 P54/S0 P53/IBF0 P52/OBF0 CNVSS/VPP RESET P51/TOUT/XCOUT P50/XCIN VSS XIN Package type: PRQP0080GB-A (Top view) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 107 of 108 XOUT VCC AVCC LPF AVSS P44/CNTR1 P43/CNTR0 P42/INT1 P41/INT0 P40/EDMA 19 24 1 2 3 4 5 6 7 8 9 APPENDIX 7641 Group 3.10 Pin configuration 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 60 P21/DB1 P20/DB0 P74/OBF1 P73/IBF1/HLDA P72/S1 P71/HOLD P70/SOF USB D+ USB DExt.Cap VSS VCC P67/DQ7 P66/DQ6 P65/DQ5 P64/DQ4 P63/DQ3 P62/DQ2 P61/DQ1 P60/DQ0 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 10 11 12 13 14 15 16 17 18 19 20 6 7 1 2 3 4 5 8 9 42 41 P22/DB2 P23/DB3 P24/DB4 P25/DB5 P26/DB6 P27/DB7 P00/AB0 P01/AB1 P02/AB2 P03/AB3 P04/AB4 P05/AB5 P06/AB6 P07/AB7 P10/AB8 P11/AB9 P12/AB10 P13/AB11 P14/AB12 P15/AB13 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 M37641M8-XXXHP M37641F8HP P16/AB14 P17/AB15 P30/RDY P31 P32 P33/DMAOUT P34/φ OUT P35/SYNCOUT P36/WR P37/RD P80/UTXD2/SRDY P81/URXD2/SCLK P82/CTS2/SRXD P83/RTS2/STXD P84/UTXD1 P85/URXD1 P86/CTS1 P87/RTS1 P40/EDMA P41/INT0 Package type: PLQP0080KB-A (Top view) Rev.2.00 Aug 28, 2006 REJ09B0336-0200 page 108 of 108 P57/W/(R/W) P56/R(E) P55/A0 P54/S0 P53/IBF0 P52/OBF0 CNVSS/VPP RESET P51/TOUT/XCOUT P50/XCIN VSS XIN XOUT VCC AVCC LPF AVSS P44/CNTR1 P43/CNTR0 P42/INT1 REVISION HISTORY Rev. 1.0 2.0 Date Page 02/26/2002 First edition 7641 GROUP USER’S MANUAL Description Summary 08/28/2006 All pages Package names “80P6N-A” → “PRQP0080GB-A” revised Package names “80P6Q-A” → “PLQP0080KB-A” revised All pages “USB std. spec. ver.1.1” → “Full-Speed USB2.0 specification” Chapter 1 39 DMAC; “(DxCEN)” → “(DxHR)” 55 Fig. 47 “4: To use the AUTO_SET function .... to single buffer mode.” added 71 CLOCK GENERATING CIRCUIT; “No external resistor is needed .... resistor exists on-chip.” → “No external resistor is needed .... depending on conditions.) Fig. 64; Pulled up added, NOTE added 108 UART; “•Do not update .... data might be output.” added 109 USB; “•Use the AUTO_FLUSH Bit .... buffer mode.”, “•To use the AUTO_SET function .... to single buffer mode.” added 111 Oscillator Connection Notice; “The built-in feedback register (400 ) .... pins X IN and XOUT.” → “The built-in feedback register (1 M ) .... pins X IN and XOUT.” Power Source Voltage added 112 USB Communication added “For the mask ROM confirmation .... http://www.infomicom.maec.co.jp/indexe.htm” → “For the mask ROM confirmation .... (http://www.renesas.com).” Chapter 2 95 2.5.6 “64-byte”, “64 bytes” → “128-byte”, “128 bytes” “USB endpoint 1” → “USB endpoint 2” 96-98 Fig. 2.5.16, Fig. 2.5.17, Fig. 2.5.18 revised Chapter 3 30 (5) Receive error flag added 32 3.3.5 (4) USB Communication added 35 (5) Registers and bits; “•To use the AUTO_SET function .... to single buffer mode.” added 83 Fig. 3.5.55 “3: To use the AUTO_SET function .... to single buffer mode.” added 92 3.6 Package outline revised (1/1) RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER USER ’S MANUAL 7641 Group Publication Data : Published by : Rev.2.00 Aug 28, 2006 Sales Strategic Planning Div. Renesas Technology Corp. © 2 006. Renesas Technology Corp., All rights reserved. Printed in Japan. 7641 Group User's Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan