7643_06

REJ09B0133-0200 8 7643 Group User's Manual RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 7600 SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). Rev. 2.00 Revision date: Aug 28, 2006 www.renesas.com Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 2. 3. 4. 5. 6. 7. 8. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http:// www.renesas.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. B EFORE USING THIS MANUAL This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. Chapter 3 also includes necessary information for systems development. You must refer to that chapter. 1. Organization q C HAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. q C HAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of relevant registers. q C HAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer, such as the electrical characteristics, the notes, and the list of registers. ✽ For the mask ROM confirmation form, the ROM programming confirmation form, and the mark specifications, refer to the “Renesas Technology” Homepage (http://www.renesas.com/en/rom). 2. Structure of register The figure of each register structure describes its functions, contents at reset, and attributes as follows : (Note 2) Bits b7 b6 b5 b4 b3 b2 b1 b0 0 Bit attributes (Note 1) Contents immediately after reset release CPU mode register (CPUM) [Address : 3B16] B 0 1 2 3 4 5 6 7 Stack page selection bit Name Processor mode bits b1 b0 Function 0 0 : Single-chip mode 01: 1 0 : Not available 11: 0 : 0 page 1 : 1 page At reset RW 0 0 0 0 0 1 ✽ ✽ ✕ ✕ Nothing arranged for these bits. These are write disabled bits. When these bits are read out, the contents are “0.” Fix this bit to “0.” Main clock (XIN-XOUT) stop bit Internal system clock selection bit 0 : Operating 1 : Stopped 0 : XIN-XOUT selected 1 : XCIN-XCOUT selected : Bit in which nothing is arranged : Bit that is not used for control of the corresponding function Note 1:. Contents immediately after reset release 0....... “0” at reset release 1....... “1” at reset release ?....... Undefined at reset release ✽.......Contents determined by option at reset release Note 2: Bit attributes......... The attributes of control register bits are classified into 3 bytes : read-only, writeonly and read and write. In the figure, these attributes are represented as follows : R....... Read ...... Read enabled ✕.......Read disabled W......Write ..... Write enabled ✕...... Write disabled 3. Supplementation For details of development support tools, refer to the “Renesas Technology” Homepage (http://www.renesas.com). Table of contents 7643 Group Table of contents CHAPTER 1 HARDWARE DESCRIPTION ................................................................................................................................... 2 FEATURES ......................................................................................................................................... 2 APPLICATION ................................................................................................................................... 2 PIN CONFIGURATION (TOP VIEW) .............................................................................................. 3 FUNCTIONAL BLOCK DIAGRAM (Package: PRQP0080GB-A) ............................................... 4 PIN DESCRIPTION ........................................................................................................................... 5 PART NUMBERING .......................................................................................................................... 7 GROUP EXPANSION ....................................................................................................................... 8 Memory Type Memory Size Memory Expansion ...................................................................................................................... 8 Packages ...................................................................................................................................... 8 FUNCTIONAL DESCRIPTION ......................................................................................................... 9 CENTRAL PROCESSING UNIT (CPU) .................................................................................... 9 MEMORY .................................................................................................................................... 13 I/O PORTS ................................................................................................................................. 15 INTERRUPTS ............................................................................................................................. 21 TIMERS ...................................................................................................................................... 25 SERIAL I/O ................................................................................................................................. 27 UART .......................................................................................................................................... 31 DMAC .......................................................................................................................................... 37 USB FUNCTION ........................................................................................................................ 42 FREQUENCY SYNTHESIZER (PLL) ...................................................................................... 57 RESET CIRCUIT ....................................................................................................................... 59 CLOCK GENERATING CIRCUIT ............................................................................................ 61 PROCESSOR MODE ................................................................................................................ 65 FLASH MEMORY MODE ............................................................................................................... 71 NOTES ON PROGRAMMING ........................................................................................................ 98 USAGE NOTES ............................................................................................................................. 101 ROM ORDERING METHOD ........................................................................................................ 102 FUNCTIONAL DESCRIPTION SUPPLEMENT .......................................................................... 103 CHAPTER 2 APPLICATION 2.1 I/O port ........................................................................................................................................ 2 2.1.1 Memory map ...................................................................................................................... 2 2.1.2 Related registers ............................................................................................................... 3 2.1.3 Key-on wake-up interrupt application example ............................................................. 7 2.1.4 Terminate unused pins ..................................................................................................... 9 2.1.5 Notes on I/O port ............................................................................................................ 10 2.1.6 Termination of unused pins ........................................................................................... 11 2.2 Timer .......................................................................................................................................... 12 2.2.1 Memory map .................................................................................................................... 12 2.2.2 Related registers ............................................................................................................. 13 2.2.3 Timer application examples ........................................................................................... 16 2.2.4 Notes on timer ................................................................................................................. 22 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 1 of 12 Table of contents 7643 Group 2.3 Serial I/O ................................................................................................................................... 23 2.3.1 Memory map .................................................................................................................... 23 2.3.2 Related registers ............................................................................................................. 24 2.3.3 Serial I/O connection examples .................................................................................... 27 2.3.4 Serial I/O application example ...................................................................................... 29 2.3.5 Notes on serial I/O ......................................................................................................... 36 2.4 UART ......................................................................................................................................... 37 2.4.1 Memory map .................................................................................................................... 37 2.4.2 Related registers ............................................................................................................. 38 2.4.3 UART transfer data format ............................................................................................ 45 2.4.4 Transfer bit rate .............................................................................................................. 46 2.4.5 Operation of transmitting and receiving ....................................................................... 47 2.4.6 UART application example ............................................................................................. 49 2.4.7 Notes on UART ............................................................................................................... 73 2.5 DMAC ......................................................................................................................................... 75 2.5.1 Memory map .................................................................................................................... 75 2.5.2 Related registers ............................................................................................................. 76 2.5.3 DMAC operation description .......................................................................................... 84 2.5.4 DMAC arbitration ............................................................................................................. 88 2.5.5 Transfer time .................................................................................................................... 88 2.5.6 DMAC application example ............................................................................................ 91 2.5.7 Notes on DMAC .............................................................................................................. 95 2.6 USB ............................................................................................................................................ 96 2.6.1 USB outline ...................................................................................................................... 96 2.6.2 Memory map .................................................................................................................. 103 2.6.3 Related registers ........................................................................................................... 104 2.6.4 USB transmit .................................................................................................................. 124 2.6.5 USB receive ................................................................................................................... 126 2.6.6 USB interrupts ............................................................................................................... 127 2.6.7 Application example ...................................................................................................... 128 2.6.8 Connection with other functions .................................................................................. 148 2.6.9 Application circuit example .......................................................................................... 161 2.6.10 Notes on USB function .............................................................................................. 163 2.7 Frequency synthesizer ........................................................................................................ 167 2.7.1 Memory map .................................................................................................................. 167 2.7.2 Related registers ........................................................................................................... 168 2.7.3 Functional description ................................................................................................... 171 2.7.4 Notes on frequency synthesizer .................................................................................. 173 2.8 External devices connection .............................................................................................. 174 2.8.1 Memory map .................................................................................................................. 174 2.8.2 Related registers ........................................................................................................... 175 2.8.3 Functional description ................................................................................................... 176 2.8.4 Slow memory wait ......................................................................................................... 177 2.8.5 HOLD function ............................................................................................................... 180 2.8.6 Expanded data memory access .................................................................................. 181 2.8.7 External devices connection example ........................................................................ 182 2.8.8 Notes on external devices connection ....................................................................... 186 2.9 Reset ........................................................................................................................................ 188 2.9.1 Connection example of reset IC ................................................................................. 188 2.9.2 Notes on reset ............................................................................................................... 188 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 2 of 12 Table of contents 7643 Group 2.10 Clock generating circuit ................................................................................................... 189 2.10.1 Memory map ................................................................................................................ 189 2.10.2 Related registers ......................................................................................................... 190 2.10.3 Stop mode .................................................................................................................... 193 2.10.4 Wait mode .................................................................................................................... 194 2.10.5 Clock generating circuit application examples ........................................................ 195 CHAPTER 3 APPENDIX 3.1 Electrical characteristics ........................................................................................................ 2 3.1.1 Absolute maximum ratings ............................................................................................... 2 3.1.2 Recommended operating conditions (In Vcc = 5 V) .................................................... 3 3.1.3 Electrical characteristics (In Vcc = 5 V) ........................................................................ 4 3.1.4 Timing Requirements (In Vcc = 5 V) ............................................................................. 6 3.1.5 Timing requirements and switching characteristics in memory expansion and microprocessor modes (In Vcc = 5 V) ........................................................................... 7 3.1.6 Recommended Operating Conditions ............................................................................. 8 3.1.7 Electrical Characteristics .................................................................................................. 9 3.1.8 Timing Requirements ...................................................................................................... 11 3.1.9 Timing requirements and switching characteristics in memory expansion and microprocessor modes (In Vcc = 3 V) ......................................................................... 12 3.2 Standard characteristics ....................................................................................................... 18 3.2.1 Power source current standard characteristics ........................................................... 18 3.2.2 Port standard characteristics ......................................................................................... 19 3.3 Notes on use ........................................................................................................................... 22 3.3.1 Notes on interrupts ......................................................................................................... 22 3.3.2 Notes on serial I/O ......................................................................................................... 23 3.3.3 Notes on UART ............................................................................................................... 24 3.3.4 Notes on DMAC .............................................................................................................. 26 3.3.5 Notes on USB .................................................................................................................. 27 3.3.6 Notes on frequency synthesizer .................................................................................... 31 3.3.7 Notes on external devices connection ......................................................................... 31 3.3.8 Notes on timer ................................................................................................................. 33 3.3.9 Notes on Stop mode ...................................................................................................... 33 3.3.10 Notes on reset ............................................................................................................... 34 3.3.11 Notes on I/O port .......................................................................................................... 34 3.3.12 Notes on programming ................................................................................................. 35 3.3.13 Termination of unused pins ......................................................................................... 37 3.3.14 Notes on CPU rewrite mode for flash memory version .......................................... 38 3.4 Countermeasures against noise ......................................................................................... 39 3.4.1 Shortest wiring length ..................................................................................................... 39 3.4.2 Connection of bypass capacitor across Vss line and Vcc line ................................ 40 3.4.3 Oscillator concerns .......................................................................................................... 41 3.4.4 Setup for I/O ports .......................................................................................................... 42 3.4.5 Providing of watchdog timer function by software ..................................................... 43 3.5 Control registers ..................................................................................................................... 44 3.6 Package outline ...................................................................................................................... 82 3.7 Machine instructions ............................................................................................................. 84 3.8 List of instruction code ........................................................................................................ 95 3.9 SFR memory map ................................................................................................................... 96 3.10 Pin configuration .................................................................................................................. 97 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 3 of 12 List of figures 7643 Group List of figures CHAPTER 1 HARDWARE Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 1 M37643M8-XXXFP, M37643F8FP pin configuration ....................................................... 3 2 M37643M8-XXXHP, M37643F8HP pin configuration ....................................................... 3 3 Functional block diagram .................................................................................................... 4 4 Part numbering ..................................................................................................................... 7 5 Memory expansion ............................................................................................................... 8 6 7600 series CPU register structure ................................................................................... 9 7 Register push and pop at interrupt generation and subroutine call ........................... 10 8 Structure of CPU mode register ...................................................................................... 12 9 Memory map diagram ........................................................................................................ 13 10 Memory map of special function register (SFR) ......................................................... 14 11 Structure of port control and port P2 pull-up control registers ................................. 15 12 Port block diagram (1) .................................................................................................... 17 13 Port block diagram (2) .................................................................................................... 18 14 Port block diagram (3) .................................................................................................... 19 15 Port block diagram (4) .................................................................................................... 20 16 Interrupt control ................................................................................................................ 21 17 Structure of interrupt-related registers .......................................................................... 23 18 Connection example when using key input interrupt and port P2 block diagram .. 24 19 Timer block diagram ........................................................................................................ 25 20 Structure of timer 123 mode register ............................................................................ 26 21 Structure of serial I/O control registers 1, 2 ................................................................ 27 22 Block diagram of serial I/O ............................................................................................ 28 23 Serial I/O timing ............................................................................................................... 29 24 UART block diagram ....................................................................................................... 31 _______ 25 UART transmit timing (CTS function enabled) ............................................................ 32 _______ 26 UART transmit timing (CTS function disbled) .............................................................. 33 _______ 27 UART receiving timing (RTS function enabled) ........................................................... 33 28 Structure of UART related registers .............................................................................. 36 29 DMACx (x = 0, 1) block diagram .................................................................................. 37 30 Structure of DMACx related register ........................................................................... 38 31 Timing chart for cycle steal transfer caused by hardware-related transfer request ... 40 32 Timing chart for cycle steal transfer caused by software trigger transfer request ..... 40 33 Timing chart for burst transfer caused by hardware-related transfer request ........ 41 34 USB FCU (USB Function Control Unit) block ............................................................. 42 35 Structure of USB control register .................................................................................. 46 36 Structure of USB address register ................................................................................ 47 37 Structure of USB power management register ............................................................ 47 38 Structure of USB interrupt status register 1 ............................................................... 48 39 Structure of USB interrupt status register 2 ............................................................... 49 40 Structure of USB interrupt enable register 1 ............................................................. 49 41 Structure of USB interrupt enable register 2 ............................................................. 50 42 Structure of USB frame number registers .................................................................... 50 43 Structure of USB endpoint 0 IN control register ......................................................... 51 44 Structure of USB endpoint x (x = 1, 2) IN control register ....................................... 52 45 Structure of USB endpoint x (x = 1, 2) OUT control register ................................... 53 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 4 of 12 List of figures 7643 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 46 47 48 49 50 51 52 54 53 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 Structure of USB endpoint x IN max. packet size register ....................................... 54 Structure of USB endpoint x OUT max. packet size register ................................... 54 Structure of USB endpoint x (x = 0 to 2) OUT write count registers ...................... 55 Structure of USB endpoint x (x = 0 to 2) FIFO register ........................................... 55 Structure of USB endpoint FIFO mode register .......................................................... 56 Frequency synthesizer block diagram ........................................................................... 57 Structure of frequency synthesizer control register .................................................... 58 Reset sequence ............................................................................................................... 59 Reset circuit example ...................................................................................................... 59 Internal status at reset .................................................................................................... 60 Ceramic resonator or quartz-crystal oscillator external circuit .................................. 61 External clock input circuit ............................................................................................. 61 Structure of clock control register ................................................................................. 62 Clock generating circuit block diagram ......................................................................... 63 State transitions of clock ................................................................................................ 64 Memory maps in processor modes other than single-chip mode ............................. 65 Structure of CPU mode register A ................................................................................ 66 Structure of CPU mode register B ................................................................................ 66 Software wait timing diagram ......................................................................................... 67 RDY wait timing diagram ................................................................................................ 67 Extended RDY wait (software wait plus RDY input anytime wait) timing diagram 68 Hold function timing diagram ......................................................................................... 69 STA ($ zz), Y instruction sequence when EDMA enabled ........................................ 70 LDA ($ zz), Y instruction sequence when EDMA enabled and T flag = “ 0 ” .......... 70 LDA ($ zz), Y instruction sequence when EDMA enabled and T flag = “ 1 ” .......... 70 Block diagram of built-in flash memory ........................................................................ 72 Structure of flash memory control register ................................................................... 73 CPU rewrite mode set/release flowchart ...................................................................... 74 Program flowchart ............................................................................................................ 76 Erase flowchart ................................................................................................................. 77 Full status check flowchart and remedial procedure for errors ................................ 79 Structure of ROM code protect control ......................................................................... 80 ID code store addresses ................................................................................................. 81 Pin connection diagram in standard serial I/O mode (1) ........................................... 85 Pin connection diagram in standard serial I/O mode (2) ........................................... 86 Timing for page read ....................................................................................................... 88 Timing for reading status register ................................................................................. 88 Timing for clear status register ...................................................................................... 89 Timing for page program ................................................................................................ 89 Timing for block erasing ................................................................................................. 90 Timing for erase all blocks ............................................................................................. 90 Timing for download ........................................................................................................ 91 Timing for version information output ........................................................................... 92 Timing for Boot ROM area output ................................................................................. 92 Timing for ID check ......................................................................................................... 93 ID code storage addresses ............................................................................................ 93 Full status check flowchart and remedial procedure for errors ................................ 96 Example circuit application for standard serial I/O mode .......................................... 97 Passive components near LPF pin ............................................................................. 101 Peripheral circuit ............................................................................................................ 101 Timing chart after interrupt occurs .............................................................................. 103 Time up to execution of interrupt processing routine ................................................ 103 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 5 of 12 List of figures 7643 Group CHAPTER 2 APPLICATION Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.1.1 Memory map of registers related to I/O port .............................................................. 2 2.1.2 Structure of Port Pi register .......................................................................................... 3 2.1.3 Structure of Port P4, Port P7 registers ....................................................................... 3 2.1.4 Structure of Port Pi direction register (i = 0, 1, 2, 3, 5, 6, 8) ................................. 4 2.1.5 Structure of Port P4 direction, Port P7 direction registers ....................................... 4 2.1.6 Structure of Port control register .................................................................................. 5 2.1.7 Structure of Port P2 pull-up control register ............................................................... 5 2.1.8 Structure of Interrupt request register C ..................................................................... 6 2.1.9 Structure of Interrupt control register C ....................................................................... 6 2.1.10 Registers setting ............................................................................................................ 7 2.1.11 Connection diagram ...................................................................................................... 8 2.1.12 Control procedure .......................................................................................................... 8 2.2.1 Memory map of registers relevant to timers ............................................................. 12 2.2.2 Structure of Timer i (i=1, 2, 3) .................................................................................... 13 2.2.3 Structure of Timer 123 mode register ........................................................................ 13 2.2.4 Structure of Interrupt request register B .................................................................... 14 2.2.5 Structure of Interrupt request register C ................................................................... 14 2.2.6 Structure of Interrupt control register B ..................................................................... 15 2.2.7 Structure of Interrupt control register C ..................................................................... 15 2.2.8 Timers connection and setting of division ratios ...................................................... 16 2.2.9 Related registers setting .............................................................................................. 17 2.2.10 Control procedure ........................................................................................................ 18 2.2.11 Peripheral circuit example .......................................................................................... 19 2.2.12 Timers connection and setting of division ratios .................................................... 19 2.2.13 Relevant registers setting .......................................................................................... 20 2.2.14 Control procedure ........................................................................................................ 21 2.3.1 Memory map of registers related to serial I/O ......................................................... 23 2.3.2 Structure of Serial I/O shift register ........................................................................... 24 2.3.3 Structure of Serial I/O control register 1 ................................................................... 24 2.3.4 Structure of Serial I/O control register 2 ................................................................... 25 2.3.5 Structure of Interrupt request register C ................................................................... 26 2.3.6 Structure of Interrupt control register C ..................................................................... 26 2.3.7 Serial I/O connection examples (1) ............................................................................ 27 2.3.8 Serial I/O connection examples (2) ............................................................................ 28 2.3.9 Connection diagram ...................................................................................................... 29 2.3.10 Timing chart ................................................................................................................. 29 2.3.11 Registers setting for transmitter ................................................................................ 30 2.3.12 Setting of serial I/O transmission data .................................................................... 30 2.3.13 Control procedure of transmitter ............................................................................... 31 2.3.14 Connection diagram .................................................................................................... 32 2.3.15 Registers setting for SPI compatible mode ............................................................. 33 2.3.16 Control procedure of SPI compatible mode in slave ............................................. 34 2.3.17 Control procedure of SPI compatible mode in master .......................................... 35 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 6 of 12 List of figures 7643 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.4.1 Memory map of registers related to UART ............................................................... 37 2.4.2 Structure of UART mode register ............................................................................... 38 2.4.3 Structure of UART control register ............................................................................. 39 2.4.4 Structure of UART status register .............................................................................. 40 2.4.5 Structure of UART RTS control register .................................................................... 40 2.4.6 Structure of UART baud rate generator .................................................................... 41 2.4.7 Structure of UART transmit/receive buffer registers 1, 2 ........................................ 42 2.4.8 Structure of Interrupt request register A .................................................................... 43 2.4.9 Structure of Interrupt request register B .................................................................... 43 2.4.10 Structure of Interrupt control register A ................................................................... 44 2.4.11 Structure of Interrupt control register B ................................................................... 44 2.4.12 UART transfer data format ........................................................................................ 45 2.4.13 Connection diagram .................................................................................................... 49 2.4.14 Timing chart ................................................................................................................. 49 2.4.15 Registers setting for transmitter ................................................................................ 50 2.4.16 Registers setting for receiver (1) .............................................................................. 51 2.4.17 Registers setting for receiver (2) .............................................................................. 52 2.4.18 Control procedure of transmitter ............................................................................... 53 2.4.19 Control procedure of receiver .................................................................................... 54 2.4.20 Connection diagram .................................................................................................... 56 2.4.21 Registers setting related to UART address mode .................................................. 57 2.4.22 Control procedure (1) ................................................................................................. 58 2.4.23 Control procedure (2) ................................................................................................. 59 2.4.24 Connection diagram .................................................................................................... 60 2.4.25 Registers setting (1) ................................................................................................... 61 2.4.26 Registers setting (2) ................................................................................................... 62 2.4.27 Registers setting (3) ................................................................................................... 63 2.4.28 Control procedure (1) ................................................................................................. 64 2.4.29 Control procedure (2) ................................................................................................. 65 2.4.30 Connection diagram .................................................................................................... 66 2.4.31 Registers setting (1) ................................................................................................... 67 2.4.32 Registers setting (2) ................................................................................................... 68 2.4.33 Registers setting (3) ................................................................................................... 69 2.4.34 Registers setting (4) ................................................................................................... 70 2.4.35 Control procedure (1) ................................................................................................. 71 2.4.36 Control procedure (2) ................................................................................................. 72 2.5.1 Memory map of registers related to DMAC .............................................................. 75 2.5.2 Structure of DMAC index and status register ........................................................... 76 2.5.3 Structure of DMAC channel x (x = 0, 1) mode register 1 ...................................... 77 2.5.4 Structure of DMAC channel 0 mode register 2 ........................................................ 79 2.5.5 Structure of DMAC channel 1 mode register 2 ........................................................ 80 2.5.6 Structure of DMAC channel x source registers Low, High ..................................... 81 2.5.7 Structure of DMAC channel x destination registers Low, High .............................. 81 2.5.8 Structure of DMAC channel x transfer count registers Low, High ......................... 82 2.5.9 Structure of Interrupt request register A .................................................................... 83 2.5.10 Structure of Interrupt control register A ................................................................... 83 2.5.11 Transfer mode overview ............................................................................................. 84 2.5.12 Basic operation of registers transferring .................................................................. 85 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 7 of 12 List of figures 7643 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.5.13 Timing chart for cycle steal transfer caused by hardware-related transfer request ..... 89 2.5.14 Timing chart for cycle steal transfer caused by software trigger transfer request ....... 89 2.5.15 Timing chart for burst transfer caused by hardware-related transfer request .... 90 2.5.16 Setting of relevant registers (1) ................................................................................ 92 2.5.17 Setting of relevant registers (2) ................................................................................ 93 2.5.18 Control procedure ........................................................................................................ 94 2.6.1 1 frame image ............................................................................................................... 97 2.6.2 Packet type .................................................................................................................... 97 2.6.3 Transaction format ........................................................................................................ 98 2.6.4 Communication sequence of control transfer ............................................................ 99 2.6.5 Device state transition ................................................................................................ 102 2.6.6 Memory map of registers related to USB ................................................................ 103 2.6.7 Structure of USB control register .............................................................................. 104 2.6.8 Structure of USB address register ............................................................................ 105 2.6.9 Structure of USB power management register ....................................................... 106 2.6.10 Structure of USB interrupt status register 1 ......................................................... 107 2.6.11 Structure of USB interrupt status register 2 ......................................................... 108 2.6.12 Structure of USB interrupt enable register 1, USB interrupt enable register 2 109 2.6.13 Structure of USB endpoint index register .............................................................. 110 2.6.14 Structure of USB endpoint x IN control register .................................................. 115 2.6.15 Structure of USB endpoint x (x=1 to 2) OUT control register ........................... 117 2.6.16 Structure of USB endpoint x (x=0 to 2) IN max. packet size register .............. 118 2.6.17 Structure of USB endpoint x (x=0 to 2) OUT max. packet size register ......... 119 2.6.18 Structure of USB endpoint x (x=0 to 2) OUT write count register .................... 120 2.6.19 Structure of USB endpoint x (x=0 to 2) FIFO register ........................................ 121 2.6.20 Structure of USB endpoint FIFO mode register ................................................... 121 2.6.21 Structure of clock control register .......................................................................... 122 2.6.22 Structure of frequency synthesizer control register .............................................. 123 2.6.23 Frequency synthesizer connection and setting of division ratios ....................... 128 2.6.24 Registers setting (1) ................................................................................................. 129 2.6.25 Registers setting (2) ................................................................................................. 130 2.6.26 Registers setting (3) ................................................................................................. 131 2.6.27 Control procedure (1) (USB block initial setting) ................................................. 132 2.6.28 Control procedure (2) (USB block generating) ..................................................... 133 2.6.29 Control procedure (3) (endpoint initial setting) ..................................................... 134 2.6.30 Registers setting (1) (USB endpoint 1 transmit) .................................................. 135 2.6.31 Control procedure (USB endpoint 1 IN interrupt routine) ................................... 136 2.6.32 Registers setting (USB endpoint 1 OUT receive) ................................................ 137 2.6.33 Control procedure (USB endpoint 1 OUT interrupt routine) ............................... 138 2.6.34 Structure of SET_ADDRESS request ..................................................................... 139 2.6.35 Register setting (processing when SET_ADDRESS is received) ....................... 139 2.6.36 Control procedure ...................................................................................................... 140 2.6.37 Register setting (USB function interrupt routine) .................................................. 142 2.6.38 Control procedure (USB function interrupt routine) .............................................. 143 2.6.39 Register setting (USB suspend interrupt) .............................................................. 144 2.6.40 Control procedure (USB suspend interrupt routine) ............................................. 145 2.6.41 Register setting (USB resume interrupt) ................................................................ 146 2.6.42 Control procedure (USB resume interrupt routine) .............................................. 147 2.6.43 Connection diagram .................................................................................................. 148 2.6.44 Register setting (1) ................................................................................................... 149 2.6.45 Register setting (2) ................................................................................................... 150 2.6.46 Register setting (3) ................................................................................................... 151 2.6.47 Control procedure (1) ............................................................................................... 152 page 8 of 12 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 List of figures 7643 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.6.48 Control procedure (2) ............................................................................................... 153 2.6.49 Connection diagram .................................................................................................. 154 2.6.50 Register setting (1) ................................................................................................... 155 2.6.51 Register setting (2) ................................................................................................... 156 2.6.52 Register setting (3) ................................................................................................... 157 2.6.53 Register setting (4) ................................................................................................... 158 2.6.54 Control procedure (1) ............................................................................................... 159 2.6.55 Control procedure (2) ............................................................................................... 160 2.6.56 Electronic instrument application example ............................................................. 161 2.6.57 Encryption sytem application example ................................................................... 162 2.6.58 Peripheral circuit example ........................................................................................ 164 2.6.59 LPF peripheral circuit ............................................................................................... 164 2.6.60 Connection of insulation connector ........................................................................ 164 2.7.1 Memory map of registers related to frequency synthesizer .................................. 167 2.7.2 Structure of CPU mode register A ........................................................................... 168 2.7.3 Structure of Frequency synthesizer control register .............................................. 168 2.7.4 Structure of Frequency synthesizer multiply register 1 ......................................... 169 2.7.5 Structure of Frequency synthesizer multiply register 2 ......................................... 169 2.7.6 Structure of Frequency synthesizer divide register ................................................ 170 2.7.7 Block diagram for frequency synthesizer circuit ..................................................... 171 2.7.8 Frequency synthesizer multiply register 2 setting example .................................. 171 2.7.9 Frequency synthesizer multiply register 1 setting example .................................. 172 2.7.10 Frequency synthesizer divide register setting example ....................................... 172 2.8.1 Memory map of registers related to external devices connection ....................... 174 2.8.2 Structure of CPU mode register A ........................................................................... 175 2.8.3 Structure of CPU mode register B ........................................................................... 175 2.8.4 Software wait timing example .................................................................................... 177 2.8.5 RDY wait timing example ........................................................................................... 178 2.8.6 Extended RDY wait (software wait plus RDY input anytime wait) timing example ...... 179 2.8.7 Hold function timing diagram ..................................................................................... 180 2.8.8 Connection example of memory access up to 256 Kbytes .................................. 181 2.8.9 External ROM and RAM example ............................................................................. 182 2.8.10 RDY function use example ...................................................................................... 183 2.8.11 Read cycle (OE access, SRAM) ............................................................................. 184 2.8.12 Read cycle (OE access, EPROM) .......................................................................... 184 2.8.13 Write cycle (W control, SRAM) ............................................................................... 185 2.9.1 RAM backup system ................................................................................................... 188 2.10.1 Memory map of registers related to clock generating circuit ............................. 189 2.10.2 Structure of CPU mode register A ......................................................................... 190 2.10.3 Structure of Clock control register .......................................................................... 190 2.10.4 Structure of Frequency synthesizer control register ............................................ 191 2.10.5 Structure of Frequency synthesizer multiply register 1 ....................................... 191 2.10.6 Structure of Frequency synthesizer multiply register 2 ....................................... 192 2.10.7 Structure of Frequency synthesizer divide register .............................................. 192 2.10.8 Connection diagram .................................................................................................. 195 2.10.9 Status transition diagram during power failure ..................................................... 195 2.10.10 Setting of relevant registers .................................................................................. 196 2.10.11 Control procedure ................................................................................................... 197 2.10.12 Structure of clock counter ...................................................................................... 198 2.10.13 Initial setting of relevant registers ........................................................................ 199 2.10.14 Setting of relevant registers after detecting power failure ................................ 200 2.10.15 Control procedure (1) ............................................................................................. 201 2.10.16 Control procedure (2) ............................................................................................. 202 page 9 of 12 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 List of figures 7643 Group CHAPTER 3 APPENDIX Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.1.1 Circuit for measuring output switching characteristics (1) ...................................... 13 3.1.2 Circuit for measuring output switching characteristics (2) ...................................... 13 3.1.3 Timing diagram (1) ........................................................................................................ 14 3.1.4 Timing diagram (2) ........................................................................................................ 15 3.1.5 Timing diagram (3) ........................................................................................................ 15 3.1.6 Timing diagram (4); Memory expansion and microprocessor modes .................... 16 3.1.7 Timing diagram (5); Memory expansion and microprocessor modes .................... 17 3.2.1 Power source current standard characteristics (Ta = 25 ° C) ................................. 18 3.2.2 CMOS output port P-channel side characteristics (Ta = 25 ° C) ............................ 19 3.2.3 CMOS output port P-channel side characteristics (Ta = 70 ° C) ............................ 19 3.2.4 CMOS output port N-channel side characteristics (Ta = 25 ° C) ........................... 20 3.2.5 CMOS output port N-channel side characteristics (Ta = 70 ° C) ........................... 20 3.2.6 Port P2 0– P2 7 a t pull-up characteristics (Ta = 25 ° C) .............................................. 21 3.2.7 Port P2 0– P2 7 a t pull-up characteristics (Ta = 70 ° C) .............................................. 21 3.3.1 Sequence of setting external interrupt active edge ................................................. 22 3.3.2 Circuit example for the proper positions of the peripheral components ............... 28 3.3.3 Passive components near LPF pin ............................................................................. 28 3.3.4 Insulation connector connection .................................................................................. 28 3.3.5 Initialization of processor status register ................................................................... 35 3.3.6 Sequence of PLP instruction execution ..................................................................... 36 3.3.7 Stack memory contents after PHP instruction execution ........................................ 36 3.4.1 Wiring for the RESET pin ............................................................................................ 39 3.4.2 Wiring for clock I/O pins .............................................................................................. 39 3.4.3 Bypass capacitor across the Vss line and the Vcc line .......................................... 40 3.4.4 Wiring for a large current signal line ......................................................................... 41 3.4.5 Wiring for signal lines where potential levels change frequently ........................... 41 3.4.6 Vss pattern on the underside of an oscillator .......................................................... 42 3.4.7 Setup for I/O ports ........................................................................................................ 42 3.4.8 Watchdog timer by software ........................................................................................ 43 3.5.1 Structure of CPU mode register A ............................................................................. 44 3.5.2 Structure of CPU mode register B ............................................................................. 44 3.5.3 Structure of Interrupt request register A .................................................................... 45 3.5.4 Structure of Interrupt request register B .................................................................... 45 3.5.5 Structure of Interrupt request register C ................................................................... 46 3.5.6 Structure of Interrupt control register A ..................................................................... 46 3.5.7 Structure of Interrupt control register B ..................................................................... 47 3.5.8 Structure of Interrupt control register C ..................................................................... 47 3.5.9 Structure of Port Pi ....................................................................................................... 48 3.5.10 Structure of Port P4, Port P7 .................................................................................... 48 3.5.11 Structure of Port Pi direction register ...................................................................... 49 3.5.12 Structure of Port P4, Port P7 direction registers ................................................... 49 3.5.13 Structure of Port control register .............................................................................. 50 3.5.14 Structure of Interrupt polarity select register .......................................................... 50 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 10 of 12 List of figures 7643 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.5.15 3.5.16 3.5.17 3.5.18 3.5.19 3.5.20 3.5.21 3.5.22 3.5.23 3.5.24 3.5.25 3.5.26 3.5.27 3.5.28 3.5.29 3.5.30 3.5.31 3.5.32 3.5.33 3.5.34 3.5.35 3.5.36 3.5.37 3.5.38 3.5.39 3.5.40 3.5.41 3.5.42 3.5.43 3.5.44 3.5.45 3.5.46 3.5.47 3.5.48 3.5.49 3.5.50 3.5.51 3.5.52 3.5.53 3.5.54 3.5.55 Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure Structure of of of of of of of of of of of of of of of of of of of of of of of of of of of of of of of of of of of of of of of of of Port P2 pull-up control register ........................................................... 51 USB control register ............................................................................. 51 Clock control register ............................................................................ 52 Timer i .................................................................................................... 53 Timer 123 mode register ...................................................................... 53 Serial I/O shift register ......................................................................... 54 Serial I/O control register 1 ................................................................. 55 Serial I/O control register 2 ................................................................. 55 Timer UART mode register .................................................................. 56 UART baud rate generator .................................................................. 56 UART status regiseter .......................................................................... 57 UART control register ........................................................................... 57 UART transmit/receive buffer registers 1, 2 ...................................... 58 UART RTS control register .................................................................. 59 DMAC index and status register ......................................................... 60 DMAC channel x mode register 1 (x = 0, 1) .................................... 61 DMAC channel 0 mode register 2 ...................................................... 62 DMAC channel 1 mode register 2 ...................................................... 63 DMAC channel x source registers Low, High ................................... 64 DMAC channel x destination registers Low, High ............................ 64 DMAC channel x transfer count registers Low, High (x = 0, 1) .... 65 USB address register ........................................................................... 66 USB power management register ....................................................... 67 USB interrupt status register 1 ........................................................... 68 USB interrupt status register 2 ........................................................... 69 USB interrupt enable register 1 .......................................................... 70 USB interrupt enable register 2 .......................................................... 70 USB endpoint index register ................................................................ 71 USB endpoint x IN control register .................................................... 72 USB endpoint x OUT control register (x = 1, 2) .............................. 73 USB endpoint x IN max. packet size register (x = 0 to 2) ............ 74 USB endpoint x OUT max. packet size register (x = 0 to 2) ........ 74 USB endpoint x OUT write control register (x = 0 to 2) ................ 75 USB endpoint FIFO mode register ..................................................... 75 USB endpoint x FIFO register (x = 0 to 2) ....................................... 76 Flash memory control register ............................................................. 77 Frequency synthesizer control register .............................................. 78 Frequency synthesizer multiply register 1 ......................................... 78 Frequency synthesizer multiply register 2 ......................................... 79 Frequency synthesizer divide register ................................................ 80 ROM code protect control register ..................................................... 81 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 11 of 12 List of tables 7643 Group List of tables CHAPTER 1 HARDWARE Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 1 Pin description (1) ............................................................................................................ 5 2 Pin description (2) ............................................................................................................ 6 3 Support products ............................................................................................................... 8 4 Push and pop instructions of accumulator or processor status register ................ 10 5 Set and clear instructions of each bit of processor status register ........................ 11 6 List of I/O port function .................................................................................................. 16 7 Interrupt vector addresses and priority ........................................................................ 22 8 Port functions in memory expansion mode and microprocessor mode .................... 65 9 Summary of M37643F8 (flash memory version) ........................................................ 71 10 List of software commands (CPU rewrite mode) ..................................................... 76 11 Definition of each bit in status register (SRD) ......................................................... 78 12 Description of pin function (Standard Serial I/O Mode) .......................................... 84 13 Software commands (Standard serial I/O mode) ..................................................... 87 14 Definition of each bit of status register (SRD) ......................................................... 94 15 Bits of which state might be changed owing to software write ............................. 99 CHAPTER 2 APPLICATION Table 2.1.1 Termination of unused pins ........................................................................................ 9 Table 2.4.1 Setting examples of baud rate generator values and transfer bit rate values (f = 12 MHz) ........................................................................................................................................................... 46 Table 2.4.3 Error flags set condition and how to clear error flags ......................................... 48 Table 2.5.1 Address directions and examples of transfer result (1) ....................................... 86 Table 2.5.2 Address directions and examples of transfer result (2) ....................................... 87 Table 2.5.3 Priority to use bus ..................................................................................................... 88 Table 2.6.1 USB PID list ................................................................................................................ 98 Table 2.6.2 IN FIFO States ......................................................................................................... 125 Table 2.6.3 Bits of which state might be changed owing to software write ....................... 166 Table 2.10.2 State in Wait mode ................................................................................................ 194 CHAPTER 3 APPENDIX Table Table Table Table Table Table Table Table Table Table Table Table Absolute maximum ratings ........................................................................................ 2 Recommended operating conditions ........................................................................ 3 Electrical characteristics (1) ...................................................................................... 4 Electrical characteristics (2) ...................................................................................... 5 Timing requirements ................................................................................................... 6 Timing requirements and switching characteristics in memory expansion and microprocessor modes ............................................................................................... 7 3.1.7 Recommended operating conditions ........................................................................ 8 3.1.8 Electrical characteristics (1) ...................................................................................... 9 3.1.9 Electrical characteristics (2) .................................................................................... 10 3.1.10 Timing requirements ............................................................................................... 11 3.1.11 Timing requirements and switching characteristics in memory expansion and microprocessor modes ............................................................................................. 12 3.3.1 Bits of which state might be changed owing to software write ......................... 30 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 12 of 12 T HIS PAGE IS BLANK FOR REASONS OF LAYOUT. CHAPTER 1 OVERVIEW DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION FUNCTIONAL BLOCK PIN DESCRIPTION PART NUMBERING GROUP EXPANSION FUNCTIONAL DESCRIPION FLASH MEMORY MODE NOTES ON PROGRAMMING USAGE NOTES DATA REQUIRED FOR MASK ORDERS FUNCTIONAL DESCRIPTION SUPPLEMENT OVERVIEW 7643 Group DESCRIPTION/FEATURES/APPLICATION DESCRIPTION The 7643 group is the 8-bit microcomputer based on the 7600 series core (740 family core compatible) technology. The 7643 group is designed for PC peripheral devices, including the USB, DMAC, Serial I/O, UART, Timer and so on. q Power source voltage At 24 MHz oscillation frequency, φ = 12 MHz ......... 4.15 to 5.25 V At 24 MHz oscillation frequency, φ = 6 MHz ........... 3.00 to 3.60 V q Program/Erase voltage .................................. VCC = 4.50 V to 5.25 V, or 3.00 V to 3.60 V .................................................................. VPP = 4.50 V to 5.25 V At 24 MHz oscillation frequency, φ = 6 MHz (See Table 20.) q Memory size Flash ROM .................................................................... 32 Kbytes RAM ............................................................................. 2.5 Kbytes qFlash memory mode ....................................................... 3 modes Parallel I/O mode Standard serial I/O mode CPU rewrite mode q Programming method ....................... Programming in unit of byte q Erasing method Batch erasing Block erasing q Program/Erase control by software command qCommand number ................................................... 6 commands q Number of times for programming/erasing ............................. 100 qROM code protection Available in parallel I/O mode and standard serial I/O mode q Operating temperature range (at programming/erasing) .............. ...................................................................... Normal temperature FEATURES (a half of IN FIFO), this condition never occurs. When IN_PKT_RDY = “1” and TX_NOT_EPT = “1”, IN FIFO holds two packets in double buffer mode and one packet in single packet mode. In single packet mode, when the IN_PKT_RDY bit is set to “1” by software, the TX_NOT_EPT flag is set to “1” as well. During double buffer mode, if you want to load two packets sequentially, you must set the IN_PKT_RDY bit to “1” each time a packet is loaded. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 43 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION USB Reception Endpoint 0 to Endpoint 2 have OUT (receive) FIFOs individually. Each endpoint’s FIFO is configured in following way: Endpoint 0: 16-byte Endpoint 1: 128-byte Endpoint 2: Mode 0: 32-byte Mode 1: 128-byte When Endpoint 2 is used for data receive, the OUT FIFO size can be selected. Endpoint 2 have 2 modes programmable IN-FIFO. Each mode can be selected by the USB endpoint FIFO mode selection register (address 005F16). Data transmitted from the host-PC is stored in Endpoint x FIFO (006016 to 006216). Every time the data is stored in the FIFO, the internal OUT FIFO write pointer is increased by 1. When one complete data packet is stored, the OUT_PKT_RDY flag is set to “1” and the number of received data packets is stored in USB Endpoint x OUT write count register. When the AUTO_CLR bit is “1” and the received data is read out from the OUT FIFO, the OUT_PKT_RDY flag is cleared to “0”. When the AUTO_CLR bit is “1”, the OUT_PKT_RDY flag will not be cleared automatically by the FIFO read; it must be cleared by software. (The AUTO-CLR bit function is not applicable in Endpoint 0.) When MAXP size ≤ (a half of OUT FIFO size), the OUT_FIFO can receive 2 packets (double buffer). At this time, the OUT_ FIFO status can be checked by the OUT_PKT_RDY flag. When the FIFO holds two packets and one packet is read from the FIFO, the OUT_PKT_RDY flag is not cleared even if it is set to “0”. (The flag returns from “0” to “1” in one φ cycle after the read-out). During double buffer mode, the USB Endpoint x OUT write count register holds the number of previously received packets. This count register is updated after reading out one of packets in the OUT FIFO and clearing the OUT_PKT_RDY flag to “0”. TOGGLE Initialization In order to initialize the data toggle sequence bit of the endpoint, in other words, resetting the next data packet to DATA0; set the TOGGLE_INT bit to “1” and then clear back to “0”. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 44 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION USB Interrupts The USB FCU has USB Function Interrupt. qUSB Function Interrupt (USBF-INT) The USBF-INT is usable for the USB data flow control and power management. The USBF-INT request occurs at data transmit/receive completion, overrun/underrun, reset, or receiving suspend/ resume signal. To enable this interrupt, the USB function interrupt enable bit in the interrupt control register A (address 000516) and the respective bit in the USB interrupt enable registers 1 and 2 (addresses 0005416 and 0005516) must be set to “1”. When setting bit 7 in USB interrupt enable register 2 to “1”, the suspend interrupt and the resume interrupt are enabled. Endpoint x (x = 0 to 2) IN interrupt request occurs when the USB Endpoint x IN interrupt status flag (INTST 0, 2, 4) of USB interrupt status registers 1 and 2 (addresses 005216 and 005316) is “1”. The USB Endpoint x IN interrupt status flag is set to “1” when the respective endpoint IN_PKT_RDY bit is “1”. Endpoint x (x = 0 to 2) OUT interrupt request occurs when the USB endpoint x OUT interrupt status flag (INTST3, 5) in USB interrupt status registers 1 and 2 is set to “1”. The USB Endpoint x OUT interrupt status flag is set to “1” when the respective endpoint OUT_PKT_RDY flag is “1”. The USB reset interrupt request occurs when the USB reset interrupt status flag (INTST13) in USB interrupt status register 2 is set to “1”. This flag is set when the SE0 is detected on the D+/D- line for at least 2.5 µs. When this situation happens, all USB internal registers (addresses 005016 to 005F16), except this flag, are initialized to the default state at reset. The USB reset interrupt is always enabled. The suspend/resume interrupt request occurs when either the USB resume signal interrupt status flag (INTST14) or the USB suspend signal interrupt status flag (INTST15) in USB interrupt status register 2 is set to “1”. The bits in both interrupt status registers 1 and 2 can be cleared by writing “1” to each bit. (2) Set the USB clock enable bit to “0”. (After disabling the USB clock, do not write to any of the USB internal registers (addresses 005016 to 006216), except for the USB control register (address 001316), clock control register (address 001F16), and frequency synthesizer control register (address 006C16). (3) Set the frequency synthesizer enable bit to “0”. (4) Set the USB line driver current control bit to “1”. (Always keep the USB line driver current control bit set to “0” during USB function operations. When operating at Vcc = 3.3 V, this bit does not need to be set.) (5) Keep total drive current at 500 µA or less. (6) Disable the timer 1 interrupt. (7) Disable the timer 2 interrupt. (Disable all the other external interrupts.) (8) Set the timer 1 interrupt request bit to “0”. (9) Set the timer 2 interrupt request bit to “0”. (10) Set the interrupt disable flag (I) to “0”. (11) Execute the STP instruction. At this point, the MCU will be in stop mode (suspend mode). Before executing the STP instruction, make sure to set the USB function interrupt request bit (bit 0 at address 000216) to “0” and the USB function interrupt enable bit (bit 0 at address 000516) to “1”. The USB suspend detect signal flag goes to “0” when the USB resume signal detect flag (RESUME) is set to “1”. During suspend mode, if the clock operation is started up with a process (remote wake-up) other than the resume interrupt process (for example; reset or timer), make sure to clear the USB suspend detect signal flag to “0” when you set the USB remote wake-up bit to “1”. When the USB FCU is in suspend mode and detects a non-idle signal on the D+/D- line, the USB resume detect flag and the USB resume signal interrupt status flag both go to “1” and a resume interrupt request occurs. At this point, pull the internal registers (A, X, Y) in this interrupt process routine. Take the following procedure in the USB resume interrupt process. (1) Set the USB line driver current control bit to “0”. (When operating at Vcc = 3.3 V, this bit does not need to be set.) (2) Set the frequency synthesizer enable bit to “1” and set a 2 ms wait or more . (3) Check the frequency synthesizer lock status bit. If “0”, it must be checked again after a 0.1 ms wait. (4) Set the USB clock enable bit to “1”. Suspend/Resume Functions If no bus activity is detected on the D+/D- line for at least 3 ms, the USB suspend signal detect flag (SUSPEND) of the USB power control register (address 005116) and the USB suspend signal interrupt status flag of USB interrupt status register 2 are set to “1” and the suspend interrupt request occurs. The following procedure must be executed after pushing the internal registers (A, X, Y ) to memories during the suspend interrupt process routine. (1) Clear all bits of USB interrupt status register 1 (address 005216) and USB interrupt status register 2 (address 005316) to “0”. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 45 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION Set the USB resume signal interrupt status flag to “0” after the wake-up sequence process. The USB resume detect flag goes to “0” at the same time. When the clock operation is started up with a remote wake-up, set the USB remote wake-up bit to “1” after the wake-up sequence process. (keep it set to “1” for a minimum of 10 ms and maximum of 15 ms). By doing this, the MCU will send a resume signal to the host CPU and let it know that the suspend state has been released. After that, set the USB remote wake-up bit and the USB suspend detection flag to “0”, because the USB suspend detection flag is not automatically cleared to “0” with a remote wake-up. [USB Control Register] USBC When using the USB function, the USB enable bit must be set to “1”. The USB line driver supply bit must be set to “0” (DC-DC converter is disabled) when operating at Vcc = 3.3V. In this condition, the setting of the USB line driver current control bit has no effect on USB operations. b7 b0 0 0 0 USB control register (address 001316) USBC Reserved bit (“0” at read/write) USB default state selection bit (USBC1) 0: In default state after power-on/reset 1: In default state after USB reset signal received (Note 1) Reserved bit (“0” at read/write) USB line driver current control bit (USBC3) 0: High current mode 1: Low current mode USB line driver supply enable bit (USBC4) (Note 2) 0: Line driver disabled 1: Line driver enabled USB clock enable bit (USBC5) 0: 48 MHz clock to the USB block disabled 1: 48 MHz clock to the USB block enabled Reserved bit (“0” at read/write) USB enable bit (USBC7) 0: USB block disabled (Note 3) 1: USB block enabled Notes 1: Without regard to this bit, USB internal registers (address 005016 to 005F16) go into the states at reset (default) at the same time when USB reset is detected. 2: When using the MCU in Vcc = 3.3 V, set this bit to “0” and disable the built-in DC-DC converter 3: Setting this bit to 0” causes the contents of all USB registers to have the values at reset. Fig. 35 Structure of USB control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 46 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION [USB Address Register] USBA The USB address register maintains the USB function control unit address assigned by the host computer. When receiving the SET_ADDRESS, keep it in this register. The values of this register are “0” when the device is not yet configured. The values of this register are also set to “0” when the USB block is disabled (bit 7 of USB control register is set to “ 0 ” ). In addition, no matter what value is written to this register, it will have no effect on the set value. b7 b0 0 USB address register (address 005016) USBA Programmable function address (FUNAD0 to 6)) This register maintains the 7-bit USB function control unit address assigned by the host CPU. Reserved bit (“0” at read/write) Fig. 36 Structure of USB address register [USB Power Management Register] USBPM The USB power management register is used for power management in the USB FCU. This register needs to be set only when using the remote wake-up to resume the MCU from suspend mode. b7 b0 00000 USB power management register (address 005116) USBPM USB suspend detection flag (SUSPEND) (Read only) 0: No USB suspend detected 1: USB suspend detected USB resume detection flag (RESUME) (Read only) 0: No USB resume signa detected 1: USB resume signal detected USB remote wake-up bit (WAKEUP) 0: End of remote resume signal 1: Transmitting of remote resume signal (only when SUSPEND = “1”) Reserved bit (“0” at read/write) Fig. 37 Structure of USB power management register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 47 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION [USB Interrupt Status Registers 1 and 2] USBIS1, USBIS2 The USB interrupt status registers are used to indicate the condition that caused a USB function interrupt to be generated. Each status flag and bit can be cleared to “0” by writing “1” to the corresponding bit. Make sure to write to/read from the USB interrupt status register 1 first and then USB interrupt status register 2. b7 b0 00 0 USB interrupt status register 1 (address 005216) USBIS1 USB endpoint 0 interrupt status flag (INTST0) 0: Except the following conditions 1: Set at any one of the following conditions: • A packet data of endpoint 0 is successfully received • A packet data of endpoint 0 is successfully sent • DATA_END bit of endpoint 0 is cleared to “0” • FORCE_STALL bit of endpoint 0 is set to “1” • SETUP_END bit of endpoint 0 is set to “1”. Reserved bit (“0” at read/write) USB endpoint 1 IN interrupt status flag (INTST2) 0: Except the following condition 1: Set at which of the following condition: • A packet data of endpoint 1 is successfully sent USB endpoint 1 OUT interrupt status flag (INTST3) 0: Except the following conditions 1: Set at any one of the following conditions: • A packet data of endpoint 1 is successfully received • FORCE_STALL bit of endpoint 1 is set to “1”. USB endpoint 2 IN interrupt status flag (INTST4) 0: Except the following condition 1: Set at which of the following condition: • A packet data of endpoint 2 is successfully sent USB endpoint 2 OUT interrupt status flag (INTST5) 0: Except the following conditions 1: Set at any one of the following conditions: • A packet data of endpoint 2 is successfully received • FORCE_STALL bit of endpoint 2 is set to “1”. Reserved bit (“0” at read/write) Reserved bit (“0” at read/write) Fig. 38 Structure of USB interrupt status register 1 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 48 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION b7 b0 0 0 0 0 0 USB interrupt status register 2 (address 005316) USBIS2 Reserved bit (“0” at read/write) USB reset interrupt status flag (INTST13) 0: Except the following condition 1: Set at receiving of USB reset signal USB resume signal interrupt status flag (INTST14) 0: Except the following condition 1: Set at receiving of resume signal USB suspend signal interrupt status flag (INTST15) 0: Except the following condition 1: Set at receiving of suspend signal Fig. 39 Structure of USB interrupt status register 2 [USB Interrupt Enable Registers 1 and 2] USBIE1, USBIE2 The USB interrupt enable registers are used to enable the USB function interrupt. Upon reset, all USB interrupts except the USB suspend and USB resume interrupts are enabled. b7 b0 ✕✕ 0 USB interrupt enable register 1 (address 005416) USBIE1 USB endpoint 0 interrupt enable bit (INTEN0) 0: Disabled 1: Enabled Reserved bit (“0” at read/write) USB endpoint 1 IN interrupt enable bit (INTEN2) 0: Disabled 1: Enabled USB endpoint 1 OUT interrupt enable bit (INTEN3) 0: Disabled 1: Enabled USB endpoint 2 IN interrupt enable bit (INTEN4) 0: Disabled 1: Enabled USB endpoint 2 OUT interrupt enable bit (INTEN5) 0: Disabled 1: Enabled Reserved bit (Undefined at read/“0” at write) Fig. 40 Structure of USB interrupt enable register 1 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 49 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION b7 b0 0 1 ✕ 0 0 ✕ ✕ USB interrupt enable register 2 (address 005516) USBIE2 Reserved bit (Undefined at read/“0” at write) Reserved bit (“0” at read/write) Reserved bit (Undefined at read/“0” at write) Reserved bit (“1” at read/write) Reserved bit (“0” at read/write) USB suspend/resume interrupt enable bit (INTEN15) 0: Disabled 1: Enabled Fig. 41 Structure of USB interrupt enable register 2 [USB Endpoint Index Register] USBINDEX This register specifies the accessible endpoint. It serves as an index to endpoint-specific USB Endpoint x IN Control Register, USB Endpoint x OUT Control Register, USB Endpoint x IN Max. Packet Size Register, USB Endpoint x OUT Max. Packet Size Register, USB Endpoint x OUT Write Count Register, and USB FIFO Mode Selection Register (x = 0 to 2). b7 b0 00000 USB endpoint index register (address 005816) USBINDEX Endpoint index bit (EPINDEX) (Note) b2b1b0 0 0 0: Endpoint 0 0 0 1: Endpoint 1 0 1 0: Endpoint 2 0 1 1: Not used 1 0 0: Not used 1 0 1: Not used 1 1 0: Not used 1 1 1: Not used Reserved bit (“0” at read/write) Note: Do not set Endpoint except Endpoint 0, 1 and 2. Fig. 42 Structure of USB frame number registers Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 50 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION [USB Endpoint 0 IN Control Register ] IN_CSR This register contains the control and status information of the endpoint 0. This USB FCU sets the OUT_PKT_RDY flag to “1” upon having received a data packet in the OUT FIFO. When reading its one data packet from the OUT FIFO, be sure to set this flag to “0”. After a SETUP token is received, the MCU is in the “decode wait state ” u ntil the OUT_PKT_RDY flag is cleared. If the OUT_PKT_RDY flag is not cleared (indicating that the host request has not been successfully decoded), the USB FCU keep returning a NAK to the host for all IN/OUT tokens. Set the IN_PKT_RDY bit to “ 1 ” a fter the data packet has been written to the IN FIFO. If this bit is set to “1” even though nothing has been written to the IN FIFO, a “0” length data (NULL packet) is sent to the host. The SEND_STALL bit is for sending a STALL to the host if an unsupported request is received by the USB FCU. This bit must be set to “1”. When the OUT_PKT_RDY flag is set to “0” for request reception, the USB FCU transmits a STALL signal to the Host CPU. Perform the following three processes simultaneously: • Set SEND_STALL bit to “1” • Set DATA_END bit to “1” • Set OUT_PKT_RDY flag to “0” by setting SERVICED_OUT _PKT_RDY bit to “1”. Note that if “ 0 ” i s written to the SEND_STALL bit before the CLEAR_FEATURE (endpoint STALL) request has been received, the next STALL will not be generated. The DATA_END bit informs the USB FCU of the completion of the process indicated in the SETUP packet. Set this bit to “1” when the process requested in the SETUP packet is completed. (Control Read Transfer: set this bit after writing all of the requested data to the FIFO; Control Write Transfer: set this bit to “1” after reading all of the requested data from the FIFO.) When this bit is “1”, the host request is ignored and a STALL is returned. After the status phase process is completed, the USB FCU automatically clears it to “0”. b7 b0 USB endpoint 0 IN control register (address 005916) IN_CSR OUT_PKT_RDY flag (IN0CSR0) 0: Except the following condition (Cleared to “0” by writing “1” into SERVICED_OUT_PKT_RDY bit) 1: End of a data packet reception IN_PKT_RDY bit (IN0CSR1) 0: End of a data packet transmission 1: Write “1” at completion of writing a data packet into IN FIFO. SEND_STALL bit (IN0CSR2) 0: Except the following condition 1: Transmitting STALL handshake signal DATA_END bit (IN0CSR3) 0: Except the following condition (Cleared to “0” after completion of status phase) 1: Write “1” at completion of writing or reading the last data packet to/from FIFO. FORCE_STALL flag (IN0CSR4) 0: Except the following condition 1: Protocol error detected SETUP_END flag (IN0CSR5) (Note ) 0: Except the following condition (Cleared to “0” by writing “1” into SERVICED_SETUP_END bit) 1: Control transfer ends before the specific length of data is transferred during the data phase. SERVICED_OUT_PKT_RDY bit (IN0CSR6) Writing “1” to this bit clears OUT_PKT_RDY flag to “0”. SERVICED_SETUP_END bit (IN0CSR7) Writing “1” to this bit clears SETUP_END flag to “0”. Note: If this bit is set to “0”, stop accessing the FIFO to serve the previous setup transaction. Fig. 43 Structure of USB endpoint 0 IN control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 51 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION [USB Endpoint x (x = 1, 2) IN Control Register] IN_CSR This register contains the control and status information of the respective IN Endpoints 1, 2. Set the IN_PKT_RDY bit to “ 1 ” a fter the data packet has been written to the IN FIFO. This bit is cleared to “ 0 ” w hen the data transfer is completed. In a bulk IN transfer, this bit is cleared when an ACK signal is received from the host. If an ACK signal is not received, this bit (and the TX_NOT_EMPTY bit) remains as “1”. This same data packet is sent after the next IN token is received. The FLUSH bit is for flushing the data in the IN FIFO. b7 b0 0 USB endpoint x IN control register (address 005916) IN_CSR INT_PKT_RDY bit (INXCSR0) 0: End of a data packet transmission (Note 1) 1: Write “1” at completion of writing a data packet into IN FIFO. (Note 3) Reserved bit (“0” at read/write) SEND_STALL bit (INXCSR2) (Note 2) 0: Except the following condition 1: Transmitting STALL handshake signal TOGGLE_INIT bit (INXCSR3) (Note 2) 0: Except the following condition 1: Initializing the data toggle sequence bit INTPT bit (INXCSR4) (Note 2) 0: Except the following condition 1: Initializing to endpoint used for interrupt transfer, rate feedback TX_NOT_EPT flag (INXCSR5) (Note 1) 0: Empty in IN FIFO 1: Full in IN FIFO FLUSH bit (INXCSR6) 0: Except the following condition (Note 4) 1: Flush FIFO. (Note 4) AUTO_SET bit (INXCSR7) (Note 2) 0: AUTO_SET disabled 1: AUTO_SET enabled (Note 5) Notes 1: This bit is automatically set to “1” or cleared to “0”. 2: The user must program to “1” or “0”. 3: When AUTO_SET bit is “0”, the user must set to “1”. When AUTO_SET bit is “1”, this bit is automatically set to “1”. 4: This bit is automatically cleared to “0” after setting “1”. 5: To use the AUTO_SET function for an IN transfer when the AUTO_SET bit is set to “1”, set the FIFO to single buffer mode. Fig. 44 Structure of USB endpoint x (x = 1, 2) IN control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 52 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION [USB Endpoint x (x = 1, 2) OUT Control Register] OUT_CSR This register contains the information and status of the respective OUT endpoints 1, 2. In the endpoint 0, all bits are reserved and cannot be used (they will all be read out as “0”). The USB FCU sets the OUT_PKT_RDY flag to “1” after a data packet has been received into the OUT FIFO. After reading the data packet in the OUT FIFO, clear this flag to “0”. However, if there is still data in the OUT FIFO, the flag cannot be cleared even by writing “0” by software. b7 b0 0 0 USB endpoint x OUT control register (address 005A16) OUT_CSR OUT_PKT_RDY flag (OUTXCSR0) 0: Except the following condition (Note 3) 1: End of a data packet reception (Note 2) Reserved bit (“0” at read/write) SEND_STALL bit (OUTXCSR2) (Note 2) 0: Except the following condition 1: Transmitting STALL handshake signal TOGGLE_INIT bit (OUTXCSR3) (Note 2) 0: Except the following condition 1: Initializing the data toggle sequence bit FORCE_STALL flag (OUTXCSR4) 0: Except the following condition (Note 2) 1: Protocol error detected (Note 1) Reserved bit (“0” at read/write) FLUSH bit (OUTXCSR6) 0: Except the following condition (Note 4) 1: Flush FIFO. (Note 4) AUTO_CLR bit (OUTXCSR7) (Note 2) 0: AUTO_CLR disabled 1: AUTO_CLR enabled Notes 1: This bit is automatically set to “1” or cleared to “0”. 2: The user must program to “1” or “0”. 3: When AUTO_SET bit is “0”, the user must set to “1”. When AUTO_SET bit is “1”, this bit is automatically set to “1”. 4: This bit is automatically cleared to “0” after setting “1”. Fig. 45 Structure of USB endpoint x (x = 1, 2) OUT control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 53 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION [USB Endpoint x (x = 0 to 2) IN Max. Packet Size Register] IN_MAXP This register specifies the maximum packet size (MAXP) of an endpoint x IN packet. The value set for endpoint 1 is the number of transmitted bytes divided by 8, and the value set for endpoints 0 and 2 is the actual number of transmitted bytes. The CPU can change these values using the SET_DESCRIPTOR command. The initial value for endpoints 0 and 2 is 8, and the initial value for endpoint 1 is 1. [USB Endpoint x (x = 0 to 2) OUT Max. Packet Size Register] OUT_MAXP This register specifies the maximum packet size (MAXP) of an Endpoint x OUT packet. The value set for endpoint 1 is the number of received bytes divided by 8, and the value set for endpoints 0 and 2 is the actual number of received bytes. The CPU can change these values using the SET_DESCRIPTOR command. The initial value for endpoints 0 and 2 is 8, and the initial value for endpoint 1 is 1. When using the endpoint 0, both USB endpoint x IN max. packet size register (IN _MAXP) and USB endpoint x OUT max. packet size register (OUT_MAXP) are set to the same value. Changing one register ’s value effectively changes the value of the other register as well. b7 b0 USB endpoint x IN max. packet size register (address 005B16) IN_MAXP The maximum packet size (MAXP) of endpoint x IN is contained. MAXP = n for endpoints 0, 2 MAXP = n ✕ 8 for endpoint 1 “n” is a written value into this register. Fig. 46 Structure of USB endpoint x IN max. packet size register b7 b0 USB endpoint x OUT max. packet size register (address 005C16) OUT_MAXP The maximum packet size (MAXP) of endpoint x OUT is contained. MAXP = n for endpoints 0, 2 MAXP = n ✕ 8 for endpoint 1 “n” is a written value into this register. Fig. 47 Structure of USB endpoint x OUT max. packet size register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 54 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION [USB endpoint x (x = 0 to 2) OUT Write Count Registers] WRT_CNTR This register contain the number of bytes in the endpoint x OUT FIFO. This is read-only register. This register must be read after the USB FCU has received a packet of data from the host. When the OUT FIF0 is in double buffer mode, the CPU first reads the received number of bytes of the former data packet. The next CPU read can obtain that of the new data packet. b7 b0 USB endpoint x OUT write count register (address 005D16) WRT_CNT The number of bytes in endpoint x OUT FIFO Fig. 48 Structure of USB endpoint x (x = 0 to 2) OUT write count registers [USB Endpoint x (x = 0 to 2) FIFO Register] USBFIFOx These registers are the USB IN (transmit) and OUT (receive) FIFO data registers. Write data to the corresponding register, and read data from the corresponding register. When the maximum packet size is equal to or less than half the FIFO size, these registers function in double buffer mode and can hold two packets of data. When the IN_PKT_RDY bit is “0” and the TX_NOT_EMPTY bit is “1”, these bits indicate that one packet of data is stored in the IN FIFO. When the OUT FIFO is in double buffer mode, the OUT_PKT_RDY flag remains as “1” after the first packet of data is read out (it actually goes to “0” and returns to “1” after one φ cycle). b7 b0 USB endpoint x FIFO register (addresses 006016, 006116, 006216) USBFIFOx Endpoint x IN/OUT FIFO Fig. 49 Structure of USB endpoint x (x = 0 to 2) FIFO register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 55 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION [USB Endpoint FIFO Mode Selection Register] USBFIFOMR This register determines IN/OUT FIFO size mode for endpoint 1 or endpoint 2. b7 b0 USB endpoint FIFO mode register (address 005F16) USBFIFOMR FIFO size selection bit (Note) For endpoint 1 b3b2b1b0 X 0 0 0: IN 128-byte, OUT 128-byte For endpoint 2 0 X X X : IN 32-byte, OUT 32-byte 1 X X X : IN 128-byte, OUT 128-byte Reserved bit Note: The value set into “x” is invalid. Fig. 50 Structure of USB endpoint FIFO mode register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 56 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION FREQUENCY SYNTHESIZER (PLL) The frequency synthesizer generates the 48 MHz clock required by fUSB and fSYN, which are multiples of the external input reference f(XIN). Figure 51 shows the block diagram for the frequency synthesizer circuit. The Frequency Synthesizer Input Bit selects either f(X IN ) or f(XCIN) as an input clock fIN for the frequency synthesizer. The Frequency Synthesizer Multiply Register 2 (FSM2: address 006E16) divides fIN to generate fPIN, where fPIN = fIN / 2(n + 1), n: value set to FSM2. When the value of Frequency Synthesizer Multiply Register 2 is set to 255, the division is not performed and fPIN will equal fIN. fVCO is generated according to the contents of Frequency Synthesizer Multiply Register 1 (FSM1: address 006D16), where fVCO = fPIN ✕ {2(n + 1)}, n: value set to FSM1. Set the value of FSM1 so that the value of fVCO is 48 MHz. fSYN is generated according to the contents of the Frequency Synthesizer Divide Register (FSD: address 006F16), where fSYN = fVCO / 2(m + 1), m: value set to FSD. When the value of the Frequency Synthesizer Divide Register is set to 255, the division is not performed and fSYN becomes invalid. [Frequency Synthesizer Control Register] FSC Setting the Frequency Synthesizer Enable Bit (FSE) to “1” enables the frequency synthesizer. When the Frequency Synthesizer Lock Status Bit (LS) is “1” in the frequency synthesizer enabled, this indicates that fSYN and fVCO have correct frequencies. sNotes Make sure to connect a low-pulse filter to the LPF pin when using the frequency synthesizer. In addition, please refer to “Programming Notes: Frequency Synthesizer ” w hen recovering from a Hardware Reset. fVCO fIN Prescaler fPIN Frequency Multiplier Frequency Divider fSYN fUSB FSM2 (address 006E16) FSM1 (address 006D16) Frequency synthesizer lock status bit FSC (address 006C16) FSD (address 006F16) Data Bus Fig. 51 Frequency synthesizer block diagram Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 57 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION b7 b0 0 00 Frequency synthesizer control register (address 006C16) FSC Frequency synthesizer enable bit (FSE) 0: Disabled 1: Enabled Fix to “00”. Frequency synthesizer input bit (FIN) 0: f(XIN) 1: f(XCIN) Reserved bit (“0” at read/write) LPF current control (CHG1, CHG0) (Note) b6b5 0 0: Not available 0 1: Low current 1 0: Intermediate current (recommended) 1 1: High current Frequency synthesizer lock status bit 0: Unlocked 1: Locked Note: Bits 6 and 5 are set to (bit 6, bit 5) = (1, 1) at reset. When using the frequency synthesizer, we recommend to set to (bit 6, bit 5) = (1, 0) after locking the frequency synthesizer. Fig. 52 Structure of frequency synthesizer control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 58 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an “L” level for 20 cycles or more of φ. Then the RESET pin is returned to an “H” level, and reset is released. They must be performed when the power source voltages are between 3.00 V and 3.60 V or 4.15 V and 5.25 V. After the reset is completed, the program starts from the address contained in address FFFA 16 ( high-order byte) and address FFFB16 (low-order byte). After oscillation has restarted, the timers 1 and 2 secures waiting time for the internal clock φ oscillation stabilized automatically by setting the timer 1 to “FF16 ” and timer 2 to “01 16”. The internal clock φ retains “H” level until Timer 2’s underflow and it cannot be supplied until the underflow. The pins state during reset are follows: •When CNVss = “H” : Outputting Ports P0, P1, P33 to P37 Pins other than above mentioned ports : Inputting •When CNVss = “L” All pins : Inputting. Poweron RESET VCC Power source voltage 0V Reset input voltage 0V (Note) 0.2VCC Note : Reset release voltage ; Vcc = 3.00 or 4.15 V RESET VCC Power source voltage detection circuit Fig. 53 Reset circuit example φ RESET Internal reset Address ? ? ? ? FFFA FFFB ADH,L Reset address from the vector table. Data ? ? ? ? ADL ADH SYNC XIN: 512 clock cycles Notes: The question marks (?) indicate an undefined state that depends on the previous state. Fig. 54 Reset sequence Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 59 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION Address Register contents (1) (2) (3) (4) (5) (6) (7) (8) (9) CPU mode register A (CPUA) CPU mode register B (CPUB) Interrupt request register A (IREQA) Interrupt request register B (IREQB) Interrupt request register C (IREQC) Interrupt control register A (ICONA) Interrupt control register B (ICONB) Interrupt control register C (ICONC) Address Register contents (39) UART status register (USTS) (40) UART control register (UCON) (41) UART RTS control register (URTSC) (42) DMAC index and status register (DMAIS) (43) DMAC channel x mode register 1 (DMAx1) (44) DMAC channel x mode register 2 (DMAx2) (45) DMAC channel x source register Low (DMAxSL) (46) DMAC channel x source register High (DMAxSH) (47) DMAC channel x destination register Low (DMAxDL) (48) DMAC channel x destination register High (DMAxDH) 003216 0 0 0 0 0 0 1 1 003316 0016 000016 0 0 0 0 1 1 0 0 000116 1 0 0 0 0 0 1 1 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001F16 002416 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 FF16 003616 1 0 0 0 0 0 0 0 003F16 004016 004116 004216 004316 004416 004516 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 Port P0 (P0) (10) Port P0 direction register (P0D) (11) Port P1 (P1) (12) Port P1 direction register (P1D) (13) Port P2 (P2) (14) Port P2 direction register (P2D) (15) Port P3 (P3) (16) Port P3 direction register (P3D) (17) Port control register (PTC) (18) Interrupt polarity select register (IPOL) (19) Port P2 pull-up control register (PUP2) (20) USB control register (USBC) (21) Port P6 (P6) (22) Port P6 direction register (P6D) (23) Port P5 (P5) (24) Port P5 direction register (P5D) (25) Port P4 (P4) (26) Port P4 direction register (P4D) (27) Port P7 (P7) (28) Port P7 direction register (P7D) (29) Port P8 (P8) (30) Port P8 direction register (P8D) (31) Clock control register (CCR) (32) Timer 1 (T1) (33) Timer 2 (T2) (34) Timer 3 (T3) (35) Timer 123 mode register (T123M) (36) Serial I/O control register 1 (SIOCON1) (37) Serial I/O control register 2 (SIOCON2) (38) UART mode register (UMOD) (49) DMAC channel x transfer count register Low (DMAxCL) 004616 (50) DMAC channel x transfer count register High (DMAxCH) 004716 (51) USB address register (USBA) 005016 (52) USB power management register (USBPM) 005116 (53) USB interrupt status register 1 (USBIS1) (54) USB interrupt status register 2 (USBIS2) (55) USB interrupt enable register 1 (USBIE1) (56) USB interrupt enable register 2 (USBIE2) (57) USB endpoint index register (USBINDEX) 005216 005316 005416 ✕ ✕ 1 1 1 1 1 1 005516 0 0 1 ✕ 0 0 ✕ ✕ 005816 0016 0016 0016 (58) USB endpoint x IN control register (IN_CSR) 005916 (59) USB endpoint x OUT control register (OUT_CSR) (Note 1) (Note 1) 005A16 (60) USB endpoint x IN max. packet size register (IN_MAXP) 005B16 0 0 0 0 1 0 0 0 (61) USB endpoint x OUT max. packet size register (OUT_MAXP) 005C16 0 0 0 0 1 0 0 0 (62) USB endpoint x OUT write count register (WRT_CNT) 005D16 005F16 0016 0016 (63) USB endpoint FIFO mode register (USBFIFOMR) (64) Flash memory control register (FMCR) (Note 3) 006A16 0 0 0 0 0 0 0 1 006C16 0 1 1 0 0 0 0 0 006D16 006E16 006F16 FFC916 (PS) (PCH) (PCL) FF16 FF16 FF16 FF16 ✕✕✕✕✕ 1 ✕✕ FFFB16 contents FFFA16 contents (65) Frequency synthesizer control register (FSC) (66) Frequency synthesizer multiply register 1 (FSM1) (67) Frequency synthesizer multiply register 2 (FSM2) (68) Frequency synthesizer divide register (FSM2) (69) ROM code protect control register (ROMCP) (Note 3) (70) Processor status register (71) Program counter 002516 0 0 0 0 0 0 0 1 002616 002916 FF16 0016 002B16 0 1 0 0 0 0 0 0 002C16 0 0 0 1 1 0 0 0 003016 0016 X : Not fixed Notes 1: When using the endpoint 0or endpoint 2, this contents are “0816”. When using the endpoint 1, this contents are “0116”. 2: Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. 3: The flash memory control register and the ROM code protect control register exists in the flash memory version only. Fig. 55 Internal status at reset Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 60 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION CLOCK GENERATING CIRCUIT The 7643 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer ’s recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. (An external feed-back resistor may be needed depenging on conditions.) However, an external feed-back resistor is needed between XCIN and XCOUT. When using an external clock, input the clocks to the XIN or XCIN pin and leave the XOUT or XCOUT pin open. Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. XCIN Rf XCOUT Rd CCOUT XIN XOUT Rd (Note) CCIN CIN COUT Frequency Control The internal system clock can be selected among f SYN, f(XIN), f(XIN)/2, and f(XCIN). The internal clock φ is half the frequency of internal system clock. (1) fSYN clock This is made by the frequency synthesizer. f(XIN) or f(XCIN) can be selected as its input clock. See also section “FREQUENCY SYNTHESIZER”. Notes : Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feedback resistor between XIN and XOUT following the instruction. (2) f(XIN) clock The frequency of internal system clock is the frequency of XIN pin. Fig. 56 Ceramic resonator or quartz-crystal oscillator external circuit (3) f(XIN)/2 clock The frequency of internal system clock is half the frequency of XIN pin. (4) f(XCIN) clock The frequency of internal system clock is the frequency of XCIN pin. XCIN XCOUT Open XIN XOUT Open sNote If you switch the oscillation between XIN - XOUT and XCIN - XCOUT, stabilize both XIN and XCIN oscillations. The sufficient time is required for the XCIN oscillation to stabilize, especially immediately after power on and at returning from the stop mode. External oscillation circuit VCC VSS External oscillation circuit VCC VSS Fig. 57 External clock input circuit Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 61 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION (5) Low power dissipation mode • The low power dissipation operation can be realized by stopping the main clock X IN w hen using f(X CIN) as the internal system clock. To stop the main clock, set the Main Clock (X IN-X OUT) Stop Bit of the CPU mode register A to “1”. • The low power dissipation operation can be realized by disabling the reversed amplifier when inputting external clocks to the XIN pin or XCIN pin. To disable the reversed amplifier, set the XCOUT Oscillation Drive Disable Bit (CCR5) or XOUT Oscillation Drive Disable Bit (CCR6) of the clock control register to “1”. (2) Wait mode If the WIT instruction is executed, the internal clock φ stops at “H” level, but the oscillator does not stop. The internal clock φ restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the internal clock φ is restarted. Set the Interrupt Enable Bit to be used to release the wait mode to enabled (“1”) and the Interrupt Disable Flag (I) to “0”. Oscillation Control (1) Stop mode If the STP instruction is executed, the internal clock φ stops at “H” level, and XIN and XCIN oscillators stop. Then the timer 1 is set to “FF16” and the internal clock φ divided by 8 is automatically selected as its count source. Additionally, the timer 2 is set to “0116” and the timer 1 ’s output is automatically selected as its count source. Set the Timer 1 and Timer 2 Interrupt Enable Bits to disabled (“0”) before executing the STP instruction. When using an external interrupt to release the stop mode, set the Interrupt Enable Bit to be used to enabled (“1”) and the Interrupt Disable Flag (I) to “0”. Oscillator restarts at reset or when an external interrupt including USB resume interrupts is received, but the internal clock φ r emains at “H” until the timer 2 underflows. The internal clock φ is supplied for the first time when the timer 2 underflows. Therefore make sure not to set the Timer 1 Interrupt Request Bit and Timer 2 Interrupt Request Bit to “1” before the STP instruction stops the oscillator. b7 b0 00000 Clock control register (address 001F16) CCR Reserved bits (“0” at read/write) Fix to “0”. XCOUT oscillation drive disable bit (CCR5) 0: XCOUT oscillation drive is enabled. (When XCIN oscillation is enabled.) 1: XCOUT oscillation drive is disabled. XOUT oscillation drive disable bit (CCR6) 0: XOUT oscillation drive is enabled. (When XIN oscillation is enabled.) 1: XOUT oscillation drive is disabled. XIN divider select bit (CCR7) Valid when CPMA6, CPMA7 = “00” 0: f(XIN)/2 is used for the system clock. 1: f(XIN) is used for the system clock. Fig. 58 Structure of clock control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 62 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION P1HATRSTB P2LATRSTB DQ PIN1 DQ PIN2 DQ PIN1 DQ P2+ RQ S PIN1 DQ T DQ RESET T R TR T R TR RESET P2+ STP instruction P2LATRSTB P2 peripheral P1 peripheral P2 peripheral T Oscillator count-down timer 1 to 2 STP instruction RQ RQ STP instruction DQ T S S P1HATRSTB P1 peripheral RQ WI T instruction PIN2 DQ T P2 out SQ R Internal clock φ Interrupt request Interrupt disable flag l RESET S P1 out S Delay R QB P2+ P2LATRSTB STP instruction DQ T P2 OSCSTP XOSCSTP Main clock (XIN-XOUT) stop bit P1 P1HATRSTB XCOSCSTP XOD Sub-clock (XCIN-XCOUT) stop bit PIN1, PIN2 XCOD Slow memory wait select bit Slow memory wait mode select bit RDY XIN drive select bit External clock select bit f(XIN) f(XCIN) XDOSCSTP XCDOSCSTP Slow memory wait P1+, P2+ LPF XOSCSTP 1/2 LPF XCOSCSTP fEXT Frequency synthesizer input bit fIN fSYN Internal system clock select bit Main clock (XIN-XOUT) stop bit Sub-clock (XCIN-XCOUT) stop bit 1/2 USB 48 MHz clock output Frequency synthesizer Frequency synthesizer LPF enable bit XIN XOUT XCIN XCOUT Fig. 59 Clock generating circuit block diagram Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 63 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION Reset (Note 2) φ = f(XIN/4) (Note 3) XIN clock oscillating, XCIN clock stopped, Frequency synthesizer clock stopped, CPMA = 0C, FSC = 60 φ = f(XIN/4) (Note 3) φ = f(PLL)/2 STOP WAIT FSC0 “0”←→“1” XIN clock oscillating, XCIN clock stopped, Frequency synthesizer clock oscillating, (Note 4) CPMA = 0C, FSC = 41 CPMA6 “0”←→“1” XIN clock oscillating, XCIN clock stopped, Frequency synthesizer clock oscillating, CPMA = 4C, FSC = 41 WAIT CPMA4 “1”←→“0” φ = f(XIN/4) (Note 3) XIN clock oscillating, XCIN clock oscillating, Frequency synthesizer clock stopped, CPMA = 1C, FSC = 60 (Note 2) STOP WAIT FSC0 “0”←→“1” φ = f(XIN/4) (Note 3) XIN clock oscillating, XCIN clock oscillating, Frequency synthesizer clock oscillating, (Note 4) CPMA = 1C, FSC = 41 CPMA6 “0”←→“1” φ = f(PLL)/2 XIN clock oscillating, XCIN clock oscillating, Frequency synthesizer clock oscillating, CPMA = 5C, FSC = 41 WAIT CPMA7 “1”←→“0” φ = f(XCIN/2) XIN clock oscillating, XCIN clock oscillating, Frequency synthesizer clock stopped, CPMA = 9C, FSC = 60 (Note 2) STOP WAIT FSC0 “0”←→“1” φ = f(XCIN/2) XIN clock oscillating, XCIN clock oscillating, Frequency synthesizer clock oscillating, (Note 4) CPMA = 9C, FSC = 41 CPMA6 “0”←→“1” φ = f(PLL)/2 XIN clock oscillating, XCIN clock oscillating, Frequency synthesizer clock oscillating, CPMA = DC, FSC = 41 WAIT CPMA5 “1”←→“0” φ = f(XCIN/2) (Note 5) (Note 2) STOP WAIT XIN clock stopped, XCIN clock oscillating, Frequency synthesizer clock stopped, CPMA = BC, FSC = 68 FSC0 “0”←→“1” φ = f(XCIN/2) XIN clock stopped, XCIN clock oscillating, Frequency synthesizer clock oscillating, (Note 4) CPMA = BC, FSC = 49 CPMA6 “0”←→“1” φ = f(PLL)/2 XIN clock stopped, XCIN clock oscillating, Frequency synthesizer clock oscillating, CPMA = FC, FSC = 49 WAIT Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2 : In Stop mode, though the frequency synthesizer is not automatically disabled, the oscillator which sends clocks to the frequency synthesizer stops. Set the system clock and disable the frequency synthesizer before execution of the STP instruction. 3 : φ = f(XIN)/2 can be also used by setting the XIN divider select bit (CCR7) to “1”. Then this diagram also applies to that case. 4 : The frequency synthesizer’s input can be selected between XIN input and XCIN input regardless of the system clock. This diagram assumes the frequency synthesizer’s input to be the system clock. Enable the oscillator to be used for the frequency synthesizer’s input before enabling the frequency synthesizer. 5 : Select the XCIN input as the frequency synthesizer’s input by setting the frequency synthesizer input bit (FSC3) to “1” before stopping XIN oscillation. Remarks : This diagram assumes that: •Stack page is page 1 •In single-chip mode (Depending on the CPU mode register A) •φ expresses the internal clock. Fig. 60 State transitions of clock Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 64 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION PROCESSOR MODE Single-chip mode, memory expansion mode, and microprocessor mode which is only in the mask ROM version can be selected by using the Processor Mode Bits of CPU mode register A (bits 0 and 1 of address 000016). In the memory expansion mode and microprocessor mode, a memory can be expanded externally via ports P0 to P3. In these modes, ports P0 to P3 lose their I/O port functions and become bus pins. The port direction registers corresponding to those ports become external memory areas. M37643M8 000016 000816 001016 007016 Internal RAM SFR area 000016 000816 001016 007016 SFR area SFR area SFR area Internal RAM Table 8 Port functions in memory expansion mode and microprocessor mode Port Name Port P0 Port P1 Port P2 Port P3 Function Outputs low-order 8 bits of address. Outputs high-order 8 bits of address. Operates as I/O pins for data D7 to D0 (including instruction code). P30 is the RDY input pin. P31 and P32 function only as output pins P33 is the DMAOUT output pin. P34 is the φOUT output pin. P35 is the SYNCOUT output pin. P36 is the WR output pin, and P37 is the RD output pin. P40 is the EDMA pin. 047016 047016 800016 Internal ROM FFFF16 FFFF16 Memory expansion mode Microprocessor mode The shaded areas are external areas. Port P4 (1) Single-chip mode Select this mode by resetting the MCU with CNVSS connected to VSS. M37643F8 000016 SFR area (2) Memory expansion mode Select this mode by setting the Processor Mode Bits (b1, b0) to “01” in software with CNVSS connected to VSS. This mode enables external memory expansion while maintaining the validity of the internal ROM. 000816 001016 007016 Internal RAM SFR area (3) Microprocessor mode Select this mode by resetting the MCU with CNVSS connected to VCC, or by setting the Processor Mode Bits (b1, b0) to “10” in software with CNVSS connected to VSS. In the microprocessor mode, the internal ROM is no longer valid and an external memory must be used. Do not set this mode in the flash memory version. 0A7016 100016 Reserved area 800016 Internal ROM FFFF16 Memory expansion mode The shaded areas are external areas. Fig. 61 Memory maps in processor modes other than singlechip mode Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 65 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION b7 b0 1 CPU mode register A (address 000016) CPMA Processor mode bits b1b0 0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Microprocessor mode (Note 1) 1 1: Not available Stack page select bit 0: Page 0 1: Page 1 Fix to “1”. Sub-clock (XCIN-XCOUT) control bit 0: Stopped 1: Oscillating Main clock (XIN-XOUT) control bit 0: Oscillating 1: Stopped Internal system clock select bit (Note 2) 0: External clock (XIN-XOUT or XCIN-XCOUT) 1: fSYN External clock select bit 0: XIN-XOUT 1: XCIN-XCOUT Notes 1: This is not available in the flash memory version. 2: When (CPMA 6, 7) = (0, 0), the internal system clock can be selected between f(XIN) or f(XIN)/2 by CCR7. The internal clock φ is the internal system clock divided by 2. Fig. 62 Structure of CPU mode register A b7 b0 10 CPU mode register B (address 000116) CPMB Slow memory wait select bits b1b0 0 0: No wait 0 1: One-time wait 1 0: Two-time wait 1 1: Three-time wait Slow memory wait mode select bits b3b2 0 0: Software wait 0 1: Not available 1 0: RDY wait 1 1: Software wait plus RDY input anytime wait Expanded data memory access bit 0: EDMA output disabled 1: EDMA output enabled HOLD function enable bit 0: HOLD function disabled 1: HOLD function enabled Reserved bit (“0” at read/write) Fix to “1”. Fig. 63 Structure of CPU mode register B Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 66 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION Slow Memory Wait The 7643 Group is equipped with the slow memory wait function (Software wait, RDY wait, and Extended RDY wait: software wait plus RDY input anytime wait) for easier interfacing with external devices that have long access times. The slow memory wait function can be enabled in the memory expansion mode and microprocessor mode. The appropriate wait mode is selected by setting bits 0 to 3 of CPU mode register B (address 000116). This function can extend the read cycle or write cycle only for access to an external memory. However, this wait function cannot be enabled for access to addresses 000816 to 000F16. (2) RDY wait RDY Wait is selected by setting “ 10 ” t o the Slow Memory Wait Mode Select Bits of CPU mode register B (address 000116). When a fixed time of “L” is input to the RDY pin at the beginning of a read/write cycle (before φ cycle falls), the MCU goes to the RDY state. The read/write cycle can then be extended by one to three φ cycles. The number of φ cycles to be added can be selected by the Slow Memory Wait Bits. (3) Software wait + Extended RDY wait Extended RDY Wait is selected by setting “ 11 ” t o the Slow Memory Wait Mode Select Bits of CPU mode register B (address 000116). The read/write cycle can be extended when a fixed time of “L” is input to the RDY pin at the beginning of a read/write cycle (before φ cycle falls). The RDY pin state is checked continually at each fall of φ cycle until the RDY pin goes to “H”. When “H” is input to the RDY pin, the wait is released within 1, 2, or 3 φ cycles (as selected with the Slow Memory Wait Bits). (1) Software wait The software wait is selected by setting “00” to the Slow Memory Wait Mode Select Bits of CPU mode register B (address 000116). Read/write cycles (“L” width of RD pin/WR pin) can be extended by one to three φ cycles. The number of cycles to be extended can be selected with the Slow Memory Wait Select Bits. When the software wait function is selected, the RDY pin status becomes invalid. XIN φ OUT ADOUT RD WR No wait CPMB = 0016 1-cycle software wait CPMB = 0116 2-cycle software wait CPMB = 0216 3-cycle software wait CPMB = 0316 Note: This diagram assumes φ = XIN/2. Fig. 64 Software wait timing diagram XIN φ OUT ADOUT RD WR RDY No wait CPMB = 0816 1-cycle RDY wait CPMB = 0916 2-cycle RDY wait CPMB = 0A16 3-cycle RDY wait CPMB = 0B16 tsu tsu tsu tsu tsu tsu Note: This diagram assumes φ = XIN/2. Fig. 65 RDY wait timing diagram Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 67 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION XIN φOUT ADOUT RD WR tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu RDY No wait CPMB = 0C16 1-cycle extended RDY wait CPMB = 0D16 2-cycle extended RDY wait CPMB = 0E16 XIN φOUT ADOUT RD WR tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu RDY 2-cycle extended RDY wait CPMB = 0E16 3-cycle extended RDY wait CPMB = 0F16 Note: This diagram assumes φ = XIN/2. Fig. 66 Extended RDY wait (software wait plus RDY input anytime wait) timing diagram Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 68 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION HOLD Function The HOLD function is used for systems that consist of external circuits that access MCU buses without use of the CPU (Central Processing Unit). The HOLD function is used to generate the timing in which the MCU will relinquish the bus from the CPU to the external circuits. To use the HOLD function, set the HOLD function Enable Bit of CPU mode register B (address 000116) to “1”. This function can be used with both the HOLD pin and the HLDA pin. The HOLD signal is a signal from an external circuit requesting the MCU to relinquish use of the bus. When “L” level is input, the MCU goes to the HOLD state and remains so while the pin is at “L”. The oscillator does not stop oscillating during the HOLD state, therefore allowing the internal peripheral functions to operate during this time. When the MCU relinquishes use of the bus, “L” level is output from the HLDA pin. The MCU makes ports P0 and P1 (address buses) and port P2 (data bus) tri-state outputs and holds port P37 (RD pin) and port P36 (WR pin) “H” level. Port P34 (φ OUT pin) continues to oscillate. This function is not valid when the MCU is using the IBF1 function with the HLDA pin. Expanded Data Memory Access In Expanded Data Memory Access Mode, the MCU can access a data area larger than 64 Kbytes with the LDA ($zz), Y (indirect Y) instruction and the STA ($zz), Y (indirect Y) instruction. To use this mode, set the Expanded Data Memory Access Bit of CPU mode register B (address 000116) to “1”. In this case, port P40 (EDMA pin) goes “L” level during the read/write cycle of the LDA or STA instruction. The determination of which bank to access is done by using an I/ O port to represent expanded addresses exceeding address bus AB15. For example, when accessing 4 banks, use two I/O ports to represent address buses AB16 and AB17. XI N φ OUT RD, W R ADDROUT DATAIN/OUT tsu(HOLD-φ) HOLD HLDA td(φ-HLDAL) td(φ-HLDAH) th(φ-HOLD) Note: This diagram assumes φ = XIN/2. Fig. 67 Hold function timing diagram Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 69 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION φ SYNCOUT RD WR Address Data EDMA PC PC +1 Op code BAL, 00 BAL BAL+1, 00 ADL + Y, ADH ADL + Y, ADH + C PC + 2 Next Op code ADL ADH Invalid Data Fig. 68 STA ($ zz), Y instruction sequence when EDMA enabled φ SYNCOUT RD WR Address Data EDMA PC PC +1 Op code BAL, 00 BAL BAL+1, 00 ADL + Y, ADH ADL + Y, ADH + C PC + 2 Next Op code ADL ADH Invalid Data Fig. 69 LDA ($ zz), Y instruction sequence when EDMA enabled and T flag = “0” φ SYNCOUT RD WR Address Data EDMA Fig. 70 LDA ($ zz), Y instruction sequence when EDMA enabled and T flag = “1” PC PC +1 Op code BAL, 00 BAL BAL+1, 00 ADL + Y, ADH ADL + Y, ADH + C X, 00 Invalid PC + 2 Data Next Op code ADL ADH Invalid Data Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 70 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE FLASH MEMORY MODE The M37643F8FP/HP (flash memory version) has an internal new DINOR (DIvided bit line NOR) flash memory that can be rewritten with a single power source when VCC is 5 V, and 2 power sources when VPP is 5 V and VCC is 3.3 V in the CPU rewrite and standard serial I/O modes. For this flash memory, three flash memory modes are available in which to read, program, and erase: the parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and the CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). Summary Table 9 lists the summary of the M37643F8 (flash memory version). This flash memory version has some blocks on the flash memory as shown in Figure 71 and each block can be erased. The flash memory is divided into User ROM area and Boot ROM area. In addition to the ordinary User ROM area to store the MCU operation control program, the flash memory has a Boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user ’s application system. This Boot ROM area can be rewritten in only parallel I/O mode. Table 9 Summary of M37643F8 (flash memory version) Item Power source voltage (For Program/Erase) VPP voltage (For Program/Erase) Flash memory mode Specifications Vcc = 3.00 – 3.60 V, 4.50 – 5.25 V (f(XIN) = 24 MHz, φ = 6 MHz) (Note 1) VPP = 4.50 – 5.25 V 3 modes; Flash memory can be manipulated as follows: (1) CPU rewrite mode: Manipulated by the Central Processing Unit (CPU) (2) Parallel I/O mode: Manipulated using an external programmer (Note 2) (3) Standard serial I/O mode: Manipulated using an external programmer (Note 2). Erase block division User ROM area Boot ROM area See Figure 71. 1 block (4 Kbytes) (Note 3) Byte program Batch erasing/Block erasing Program/Erase control by software command 6 commands 100 times Available in parallel I/O mode and standard serial I/O mode Program method Erase method Program/Erase control method Number of commands Number of program/Erase times ROM code protection Notes 1: After programming/erasing at Vcc = 3.0 to 3.6 V, the MCU can operate only at Vcc = 3.0 to 3.6 V. After programming/erasing at Vcc = 4.5 to 5.25 V or programming/erasing with the exclusive external equipment flash programmer, the MCU can operate at both Vcc = 3.0 to 3.6 V and 4.15 to 5.25 V. 2: In the parallel I/O mode or the standard serial I/O mode, use the exclusive external equipment flash programmer which supports the 7643 Group (flash memory version). 3: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be rewritten in only parallel I/O mode. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 71 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE (1) CPU Rewrite Mode In CPU rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the User ROM area shown in Figure 71 can be rewritten; the Boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the User ROM area and each block area. The control program for CPU rewrite mode can be stored in either User ROM or Boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to internal RAM area to be executed before it can be executed. Microcomputer Mode and Boot Mode The control program for CPU rewrite mode must be written into the User ROM or Boot ROM area in parallel I/O mode beforehand. (If the control program is written into the Boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 71 for details about the Boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNV SS pin low. In this case, the CPU starts operating using the control program in the User ROM area. When the microcomputer is reset by pulling the P36 (CE) pin high, the P81 (SCLK) pin high, the CNVSS pin high, the CPU starts operating using the control program in the Boot ROM area. This mode is called the “Boot” mode. Block Address Block addresses refer to the maximum address of each block. These addresses are used in the block erase command. Parallel I/O mode User ROM area 800016 Block 2 : 16 Kbytes C00016 E00016 FFFF16 Block 1 : 8 Kbytes Block 0 : 8 Kbytes BSEL = “L” F00016 FFFF16 Boot ROM area 4 Kbytes BSEL = “H” CPU rewrite mode, standard serial I/O mode User ROM area 800016 Block 2 : 16 Kbytes C00016 E00016 FFFF16 Block 1 : 8 Kbytes Block 0 : 8 Kbytes F00016 FFFF16 Boot ROM area 4 Kbytes User area / Boot area select bit = “0” User area / Boot area select bit = “1” Notes 1: The Boot ROM area can be rewritten in only parallel I/O mode. (Access to any other areas is inhibited.) 2: To specify a block, use the maximum address in the block. Fig. 71 Block diagram of built-in flash memory Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 72 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE Outline Performance (CPU Rewrite Mode) CPU rewrite mode is usable in the single-chip, memory expansion or Boot mode. The only User ROM area can be rewritten in CPU rewrite mode. In CPU rewrite mode, the CPU erases, programs and reads the internal flash memory by executing software commands. This rewrite control program must be transferred to a memory such as the internal RAM before it can be executed. The MCU enters CPU rewrite mode by applying 4.50 V to 5.25 V to the CNVSS pin and setting “1” to the CPU Rewrite Mode Select Bit (bit 1 of address 006A16). Software commands are accepted once the mode is entered. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Figure 72 shows the flash memory control register. Bit 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase operations, it is “0” (busy). Otherwise, it is “1” (ready). Bit 1 is the CPU Rewrite Mode Select Bit. When this bit is set to “1”, the MCU enters CPU rewrite mode. Software commands are accepted once the mode is entered. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly. Therefore, use the control program in a memory other than internal flash memory for write to bit 1. To set this bit to “ 1 ” , it is necessary to write “0” and then write “1” in succession. The bit can be set to “0” by only writing “0”. Bit 2 is the CPU Rewrite Mode Entry Flag. This flag indicates “1” in CPU rewrite mode, so that reading this flag can check whether CPU rewrite mode has been entered or not. Bit 3 is the flash memory reset bit used to reset the control circuit of internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU Rewrite Mode Select Bit is “1”, setting “1” for this bit resets the control circuit. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession. To release the reset, it is necessary to set this bit to “0”. Bit 4 is the User Area/Boot Area Select Bit. When this bit is set to “1”, Boot ROM area is accessed, and CPU rewrite mode in Boot ROM area is available. In Boot mode, this bit is set to “1” automatically. Reprogramming of this bit must be in a memory other than internal flash memory. Figure 73 shows a flowchart for setting/releasing CPU rewrite mode. b7 b0 Flash memory control register (address 006A16) (Note 1) FMCR RY/BY status flag 0: Busy (being programmed or erased) 1: Ready CPU rewrite mode select bit (Note 2) 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) CPU rewrite mode entry flag 0: Normal mode 1: CPU rewrite mode Flash memory reset bit (Note 3) 0: Normal operation 1: Reset User ROM area / Boot ROM area select bit (Note 4) 0: User ROM area accessed 1: Boot ROM area accessed Reserved bits (Indefinite at read/ “0” at write) Notes 1: The contents of flash memory control register are “XXX00001” just after reset release. 2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. If it is not this procedure, this bit will not be set to ”1”. Additionally, it is required to ensure that no interrupt will be generated during that interval. Use the control program in the area except the built-in flash memory for write to this bit. 3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently after setting bit 3 to “1”. 4: Use the control program in the area except the built-in flash memory for write to this bit. Fig. 72 Structure of flash memory control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 73 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE Start Single-chip mode, Memory expansion mode or Boot mode Set CPU mode registers A, B (Note 2) Transfer CPU rewrite mode control program to memory other than internal flash memory Jump to control program transferred in memory other than internal flash memory (Subsequent operations are executed by control program in this memory) Setting Set CPU rewrite mode select bit to “1” (by writing “0” and then “1” in succession) Check CPU rewrite mode entry flag Using software command execute erase, program, or other operation Execute read array command or reset flash memory by setting flash memory reset bit (by writing “1” and then “0” in succession) (Note 3) Released Write “0” to CPU rewrite mode select bit End Notes 1: When starting the MCU in the single-chip mode or memory expansion mode, supply 4.5 V to 5.25 V to the CNVss pin until checking the CPU rewrite mode entry flag. 2: Set the main clock as follows depending on the XIN divider select bit of clock control register (bit 7 of address 001F16): When XIN divider select bit = “0” (φ = f(XIN)/4), the main clock is 24 MHz or less When XIN divider select bit = “1” (φ = f(XIN)/2), the main clock is 12 MHz or less. 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute the read array command or reset the flash memory. Fig. 73 CPU rewrite mode set/release flowchart Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 74 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE Notes on CPU Rewrite Mode The below notes applies when rewriting the flash memory in CPU rewrite mode. qOperation speed During CPU rewrite mode, set the internal clock φ to 6 MHz or less using the XIN Divider Select Bit (bit 7 of address 001F16). qInstructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during CPU rewrite mode . qInterrupts inhibited against use The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. qReset Reset is always valid. When CNVSS is “H” at reset release, the program starts from the address stored in addresses FFFA16 and FFFB16 of the boot ROM area in order that CPU may start in boot mode. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 75 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE Software Commands (CPU Rewrite Mode) Table 10 lists the software commands. After setting the CPU Rewrite Mode Select Bit of the flash memory control register to “1”, execute a software command to specify an erase or program operation. Each software command is explained below. qRead Array Command (FF16) The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the contents of the specified address are read out at the data bus (DB0 to DB7). The read array mode is retained intact until another command is written. qRead Status Register Command (7016) The read status register mode is entered by writing the command code “7016” in the first bus cycle. The contents of the status register are read out at the data bus (DB0 t o DB 7) by a read in the second bus cycle. The status register is explained in the next section. qClear Status Register Command (5016) This command is used to clear the bits SR4 and SR5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code “5016” in the first bus cycle. qProgram Command (4016) Program operation starts when the command code “4016” is written in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and verification) will start. Whether the write operation is completed can be confirmed by _____ reading the status register or the RY/BY Status Flag of the flash memory control register. When the program starts, the read status register mode is entered automatically and the contents of the status register is read at the data bus (DB 0 t o DB 7 ). The status register bit 7 (SR7) is set to “0” at the same time the write operation starts and is returned to “ 1 ” u pon completion of the write operation. In this case, the read status register mode remains active until the next command is written. ____ The RY/BY Status Flag is “0” (busy) during write operation and “1” (ready) when the write operation is completed as is the status register bit 7. At program end, program results can be checked by reading bit 4 (SR4) of the status register. Start Write 4016 Write Write address Write data Status register read SR7 = 1 ? or RY/BY = 1 ? YES NO S R4 = 0 ? YES Program completed NO Program error Fig. 74 Program flowchart Table 10 List of software commands (CPU rewrite mode) Command Read array Read status register Clear status register Program Erase all blocks Block erase Cycle number 1 2 1 2 2 2 Mode Write Write Write Write Write Write First bus cycle Data Address (DB0 to DB7) X (Note 4) Second bus cycle Data Mode Address (DB0 to DB7) FF16 7016 5016 4016 2016 2016 Write Write Write BA WA (Note 2) X (Note 3) X X X X X Read X SRD (Note 1) WD (Note 2) 2016 D016 Notes 1: SRD = Status Register Data 2: WA = Write Address, WD = Write Data 3: BA = Block Address to be erased (Input the maximum address of each block.) 4: X denotes a given address in the User ROM area . Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 76 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE qErase All Blocks Command (2016/2016) By writing the command code “2016” in the first bus cycle and the confirmation command code “2016” in the second bus cycle that follows, the operation of erase all blocks (erase and erase verify) starts. Whether the erase all blocks command is terminated can be con____ firmed by reading the status register or the RY/BY Status Flag of flash memory control register. When the erase all blocks operation starts, the read status register mode is entered automatically and the contents of the status register can be read out at the data bus (DB0 to DB 7). The status register bit 7 (SR7) is set to “0” at the same time the erase operation starts and is returned to “1” upon completion of the erase operation. In this case, the read status register mode remains active until another command is written. ____ The RY/BY Status Flag is “0” during erase operation and “1” when the erase operation is completed as is the status register bit 7 (SR7). After the erase all blocks end, erase results can be checked by reading bit 5 (SRS) of the status register. For details, refer to the section where the status register is detailed. qBlock Erase Command (2016/D016) By writing the command code “2016” in the first bus cycle and the confirmation command code “D016” and the blobk address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. Whether the block erase operation is completed can be confirmed ____ by reading the status register or the RY/BY Status Flag of flash memory control register. At the same time the block erase operation starts, the read status register mode is automatically entered, so that the contents of the status register can be read out. The status register bit 7 (SR7) is set to “0” at the same time the block erase operation starts and is returned to “1” upon completion of the block erase operation. In this case, the read status register mode remains active until the read array command (FF16) is written. ____ The RY/BY Status Flag is “0” during block erase operation and “1” when the block erase operation is completed as is the status register bit 7. After the block erase ends, erase results can be checked by reading bit 5 (SRS) of the status register. For details, refer to the section where the status register is detailed. Start Write 2016 Write 2016/D016 Block address 2016:Erase all blocks command D016:Block erase command Status register read SR7 = 1 ? or RY/BY = 1 ? NO YES NO SR5 = 0 ? Erase error YES Erase completed Fig. 75 Erase flowchart Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 77 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE Status Register (SRD) The status register shows the operating status of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways: (1) By reading an arbitrary address from the User ROM area after writing the read status register command (7016) (2) By reading an arbitrary address from the User ROM area in the period from when the program starts or erase operation starts to when the read array command (FF16) is input. Also, the status register can be cleared by writing the clear status register command (5016). After reset, the status register is set to “8016”. Table 11 shows the status register. Each bit in this register is explained below. •Sequencer status (SR7) The sequencer status indicates the operating status of the flash memory. This bit is set to “0” (busy) during write or erase operation and is set to “1” when these operations ends. After power-on, the sequencer status is set to “1” (ready). •Erase status (SR5) The erase status indicates the operating status of erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”. •Program status (SR4) The program status indicates the operating status of write operation. When a write error occurs, it is set to “1”. The program status is set to “0” when it is cleared. If “ 1 ” i s written for any of the SR5 and SR4 bits, the program, erase all blocks, and block erase commands are not accepted. Before executing these commands, execute the clear status register command (5016) and clear the status register. Also, if any commands are not correct, both SR5 and SR4 are set to “1”. Table 11 Definition of each bit in status register (SRD) Symbol SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved Definition “1” Ready Terminated in error Terminated in error - “0” Busy Terminated normally Terminated normally - Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 78 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE Full Status Check By performing full status check, it is possible to know the execution results of erase and program operations. Figure 76 shows a full status check flowchart and the action to be taken when each error occurs. Read status register SR4 = 1 and SR5 = 1 ? NO SR5 = 0 ? YES SR4 = 0 ? YES YES Command sequence error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should an erase error occur, the block in error cannot be used. NO Erase error NO Program error Should a program error occur, the block in error cannot be used. End (erase, program) Note: When one of SR5 and SR4 is set to “1”, none of the read aray, the program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands. Fig. 76 Full status check flowchart and remedial procedure for errors Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 79 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of internal flash memory from being read out or rewritten easily, this MCU incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode. qROM Code Protect Function (in Pararell I/O Mode) The ROM code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the ROM code protect control (address FFC916 ) in parallel I/O mode. Figure 77 shows the ROM code protect control (address FFC916). (This address exists in the User ROM area.) If one or both of the pair of ROM Code Protect Bits is set to “0”, the ROM code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. The ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default. If both of the two ROM Code Protect Reset Bits are set to “00”, the ROM code protect is turned off, so that the contents of internal flash memory can be read out or modified. Once the ROM code protect is turned on, the contents of the ROM Code Protect Reset Bits cannot be modified in parallel I/O mode. Use the serial I/O or CPU rewrite mode to rewrite the contents of the ROM Code Protect Reset Bits. b7 b0 1 1 ROM code protect control (address FFC916) (Note 1) ROMCP Reserved bits (“1” at read/write) ROM code protect level 2 set bits (ROMCP2) (Notes 2, 3) b3b2 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled ROM code protect reset bits (Note 4) b5b4 0 0: Protect removed 0 1: Protect set bits effective 1 0: Protect set bits effective 1 1: Protect set bits effective ROM code protect level 1 set bits (ROMCP1) (Note 2) b7b6 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled Notes 1: This area is on the ROM in the mask ROM version. 2: When ROM code protect is turned on, the internal flash memory is protected against readout or modification in parallel I/O mode. 3: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc. also is inhibited. 4: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, since these bits cannot be modified in parallel I/O mode, they need to be rewritten in standard serial I/O mode or CPU rewrite mode. Fig. 77 Structure of ROM code protect control Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 80 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE ID Code Check Function (in Standard serial I/O mode) Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the programmer is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID code consists of 8-bit data, and its areas are FFC216 to FFC816. Write a program which has had the ID code preset at these addresses to the flash memory. Address FFC216 FFC316 FFC416 FFC516 FFC616 FFC716 FFC816 FFC916 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ROM code protect control Interrupt vector area Fig. 78 ID code store addresses Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 81 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE (2) Parallel I/O Mode Parallel I/O mode is the mode which parallel output and input software command, address, and data required for the operations (read, program, erase, etc.) to a built-in flash memory. Use the exclusive external equipment flash programmer which supports the 7643 Group (flash memory version). Refer to each programmer maker ’s handling manual for the details of the usage. User ROM and Boot ROM Areas In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 71 can be rewritten. Both areas of flash memory can be operated on in the same way. Program and block erase operations can be performed in the user ROM area. The user ROM area and its block is shown in Figure 71. The boot ROM area is 4 Kbytes in size. It is located at addresses F00016 through FFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the Boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the Renesas factory. Therefore, using the device in standard serial I/O mode, you do not need to write to the boot ROM area. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 82 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE (3) Standard serial I/O Mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. This mode requires the exclusive external equipment (flash programmer). The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU rewrite mode), rewrite data input and so forth. The standard serial I/O mode is started by connecting “H” to the P36 (CE) pin and “H” to the P81 (SCLK) pin and “H” to the CNVSS pin (apply 4.5 V to 5.25 V to Vpp from an external source), and releasing the reset operation. (In the ordinary microcomputer mode, set CNVss pin to “L” level.) This control program is written in the Boot ROM area when the product is shipped from Renesas. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the Boot ROM area is rewritten in parallel I/O mode. Figures 79 and 80 show the pin connections for the standard serial I/O mode. In standard serial I/O mode, serial data I/O uses the four serial I/O pins SCLK, SRXD, STXD and SRDY (BUSY). The SCLK pin is the transfer clock input pin through which an external transfer clock is input. The STXD pin is for CMOS output. The SRDY (BUSY) pin outputs “L” level when ready for reception and “H” level when reception starts. Serial data I/O is transferred serially in 8-bit units. In standard serial I/O mode, only the User ROM area shown in Figure 71 can be rewritten. The Boot ROM area cannot be rewritten. In standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, commands sent from the peripheral unit (programmer) are not accepted unless the ID code matches. Outline Performance (Standard Serial I/O Mode) In standard serial I/O mode, software commands, addresses and data are input and output between the MCU and peripheral units (flash programer, etc.) using 4-wire clock-synchronized serial I/O. In reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the SCLK pin, and are then input to the MCU via the SRXD pin. In transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the STXD pin. The STXD pin is for CMOS output. Transfer is in 8-bit units with LSB first. When busy, such as during transmission, reception, erasing or program execution, the SRDY (BUSY) pin is “H” level. Accordingly, always start the next transfer after the SRDY (BUSY) pin is “L” level. Also, data and status registers in a memory can be read after inputting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following explains software commands, status registers, etc. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 83 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE Table 12 Description of pin function (Standard Serial I/O Mode) Pin name VCC,VSS CNVSS RESET X IN XOUT AVCC, AVSS LPF Ext.Cap Signal name Power supply input CNVSS Reset input Clock input Clock output Analog power supply input LPF 3.3 V line power supply input I/O Function Apply 4.50 V – 5.25 V for 5 V version or 3.00 V – 3.60 V for 3 V version to the VCC pin. Apply 0 V to the Vss pin. I I This controls the MCU operating mode. Connect this pin to VPP (= 4.50 V – 5.25 V To reset, input “L” level for 20 cycles or longer clocks of φ. Connect a ceramic or crystal resonator between the XIN and XOUT pins. When inputting an externally derived clock, input it from XIN and leave XOUT open. Apply 4.50 V – 5.25 V for 5 V version or 3.00 V – 3.60 V for 3 V version to the AVCC pin. Apply 0 V to the AVss pin. O I Loop filter for the frequency synthesizer. When this pin is not used, leave this open. Power supply input pin for 3.3 V USB line driver. When this pin is not used, input “H” level. USB D+ signal port. When this pin is not used, input “H” level. USB D- signal port. When this pin is not used, input “L” level. When these ports are not used, input “L” or “H” level, or leave them open in output mode. USB D+ USB D- USB D+ USB D- I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O O I I O I/O P00 to P07 P10 to P17 P20 to P27 I/O port P0 I/O port P1 I/O port P2 P30 to P35, P37 I/O port P3 P36 P40 to P44 P50 to P57 P60 to P67 P70 to P74 P80 P81 P 82 P83 P84 to P87 CE input I/O port P4 I/O port P5 I/O port P6 I/O port P7 BUSY output SCLK input SRXD input STXDoutput I/O port P8 Input “H” level. When these ports are not used, input “L” or “H” level, or leave them open in output mode. This is a BUSY output pin. This is a serial clock input pin. This is a serial data input pin. This is a serial data output pin. When these ports are not used, input “L” or “H” level, or leave them open in output mode. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 84 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE 53 52 64 63 50 49 48 47 46 45 44 43 42 41 60 59 58 57 56 55 54 62 61 51 P20/DB0 P21/DB1 P22/DB2 P23/DB3 P24/DB4 P25/DB5 P26/DB6 P27/DB7 P00/AB0 P01/AB1 P02/AB2 P03/AB3 P04/AB4 P05/AB5 P06/AB6 P07/AB7 P10/AB8 P11/AB9 P12/AB10 P13/AB11 P14/AB12 P15/AB13 P16/AB14 P17/AB15 P74 P73/HLDA P72 P71/HOLD P70 USB D+ USB DExt.Cap VSS VCC P67 P66 P65 P64 P63 P62 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 M37643F8FP 33 32 31 30 29 28 27 26 25 P30/RDY P31 P32 P33/DMAOUT P34/φ OUT P35/SYNCOUT P36/WR P37/RD P80/SRDY P81/SCLK P82/SRXD P83/STXD P84/UTXD P85/URXD P86/CTS P87/RTS CE BUSY SCLK SRXD STXD 20 21 12 15 16 17 11 18 22 23 13 14 10 19 24 5 6 7 8 9 3 4 1 2 VSS P61 P60 P57 P56 P55 P54 P53 P52 CNVSS/VPP RESET P51/TOUT/XCOUT P50/XCIN VSS XIN XOUT VCC AVCC LPF AVSS P44 P43 P42/INT1 P41/INT0 P40/EDMA VCC Mode setup method Signal Value 4.5 to 5.25 V CNVSS Connect to oscillator circuit. RESET SCLK RESET CE VCC (Note) VCC Note: It is necessary to apply Vcc only when reset is released. VPP VSS → VCC Package outline: PRQP0080GB-A Fig. 79 Pin connection diagram in standard serial I/O mode (1) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 85 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 P21/DB1 P20/DB0 P74 P73/HLDA P72 P71/HOLD P70 USB D+ USB DExt.Cap VSS VCC P67 P66 P65 P64 P63 P62 P61 P60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 60 42 41 P22/DB2 P23/DB3 P24/DB4 P25/DB5 P26/DB6 P27/DB7 P00/AB0 P01/AB1 P02/AB2 P03/AB3 P04/AB4 P05/AB5 P06/AB6 P07/AB7 P10/AB8 P11/AB9 P12/AB10 P13/AB11 P14/AB12 P15/AB13 M37643F8HP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P16/AB14 P17/AB15 P30/RDY P31 P32 P33/DMAOUT P34/φ OUT P35/SYNCOUT P36/WR P37/RD P80/SRDY P81/SCLK P82/SRXD P83/STXD P84/UTXD P85/URXD P86/CTS P87/RTS P40/EDMA P41/INT0 CE BUSY SCLK SRXD STXD 10 11 13 14 12 P57 P56 P55 P54 P53 P52 CNVSS/VPP RESET P51/TOUT/XCOUT P50/XCIN VSS XIN XOUT VCC AVCC LPF AVSS P44 P43 P42/INT1 15 16 17 18 19 20 5 8 9 3 4 1 2 6 7 VSS VCC Mode setup method Signal Value 4.5 to 5.25 V CNVSS VCC (Note) SCLK VSS → VCC RESET CE VCC Connect to oscillator circuit. RESET VPP Note: It is necessary to apply Vcc only when reset is released. Package outline: PLQP0080KB-A Fig. 80 Pin connection diagram in standard serial I/O mode (2) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 86 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE Software Commands (Standard Serial I/O Mode) Table 13 lists software commands. In standard serial I/O mode, erase, program and read are controlled by transferring software Table 13 Software commands (Standard serial I/O mode) Control command 1st byte transfer FF16 1 Page read 4116 2 3 4 5 6 7 Page program Block erase Erase all blocks Read status register Clear status register ID code check 2016 A716 7016 5016 F516 FA16 8 Download function Address (low) Size (low) Address (middle) Size (high) 2nd byte Address (middle) Address (middle) Address (middle) D016 SRD output SRD1 output 3rd byte Address (high) Address (high) Address (high) commands via the SRXD pin. Software commands are explained here below. 4th byte Data output Data input D016 5th byte Data output Data input 6th byte Data output Data input ..... Data output to 259th byte Data input to 259th byte When ID is not verified Not acceptable Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Address (high) Checksum ID size Data input ID1 To required number of times Version data output Data output To ID7 Acceptable Not acceptable FB16 9 10 Version data output function Boot ROM area output function FC16 Version data output Address (middle) Version data output Address (high) Version data output Data output Version data output Data output Version data output to 9th byte Data output to 259th byte Acceptable Not acceptable Notes1: Shading indicates transfer from the internal flash memory microcomputer to a programmer. All other data is transferred from an external equipment (programmer) to the internal flash memory microcomputer. 2: SRD refers to status register data. SRD1 refers to status register 1 data. 3: All commands can be accepted for the products of which boot ROM area is totally blank. 4: Address low is AB0 to AB7; Address middle is AB8 to AB15; Address high is AB16 to AB23. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 87 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE qPage Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the “FF16” command code with the 1st byte. (2) Transfer addresses AB8 to AB15 and AB16 to AB23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (DB0 to DB7) for the page (256 bytes) specified with addresses AB8 to AB23 will be output sequentially from the smallest address first synchronized with the fall of the clock. SCLK SRXD FF16 AB8 to AB16 to AB15 AB23 STXD data0 data255 SRDY (BUSY) Fig. 81 Timing for page read qRead Status Register Command This command reads status information. When the “70 16” command code is transferred with the 1st byte, the contents of the status register (SRD) with the 2nd byte and the contents of status register 1 (SRD1) with the 3rd byte are read. SCLK SRXD 7016 STXD SRD output SRD1 output SRDY (BUSY) Fig. 82 Timing for reading status register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 88 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE qClear Status Register Command This command clears the bits (SR3 to SR5) which are set when the status register operation ends in error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared. When the clear status register operation ends, the SRDY (BUSY) signal changes from “H” to “L” level. SCLK SRXD 5016 STXD SRDY (BUSY) Fig. 83 Timing for clear status register qPage Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the “4116” command code with the 1st byte. (2) Transfer addresses AB8 to AB15 and AB16 to AB23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (DB0 to DB7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. When reception setup for the next 256 bytes ends, the SRDY (BUSY) signal changes from “ H ” t o “ L ” l evel. The result of the page program can be known by reading the status register. For more information, see the section on the status register. SCLK SRXD 4116 AB8 to AB16 to data0 AB15 AB23 data255 STXD SRDY (BUSY) Fig. 84 Timing for page program Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 89 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE qBlock Erase Command This command erases the contents of the specifided block. Execute the block erase command as explained here following. (1) Transfer the “2016” command code with the 1st byte. (2) Transfer addresses AB8 to AB15 and AB16 to AB23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code “D016 ” with the 4th byte. With the verify command code, the erase operation will start for the specifided block in the flash memory. Set the addresses AB8 to AB23 to the maximum address of the specified block. When block erasing ends, the SRDY (BUSY) signal changes from “H” to “L” level. The result of the erase operation can be known by reading the status register. For more information, see the section on the status register. SCLK SRXD 2016 AB8 to AB15 AB16 to AB23 D016 STXD SRDY(BUSY) Fig. 85 Timing for block erasing qErase All Blocks Command This command erases the contents of all blocks. Execute the erase all blocks command as explained here following. (1) Transfer the “A716” command code with the 1st byte. (2) Transfer the verify command code “D0 16” with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. When erase all blocks end, the SRDY (BUSY) signal changes from “ H ” t o “ L ” l evel. The result of the erase operation can be known by reading the status register. SCLK SRXD A716 D016 STXD SRDY (BUSY) Fig. 86 Timing for erase all blocks Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 90 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE qDownload Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the “FA16” command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM. SCLK SRXD FA16 Data size Data size (low) (high) Check sum Program data STXD Program data SRDY (BUSY) Fig. 87 Timing for download Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 91 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE qVersion Information Output Command This command outputs the version information of the control program stored in the Boot ROM area. Execute the version information output command as explained here following. (1) Transfer the “FB16” command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters. SCLK SRXD FB16 STXD ‘V ’ ‘E’ ‘R’ ‘X’ SRDY (BUSY) Fig. 88 Timing for version information output qBoot ROM Area Output Command This command reads the control program stored in the Boot ROM area in page (256 bytes) unit. Execute the Boot ROM area output command as explained here following. (1) Transfer the “FC16” command code with the 1st byte. (2) Transfer addresses AB8 to AB15 and AB16 to AB23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (DB0 to DB7) for the page (256 bytes) specified with addresses AB8 to AB23 will be output sequentially from the smallest address first synchronized with the fall of the clock. SCLK SRXD FC16 A B 8 to A B 15 AB 1 6 to A B 23 STXD data0 data255 SRDY(BUSY) Fig. 89 Timing for Boot ROM area output Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 92 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE qID Code Check This command checks the ID code. Execute the boot ID check command as explained here following. (1) Transfer the “F516” command code with the 1st byte. (2) Transfer addresses AB0 to AB7, AB8 to AB15 and AB16 to AB23 (“0016”) of the 1st byte of the ID code with the 2nd and 3rd respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) Transfer the ID code with the 6th byte onward, starting with the 1st byte of the code. SCLK SRXD F516 C216 FF16 0016 ID size ID1 ID7 STXD SRDY (BUSY) Fig. 90 Timing for ID check qID Code When the flash memory is not blank, the ID code sent from the serial programmer and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the serial programmer is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses FFC216 to FFC816. Write a program into the flash memory, which already has the ID code set for these addresses. Address FFC216 FFC316 FFC416 FFC516 FFC616 FFC716 FFC816 FFC916 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ROM code protect control Interrupt vector area Fig. 91 ID code storage addresses Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 93 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE qStatus Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status register command (70 16 ). Also, the status register is cleared by writing the clear status register command (5016). Table 14 lists the definition of each status register bit. After releasing the reset, the status register becomes “8016”. •Sequencer status (SR7) The sequencer status indicates the operating status of the the flash memory. After power-on and recover from deep power down mode, the sequencer status is set to “1” (ready). This status bit is set to “0” (busy) during write or erase operation and is set to “1” upon completion of these operations. •Erase status (SR5) The erase status indicates the operating status of erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”. •Program status (SR4) The program status indicates the operating status of write operation. If a program error occurs, it is set to “1”. When the program status is cleared, it is set to “0”. Table 14 Definition of each bit of status register (SRD) Definition SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved “1” Ready Terminated in error Terminated in error - “0” Busy Terminated normally Terminated normally - Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 94 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE qStatus Register 1 (SRD1) The status register 1 indicates the status of serial communications, results from ID checks and results from check sum comparisons. It can be read after the status register (SRD) by writing the read status register command (7016). Also, status register 1 is cleared by writing the clear status register command (5016). Table 15 lists the definition of each status register 1 bit. This register becomes “0016” when power is turned on and the flag status is maintained even after the reset. •Boot update completed bit (SR15) This flag indicates whether the control program was downloaded to the RAM or not, using the download function. •Check sum consistency bit (SR12) This flag indicates whether the check sum matches or not when a program, is downloaded for execution using the download function. •ID code check completed bits (SR11 and SR10) These flags indicate the result of ID code checks. Some commands cannot be accepted without an ID code check. •Data reception time out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the received data is discarded and the MCU returns to the command wait state. Table 15 Definition of each bit of status register 1 (SRD1) SRD1 bits SR15 (bit7) SR14 (bit6) SR13 (bit5) SR12 (bit4) SR11 (bit3) SR10 (bit2) Status name Boot update completed bit Reserved Reserved Checksum match bit ID code check completed bits Definition “1” Update completed Match 00 01 10 11 “0” Not Update Mismatch Not verified Verification mismatch Reserved Verified Normal operation - SR9 (bit1) SR8 (bit0) Data reception time out Reserved Time out - Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 95 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE Full Status Check Results from executed erase and program operations can be known by running a full status check. Figure 92 shows a flowchart of the full status check and explains how to remedy errors which occur. Read status register SR4 = 1 and SR5 = 1 ? NO SR5 = 0 ? YES SR4 = 0 ? YES YES Command sequence error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should an erase error occur, the block in error cannot be used. NO Erase error NO Program error Should a program error occur, the block in error cannot be used. End (Erase, program) Note: When one of SR5 to SR4 is set to “1” , none of the page read, program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands. Fig. 92 Full status check flowchart and remedial procedure for errors Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 96 of 103 OVERVIEW 7643 Group FLASH MEMORY MODE Example Circuit Application for Standard Serial I/O Mode Figure 93 shows a circuit application for the standard serial I/O mode. Control pins will vary according to a programmer, therefore see a programmer manual for more information. Clock input BUSY output Data input Data output SCLK SRDY (BUSY) SRXD STXD P36/WR (CE) M37643F8 VPP power source input CNVss Notes 1: Control pins and external circuitry will vary according to a programmer. For more information, see the programmer manual. 2: In this example, the Vpp power supply is supplied from an external source (programmer). To use the user’s power source, connect to 4.5 V to 5.25 V. Fig. 93 Example circuit application for standard serial I/O mode Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 97 of 103 OVERVIEW 7643 Group NOTES ON PROGRAMMING NOTES ON PROGRAMMING Processor Status Register •The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. •To reference the contents of the processor status register (PS), execute the P HP i nstruction once then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its original status. A NOP instruction must be executed after every PLP instruction. •A SEI instruction must be executed before every PLP instruction. A NOP instruction must be executed before every CLI instruction. Ports •When the data register (port latch) of an I/O port is modified with the bit managing instruction (SEB, CLB instructions) the value of the unspecified bit may be changed. •In standby state (the stop mode by executing the STP instruction, and the wait mode by executing the W IT i nstruction) for lowpower dissipation, do not make input levels of an I/O port “undefined”, especially for I/O ports of the P-channel and the Nchannel open-drain. Pull-up (connect the port to Vcc) or pull-down (connect the port to Vss) these ports through a resistor. When determining a resistance value, note the following points: (1) External circuit (2) Variation of output levels during the ordinary operation When using built-in pull-up or pull-down resistor, note on varied current values. (1) When setting as an input port : Fix its input level (2) When setting as an output port : Prevent current from flowing out to external BRK Instruction It can be detected that the BRK instruction interrupt event or the least priority interrupt event by referring the stored B flag state. Refer to the stored B flag state in the interrupt routine. Decimal Calculations When decimal mode is selected, the values of the V flags are invalid. The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be initialized to “1” before each calculation. Serial I/O Do not write to the serial I/O shift register during a transfer when in SPI compatible mode. UART •The all error flags PER, FER, OER and SER are cleared to “0” when the UART status register is read, at the hardware reset or initialization by setting the Transmit Initialization Bit. These flags are also cleared to “0” by execution of bit test instructions such as BBC and BCS. •The transmission interrupt request bit might be set and the interrupt request is generated by setting the transmit initialization bit to “1” even when selecting timing that either of the following flags is set to “1” as timing where the transmission interrupt is generated: (1) Transmit buffer empty flag is set to “1” (2) Transmit complete flag is set to “1”. Therefore, when the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as the following sequence: (1) Transmit initialization bit is set to “1” (2) Transmit interrupt request bit is set to “0” (3) Transmit interrupt enable bit is set to “1”. •Do not update a value of UART baud rate generator in the condition of transmission enabled or reception enabled. Disable transmission and reception before updating the value. If the former data remains in the UART transmit buffer registers 1 and 2 when transmission is enabled, an undefined data might be output. Multiplication and Division Instructions •The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. Timers •If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). •P51/XCOUT/TOUT pin cannot function as an I/O port when XCIN XCOUT is oscillating. When XCIN - XCOUT oscillation is not used or X COUT oscillation drive is disabled, this pin can function as the TOUT output pin of the timer 1 or 2. When using the TOUT output function and f(XCIN) divided by 2 is used as the timer 1 count source (bit 2 of T123M = “1”), disable XCOUT oscillation drive (bit 5 of CCR = “1”). Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 98 of 103 OVERVIEW 7643 Group NOTES ON PROGRAMMING •The receive buffer full interrupt request is not generated if receive errors are detected at receiving. •If a character bit length is 7 bits, bit 7 of the UART transmit/receive buffer register 1 and bits 0 to 7 of the UART transmit/ receive buffer register 2 are ignored at transmitting; they are invalid at receiving. If a character bit length is 8 bits, bits 0 to 7 of the UART transmit/ receive buffer register 2 are ignored at transmitting; they are invalid at receiving. If a character bit length is 9 bits, bits 1 to 7 of the UART transmit/ receive buffer register 2 are ignored at transmitting; they are “0” at receiving. •When using the MCU at Vcc = 3.3V, set the USB Line Driver Supply Enable Bit to “0” (line driver disable). Note that setting the USB Line Driver Current Control Bit (USBC3) doesn’t affect the USB operation. •Read one packet data from the OUT FIFO before clearing the OUT_PKT_RDY Flag. If the OUT_PKT_RDY Flag is cleared while one packet data is being read, the internal read pointer cannot operate normally. •Use the transfer instructions such as LDA and STA to set the registers: USB interrupt status registers 1, 2 (addresses 0052 16, 0053 16); USB endpoint 0 IN control register (address 005916 ); USB endpoint x IN control register (address 005916); USB endpoint x OUT control register (address 005A16). Do not use the read-modify-write instructions such as the SEB or the CLB instruction. When writing to bits shown by Table 15 using the transfer instruction such as LDA or STA, a value which never affect its bit state is required. Take the following sequence to change these bits contents: (1) Store the register contents onto a variable or a data register. (2) Change the target bit on the variable or the data register. Simultaneously mask the bit so that its bit state cannot be changed. (See to Table 15.) (3) Write the value from the variable or the data register to the register using the transfer instruction such as LDA or STA. • To use the AUTO_SET function for an IN transfer when the AUTO_SET bit is set to 1, set the FIFO to single buffer mode. USB •When the USB Reset Interrupt Status Flag is kept at “1”, all other flags in the USB internal registers (addresses 005016 to 005F16) will return to their reset status. However, the following registers are not affected by the USB reset: USB control register (address 0013 16 ), Frequency synthesizer control register (address 006C16), Clock control register (address 001F16), and USB endpoint-x FIFO register (addresses 006016 to 006216). •When not using the USB function, set the USB Line Driver Supply Enable Bit of the USB control register (address 001316) to “1” for power supply to the internal circuits (at Vcc = 5V). •The IN_PKT_RDY Bit can be set by software even when using the AUTO_SET function. •When writing to USB-related registers, set the USB Clock Enable Bit to “1”, then perform the write after four φ cycle waits. Table 15 Bits of which state might be changed owing to software write Register name Bit name USB endpoint 0 IN control register IN_PKT_RDY (b1) DATA_END (b3) FORCE_STALL (b4) USB endpoint x (x = 1, 2) IN control register IN_PKT_RDY (b0) USB endpoint x (x = 1, 2) OUT control register OUT_PKT_RDY (b0) FORCE_STALL (b4) Value not affecting state (Note) “0” “0” “1” “0” “1” “1” Note: Writing this value will not change the bit state, because this value cannot be written to the bit by software. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 99 of 103 OVERVIEW 7643 Group NOTES ON PROGRAMMING Frequency Synthesizer •The frequency synthesizer and DC-DC converter must be set up as follows when recovering from a Hardware Reset: (1) Enable the frequency synthesizer after setting the frequency synthesizer related registers (addresses 006C16 to 006F16). Then wait for 2 ms. (2) Check the Frequency Synthesizer Lock Status Bit. If “0”, wait for 0.1 ms and then recheck. (3) When using the USB built-in DC-DC converter, set the USB Line Driver Supply Enable Bit of the USB control register to “1”. This setting must be done 2 ms or more after the setup described in step (1). The USB Line Driver Current Control Bit must be set to “0” at this time. (When Vcc = 3.3V, the setting explained in this step is not necessary.) (4) After waiting for (C + 1) ms so that the external capacitance pin (Ext. Cap. pin) can reach approximately 3.3 V, set the USB Clock Enable Bit to “1”. At this time, “C” equals the capacitance (µ F) of the capacitor connected to the Ext. Cap. pin. For example, if 2.2 µF and 0.1 µF capacitors are connected to the Ext. Cap. in parallel, the required wait will be (2.3 + 1) ms. (5) After enabling the USB clock, wait for 4 or more f cycles, and then set the USB Enable Bit to “1”. After enabling USB clock, read or write the USB internal registers (address 005016 to 006216 with the exception of USBC, CCR and PSC) . •Bits 6 and 5 of the frequency synthesizer control register (address 006C 16) are initialized to “ 11 ” a fter reset release. Make sure to set bits 6 and 5 to “10” after the Frequency Synthesizer Lock Status Bit goes to “1”. •When using the frequency synthesized clock function, we recommend using the fastest frequency possible of f(XIN) or f(XCIN) as an input clock for the PLL. Owing to the PLL mechanism, the PLL controls the speed of multiplied clocks from the source clock. As a result, when the source clock input is lower, the generated clock becomes less stable. This is because more multipliers are needed and the speed control is very rough. Higher source clock input generates a stabler clock, as less multipliers are needed and the speed control is more accurate. However, if the input clock frequency is relatively high, the PLL clock generator can quickly lock-up the output clock to the source and make the output clock very stable. •Set the value of frequency synthesizer multiply register 2 (FSM2) so that the fPIN is 1 MHZ or higher. does not get mixed in with the transfer data. •When setting the DMAC channel x enable bit (bit 7 of address 004116) to “1”, be sure simultaneously to set the DMAC channel x transfer initiation source capture register reset bit (bit 6 of address 004116) to “1”. If this is not performed, an incorrect data will be transferred at the same time when the DMAC is enabled. Memory Expansion Mode & Microprocessor Mode •In both memory expansion mode and microprocessor mode, use the LDM instruction or STA instruction to write to port P3 (address 000E16). When using the Read-Modify-Write instruction (SEB instruction, CLB instruction) you will need to map a memory that the CPU can read from and write to. • In the memory expansion mode, if the internal and external memory areas overlap, the internal memory becomes the valid memory for the overlapping area. When the CPU performs a read or a write operation on this overlapped area, the following things happen: (1) Read The CPU reads out the data in the internal memory instead of in the external memory. Note that, since the CPU will output a proper read signal, address signal, etc., the memory data at the respective address will appear on the external data bus. (2) Write The CPU writes data to both the internal and external memories. •The wait function is serviceable at accessing an external memory. Stop Mode •When the STP instruction is executed, bit 7 of the clock control register (address 001F16) goes to “0”. To return from stop mode, reset CCR7 to “1”. •When using fSYN (set Internal System Clock Select Bit (CPMA6) to “1”) as the internal system clock, switch CPMA6 to “0” before executing the STP instruction. Reset CPMA6 after the system returns from Stop Mode and the frequency synthesizer has stabilized. CPMA6 does not need to be switched to “0” when using the WIT instruction. •When the STP instruction is being executed, all bits except bit 4 of the timer 123 mode register (address 002916) are initialized to “0”. It is not necessary to set T123M1 (Timer 1 Count Stop Bit) to “0” before executing the STP instruction. After returning from Stop Mode, reset the timer 1 (address 0024 16 ), timer 2 (address 002516), and the timer 123 mode register (address 002916). DMA •In the memory expansion mode and microprocessor mode, the DMAOUT pin outputs “H” during a DMA transfer. • Do not access the DMAC-related registers by using a DMAC transfer. The destination address data and the source address data will collide in the DMAC internal bus. •When using the USB FIFO as the DMA transfer source, make sure that, if you use the AUTO_SET function, short packet data Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 100 of 103 OVERVIEW 7643 Group USAGE NOTES USAGE NOTES Oscillator Connection Notice The built-in feedback register (1 MΩ) and the dumping resistor (400 Ω) is internally connected between pins XIN and XOUT. AVss and AVcc Pin Treatment Notice (Noise Elimination) An insulation connector (Ferrite Beads) must be connected between AVss and Vss pins and between AVcc and Vcc pins. Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. U S B Tr a n s c e i v e r Tr e a t m e n t ( N o i s e Elimination) •The Full-Speed USB2.0 specification requires a driver -impedance 28 to 44 Ω. (Refer to Clause 7.1.1.1 Full-speed (12 Mb/s) Driver Characteristics in the USB specification.) In order to meet the USB specification impedance requirements, connect a resistor (27 Ω to 33 Ω recommended) in series to the USB D+ pin and the USB D- pin. In addition, in order to reduce the ringing and control the falling/ rising timing of USB D+/D- and a crossover point, connect a capacitor between the USB D+/D- pins and the Vss pin if necessary. The values and structure of those peripheral elements depend on the impedance characteristics and the layout of the printed circuit board. Accordingly, evaluate your system and observe waveforms before actual use and decide use of elements and the values of resistors and capacitors. •Connect a capacitor between the Ext. Cap. pin and the Vss pin. The capacitor should have a 2.2 µF capacitor (Tantalum capacitor) and a 0.1 µ F capacitor (ceramic capacitor) connected in parallel. Figure 95 for the proper positions of the peripheral components. Power Supply Pins Treatment Notice Please connect 0.1 µF and 4.7 µF capacitors in parallel between pins Vcc and Vss, and pins AVss and AVcc. These capacitors must be connected as close as possible between the DC supply and GND pins, and also the analog supply pin and corresponding GND pin. Wiring patterns for these supply and GND pins must be wider than other signal patterns. These filter capacitors should not be placed near the LPF pins as they will cause noise problems R e s e t P i n Tr e a t m e n t N o t i c e ( N o i s e Elimination) If the reset input signal rises very slowly, we recommend attaching a capacitor, such as a 1000 pF ceramic capacitor with excellent high frequency characteristics, between the RESET pin and the Vss pin. Please note the following two issues for this capacitor connection. (1) Capacitor wiring pattern must be as short as possible (within 20 mm). (2) The user must perform an application level operation test. XIN Frequency Synthesizer USBC5 enable DC-DC converter current mode enable lock LS enable FSE Note 1 Ext. Cap. 2.2 µF 0.1 µF 1.5 kΩ USBC4 USBC3 USB Clock (48 MHz) USB FCU enable USB transceiver enable D+ USBC7 USBC7 Note 2 D- LPF Pin Treatment Notice All passive components must be located as close as possible to the LPF pin. Notes 1: In Vcc = 3.3 V, connect to Vcc. In Vcc =5 V, do not connect the external DC-DC converter to the Ext. Cap pin. 2: The resistors values depend on the layout of the printed circuit board. Fig.95 Peripheral circuit •In Vcc = 3.3 V operation, connect the Ext. Cap. pin directly to the Vcc pin in order to supply power to the USB transceiver. In addition, you will need to disable the DC-DC converter in this operation (set bit 4 of the USB control register to “0”.) If you are using the bus powered supply in Vcc = 3.3 V operation, the DCDC converter must be placed outside the MCU. •In Vcc = 5 V operation, do not connect the external DC-DC converter to the Ext. Cap. pin. Use the built-in DC-DC converter by enabling the USB line driver. •Make sure the USB D+/D- lines do not cross any other wires. Keep a large GND area to protect the USB lines. Also, make sure you use a USB specification compliant connecter for the connection. LPF pin 1 kΩ 680 pF 0.1 µF AVSS pin Fig. 94 Passive components near LPF pin Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 101 of 103 OVERVIEW 7643 Group USAGE NOTES USB Communication In applications requiring high-reliability, we recommend providing the system with protective measures such as USB function initialization by software or USB reset by the host to prevent USB communication from being terminated unexpectedly, for example due to external causes such as noise. • Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. • At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins. Clock Input/Output Pin Wiring (Noise Elimination) (1) Make the wiring for the input/output pins as short as possible. (2) Make the wiring across the grounding lead of the capacitor which is connected to an oscillator and the Vss pin of the MCU as short as possible (within 20 mm) (3) Make sure to isolate the oscillation Vss pattern from other patterns for oscillation circuit-use only. Electric Characteristic Differences Between Mask ROM and Flash Memory Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and Flash Memory version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with the Flash Memory version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version. Oscillator Wiring (Noise Elimination) (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines, including USB signal lines, where a current larger than the tolerance of current value flows. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. ROM ORDERING METHOD 1.Mask ROM Order Confirmation Form 2.Mark Specification Form 3.Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk. • F or the mask ROM confirmation and the mark specifications, refer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com). Terminate Unused Pins (1) Output ports : Open (2) Input ports : Connect each pin to Vcc or Vss through each resistor of 1 kΩ to 10 kΩ. Ports that permit the selecting of a built-in pull-up or pull-down resistor can also use this resistor. As for pins whose potential affects to operation modes such as pins CNVss, INT or others, select the Vcc pin or the Vss pin according to their operation mode. (3) I/O ports : • Set the I/O ports for the input mode and connect them to Vcc or Vss through each resistor of 1 kΩ to 10 kΩ. Ports that permit the selecting of a built-in pull-up or pull-down resistor can also use this resistor. Set the I/O ports for the output mode and open them at “L” or “H”. • When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 102 of 103 OVERVIEW 7643 Group FUNCTIONAL DESCRIPTION SUPPLEMENT FUNCTIONAL DESCRIPTION SUPPLEMENT Timing After Interrupt The interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently in execution. Figure 96 shows a timing chart after an interrupt occurs, and Figure 97 shows the time up to execution of the interrupt processing routine. φ SYNC RD WR Address bus Data bus PC Not used S, SPS S-1, SPS S-2, SPS BL AL BH AL, AH AH PCH P CL PS SYNC : CPU operation code fetch cycle (This is an internal signal which cannot be observed from the external unit.) BL, BH : Vector address of each interrupt AL, AH : Jump destination address of each interrupt SPS : “0016” or “0116” Fig. 96 Timing chart after interrupt occurs Interrupt request occurs Interrupt operation starts Main routine Waiting time for pipeline postprocessing Push onto stack vector fetch Interrupt processing routine 0 to 16 cycles 2 cycles 5 cycles 7 to 23 cycles (f(φ) = 12 MHz, 0.583 µs to 1.92 µs) Fig. 97 Time up to execution of interrupt processing routine Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 103 of 103 T HIS PAGE IS BLANK FOR REASONS OF LAYOUT. CHAPTER 2 APPLICATION 2.1 I/O port 2.2 Timer 2.3 Serial I/O 2.4 UART 2.5 DMAC 2.6 USB 2.7 Frequency synthesizer 2.8 External devices connection 2.9 Reset 2.10 Clock generating circuit APPLICATION 7643 Group 2.1 I/O Port 2.1 I/O port This paragraph explains the registers setting method and the notes related to the I/O port. 2.1.1 Memory map Address 000416 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001216 Interrupt request register C (IREQC) Interrupt control register C (ICONC) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port control register (PTC) Port P2 pull-up control register (PUP2) 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 Port P6 (P6) Port P6 direction register (P6D) Port P5 (P5) Port P5 direction register (P5D) Port P4 (P4) Port P4 direction register (P4D) Port P7 (P7) Port P7 direction register (P7D) Port P8 (P8) Port P8 direction register (P8D) Fig. 2.1.1 Memory map of registers related to I/O port Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 2 of 202 APPLICATION 7643 Group 2.1 I/O Port 2.1.2 Related registers Port Pi b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (i = 0, 1, 2, 3, 5, 6, 8) (Pi : addresses 0816, 0A16, 0C16, 0E16, 1616, 1416, 1C16) b 0 Port Pi0 1 Port Pi1 2 Port Pi2 3 Port Pi3 4 Port Pi4 5 Port Pi5 6 Port Pi6 7 Port Pi7 Name Functions qIn output mode Write •••••••• Port latch Read •••••••• Port latch qIn input mode Write •••••••• Port latch Read •••••••• Value of pin At reset R W 0 0 0 0 0 0 0 0 Fig. 2.1.2 Structure of Port Pi register Port P4, Port P7 b7 b6 b5 b4 b3 b2 b1 b0 Port P4, Port P7 (P4, P7 : addresses 1816, 1A16) b Name Functions qIn output mode Write •••••••• Port latch Read •••••••• Port latch qIn input mode Write •••••••• Port latch Read •••••••• Value of pin At reset R W 0 0 0 0 0 Undefined ✕ ✕ Undefined ✕ ✕ Undefined ✕ ✕ 0 Port P40 or Port P70 1 Port P41 or Port P71 2 Port P42 or Port P72 3 Port P43 or Port P73 4 Port P44 or Port P74 5 Nothing is arranged for these bits. 6 When these bits are read out, the contents are undefined. 7 Fig. 2.1.3 Structure of Port P4, Port P7 registers Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 3 of 202 APPLICATION 7643 Group 2.1 I/O Port Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (i = 0, 1, 2, 3, 5, 6, 8) (PiD : addresses 0916, 0B16, 0D16, 0F16, 1716, 1516, 1D16) b Name Functions 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode At reset R W 0 0 0 0 0 0 0 0 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ 0 Port Pi direction register 1 2 3 4 5 6 7 Fig. 2.1.4 Structure of Port Pi direction register (i = 0, 1, 2, 3, 5, 6, 8) Port P4, P7 direction registers b7 b6 b5 b4 b3 b2 b1 b0 Port P4 direction register, Port P7 direction register (P4D, P7D : addresses 1916, 1B16) b Name Functions 0 : Port P40 or P70 input mode 1 : Port P40 or P70 output mode 0 : Port P41 or P71 input mode 1 : Port P41 or P71 output mode 0 : Port P42 or P72 input mode 1 : Port P42 or P72 output mode 0 : Port P43 or P73 input mode 1 : Port P43 or P73 output mode 0 : Port P44 or P74 input mode 1 : Port P44 or P74 output mode At reset R W 0 0 0 0 0 ✕ ✕ ✕ ✕ ✕ 0 Port P4 direction register Port P7 direction register 1 2 3 4 5 Nothing is arranged for these bits. 6 When these bits are read out, the contents are undefined. 7 Undefined ✕ ✕ Undefined ✕ ✕ Undefined ✕ ✕ Fig. 2.1.5 Structure of Port P4 direction, Port P7 direction registers Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 4 of 202 APPLICATION 7643 Group 2.1 I/O Port Port control register b7 b6 b5 b4 b3 b2 b1 b0 0 Port control register (PTC : address 1016) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 Port P0 to P3 slew rate 0 : Disabled control bit (Note 1) 1 : Enabled 1 Port P4 slew rate control 0 : Disabled bit (Note 1) 1 : Enabled 2 Port P5 slew rate control 0 : Disabled bit (Note 1) 1 : Enabled 3 Port P6 slew rate control 0 : Disabled bit (Note 1) 1 : Enabled 0 : Disabled 4 Port P7 slew rate control bit (Note 1) 1 : Enabled 5 Port P8 slew rate control 0 : Disabled bit (Note 1) 1 : Enabled 6 Port P2 input level select 0 : Reduced VIHL level input (Note 2) bit 1 : CMOS level input 7 Nothing is arranged for this bit. Fix this bit to “0”. Notes 1: The slew rate function can reduce di/dt by modifying an internal buffer structure. 2: The characteristics of VIHL level is basically the same as that of TTL level. But, its switching center point is a little higher than TTL’s. Fig. 2.1.6 Structure of Port control register Port P2 pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Port P2 pull-upt control register (PUP2 : address 1216) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 Port P20 pull-up control bit 0 : Disabled 1 : Enabled 1 Port P21 pull-up control bit 0 : Disabled 1 : Enabled 2 Port P22 pull-up control bit 0 : Disabled 1 : Enabled 3 Port P23 pull-up control bit 0 : Disabled 1 : Enabled 4 Port P24 pull-up control bit 0 : Disabled 1 : Enabled 5 Port P25 pull-up control bit 0 : Disabled 1 : Enabled 6 Port P26 pull-up control bit 0 : Disabled 1 : Enabled 7 Port P27 pull-up control bit 0 : Disabled 1 : Enabled Fig. 2.1.7 Structure of Port P2 pull-up control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 5 of 202 APPLICATION 7643 Group 2.1 I/O Port Interrupt request register C b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register C (IREQC : address 0416) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 ✽ ✽ ✽ 0 Timer 3 interrupt request bit 1 Nothing is arranged for these bits. When these bits are read out, the contents are undefined. 2 These bits are “0” at write. 3 Serial I/O interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit 4 Nothing is arranged for these bits. When these bits are read out, the contents are undefined. 5 These bits are “0” at write. 6 Key input interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit 7 Nothing is arranged for this bit. Fix this bit to “0”. ✽: “0” can be set by software, but “1” cannot be set. Fig. 2.1.8 Structure of Interrupt request register C Interrupt control register C b7 b6 b5 b4 b3 b2 b1 b0 0 00 00 Interrupt control register C (ICONC : address 0716) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 Timer 3 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 1 Nothing is arranged for these bits. 2 Fix these bits to “0”. 3 Serial I/O interrupt enable 0 : Interrupt disabled 1 : Interrupt enabled bit 4 Nothing is arranged for these bits. 5 Fix these bits to “0”. 6 Key input interrupt enable 0 : Interrupt disabled 1 : Interrupt enabled bit 7 Nothing is arranged for this bit. Fix this bit to “0”. Fig. 2.1.9 Structure of Interrupt control register C Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 6 of 202 APPLICATION 7643 Group 2.1 I/O Port 2.1.3 Key-on wake-up interrupt application example Outline : Key-on wake-up is realized, using internal pull-up resistors. Specifications: System is returned from the wait mode when the key-on wakeup interrupt occurs by input of the falling edge to port P2i. Figure 2.1.10 shows the registers setting; Figure 2.1.11 shows a connection diagram; Figure 2.1.12 shows the control procedure. Port P2 direction register (address 0D16) b7 b0 P2D 000 00 Input mode Port P2 pull-up control register (address 1216) b7 b0 PUP2 111 11 Port P20 to P24 pull-up enabled Port control register (address 1016) b7 b0 PTC 00 VIHL level Interrupt request register C (address 0416) b7 b0 IREQC 00 Key input interrupt request bit Interrupt control register C (address 0716) b7 b0 ICONC 01 Key input interrupt: Enabled Fig. 2.1.10 Registers setting Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 7 of 202 APPLICATION 7643 Group 2.1 I/O Port 7643 group P20 P2i (i : 0 to 4) P21 Key ON P22 P23 P24 Fig. 2.1.11 Connection diagram RESET q X: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization P2D (address 0D16) PUP2 (address 1216) PTC (address 1016) ..... .... XXX000002 XXX111112 00XXXXXX2 •Set to input mode •Pull-up enabled •Reduced VIHL level Power down process IREQC,bit6 (address 0416) ICONC,bit6 (address 0716) WIT ..... 0 1 •Set key input interrupt request bit to “0” •Key input interrupt enabled Key input interrupt routine Key input interrupt process ..... RTI Process continued ..... Fig. 2.1.12 Control procedure Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 8 of 202 APPLICATION 7643 Group 2.1 I/O Port 2.1.4 Terminate unused pins Table 2.1.1 Termination of unused pins Termination P0, P1, P2, P3, P4, P5, • S et to the input mode and connect each to VCC o r V SS t hrough a resistor of 1 k Ω t o 10 k Ω . P6, P7, P8 • S et to the output mode and open at “ L ” o r “ H ” o utput state. Pins/Ports name HOLD, RDY CNVSS AVSS AVCC XOUT USB D+ USB DExt. Cap. Connect to Vcc (DC-DC converter disabled) when the USB function is not used. Note: T his is the termination in case USB is not used. Connect to Vcc through a resistor (pull-up). Connect to Vcc or Vss. Connect to Vss (GND). Connect to Vcc. Open (only when using external clock) Open Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 9 of 202 APPLICATION 7643 Group 2.1 I/O Port 2.1.5 Notes on I/O port (1) Notes in standby state In standby state ✽1 f or low-power dissipation, do not make input levels of an I/O port “ undefined ” . Pull-up (connect the port to V CC) or pull-down (connect the port to V SS ) these ports through a resistor. When determining a resistance value, note the following points: • E xternal circuit • V ariation of output levels during the ordinary operation When using built-in pull-up resistor, note on varied current values: • W hen setting as an input port : Fix its input level • When setting as an output port : Prevent current from flowing out to external q Reason The potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an I/O port are “ undefined ” . This may cause power source current. ✽1 standby state: stop mode by executing S TP i nstruction wait mode by executing W IT i nstruction (2) Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction✽2, the value of the unspecified bit may be changed. q R eason The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an I/O port, the following is executed to all bits of the port latch. • As for bit which is set for input port: The pin state is read in the CPU, and is written to this bit after bit managing. • As for bit which is set for output port: The bit value is read in the CPU, and is written to this bit after bit managing. Note the following: •Even when a port which is set as an output port is changed for an input port, its port latch holds the output data. •As for a bit of which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. ✽2 Bit managing instructions: S EB a nd C LB i nstructions (3) Pull-up control When using port P2, which includes a pull-up resistor, as an output port, its port pull-up control is invalidated, that is, pull-up cannot be enabled. q R eason Pull-up/pull-down control is valid only when each direction register is set to the input mode. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 10 of 202 APPLICATION 7643 Group 2.1 I/O Port 2.1.6 Termination of unused pins (1) Terminate unused pins ➀ I /O ports : • Set the I/O ports for the input mode and connect them to VCC o r VSS t hrough each resistor of 1 k Ω t o 10 k Ω . Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/O ports for the output mode and open them at “L” or “H”. • When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. • Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. ➁ T he AVss pin when not using the A/D converter : • When not using the A/D converter, handle a power source pin for the A/D converter, AVss pin as follows: AVss: Connect to the Vss pin. (2) Termination remarks ➀ I /O ports : Do not open in the input mode. q R eason • The power source current may increase depending on the first-stage circuit. • An effect due to noise may be easily produced as compared with proper termination ➁ and shown on the above. ➁ I /O ports : When setting for the input mode, do not connect to V CC o r V SS d irectly. q R eason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and V CC ( or V SS ). ➂ I /O ports : When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through a resistor. q R eason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. • At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 11 of 202 APPLICATION 7643 Group 2.2 Timer 2.2 Timer This paragraph explains the registers setting method and the notes related to the timers. 2.2.1 Memory map Address 000316 000416 000616 000716 002416 002516 002616 002916 Interrupt request register B (IREQB) Interrupt request register C (IREQC) Interrupt control register B (ICONB) Interrupt control register C (ICONB) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 123 mode register (T123M) Fig. 2.2.1 Memory map of registers relevant to timers Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 12 of 202 APPLICATION 7643 Group 2.2 Timer 2.2.2 Related registers Timer i (i = 1 to 3) b7 b6 b5 b4 b3 b2 b1 b0 Timer 1, Timer 2, Timer 3 (T1, T2, T3: addresses 2416, 2516, 2616) b 0 1 2 3 4 5 6 7 Functions qTimer i’s count value is set through this register. qTimer 1 and Timer 2 Writing operation depends on the timers 1, 2 write control bit. When it is “0”, the values are simultaneously written into their latches and counters. When it is “1”, the values are written into only their latches. qTimer 3 The values are simultaneously written into their latches and counters. qWhen reading this register’s address, its timer’s count values are read out. qThe timer causes an underflow at the count pulse following the count where the timer contents reaches “0016”. Then The contents of latches are automatically reloaded into the timer. At reset R W (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) Note: Timer 1 and Timer 3’s values are “FF16”. Timer 2 ’s value are “0116”. Fig. 2.2.2 Structure of Timer i (i=1, 2, 3) Timer 123 mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer 123 mode register (T123M : address 2916) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 TOUT factor select bit 1 2 3 4 5 6 7 0 : Timer 1 output 1 : Timer 2 output 0 : Count start Timer 1 count stop bit 1 : Count stop Timer 1 count source 0:φ/8 select bit 1 : f(XCIN) / 2 Timer 2 count source 0 : Timer 1 output select bit 1:φ 0 : Timer 1 output Timer 3 count source 1:φ/8 select bit TOUT output active edge 0 : Start at “H” output switch bit 1 : Start at “L” output TOUT output control bit 0 : TOUT output disabled 1 : TOUT output enabled Timers 1, 2 write control bit 0 : Write value in latch and counter 1 : Write value in latch only Fig. 2.2.3 Structure of Timer 123 mode register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 13 of 202 APPLICATION 7643 Group 2.2 Timer Interrupt request register B b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register B (IREQB : address 0316) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 ✽ 0 UART summing error interrupt request bit 1 2 3 4 5 6 Nothing is arranged for these bits. When these bits are read out, the contents are undefined. These bits are “0” at write. 0 : No interrupt request issued Timer 1 interrupt request 1 : Interrupt request issued bit 0 : No interrupt request issued 7 Timer 2 interrupt request bit 1 : Interrupt request issued ✽: “0” can be set by software, but “1” cannot be set. ✽ ✽ Fig. 2.2.4 Structure of Interrupt request register B Interrupt request register C b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register C (IREQC : address 0416) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 ✽ ✽ ✽ 0 Timer 3 interrupt request bit 1 Nothing is arranged for these bits. When these bits are read out, the contents are undefined. 2 These bits are “0” at write. 3 Serial I/O interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit 4 Nothing is arranged for these bits. When these bits are read out, the contents are undefined. 5 These bits are “0” at write. 6 Key input interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit 7 Nothing is arranged for this bit. Fix this bit to “0”. ✽: “0” can be set by software, but “1” cannot be set. Fig. 2.2.5 Structure of Interrupt request register C Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 14 of 202 APPLICATION 7643 Group 2.2 Timer Interrupt control register B b7 b6 b5 b4 b3 b2 b1 b0 00000 Interrupt control register B (ICONB : address 0616) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 0 0 0 0 0 0 UART summing error interrupt enable bit 1 Nothing is arranged for these bits. 2 Fix these bits to “0”. 3 4 5 6 Timer 1 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 7 Timer 2 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled Fig. 2.2.6 Structure of Interrupt control register B Interrupt control register C b7 b6 b5 b4 b3 b2 b1 b0 0 00 00 Interrupt control register C (ICONC : address 0716) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 Timer 3 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 1 Nothing is arranged for these bits. 2 Fix these bits to “0”. 3 Serial I/O interrupt enable 0 : Interrupt disabled 1 : Interrupt enabled bit 4 Nothing is arranged for these bits. 5 Fix these bits to “0”. 6 Key input interrupt enable 0 : Interrupt disabled 1 : Interrupt enabled bit 7 Nothing is arranged for this bit. Fix this bit to “0”. Fig. 2.2.7 Structure of Interrupt control register C Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 15 of 202 APPLICATION 7643 Group 2.2 Timer 2.2.3 Timer application examples (1) Basic functions and uses [Function 1] Control of event interval (Timer 1 to Timer 3) When a certain time, by setting a count value to each timer, has passed, the timer interrupt request occurs. • Generating of an output signal timing • Generating of a wait time [Function 2] Control of cyclic operation (Timer 1 to Timer 3) The value of the timer latch is automatically written to the corresponding timer each time the timer underflows, and each timer interrupt request occurs in cycles. • Generating of cyclic interrupts • Clock function (measurement of 1 s); see “ (2) Timer application example 1 ” • Control of a main routine cycle [Function 3] Output of rectangular waveform (Timer 1, Timer 2) The output levels of the T OUT p in is inverted each time the timer underflows. • Piezoelectric buzzer output; see “ (3) Timer application example 2 ” • Generating of the remote control carrier waveforms (2) Timer application example 1: Clock function (measurement of 1 s) Outline : The input clock is divided by the timer so that the clock can count up at 1 s intervals. Specifications : • The clock f(X CIN) = 32 kHz is divided by the timer. • The timer 2 interrupt request bit is checked in main routine, and if the interrupt request is issued, the clock is counted up. • The timer 1 interrupt occurs every 10 ms to execute processing of other interrupts. Figure 2.2.8 shows the timers connection and setting of division ratios; Figure 2.2.9 shows the related registers setting; Figure 2.2.10 shows the control procedure. Timer 1 f(XCIN) 32 kHz 1/2 1/160 Timer 2 1/100 Timer 2 interrupt request bit 0/1 1s 0/1 10 ms 0 : No interrupt request issued 1 : Interrupt request issued Timer 1 interrupt request bit Fig. 2.2.8 Timers connection and setting of division ratios Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 16 of 202 APPLICATION 7643 Group 2.2 Timer CPU mode register A (address 0016) b7 b0 CPMA 10111 Processor mode selected Stack page select selected Sub-clock (XCIN-XCOUT): Oscillating Main clock (XIN-XOUT): Stopped External clock: XCIN-XCOUT Timer 123 mode register (address 2916) b7 b0 T123M 00 010 Timer 1 count: Count start Timer 1 count source: f(XCIN) / 2 Timer 2 count source: Timer 1 output TOUT output disabled Timers 1, 2 write control: Write value in latch and counter Timer 1 (address 2416) b7 b0 T1 9F16 Timer 2 (address 2516) b7 b0 Set “division ratio – 1”. [ T1 = 159 (9F16), T2 = 99 (6316) ] T2 6316 Interrupt request register B (address 0316) b7 b0 IREQB Timer 1 interrupt request Timer 2 interrupt request Interrupt control register B (address 0616) b7 b0 ICONB 0100000 Timer 1 interrupt: Enabled Timer 2 interrupt: Disabled Fig. 2.2.9 Related registers setting Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 17 of 202 APPLICATION 7643 Group 2.2 Timer RESET q X: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization SEI CPMA T123M T1 T2 ..... ..... ..... •All interrupts disabled (address 0016) (address 2916) (address 2416) (address 2516) (address 0316) (address 0616) (address 2916), bit1 10111XXX2 00XX011X2 9F16 6316 00XXXXXX2 0100000X2 0 •Connection of Timers 1 and 2 •Setting “Division ratio – 1” to Timers 1 and 2 IREQB ICONB T123M CLI ..... ✽ IREQB (address 0316), bit7 Main processing (Note) T2 IREQB (address 2516) (address 0316), bit7 6316 0 ..... Fig. 2.2.10 Control procedure Rev.2.00 Aug 28, 2006 REJ09B0133-0200 ..... •Setting of Interrupt request bits of Timers 1 and 2 to “0” •Timer 1 interrupt enabled, Timer 2 interrupt disabled •Timer count start •Interrupts enabled Clock is stopped ? N Y •Judgment whether time is not set or time is being set IREQB (address 0316), bit7 ? 0 •Confirmation that 1 s has passed (Check of Timer 2 interrupt request bit) 1 0 •Interrupt request bit cleared (Clear it by software when not using the interrupt.) Clock count up Second to Year •Clock count up •Adjust the main processing so that all processing in the loop ✽ will be processed within 1 s interval. •Set Timers again when starting clock from 0 s after end of clcok setting. •Do not set Timer 1 again because Timer 1 is used to generate the interrupt at 10 ms intervals. Note : Perform procedure for end of clock setting only when end of clock setting. page 18 of 202 APPLICATION 7643 Group 2.2 Timer (3) Timer application example 2: Piezoelectric buzzer output Outline: The rectangular waveform output function of the timer is applied for a piezoelectric buzzer output. Specifications: •The rectangular waveform, dividing the clock f(XIN) = 4.19 MHz (222 Hz) into about 2 kHz (2048 Hz), is output from the P5 1/T OUT/X COUT p in. • The level of the P5 1/T OUT/X COUT p in is fixed to “ H ” w hile a piezoelectric buzzer output stops. Figure 2.2.11 shows a peripheral circuit example, and Figure 2.2.12 shows the timers connection and setting of division ratios. Figure 2.2.13 shows the related registers setting, and Figure 2.2.14 shows the control procedure. The “H” level is output while a piezoelectric buzzer output stops. TOUT output P51/TOUT/XCOUT 244 µs 244 µs Set a division ratio so that the underflow output period of the timer 1 can be 244 µs. 7643 Group PiPiPi..... Fig. 2.2.11 Peripheral circuit example Count source selection φ/8 f(XIN) 4.19 MHz 1/2 1/8 Timer 1 1/64 Fixed 1/2 P51/TOUT/XCOUT Fig. 2.2.12 Timers connection and setting of division ratios Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 19 of 202 APPLICATION 7643 Group 2.2 Timer Clock control register (address 1F16) b7 b0 CCR 1 00000 System clock: f(XIN) CPU mode register A (address 0016) b7 b0 CPMA 000 1 Processor mode bits Stack page select bit Main clock (XIN-XOUT): Oscillating External clock: XIN-XOUT Port P5 (address 1616) b7 b0 P5 0116 Set an initial value. Port P5 direction register (address 1716) b7 b0 P5D 1 Set to output mode. Timer 123 mode register (address 2916) b7 b0 T123M 010 000 TOUT factor: Timer 1 Timer 1: stop Timer 1 count source: φ / 8 TOUT output active edge: start at “H” output TOUT output : enabled Timers 1, 2 write control: write value in latch and counter Timer 1 (address 2416) b7 b0 T1 3F16 Set “division ratio – 1” = 63 (3F16) Interrupt control register B (address 0616) b7 b0 ICONB 000000 Timer 1 interrupt: Disabled Fig. 2.2.13 Relevant registers setting Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 20 of 202 APPLICATION 7643 Group 2.2 Timer RESET Initialization SEI CCR CPMA P5 P5D T123M T1 ICONB (address 1F16), bit7 (address 0016) (address 1616), bit1 (address 1716), bit1 (address 2916) (address 2416) (address 0616), bit6 1 000X1XXX2 1 1 010XX0002 3F16 0 •All interrupts disabled •φ = f(XIN)/2 •Port P51/TOUT/XCOUT state setting at buzzer output stopped; “H” level output CLI •Timer 1 interrupt disabled •TOUT output stopped; Buzzer output stopped •Interrupts enabled Main processing Output unit Piezoelectric buzzer request ? Yes Stop of piezoelectric buzzer output Fig. 2.2.14 Control procedure Rev.2.00 Aug 28, 2006 REJ09B0133-0200 .... . No T123M (address 2916), bit1 T1 (address 2416) 1 3F16 •Processing buzzer request, generated during main processing, in output unit T123M(address 2916), bit1 0 Start of piezoelectric buzzer output page 21 of 202 APPLICATION 7643 Group 2.2 Timer 2.2.4 Notes on timer (1) Read/Write for timer • The timer division ratio is : 1 / (n + 1) (n = “ 0 ” t o “ 255 ” w ritten into the timer) • When the value is loaded only in the latch, the value is loaded in the timer at the count pulse following the count where the timer reaches “ 00 16” . • In the timers 1 to 3, switching of the count sources of timers 1 to 3 does not affect the values of reload latches. However, that may make count operation started. Therefore, write values again in the order of timers 1, 2 and then timer 3 after their count sources have been switched. • The timer current count value can be read out by reading the timer. (2) Pulse output • When using the T OUT o utput of timer 1 or timer 2, set bit 1 of port P5 direction register to “ 1 ” (output mode). •The T OUT output pin is shared with the XCOUT pin. Accordingly, when using f(XCIN)/2 as the timer 1 count source (bit 2 of timer 123 mode register = “0”), X COUT oscillation drive must be disabled (bit 5 of clock control register = “ 1 ” ) to input clocks from the X CIN p in. •The P51/XCOUT/TOUT pin cannot function as an ordinary I/O port while XCIN-XCOUT is oscillating. When XCIN-XCOUT oscillation is stopped or X COUT oscillation drive is disabled, this can be used as the T OUT output pin of timer 1 or 2. (3) STP instruction When the reset or STP instruction is being executed, “0116” is set to the timer 2 and timer 2 latch, and “FF16” is set to the timer 1 and timer 1 latch, and the timer 1 output is forcibly set as the timer 2 count source. Also, all bits except bit 4 of the timer 123 mode register (address 0029 16) are initialized to “ 0 ” . After returning from Stop Mode, reset the timer 1 (address 0024 16), timer 2 (address 002516 ), and the timer 123 mode register (address 0029 16). Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 22 of 202 APPLICATION 7643 Group 2.3 Serial I/O 2.3 Serial I/O This paragraph explains the registers setting method and the notes related to the serial I/O. 2.3.1 Memory map Address 000416 000716 Interrupt request register C (IREQC) Interrupt control register C (ICONC) 002A16 002B16 002C16 Serial I/O shift register (SIOSHT) Serial I/O control register 1 (SIOCON1) Serial I/O control register 2 (SIOCON2) Fig. 2.3.1 Memory map of registers related to serial I/O Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 23 of 202 APPLICATION 7643 Group 2.3 Serial I/O 2.3.2 Related registers Serial I/O shift register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O shift register (SIOSHT: address 2A16) b Functions At reset R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 qAt transmitting Writing transmitted data to this register starts transmitting operation. 1 2 qAt receiving Read received data through this register. 3 4 5 6 7 Fig. 2.3.2 Structure of Serial I/O shift register Serial I/O control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O control register 1 (SIOCON1 : address 2B16) b Name b2b1b0 Functions 0 0 0 : φ/2 0 0 1 : φ/4 0 1 0 : φ/8 0 1 1 : φ/16 1 0 0 : φ/32 1 0 1 : φ/64 1 1 0 : φ/128 1 1 1 : φ/256 At reset R W 0 0 Internal synchronous clock select bits 1 2 3 Serial I/O port select bit 4 5 6 7 0 0 0 : I/O port 1 : STXD, SCLK signal output 0 : I/O port SRDY output select bit 1 : SRDY signal output Transfer direction select bit 0 : LSB first 1 : MSB first Synchronous clock select 0 : External input (SCLK pin input) 1 : Internal synchronous clock bit STXD output channel 0 : CMOS output control bit 1 : N-channel open drain output 0 0 0 1 0 Fig. 2.3.3 Structure of Serial I/O control register 1 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 24 of 202 APPLICATION 7643 Group 2.3 Serial I/O Serial I/O control register 2 b7 b6 b5 b4 b3 b2 b1 b0 000 0 Serial I/O control register 2 (SIOCON2 : address 2C16) b Name Functions At reset R W 0 0 0 1 1 0 SPI mode select bit 1 2 3 4 5 6 7 0 : Normal serial I/O mode 1 : SPI compatible mode (Note) Nothing is arranged for this bit. Fix this bit to “0”. SRXD input enable bit 0 : SRXD input disabed 1 : SRXD input enabed Clock polarity select bit 0 : SCLK starting at “L” (CPoL) 1 : SCLK starting at “H” 0 : Serial transfer starting at falling edge Clock phase select bit of SRDY (CPha) 1 : Serial transfer starting after a half cycle of SCLK passed at falling edge of SRDY Nothing is arranged for these bits. Fix these bits to “0”. 0 0 0 Note: To set the slave mode, also set bit 4 of serial I/O control register 1 to “1”. Fig. 2.3.4 Structure of Serial I/O control register 2 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 25 of 202 APPLICATION 7643 Group 2.3 Serial I/O Interrupt request register C b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register C (IREQC : address 0416) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 ✽ ✽ ✽ 0 Timer 3 interrupt request bit 1 Nothing is arranged for these bits. When these bits are read out, the contents are undefined. 2 These bits are “0” at write. 3 Serial I/O interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit 4 Nothing is arranged for these bits. When these bits are read out, the contents are undefined. 5 These bits are “0” at write. 6 Key input interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit 7 Nothing is arranged for this bit. Fix this bit to “0”. ✽: “0” can be set by software, but “1” cannot be set. Fig. 2.3.5 Structure of Interrupt request register C Interrupt control register C b7 b6 b5 b4 b3 b2 b1 b0 0 00 00 Interrupt control register C (ICONC : address 0716) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 Timer 3 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 1 Nothing is arranged for these bits. 2 Fix these bits to “0”. 3 Serial I/O interrupt enable 0 : Interrupt disabled 1 : Interrupt enabled bit 4 Nothing is arranged for these bits. 5 Fix these bits to “0”. 6 Key input interrupt enable 0 : Interrupt disabled 1 : Interrupt enabled bit 7 Nothing is arranged for this bit. Fix this bit to “0”. Fig. 2.3.6 Structure of Interrupt control register C Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 26 of 202 APPLICATION 7643 Group 2.3 Serial I/O 2.3.3 Serial I/O connection examples (1) Control of peripheral IC equipped with CS pin Figure 2.3.7 shows connection examples of a peripheral IC equipped with the CS pin. (1) Only transmission (Using the SRXD pin as an I/O port) Port SCLK STXD CS CLK DATA (2) Transmission and reception Port SCLK STXD SRXD 7643 group CS CLK IN OUT Peripheral IC 2 (E PROM etc.) 7643 group Peripheral IC (OSD controller etc.) (3) Transmission and reception (When connecting SRXD with STXD) (When connecting IN with OUT in peripheral IC) Port SCLK STXD SRXD CS CLK IN (4) Connection of plural IC Port SCLK STXD SRXD Port 7643 group CS CLK IN OUT Peripheral IC 1 OUT 7643 group✽1 Peripheral IC ✽2 2 (E PROM etc.) Select an N-channel open-drain output for STXD pin output control. ✽2: Use the OUT pin of peripheral IC which is an N-channel opendrain output and becomes high impedance during receiving data. Notes : “Port” means an output port controlled by software. ✽1: CS CLK IN OUT Peripheral IC 2 Fig. 2.3.7 Serial I/O connection examples (1) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 27 of 202 APPLICATION 7643 Group 2.3 Serial I/O (2) Connection with microcomputer Figure 2.3.8 shows connection examples with another microcomputer. (1) Selecting internal synchronous clock (2) Selecting external clock (SLCK pin input) SCLK STXD SRXD 7643 group CLK IN OUT Microcomputer SCLK STXD SRXD 7643 group CLK IN OUT Microcomputer (3) Using SRDY signal output function (Selecting an external clock (SLCK pin input)) SRDY SCLK STXD SRXD 7643 group RDY CLK IN OUT Microcomputer Fig. 2.3.8 Serial I/O connection examples (2) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 28 of 202 APPLICATION 7643 Group 2.3 Serial I/O 2.3.4 Serial I/O application example (1) Output of serial data (control of peripheral IC) Outline : Serial communication is performed, connecting port to CS pin of peripheral IC. To perform reception, it needs to write dummy data into serial I/O shift register. Figure 2.3.9 shows a connection diagram, and Figure 2.3.10 shows a timing chart. P31 P81/SCLK P83/STXD CS CLK DATA CS CLK DATA 7643 group Peripheral IC Fig. 2.3.9 Connection diagram Specifications : • Synchronous clock frequency : 187.5 kHz (f(X IN) = 24 MHz ) • Transfer direction : LSB first • Serial I/O interrupt is not used. • Port P31 is connected to the CS pin (“L” active) of the peripheral IC for transmission control; the output level of port P3 1 i s controlled by software. CS CLK DATA DATA0 DATA1 DATA2 DATA3 Fig. 2.3.10 Timing chart Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 29 of 202 APPLICATION 7643 Group 2.3 Serial I/O Figure 2.3.11 shows the registers setting for the transmitter, and Figure 2.3.12 shows a setting of serial I/O transmission data. Serial I/O control register 1 (Address : 2B16) b7 b0 SIOCON1 01001100 Internal synchronous clock : φ/32 STXD, SCLK output selected SRDY output selected LSB first Internal synchronous clock STXD pin : CMOS output Serial I/O control register 2 (Address : 2C16) b7 b0 SIOCON2 00011100 Normal serial I/O mode SRXD input enabled Port P3 (Address : 0E16) b7 b0 P3 1 Set P31 output level to “H”. Port P3 direction register (Address : 0F16) b7 b0 P3D 1 Set P31 to output mode. Interrupt request register C (Address : 0416) b7 b0 IREQC 0 0 Serial I/O interrupt request bit Interrupt control register C (Address : 0716) b7 b0 ICONC 0 00000 Serial I/O interrupt : Disabled Fig. 2.3.11 Registers setting for transmitter Serial I/O shift register (Address : 2A16) b7 b0 SIOSHT Set a transmission data. Confirm that transmission of the previous data is completed (Serial I/O interrupt request bit is “1”) before writing data. Fig. 2.3.12 Setting of serial I/O transmission data Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 30 of 202 APPLICATION 7643 Group 2.3 Serial I/O When the registers are set as shown in Figure 2.3.13, the serial I/O can transmit 1-byte data by writing data into the serial I/O shift register. Thus, after setting the CS signal to “L”, write the transmission data to the serial I/O shift register by each 1 byte, and return the CS signal to “H” when all required data have been transmitted. Figure 2.3.13 shows a control procedure of transmitter. RESET Initialization SIOCON1 SIOCON2 P3 P3D IREQC ICONC CLI q x: This bit is not used here. Set it to “0” or “1” arbitrarily. SIOSHT (Address : 2A16) .... (Address : 2B16) 010011002 (Address : 2C16) 000111002 (Address : 0E16), bit1 1 (Address : 0F16), bit1 1 (Address : 0416), bit3 0 (Address : 0716), bit3 0 •Serial I/O set •CS signal output port set (“H” level output) •Serial I/O interrupt request bit set to “0” •Serial I/O interrupt disabled .... P3 (Address : 0E16), bit1 0 •CS signal output level to “L” set Transmission data •Transmission data write (Start of transmit 1-byte data) IREQC (Address : 0416), bit3? 1 0 •Judgment of completion of transmitting 1-byte data IREQC (Address : 0416), bit3 0 N Complete to transmit all data? Y •Return the CS signal output level to “H” when transmission of all data is completed •Use any of RAM area as a counter for counting the number of transmitted bytes •Judgment of completion of transmitting all data P3 (Address : 0E16), bit1 1 Fig. 2.3.13 Control procedure of transmitter Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 31 of 202 APPLICATION 7643 Group 2.3 Serial I/O (2) Serial communication using SPI compatible mode qExplanation of SPI compatible mode Setting the SPI mode select bit (bit 0 of SIOCON2) to “1” puts the serial I/O in SPI compatible mode. The synchronous clock select bit (bit 6 of SIOCON1) determines whether the serial I/O is an SPI master or slave. When the external clock (SCLK pin input) is selected (“0”), the serial I/O is in slave mode; when the internal synchronous clock is selected (“1”), the serial I/O is in master mode. In SPI compatible mode the SRXD pin functions as a MISO (Master In/Slave Out) pin and the STXD pin functions as a MOSI (Master Out/Slave In) pin. In slave mode the transmit data is output from the MISO pin and the receive data is input from the MISO pin. The SRDY pin functions as the chip-select signal input pin from an external. In master mode the transmit data is output from the MOSI pin and the receive data is input from the MISO pin. The SRDY pin functions as the chip-select signal output pin to an external. qSlave mode operation In slave mode of SPI compatible mode 4 types of clock polarity and clock phase can be usable by bits 3 and 4 of serial I/O control register 2. If the SRDY pin is held “H”, the shift clock is inhibited, the serial I/O counter is set to “7”. If the SRDY pin is held “ L ” , then the shift clock will start. Make sure during transfer to maintain the SRDY input at “L” and not to write data to the serial I/O counter. Outline : Serial communication is performed between 7643 group MCUs, using SPI compatible mode. Specifications : • Synchronous clock frequency : 187.5 kHz (f(X IN) = 24 MHz ) • Transfer direction : LSB first Figure 2.3.14 shows a connection diagram; Figure 2.3.15 shows the registers setting for SPI compatible mode; Figures 2.3.16 and 2.3.17 show a control procedure of SPI compatible mode. Slave unit P80/SRDY P81/SCLK P82/MISO P83/MOSI 7643 group Fig. 2.3.14 Connection diagram Master unit CS CLK DATA DATA P80/SRDY P81/SCLK P82/MISO P83/MOSI 7643 group Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 32 of 202 APPLICATION 7643 Group 2.3 Serial I/O qSlave Unit Serial I/O control register 1 (Address : 2B16) b7 b0 SIOCON1 00011 STXD, SCLK output selected SRDY output selected LSB first External clock (SCLK pin input) STXD pin : CMOS output Serial I/O control register 2 (Address : 2C16) b7 b0 SIOCON2 00011101 SPI compatible mode SRXD input enabled SCLK starting at “H” Serial transfer starting afer a half cycle of SCLK passed at falling edge of SRDY Interrupt control register C (Address : 0716) b7 b0 ICONC 0 00000 Serial I/O interrupt : Disabled qMaster Unit Serial I/O control register 1 (Address : 2B16) b7 b0 SIOCON1 01001100 Internal synchronous clock : φ/32 STXD, SCLK output selected No SRDY output LSB first Internal synchronous clock STXD pin : CMOS output Serial I/O control register 2 (Address : 2C16) b7 b0 SIOCON2 00011100 SPI compatible mode SRXD input enabled SCLK starting at “H” Serial transfer starting afer a half cycle of SCLK passed at falling edge of SRDY Interrupt control register C (Address : 0716) b7 b0 ICONC 0 00000 Serial I/O interrupt : Disabled Fig. 2.3.15 Registers setting for SPI compatible mode Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 33 of 202 APPLICATION 7643 Group 2.3 Serial I/O Slave Unit RESET Initialization SIOCON1 (Address : 2B16) SIOCON2 (Address : 2C16) IREQC ICONC CLI .... .... .... q x: This bit is not used here. Set it to “0” or “1” arbitrarily. 00011XXX2 000111012 0 0 •Serial I/O set (Address : 0416), bit3 (Address : 0716), bit3 •Serial I/O interrupt request bit set to “0” •Serial I/O interrupt disabled SIOSHT (Address : 2A16) Transmission data •Transmission data write (Do not set data during data reception.) IREQC (Address : 0416), bit3? 1 Read out received data from SIOSHT (Address : 2A16) 0 •Judgment of completion of receiving 1-byte data •Transmission/Reception starts owing to “L” input to P80/SRDY pin or shift clock input. IREQC (Address : 0416), bit3 0 Fig. 2.3.16 Control procedure of SPI compatible mode in slave Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 34 of 202 APPLICATION 7643 Group 2.3 Serial I/O Master Unit RESET Initialization SIOCON1 SIOCON2 IREQC ICONC CLI .... .... q x: This bit is not used here. Set it to “0” or “1” arbitrarily. (Address : 2B16) 010111012 (Address : 2C16) 000111012 (Address : 0416), bit3 0 (Address : 0716), bit3 0 •Serial I/O set •Serial I/O interrupt request bit set to “0” •Serial I/O interrupt disabled SIOSHT (Address : 2A16) Transmission data •Transmission data write (Start of transmit 1-byte data) •Then P80/SRDY pin set to “L” IREQC (Address : 0416), bit3? 1 Read out received data from SIOSHT (Address : 2A16) 0 •Judgment of completion of transmitting 1-byte data •“L” output from P80/SRDY pin IREQC (Address : 0416), bit3 0 N Complete to transmit all data? Y •Use any of RAM area as a counter for counting the number of transmitted bytes •Judgment of completion of transmitting all data Fig. 2.3.17 Control procedure of SPI compatible mode in master Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 35 of 202 APPLICATION 7643 Group 2.3 Serial I/O 2.3.5 Notes on serial I/O (1) Clock When the external clock (SCLK pin input) is selected as the transfer clock, its transfer clock needs to be controlled by the external source because the serial I/O shift register will keep being shifted while transfer clock is input even after transfer completion. (2) Reception When the external clock (SCLK pin input) is selected as the transfer clock for reception, the receiving operation will start owing to the shift clock input even if write operation to the serial I/ O shift register (SIOSHT) is not performed. The serial I/O interrupt request also occurs at completion of receiving. However, we recommend to write dummy data in the serial I/O shift register. Because this will cause followings and improve transfer reliability. •Write to SIOSHT puts the SRDY pin to “L”. This enables shift clock output of an external device. • Write to SIOSHT clears the internal serial I/O counter. Note: Do not read the serial I/O shift register which is shifting. Because this will cause incorrectdata read. (3) STXD output •When the internal synchronous clock is selected as the transfer clock, the STXD pin goes a highimpedance state after transfer completion. • When the external clock (SCLK pin input) is selected as the transfer clock, the STXD pin does not go a high-impedance state after transfer completion. (4) SPI compatible mode • When using the SPI compatible mode, set the SRDY select bit to “ 1 ” ( SRDY signal output). • When the external clock is selected in SPI compatible mode, the SRXD pin functions as a data output pin and the STXD pin functions as a data input pin. • Do not write to the serial I/O shift register (SIOSHT) during a transfer as slave when in SPI compatible mode. • Master operation of SPI compatible mode requires the timings: -From write operation to the SIOSHT to SRDY pin put to “ L ” Requires 2 cycles of internal clock φ + 2 c ycles of serial I/O synchronous clock + 35 ns -From SRDY pin put to “ L ” t o SCLK switch Requires 35 ns -From the last pulse of SCLK to SRDY pin put to “ H ” Requires 35 ns. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 36 of 202 APPLICATION 7643 Group 2.4 UART 2.4 UART This paragraph explains the registers setting method and the notes related to the UART. 2.4.1 Memory map Address 000216 000316 000516 000616 003016 003116 003216 003316 003416 003516 003616 Interrupt request register A (IREQA) Interrupt request register B (IREQB) Interrupt control register A (ICONA) Interrupt control register B (ICONB) UART mode register (UMOD) UART baud rate generator (UBRG) UART status register (USTS) UART control register (UCON) UART transmit/receive buffer register 1 (UTRB1) UART transmit/receive buffer register 2 (UTRB2) UART RTS control register (URTSC) Fig. 2.4.1 Memory map of registers related to UART Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 37 of 202 APPLICATION 7643 Group 2.4 UART 2.4.2 Related registers UART mode register b7 b6 b5 b4 b3 b2 b1 b0 0 UART mode register (UMOD : address 3016) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 Nothing is arranged for this bit. Fix this bit to “0”. b2b1 1 UART clock prescaling 0 0 : φ/1 select bits (PS) 0 1 : φ/8 2 1 0 : φ/32 1 1 : φ/256 Stop bit length select bit 0 : 1 stop bit 3 (STB) 1 : 2 stop bits 0 : Even parity 4 Parity select bit (PMD) 1 : Odd parity 5 Parity enable bit (PEN) 0 : Parity checking disabled 1 : Parity checking enabled b7b6 6 UART character length 0 0 : 7 bits select bit (LE1, 0) 0 1 : 8 bits 7 1 0 : 9 bits 1 1 : Not available Fig. 2.4.2 Structure of UART mode register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 38 of 202 APPLICATION 7643 Group 2.4 UART UART control register b7 b6 b5 b4 b3 b2 b1 b0 UART control register (UCON : address 3316) b Name Functions 0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled 0 : No action 1 : Initializing (Note 1) 0 : No action 1 : Initializing (Note 2) 0 : Interrupt when transmit buffer has emptied 1 : Interrupt when transmit shift operation is completed 0 : CTS function disabled (Note 3) 1 : CTS function enabled 0 : RTS function disabled (Note 4) 1 : RTS function enabled 0 : Address mode disabled 1 : Address mode enabled At reset R W 0 0 0 0 0 0 Transmit enable bit (TEN) 1 Receive enable bit (REN) 2 Transmit initialization bit (TIN) 3 Receive initialization bit (RIN) 4 Transmit interrupt source select bit (TIS) 5 CTS function enable bit (CTS_SEL) 6 RTS function enable bit (RTS_SEL) UART address mode 7 enable bit (AME) 0 0 0 Notes 1: When setting the TIN bit to “1”, the TEN bit is set to “0” and the UART status register will be set to “0316” after the data has been transmitted. To retransmit, set the TEN bit to “1” and set a data to the transmit buffer register again. The TIN bit will be cleared to “0” one cycle later after the TIN bit has been set to “1”. 2: Setting the RIN bit to “1” suspends the receiving operation and will set all of the REN, RBF and the receive error flags (PER, FER, OER, SER) to “0”. The RIN bit will be cleared to “0” one cycle later after the RIN bit has been set to “1”. 3: When CTS function is disabled (CTS_SEl = “0”), P86 pin can be used as ordinary I/O ports. 4: When RTS function is disabled (RTS_SEl = “0”), P83 pin can be used as ordinary I/O ports. Fig. 2.4.3 Structure of UART control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 39 of 202 APPLICATION 7643 Group 2.4 UART UART status register b7 b6 b5 b4 b3 b2 b1 b0 UART status register (USTS : address 3216) b Name Functions 0 : Transmit shift in progress 1 : Transmit shift completed 0 : Buffer full 1 : Buffer empty 0 : Buffer empty 1 : Buffer full 0 : No error 1 : Parity error 0 : No error At reset R W 1 1 0 0 0 0 0 0 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ 0 Transmit complete flag (TCM) 1 Transmit buffer empty flag (TBE) 2 Receive buffer full flag (RBF) 3 Parity error flag (PER) 4 Framing error flag (FER) 5 Overrun error flag (OER) 0 : No error 1 : Overrun error 6 Summing error flag (SER) 0 : (PER) U (FER) U (OER) = 0 1 : (PER) U (FER) U (OER) = 1 Nothing is arranged for this bit. This is a write disable bit. When this 7 bit is read out, the contents are “0”. Fig. 2.4.4 Structure of UART status register UART RTS control register b7 b6 b5 b4 b3 b2 b1 b0 0000 UART RTS control register (URTSC : address 3616) b Name Functions At reset R W 0 0 0 0 0 0 Nothing is arranged for these bits. 1 Fix these bits to “0”. 2 3 4 RTS assertion delay count b7b6b5b4 0 0 0 0 : No delay; Assertion immediately select bits (RTS) 0 0 0 1 : 8-bit term assertion at “H” 0 0 1 0 : 16-bit term assertion at “H” 0 0 1 1 : 24-bit term assertion at “H” 5 0 1 0 0 : 32-bit term assertion at “H” 0 1 0 1 : 40-bit term assertion at “H” 0 1 1 0 : 48-bit term assertion at “H” 0 1 1 1 : 56-bit term assertion at “H” 6 1 0 0 0 : 64-bit term assertion at “H” 1 0 0 1 : 72-bit term assertion at “H” 1 0 1 0 : 80-bit term assertion at “H” 1 0 1 1 : 88-bit term assertion at “H” 7 1 1 0 0 : 96-bit term assertion at “H” 1 1 0 1 : 104-bit term assertion at “H” 1 1 1 0 : 112-bit term assertion at “H” 1 1 1 1 : 120-bit term assertion at “H” 0 0 1 Fig. 2.4.5 Structure of UART RTS control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 40 of 202 APPLICATION 7643 Group 2.4 UART UART baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 UART baud rate generator (UBRG: address 3116) b Functions At reset R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 qThe UBRG determines the baud rate for transfer. 1 qThis is a 8-bit counter with its reload register. This generator divides the frequency of the count source by 1/(n + 1), where “n” is the 2 value written to the UBRG. 3 4 5 6 7 Fig. 2.4.6 Structure of UART baud rate generator Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 41 of 202 APPLICATION 7643 Group 2.4 UART UART transmit/receive buffer registers 1, 2 b7 b6 b5 b4 b3 b2 b1 b0 UART transmit/receive buffer register 1 (UTRB1: address 3416) b 0 1 2 3 4 5 6 Functions The transmit buffer register and the receive buffer register are located at the same address. Writing a transmitting data and reading a received data are performed through the UTRB. This is its low-order byte. •At write The data is written into the transmit buffer register. It is not done into the receive buffer register. •At read The contents of receive buffer register is read. If a character bit length is 7 bits, the MSB of received data is invalid. At reset R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 Note that the contents of transmit buffer register cannot be read. b7 b6 b5 b4 b3 b2 b1 b0 UART transmit/receive buffer register 2 (UTRB2: address 3516) b Functions At reset R W 0 The transmit buffer register and the receive buffer register are located Undefined at the same address. Writing a transmitting data and reading a received data are performed through the UTRB. This is its high-order byte. •At write The data is written into the transmit buffer register. It is not done into the receive buffer register. •At read The contents of receive buffer register is read. If a character bit length is 9 bits, the received high-order 7 bits of UTRB2 are “0” Note that the contents of transmit buffer register cannot be read. If a character bit length is 7 or 8 bits, the received contents of UTRB2 are invalid. 1 Nothing is arranged for these bits. These are write disable bits. 2 When these bits are read out, the contents are “0”. 3 4 5 6 7 Undefined Undefined Undefined Undefined Undefined Undefined Undefined ✕ ✕ ✕ ✕ ✕ ✕ ✕ Fig. 2.4.7 Structure of UART transmit/receive buffer registers 1, 2 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 42 of 202 APPLICATION 7643 Group 2.4 UART Interrupt request register A b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register A (IREQA : address 0216) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 ✽ ✽ ✽ ✽ ✽ ✽ ✽ 0 USB function interrupt request bit 1 Nothing is arranged for this bit. When this bit is read out, the contents are undefined. This bit is “0” at write. 0 : No interrupt request issued 2 INT0 interrupt request bit 1 : Interrupt request issued 3 INT1 interrupt request bit 4 DMAC0 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 5 DMAC1 interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit 0 : No interrupt request issued 6 UART receive buffer full 1 : Interrupt request issued interrupt request bit UART transmit interrupt 0 : No interrupt request issued 7 request bit 1 : Interrupt request issued ✽: “0” can be set by software, but “1” cannot be set. Fig. 2.4.8 Structure of Interrupt request register A Interrupt request register B b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register B (IREQB : address 0316) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 ✽ 0 UART summing error interrupt request bit 1 2 3 4 5 6 Nothing is arranged for these bits. When these bits are read out, the contents are undefined. These bits are “0” at write. 0 : No interrupt request issued Timer 1 interrupt request 1 : Interrupt request issued bit 0 : No interrupt request issued 7 Timer 2 interrupt request bit 1 : Interrupt request issued ✽: “0” can be set by software, but “1” cannot be set. ✽ ✽ Fig. 2.4.9 Structure of Interrupt request register B Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 43 of 202 APPLICATION 7643 Group 2.4 UART Interrupt control register A b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt control register A (ICONA : address 0516) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 0 0 0 0 0 0 USB function interrupt enable bit 1 Nothing is arranged for this bit. Fix this bit to “0”. 0 : Interrupt disabled 2 INT0 interrupt enable bit 1 : Interrupt enabled 3 INT1 interrupt enable bit 4 DMAC0 interrupt enable bit 5 DMAC1 interrupt enable bit 6 UART receive buffer full interrupt enable bit 7 UART transmit interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Fig. 2.4.10 Structure of Interrupt control register A Interrupt control register B b7 b6 b5 b4 b3 b2 b1 b0 00000 Interrupt control register B (ICONB : address 0616) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 0 0 0 0 0 0 UART summing error interrupt enable bit 1 Nothing is arranged for these bits. 2 Fix these bits to “0”. 3 4 5 6 Timer 1 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 7 Timer 2 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled Fig. 2.4.11 Structure of Interrupt control register B Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 44 of 202 APPLICATION 7643 Group 2.4 UART 2.4.3 UART transfer data format Figure 2.4.12 shows the UART transfer data format. 1ST-9DATA-1SP ST LSB MSB SP 1ST-8DATA-1SP ST LSB MSB SP 1ST-7DATA-1SP ST LSB MSB SP 1ST-9DATA-1PAR-1SP ST LSB MSB PAR SP 1ST-8DATA-1PAR-1SP ST LSB MSB PAR SP 1ST-7DATA-1PAR-1SP UART ST LSB MSB PAR SP 1ST-9DATA-2SP ST LSB MSB 2SP 1ST-8DATA-2SP ST LSB MSB 2SP 1ST-7DATA-2SP ST LSB MSB 2SP 1ST-9DATA-1PAR-2SP ST LSB MSB PAR 2SP 1ST-8DATA-1PAR-2SP ST LSB MSB PAR 2SP 1ST-7DATA-1PAR-2SP ST LSB MSB PAR 2SP Fig. 2.4.12 UART transfer data format Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 45 of 202 APPLICATION 7643 Group 2.4 UART 2.4.4 Transfer bit rate Table 2.4.1 shows setting examples of the baud rate generator (BRG) values and transfer bit rate values. The internal clock φ i s selected for the UART clock. Table 2.4.1 Setting examples of baud rate generator values and transfer bit rate values (φ = 12 MHz)) φ /8 ( Note 1 ) φ /1 ( Note 1 ) BRG setting Transfer BRG setting Transfer bit rate (bps) value bit rate (bps) value 00 (00 16) 750,000.0 01 (01 16) 375,000.0 02 (02 16) 250,000.0 03 (03 16) 187,500.0 04 (04 16) 150,000.0 05 (05 16) 125,000.0 06 (06 16) 107,142.9 07 (07 16) 93,750.0 00 (00 16) 93,750.0 08 (08 16) 83,333.3 01 (01 16) 46,875.0 31,250.0 09 (09 16) 75,000.0 02 (02 16) 68,181.8 03 (03 16) 23,437.5 10 (0A 16) 65,250.0 04 (04 16) 18,750.0 11 (0B 16) 15,625.0 12 (0C 16) 57,692.3 05 (05 16) 13 (0D 16) 53,571.4 06 (06 16) 13,392.8 50,000.0 07 (07 16) 11,718.7 14 (0E 16) 10,416.6 15 (0F 16) 46,875.0 08 (08 16) 09 (09 16) 9,375.0 8,522.7 10 (0A 16) 11 (0B 16) 7,812.5 12 (0C 16) 7,211.5 6,696.4 13 (0D 16) 14 (0E 16) 6,250.0 15 (0F 16) 5,859.3 ○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○ ○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○ ○○○○○○○○○○○○○○○○○○ ○○○○○○○○○○○○○○○○○○ φ /32 ( Note 1 ) φ /256 ( Note 1) BRG setting Transfer BRG setting Transfer bit value bit rate (bps) value rate (bps) 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 (00 16) (01 16) (02 16) (03 16) (04 16) (05 16) (06 16) (07 16) (08 16) (09 16) (0A 16) (0B 16) (0C16) (0D16) (0E 16) (0F 16) ○○○○○○○○○○○○○○ 23,437.5 11,718.7 7,812.5 5,859.4 4,687.5 3,906.3 3,348.2 2,929.7 2,604.2 2,343.7 2,130.6 1,953.1 1,802.8 1,674.1 1,562.5 1,464.8 ○○○○○○○○○○○○○○ 00 (0016) 01 (0116) 02 (0216) 03 (0316) 04 (0416) 05 (0516) 06 (0616) 07 (0716) 08 (0816) 09 (0916) 10 (0A16) 11 (0B16) 12 (0C16) 13 (0D16) 14 (0E16) 15 (0F 16) ○○ 2,929.7 1,464.8 976.6 732.4 585.9 488.3 418.5 366.2 325.5 292.9 266.3 244.1 225.3 209.2 195.3 183.1 ○○ 253 (FD 16) 2,952.7 253 (FD16) 254 (FE 16) 2,941.1 254 (FE 16) 255 (FF 16) 2,929.7 255 (FF 16) Notes 1: S elect the UART clock prescaling 2: E quation of transfer bit rate: Transfer bit rate (bps) = 369.0 253 (FD 16) 367.6 254 (FE 16) 366.2 255 (FF 16) with bits 1 and 2 of UART 92.2 253 (FD16) 91.9 254 (FE 16) 91.6 255 (FF 16) mode register. 11.5 11.4 11.4 fi ✽ (BRG setting value + 1) ✕ 1 6 ✽ : fi is selectable among φ/1, φ/8, φ/32, and φ/256 with bits 1 and 2 of UART mode register. page 46 of 202 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 APPLICATION 7643 Group 2.4 UART 2.4.5 Operation of transmitting and receiving (1) Transmit operation •The transmit buffer empty flag (TBE) is set to “0” when the low-order byte of transmitted data is written into the UART transmit buffer register 1 in the condition of transmission enabled. When using 9-bit character length, set the data into the UART transmit buffer register 2 (high-order byte) first before the UART transmit buffer register 1 (low-order byte). • If the transmit shift register is empty in the condition of CTS function disabled, the transmitted data which is written into the UART transmit buffer register 1 will be transferred to the transmit shift register at the same time. When the TBE flag becomes “ 1 ” , the following data can be set to the UART transmit buffer. At this point, the UART transmit interrupt request occurs when the transmit interrupt source select bit (TIS) is “ 0 ” . • When the CTS function is enabled, the transmitted data is not transferred to the transmit shift register until “ L ” i s input to the CTS pin (P8 6/CTS). •The data is transmitted with the LSB first format. Once the transmission starts, it continues until the last bit has been transmitted even though clearing the transmit enable bit (TEN) to “ 0 ” (disabled) or inputting “ H ” t o the CTS pin. •After completion of the last bit transmitting, if the TBE flag is “1”, or the TEN bit is “0” (disabled) or “ H ” i s input to the CTS pin, the transmit complete flag (TCM) goes to “ 1 ” . At this point, the UART transmit interrupt request occurs when the TIS bit is “ 1 ” . (2) Receive operation • The data is received with the LSB first format in the condition of reception enabled. • When the stop bit is detected, the received data is transferred from the receive shift register to the UART receive buffer register. At the same time, if there is no error, the receive buffer full flag (RBF) is set to “ 1 ” a nd the UART receive buffer full interrupt request occurs. • If receive errors occur, the corresponding error flags of UART status register are set to “ 1 ” a nd the UART summing error interrupt request occurs. •The receive buffer full flag (RBF) is set to “0” when the contents of UART receive buffer register 1 is read out. Then when the RTS function is disabled, the following data can be received. When using 9-bit character length, read the data from the UART receive buffer register 2 (highorder byte) first before the UART receive buffer register 1 (low-order byte). •When the RTS function is enabled, the RTS assertion delay count is specified by the UART RTS control register. The delay time from the reception of the last stop bit to the start bit is selectable. The RTS pin (P87/RTS) outputs “H” during the delayed time. After that, the RTS pin outputs “L” and a reception is enabled. • If the start bit is detected in the term of “ H ” a ssertion of RTS, its assertion count is suspended and the RTS pin remains “ H ” o utput. After receiving the last stop bit, the count is resumed. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 47 of 202 APPLICATION 7643 Group 2.4 UART (3) Countermeasure for errors Three errors can be detected at reception. Each error is detected simultaneously when the data is transferred from the receive shift register to the receive buffer register. If receive errors occur, the corresponding error flags of UART status register are set to “ 1 ” . When any one of errors occurs, the summing error flag is set to “ 1 ” a nd the UART summing error interrupt request bit is also set to “ 1 ” . If a receive error occurs, the reception does not set the UART receive buffer full interrupt request bit to “ 1 ” . If receive errors occur, initialize the error flags and the UART receive buffer register and then retransmit the data. Table 2.4.3 shows the error flags set condition and how to clear error flags. Table 2.4.3 Error flags set condition and how to clear error flags Error flag Overrun flag (OER) Error flag set condition How to clear error flag •If the previous data in the receive buffer register • Reading UART status register is not read before the current receive operation •Hardware reset is completed. •Setting the receive initialization •If any one of error flags is “1” for the previous bit (RIN) to “ 1 ” data and the current receive operation is completed. F r a m i n g e r r o r f l a g • When the number of stop bit of the received (FER) data does not correspond with the selection with the stop bit length select bit (STB). Parity error flag (PER) •When the sum total of 1s of received data and the parity does not correspond with the selection with the parity select bit (PMD). Summing error flag • When any one of the PER, FER and OER is (SER) set to “ 1 ” . Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 48 of 202 APPLICATION 7643 Group 2.4 UART 2.4.6 UART application example (1) Data output (control of peripheral IC) Outline : Data is transmitted and received, using the UART. Figure 2.4.13 shows a connection diagram, and Figure 2.4.14 shows a timing chart. Transmitting side P84/UTXD P85/URXD P86/CTS Receiving side P84/UTXD P85/URXD P87/RTS 7643 group 7643 group Fig. 2.4.13 Connection diagram Specifications : • Transmitter: UART is used. • Receiver: UART is used. • Transfer bit rate : 9600 bps (φ = 1 2 MHz divided by 1248) • Data format: 1ST-8DATA-2SP • Use of CTS and RTS functions • 2-byte data is transferred from the transmitting side to the receiving side at intervals of 10 ms generated by the timer. P86/CTS P84/UTXD ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2) ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2) ST D0 ••• 10 ms Fig. 2.4.14 Timing chart Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 49 of 202 APPLICATION 7643 Group 2.4 UART Figure 2.4.15 shows the registers setting for the transmitter, and Figures 2.4.16 and 2.4.17 show the registers setting for the receiver. Transmitting side UART mode register (Address : 3016) b7 b0 UMOD 010 1000 UART clock : φ/1 Stop bit length : 2 stop bits Parity checking disabled Character length : 8 bits UART control register (Address : 3316) b7 b0 UCON 001 101 Transmit enabled Receive disabled Transmit initializing CTS function enabled RTS function disabled UART address mode disabled UART baud rate generator (Address : 3116) b7 b0 UBRG 4D16 Interrupt control register A (Address : 0516) b7 b0 ICONA 0 0 UART transmit interrupt disabled UART transmit/receive buffer register 2 (Address : 3516) b7 b0 UTRB2 high-order 1 bit of transmitting data set UART transmit/receive buffer register 1 (Address : 3416) b7 b0 UTRB1 low-order 8 bits of transmitting data set UART status register (Address : 3216) b7 b0 Write data to high-order address first, then to low-order address. USTS Transmit complete flag Transmit buffer empty flag Fig. 2.4.15 Registers setting for transmitter Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 50 of 202 APPLICATION 7643 Group 2.4 UART Receiving side UART mode register (Address : 3016) b7 b0 UMOD 010 0000 UART clock : φ/1 Stop bit length : 2 stop bits Parity checking disabled Character length : 8 bits UART control register (Address : 3316) b7 b0 UCON 010 1 10 Transmit disabled Receive enabled Receive initializing CTS function disabled RTS function enabled UART address mode disabled UART RTS control register (Address : 3616) b7 b0 URTSC 00000000 No delay; Assertion immediately Interrupt control register A (Address : 0516) b7 b0 ICONA 0 UART receive buffer full interrupt disabled Interrupt control register B (Address : 0616) b7 b0 ICONB 000000 UART summing error interrupt disabled UART baud rate generator (Address : 3116) b7 b0 UBRG 4D16 Fig. 2.4.16 Registers setting for receiver (1) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 51 of 202 APPLICATION 7643 Group 2.4 UART UART transmit/receive buffer register 2 (Address : 3416) b7 b0 UTRB2 high-order 1 bit of receiving data read UART transmit/receive buffer register 1 (Address : 3316) b7 b0 UTRB1 low-order 8 bits of receiving data read UART status register (Address : 3216) b7 b0 Read data from high-order address first, then from low-order address. USTS Receive buffer full flag Parity error flag Framing error flag Overrun error flag Summing error flag Fig. 2.4.17 Registers setting for receiver (2) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 52 of 202 APPLICATION 7643 Group 2.4 UART Figure 2.4.18 shows a control procedure of transmitter, and Figure 2.4.19 shows a control procedure of receiver. RESET q x: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization (Address : 3116) (Address : 3316), bit7 to bit 1 UCON (Address : 3316), bit0 UMOD (Address : 3016) UBRG UCON ..... ..... 4D16 001xx102 1 010x10002 • CTS function enabled • φ as UART clock, 2 stop bits, Parity checking disabled, 8-bit character length • UART transmit interrupt disabled ICONA (Address : 0516), bit7 CLI 0 10 ms pass ? Y UTRB2 (Add. : 3516) UTRB1 (Add. : 3416) N • An interval of 10 ms generated by Timer The first byte of a transmission data • Transmission data write Transmit buffer empty flag is set to “0” by this writing. Transmission starts owing to “L” input to CTS pin. • Judgment of transferring data from Transmit buffer register to Transmit shift register (Transmit buffer empty flag) USTS (Address : 3216), bit1? 1 UTRB2 (Add. : 3516) UTRB1 (Add. : 3416) 0 The second byte of a transmission data • Transmission data write Transmit buffer empty flag is set to “0” by this writing. USTS (Address : 3216), bit1? 1 0 • Judgment of transferring data from Transmit buffer register to Transmit shift register (Transmit buffer empty flag) USTS (Address : 3216), bit0? 1 0 • Judgment of shift completion of Transmit shift register (Transmit complete flag) Fig. 2.4.18 Control procedure of transmitter Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 53 of 202 APPLICATION 7643 Group 2.4 UART RESET q x: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization UBRG UCON UMOD URTSC ..... ..... (Address : 3116) (Address : 3316) (Address : 3016) (Address : 3616) 4D16 010x1x102 010x10002 000000002 x0xxxxxx2 xx0000002 • RTS function enabled • φ as UART clock, 2 stop bits, Parity checking disabled, 8-bit character length • No delay of RTS • UART receive buffer full interrupt disabled • UART summing error interrupt disabled ICONA (Address : 0516) ICONB (Address : 0616) CLI UCON (Address : 3316), bit1 12 • Reception starts. USTS (Address : 3216), bit2? 1 0 • Judgment of completion of receiving (Receive buffer full flag) Read out a received data from UTRB2 (Add. : 3516), UTRB1 (Add. : 3416) • Reception of the first byte data Receive buffer full flag is set to “0” by reading data. 1 • Judgment of an error flag USTS (Address : 3216), bit6? 0 USTS (Address : 3216), bit2? 1 0 • Judgment of completion of receiving (Receive buffer full flag) • Reception of the second byte data Receive buffer full flag is set to “0” by reading data. Read out a received data from UTRB2 (Add. : 3516), UTRB1 (Add. : 3416) USTS (Address : 3216), bit6? 0 1 • Judgment of an error flag Processing for error UCON (Address : 3316), bit1 02 UCON (Address : 3316) UCON (Address : 3316) 010x10002 010x10102 • Countermeasure for a bit slippage Fig. 2.4.19 Control procedure of receiver Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 54 of 202 APPLICATION 7643 Group 2.4 UART (2) UART address mode qOperation explanation The UART address mode is intended for use to communicate between the specified MCUs in a multi-MCU environment. The UART address mode can be used in either an 8-bit or 9-bit character length. An address is identified by the MSB of the incoming data being “ 1 ” . The bit is “ 0 ” f or non-address data. When the MSB of the incoming data is “0” in the UART address mode, the Receive Buffer Full Flag is set to “ 1 ” , but the Receive Buffer Full Interrupt Request Bit is not set to “ 1 ” . When the MSB of the incoming data is “1”, normal receive operation is performed. In the UART address mode an overrun error is not detected for reception of the 2nd and onward bytes. An occurrence of framing error or parity error sets the Summing Error Interrupt Request Bit to “1” and the data is not received independent of its MSB contents. Usage of UART address mode is explained as follows: (1) Set the UART Address Mode Enable Bit to “ 1 ” . (2) Sends the address data of a slave MCU first from a host MCU to all slave MCUs. The MSB of address data must be “ 1 ” a nd the remaining 7 bits specify the address. (3) The all slave MCUs automatically check for the received data whether its stop bit is valid or not, and whether the parity error occurs or not (when the parity enabled). If these errors occur, the Framing Error Flag or Parity Error Flag and the Summing Error Flag are set to “ 1 ” . Then, the Summing Error Interrupt Request Bit is also set to “ 1 ” . (4) When received data has no error, the all slave MCUs must judge whether the address of the received address data matches with their own addresses by a program. After the MSB being “1” is received, the UART Address Mode Enable Bit is automatically set to “0” (disabled). (5) The UART Address Mode Enable Bit of the slave MCUs which have be judged that the address does not match with them must be set to “ 1 ” ( enabled) again by a program to disable reception of the following data. (6) Transmit the data of which MSB is “ 0 ” f rom the host MCU. The slave MCUs disabling the UART address mode receive the data, and their Receive Buffer Full Flags and the Receive Buffer Full Interrupt Request Bits are set to “ 1 ” . For the other slave MCUs enabling the UART address mode, their Receive Buffer Full Flag are set to “1”, but their Receive Buffer Full Interrupt Request Bits are not set to “ 1 ” . (7) An overrun error cannot be detected after the first data has been received in UART Address Mode. Accordingly, even if the slave MCUs does not read the received data and the next data has been received, an overrun error does not occur. Thus, a communication between a host MCU and the specified MCU can be realized. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 55 of 202 APPLICATION 7643 Group 2.4 UART q UART address mode application example Outline : The slave CPU (B) receives the data from the host CPU, using the UART address mode. Specifications : • Transfer bit rate : 9600 bps •Data format: 1ST-8DATA-2SP • Use of port P3 1 f or communication control Figure 2.4.20 shows a connection diagram; Figure 2.4.21 shows the registers setting related to UART address mode; Figures 2.4.22 and 2.4.23 show the control procedures. Host CPU UTXD Port A P84/URXD P31 B P84/URXD P31 C P84/URXD P31 Slave CPU : 7643 Group (Address : 0116) Slave CPU : 7643 Group (Address : 0216) Slave CPU : 7643 Group (Address : 0316) Fig. 2.4.20 Connection diagram Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 56 of 202 APPLICATION 7643 Group 2.4 UART UART mode register (Address : 3016) b7 b0 UMOD 010 1000 UART clock : φ/1 Stop bit length : 2 stop bits Parity checking disabled Character length : 8 bits UART control register (Address : 3316) b7 b0 UCON 100 1 10 Transmit disabled Receive enabled Receive initializing CTS function disabled RTS function disabled UART address mode enabled UART baud rate generator (Address : 3116) b7 b0 UBRG 4D16 UART transmit/receive buffer register 1 (Address : 3416) b7 b0 UTRB1 Receiving data read Port P3 direction register (Address : 0F16) b7 b0 P3D 0 Input mode Interrupt control register A (Address : 0516) b7 b0 ICONA 1 UART receive buffer full interrupt enabled Interrupt control register B (Address : 0616) b7 b0 ICONB 000001 UART summing error interrupt disabled UART status register (Address : 3216) b7 b0 USTS Receive buffer full flag Parity error flag Framing error flag Overrun error flag Summing error flag Fig. 2.4.21 Registers setting related to UART address mode Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 57 of 202 APPLICATION 7643 Group 2.4 UART RESET q x: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization UBRG UCON UMOD P3D ICONA ICONB ..... ..... (Address : 3116) (Address : 3316) (Address : 3016) (Address : 0F16), bit1 (Address : 0516), bit6 (Address : 0616), bit0 4D16 100x11102 010x10002 0 1 1 • φ as UART clock, 2 stop bits, Parity checking disabled, 8-bit character length • Port P31 to input mode • UART receive buffer full interrupt enabled • UART summing error interrupt enabled CLI UCON (Address : 3316), bit1 12 • Reception starts. Main process 0 P3 (Address : 0E16), bit1? 1 UCON (Address : 3316) UCON (Address : 3316) 010x10002 010x10102 • Countermeasure for a bit slippage UART summing error interrupt routine CLT (Note 1) CLD (Note 2) Push registers to stack Error process Note 1: When using Index X mode flag (T) Note 2: When using Decimal mode flag (D) •Push registers used in interrupt process routine Pop registers RTI Fig. 2.4.22 Control procedure (1) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 58 of 202 APPLICATION 7643 Group 2.4 UART Slave CPU (B) receiving side UART receive buffer full interrupt routine CLT (Note 1) CLD (Note 2) Push registers to stack Read out a received data from UTRB1 (Address : 3416) q x: This bit is not used here. Set it to “0” or “1” arbitrarily. Note 1: When using Index X mode flag (T) Note 2: When using Decimal mode flag (D) •Push registers used in interrupt process routine • Data reception Receive buffer full flag is set to “0” by reading data. 0 : Data reception MSB of received data? 1 : Address reception Yes : Address of Slave CPU (B) Low-order 7 bits of received data = 0216? Store received data No : Address other than Slave CPU (B)’s UCON (Address : 3316), bit7 1 • Address mode enabled Pop registers RTI Fig. 2.4.23 Control procedure (2) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 59 of 202 APPLICATION 7643 Group 2.4 UART (3) Data packet transfer (with no error processing) from USB FIFO to UART using DMA Outline : t ransmit the data in USB FIFO to Host CPU using DMA and UART. Specifications : • U SB Endpoint1: OUT bulk transfer • U SB Endpoint1: OUT interrupt • U SB Endpoint1 packet size: 64 Bytes • U ART transmit is used. • D MA cycle steal transfer mode (fixed address -> fixed address transfer) • D MA transfer unit : 64 bytes fixed (short packet un-supported) • UART transmit interrupt request (when transmitting shift operation is completed) is used for DMA factor • Transfer bit rate : 9600 bps ( φ = 1 2 MHz divided by 1248) In this case, f(XIN)=24 MHz, system clock=f(XIN). φ is system clock divided by 2. • Data format: 1ST-8DATA-1SP • P arity bit is disabled • R e-transmit by transfer error is not performed • U se of CTS functions The UART transmit is enabled by USB Endpoint1 OUT interrupt after USB data is received from the host PC. The UART transmit interrupt source is set for a trigger of DMA. The first UART transmit interrupt source (UART transmit interrupt is not used) occurs by enable of UART transmit. By this UART transmit interrupt as a trigger of DMA, the data of USB FIFO is transmitted to the UART transmit/receive buffer register. In the 7643 group, DMA interrupt occurs after DMA transmits the 64-byte data of USB FIFO to UART. In this time, the UART transmit is disabled and the OUT_PKT_RDY flag of USB Endpoint1 OUT is cleared to “ 0. ” A s a result, the USB Endpoint1 can receive the following data. Figure 2.4.24 shows a connection diagram. Figure 2.4.25, 2.4.26 and 2.4.27 show register settings. Figure 2.4.28 and 2.4.29 show control procedures. Transmitting side P84/UTXD USB P86/CTS USB OUT DMA transfer Receiving side URXD RTS Host PC 7643 Group Host CPU Fig. 2.4.24 Connection diagram Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 60 of 202 APPLICATION 7643 Group 2.4 UART Transmitting side UART mode register (Address : 3016) b7 UMOD b0 010 0000 UART clock : φ/1 Stop bit length : 1 stop bit Parity checking disabled Character length : 8 bits UART control register (Address : 3316) b7 UCON b0 001 10 1 Transmit enabled Receive disabled Transmit initializing CTS function enabled RTS function disabled UART address mode disabled UART baud rate generator (Address : 3116) b7 b0 UBRG 4D16 Interrupt request register A (Address : 0216) b7 b0 IREQA 0 0 0 USB function interrupt request bit DMAC0 interrupt request bit UART transmit interrupt request bit Interrupt control register A (Address : 0516) b7 b0 ICONA 0 1 1 USB function interrupt: enabled DMAC0 interrupt: enabled UART transmit interrupt: disabled UART transmit/receive buffer register 1 (Address : 3416) b7 b0 UTRB1 transmitting data set UART status register (Address : 3216) b7 b0 USTS Transmit complete flag Transmit buffer empty flag Fig. 2.4.25 Registers setting (1) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 61 of 202 APPLICATION 7643 Group 2.4 UART Transmitting side Clock control register (Address : 1F16) b7 CCR b0 1 00000 φ = System clock/2, system clock = f(XIN) Frequency synthesizer multiply register 1 (Address : 6D16) b7 FSM1 b0 0016 Frequency synthesizer multiply register 2 (Address : 6E16) b7 FSM2 b0 FF16 Frequency synthesizer divide register (Address : 6F16) FSD 0016 Frequency synthesizer control register (Address : 6C16) b7 FSC b0 01 00000 1 Frequency synthesizer: enabled Frequency synthesizer input: f(XIN) USB control register (Address : 1316) b7 USBC b0 101100 0 USB line driver current : High USB line driver : enabled USB clock: enabled USB function control unit : USB block enabled Fig. 2.4.26 Registers setting (2) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 62 of 202 APPLICATION 7643 Group 2.4 UART USB endpoint FIFO mode register (Address : 5F16) b7 USBFIFOMR b0 00 Endpoint1FIFO size: OUT 128 bytes USB interrupt enable register 1 (Address : 5416) b7 USBIE1 b0 1 1 Endpoint0 interrupt : enabled Endpoint1 OUT interrupt : enabled USB endpoint index register 1 (Address : 5816) b7 USBINDEX b0 00000 01 Endpoint1 USB endpoint 1 OUT max. packet size register (Address : 5C16) b7 OUT_MAXP b0 0816 8 ✕ 8 = 64 bytes USB endpoint x OUT control register (Address : 5A16) b7 OUT_CSR b0 0 01 OUT_PKT_RDY flag Fig. 2.4.27 Registers setting (3) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 63 of 202 APPLICATION 7643 Group 2.4 UART RESET Initialization ..... (Interrupt disabled) CCR (Address : 1F16) FSM1 (Address : 6D16) FSM2 (Address : 6E16) FSD (Address : 6F16) FSC (Address : 6C16) USBC (Address : 1316) USBFIFOMR (Address : 5F16) USBIE1 (Address : 5416) USBINDEX (Address : 5816) OUT_MAXP (Address : 5C16) OUT_CSR (Address : 5A16) UBRG (Address : 3116) UMOD (Address : 3016) UCON (Address : 3316) DMAIS (Address : 3F16) DMA0SL (Address : 4216) DMA0SH (Address : 4316) DMA0DL (Address : 4416) DMA0DH (Address : 4516) DMA0CL (Address : 4616) DMA0CH (Address : 4716) DMA0M1 (Address : 4016) DMA0M2 (Address : 4116) ICONA (Address : 0516) IREQA (Address : 0216) ..... (interrupt enabled) 8016 0016 FF1 6 0016 4116 101100x02 xxxxxx002 xxxx10012 000000012 0816 000100012 4D16 010x00002 0011x0002 0xxxxxxx2 6116 0016 3416 0016 6416 0016 00110x0x2 0x0x00102 0xx1xxx12 0016 q x: This bit is not used here. Set it to “0” or “1” arbitrarily. Refer to the USB initiral setting. • USB initializing Endpoint1FIFO : OUT128 bytes Endpoint0, Endpoint1OUT interrupt enabled Max. packet size : 64 bytes ... • UART initializing φ as UART clock, 1 stop bit, Parity checking disabled, 8-bit character length CTS function enabled, RTS function disabled Tramsmit interrupt source : Transmit shift completed • DMA initializing DMA0 selected Source address : USBFIFO1 Destination address : UART transmit buffer register 1 Transmit byte : 64 bytes fixed DMAC channel 0 source increment : disabled DMAC channel 0 source register increment : disabled DMAC channel 0 destination register increment : disabled DMAC channel 0 write control : Writing data in reload latch only DMAC count register underflow : enabled DMAC channel 0 transfer mode : cycle steal transfer mode DMAC channel 0 hardware transfer request : UART transmit interrupt DMAC channel 0 : disabled • Others USB function interrupt : enabled DMAC0 interrupt : enabled UART transmit interrupt : disabled Fig. 2.4.28 Control procedure (1) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 64 of 202 APPLICATION 7643 Group 2.4 UART q x: This bit is not used here. Set it to “0” or “1” arbitrarily. Interrupt occurs USB endpoint 1OUT interrupt Push registers to stack USBIS1 (Address : 5216), bit3 DMA0M2 (Address : 4116) UCON (Address : 3316) ,bit2 UCON (Address : 3316) ,bit0 Pop registers R TI 1 110000102 1 1 • Start processing DMA0 enabled UART transmit initializing UART transmit enabled * Interrupt request flag is set as soon as UART transmit interrupt is enabled. However, in this time, since interrupt request flag is only for reference, so that the interrupt processing is not performed actually. Interrupt occurs DMA0 interrupt Push registers to stack DMA0M2 (Address : 4116) USBINDEX (Address : 5816) OUT_CSR (Address : 5A16) Pop registers R TI 000000102 000000012 000100012 * When USBINDEX is set, the stored value is pushed to the temporary buffer, and after the interrupt processing is finished, pop the pushed values to USBINDEX. • End processing DMA0 disabled USB receive (OUT) : enabled Fig. 2.4.29 Control procedure (2) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 65 of 202 APPLICATION 7643 Group 2.4 UART (4) Data packet transfer (with no error processing) from UART to USB FIFO using DMA Outline : write the data received from host CPU by UART to USB FIFO by DMA, and transmit the data to host PC. Specifications : • U SB Endpoint1: IN bulk transfer • U SB Endpoint1: IN interrupt • U SB Endpoint1 packet size: 64 Bytes • U ART receive is used. • D MA cycle steal transfer mode (fixed address -> fixed address transfer) • D MA transfer unit : 64 bytes fixed (short packet un-supported) • U ART receive buffer full interrupt request is used for DMA factor • Transfer bit rate : 9600 bps ( φ = 1 2 MHz divided by 1248) In this case, f(XIN)=24 MHz, system clock=f(XIN). φ is system clock divided by 2. • Data format: 1ST-8DATA-1SP • P arity bit is disabled • R e-transmit by transfer error is not performed • U se of RTS functions After the hardware reset, the UART receive and DMA are enabled in the initial setting. The UART receive interrupt source is set for a trigger of DMA. When the UART receive is started, the UART receive interrupt source (UART receive buffer full interrupt and UART receive summing error interrupt are not used) occurs. By this UART receive interrupt as a trigger of DMA, the 1-byte data of UART transmit/receive buffer register is transferred to the USB FIFO. In the 7643 group, DMA interrupt occurs after DMA transfers the 64-byte UART receive data to USB FIFO. In this time, the DMA is disabled and the IN_PKT_RDY flag of USB Endpoint1 IN is set to “ 1. ” A s a result, the USB Endpoint1 can transmit the data to host PC. Meanwhile, in the 7643 Group, after the data of USB FIFO is transmitted to host PC, the USB Endpoint1 IN interrupt occurs. In this time, DMA is set to be enabled again and the DMA transfer of the next UART receive data to USB FIFO is started. Figure 2.4.30 shows a connection diagram. Figure 2.4.31, 2.4.32 and 2.4.33 show register settings. Figure 2.4.34 and 2.4.35 show control procedures. Transmitting side P85/URXD USB P87/RTS USB IN DMA transfer Receiving side UTXD CTS Host PC 7643 Group Fig. 2.4.30 Connection diagram Host CPU Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 66 of 202 APPLICATION 7643 Group 2.4 UART UART mode register (Address : 3016) b7 UMOD b0 010 0000 UART clock : φ/1 Stop bit length : 1 stop bit Parity checking disabled Character length : 8 bits UART control register (Address : 3316) b7 UCON b0 010 1 10 Transmit disabled Receive enabled Receive initializing CTS function disabled RTS function enabled UART address mode disabled UART RTS control register (Address : 3616) b7 b0 URTSC 0000 RTS assertion delay count select bits UART baud rate generator (Address : 3116) b7 b0 UBRG 4D16 Interrupt request register A (Address : 0216) b7 b0 IREQA 0 0 0 USB function interrupt request bit DMAC0 interrupt request bit UART receive buffer full interrupt request bit Interrupt request register B (Address : 0316) b7 b0 IREQB 0 UART summing error interrupt request bit Interrupt control register A (Address : 0516) b7 b0 ICONA 0 1 1 USB function interrupt: enabled DMAC0 interrupt: enabled UART transmit interrupt: disabled Interrupt control register B (Address : 0616) b7 b0 ICONB 00 0000 UART summing error interrupt : disabled Fig. 2.4.31 Registers setting (1) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 67 of 202 APPLICATION 7643 Group 2.4 UART UART transmit/receive buffer register 1 (Address : 3416) b7 UTRB1 b0 Receive data UART status register (Address : 3216) b7 USTS b0 Receive buffer full flag Parity error flag Framing error flag Overrun error flag Summing error flag Fig. 2.4.32 Registers setting (2) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 68 of 202 APPLICATION 7643 Group 2.4 UART Transmitting side Clock control register (Address : 1F16) b7 CCR b0 1 00000 φ = System clock/2, system clock = f(XIN)/2 Frequency synthesizer multiply register 1 (Address : 6D16) b7 FSM1 b0 0016 Frequency synthesizer multiply register 2 (Address : 6E16) b7 b0 FSM2 FF16 Frequency synthesizer divide register (Address : 6F16) FSD 0016 Frequency synthesizer control register (Address : 6C16) b7 FSC b0 01 00000 1 Frequency synthesizer: enabled Frequency synthesizer input: f(XIN) USB control register (Address : 1316) b7 USBC b0 101100 0 USB line driver current : High USB line driver : enabled USB clock: enabled USB function control unit : USB block enabled Fig. 2.4.33 Registers setting (3) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 69 of 202 APPLICATION 7643 Group 2.4 UART USB endpoint FIFO mode register (Address : 5F16) b7 USBFIFOMR b0 00 Endpoint1FIFO size: OUT 128 bytes USB interrupt enable register 1 (Address : 5416) b7 USBIE1 b0 1 1 Endpoint0 interrupt : enabled Endpoint1 IN interrupt : enabled USB endpoint index register 1 (Address : 5816) b7 USBINDEX b0 00000 01 Endpoint1 USB endpoint 1 IN max. packet size register (Address : 5B16) IN_MAXP 0816 8 ✕ 8 = 64 bytes USB endpoint 1 IN control register (Address : 5916) b7 IN_CSR b0 0 00 IN_PKT_RDY bit Fig. 2.4.34 Registers setting (4) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 70 of 202 APPLICATION 7643 Group 2.4 UART RESET Initialization ..... (Interrupt disabled) CCR (Address : 1F16) FSM1 (Address : 6D16) FSM2 (Address : 6E16) FSD (Address : 6F16) FSC (Address : 6C16) USBC (Address : 1316) USBFIFOMR (Address : 5F16) USBIE1 (Address : 5416) USBINDEX (Address : 5816) IN_MAXP (Address : 5B16) IN_CSR (Address : 5916) UBRG (Address : 3116) UMOD (Address : 3016) UCON (Address : 3316) DMAIS (Address : 3F16) DMA0SL (Address : 4216) DMA0SH (Address : 4316) DMA0DL (Address : 4416) DMA0DH (Address : 4516) DMA0CL (Address : 4616) DMA0CH (Address : 4716) DMA0M1 (Address : 4016) DMA0M2 (Address : 4116) ICONA (Address : 0516) ICONB (Address : 0616) IREQA (Address : 0216) IREQB (Address : 0316) 8016 0016 FF16 0016 4116 101100X02 XXXX01012 000000012 X00000012 0816 0X00X0002 4D16 010X00002 010X1X102 00XXXXXX2 3416 0016 6116 0016 6416 0016 00110X0X2 1X0X00012 X0X1XXX12 XX0000002 0016 0016 q x: This bit is not used here. Set it to “0” or “1” arbitrarily. Refer to the USB initiral setting. • USB initializing Endpoint1FIFO : OUT128 bytes Endpoint0, Endpoint1IN interrupt enabled Max. packet size : 64 bytes ... • UART initializing φ as UART clock, 1 stop bit, Parity checking disabled, 8-bit character length CTS function disabled, RTS function enabled Receive enabled • DMA initializing DMA0 selected Source address : UART receive buffer Destination address : USBFIFO1 Transmit byte : 64 bytes fixed DMAC channel 0 source register increment : disabled DMAC channel 0 destination register increment : disabled DMAC channel 0 write control : Writing data in reload latch only DMAC count register underflow : enabled DMAC channel 0 transfer mode : cycle steal transfer mode DMAC channel 0 hardware transfer request : UART receive interrupt DMAC channel 0 : enabled • Others USB function interrupt : enabled DMAC0 interrupt : enabled UART receive buffer full interrupt : disabled UART summing error interrupt : disabled ..... (interrupt enabled) Fig. 2.4.35 Control procedure (1) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 71 of 202 APPLICATION 7643 Group 2.4 UART Interrupt occurs DMA0 interrupt Push registers to stack DMA0M2 (Address : 4116) USBINDEX (Address : 5816) IN_CSR (Address : 5916) Pop registers RTI 000000102 000000012 000000012 * When USBINDEX is set, the stored value is pushed to the temporary buffer, and after the interrupt processing is finished, pop the pushed values to USBINDEX. • End processing DMAC channel 0 disabled USB transmit (IN) : enabled Interrupt occurs USB endpoint 1IN interrupt Push registers to stack USBIS1 (Address : 5216), bit2 DMA0M2 (Address : 4116) 1 100000102 • Start processing DMAC channel 0 enabled (do not reset the source capture register) Pop registers RTI Fig. 2.4.36 Control procedure (2) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 72 of 202 APPLICATION 7643 Group 2.4 UART 2.4.7 N otes on UART (1) Receive • When any one of errors occurs, the summing error flag is set to “ 1 ” a nd the UART summing error interrupt request bit is also set to “1”. If a receive error occurs, the reception does not set the UART receive buffer full interrupt request bit to “ 1 ” . •If the receive enable bit (REN) is set to “0” (disabled) while a data is being received, the receiving operation will stop after the data has been received. • Setting the receive initialization bit (RIN) to “ 1 ” r esets the UART RTS control register (URTS) to “ 80 16” . After setting the RIN bit to “ 1 ” , set this URTS. (2) Transmit •Once the transmission starts, it continues until the last bit has been transmitted even though clearing the transmit enable bit (TEN) to “ 0 ” ( disabled) or inputting “ H ” t o the CTS pin. After completion of the current transmission, the transmission is disabled. •The transmit complete flag (TCM) is changed from “1” to “0” later than 0.5 to 1.5 clocks of the shift clock. Accordingly, take it in consideration to transmit data confirming the TCM flag after the data is written into the transmit buffer register. (3) Register settings •If updating a value of UART baud rate generator while the data is being transmitted or received, be sure to disable the transmission and reception before updating. If the former data remains in the UART transmit buffer registers 1 and 2 at retransmission, an undefined data might be output. • The all error flags PER, FER, OER and SER are cleared to “ 0 ” w hen the UART status register is read, at the hardware reset or initialization by setting the Transmit Initialization Bit. These flags are also cleared to “ 0 ” b y execution of bit test instructions such as B BC a nd B CS . • The transmit buffer empty flag (TBE) is set to “ 0 ” w hen the low-order byte of transmitted data is written into the UART transmit buffer register 1. When using 9-bit character length, set the data into the UART transmit buffer register 2 (high-order byte) first before the UART transmit buffer register 1 (low-order byte). •The receive buffer full flag (RBF) is set to “0” when the contents of UART receive buffer register 1 is read out. When using 9-bit character length, read the data from the UART receive buffer register 2 (high-order byte) first before the UART receive buffer register 1 (low-order byte). • If a character bit length is 7 bits, bit 7 of the UART transmit/receive buffer register 1 and bits 0 to 7 of the UART transmit/receive buffer register 2 are ignored at transmitting; they are invalid at receiving. If a character bit length is 8 bits, bits 0 to 7 of the UART transmit/receive buffer register 2 are ignored at transmitting; they are invalid at receiving. If a character bit length is 9 bits, bits 1 to 7 of the UART transmit/receive buffer register 2 are ignored at transmitting; they are “ 0 ” a t receiving. • The reset cannot affect the contents of baud rate generator. (4) UART address mode • When the MSB of the incoming data is “ 0 ” i n the UART address mode, the receive buffer full flag (RBF) is set to “ 1 ” , but the receive buffer full interrupt request bit is not set to “ 1 ” . •An overrun error cannot be detected after the first data has been received in UART address mode. • The UART address mode can be used in either an 8-bit or 9-bit character length. 7-bit character length cannot be used. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 73 of 202 APPLICATION 7643 Group 2.4 UART (5) Receive error flag The all error flags PER, FER, OER and SER are cleared to “ 0 ” w hen the UART status register is read, at the hardware reset or initialization by setting the Transmit Initialization Bit. Accordingly, note that these flags are also cleared to “ 0 ” b y execution of bit test instructions such as BBC and BBS, not only LDA. (6) CTS function When the CTS function is enabled, the transmitted data is not transferred to the transmit shift register until “L” is input to the CTS pin (P8 6/CTS). As the result, do not set the following data to the transmit buffer register. (7) RTS function •If the start bit is detected in the term of “H” assertion of RTS, its assertion count is suspended and the RTS pin remains “ H ” o utput. After receiving the last stop bit, the count is resumed. • Setting the receive initialization bit (RIN) to “ 1 ” r esets the UART RTS control register (URTS) to “ 80 16” . After setting the RIN bit to “ 1 ” , set this URTS. (8) Interrupt •When setting the transmit initialization bit (TIN) to “1”, both the transmit buffer empty flag (TBE) and the transmit complete flag (TCM) are set to “ 1 ” , so that the transmit interrupt request occurs independent of its interrupt source. After setting the transmit initialization bit (TIN) to “1”, clear the transmit interrupt request bit to “ 0 ” b efore setting the transmit enable bit (TEN) to “ 1 ” . •The transmit interrupt request bit is set and the interrupt request is generated by setting the transmit enable bit (TIN) to “1” even when selecting timing that either of the following flags is set to “1” as timing where the transmission interrupt is generated: (1) Transmit buffer empty flag is set to “ 1 ” (2) Transmit complete flag is set to “ 1 ” . Therefore, when the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as the following sequence: (1) Transmit enable bit is set to “ 1 ” (2) Transmit interrupt request bit is set to “ 0 ” (3) Transmit interrupt enable bit is set to “ 1 ” . Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 74 of 202 APPLICATION 7643 Group 2.5 DMAC 2.5 DMAC This paragraph explains the registers setting method and the notes related to the DMAC. 2.5.1 Memory map Address 000216 000516 003F16 004016 004116 004216 004316 004416 004516 004616 004716 Interrupt request register A (IREQA) Interrupt control register A (ICONA) DMAC index and status register (DMAIS) DMAC channel x mode register 1 (DMAx1) DMAC channel x mode register 2 (DMAx2) DMAC channel x source register Low (DMAxSL) DMAC channel x source register High (DMAxSH) DMAC channel x destination register Low (DMAxDL) DMAC channel x destination register High (DMAxDH) DMAC channel x transfer count register Low (DMAxCL) DMAC channel x transfer count register High (DMAxCH) Fig. 2.5.1 Memory map of registers related to DMAC Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 75 of 202 APPLICATION 7643 Group 2.5 DMAC 2.5.2 Related registers (1) DMAC index and status register • DMAC channel x (x = 0, 1) count register underflow flag (DxUF) When the corresponding transfer count register Low (address 4616) underflows, this DxUF flag is set to “ 1 ” . Writing “ 0 ” i nto this flag clears it. • DMAC channel x (x = 0, 1) suspend flag (DxSFI) When an interrupt routine is processed during any DMA operation, the transfer operation is suspended and the DMAC automatically sets the corresponding DxSFI flag to “ 1 ” . As soon as the CPU completes the interrupt operation, the DMAC clears the DxSFI flag to “0” and resumes the original operation from the point where it was suspended. • DMAC transfer suspend control bit (DTSC) This bit specifies the transfer mode which can be suspended by an interrupt process. • DMAC register reload disable bit (DRLDD) If the DRLDD bit is “1”, when the DMAC channel x transfer count register underflows, the DMAC channel x source registers and destination registers are disabled from being reloaded from their latches. • Channel index bit (DCI) The related registers of channels 1 and 2 are assigned on the same SFR addresses. This DCI bit specifies the accessible channel. DMAC index and status register b7 b6 b5 b4 b3 b2 b1 b0 0 DMAC index and status register (DMAIS : address 3F16) b Name Functions At reset R W 0 0 0 0 0 ✽ 0 : No underflow 1 : Underflow generated 0 : Not suspended 1 : Suspended 0 : No underflow 1 : Underflow generated 0 : Not suspended 1 : Suspended 0 :Suspending only burst transfers during interrupt process 1 : Suspending both burst and cycle steal transfers during interrupt process 0 :Enabling reload of source and 5 DMAC register reload destination registers of both channels disable bit (DRLDD) 1 : Disabling reload of source and (Note 3) destination registers of both channels 6 Nothing is arranged for this bit. Fix this bit to “0”. 7 Channel index bit (DCI) 0 : Channel 0 accessible 1 : Channel 1 accessible Accessed registers: Mode register, 0 DMAC channel 0 count register underflow flag (D0UF) 1 DMAC channel 0 suspend flag (D0SFI) (Note 1) 2 DMAC channel 1 count register underflow flag (D1UF) 3 DMAC channel 1 suspend flag (D1SFI) (Note 1) 4 DMAC transfer suspend control bit (DTSC) (Note 2) ✕ ✽ ✕ 0 0 0 source register, destination register, transfer count register. ✽: “0” can be set by software, but “1” cannot be set. Notes 1: Suspended by an interrupt. 2: Transfer suspended during interrupt process 3: This settings affect the source and destination registers of both channels. Fig. 2.5.2 Structure of DMAC index and status register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 76 of 202 APPLICATION 7643 Group 2.5 DMAC (2) DMAC channel x (x = 0, 1) mode register 1 • DMAC channel x source register increment/decrement selection bit (DxSRID) • DMAC channel x source register increment/decrement enable bit (DxSRCE) • DMAC channel x destination register increment/decrement selection bit (DxDRID) • DMAC channel x destination register increment/decrement enable bit (DxDRCE) These bits select that the DMAC channel X source registers and destination registers are either decreased or increased by 1 after transfer completion. • DMAC channel x data write control bit (DxDWC) The DxDWC bit controls write operation to the following registers and their latches: Low and High bytes of DMAC channel x source registers, destination registers and transfer count registers. When the DxDWC bit is “ 0 ” , data is simultaneously written into each latch and register. When this bit is “ 1 ” , data is written only into their latches. • DMAC channel x disable after count register underflow enable bit (DxDAUE) When the DxDAUE bit is “1”, after the DMAC channel x transfer count register Low underflows the corresponding channel x is disabled. The DMAC channel x enable bit (DxCEN, bit 7 of DMAxM2) goes to “ 0 ” a t the same time. • DMAC channel x register reload bit (DxRLD) Writing “ 1 ” t o the DxRLD bit can update the DMAC channel x source registers, destination registers and transfer count registers with the values in their respective latches. It can be performed at anytime. This bit is fixed to “ 0 ” a t read. • DMAC channel x transfer mode selection bit (DxTMS) The DxTMS bit selects the transfer mode. DMAC channel x mode register 1 (x = 0, 1) b7 b6 b5 b4 b3 b2 b1 b0 DMAC channel x mode register 1 (DMAxM1 : address 4016) (Note 1) b Name Functions 0 : Increment after transfer 1 : Decrement after transfer 0 : Disabled (No change after transfer) 1 : Enabled 0 : Increment after transfer 1 : Decrement after transfer 0 : Disabled (No change after transfer) 1 : Enabled At reset R W 0 0 : Writing data in reload latches and 0 registers 1 : Writing data in reload latches only 5 DMAC channel x disable after 0 : Channel x enabled after count 0 register underflow count register underflow 1 : Channel x disabled after count enable bit (DxDAUE) register underflow DMAC channel x register 0 : Not reloaded 6 0 (Note 2) 1 : Source, destination, and transfer reload bit (DxRLD) count registers contents of channel x to be reloaded 0 : Cycle steal transfer mode 7 DMAC channel x transfer 0 mode selection bit (DxTMS) 1 : Burst transfer mode Notes 1: Channels 1 and 2 share this register. The channel selection which can use this register depends on channel index bit, bit 7 of DMAC index and status register. 2: These bits’ contents are “0” at read. 0 DMAC channel x source register increment/decrement selection bit (DxSRID) 1 DMAC channel x source register increment/decrement enable bit (DxSRCE) 2 DMAC channel x destination register increment/decrement selection bit (DxDRID) 3 DMAC channel x destination register increment/decrement enable bit (DxDRCE) 4 DMAC channel x data write control bit (DxDWC) 0 0 0 Fig. 2.5.3 Structure of DMAC channel x (x = 0, 1) mode register 1 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 77 of 202 APPLICATION 7643 Group 2.5 DMAC (3) DMAC channel x (x = 0, 1) mode register 2 • DMAC channel x software transfer trigger bit (DxSWT) Writing “ 1 ” t o the DxSWT bit can generate a transfer request as a software trigger. If all of DMACx hardware transfer request source bits (DxHR) are “ 0 ” , the software trigger is only transfer request factor. This bit is fixed to “ 0 ” a t read. • DMAC channel x transfer initiation source capture register reset bit (DxCRR) Writing “ 1 ” t o the DxCRR bit can reset the transfer initiation source capture register. The request of the transfer initiation source is latched asynchronously and it is sampled into the transfer initiation source capture register at a rising edge of φ . This bit is fixed to “ 0 ” a t read. • DMAC channel x enable bit (DxCEN) The DMAC channel x is enabled by setting this bit to “ 1 ” . When clearing this to “ 0 ” , the DMA transfer is finished. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 78 of 202 APPLICATION 7643 Group 2.5 DMAC DMAC channel 0 mode register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 DMAC channel 0 mode register 2 (DMA0M2 : address 4116) (Note 1) b Name Functions At reset R W 0 0 DMAC channel 0 hardware b3b2b1b0 0 0 0 0 : Not used transfer request source 0 0 0 1 : UART receive interrupt bits (D0HR) 0 0 1 0 : UART transmit interrupt 0 0 1 1 : Not used 0 1 0 0 : INT0 interrupt 0 1 0 1 : USB endpoint 1 IN_PKT_RDY signal (falling edge active) 1 0 1 1 0 : USB endpoint 2 IN_PKT_RDY signal (falling edge active) 0 1 1 1 : Not used 1 0 0 0 : USB endpoint 1 OUT_PKT_RDY signal (rising edge active) 2 1 0 0 1 : USB endpoint 1 OUT_FIFO_NOT_EMPTY signal (rising edge active) 1 0 1 0 : USB endpoint 2 OUT_PKT_RDY signal (rising edge active) 1 0 1 1 : Not used 3 1 1 0 0 : Not used 1 1 0 1 : Not used 1 1 1 0 : Serial I/O transmit/receive interrupt 1 1 1 1 : Not used 4 DMAC channel 0 software 0 : No action 1 : Request of channel 0 transfer by transfer trigger (D0SWT) writing “1” 5 Nothing is arranged for this bit. Fix this bit to “0”. 6 DMAC channel 0 transfer 0 : No action 1 : Reset of channel 0 capture register by initiation source capture writing “1” register reset bit (D0CRR) 0 : Channel 0 disabled 7 DMAC channel 0 enable 1 : Channel 0 enabled (Note 3) bit (D0CEN) 0 0 0 0 (Note 2) 0 0 (Note 2) 0 Notes 1: DMAC channel 0 mode register 2 and DMAC channel 1 mode register 2 are assigned at the same address 4116. The accessible register depends on channel index bit, bit 7 of DMAC index and status register. 2: These bits’ contents are “0” at read. This bit is automatically cleared to “0” after writing “1”. 3: When setting this bit to “1”, simultaneously set the DMAC channel 0 transfer initiation source capture register reset bit (bit 6 of DMA0M2) to “1”. Fig. 2.5.4 Structure of DMAC channel 0 mode register 2 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 79 of 202 APPLICATION 7643 Group 2.5 DMAC DMAC channel 1 mode register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 DMAC channel 1 mode register 2 (DMA1M2 : address 4116) (Note 1) b Name Functions At reset R W 0 0 DMAC channel 1 hardware b3b2b1b0 0 0 0 0 : Not used transfer request source 0 0 0 1 : Not used bits (D1HR) 0 0 1 0 : Not used 0 0 1 1 : Not used 0 1 0 0 : INT1 interrupt 0 1 0 1 : USB endpoint 1 IN_PKT_RDY 1 signal (falling edge active) 0 1 1 0 : USB endpoint 2 IN_PKT_RDY signal (falling edge active) 0 1 1 1 : Not used 1 0 0 0 : USB endpoint 1 OUT_PKT_RDY signal (rising edge active) 2 1 0 0 1 : USB endpoint 1 OUT_FIFO_NOT_EMPTY signal (rising edge active) 1 0 1 0 : USB endpoint 2 OUT_PKT_RDY signal (rising edge active) 1 0 1 1 : Not used 3 1 1 0 0 : Not used 1 1 0 1 : Not used 1 1 1 0 : Timer 1 interrupt 1 1 1 1 : Not used 4 DMAC channel 1 software 0 : No action 1 : Request of channel 1 transfer by transfer trigger (D1SWT) writing “1” 5 Nothing is arranged for this bit. Fix this bit to “0”. 6 DMAC channel 1 transfer 0 : No action 1 : Reset of channel 1 capture register by initiation source capture writing “1” register reset bit (D1CRR) 0 : Channel 1 disabled 7 DMAC channel 1 enable 1 : Channel 1 enabled (Note 3) bit (D1CEN) 0 0 0 0 (Note 2) 0 0 (Note 2) 0 Notes 1: DMAC channel 0 mode register 2 and DMAC channel 1 mode register 2 are assigned at the same address 4116. The accessible register depends on channel index bit, bit 7 of DMAC index and status register. 2: These bits’ contents are “0” at read. This bit is automatically cleared to “0” after writing “1”. 3: When setting this bit to “1”, simultaneously set the DMAC channel 1 transfer initiation source capture register reset bit (bit 6 of DMA1M2) to “1”. Fig. 2.5.5 Structure of DMAC channel 1 mode register 2 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 80 of 202 APPLICATION 7643 Group 2.5 DMAC DMAC channel x source registers Low, High b7 b6 b5 b4 b3 b2 b1 b0 DMAC channel x source registers Low, High (DMAxSL,DMAxSH : addresses 4216, 4316) b Functions At reset R W 0 qThis is a 16-bit register with a latch. 0 1 0 2 qThis register indicates the source address for data transfer. 0 3 0 4 0 5 0 6 0 7 0 Notes 1: DMAC channel x source registers low, high of channels 0 and 1 are assigned at the same addresses. The accessible register depends on channel index bit, bit 7 of DMAC index and status register. 2: Write data into the lower bytes first, and then the higher bytes. 3: Read the contents from the higher bytes first, and then the lower bytes. Fig. 2.5.6 Structure of DMAC channel x source registers Low, High DMAC channel x destination registers Low, High b7 b6 b5 b4 b3 b2 b1 b0 DMAC channel x destination registers Low, High (DMAxDL,DMAxDH : addresses 4416, 4516) b Functions At reset R W 0 qThis is a 16-bit register with a latch. 0 1 0 2 qThis register indicates the destination address for data transfer. 0 3 0 4 0 5 0 6 0 7 0 Notes 1: DMAC channel x destination registers low, high of channels 0 and 1 are assigned at the same addresses. The accessible register depends on channel index bit, bit 7 of DMAC index and status register. 2: Write data into the lower bytes first, and then the higher bytes. 3: Read the contents from the higher bytes first, and then the lower bytes. Fig. 2.5.7 Structure of DMAC channel x destination registers Low, High Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 81 of 202 APPLICATION 7643 Group 2.5 DMAC DMAC channel x transfer count registers Low, High b7 b6 b5 b4 b3 b2 b1 b0 DMAC channel x transfer count registers Low (DMAxCL : address 4616) b 0 1 2 3 4 5 6 7 b7 b6 b5 b4 b3 b2 b1 b0 Functions qThis is the lower 8-bit register with a latch. Set the lower 8 bits of transfer numbers. qThis register indicates the remaining transfer numbers while transfer is continuing. qThis contents are decreased by 1 at every transfer operation. qWhen this register underflows, the DMAC interrupt request bit and the count register underflow flag (Note 2) are set to “1”. At reset R W 0 0 0 0 0 0 0 0 DMAC channel x transfer count registers High (DMAxCH : address 4716) b Functions At reset R W 0 qThis is the higher 8-bit register with a latch. Set the higher 8 bits of 0 transfer numbers. 1 0 2 qThis register indicates the remaining transfer numbers while 0 transfer is continuing. 3 0 qThis contents are decreased by 1 at every transfer operation. 4 0 5 0 6 0 7 0 Notes 1: DMAC channel x transfer count registers low, high of channels 0 and 1 are assigned at the same addresses 4616 and 4716. The accessible channel depends on channel index bit, bit 7 of DMAC index and status register. 2: Channel 0 used: Bit 0 of DMAC index and status register Channel 1 used: Bit 2 of DMAC index and status register 3: Write data into the lower byte first, and then the higher byte. 4: Read the contents from the higher byte first, and then the lower byte. Fig. 2.5.8 Structure of DMAC channel x transfer count registers Low, High Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 82 of 202 APPLICATION 7643 Group 2.5 DMAC Interrupt request register A b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register A (IREQA : address 0216) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 ✽ ✽ ✽ ✽ ✽ ✽ ✽ 0 USB function interrupt request bit 1 Nothing is arranged for this bit. When this bit is read out, the contents are undefined. This bit is “0” at write. 0 : No interrupt request issued 2 INT0 interrupt request bit 1 : Interrupt request issued 3 INT1 interrupt request bit 4 DMAC0 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 5 DMAC1 interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit 0 : No interrupt request issued 6 UART receive buffer full 1 : Interrupt request issued interrupt request bit UART transmit interrupt 0 : No interrupt request issued 7 request bit 1 : Interrupt request issued ✽: “0” can be set by software, but “1” cannot be set. Fig. 2.5.9 Structure of Interrupt request register A Interrupt control register A b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt control register A (ICONA : address 0516) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 0 0 0 0 0 0 USB function interrupt enable bit 1 Nothing is arranged for this bit. Fix this bit to “0”. 0 : Interrupt disabled 2 INT0 interrupt enable bit 1 : Interrupt enabled 3 INT1 interrupt enable bit 4 DMAC0 interrupt enable bit 5 DMAC1 interrupt enable bit 6 UART receive buffer full interrupt enable bit 7 UART transmit interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Fig. 2.5.10 Structure of Interrupt control register A Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 83 of 202 APPLICATION 7643 Group 2.5 DMAC 2.5.3 DMAC operation description The DMAC transfers data using the bus without use of the CPU. The DMAC consists of DMAC0 and DMAC1, which have the same function each. There are two transfer modes: Burst transfer mode or Cycle steal transfer mode. • Burst transfer mode Once a DMA transfer request is accepted, an entire batch of data is transferred. The right to use bus is not returned to the CPU until the transfer of all data has been completed. The DMAC transfers the number of bytes data specified by the transfer count register for each request. The count register is a 16-bit counter; the maximum number of data is 65,536 bytes per one request. • Cycle steal mode The DMAC transfers one byte of data for each request. If one byte transfer has been completed and then a DMA transfer request is not generated, the right to use bus is returned to the CPU. Figure 2.5.11 shows the transfer mode overview. s Burst transfer mode DMACx request is accepted. ➔ DMACx (x = 0, 1) (Transfer of entire batch of data) CPU Right to use bus CPU s Cycle steal transfer mode DMAC0 request is accepted. DMAC0 request is accepted. DMAC1 request is accepted. ➔ ➔ ➔ CPU Right to use bus CPU DMAC0 (One-byte transfer) CPU DMAC0 DMAC1 (One-byte transfer)(One-byte transfer) Fig. 2.5.11 Transfer mode overview (1) Priority The DMAC places a higher priority on Channel-0 transfer requests than on Channel-1 transfer requests. If a channel-0 transfer request occurs during a channel-1 burst transfer operation, the DMAC completes the next transfer source and destination read/write operation first, and then starts the channel-0 transfer operation. As soon as the channel-0 transfer is completed, the DMAC resumes the channel-1 transfer operation. (2) Transfer request acceptance A transfer request is confirmed at every rising of φ . After that a channel priority and a right to use the bus is judged. A software trigger and/or a hardware factor can be selected as a transfer request source. The DMAC channel x hardware transfer request source bits (DxHR) selects a hardware factor. Writing “1” to the DMAC channel x software transfer trigger bit (DxSWT) can generate a transfer request as a software trigger. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 84 of 202 APPLICATION 7643 Group 2.5 DMAC (3) DMA execution The selected channel transfers one byte of data from the address indicated by its source register (address 42 16 or 43 16) into the address indicated by its destination register (address 44 16 or 4516) with at 2 cycles of φ . The operataion of the source registers and destination registers after transfer completion can be selected between decreased/increased by 1 and no change with bits 0 to 3 in the DMAC channel x mode register 1. When the transfer count register underflows, the source registers and destination registers are reloaded from their latches when the DMAC register reload disable bit (DRLDD) is “ 0 ” . If the DRLDD bit is set to “ 1 ” , a reload is disabled. A read/write must be performed to the source registers, destination registers and transfer count registers as follows: Read from each higher byte first, then the lower byte Write to each lower byte first, then the higher byte. Figure 2.5.12 shows the basic operation of registers transferring. Tables 2.5.1 and 2.5.2 shows the address directions and examples of transfer result. (1) Read cycle DMAC DMAxSL, DMAxSH DMAxSL, DMAxSH latch ➂ DMAxDL, DMAxDH DMAxDL, DMAxDH latch DMAxCL, DMAxCH DMAxCL, DMAxCH latch Temporary register Transfer destination Decrementer Incrementer/ Decrementer Memory ➀Transfer source address is specified. ➁Contents of DMAxCL, DMAxCH are updated by Decrementer. ➂Contents of DMAxSL, DMAxSH are updated by Incrementer/Decrementer. ➃Data is read from memory and retained in Temporary register. ➀ Transfer source ➃ ➁ (2) Write cycle DMAC DMAxSL, DMAxSH DMAxSL, DMAxSH latch ➅ DMAxDL, DMAxDH DMAxDL, DMAxDH latch DMAxCL, DMAxCH DMAxCL, DMAxCH latch Temporary register Incrementer/ Decrementer Transfer source Memory ➄Transfer destination address is specified. ➅Contents of DMAxDL, DMAxDH are updated by Incrementer/Decrementer. ➆Contents of temporary register is written into memory. ➄ Decrementer ➆ Transfer destination Note: The temporary register is an internal use register, so that it cannot be read out or written into by program. Fig. 2.5.12 Basic operation of registers transferring Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 85 of 202 APPLICATION 7643 Group 2.5 DMAC Table 2.5.1 Address directions and examples of transfer result (1) Address direction Source Destination Data arrangement on transfer source memory Transfer sequence Data arrangement on transfer destination memory (Ttransfer result) Fixed Fixed * Data Da t a * Fixed Forward * Data 1 to 6 ➀ ➁ ➂ ➃ ➄ ➅ Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 * Fixed Backward ➅ * Data 1 to 6 ➄ ➃ ➂ ➁ ➀ Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 * Forward Fixed * Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 ➀ ➁ ➂ ➃ ➄ ➅ Data 1 to 6 * Forward Forward * Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 ➀ ➁ ➂ ➃ ➄ ➅ Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 * Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 86 of 202 APPLICATION 7643 Group 2.5 DMAC Table 2.5.2 Address directions and examples of transfer result (2) Address direction Source Destination Data arrangement on transfer source memory Transfer sequence Data arrangement on transfer destination memory (Ttransfer result) Forward Backward * Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 ➀ ➁ ➂ ➃ ➄ ➅ Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 * Backward Fixed Data 6 Data 5 Data 4 Data 3 Data 2 ➅ ➄ ➃ ➂ ➁ ➀ Data 1 to 6 * * Backward Forward Data 1 Data 6 Data 5 Data 4 Data 3 Data 2 ➅ ➄ ➃ ➂ ➁ ➀ Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 * * Backward Backward Data 1 Data 1 6 Data 2 5 Data 3 4 Data 4 3 Data 5 2 ➅ ➄ ➃ ➂ ➁ ➀ Data 1 6 Data 2 5 Data 3 4 Data 4 3 Data 5 2 Data 6 1 * Data 6 1 * (4) Transfer suspension Writing “ 0 ” t o the DMAC channel x enable bit (DxCEN) can compulsorily suspend the transfer being executed. The suspended transfer can be resumed by writing “ 1 ” t o the DxCEN bit. When an interrupt request, which is enabled, occurs during any DMA operation, the transfer operation is suspended and the interrupt process routine is initiated. During the interrupt operation, the DMAC automatically sets the corresponding DMAC channel x suspend flag to “ 1 ” . When the DMAC transfer suspend control bit (DTSC) is “1”, the transfer is suspended in both burst transfer and cycle steal transfer modes during an interrupt process; when the DTSC bit is “0”, it is suspended in only burst transfer mode. The suspended transfer due to the interrupt can also be resumed during its interrupt process routine by writing “ 1 ” t o the DxCEN bit. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 87 of 202 APPLICATION 7643 Group 2.5 DMAC 2.5.4 DMAC arbitration The DMA transfer request is accepted at a rising of φ . If the bus is not released 1 cycle of φ l ater than the transfer request acceptance, the DMAC will wait for the bus released. When the bus is released, the DMAC has a right to use the bus and starts the DMA transfer unless a request of the right to use the bus having priority over the DMAC occurs. Table 2.5.3 shows the priority to use the bus. Table 2.5.3 Priority to use bus Priority 2 Factor requesting right to use bus DMAC 1 (Higher) Hold request via HOLD pin 3 CPU data access 4 (Lower) CPU instruction access 2.5.5 Transfer time One-byte transfer of the cycle steal transfer mode requires the time calculated by the following equation: Time (T) = A + B + C A: This means the time from the occurrence of DMA transfer source request to sampling it. It needs 1 cycle of φ a t the maximum. The sampling is asynchronously performed. B: This means the delay time to sample the DMA transfer source request. It needs 1 cycle of φ a t the maximum. C: This means the time to transfer data. It needs 2 cycles of φ. Figures 2.5.13 to 2.5.15 show the timing chart for DMA transfer. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 88 of 202 APPLICATION 7643 Group 2.5 DMAC φ OUT SYNCOUT RD WR LDA $zz STA $zz ADL1, 00 PC + 2 85 DMA transfer DMA source add. DMA destination add. STA $zz (last 2 cycles) PC + 3 ADL2, 00 Next instruction PC + 4 Op code 3 Address Data DMAOUT (Port P33) Transfer request source (“L” active) Transfer request source sampling Reset of transfer request source sampling PC A5 PC + 1 ADL1 Data DMA data DMA data ADL2 Data Fig. 2.5.13 Timing chart for cycle steal transfer caused by hardware-related transfer request φ OUT SYNCOUT RD WR LDM #$90, $41 1 cycle 1 cycle 1 cycle instruction instruction instruction 42, 00 41 DMA transfer DMA source add. DMA destination add. Next instruction PC + 6 Op code 6 Address Data DMAOUT (Port P33) Transfer request source (“L” active) Transfer request source sampling Reset of transfer request source sampling PC 3C PC + 1 18 PC + 2 PC + 3 90 PC + 4 PC + 5 Op code 2 Op code 3 Op code 4 DMA data DMA data Fig. 2.5.14 Timing chart for cycle steal transfer caused by software trigger transfer request Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 89 of 202 APPLICATION 7643 Group 2.5 DMAC φ OUT SYNCOUT RD WR LDA $zz STA $zz (First cycle) ADL1, 00 PC + 2 85 DMA source add. 1 DMA transfer DMA destination add. 1 DMA source add . 2 STA $zz (Second cycle) DMA destination add. 2 Address Data DMAOUT (Port P33) Transfer request source (“L” active) Transfer request source sampling Reset of transfer request source sampling PC A5 PC + 1 PC + 3 ADL2 ADL1 Data DMA data 1 DMA data 1 DMA data 2 DMA data 2 Fig. 2.5.15 Timing chart for burst transfer caused by hardware-related transfer request Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 90 of 202 APPLICATION 7643 Group 2.5 DMAC 2.5.6 DMAC application example (1) Transfer from external FIFO to USB FIFO Outline: D ata are transferred from external FIFOs to USB FIFOs. Specifications: • A burst transfer is used and 128-byte (128 bytes/packet) continuous transfer is performed. The external FIFO size must be set as 128 bytes of an integral multiple. •If the data is deficient in the external FIFO, the DMAC channel 0 transferring is stopped in the DMAC channel 0 interrupt routine process. The DMA transfer is resumed in the main routine process when the data is sufficient. •To confirm the external FIFO state after completion of 128 bytes transferring, set the DMAC channel x disable after count register underflow enable bit (DxDAUE) to “ 1 ” . •USB endpoint 2 IN_PKT_RDY (falling edge) selected as hardware transfer request source. Figures 2.5.16 and 2.5.17 show a setting of the related registers and Figure 2.5.18 shows a control procedure. If data are transferred from USB FIFOs to external FIFOs as well as this, use USB endpoint 2 OUT_PKT_RDY (rising edge) selected as hardware transfer request source. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 91 of 202 APPLICATION 7643 Group 2.5 DMAC Clock control register (address 1F16) b7 b0 CCR 0 00000 φ = f(XIN)/2 Frequency synthesizer multiply register 1 (address 6D16) b7 b0 FSM1 0016 Frequency synthesizer multiply register 2 (address 6E16) b7 b0 FSM2 FF16 Frequency synthesizer control register (address 6C16) b7 b0 FSC 01000001 Frequency synthesizer enabled f(XIN) selected as frequency synthesizer input USB control register (address 1316) b7 b0 USBC 1 1100 0 “H” current for USB line driver USB line driver enabled USB clock enabled USB block enabled USB endpoint index register (address 5816) b7 b0 USBINDEX 010 Endpoint 2 USB endpoint FIFO mode register (address 5F16) b7 b0 USBFIFOMR 1XXX FIFO size selection bit For endpoint 2 IN 128 bytes,OUT 128 bytes USB endpoint 2 IN max. packet size register (address 5B16) b7 b0 IN_MAXP 128 128 bytes USB endpoint 2 IN control register (address 5916) b7 b0 IN_CSR 1 IN_PKT_RDY bit AUTO_SET bit DMAC index and status register (address 3F16) b7 b0 DMAIS 0 Channel 0 accessible DMAC channel 0 source registers Low, High (addresses 4216, 4316) b7 b0 DMA0SL XX16 b7 b0 External FIFO address (low-order) DMA0SH XX16 External FIFO address (high-order) Fig. 2.5.16 Setting of relevant registers (1) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 92 of 202 APPLICATION 7643 Group 2.5 DMAC DMAC channel 0 destination registers Low, High (addresses 4416, 4516) b7 b0 DMA0DL 6216 USB endpoint 2 FIFO address (low-order) b7 b0 DMA0DH 0016 USB endpoint 2 FIFO address (high-order) DMAC channel 0 transfer count registers Low, High (addresses 4616, 4716) b7 b0 DMA0CL 127 128-byte counts b7 b0 DMA0CH 0 High-order of transfer counter DMAC channel 0 mode register 1 (address 4016) b7 b0 DMA0M1 100 0 0 DMAC channel 0 source register increment/decrement disabled DMAC channel 0 destination register increment/decrement disabled Channel 0 enabled after count register underflow Burst transfer mode selected USB interrupt enable register 1 (address 5416) b7 b0 USBIE1 00 USB endpoint 2 IN interrupt disabled USB endpoint 2 OUT interrupt disabled Interrupt request register A (address 0216) b7 b0 IREQA 0 DMAC0 interrupt request Interrupt control register A (address 0516) b7 b0 ICONA 1 0 USB function interrupt disabled DMAC0 interrupt enabled DMAC channel 0 mode register 2 (address 4116) b7 b0 DMA0M2 11010110 USB endpoint 2 IN_PKT_RDY signal hardware transfer request source Software transfer trigger requesting Reset of channel 0 capture register Channel 0 enabled Fig. 2.5.17 Setting of relevant registers (2) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 93 of 202 APPLICATION 7643 Group 2.5 DMAC RESET Initialization SEI CCR (address 1F16) FSM1 (address 6D16) FSM2 (address 6E16) FSD (address 6F16) FSC (address 6C16) USBC (address 1316) USBINDEX (address 5816) USBFIFOMR (address 5F16) q x: This bit is not used here. Set it to “0” or “1” arbitrarily. IN_MAXP (address 5B16) IN_CSR (address 5916) DMAIS (address 3F16) DMA0SL (address4216) DMA0SH (address 4316) DMA0DL (address4416) DMA0DH (address 4516) DMA0CL (address4616) DMA0CH (address 4716) DMA0M1 (address 4016) USBIE1 (address 5416) IREQA (address 0216) ICONA (address 0516) DMA0M2 (address 4116) CLI ..... 0016 0016 FF16 0016 4116 101100X02 000000102 000010002 8016 1XXXXXXX2 0XXXXX002 XX16 XX16 6216 0016 7F16 0016 100X0X0X2 0000XXXX2 0016 XXX1XXX02 110101102 •USB initialization •Maximum packet size of 128 bytes •External FIFO for source register •USB FIFO1 for destination register •USB endpoint 2 IN_PKT_RDY as hardware transfer request source •USB endpoint 2 IN and OUT interrupts disabled •DMAC channel 0 USB and master CPU bus interface disabled •After confirming external FIFO state, generate the software transfer trigger request ..... DMAC channel 0 interrupt Note 1: When using Index X mode flag (T) 2: When using Decimal mode flag (D) •Push registers used in interrupt process routine CLT (Note 1) CLD (Note 2) Push registers to stack Y Data is available in external FIFO ? N DMA0M2 (address 4116), bit 7 0 •If a data is deficient, stop the DMA transferring. After all data have been available, resume the transfer. Pop registers R TI Fig. 2.5.18 Control procedure Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 94 of 202 APPLICATION 7643 Group 2.5 DMAC 2.5.7 N otes on DMAC (1) Transfer time • One-byte data transfer requires 2 cycles of φ ( read and write cycles). •To perform DMAC transfer due to the different transfer requests on the same DMAC channel or DMAC transfer between both DMAC channels, 1 cycle of φ or more is needed before transfer is started. (2) Priority • The DMAC places a higher priority on channel-0 transfer requests than on channel-1 transfer requests. If a channel-0 transfer request occurs during a channel-1 burst transfer operation, the DMAC completes the next transfer source and destination read/write operation first, and then stops the channel-1 transfer operation. The channel-1 transfer operation which has been suspended is automatically resumed from the point where it was suspended so that channel-1 transfer can complete its one-burst transfer unit. This will be performed even if another channel-0 transfer request occurs. • The suspended transfer due to the interrupt can also be resumed during its interrupt process routine by writing “ 1 ” t o the DMAC channel x enable bit (DxCEN). (3) Related registers •A read/write must be performed to the source registers, transfer destination registers and transfer count registers as follows: Read from each higher byte first, then the lower byte Write to each lower byte first, then the higher byte. Note that if the lower byte is read out first, the values are the higher byte ’ s. • Do not access the DMAC-related registers by using a DMAC transfer. The destination address data and the source address data will collide in the DMAC internal bus. •When setting the DMAC channel x enable bit (bit 7 of address 4116) to “1”, be sure simultaneously to set the DMAC channel x transfer initiation source capture register reset bit (bit 6 of address 41 16) to “1”. If this is not performed, an incorrect data will be transferred at the same time when the DMAC is enabled. (4) DMA OUT p in In the memory expansion mode and microprocessor mode, the DMA OUT pin (P3 3/DMAOUT) outputs “ H ” d uring a DMA transfer. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 95 of 202 APPLICATION 7643 Group 2.6 USB 2.6 USB The 7643 Group USB Function Control Unit (USB FCU) complies with the Full-Speed USB2.0 Specification, which defines the following four USB transfer types. q C ontrol t ransfer q I nterrupt transfer q B ulk transfer q I sochronous transfer The 7643 Group default transfer mode is the bulk transfer. Interrupt (rate feedback) transfer is performed by endpoints 1 and 2, which need to be initialized accordingly. Control transfer is only performed by endpoint 0; the transfer format is the same as that of the bulk transfer. To use a USB interrupt, set the USB enable bit (USBC7) to “1”. This paragraph explains the registers setting method and the notes related to USB. 2.6.1 USB outline (1) Transfer types The USB specification is generally divided into two sections: the host side (PC, Hub) which controls the peripherals, and the peripheral side (devices), indicating the peripherals that are connected to the host. In addition, the peripheral side has two communication (transfer) specifications which are applied according to the data to be transferred: the Full-Speed function supports high transfer speeds (12Mbps) for peripherals requiring large amounts of data transferred at one time (images, voice, etc.) and the Low-Speed function supports lower transfer speeds (1.5Mbps) for peripherals sending smaller amounts of data (keyboard, mouse, etc). The recent addition of the Hi-Speed function (480Mbps) specification allows for even faster data transfer. The communication specification to be used is determined by the Device Class of the peripheral, and the transfer type is determined according to each peripheral device. The 7643 Group is equipped with a Full-Speed Function Control Unit, which supports the following three transfer types. Control transfer Control transfer is a request-response, bi-directional transfer in the non-periodic and bursty communications. These are typically used during setup. As all devices must support standard device requests, all USB products support control transfers with no exception. Bulk transfer Bulk transfer is a non-periodic and bursty communication which is not adversely affected by delays. These are typically used for transfers of large amounts of data. To ensure that the data is transferred successfully, hardware is set to check for errors. If an error is detected, the data is resent. Examples of bulk transfer are word data to printers and image data from scanners. Interrupt transfer Interrupt transfer is used to inform the host of periodic, low-frequency data communication from the device. For example, interrupt transfer informs the host that the printer is out of paper or send data from the mouse or keyboard to the host. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 96 of 202 APPLICATION 7643 Group 2.6 USB (2) Communication protocol The host CPU does control a ll USB communications. Even when data is transmitted to the host from the device, the transmission is executed after the host gives the device the right to use the bus. In order for the host to process multiple transfers simultaneously, each transfer is scheduled in packet units within 1ms frame. The diagram below shows an image of one frame. 1ms SOF Audio mouse printer/scanner SOF Audio 1ms printer/scanner 1ms SOF Audio mouse printer/scanner Isochronous transfer Interrupt transfer Bulk transfer Fig. 2.6.1 1 frame image q P acket A packet is the unit used by the host CPU or the device to secure use of the bus. In USB communications, data is transmitted and received in packet units. A packet is a group of data string (field) of some bits. It starts from a SYNC (synchronous data) field and continues to a PID (Packet ID) field. Each type of packet can be identified by this PID field. The following is a list of packet types. SOF packet : indicates the packet of frame start that Host sends every 1 ms. 8 bits 8 bits 5 bits PID Frame number CRC5 PID : SOF(0xA5) Token packet : indicates the packet Host sends at transaction start. 8 bits 7 bits 4 bits 5 bits PID ADDR ENDP CRC5 PID : OUT(0xE1),IN(0x69),SETUP(0x2D) Data packet : indicates the packet to transfer data. 8 bits 0 to 1023 bytes 16 bits PID DATA CRC16 PID : DATA0(0xC3),DATA1(0x4B) Handshake packet : indicates the packet in transaction to control the flow. 8 bits PID PID : ACK(0xD2),NAK(0xA5),STALL(0x1E) The start of each packet is SOP. The end of each packet is EOP. Fig. 2.6.2 Packet type Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 97 of 202 APPLICATION 7643 Group 2.6 USB Table 2.6.1 USB PID list PID PID bit structure type name (bit 3 to bit 0) Token SETUP 11012 IN 10012 OUT 00012 SOF 01012 DATA0 00112 Data DATA1 10112 ACK 00102 10102 Handshake NAK STALL 11102 Outline of processing Host CPU informs device of operation process. Host CPU requests data transmit from device. Host CPU requests data receive from device. Host CPU informs start of frame to device. Indicates that the number of transfer data sequence bits is even. Indicates that the number of transfer data sequence bits is odd. Reports that data transmit was successfully completed. Reports that the device is in the transfer ready status. Reports that transfer was completed successfully. q Transaction A transaction is the unit in which the host CPU schedules 1 frame. Each transaction is comprised of packets. The transaction format is shown below. ➀ IN transaction (Idle state) IN DATA0/1 ACK (Idle state) ➃ Isochronous transaction (IN) (Idle state) IN DATA0/1 (Idle state) NAK STAL L ➁ OUT transaction (Idle state) OUT DATA0/1 ACK NAK STALL (Idle state) ➂ SETUP transaction (Idle state) SETUP DATA0 ACK (Idle state) ➃ Isochronous transaction (OUT) (Idle state) OUT DATA0/1 (Idle state) : Token packet sent by host : Handshake packet sent by host : Date packet sent by host : Date packet sent by device : Handshake packet sent by device Fig. 2.6.3 Transaction format Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 98 of 202 APPLICATION 7643 Group 2.6 USB (3) Communication sequence Each transfer type has a different transfer sequence, as described below. Control transfer communication sequence The control transfer is the common transfer type used at setup for all devices. Each transfer process consists of three different stages. The control transfer starts with the setup stage. Based on the contents of the Setup stage, the data stage (control Read transfer or control Write transfer) is executed. When the transfer is complete, the status stage is executed, completing one full process. Endpoint 0 is always used for control transfer. Figure 2.6.4 shows the communication sequence for a control transfer. Control transfer q Control Read Setup stage SETUP Data stage IN Status stage OUT DATA0 DATA1/0 DATA1 Handshake Handshake Handshake q Control Write Setup stage SETUP Data stage OUT Status stage IN DATA0 DATA1/0 DATA1 Handshake Handshake Handshake q No control data Setup stage Status stage IN SETUP DATA0 DATA1 : Host issue Handshake Handshake : Device issue Fig. 2.6.4 Communication sequence of control transfer Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 99 of 202 APPLICATION 7643 Group 2.6 USB Control Read transfer After the SETUP transaction, the IN transaction is repeated to transmit data from the device to the host (data stage). Then, in order to wait for the host to finish processing the data, an IN transaction of data empty is executed (status stage). Control Write transfer After the SETUP transaction, the OUT transaction is repeated to transmit data from the host to the device (data stage). Then, in order that host waits the device to finish processing the data, an IN transaction of data empty is executed (status stage). No data After the SETUP transaction, if there is no request for data to be transmitted/received in the data stage, in order that host waits for the device to finish processing, an IN transaction of data empty is executed (status stage). The status stage is used for reporting the results of the setup and data stage operations to the host CPU. The responses used in the status stage are as follows. - Function completed normally Control Write transfer … Data packet Control Read transfer … ACK handshake - Error detected in function Control Write transfer … STALL handshake Control Read transfer … STALL handshake - Function in busy state Control Write transfer … NAK handshake Control Read transfer … NAK handshake Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 100 of 202 APPLICATION 7643 Group 2.6 USB q D evice request The SETUP transaction in the setup stage of a control transfer is called a device request. The device request defines the format of its data phase. When type is standard (0): Standard device request This is the basic device request necessary for all USB devices. When type is class (1): Class device request Device class is defined by the USB Implementers Forum (USB IF). The USB IF also determines the requested configuration and class request. Please refer to the Full-Speed USB2.0 specification for more details on each data format. q B ulk transfer Bulk IN transfer The bulk IN transfer, which transmits data from the device to host CPU, continually repeats IN transactions. The 7643 MCU issues a data packet in response to an IN token. When the data is not transmitted successfully, the MCU sends one of the following responses. - No response if the received IN token is broken. - STALL handshake is returned if 7643 Group is stalled. - NAK packet is returned if there is no transmit data in the IN FIFO. Bulk OUT Transfer The bulk OUT transfer, which transmits data from the host CPU to the device, continually repeats OUT transactions. When the 7643 MCU receives a data packet successfully, an ACK packet is returned. A successful receive is the state in which there is no bit-stuffing error or CRC error, and the data PID was received correctly. DATA0 and DATA1 of data packet of next data phase are toggled during the handshake phase of each transaction if the ACK packet sent by the receive side is received successfully by the transmit side. The 7643 MCU transmits the following responses when data is not successfully received. - No response if the received data is broken. - STALL handshake is returned if 7643 Group is stalled. - ACK packet is returned if inconsistency of sequence bit in received data. - NAK packet is returned if the 7643 Group OUT FIFO is full. For more details, refer to the Full-Speed USB2.0 specification. q I nterrupt transfer The interrupt transfer format is the same as that of the bulk transfer. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 101 of 202 APPLICATION 7643 Group 2.6 USB (4) Device State The device has various states and can transit states. In the 7643 Group, control the state transition by software, not hardware. Enumelation is the continuous process from bus connection to system configuration. Connecting HUB configuration HUB configuration released Bus no active Power on Bus active Bus reset Power off Bus no active Default Bus active Set address request Bus no active Address Bus active Set Configuration request Bus no active Configuration Bus active Suspend Suspend Suspend Suspend Fig. 2.6.5 Device state transition 1. Connection state: When the device is connected to the bus. 2. Power-on state: When the HUB has been configured and power is supplied to the bus. 3. Default state: When a reset signal is received from the host CPU. Default address (0) is configured. 4. Address assignment state: When the SET_ADDRESS standard device request is received. This is the unconfigured state (configuration 0). 5. The device is configured when the SET_CONFIGURATION standard device request is received. 6. Suspend state: When there is no activity on the bus for a 3ms period. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 102 of 202 APPLICATION 7643 Group 2.6 USB 2.6.2 Memory map 001316 USB control register (USBC) 005016 USB address register (USBA) 005116 USB power management register (USBPM) 005216 USB interrupt status register 1 (USBIS1) 005316 USB interrupt status register 2 (USBIS2) 005416 USB interrupt enable register 1 (USBIE1) 005516 USB interrupt enable register 2 (USBIE2) 005816 USB endpoint index register (USBINDEX) 005916 USB endpoint x IN control register (IN_CSR) 005A16 USB endpoint x OUT control register (OUT_CSR) 005B16 USB endpoint x IN max. packet size register (IN_MAXP) 005C16 USB endpoint x OUT max. packet size register (OUT_MAXP) 005D16 USB endpoint x OUT write count register (WRT_CNT) 005F16 USB endpoint FIFO mode register (USBFIFOMR) 006016 USB endpoint 0 FIFO (USBFIFO0) 006116 USB endpoint 1 FIFO (USBFIFO1) 006216 USB endpoint 2 FIFO (USBFIFO2) Fig. 2.6.6 Memory map of registers related to USB Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 103 of 202 APPLICATION 7643 Group 2.6 USB 2.6.3 Related registers (1) USB control register This register is used for all operation controls performed by the USB function control unit (USB FCU). USB reset does not affect this register. q U SB default state selection bit This bit selects the cases in which the USB core state machine ‘state’ (the section that controls transitions of the USB core state) will return to the default state. However, without regard to this bit, USB internal registers (addresses 005016 to 005F16) go into the states at reset (default state) at the same time when USB reset is detected. When this bit is “ 0 ” , the state returns to the default state at power-on/reset. When this bit is “ 1 ” , the state returns to the default state when the USB reset is received (recommended). q U SB line driver current control bit This bit is used to reduce the amount of USB dissipation power. Set to “ 1 ” f or the suspend state, but always set to “ 0 ” f or USB control operations. When using the MCU in Vcc = 3.3V, the value of this bit does not affect USB operations. q U SB line driver supply enable bit Set this bit to “ 1 ” t o use the USB built-in DC-DC converter when using the MCU in Vcc = 5V. The built-in DC-DC converter is disabled when this bit is “ 0 ” ; therefore, set to “ 0 ” w hen using the MCU in Vcc = 3.3V. q U SB clock enable bit Set this bit to “ 1 ” t o enable the USB clock. q U SB enable bit Set to “1” to enable the USB function. Make sure you include a 250ns wait after setting the bit to “ 1 ” t o read from/write to other USB-related registers. Figure 2.6.7 shows the structure of USB control related register. USB control register b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 USB control register (USBC : address 1316) b Name Functions At reset R W 0 0 0 Nothing is arranged for this bit. Fix this bit to “0”. 1 USB default state selection 0 : In default state after power-on/reset bit (USBC1) 1 : In default state after USB reset signal received (Note 1) 2 Nothing is arranged for this bit. Fix this bit to “0”. 3 USB line driver current 0 : High current mode 1 : Low current mode control bit (USBC3) 0 : Line driver disabled 4 USB line driver supply enable bit (USBC4) (Note 2) 1 : Line driver enabled 0 : 48 MHz clock to the USB block disabled 5 USB clock enable bit 1 : 48 MHz clock to the USB block enabled (USBC5) 6 Nothing is arranged for this bit. Fix this bit to “0”. 0 : USB block disabled (Note 3) 7 USB enable bit (USBC7) 1 : USB block enabled 0 0 0 0 0 0 Notes 1: Without regard to this bit, USB internal registers (address 005016 to 005F16) go into the states at reset (default) at the same time when USB reset is detected. 2: When using the MCU in Vcc = 3.3 V, set this bit to “0” and disable the built-in DCDC converter. 3: Setting this bit to 0” causes the contents of all USB registers to have the values at reset. Fig. 2.6.7 Structure of USB control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 104 of 202 APPLICATION 7643 Group 2.6 USB (2) USB address register This register maintains the 7-bit USB function control unit (USB FCU) address assigned by the host CPU. The USB FCU stores addresses of USB token packets by using the value of this register. The value of this register is “ 00 16” w hen the device is not yet configured at reset. Figure 2.6.8 shows the structure of the USB address register. USB address register b7 b6 b5 b4 b3 b2 b1 b0 0 USB address register (USBA : address 5016) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 This register maintains the 7-bit USB function control unit address assigned by the host CPU. 1 2 3 4 5 6 7 Nothing arranged for this bit. Fix this bit to “0”. Fig. 2.6.8 Structure of USB address register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 105 of 202 APPLICATION 7643 Group 2.6 USB (3) USB power management register This register is used for power management in the USB FCU. q U SB suspend detection flag If no activity is detected on the D+/D- line for a period of 3ms, this flag is set to “1” and a USB suspend interrupt occurs. When the USB resume detection flag is set to “1” after the MCU returns from the USB suspend state by a USB resume interrupt, the USB suspend detection flag is automatically cleared to “0”. Even if the USB remote wake-up bit is cleared to “ 0 ” a fter the MCU returns from the suspend state by a remote wake-up (USB remote wake-up bit set to “ 1 ” ), the suspend detection flag is not automatically cleared to “ 0 ” . Clear this flag to “ 0 ” b y software. q U SB resume detection flag When a non-idle signal is detected on the D+/D- line in the suspend mode, this flag is set to “1” and a USB resume interrupt occurs. This flag is cleared to “0” when the USB resume signal interrupt status flag of USB interrupt status register 2 is cleared to “ 0 ” . q U SB remote wake-up bit Set this bit to “1” after the MCU returns from the USB suspend state by a remote wake-up (INT interrupt, etc.). While this bit is “ 1 ” , the USB FCU sends a resume signal to the host CPU, informing it of the return from the suspend state. Clear the bit to “ 0 ” a fter holding it at “ 1 ” f or 10ms to 15ms. Figure 2.6.9 shows the structure of the USB power management register. USB power management register b7 b6 b5 b4 b3 b2 b1 b0 00000 USB power management register (USBPM : address 5116) b Name Functions 0 : No USB suspend detected 1 : USB suspend detected (Note 1) 0 : No USB resume signal detected 1 : USB resume signal detected 0 : End of remote resume signal 1 : Transmitting of remote resume signal (only when SUSPEND = “1”) (Note 2) At reset R W 0 0 0 ✕ ✕ 0 USB suspend detection flag (SUSPEND) 1 USB resume detection flag (RESUME) 2 USB remote wake-up bit (WAKEUP) 3 Nothing arranged for these bits. Fix these bits to 4 5 6 7 0 0 0 0 0 Notes 1: This bit is cleared when the WAKEUP bit is “1”. 2: When the SUSPEND bit is “1”, set this bit to “1” and keep “1” for 10 ms to 15 ms. Fig. 2.6.9 Structure of USB power management register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 106 of 202 APPLICATION 7643 Group 2.6 USB (4) USB interrupt status registers 1, 2 These registers are used to determine the state of a USB function interrupt source. When an interrupt request occurs, the flag corresponding to the interrupt source is set to “ 1 ” . After “1” is read from each flag in this register, they are cleared to “0” when the next “1” is written. This flag is not cleared even if “ 0 ” i s written. Make sure to write to/read from the USB interrupt status register 1 first and then USB interrupt status register 2. Figures 2.6.10 and 2.6.11 show the structures of USB interrupt status registers 1 and 2, respectively. USB interrupt status register 1 b7 b6 b5 b4 b3 b2 b1 b0 00 0 USB interrupt status register 1 (USBIS1 : address 5216) b Name Functions 0 : Except the following conditions 1 : Set at any one of the following conditions: • A packet data of endpoint 0 is successfully received • A packet data of endpoint 0 is successfully sent • DATA_END bit of endpoint 0 is cleared to “0” • FORCE_STALL bit of endpoint 0 is set to “1” • SETUP_END bit of endpoint 0 is set to “1”. At reset R W 0 ✽ 0 USB endpoint 0 interrupt status flag (INTST0) 1 Nothing arranged for this bit. Fix this bit to “0”. 2 USB endpoint 1 IN 0 : Except the following conditions interrupt status flag 1 : Set at which of the following (INTST2) condition: • A packet data of endpoint 1 is successfully sent 3 USB endpoint 1 OUT interrupt status flag (INTST3) 0 : Except the following conditions 1 : Set at any one of the following conditions: • A packet data of endpoint 1 is successfully received • FORCE_STALL bit of endpoint 1 is set to “1”. 0 : Except the following conditions 1 : Set at which of the following condition: • A packet data of endpoint 2 is successfully sent 0 : Except the following conditions 1 : Set at any one of the following conditions: • A packet data of endpoint 2 is successfully received • FORCE_STALL bit of endpoint 2 is set to “1”. 0 0 ✽ 0 ✽ 4 USB endpoint 2 IN interrupt status flag (INTST4) 0 ✽ 5 USB endpoint 2 OUT interrupt status flag (INTST5) 0 ✽ 6 Nothing arranged for these bits. 7 Fix these bits to “0”. ✽: “0” can be set by software, but “1” cannot be set. To clear the bit set to “1”, write “1” to the bit. 0 0 Fig. 2.6.10 Structure of USB interrupt status register 1 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 107 of 202 APPLICATION 7643 Group 2.6 USB USB interrupt status register 2 b7 b6 b5 b4 b3 b2 b1 b0 00000 USB interrupt status register 2 (USBIS2 : address 5316) b Name Functions At reset R W 0 0 0 0 0 0 0 ✽ ✽ 0 Nothing arranged for these bits. Fix these bist to “0”. 1 2 3 4 5 USB reset interrupt status 0 : Except the following conditions 1 : Set at receiving of USB reset signal flag (INTST13) 6 USB resume signal interrupt status flag (INTST14) 7 USB suspend signal interrupt status flag (INTST15) 0 : Except the following conditions 1 : Set at receiving of resume signal 0 : Except the following conditions 1 : Set at receiving of suspend signal 0 ✽ ✽: “0” can be set by software, but “1” cannot be set. To clear the bit set to “1”, write “1” to the bit. Fig. 2.6.11 Structure of USB interrupt status register 2 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 108 of 202 APPLICATION 7643 Group 2.6 USB (5) USB interrupt enable registers 1, 2 The USB interrupt enable registers are used to enable the USB function interrupt. Upon reset, all USB interrupts except the USB suspend and USB resume interrupts are enabled. The USB reset interrupt does not have an enable bit and is always in the enabled state. Figures 2.6.12 shows the structures of USB interrupt enable registers 1 and 2. USB interrupt enable register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 USB interrupt enable register 1 (USBIE1 : address 5416) b Name Functions At reset R W 1 1 1 1 1 1 ✕ ✕ 0 USB endpoint 0 interrupt 0 : Disabled enable bit (INTEN0) 1 : Enabled 1 Nothing arranged for this bit. Fix this bit to “0”. 2 USB endpoint 1 IN interrupt 0 : Disabled 1 : Enabled enable bit (INTEN2) 3 USB endpoint 1 OUT inter- 0 : Disabled 1 : Enabled rupt enable bit (INTEN3) USB endpoint 2 IN interrupt 0 : Disabled 4 1 : Enabled enable bit (INTEN4) 5 USB endpoint 2 OUT inter- 0 : Disabled 1 : Enabled rupt enable bit (INTEN5) 6 Nothing is arranged for these bits. When these bits are read out, the 7 contents are undefined. These bits are “0” at write. USB interrupt enable register 2 b7 b6 b5 b4 b3 b2 b1 b0 01 00 USB interrupt enable register 2 (USBIE2 : address 5516) b Name Functions At reset R W ✕ ✕ 0 0 ✕ 1 0 0 0 Nothing is arranged for this bit. When this bit is read out, the contents 1 are undefined. This bit is “0” at write. 2 Nothing is arranged for these bits. Fix these bits to “0”. 3 4 Nothing is arranged for this bit. When this bit is read out, the contents are undefined. This bit is “0” at write. 5 Nothing is arranged for this bit. Fix this bit to “1”. 6 Nothing is arranged for this bit. Fix this bit to “0”. 0 : Disabled 7 USB suspend/resume interrupt enable bit (INTEN15) 1 : Enabled Fig. 2.6.12 Structure of USB interrupt enable register 1, USB interrupt enable register 2 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 109 of 202 APPLICATION 7643 Group 2.6 USB (6) USB endpoint index register Endpoint index bits These bits specify the accessible endpoint. These bits serve as an index of the following registers; - USB endpoint x (x=0 to 2) IN control register - USB endpoint x (x=1 to 2) OUT control register - USB endpoint x (x=0 to 2) IN max. packet size register - USB endpoint x (x=0 to 2) OUT max. packet size register - USB endpoint x (x=0 to 2) OUT write count register - USB endpoint FIFO mode register (only endpoint 1 and endpoint 2) Figure 2.6.13 shows the structure of the USB endpoint index register. USB endpoint index register b7 b6 b5 b4 b3 b2 b1 b0 00000 USB endpoint index register (USBINDEX : address 5816) b Name b2b1b0 Functions 0 0 0 : Endpoint 0 0 0 1 : Endpoint 1 0 1 0 : Endpoint 2 0 1 1 : Not used 1 0 0 : Not used 1 0 1 : Not used 1 1 0 : Not used 1 1 1 : Not used At reset R W 0 0 Endpoint index bit (EPINDEX) 1 2 0 0 0 0 0 0 0 3 Nothing is arranged for these bits. Fix these bits to “0”. 4 5 6 7 Fig. 2.6.13 Structure of USB endpoint index register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 110 of 202 APPLICATION 7643 Group 2.6 USB (7) USB endpoint 0 IN control register This register comprises the bits related to endpoint 0 control and status information. q O UT_PKT_RDY flag This flag is set to “1” when a valid SETUP/OUT token is received from the host CPU. After the OUT FIFO is read, clear this flag to “ 0 ” b y writing “ 1 ” t o the SERVICED_OUT_PKT_RDY bit. (However, do not clear this flag to “0” until the request from the host CPU has been completely decoded.) Nothing is changed even when writing “ 1 ” t o this flag is executed. q I N_PKT_RDY bit Set this bit to “ 1 ” a fter writing one packet of data to the endpoint 0 IN FIFO. The USB FCU clears this bit to “ 0 ” a fter an IN FIFO transmit or when the SETUP_END flag is set to “ 1 ” . Nothing is changed even when writing “ 0 ” t o this flag is executed. q S END_STALL bit Set this bit to “ 1 ” w hen an invalid standard request is received from the host CPU. When the OUT_PKT_RDY flag to receive the request is set to “0”, the USB FCU sends a STALL handshake signal to the host CPU in response to all IN/OUT transactions. Write “ 0 ” t o this bit to clear it. If the OUT_PKT_RDY flag is “ 1 ” w hen the SEND_STALL bit is set to “1”, the OUT_PKT_RDY flag can be cleared to “0” by setting the SERVICED_OUT_PKT_RDY bit to “ 1 ” . q D ATA_END bit When the last data is written to the FIFO (IN data phase) or the last data is read from the FIFO (OUT data phase), set this bit to “ 1 ” . This informs the USB FCU that all data set in the setup phase has been completely processed. The USB FCU sets this bit to “ 0 ” a utomatically after the status phase process is completed. When this bit is “1”, data receive and data transmit requests from the host are ignored. The USB FCU sends a STALL handshake signal to the host CPU and completes the current control operation. q F ORCE_STALL flag This flag is set to “ 1 ” f or an error report if any of the following conditions occur. - An IN/OUT token is received which does not have a setup stage. - An incorrect data toggle is received (DATA0) in the status stage. - An incorrect data toggle is received (DATA1) in the setup stage. - A request for more data than requested in the setup stage (an IN token is received after the DATA_END bit is set). - A data receive for more data than specified in the setup stage (an OUT token is received after the DATA_END bit is set). - More data is received than the number of bytes in the maximum packet size of the corresponding endpoint. Excluding the case in which an incorrect data toggle occurs in the setup stage, when one of the above conditions occurs, a STALL is sent in response to the problematic IN/OUT token. When there is an incorrect data toggle in the setup stage, an ACK is returned in response to the setup stage, and a STALL is returned in response to the next IN/OUT token. The generated STALL handshake is transmitted in response to only one transaction, and the control transfer in process is completed. The next packet received after the STALL handshake is recognized as the beginning of a new control transfer. Write “ 0 ” t o this flag to clear it. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 111 of 202 APPLICATION 7643 Group 2.6 USB q S ETUP_END flag During a control transfer, if the process is terminated before the number of data bytes, as set in the data stage process, is completed, the SETUP_END flag will go to “ 1 ” . Clear the SETUP_END flag to “ 0 ” b y setting the SERVICED_SETUP_END bit to “ 1 ” . When this flag is set to “1”, you need to disable the access to the FIFO and execute the setup process before it. When this flag is set to “ 1 ” , the data in the IN FIFO is automatically flushed out. If this flag and the OUT_PKT_RDY flag are set to “ 1 ” a t the same time, it indicates that the previous setup process has been completed and there is a new SETUP token in the FIFO. q SERVICED_OUT_PKT_RDY bit Setting this bit to “ 1 ” c lears the OUT_PKT_RDY flag to “ 0 ” . q S ERVICED_SETUP_END bit Setting this bit to “ 1 ” c lears the SETUP_END flag to “ 0 ” . Figure 2.6.14 shows the structure of the USB endpoint x (x = 0 to 2) IN control register. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 112 of 202 APPLICATION 7643 Group 2.6 USB (8) USB endpoint 1, 2 IN control register These registers comprise bits related to endpoints 1 and 2 control and status information. q I N_PKT_RDY bit Single-buffer mode: Set this bit to “ 1 ” a fter writing one packet of data to the IN FIFO (this bit is automatically set to “ 1 ” w hen AUTO_SET bit is “ 1 ” ). The USB FCU clears this bit to “ 0 ” w hen the IN FIFO transmit is completed (after the ACK is received from the host). Double-buffer mode: Set this bit to “ 1 ” e very writing one packet of data to the IN FIFO. After writing one packet of data, if there is one packet in the FIFO, the IN_PKT_RDY bit is not set to “1”; only the TX_NOT_EPT flag is set to “1”. If the FIFO has two packets (FIFO full state) after the write, both the IN_PKT_RDY bit and TX_NOT_EPT flag are set to “ 1 ” ( refer to Table 2.6.2). The USB FCU clears this bit to “ 0 ” w hen the IN FIFO transmit is completed (after the ACK is received from the host). Nothing is changed even when writing “0” to this flag is executed. When you need to access this bit in a case such as setting other bits in the endpoint x IN control register is performed, clear this bit to “ 0 ” b y program. q S END_STALL bit Set this bit to “ 1 ” i n the STALL state. When this bit is “ 1 ” , the USB FCU sends a STALL handshake signal to the host CPU. q T OGGLE_INIT bit This bit initializes the toggle sequence bit. Setting the TOGGLE_INIT bit to “1” assigns the PID of the next packet of data to be transmitted to the host as DATA0. To initialize the data toggle sequence bit for an endpoint (reset the next data packet as DATA0), set this bit to “ 1 ” a nd then clear it to “ 0 ” . q I NTPT bit Set this bit to “1” in order to use an IN endpoint for rate feedback interrupt transfer, as described in detail below. 1. Set the USB endpoint x IN maximum packet size register to a value larger than 1/2 the USB endpoint x FIFO size. 2. Set the INTPT bit to “ 1 ” . 3. Flush out the old data in the FIFO. 4. Store the transmit data in the IN FIFO and set IN_PKT_RDY bit to “ 1 ” . 5. Repeat steps 3 and 4. When using the endpoint for rate feedback interrupt transfer in an actual application, the functionside always must have transmit data to send to the host. Therefore, in a rate feedback interrupt transfer, the device never returns a NAK in response to the IN token from the host. The device transmits the data in the FIFO in response to an IN token regardless of the IN_PKT_RDY status. However, this function in the 7643 Group assumes that there is an ACK response from the host after data is transmitted in response to an IN token. q T X_NOT_EPT flag This flag is set to “ 1 ” w hen there is data in the IN FIFO. q F LUSH bit Set this bit to “1” in order to erase the data in the FIFO. If there are two or more packets in the IN FIFO, the old data will be erased. Setting this bit to “1” during a USB transfer may cause the transmit data to be erased. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 113 of 202 APPLICATION 7643 Group 2.6 USB q A UTO_SET bit When this bit is “ 1 ” , if the data written to the IN FIFO matches the max. IN packet size, the IN_PKT_RDY bit is automatically set to “ 1 ” . However, when transmitting a short packet (fewer data packet than the max. packet size), set the IN_PKT_RDY bit to “1” after writing the data to the IN FIFO. Figure 2.6.14 shows the structure of USB endpoint x (0 to 2) IN control registers. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 114 of 202 APPLICATION 7643 Group 2.6 USB USB endpoint 0 IN control register b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint 0 IN control register (IN_CSR : address 5916) b Name Functions 0 : Except the following condition (Cleared to “0” by writing “1” into SERVICED_OUT_PKT_RDY bit) 1 : End of a data packet reception 0 : End of a data packet transmission 1 : Write “1” at completion of writing a data packet into IN FIFO. 0 : Except the following condition 1 : Transmitting STALL handshake signal At reset R W 0 ✽1 0 OUT_PKT_RDY flag (IN0CSR0) 1 IN_PKT_RDY bit (IN0CSR1) 0 ✽2 2 SEND_STALL bit (IN0CSR2) 3 DATA_END bit (IN0CSR3) 0 : Except the following condition (Cleared to “0” after completion of status phase) 1 : Write “1” at completion of writing or reading the last data packet to/from FIFO. 0 : Except the following condition 4 FORCE_STALL flag (IN0CSR4) 1 : Protocol error detected 0 : Except the following condition 5 SETUP_END flag (Cleared to “0” by writing “1” into (IN0CSR5) SERVICED_SETUP_END bit) 1 : Control transfer ends before the specific length of data is transferred during the data phase. 6 SERVICED_OUT_PKT_R 0 : Except the following condition DY bit (IN0CSR6) 1 : Writing “1” to this bit clears OUT_ PKT_RDY flag to “0”. SERVICED_SETUP_END 0 : Except the following condition 7 bit (IN0CSR7) 1 : Writing “1” to this bit clears SETUP_ END flag to “0”. 0 0 ✽2 0 0 ✽1 ✽1 0 0 USB endpoint 1, 2 IN control register b7 b6 b5 b4 b3 b2 b1 b0 0 USB endpoint 1, 2 IN control register (IN_CSR : address 5916) b Name Functions 0 : End of a data packet transmission 1 : Write “1” at completion of writing a data packet into IN FIFO. (Note 2) At reset R W 0 ✽2 0 INT_PKT_RDY bit (INXCSR0) ✽1 1 Nothing is arranged for this bit. Fix this bit to “0”. 0 : Except the following condition 2 SEND_STALL bit (INXCSR2) 1 : Transmitting STALL handshake signal 3 TOGGLE_INIT bit (INXCSR3) 0 : Except the following condition 1 : Initializing the data toggle sequence bit 0 : Except the following condition 1 : Initializing to endpoint used for interrupt transfer, rate feedback 0 0 0 4 INTPT bit (INXCSR4) 0 5 TX_NOT_EPT flag (INXCSR5) 6 FLUSH bit (INXCSR6) 0 : Empty in IN FIFO 1 : Full in IN FIFO 0 : Except the following condition 1 : Flush FIFO 7 AUTO_SET bit (INXCSR7) 0 : AUTO_SET disabled 1 : AUTO_SET enabled ✽3 0 0 0 ✕ ✽1 ✽ 1: “1” can be set by software, but “0” cannot be set. ✽ 2: When INXCSR7=“1”, this bit is automatically set to “1”. When INXCSR7=“0”, writing data to FIFO, and then write “1” to this bit. ✽ 3: To use the AUTO_SET function for an IN transfer when the AUTO_SET bit is set to “1”, set the FIFO to single buffer mode. Fig. 2.6.14 Structure of USB endpoint x IN control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 115 of 202 APPLICATION 7643 Group 2.6 USB (9) USB endpoint x (x = 1, 2) OUT control registers When using endpoint 0, these registers are the reserved registers and cannot be assigned to any function. q O UT_PKT_RDY flag This flag is set to “ 1 ” w hen a data receive from the host CPU is completed. Clear the flag to “0” after the data is read from the OUT FIFO. This flag is automatically cleared to “0” when the AUTO_CLR bit is “1”. To avoid internal Read pointer malfunction, do not clear the flag to “0” until reading out one packet of data from the host is completed. The value of the USB endpoint x OUT write count register is updated when this flag is cleared. When two or more data packets are written to the OUT FIFO in the double-buffer mode, the flag is set to “ 0 ” i f “ 0 ” i s written to it after one packet of data is read, but returns to “ 1 ” a fter 83ns (Vcc = 5V, f(X IN) = 24MHz). USB operations are not affected by writing “1” to this flag. Write “1” to the OUT_PKT_RDY flag to access i t. q S END_STALL bit Set this bit to “ 1 ” i n the STALL state. When this bit is “ 1 ” , the USB FCU sends a STALL handshake signal to the host CPU. q T OGGLE_INIT bit This bit initializes the toggle sequence bit. Setting the TOGGLE_INIT bit to “1” assigns the PID of the next packet received from the host as DATA0. To initialize the data toggle sequence bit of an endpoint (reset the next data packet as DATA0), set this bit to “ 1 ” a nd then clear it to “ 0 ” . q F ORCE_STALL flag This flag is set to “1” when data received from the host CPU is larger than the max. OUT packet size. The USB FCU then sends a STALL handshake signal to the host CPU. Write “ 0 ” t o this flag to clear it. q F LUSH bit Set this bit to “ 1 ” t o erase the data in the OUT FIFO. When there are two or more packets of data in the OUT FIFO, the old data will be erased. Setting this bit to “1” during a transfer may cause the receive data to be erased. When setting the OUT_PKT_RDY flag to “1”, also set this bit to “ 1 ” . q A UTO_CLR bit When this bit is “ 1 ” a nd the size of the data read from the OUT FIFO matches that of the received OUT packet, the OUT_PKT_RDY flag is automatically cleared to “ 0 ” . Figure 2.6.15 shows the structure of the USB endpoint x (x = 1, 2) OUT control register. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 116 of 202 APPLICATION 7643 Group 2.6 USB USB endpoint x OUT control register b7 b6 b5 b4 b3 b2 b1 b0 0 0 USB endpoint x OUT control register (OUT_CSR : address 5A16) b Name Functions At reset R W 0 0 0 0 ✽2 0 : Except the following condition (Note) 0 OUT_PKT_RDY flag (OUTXCSR0) 1 : End of a data packet reception 1 Nothing is arranged for this bit. Fix this bit to “0”. 0 : Except the following condition 2 SEND_STALL bit (OUTXCSR2) 1 : Transmitting STALL handshake signal 3 TOGGLE_INIT bit (OUTXCSR3) 0 : Except the following condition 1 : Enabling reception of DATA0 and DATA1 as PID (Initializing the toggle) 0 : Except the following condition 1 : Protocol error detected 4 FORCE_STALL flag (OUTXCSR4) 5 Nothing is arranged for this bit. Fix this bit to “0”. 0 : Except the following condition 6 FLUSH bit (OUTXCSR6) 1 : Flush FIFO 7 AUTO_SET bit 0 : AUTO_SET disabled (OUTXCSR7) 1 : AUTO_SET enabled 0 0 0 0 ✽1 ✽ 1: “0” can be set by software, but “1” cannot be set. ✽ 2: When OUTXCSR7=“1”, this bit is automatically set to “1”. When OUTXCSR7=“0”, writing data to FIFO, and then write “0” to this bit. Fig. 2.6.15 Structure of USB endpoint x (x=1 to 2) OUT control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 117 of 202 APPLICATION 7643 Group 2.6 USB (10) USB endpoint x (x = 0 to 2) IN max. packet size register This register specifies the maximum packet size (MAXP) of an endpoint x (x = 0 to 2) IN packet. Modify the contents of this register when the SET_DESCRIPTOR command is received from the host CPU. The IN maximum packet sizes (MAXP) are as follows: - When using endpoints 0, 2: MAXP = n - When using endpoint 1: MAXP = n*8 (n: the value set in this register) When not using this register, clear “ 0 ” t o this register. Figure 2.6.16 shows the structure of the USB endpoinx (x = 0 to 2) IN max. packet size register. USB endpoint x IN max. packet size register b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint x IN max. packet size register (IN_MAXP: address 5B16) b Functions At reset R W (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) 0 The maximum packet size (MAXP) of endpoint x IN is contained. 1 qMAXP = n for endpoints 0, 2 2 qMAXP = n ✕ 8 for endpoint 1 “n” is a written value into this register. 3 4 5 6 7 Note: The value is “0116” in the endpoint 1 used. The value is “0816” in the endpoint 0 or 2 used. Fig. 2.6.16 Structure of USB endpoint x (x=0 to 2) IN max. packet size register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 118 of 202 APPLICATION 7643 Group 2.6 USB (11) USB endpoint x (x = 0 to 2) OUT max. packet size register This register specifies the maximum packet size (MAXP) of an endpoint x (x = 0 to 2) OUT packets. Modify the contents of this register when the SET_DESCRIPTOR command is received from the host CPU. The OUT maximum packet sizes (MAXP) are as follows: - When using endpoint 2: MAXP = n - When using endpoint 1: MAXP = n*8 (n: the value set in this register) When not using this register, clear “ 0 ” t o this register. When using the endpoint 0, both USB endpoint x I N max. packet size register (IN _MAXP) and USB endpoint x OUT max. packet size register (OUT_MAXP) are set to the same value. Changing one register ’ s value effectively changes the value o f the other register as well. If the maximum packet size is larger than 1/2 the FIFO size, one packet of data can be stored in the FIFO (single-buffer). If the maximum packet size is less than 1/2 the FIFO size, two packets can be stored (double-buffer). Figure 2.6.17 shows the structure of the USB Endpoinx (x = 0 to 2) OUT max. packet size register. USB endpoint x OUT max. packet size register b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint x OUT max. packet size register (OUT_MAXP: address 5C16) b Functions At reset R W (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) 0 The maximum packet size (MAXP) of endpoint x OUT is contained. 1 qMAXP = n for endpoints 0, 2 2 qMAXP = n ✕ 8 for endpoint 1 “n” is a written value into this register. 3 4 5 6 7 Note: The value is “0816” in the endpoint 0 or 2 used. The value is “0116” in the endpoint 1 used. Fig. 2.6.17 Structure of USB endpoint x (x=0 to 2) OUT max. packet size register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 119 of 202 APPLICATION 7643 Group 2.6 USB (12) USB endpoint x (x = 0 to 2) OUT write count register This is an 8-bit register that contains the number of bytes in the endpoint x (x = 0 to 2) OUT FIFO. This register must be read after the USB FCU has received a packet of data from the host CPU. Refer to this register when reading the data from the OUT FIFO. When there are two packets in the FIFO (double-buffer), the number of bytes of data in the first packet received will be read out from the register. After one packet of data is read from the FIFO and the OUT_PKT_RDY flag is cleared, the value of the register will be updated to the number of bytes of the packet received last. Figure 2.6.18 shows the structure of the USB endpoint x (x = 0 to 2) OUT write count register. USB endpoint x OUT write count register b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint x (x=0 to 2) OUT write count register (WRT_CNT : address 5D16) b Name Functions At reset R W 0 0 0 0 0 0 0 0 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ 0 Contains the number of bytes in endpoint x OUT FIFO. 1 2 3 4 5 6 7 Fig. 2.6.18 Structure of USB endpoint x (x=0 to 2) OUT write count register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 120 of 202 APPLICATION 7643 Group 2.6 USB (13) USB endpoint x (x = 0 to 2) FIFO register These registers are the USB IN (transmit) and OUT (receive). Write data to the corresponding register, and read data from the corresponding register. When the maximum packet size is equal to or less than 1/2 the FIFO size, these registers function in double buffer mode and can hold two packets of data. Figure 2.6.19 shows the structure of the USB endpoint x (x = 0 to 2) FIFO register. USB endpoint x FIFO register b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint x (x=0 to 2) FIFO register (USBFIFOx: addresses 6016, 6116, 6216) b Functions At reset R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 qThis is Endpoint x IN/OUT FIFO. 1 qWrite a data to be transmitted into this IN FIFO. 2 qRead a received data from this OUT FIFO. 3 4 5 6 7 Fig. 2.6.19 Structure of USB endpoint x (x=0 to 2) FIFO register (14) USB endpoint FIFO mode register This register determines the IN/OUT FIFO size mode for endpoint 1 or endpoint 2. Figure 2.6.20 shows the structure of the USB endpoint x FIFO mode register. USB endpoint FIFO mode register b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint FIFO mode register (USBFIFOMR : address 5F16) b Name For endpoint 1 b3b2b1b0 Functions ✕ 0 0 0 : IN 128-byte, OUT 128-byte For endpoint 2 At reset R W 0 0 0 0 0 0 0 0 0 FIFO size selection bit (Note) 1 2 3 b3b2b1b0 0 ✕ ✕ ✕ : IN 32-byte, OUT 32-byte 1 ✕ ✕ ✕ : IN 128-byte, OUT 128-byte 4 Nothing is arranged for these bits. When these bits are read out, the 5 contents are undefined. These bits are “0” at write. 6 7 Note: The value set into “x” is invalid. Fig. 2.6.20 Structure of USB endpoint FIFO mode register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 121 of 202 APPLICATION 7643 Group 2.6 USB (15) Clock control register This register controls all oscillators. The X IN d ivider select bit is valid when CPMA6 and CPMA7 = “ 00 ” When “ 0 ” : f(X IN)/4 is the internal φ c lock. When “ 1 ” : f(X IN)/2 is the internal φ c lock. Note that this bit is cleared to “ 0 ” b y execution of the STP instruction. Figure 2.6.21 shows the structure of the clock control register. Clock control register b7 b6 b5 b4 b3 b2 b1 b0 00000 Clock control register (CCR : address 1F16) b Name Functions At reset R W 0 0 0 0 0 0 0 Nothing is arranged for these bits. 1 Fix these bits to “0”. 2 3 4 5 XCOUT oscillation drive 0 : XCOUT oscillation drive is enabled. disable bit (CCR5) (When XCIN oscillation is enabled.) 1 : XCOUT oscillation drive is disabled. 0 : XOUT oscillation drive is enabled. 6 XOUT oscillation drive disable bit (CCR6) (When XIN oscillation is enabled.) 1 : XOUT oscillation drive is disabled. 0 : f(XIN)/2 is used for the system clock. 7 XIN divider select bit (CCR7) (Note) 1 : f(XIN) is used for the system clock. Note: This bit is valid when (b7, b6 of CPMA) = “00”. 0 0 Fig. 2.6.21 Structure of clock control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 122 of 202 APPLICATION 7643 Group 2.6 USB (16) Frequency synthesizer control register This register performs all controls related to the frequency synthesizer, which generates fUSB and f SYN f rom f(X IN). q F requency synthesizer enable bit Set this bit to “ 1 ” t o use the frequency synthesizer. q F requency synthesizer input bit When this bit is “ 0 ” , f(X IN) is used as the frequency synthesizer input. When “ 1 ” , f(X CIN) is used. q L PF current control bit Bits 6 and 5 = “ 11 ” w hen reset is released. To use the frequency synthesizer, make sure to specify bits 6 and 5 to “10” after the frequency synthesizer is locked. q F requency synthesizer lock status bit When this bit is set to “ 1 ” , it indicates that both f SYN a nd fVCO h ave stabilized. Figure 2.6.22 shows the structure of the frequency synthesizer control register. Frequency synthesizer control register b7 b6 b5 b4 b3 b2 b1 b0 0 00 Frequency synthesizer control register (FSC : address 6C16) b Name Functions At reset R W 0 0 0 0 0 1 1 0 0 Frequency synthesizer enable bit (FSE) 0 : Disabled 1 : Enabled 1 Nothing is arranged for these bits. 2 Fix these bits to “0”. 0 : f(XIN) 3 Frequency synthesizer 1 : f(XCIN) input bit (FIN) 4 Nothing is arranged for this bit. Fix this bit to “0”. 5 LPF current control bit (CHG1, CHG0) (Note) 6 7 Frequency synthesizer lock status bit b1b0 0 0 : Not available 0 1 : Low current 1 0 : Intermediate current (recommended) 1 1 : High current 0 : Unlocked 1 : Locked Note: Bits 6 and 5 are set to (bit 6, bit 5) = (1, 1) at reset. When using the frequency synthesizer, we recommend to set to (bit 6, bit 5) = (1, 0) after locking the frequency synthesizer. Fig. 2.6.22 Structure of frequency synthesizer control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 123 of 202 APPLICATION 7643 Group 2.6 USB 2.6.4 USB transmit Endpoint 0 to endpoint 2 have IN (transmit) FIFOs individually. Each endpoint ’ s FIFO is configured in following way: Endpoint 0: 16-byte Endpoint 1: 128-byte Endpoint 2: Mode 0: 32-byte Mode 1: 128-byte When endpoint 2 is used, the IN FIFO size differs according to the mode. To select the mode, use the USB endpoint FIFO mode register (address 005F 16). USB transmit data is written to the USB endpoint x (x = 0 to 2) FIFO (addresses 0060 16 to 006216). When data is written to this register, the internal Write pointer is automatically incremented by 1. The contents of the internal Write pointer cannot be read out, and the contents of the FIFO are undefined at reset. q W hen using endpoint 0 Set the IN_PKT_RDY bit to “ 1 ” a fter writing transmit data to the IN FIFO. The IN_PKT_RDY bit is set to “ 0 ” a utomatically after one packet of data is transmitted or when the SETUP_END flag is set to “ 1 ” . When using endpoint 0, set the DATA_END bit to “1” when the last data packet has been written to the IN FIFO. When the DATA_END bit is set to “1”, the USB FCU will go on to the next phase process and clear the bit to “ 0 ” . q W hen using endpoints 1, 2 When max. packet size is greater than 1/2 (single buffer) - When AUTO_SET bit = “ 1 ” The IN_PKT_RDY bit (and TX_NOT_EPT flag) is automatically set to “ 1 ” w hen the number of bytes of data written to the IN FIFO equals the value set in the endpoint x IN max. packet size register (address 005B 16). - When AUTO_SET bit = “0” or when a short packet (smaller than max. packet size) is transferred Set the IN_PKT_RDY bit to “ 1 ” b y software. When max. packet size is less than or equal to 1/2 (double buffer) Set the IN_PKT_RDY bit to “ 1 ” b y software after one packet has been written to the IN FIFO. When one packet data is set in the IN FIFO and there is only one packet stored in the IN FIFO, the IN_PKT_RDY bit is set to “1”. However, it is cleared after 83ns (when f(X IN) = 24MHz, Vcc = 5 V), and the TX_NOT_EPT flag then is set to “1”. If there are already two packets in the IN FIFO (IN FIFO full), both the IN_PKT_RDY bit and the TX_NOT_EPT flag are set to “ 1 ” . In the single-buffer mode, the IN_PKT_RDY bit and the TX_NOT_EPT flag will be automatically cleared to “ 0 ” a fter completion of the transmission. In the double-buffer mode, if there is no data in the IN FIFO, the IN_PKT_RDY bit and the TX_NOT_EPT flag will be automatically cleared to “0” after completion of the transmission. If there is one packet data already in the IN FIFO, the IN_PKT_RDY bit will be set to “0” after completion of the transmission, but the TX_NOT_EPT flag will remain at “ 1 ” . The USB transmit default mode is the bulk transfer. To use any other transfer mode, the user needs to initialize the corresponding endpoints. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 124 of 202 APPLICATION 7643 Group 2.6 USB (1) Interrupt transfer Endpoints 1 to 2 can be used in interrupt transfer mode. During a regular interrupt transfer, an interrupt transaction is similar to the bulk transfer. Therefore, there is no special setting required. When IN-endpoint is used for a rate feedback interrupt transfer, INTPT bit of the IN_CSR register must be set to “1”. The following steps show how to configure the IN-endpoint for the rate feedback interrupt transfer. 1. Set a value which is larger than 1/2 of the USB endpoint-x FIFO size to the USB endpoint x IN max. package size register. 2. Set INTPT bit to “ 1 ” . 3. Flush the old data in the FIFO. 4. Store transmission data to the IN FIFO and set the IN_PKT_RDY bit to “ 1 ” . 5. Repeat steps 3 and 4. In a real application, the function-side always has transfer data when the function sends an endpoint in a rate feedback interrupt. Accordingly, the USB FCU never returns a NAK against the host IN token for the rate feedback interrupt. The USB FCU always transmits data in the FIFO in response to an IN token, regardless of IN_PKT_RDY. However, this premises that there is always an ACK response from Host PC after the 7643 Group has transmitted data to IN token. (2) Usage notes concerning data transmit Usage notes concerning IN FIFO Determine the number of data packets in the IN FIFO by the value of the IN_PKT_RDY bit and the TX_NOT_EPT flag. Erase the contents of the USB endpoint x IN FIFO by setting the FLUSH bit to “ 1 ” . This will also modify the state of the IN_PKT_RDY bit and the TX_NOT_EPT flag. If there are two packets in the FIFO, the older packet will be erased. Table 2.6.2 shows the states of the IN FIFO. Table 2.6.2 IN FIFO States IN_PKT_RDY TX_NOT_EMP 0 0 1 1 0 1 0 1 No data packet 1 data packet (max. packet size ≤ 1 /2 IN FIFO size) In valid if max. packet size > 1/2 size Invalid 1 data packet (max. packet size > 1/2 size) 2 data packets (max. packet size ≤ 1 /2 IN FIFO size) IN FIFO States Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 125 of 202 APPLICATION 7643 Group 2.6 USB 2.6.5 USB receive Endpoint 0 to endpoint 2 have OUT (transmit) FIFOs individually. Each endpoint ’ s FIFO is configured in following way: Endpoint 0: 16-byte Endpoint 1: 128-byte Endpoint 2: Mode 0: 32-byte Mode 1: 128-byte When endpoint 2 is used, the OUT FIFO size differs according to the mode. To select the mode, use the USB endpoint FIFO mode register (address 005F 16). USB receive data is read from the USB endpoint x (x = 0 to 2) OUT FIFO. When data is read from this register, the internal Write pointer is automatically decremented by 1. The contents of the internal Write pointer cannot be read out, and the contents of the FIFO are undefined at reset. When using endpoint 0 When a receive is completed, the OUT_PKT_RDY flag is set to “1” and the number of receive data is set in the USB endpoint x (x = 0 to 2) OUT write count register (address 005D 16). After data is read from the OUT FIFO, clear the OUT_PKT_RDY flag to “ 0 ” b y writing “ 1 ” t o the SERVICED_OUT_PKT_RDY bit. When using endpoint 0, set the DATA_END bit to “1” after the last data packet is read from the OUT FIFO. When the DATA_END bit is set to “ 1 ” , the USB FCU will go on to the next phase process and clear the bit to “ 0 ” . When using endpoints 1, 2 When a receive is completed, the OUT_PKT_RDY flag is set to “ 1 ” a nd the number of bytes of receive data is set in the USB endpoint x (x = 0 to 2) OUT write count register (address 005D 16). When max. packet size is greater than 1/2 (single-buffer) - When AUTO_CLR bit = “ 1 ” When data (the size equals received OUT packet) is read from the OUT FIFO, the OUT_PKT_RDY flag is automatically cleared to “ 0 ” . - When AUTO_CLR bit = “ 0 ” The user needs to clear the OUT_PKT_RDY flag through software. When max. packet size is less than or equal to 1/2 (double-buffer) - When AUTO_CLR bit = “ 1 ” When data (the size equals received OUT packet) is read from the OUT FIFO but there is no data in the OUT FIFO, the OUT_PKT_RDY flag automatically is set to “ 0 ” . If there is one packet of data in the OUT FIFO, OUT_PKT_RDY flag will be cleared to “ 0 ” b ut then set to “ 1 ” a fter 83ns (when f(X IN) = 24MHz, Vcc = 5 V). - When AUTO_CLR bit = “ 0 ” Clear the OUT_PKT_RDY flag to “0” after reading data from the OUT FIFO (it will not be cleared automatically). When there is no data in the OUT FIFO, the OUT_PKT_RDY flag will be set to “0”. If there is one packet of data in the OUT FIFO, OUT_PKT_RDY flag is cleared to “0” once, then set to “ 1 ” a fter 83ns (when f(X IN) = 24MHz, Vcc = 5 V). (1) Usage notes concerning data receive q O UT_PKT_RDY flag Read one packet data from the OUT FIFO before clearing the OUT_PKT_RDY flag. If the OUT_PKT_RDY flag is cleared while one packet data is being read, the internal Read pointer cannot operate normally. q O UT FIFO For endpoints 1 or 2, when there are two packets of data in the OUT FIFO, after reading out the max OUT packet size of data, one packet of data will remain in the OUT FIFO. In this case, even if the OUT_PKT_RDY flag is set to “0”, it will return to “1” after 83ns (Vcc = 5V, f(XIN) = 24MHz). Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 126 of 202 APPLICATION 7643 Group 2.6 USB 2.6.6 USB interrupts (1) USB function interrupt The USB function interrupts is used for data flow control as well as USB power management. In order to use a USB function interrupt, set the Interrupt disable flag (I) to “ 0 ” a nd USB function interrupt enable bit of interrupt control register A (address 0005 16, bit 0) to “1”. In addition, set all bits corresponding to USB interrupt enable register 1 (address 0054 16) and USB interrupt enable register 2 (address 0055 16). Endpoint x IN interrupt, endpoint x OUT interrupt An interrupt request occurs when the following flag is set to “ 1 ” . USB endpoint x IN/OUT interrupt status flag of USB interrupt status register 1 or 2 (addresses 0052 16, 0053 16) Endpoints 1 and 2 have two interrupt status bits (IN and OUT) each and endpoint 0 has one interrupt status bit. Each interrupt status flag is set to “ 1 ” u nder any of the following conditions. - USB endpoint 0 interrupt status flag (INTST0) (when using endpoint 0) Endpoint 0: one packet successfully received, or Endpoint 0: one packet successfully transmitted, or DATA_END bit is “ 0 ” , or FORCE_STALL flag is “ 1 ” , or SETUP_END flag is “ 1 ” . - USB endpoint x (x = 1, 2) IN interrupt status flag (INTST2, 4) (when using endpoints 1, 2): Endpoint x (x = 1, 2): one packet data successfully transmitted - USB endpoint x (x = 1, 2) OUT interrupt status flag (INTST3, 5) (when using endpoints 1, 2): Endpoint x (x = 1, 2): one packet data successfully received, or FORCE_STALL flag is “ 1 ” . q R eset interrupt An interrupt request occurs when the USB reset interrupt status flag of USB interrupt status register 2 (005316) is “ 1 ” . The USB reset interrupt status flag is set to “ 1 ” w hen the USB FCU detects SE0 for a period of 2.5 ms on the D+/D- line by the USB FCU. At USB reset, all USB internal registers (addresses 0050 16 to 005F16) bits, excluding this bit, are initialized. Initialize each endpoint when new data transfer is received from the host CPU. q R esume signal interrupt An interrupt request occurs when the USB resume signal interrupt status flag of the USB interrupt status register 2 (address 0053 16) is “ 1 ” . The USB resume signal interrupt status flag is set to “1” if a non-idle signal is detected on the D+/D- line when the USB FCU is in the suspend mode. Also, the USB resume signal interrupt status flag is set to “1” even when the MCU returns from the suspend mode by a remote wakeup (INT interrupt, etc.) and the USB remote wake-up bit is set to “ 1 ” . q S uspend signal interrupt An interrupt request occurs when the USB suspend signal interrupt status flag of the USB interrupt status register 2 (address 0053 16) is “ 1 ” . This flag is set to “ 1 ” i f no activity is detected on the D+/D- line for a period of 3ms. The MCU returns from the suspend state with a USB resume interrupt or remote wake-up. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 127 of 202 APPLICATION 7643 Group 2.6 USB 2.6.7 Application example The following are several 7643 Group application examples showing the control procedure for performing USB controls. (1) Application example 1: Initialization of USB function control unit Outline: I nitialization the USB function control unit (USB FCU) is performed. Specification: - To generate the 48MHz required for fUSB, the frequency synthesizer is used. - USB FCU is enabled. - Each endpoint is initialized. Endpoint 0: Control transfer Endpoint 1: Bulk transfer Endpoint 2: Bulk transfer This is an example when the MCU is operating at Vcc = 5V. The following settings are required when using Vcc = 3V. q Set the USB line driver supply enable bit (USB control register, bit 4) to “0” to disable the DCDC converter. q S et φ t o 6MHz or less. When f(X IN) = 24MHz, clear bit 7 of the clock control register (X IN d ivider select bit) to “ 0 ” . Figure 2.6.23 shows the division settings of the frequency synthesizer, Figures 2.6.24 to 2.6.26 show related register settings, and Figures 2.6.27 to 2.6.29 show control procedure examples. FSM2 f(XIN) 24MHz 1/1 (FF16) fPIN FSM1 1/2 (0016) fUSB 48MHz fVCO FSD Invalid (25516) fSYN FSM1 : Frequency synthesizer multiply register 1 FSM2 : Frequency synthesizer multiply register 2 FSD : Frequency synthesizer divide register Fig. 2.6.23 Frequency synthesizer connection and setting of division ratios Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 128 of 202 APPLICATION 7643 Group 2.6 USB Clock control register (Address : 1F16) b7 b0 CCR 10100000 XCOUT oscillation drive disabled. XOUT oscillation drive enabled. System clock : f(XIN) Frequency synthesizer multiply register 1 (Address : 6D16) b7 b0 FSM1 0016 Frequency synthesizer multiply register 2 (Address : 6E16) b7 b0 48 MHz clock is generated FSM2 FF16 Frequency synthesizer divide register (Address : 6F16) b7 b0 FSD FF16 Frequency synthesizer control register (Address : 6C16) b7 b0 FSC 01100001 Frequency synthesizer : enabled Frequency synthesizer input : f(XIN) LPF current control : High current (select intermediate current “10” after lock) Frequency synthesizer lock status bit USB control register (Address : 1316) b7 b0 USBC 00010000 In default state after power-on/reset USB line driver current control : High USB line driver : enabled (Note) USB clock disabled: USB clock turns to be enabled after setting frequency synthesizer. USB function control unit disabled: USB clock turns to be enabled after initializing USB FCU. Note: When using the MCU in Vcc = 3 V, clear bit 4 of USBC to “0” and disable the built-in DC-DC converter. Fig. 2.6.24 Registers setting (1) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 129 of 202 APPLICATION 7643 Group 2.6 USB USB endpoint index register (Address : 5816) b7 b0 USBINDEX 0 0 0 0 0 0 0 0 Endpoint index: Endpoint 0 USB endpoint x (x=0 to 2) IN max. packet size register (Address : 5B16) b7 b0 IN_MAXP (Note 1) Set max. IN packet size MAXP=n✕8 when using endpoint 1 MAXP=n when using endpoint 0, 2 (n: setting value) USB endpoint x (x=1 to 2) OUT max. packet size register (Address : 5C16) b7 b0 OUT_MAXP (Note 1) Set max. OUT packet size MAXP=n✕8 when using endpoint 1 MAXP=n when using endpoint 0, 2 (n: setting value) USB endpoint x (x=1 to 2) IN control register (Address : 5916) b7 b0 IN_CSR (Note 1) IN_PKT_RDY bit SEND_STALL bit TOGGLE_INIT bit INTPT bit: “10” at interrupt (ratefeedback) transfer TX_NOT_EPT flag FLUSH bit AUTO_SET bit USB endpoint x (x=1 to 2) OUT control register (Address : 5A16) b7 b0 OUT_CSR (Note 1) OUT_PKT_RDY flag SEND_STALL bit TOGGLE_INIT bit FORE_STALL flag FLUSH bit AUTO_CLR bit Note 1: Set the corresponding endpoint to index register before setting these registers. Fig. 2.6.25 Registers setting (2) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 130 of 202 APPLICATION 7643 Group 2.6 USB USB endpoint FIFO mode register (Address : 5F16) b7 b0 USBFIFOMR 0000 000 FIFO size selection bits (For endpoint 1) b3 b2 b1 b0 ✕ 0 0 0 : IN 128byte OUT 128byte (For endpoint 2) 0 ✕ ✕ ✕ : IN 32byte OUT 32byte 1 ✕ ✕ ✕ : IN 128byte OUT128byte Reserved bits (“0” at write) Interrupt control register A (Address : 0516) b7 b0 ICONA 00000001 USB function interrupt : enabled USB interrupt enable register 1 (Address : 5416) b7 b0 USBIE1 00111101 Endpoint 0 interrupt: enabled Endpoint 1 IN interrupt: enabled Endpoint 1 OUT interrupt: enabled Endpoint 2 IN interrupt: enabled Endpoint 2 OUT interrupt: enabled USB interrupt enable register 2 (Address : 5516) b7 b0 USBIE2 10100000 USB reset interrupt: enabled USB suspend/resume interrupt: enabled Fig. 2.6.26 Registers setting (3) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 131 of 202 APPLICATION 7643 Group 2.6 USB RESET Initialization SEI q x: This bit is not used here. Set it to “0” or “1” arbitrarily. • All interrupts: disabled • System clock : f(XIN) CCR (Address : 1F16) A016 USB clock (fUSB) generating Initial setting of USB function control unit Initial setting of endpoint CLI • After set the using interrupt to be enabled, clear the interrupt disable flag to “0”. Fig. 2.6.27 Control procedure (1) (USB block initial setting) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 132 of 202 APPLICATION 7643 Group 2.6 USB USB clock generating • USB function control unit initializing FSM1 FSM2 FSD FSC (Address : 6D16) (Address : 6E16) (Address : 6F16) (Address : 6C16) 0016 FF16 FF16 6116 • Setting of division ratio of 48 MHz clock • Frequency synthesizer: enabled • fUSB=fVCO • In order to stabilize the frequency synthesizer, after the synthesizer is enabled, the 2 ms wait is required. Wait FSC (Address : 6C16),bit7? 1 • Check of lock state 0 0.1ms wait FSC (Address : 6C16) 4116 • USB line driver: enabled • USB line driver current : High Note 1: Set these only when using the MCU in Vcc = 5 V. • Wait as shown below is required; 2 to 5 ms: Time until 3.3 V is supplied to Ext.Cap pin + 1 ms USBC (Address : 1316) 1016 (Note 1) Wait USBC (Address : 1316),bit5 1 • USB clock: enabled Wait • Wait for 4 cycles or more of φ is required. USBC (Address : 1316),bit7 1 • USB function control unit: enabled RTS Fig. 2.6.28 Control procedure (2) (USB block generating) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 133 of 202 APPLICATION 7643 Group 2.6 USB Endpoint initial setting USBINDEX (Address : 5816) IN_MAXP (Address : 5B16) IN_CSR (Address : 5916) 0016 0816 C016 • Endpoint 0 initial setting Max. packet size: 8 bytes Control transfer mode USBINDEX IN_MAXP OUT_MAXP IN_CSR OUT_CSR USBFIFOMR (Address : 5816) (Address : 5B16) (Address : 5C16) (Address : 5916) (Address : 5A16) (Address : 5F16) 0116 0116 0116 4816 4816 0016 • Endpoint 1 initial setting Max. IN packet size: 8 bytes (1*8) Max. OUT packet size: 8 bytes (1*8) Bulk transfer mode USBINDEX IN_MAXP OUT_MAXP IN_CSR OUT_CSR USBFIFOMR (Address : 5816) (Address : 5B16) (Address : 5C16) (Address : 5916) (Address : 5A16) (Address : 5F16) 0216 0816 0816 4816 4816 0016 • Endpoint 2 initial setting Max. IN packet size: 8 bytes Max. OUT packet size: 8 bytes Bulk transfer mode Fig. 2.6.29 Control procedure (3) (endpoint initial setting) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 134 of 202 APPLICATION 7643 Group 2.6 USB (2) Application example 2: USB transmit Outline: D ata is transmitted in a USB IN transmit. Specification: - 8 bytes of data (data 0 to 7) is transmitted in the endpoint 1 IN interrupt routine. - AUTO_SET bit (address 0059 16, bit 7) = “ 0 ” ( disabled) - USB endpoint 1 IN max. packet size : 8 bytes Figure 2.6.30 shows the related register settings, Figure 2.6.31 shows a control procedure example. USB endpoint index register (Address : 5816) b7 b0 USBINDEX 0 0 0 0 0 0 0 1 Endpoint index: Endpoint 1 USB endpoint x IN control register (Address : 5916) b7 b0 IN_CSR 0 IN_PKT_RDY bit : set this bit to “1” after data is set to FIFO. AUTO_SET bit : disabled USB endpoint 1 FIFO (Address : 6116) b7 b0 USBFIFO1 Transmit data set Fig. 2.6.30 Registers setting (1) (USB endpoint 1 transmit) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 135 of 202 APPLICATION 7643 Group 2.6 USB USB endpoint 1 IN interrupt routine CLT (Note 1) CLD (Note 2) Push registers to stack Notes 1: This is executed when index X mode flag is used. 2: This is executed when decimal mode flag is used. • Push registers used in the interrupt routine USBINDEX (Address : 5816) 0116 • Endpoint 1 1 IN_CSR (Address : 5916),bit0? • Check of IN_PKT_RDY bit 0 (X) register 0016 • Setting of “0” to index register X USBFIFO1 (Address : 6116) (X)th data • Setting of (X)th data to FIFO. (X)+1 N (X) = 8? Y IN_PKT_RDY bit set Pop registers RTS Fig. 2.6.31 Control procedure (USB endpoint 1 IN interrupt routine) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 136 of 202 APPLICATION 7643 Group 2.6 USB (3) Application example 3: USB receive Outline: D ata is received in a USB OUT receive Specification: - Data is received in the endpoint 1 OUT interrupt routine. - AUTO_CLR bit (address 005A 16, bit 7) = “ 0 ” ( disabled). Figure 2.6.32 shows the related register settings, Figure 2.6.33 shows a control procedure example. USB endpoint index register (Address : 5816) b7 b0 USBINDEX 00000001 Endpoint index: Endpoint 1 USB endpoint x OUT control register (Address : 5A16) b7 b0 OUT_CSR 0 OUT_PKT_RDY flag: This bit is set to “1” when data is received. AUTO_CLR bit: disabled USB endpoint 1 OUT write count register (Address : 5D16) b7 b0 WRT_CNT Count value Fig. 2.6.32 Registers setting (USB endpoint 1 OUT receive) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 137 of 202 APPLICATION 7643 Group 2.6 USB USB endpoint 1 OUT interrupt routine CLT (Note 1) CLD (Note 2) Push registers to stack 0116 Notes 1: This is executed when index X mode flag is used. 2: This is executed when decimal mode flag is used. • Push registers used in the interrupt routine USBINDEX (Address : 5816) • Endpoint 1 0 OUT_CSR (Address : 5A16),bit0? 1 WRT_CNT (Address : 5D16) (RAM_CNT) • Push number of receive data to RAM_CNT (1 byte) • RAM_CNT: User defined RAM • Check of OUT_PKT_RDY flag. (RAM_DATA) USBFIFO1 (Address : 6116) • Reading data from number of receive data (RAM_CNT) FIFO • RAM_DATA: User defined RAM Definition of RAM_DATA according to the required number of bytes. (RAM_CNT) – 1 N (RAM_CNT)=“0”? Y OUT_PKT_RDY flag cleared Pop registers RTS Fig. 2.6.33 Control procedure (USB endpoint 1 OUT interrupt routine) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 138 of 202 APPLICATION 7643 Group 2.6 USB (4) Application example 4: Standard device • r equest (SET_ADDRESS) receive Outline: M 37643 performs enumeration process after USB cable connection. The USB endpoint 0 interrupt occurs when data is received successfully from the host CPU in an endpoint 0 control transfer. Whether the data was received in the setup stage or the data stage is not determined by hardware. The user needs to determine the received data by software and execute the process in an interrupt routine accordingly. For details on the data configuration of the standard device request, refer to the FullSpeed USB 2.0 specification. The process at a SET_ADDRESS receive is shown as a control example. The SET_ADDRESS request for the address setting is received from the host CPU, and it is set in the USB address register (address 0050 16). The USB FCU uses this address for all subsequent device accesses. A standard device request comprises 8 bytes. Figure 2.6.34 shows the structure of the SET_ADDRESS request, Figure 2.6.35 shows the related register settings, and Figure 2.6.36 shows a control procedure example. 0 byte bmRequestType 00000000B bRequest SET_ADDRESS (Code: 0516) wValue Device • address Loworder Highorder 0 windex 7th byte wlength 0 Fig. 2.6.34 Structure of SET_ADDRESS request USB endpoint index register (Address : 5816) b7 b0 USBINDEX 00 Endpoint index: Endpoint 0 USB endpoint 0 IN control register (Address : 5916) b7 b0 IN_CSR OUT_PKT_RDY flag SERVICED_SETUP_END bit USB endpoint 0 FIFO (Address : 6016) b7 b0 USBFIFO0 Endpoint 0 IN/OUT FIFO register USB address register (Address : 5016) b7 b0 USBA 0 This register maintains the 7-bit USB function control unit address Fig. 2.6.35 Register setting (processing when SET_ADDRESS is received) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 139 of 202 APPLICATION 7643 Group 2.6 USB Device • address receive routine (Set endpoint0 in the interrupt routine.) USBINDEX (Address 5816),bit0 0 • Endpoint 0 used No receive data in FIFO0 0 IN_CSR (Address 5916),bit0 ? 1 Data receive in FIFO0 X 0 • USR_RAM: User defined RAM 8 bytes required. • X : Index register X USR_RAM,X USBFIFO0 (Address 6016) X X+1 N X = 8? • 8th byte is stored? Y (1st byte of USR_RAM)? Branch to processing routine of each standard request =“0516” (SET_ADDRESS request received) N: new address (2nd byte of USR_RAM) = 0 ? Y: non-zero address USBA (Address 5016) (2nd byte of USR_RAM) IN_CSR (Address 5916),bit6 1 • OUT_PKT_RDY flag cleared IN_CSR (Address 5916),bit6 1 IN_CSR (Address 5916),bit3 1 • Set DATA_END bit to “1” IN_CSR (Address 5916),bit3 1 Wait the end of status phase Wait the end of status phase USBA (Address 5016) • Set (low-order) and ignore (high-order) (2nd byte of USR_RAM) RTS Fig. 2.6.36 Control procedure Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 140 of 202 APPLICATION 7643 Group 2.6 USB (5) Application example 5: USB function interrupt routine Outline: The following interrupts are assigned to the same vector. - USB endpoint 0 interrupt - USB endpoint x (x=1, 2) IN interrupt - USB endpoint x (x=1, 2) OUT interrupt - USB reset interrupt - USB suspend interrupt - USB resume interrupt Make all of the following settings in order to enable the interrupts. - Set USB function interrupt enable bit of interrupt control register A to “ 1 ” . - Set the bits corresponding to USB interrupt enable registers 1 and 2 to “ 1 ” . - Set the interrupt disable flag (I) to “ 0 ” . Each interrupt is determined according to the contents of USB interrupt status registers 1 and 2 in the USB function interrupt routine. When “ 1 ” , the corresponding process routine is executed. The USB reset interrupt does not have a specified enable bit and is always in the enabled state. Figure 2.6.37 shows the related register settings and Figure 2.6.38 shows a control procedure example. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 141 of 202 APPLICATION 7643 Group 2.6 USB Interrupt control register A (Address : 0516) b7 b0 ICONA 01 USB function interrupt : enabled USB interrupt enable register 1 (Address : 5416) b7 b0 USBIE1 0 Endpoint 0 interrupt: enabled Endpoint 1 IN interrupt: enabled Endpoint 1 OUT interrupt: enabled Endpoint 2 IN interrupt: enabled Endpoint 2 OUT interrupt: enabled USB interrupt enable register 2 (Address : 5516) b7 b0 USBIE2 01 00 USB suspend/resume interrupt: enabled USB interrupt status register 1 (Address : 5216) b7 b0 USBIS1 00 0 Endpoint 0 interrupt status flag Endpoint 1 IN interrupt status flag Endpoint 1 OUT interrupt status flag Endpoint 2 IN interrupt status flag Endpoint 2 OUT interrupt status flag USB interrupt status register 2 (Address : 5316) b7 b0 USBIS2 00000 USB reset interrupt status flag USB resume interrupt status flag USB suspend interrupt status flag Fig. 2.6.37 Register setting (USB function interrupt routine) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 142 of 202 APPLICATION 7643 Group 2.6 USB USB function interrupt routine • In the initial setting routine, enable each interrupt by ICONA (address 000516), USBIE1 (address 005416) and USBIE2 (address 005516). Push registers to stack Read and push in the following order; USBIS1 → RAM1, USBIS2 → RAM2 • USB interrupt status registers 1 and 2 cleared Set “1” again to the corresponding bits of USBIS1, USBIS2 to clear these bits. Note 1: When the USB block is enabled (USBC7=1) and USB clock is enabled (USBC5=1), writing to USB related registers (address 005016 to 006216) except USBC can be enabled. In the case of the resume interrupt, clear the USB resume signal interrupt status flag in the USB resume interrupt routine. Write in the following order; RAM1 → USBIS1, RAM2 → USBIS2 (Note 1) RAM1 (Address 5216) ? RAM2 (Address 5316) ? RAM1,bit0=1 or RAM1,bit2=1 or RAM1,bit4=1 RAM1,bit1=1 or RAM1,bit3=1 RAM2,bit5=1 RAM2,bit6=1 RAM2,bit7=1 USB endpoint x IN interrupt routine USB endpoint x OUT interrupt routine USB reset interrupt routine USB resume interrupt routine USB suspend interrupt routine Pop registers RTI Fig. 2.6.38 Control procedure (USB function interrupt routine) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 143 of 202 APPLICATION 7643 Group 2.6 USB (6) Application example 6: USB suspend interrupt Outline: Execute the suspend mode process routine when the USB suspend signal interrupt status flag is “ 1 ” i n the USB function interrupt routine. Set the USB function interrupt enable bit and the USB suspend/resume interrupt enable bit to “ 1 ” ( enabled). Before executing the STP instruction, clear all bits of USB interrupt status registers 1 and 2. In addition, when an interrupt process is not used to transition to the suspend mode, be sure to set the USB function interrupt enable bit to “ 1 ” a nd clear the USB function interrupt request bit to “ 0 ” b efore executing the STP instruction. Figure 2.6.39 shows the related register settings and Figure 2.6.40 shows a control procedure example. USB interrupt status register 2 (Address : 5316) b7 b0 USBIS2 USB suspend signal interrupt status flag USB control register (Address : 1316) b7 b0 USBC 1 011 USB line driver current control : Low (Set USB line driver current to High when returning from suspend state) USB line driver : enabled (Note) USB clock disabled USB function control unit : enabled Frequency synthesizer control register (Address : 6C16) b7 b0 FSC 0 Frequency synthesizer : disabled (Set this to be enabled when returning from suspend state) Interrupt control register B (Address : 0616) b7 b0 ICONB 00 Timer 1 interrupt : enabled Timer 2 interrupt : enabled Interrupt request register B (Address : 0316) b7 b0 IREQB 00 Timer 1 interrupt request bit Timer 2 interrupt request bit Note: When using the MCU in Vcc = 3 V, clear bit 4 of USBC to “0” and disable the built-in DC-DC converter. Fig. 2.6.39 Register setting (USB suspend interrupt) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 144 of 202 APPLICATION 7643 Group 2.6 USB USB suspend interrupt routine USBC,bit5 (Address 1316) 0 • USB clock enable bit : 48 MHz clock supply: stop FSC,bit0 (Address 6C16) 0 • Frequency synthesizer disabled USBC,bit3 (Address 1316) 1 • USB line driver current: Low Total current consumption of peripheral function < 500 µA ICONB (Address 0616) 000000002 • Timer 1 and timer 2 interrupts disabled IREQB (Address 0316) 000000002 • Timer 1 and timer 2 interrupt request bits cleared • When other external interrupts are not disabled and system is returned from suspend by except the USB resume interrupt, set the USB remote wake-up bit to “1”. Other external interrupts disabled CLI STP instruction executed Fig. 2.6.40 Control procedure (USB suspend interrupt routine) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 145 of 202 APPLICATION 7643 Group 2.6 USB (7) Application example 7: USB resume interrupt Outline: P erform the resume process when the USB resume signal interrupt status flag is “ 1 ” i n the USB function interrupt routine. Set the USB function interrupt enable bit to “ 1 ” ( enabled). This is an example when the MCU is operating at Vcc = 5V. The following settings are required when using Vcc = 3V. q S et USB line driver supply select bit (USB control register, bit 4) to “ 0 ” t o disable the DC-DC converter. q S et φ t o 6MHz or less. When f(X IN) = 24MHz, set bit 7 of the clock control register (XIN d ivider select bit) to “ 0 ” . Figure 2.6.41 shows the related register settings and Figure 2.6.42 shows a control procedure example. Frequency synthesizer control register (Address : 6C16) b7 b0 FSC 1000001 Frequency synthesizer : enabled Frequency synthesizer input : f(XIN) LPF current control bit : (intermediate current) Frequency synthesizer lock status bit Clock control register (Address : 1F16) b7 b0 CCR 10100000 System clock : f(XIN) (Note 1) USB interrupt status register 2 (Address : 5316) b7 b0 USBIS2 USB resume signal interrupt status flag USB control register (Address : 1316) b7 b0 USBC 1 0100 0 USB line driver current control : High USB line driver : enabled (Note 2) USB clock disabled: USB clock turns to be enabled after setting frequency synthesizer. USB function control unit : enabled Notes 1: When using the MCU in Vcc=3.3 V, set φ to 6 MHz (when using the MCU in Vcc=3 V and f(XIN)=24 MHz, clear bit 7 of CCR to “0”.) 2: When using the MCU in Vcc = 3.3 V, clear bit 4 of USBC to “0” and disable the built-in DC-DC converter. Fig. 2.6.41 Register setting (USB resume interrupt) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 146 of 202 APPLICATION 7643 Group 2.6 USB USB resume interrupt routine USBC (Address 1316),bit3 0 • USB line driver current control: High CCR (Address 1F16) C016 • System clock : f(XIN) FSC (Address 6C16),bit0 1 • Frequency synthesizer: enabled Wait • After frequency synthesizer is enabled, wait of 2 ms or more is required to stabilize frequency syntesizer FSC (Address 6C16),bit7 1 • Lock state is checked 0 0.1ms wait USBC (Address 1316),bit5 1 • USB clock enabled RTS Fig. 2.6.42 Control procedure (USB resume interrupt routine) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 147 of 202 APPLICATION 7643 Group 2.6 USB 2.6.8 Connection with other functions The 7643 Group also has DMAC and UART connections for USB transfers, enabling high-volume data transfers. (1) Application example 1: Data packet transfer from USB FIFO to UART (without DMA) Outline: D ata is transmitted from USB FIFO to host CPU using UART. Specification: - USB endpoint 1 OUT bulk transfer is used. - USB endpoint 1 OUT interrupt is used. - USB endpoint 1 OUT packet size: 64 bytes - UART transmit is used. - UART transmit interrupt (when transmit shift operation is completed) is used. - Transfer bit rate: 9600bps (φ = 1 2MHz divided by 1248) - Data format: 1ST-8DATA-1SP - Parity bit is disabled - Re-transmit is executed if transfer error occurs (re-transmit in byte unit) - P41/INT0 pin is used to detect the re-transmit request (host CPU sets P4 1/INT0 pin to “ L ” w hen UART receive error occurs) - INT0 interrupt request flag (falling edge) to detect the re-transmit request is used. - P40 t o inform host CPU of USB packet transmit is used. - CTS function is used. After USB data is received from the host PC, the 7643 MCU stores the value of the USB endpoint 1 OUT write count register (number of received bytes) in Storage RAM 1 by the USB endpoint 1 OUT interrupt. Then, sets P4 0 t o “ L ” , the UART transmit interrupt to be enabled, and starts the UART transmit. As soon as the UART transmit is enabled, the first UART transmit interrupt occurs. Therefore, the 7643 MCU writes one byte of the received USB FIFO data to both Storage RAM2 and UART transfer buffer register 1, and returns from the interrupt. Next, the host CPU sets the CTS pin to “L” and reads the data in the UART transmit/receive shift register. At this time, since another UART transfer interrupt occurs, the same process is repeated until the USB FIFO is empty. On the other hand, when the host CPU requests a re-transmit by a UART receive error etc., it is programmed to set the P41/INT0 pin to “L”. In the 7643 Group, the data in Re-transmit RAM 2 is written to the UART transmit/receive buffer register if the INT0 interrupt request flag is “1” in the UART transmit interrupt routine. By this action, the previous data is resent to the host CPU. As described above, when all data in the USB FIFO are transmitted to the host CPU, P40 is set to “ H ” , the UART transmit interrupt is disabled, and the OUT_PKT_RDY flag of USB endpoint 1 OUT is cleared. This makes USB endpoint 1 ready to receive the next USB data packet. Figure 2.6.43 shows the connection diagram, Figures 2.6.44 to 2.6.46 show related register settings, and Figures 2.6.47 and 2.6.48 show control procedure examples. Transmitting side P84/UTXD USB P86/CTS USB OUT Transfer P41/INT0 P40 7643 Group RTS General purpose port 1 General purpose port 2 Host CPU Receiving side URXD Host PC Fig. 2.6.43 Connection diagram Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 148 of 202 APPLICATION 7643 Group 2.6 USB UART mode register (Address : 3016) b7 UMOD b0 010 0000 UART clock : φ/1 Stop bit length : 1 stop bit Parity checking disabled Character length : 8 bits UART control register (Address : 3316) b7 UCON b0 0011 101 Transmit enabled Receive disabled Transmit initializing Interrupt when transmit shift operation is completed CTS function enabled RTS function disabled UART address mode disabled UART baud rate generator (Address : 3116) b7 b0 UBRG 4D16 Interrupt control register A (Address : 0516) b7 b0 ICONA 1 1 USB function interrupt : enabled UART transmit interrupt : enabled UART transmit/receive buffer register 1 (Address : 3416) b7 b0 UTRB1 Transmit data UART statis regoster (Address : 3216) b7 b0 USTS Transmit complete flag Transmit buffer empty flag Fig. 2.6.44 Register setting (1) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 149 of 202 APPLICATION 7643 Group 2.6 USB Port P4 direction register (Address : 1916) b7 P4D b0 01 P40: output P41: input Interrupt polarity select register (Address : 1116) b7 IPOL b0 0 INT0 interrupt edge : Falling edge Clock control register (Address : 1F16) b7 CCR b0 1 00000 φ = system clock/2, system clock = f(XIN) Frequency synthesizer multiply register 1 (Address : 6D16) b7 FSM1 b0 0016 Frequency synthesizer multiply register 2 (Address : 6E16) b7 b0 FSM2 FF16 Frequency synthesizer divide register (Address : 6F16) b7 b0 FSD 0016 Frequency synthesizer control register (Address : 6C16) b7 FSC b0 01 00000 1 Frequency synthesizer : enabled Frequency synthesizer input : f(XIN) Fig. 2.6.45 Register setting (2) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 150 of 202 APPLICATION 7643 Group 2.6 USB USB control register (Address : 1316) b7 USBC b0 1 11 00 0 USB line driver current control : High USB line driver : enabled USB clock : enabled USB function control unit : enabled USB endpoint FIFO mode register (Address : 5F16) b7 USBFIFOMR b0 00 Endpoint 1 FIFO size: OUT 128 bytes USB interrupt enable register 1 (Address : 5416) b7 USBIE1 b0 1 1 Endpoint 0 interrupt: enabled Endpoint 1 OUT interrupt: enabled USB endpoint index register (Address : 5816) b7 USBINDEX b0 01 Endpoint 1 USB endpoint 1 OUT max. packet size register (Address : 5C16) b7 OUT_MAXP b0 0816 8 ✕ 8=64 bytes USB endpoint x OUT control register (Address : 5A16) b7 OUT_CSR b0 1 OUT_PKT_RDY bit Fig. 2.6.46 Register setting (3) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 151 of 202 APPLICATION 7643 Group 2.6 USB RESET Initialization ..... (Interrupt disabled) CCR (Address : 1F16) FSM1 (Address : 6D16) FSM2 (Address : 6E16) FSD (Address : 6F16) FSC (Address : 6C16) USBC (Address : 1316) USBFIFOMR (Address : 5F16) USBIE1 (Address : 5416) USBINDEX (Address : 5816) OUT_MAXP (Address : 5C16) OUT_CSR (Address : 5A16) UBRG (Address : 3116) UMOD (Address : 3016) UCON (Address : 3316) P4 (Address : 1816) P4D (Address : 1916) IPOL (Address : 1116) ICONA (Address : 0516) IREQA (Address : 0216) ..... (interrupt enabled) 8016 0016 FF 1 6 0016 4116 1X1100X02 XXXXXX002 000010012 X00000012 0816 0XXXXXX12 4D16 010X00002 0011X0002 XXXXXXX12 XXXXXX012 XXXXXXX02 0XXXXXX12 0016 q x: This bit is not used here. Set it to “0” or “1” arbitrarily. Refer to the USB initiral setting. • USB initializing Endpoint 1 FIFO : OUT128 bytes Endpoint 0, Endpoint 1OUT interrupt enabled Max. packet size : 64 bytes ... • UART initializing φ as UART clock, 1 stop bit, Parity checking disabled, 8-bit character length CTS function enabled, RTS function disabled Tramsmit interrupt source : Transmit shift completed • Others P40 : output, P41 : input USB function interrupt : enabled UART transmit interrupt : disabled Interrupt occurs USB endpoint 1 OUT interrupt Push registers to stack USBIS1 (Address : 5216),bit3 1 USBINDEX (Address : 5816) X00000012 RAM1 WRT_CNT (Address : 5D16) UCON (Address : 3316),bit2 1 UCON (Address : 3316),bit0 1 1 ICONA (Address : 0516),bit7 0 IREQA (Address : 0216),bit2 Pop registers RTI * When USBINDEX is set, push its data to temporary buffer, and return the data to USBINDEX after interrupt is completed. • Start processing Number of USB receive bytes UART transmit initializing UART transmit enabled UART transmit interrupt enabled * Interrupt request flag is set as soon as UART transmit interrupt is enabled. •INT0 interrupt request bit set to “0” Fig. 2.6.47 Control procedure (1) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 152 of 202 APPLICATION 7643 Group 2.6 USB Interrupt occurs UART transmit interrupt Push registers to stack Wait the processing of Host CPU error detection is completed. Y Re-transmit requested ? N RAM1 > 0? Y (Address : 1816) P4 RAM2 USBFIFO1 UTRB1 (Address : 3416) RAM1 – 1 RAM1 XXXXXXX02 (Address : 6116) RAM2 • Writing data P40 is “L” Writing to UART • Re-transmit When re-transmit request occurs, the previous value is re-transmitted. N UTRB1 (Address 3416) RAM2 Host CPU detects error and waits until host CPU operates INT0. * Wait time here depends on processing by Host CPU. Check of INT0 interrupt request flag. RAM1=“0”? Y P4 (Address : 1816) XXXXXXX12 N P40 is “H” ICONA (Address : 0516), bit7 USBINDEX (Address : 5816) OUT_CSR (Address : 5A16) 0 X00000012 0XXXXXX12 • End processing UART transmit interrupt disabled USB receive (OUT) enabled Re-transmit request cleared • INT0 interrupt request flag is cleared. Pop registers RTI Fig. 2.6.48 Control procedure (2) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 153 of 202 APPLICATION 7643 Group 2.6 USB (2) Application example 2: Data packet transfer from UART to USB FIFO (without DMA) Outline: T he data received from host CPU through UART to the USB FIFO is written, and then it is transmitted to host PC. Specification: - Use USB endpoint 1 IN bulk transfer is used. - USB endpoint 1 IN interrupt is used. - USB endpoint one packet size: 64 bytes - UART receive is used. - UART receive buffer full interrupt is used. - UART receive summing error interrupt is used. - Transfer bit rate: 9600bps ( φ = 12MHz divided by 1248) - Data format: 1ST-8DATA-1SP - Parity bit is disabled. - Re-transmit is executed if transfer error occurs (re-transmit in byte unit) - P40 pin to detect packet transmit from host CPU is used. (the host CPU keeps P40 at “ L ” d uring a packet transfer, at “ H ” a t all other times) - RTS function is used. When the USB FIFO data is transmitted to the host PC, in the 7643 Group, a USB endpoint 1 interrupt occurs. At this point, the 7643 MCU enables the UART receive (UART receive buffer full interrupt, UART receive summing error interrupt). After the UART function is received from the host PC, in the 7643 Group, a UART receive buffer full interrupt occurs; the UART transmit/receive buffer register is read and the received data is written to the USB FIFO. The RTS pin is set to “L”, indicating that the RTS pin is ready to receive the next data. If Port P4 0 i s “ H ” a t this point, that receive of one-packet data (64 bytes or more) has been completed is recognized, and sets the IN_PKT_RD flag USB endpoint 1 IN. This makes the data in the USB endpoint 1 FIFO ready for transmit. On the other hand, if a UART receive summing error interrupt, not the UART receive buffer interrupt, occurs, both the UART transmit/receive buffer register and the UART status register is read (this clears the error flag), and an “ L ” p ulse is generated to P4 1 ( as a result from this operation, the re-transmit the previous data from the host CPU is realized). Note that the data received when an error occurs will be erased. Figure 2.6.49 shows the connection diagram, Figures 2.6.50 to 2.6.53 show related register settings, and Figures 2.6.54 and 2.6.55 show control procedure examples. Transmitting side P85/URXD USB P87/RTS USB IN Transfer P41/INT0 P40 7643 Group Receiving side UTXD CTS General purpose port 1 General purpose port 2 Host CPU Host PC Fig. 2.6.49 Connection diagram Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 154 of 202 APPLICATION 7643 Group 2.6 USB UART mode register (Address : 3016) b7 UMOD b0 010 0000 UART clock : φ/1 Stop bit length : 1 stop bit Parity checking disabled Character length : 8 bits UART control register (Address : 3316) b7 UCON b0 010 1 10 Transmit disabled Receive enabled Receive initializing CTS function disabled RTS function enabled UART address mode disabled UART RTS control register (Address : 3616) b7 b0 URTSC 0000 RTS assertion delay count select bits UART baud rate generator (Address : 3116) b7 b0 UBRG 4D16 Interrupt control register A (Address : 0516) b7 b0 ICONA 1 1 USB function interrupt : enabled UART receive buffer full interrupt : enabled Interrupt control register B (Address : 0616) b7 b0 ICONB 1 UART summing error interrupt : enabled Fig. 2.6.50 Register setting (1) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 155 of 202 APPLICATION 7643 Group 2.6 USB UART transmit/receive buffer register 1 (Address : 3416) b7 b0 UTRB1 Receive data UART statis regoster (Address : 3216) b7 b0 USTS Receive buffer full flag Parity error flag Framing error flag Overrun error flag Summing error flag Fig. 2.6.51 Register setting (2) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 156 of 202 APPLICATION 7643 Group 2.6 USB Port P4 direction register (Address : 1916) b7 P4D b0 10 P40: input P41: output Clock control register (Address : 1F16) b7 CCR b0 0 00000 φ = system clock/2, system clock = f(XIN) Frequency synthesizer multiply register 1 (Address : 6D16) b7 FSM1 b0 0016 Frequency synthesizer multiply register 2 (Address : 6E16) b7 b0 FSM2 FF16 Frequency synthesizer divide register (Address : 6F16) b7 FSD b0 0016 Frequency synthesizer control register (Address : 6C16) b7 FSC b0 01 00000 1 Frequency synthesizer : enabled Frequency synthesizer input : f(XIN) USB control register (Address : 1316) b7 USBC b0 1 1100 0 USB line driver current control : High USB line driver : enabled USB clock : enabled USB function control unit : enabled Fig. 2.6.52 Register setting (3) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 157 of 202 APPLICATION 7643 Group 2.6 USB USB endpoint FIFO mode register (Address : 5F16) b7 USBFIFOMR b0 00 Endpoint 1 FIFO size: OUT 128 bytes USB interrupt enable register 1 (Address : 5416) b7 USBIE1 b0 1 1 Endpoint 0 interrupt: enabled Endpoint 1 IN interrupt: enabled USB endpoint index register (Address : 5816) b7 USBINDEX b0 01 Endpoint 1 USB endpoint 1 IN max. packet size register (Address : 5B16) b7 IN_MAXP b0 0816 8 ✕ 8=64 bytes USB endpoint x IN control register (Address : 5916) b7 IN_CSR b0 0 IN_PKT_RDY bit Fig. 2.6.53 Register setting (4) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 158 of 202 APPLICATION 7643 Group 2.6 USB RESET q x: This bit is not used here. Set it to “0” or “1” arbitrary. Initialization ..... (Interrupt disabled) CCR (Address 1F16) FSM1 (Address 6D16) FSM2 (Address 6E16) FSD (Address 6F16) FSC (Address 6C16) USBC (Address 1316) USBFIFOMR (Address 5F16) USBIE1 (Address 5416) USBINDEX (Address 5816) IN_MAXP (Address 5B16) IN_CSR (Address 5916) UBRG (Address 3116) UMOD (Address 3016) UCON (Address 3316) P4 (Address 1816) P4D (Address 1916) ICONA (Address 0516) ICONB (Address 0616) IREQA (Address 0216) IREQB (Address 0316) ..... (Interrupt enabled) 8016 0016 FF16 0016 4116 1X1100X02 XXXXXX002 000001012 X00000012 0816 0XXXXXX02 4D16 010X00002 0100X0102 XXXXXX1X2 XXXXXX102 X1XXXXX12 XXXXXXX12 0016 0016 * Refer to the USB initial setting. • USB initial setting Endpoint1FIFO: IN128 bytes Endpoint0, Endpoint1IN interrupts enabled Max. packet size: 64 bytes ... • UART initial setting CTS function disabled, RTS function enabled, φ as UART clock, 1 stop bit, Parity checking disabled, 8-bit character length receive enabled • Others P40: input, P41: output USB function interrupt: enabled UART receive buffer full interrupt: enabled UART summing error interrupt: enabled Interrupt occurs USB Endpoint 1 IN interrupt Push registers to stack USBIS1 (Address 5216),bit2 UCON (Address 3316),bit1 1 1 * In the initial setting, set the first UART receive to be enabled. • Start processing UART receive enabled Pop registers RTI Fig. 2.6.54 Control procedure (1) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 159 of 202 APPLICATION 7643 Group 2.6 USB Interrupt occurs UART receive buffer full interrupt Push registers to stack USBFIFO1 (Address 6116) UTRB1(Address 3416) • The contents of USB receive buffer is written to USB endpoint 1 FIFO. N P40=“H”? Y USBINDEX (Address 5816) IN_CSR (Address 5916) UCON (Address 3316), bit1 X00000012 0XXXXXX12 0 • Receive operation completed USB transmit processing When one-packet data is received, USB transmit is enabled. Receive is disabled. Pop registers RTI Interrupt occurs UART summing error interrupt Push registers to stack A register A register USTS (Address 3216) UTRB1 (Address 3416) • Read UART status register and clear error flag. • Read out USB receive buffer to make it be empty. P41 NOP P41 0 1 • “L” pulse is generated on P41, and re-transmit is requested to host CPU. Pop registers RTI Fig. 2.6.55 Control procedure (2) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 160 of 202 7643 Group Rev.2.00 Aug 28, 2006 REJ09B0133-0200 1MB DRAM Memory Controller DSP D/A Program ROM Sound source LSI 2.6.9 Application circuit example Fig. 2.6.56 Electronic instrument application example Audio output Dedicated I/O ASIC 7643 Group BUS I/F CSC DRAMC M37643 I/F D+ DDMAC UART USB DTimer Port INTC UART MIDI USB Transfer I/F USB D+ USB Port Ext. Cap D+ pull-up voltage supply The resistor value depends on the layout of printed circuit board. page 161 of 202 SRAM Flash Memory M32R/ D 32R Core M 4KB Cache Memory Keyboard controller LCD controller 8-bit single-chip LCD panel controller A/D APPLICATION 2.6 USB APPLICATION 7643 Group 2.6 USB D+ Dencrypt /decrypt (S/W) Endpoint 1 OUT Endpoint 1 IN 3-DES Endpoint 0 USB Port Fig. 2.6.57 Encryption sytem application example Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 162 of 202 IC Card or Biometrics System 7643 Group UART APPLICATION 7643 Group 2.6 USB 2.6.10 Notes on USB function (1) USB receive q F or endpoints 1 or 2, when there are two packets of data in the OUT FIFO, after reading out the max OUT packet size of data, one packet of data will remain in the OUT FIFO. In this case, even if the OUT_PKT_RDY flag is set to “0”, it will return to “1” after 83ns (Vcc = 5V, f(X IN) = 24MHz). q R ead one packet data from the OUT FIFO before clearing the OUT_PKT_RDY flag. If the OUT_PKT_RDY flag is cleared while one packet data is being read, the internal Read pointer cannot operate normally. (2) USB transmit q Determine the number of data packets in the IN FIFO by the value of the IN_PKT_RDY bit and the TX_NOT_EPT flag. For more details, refer to Table 2.6.2 in [Section 2.6.4 USB transmit]. q For endpoints 1 or 2, to transmit a NULL packet, set the IN_PKT_RDY bit to “1” without writing data to the FIFO. (3) External circuits q F igure 2.6.58 shows a peripheral circuit example of the external capacitor (Ext. Cap) pin. Connect a low-frequency 2.2 µ F T antal capacitor and a 0.1 µF ceramic capacitor (X7R type recommended) in parallel between the Ext. Cap pin and the Vss pin. In addition, connect a 1.5k Ω ( ±5%) resistor between the Ext. Cap pin and the D+ pin. q The Full-Speed USB2.0 specification requires a driver-impedance of 28 to 44 Ω (refer to Clause 7.1.1.1 Full-Speed (12Mb/s) Driver Characteristics). In order to meet USB specification impedance requirements, connect a resistor (27 to 33 Ω recommended) in series to the USB D+ and D- pins. In addition, in order to reduce the ringing and control the falling/rising timing of USB D+/D- and a crossover point, connect a capacitor (69pF recommended) between the USB D+/D- pins and the Vss pin if necessary. The values and structure of those peripheral elements depend on the impedance characteristics and the layout of the printed circuit board. Accordingly, evaluate your system and observe waveforms before actual use and decide use of elements and the values of resistors and capacitors. q M ake sure the wiring of the USB connector or USB cable is as short as possible. q M ake sure the USB D+/D- lines do not cross any other wires. Keep a large GND area to protect the USB lines. Also, make sure you use a USB specification compliant connecter for the connection. q A ll passive components must be located as close as possible to the LPF pin. For recommended values, see Figure 2.6.59. q A n insulation connector (Ferrite Beads) must be connected between AVss and Vss pins and between AVcc and Vcc pins. q C onnect 0.1 µ F and 4.7 µ F capacitors in parellel between the Vss and Vcc pins and between the AVss and AVcc pins. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 163 of 202 APPLICATION 7643 Group 2.6 USB XIN USBC5 Frequency synthesizer enable lock enable DC-DC converter enable current mode FSE LS USBC4 USBC3 Ext.Cap Note 2 USB Clock USB FCU (48MHz) enable USBC7 USB transceiver enable USBC7 D+ Peripheral circuit example is shown below. D- ➀ Vcc=5V(built-in DC-DC converter used) 5V M37643 Vcc Ext.Cap ➁ Vcc=3V (DC-DC converter disabled) 3.3V M37643 Vcc Ext.Cap VCC 2.2µF 0.1µF 1.5kΩ 2.2µF 0.1µF D+ D+ DNote 1 DNote 1 Notes 1: The resistor value depends on the layout of printed circuit board. 2: When Vcc = 5 V, do not connect the external DC-DC converter to the Ext.Cap pin. Fig. 2.6.58 Peripheral circuit example Ferrite Beads LPF pin 1 kΩ Vcc AVcc 680pF C3 C1 C2 C4 0.1 µF AVSS pin Vss Decoupling Capacitors AVss Capacitor C1, C2 : 0.1µF C3, C4 : 4.7µF Fig. 2.6.59 LPF peripheral circuit Fig. 2.6.60 Connection of insulation connector Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 164 of 202 1.5kΩ APPLICATION 7643 Group 2.6 USB (4) USB Communication q I n applications requiring high-reliability, we recommend providing the system with protective measures such as USB function initialization by software or USB reset by the host to prevent USB communication from being terminated unexpectedly, for example due to external causes such as noise. (5) Registers and bits q When using endpoint 0, use USB endpoint 0 IN max. packet size register (IN_MAXP: address 005B 16) for data transfer to/from (IN packet size or OUT packet size). q W hen not using USB endpoint x (x = 0 to 2) IN max. packet size register (IN_MAXP: address 005B 16), USB endpoint x (x = 0 to 2) OUT max. packet size register (OUT_MAXP: address 005C 16), clear “ 0 ” t o this register. q M ake sure to write to/read from the USB interrupt status register 1 (USBIS1: address 005216) first and then USB interrupt status register 2 (USBIS2: address 0053 16). q W hen accessing the following registers, always confirm that the index (bits 0 to 2 of USB endpoint index register (USBINDEX: address 0058 16) is set properly. - USB endpoint x IN control register (IN_CSR: address 0059 16) - USB endpoint x OUT control register (OUT_CSR: address 005A 16) - USB endpoint x IN max. packet size register (IN_MAXP: address 005B 16) - USB endpoint x OUT max. packet size register (OUT_MAXP: address 005C 16) - USB endpoint x OUT write count register (WRT_CNT: address 005D 16) - USB endpoint FIFO mode register (USBFIFOMR: address 005F 16) q W hen the USB reset interrupt status flag is kept at “ 1 ” , all other flags in the USB internal registers (addresses 0050 16 t o 005F 16) will return to their reset status. However, the following registers are not affected by the USB reset: - USB control register (USBC: address 0013 16), - Frequency synthesizer control register (FSC: address 006C16 ), - Clock control register (CCR: address 001F 16), - USB endpoint-x FIFO register (USB FIFOx: addresses 0060 16 t o 006216). q When not using the USB function, set the USB line driver supply enable bit of the USB control register (USBC: address 0013 16) to “ 1 ” f or power supply to the internal circuits (at Vcc = 5V). q T he IN_PKT_RDY Bit can be set by software even when using the AUTO_SET function. q When the USB clock is disabled, do not write to any USB internal registers (addresses 0050 16 to 0062 16) other than registers USBC, CCR, and FSC. q I n the USB suspend state, USB enable bit is fixed to “ 1 ” ( USB clock enabled state). To write to a USB register other than registers USBC, CCR, and FSC (i.e. to addresses 0050 16 to 0062 16) after the MCU recovers from the USB suspend state, set the USB clock enable bit (USBC, bit 5) to “ 1 ” , and write to the register after a φ = 4 w ait cycle. q W hen using the MCU at Vcc = 3V, set the USB line driver supply selection bit (USBC, bit 4) to “ 0 ” ( line driver disabled). Note that the USB line driver divider select bit (USBC, bit 3) does not affect the USB operation. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 165 of 202 APPLICATION 7643 Group 2.6 USB q U se the transfer instructions such as L DA a nd S TA t o set the following registers: - USB interrupt status registers 1, 2 (USBIS1, USBIS2: addresses 0052 16, 0053 16) - USB endpoint 0 IN control register (IN_CSR: address 0059 16) - USB endpoint x IN control register (IN_CSR: address 005916) - USB endpoint x OUT control register (OUT_CSR: address 005A 16) Do not use the read-modify-write instructions such as the S EB o r the C LB i nstruction. When writing to bits shown by Table 2.6.3 using the transfer instruction such as L DA o r S TA, a value which never affects its bit state is required. Take the following sequence to change these bits contents: 1. Store the register contents onto a variable or a data register. 2. Change the target bit on the variable or the data register. Simultaneously mask the bit so that its bit state cannot be changed. (See to Table 2.6.3.) 3. Write the value from the variable or the data register to the register using the transfer instruction such as L DA o r S TA. q E rase the contents of the IN FIFO or OUT FIFO by setting the FLUSH bit to “ 1 ” . If there are two packets in the FIFO, the older packet will be erased. This will also modify the state of the IN_PKT_RDY bit and the TX_NOT_EPT flag. q T ransfer data may be erased if the FLUSH bit is set to “ 1 ” d uring a transfer. Receive: Set the FLUSH bit to “ 1 ” w hen the OUT_PKT_RDY flag is “ 1 ” . q To use the AUTO_SET function for an IN transfer when the AUTO_SET bit is set to 1, set the FIFO to single buffer mode. Table 2.6.3 Bits of which state might be changed owing to software write Register name USB endpoint 0 IN control register Bit name IN_PKT_RDY (b1) DATA_END (b3) FORCE_STALL (b4) USB endpoint x (x = 1, 2) IN control register IN_PKT_RDY (b0) USB endpoint x (x = 1, 2) OUT control register OUT_PKT_RDY (b0) FORCE_STALL (b4) Value not affecting state (Note ) “0” “0” “1” “0” “1” “1” Note: Writing this value will not change the bit state, because this value cannot be written to the bit by software. Some application notes are available on the Web site: http://www.renesas.com/en/usb Please refer to them for more explanation and application of USB function. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 166 of 202 APPLICATION 7643 Group 2.7 PLL 2.7 Frequency synthesizer This paragraph explains the registers setting method and the notes related to the frequency synthesizer. 2.7.1 Memory map Address 000016 006C16 006D16 006E16 006F16 CPU mode register A (CPMA) Frequency synthesizer control register (FSC) Frequency synthesizer multiply register 1 (FSM1) Frequency synthesizer multiply register 2 (FSM2) Frequency synthesizer divide register (FSD) Fig. 2.7.1 Memory map of registers related to frequency synthesizer Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 167 of 202 APPLICATION 7643 Group 2.7 PLL 2.7.2 Related registers CPU mode register A b7 b6 b5 b4 b3 b2 b1 b0 1 CPU mode register A (CPMA : address 0016) b Name b1b0 Functions At reset R W 0 0 1 1 0 Processor mode bits 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 1 0 : Microprocessor mode (Note 1) 1 1 : Not available 2 Stack page select bit 0 : Page 0 1 : Page 1 3 Nothing is arranged for this bit. Fix this bit to “1”. 4 Sub-clock (XCIN-XCOUT) stop bit 5 Main clock (XIN-XOUT) stop bit Internal system clock 6 select bit (Note 2) 7 External clock select bit 0 0 : Stopped 1 : Oscillating 0 : Oscillating 0 1 : Stopped 0 0 : External clock (XIN-XOUT or XCIN-XCOUT) 1 : fsyn 0 0 : XIN-XOUT 1 : XCIN-XCOUT Notes 1: This is not available in the flash memory version. 2: When (CPMA 7, 6) = (0, 0), the internal system clock can be selected between f(XIN) and f(XIN)/2 by CCR7. The internal clock φ is the internal system clock divided by 2. Fig. 2.7.2 Structure of CPU mode register A Frequency synthesizer control register b7 b6 b5 b4 b3 b2 b1 b0 0 00 Frequency synthesizer control register (FSC : address 6C16) b Name Functions At reset R W 0 0 0 0 0 1 1 0 0 Frequency synthesizer enable bit (FSE) 0 : Disabled 1 : Enabled 1 Nothing is arranged for these bits. 2 Fix these bits to “0”. 0 : f(XIN) 3 Frequency synthesizer 1 : f(XCIN) input bit (FIN) 4 Nothing is arranged for this bit. Fix this bit to “0”. 5 LPF current control bit (CHG1, CHG0) (Note) 6 7 Frequency synthesizer lock status bit b1b0 0 0 : Not available 0 1 : Low current 1 0 : Intermediate current (recommended) 1 1 : High current 0 : Unlocked 1 : Locked Note: Bits 6 and 5 are set to (bit 6, bit 5) = (1, 1) at reset. When using the frequency synthesizer, we recommend to set to (bit 6, bit 5) = (1, 0) after locking the frequency synthesizer. Fig. 2.7.3 Structure of Frequency synthesizer control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 168 of 202 APPLICATION 7643 Group 2.7 PLL Frequency synthesizer multiply register 1 b7 b6 b5 b4 b3 b2 b1 b0 Frequency synthesizer multiply register 1 (FSM1: address 6D16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qfVCO clock is generated by multiplying fPIN clock, which is generated by FSM2, by the contents of this register: 1 2 fVCO = fPIN • {2(n +1)}, n: value set to FSM1. 3 4 5 6 7 Fig. 2.7.4 Structure of Frequency synthesizer multiply register 1 Frequency synthesizer multiply register 2 b7 b6 b5 b4 b3 b2 b1 b0 Frequency synthesizer multiply register 2 (FSM2: address 6E16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qfPIN clock is generated by dividing fIN clock by the contents of this register. 1 Either f(XIN) or f(XCIN) as an input clock fIN for the frequency 2 synthesizer is selectable. 3 4 fPIN = fIN / {2(n +1)}, n: value set to FSM2 5 6 7 Fig. 2.7.5 Structure of Frequency synthesizer multiply register 2 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 169 of 202 APPLICATION 7643 Group 2.7 PLL Frequency synthesizer divide register b7 b6 b5 b4 b3 b2 b1 b0 Frequency synthesizer divide register (FSD: address 6F16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qfSYN clock is generated by dividing fVCO clock by the contents of this register: 1 2 fSYN = fVCO / {2(m +1)}, m: value set to FSD 3 4 5 6 7 Fig. 2.7.6 Structure of Frequency synthesizer divide register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 170 of 202 APPLICATION 7643 Group 2.7 PLL 2.7.3 Functional description The frequency synthesizer generates the 48 MHz clock required by f USB and fSYN, which are multiples of the external input reference f(XIN) or f(XCIN). To use the frequency synthesizer, set the frequency synthesizer enable bit of frequency synthesizer control register (address 6C 16) to “ 1 ” . The frequency synthesizer input bit selects either f(X IN) or f(XCIN) as an input clock fIN for the frequency synthesizer. Figure 2.7.7 shows the block diagram for the frequency synthesizer circuit. fVCO fIN Prescaler fPIN Frequency Multiplier Frequency Divider fSYN fUSB FSM2 (address 006E16) FSM1 (address 006D16) Frequency synthesizer lock status bit FSC (address 006C16) FSD (address 006F16) Data Bus Fig. 2.7.7 Block diagram for frequency synthesizer circuit (1) fPIN fIN is divided by the contents of frequency synthesizer multiply register 2 (FSM2: address 6E 16) to generate f PIN, where f PIN = f IN / 2 (n + 1), n: value set to FSM2. When the value of FSM2 is set to 255, the division is not performed and fPIN w ill equal f IN. Figure 2.7.8 shows the frequency synthesizer multiply register 2 setting example. Note : Be sure to set f PIN t o 1 MHz or more. fPIN 24 MHz 1 MHz 2 MHz 3 MHz 6 MHz 12 MHz FSM2 register set value Decimal 255 11 5 3 1 0 Hexadecimal FF16 0B16 0516 0316 0116 0016 fIN 24.00 MHz 24.00 MHz 24.00 MHz 24.00 MHz 24.00 MHz 24.00 MHz Fig. 2.7.8 Frequency synthesizer multiply register 2 setting example Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 171 of 202 APPLICATION 7643 Group 2.7 PLL (2) fVCO f VCO i s generated by multiplying f PIN b y the contents of frequency synthesizer multiply register 1 (FSM1: address 6D 16), where f VCO = f PIN ✕ { 2(n + 1)}, n: value set to FSM1. Set the value of FSM1 so that f VCO w ill be 48 MHz. f VCO i s optimized in the frequency synthesizer to be used as f USB a nd it will be sent into the USB function control unit. While the frequency synthesizer enable bit is “ 0 ” ( disabled), f VCO r etains “ H ” o r “ L ” l evel. Figure 2.7.9 shows the frequency synthesizer multiply register 1 setting example. fPIN 2 MHz 4 MHz 6 MHz 12 MHz 24 MHz FSM1 register set value Decimal Hexadecimal 11 0B16 5 0516 3 0316 1 0116 0 0016 fVCO 48.00 MHz 48.00 MHz 48.00 MHz 48.00 MHz 48.00 MHz Fig. 2.7.9 Frequency synthesizer multiply register 1 setting example (3) f SYN f VCO i s divided by the contents of frequency synthesizer divide register (FSD: address 6F 16) to generate fSYN, where f SYN = f VCO / 2 (m + 1), m: value set to FSD. When the value of FSD is set to 255, the division is not performed and f SYN b ecomes invalid. fSYN can be used as the internal system clock by setting the internal system clock select bit of CPU mode register A. Figure 2.7.10 shows the frequency synthesizer divide register setting example. When the frequency synthesizer lock status bit is “ 1 ” i n the frequency synthesizer enabled, this indicates that fSYN a nd fVCO h ave correct frequencies. fVCO 48.00 MHz 48.00 MHz FSD register set value Decimal 00 127 Hexadecimal 0016 7F16 fSYN 24.00 MHz 187.5 kHz Fig. 2.7.10 Frequency synthesizer divide register setting example Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 172 of 202 APPLICATION 7643 Group 2.7 PLL (4) Recovering from hardware reset The frequency synthesizer and DC-DC converter must be set up as follows when recovering from a Hardware Reset: x Enable the frequency synthesizer after setting the frequency synthesizer related registers (addresses 6C16 t o 6F 16). Then wait for 2 ms. y C heck the frequency synthesizer lock status bit. If “ 0 ” , wait for 0.1 ms and then recheck. z To use the intermediate current, set the LPF current control bits of frequency synthesizer control register (address 6C 16) to (b6, b5) = “ 10 ” . { When using the USB built-in DC-DC converter, set the USB line driver supply enable bit of the USB control register (address 13 16) to “ 1 ” . This setting must be done 2 ms or more later than the setup described in step x. The USB line driver current control bit must be set to “0” at this time. (When Vcc = 3.3V, the setting explained in this step is not necessary.) | A fter waiting for (C + 1) ms so that the external capacitance pin (Ext. Cap. pin) can reach approximately 3.3 V, set the USB clock enable bit to “1”. At this time, “C” equals the capacitance ( µ F) of the capacitor connected to the Ext. Cap. pin. For example, if 2.2 µ F and 0.1 µ F capacitors are connected to the Ext. Cap. in parallel, the required wait will be (2.3 + 1) ms. } A fter enabling the USB clock, wait for 4 or more φ c ycles, and then set the USB enable bit to “1”. Do not write to any of the USB internal registers (addresses 50 16 t o 62 16) until the USB clock enabled, except for the USB control register (address 13 16), clock control register (address 1F16), and frequency synthesizer control register (address 6C 16). 2.7.4 N otes on frequency synthesizer •Bits 6 and 5 of the frequency synthesizer control register (address 6C16) are initialized to (b6, b5) = “11” after reset release. Make sure to set bits 6 and 5 to “ 10 ” a fter the frequency synthesizer lock status bit goes to “ 1 ” . •Use the frequency synthesizer output clocks 2 ms to 5 ms later than setting the frequency synthesizer enable bit to “1” (enabled). After that do not change any register values because it might cause output clocks unstabilized temporarily. • Make sure to connect a low-pulse filter to the LPF pin when using the frequency synthesizer. • The frequency synthesizer divide register set value never affects f USB f requency. • When using the f SYN a s an internal system clock, set the frequency synthesizer divide register so that f SYN c ould be 24 MHz or less. • When using the frequency synthesized clock function, we recommend using the fastest frequency possible of f(X IN) or f(XCIN) as an input clock for the PLL. • Set the value of frequency synthesizer multiply register 2 (FSM2) so that the f PIN i s 1 MHZ or higher. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 173 of 202 APPLICATION 7643 Group 2.8 External device connection 2.8 External devices connection This paragraph explains the registers setting method and the notes related to the external devices connection. 2.8.1 Memory map Address 000016 000116 CPU mode register A (CPMA) CPU mode register B (CPMB) Fig. 2.8.1 Memory map of registers related to external devices connection Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 174 of 202 APPLICATION 7643 Group 2.8 External device connection 2.8.2 Related registers CPU mode register A b7 b6 b5 b4 b3 b2 b1 b0 1 CPU mode register A (CPMA : address 0016) b Name b1b0 Functions At reset R W 0 0 1 1 0 Processor mode bits 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 1 0 : Microprocessor mode (Note 1) 1 1 : Not available 2 Stack page select bit 0 : Page 0 1 : Page 1 3 Nothing is arranged for this bit. Fix this bit to “1”. 4 Sub-clock (XCIN-XCOUT) stop bit 5 Main clock (XIN-XOUT) stop bit Internal system clock 6 select bit (Note 2) 7 External clock select bit 0 0 : Stopped 1 : Oscillating 0 : Oscillating 0 1 : Stopped 0 0 : External clock (XIN-XOUT or XCIN-XCOUT) 1 : fsyn 0 0 : XIN-XOUT 1 : XCIN-XCOUT Notes 1: This is not available in the flash memory version. 2: When (CPMA 7, 6) = (0, 0), the internal system clock can be selected between f(XIN) and f(XIN)/2 by CCR7. The internal clock φ is the internal system clock divided by 2. Fig. 2.8.2 Structure of CPU mode register A CPU mode register B b7 b6 b5 b4 b3 b2 b1 b0 10 CPU mode register B (CPMB : address 0116) b Name b1b0 Functions 0 0 : No wait 0 1 : One-time wait 1 0 : Two-time wait 1 1 : Three-time wait b3b2 At reset R W 1 1 0 0 0 Slow memory wait select bits 1 2 Slow memory wait mode select bits 3 0 0 : Software wait 0 1 : Not available 1 0 : RDY wait 1 1 : Software wait plus RDY input anytime wait 4 Expanded data memory access bit 5 HOLD function enable bit 0 : EDMA output disabled 1 : EDMA output enabled 0 : HOLD function disabled 1 : HOLD function enabled 6 Nothing is arranged for this bit. Fix this bit to “0”. 0 0 0 1 7 Nothing is arranged for this bit. Fix this bit to “1”. Fig. 2.8.3 Structure of CPU mode register B Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 175 of 202 APPLICATION 7643 Group 2.8 External device connection 2.8.3 Functional description This MCU starts its operation in the single-chip mode just after reset. (1) Memory expansion mode This mode is selected by setting “ 01 ” t o the processor mode bits (b1, b0 of CPMA) in software with CNV SS c onnected to V SS. In this mode, the ports function as follows: Ports P0 and P1 as address buses (AB 0 t o AB 15) Port P2 as data buses (DB 0 t o DB 7) ______ ______ Ports P3 3 t o P3 7 a s DMA OUT, φ OUT, SYNC OUT, WR, RD pins respectively. This mode enables external memory expansion while maintaining the validity of the internal ROM. (2) Microprocessor mode This mode is selected by resetting the MCU with CNV SS c onnected to VCC, or by setting “ 10 ” t o the processor mode bits (b1, b0 of CPMA) in software with CNVSS connected to V SS. The function is the same as that of memory expansion mode. In the microprocessor mode, the internal ROM is no longer valid and an external memory must be used. Do not set this mode in the flash memory version. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 176 of 202 APPLICATION 7643 Group 2.8 External device connection 2.8.4 Slow memory wait The slow memory wait function is for easier interfacing with external devices that have long access times. This can be enabled in the memory expansion mode and microprocessor mode. The wait is effective only to external areas. Access to internal area is always performed without wait. (1) Software wait The software wait is selected by setting “ 00 ” t o the slow memory wait mode select bits (b3, b2 of CPMB). Figure 2.8.4 shows the software wait timing example. > 1 bus cycle φ OUT ADOUT DB IN/OUT RD WR Address Address IN OUT Note : Accessing to internal areas is always performed on this waveform. > 1 bus cycle φ OUT ADOUT DB IN/OUT RD WR Address IN Address OUT Note : This example is the 1-cycle software wait. Refer to Chapter 1 “ Slow Memory Wait in PROCESSOR MODE ” f or 2- and 3-cycle software wait timings. Fig. 2.8.4 Software wait timing example Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 177 of 202 APPLICATION 7643 Group 2.8 External device connection (2) RDY wait RDY wait is selected by setting “10” to the slow memory wait mode select bits (b3, b2 of CPMB). When a fixed time of “L” (tsu) is input to the RDY pin at the beginning of a read/write cycle (before φ cycle falls), the MCU goes to the RDY state. Then the read/write cycle can be extended by one to three φ c ycles. The number of φ c ycles to be extended can be selected by the slow memory wait select bits (b1, b0 of CPMB). Even if “L” is input to the RDY pin at the end of waited read/write cycle, the cycle is not extended. When a fixed time of “H” (tsu) is input to the RDY pin at the beginning of a read/write cycle (before φ c ycle falls), the MCU is released from the RDY state. Figure 2.8.5 shows the RDY wait timing example. > 1 bus cycle φ OUT ADOUT DB IN/OUT RD WR Address Address IN OUT > 1 bus cycle φ OUT ADOUT DB IN/OUT RD WR Address IN Address OUT tsu(RDY- φ ) tsu(RDY- φ ) RDY Note : This example is the 1-cycle RDY wait . Refer to Chapter 1 “ Slow Memory Wait in PROCESSOR MODE ” f or 2- and 3-cycle RDY wait timings. Fig. 2.8.5 RDY wait timing example Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 178 of 202 APPLICATION 7643 Group 2.8 External device connection (3) Software wait + Extended RDY wait Extended RDY wait (software wait plus RDY input anytime wait) is selected by setting “11” to the slow memory wait mode select bits (b3, b2 of CPMB). The read/write cycle can be extended when a fixed time (tsu) of “ L ” i s input to the RDY pin at the beginning of a read/write cycle (before φ cycle falls). The RDY pin state is checked continually at each fall of φ cycle until the RDY pin goes to “H” and the cycle keeps being extended. When a fixed time of “H” (tsu) is input to the RDY pin at the beginning of a read/write cycle (before φ c ycle falls), the MCU is released from the wait within 1, 2, or 3 φ c ycles as selected with the slow memory wait bits (b1, b0 of CPMB). Figure 2.8.6 shows the extended RDY wait (software wait plus RDY input anytime wait) timing example > 1 bus cycle φ OUT ADOUT DB IN/OUT RD WR Address Address IN OUT > 1 bus cycle φ OUT ADOUT DB IN/OUT RD WR tsu Address IN tsu tsu tsu RDY 1 2 3 4 1. When a fixed time (tsu) of “L” is input to the RDY pin before φ falls, the MCU goes to RDY state. 2. The RDY pin state is checked continually at each fall of φ cycle. 3. The RDY pin is “L” at the φ fall of the end of the current wait time, so that the read/write cycle is extended for one wait once again. 4. When a fixed time (tsu) of “H” is input to the RDY pin before φ falls, the RDY state is released after the current wait time. Note : This example is the 1-cycle extended RDY wait (RD). The 1-cycle extended RDY wait (WR) is the same timing as this. Refer to Chapter 1 “ Slow Memory Wait in PROCESSOR MODE ” f or 2- and 3-cycle extended RDY wait timings. Fig. 2.8.6 Extended RDY wait (software wait plus RDY input anytime wait) timing example Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 179 of 202 APPLICATION 7643 Group 2.8 External device connection 2.8.5 HOLD function The HOLD function is used for systems that consist of external circuits that access MCU buses without use of the CPU (Central Processing Unit). The HOLD function is used to generate the timing in which the MCU will relinquish the bus from the CPU to the external circuits. To use the HOLD function, set the HOLD function enable bit (b5 of CPMB) to “1”. This can be enabled in the memory expansion mode and microprocessor mode. When “ L ” l evel is input to the HOLD pin, the MCU goes to the HOLD state and remains so while the pin is at “L”. When the MCU relinquishes use of the bus, “L” level is output from the HLDA pin. The MCU puts ports P0 and P1 (address buses) and port P2 (data bus) to tri-state outputs and holds the RD pin (P3 7) and WR pin (P3 6) “ H ” l evel. This will prevent incorrect operations of external devices. Though the clock supply to the CPU halts in HOLD state, the internal peripheral clocks and φ OUT ( P3 4) continues to be supplied. When “ H ” l evel is input to the HOLD pin, “ H ” l evel is output from the HLDA pin and the MCU can use address buses, data bus, signals RD and WR to access to external devices. Figure 2.8.7 shows the Hold function timing diagram. XIN φ OUT RD, W R ADDROUT DATAIN/OUT tsu(HOLD-φ) HOLD HLDA td(φ-HLDAL) td(φ-HLDAH) th(φ-HOLD) Note: This diagram assumes φ = XIN/2. Fig. 2.8.7 Hold function timing diagram Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 180 of 202 APPLICATION 7643 Group 2.8 External device connection 2.8.6 Expanded data memory access In Expanded Data Memory Access Mode (EDMA mode), the MCU can access a data area larger than 64 Kbytes with the LDA ($zz), Y (indirect Y) instruction and the STA ($zz), Y (indirect Y) instruction. It is only able to store and read data for the expanded data memory area. The access can be performed with T flag = “ 0 ” o r “ 1 ” . (T flag is Index X mode flag.) To use this mode, set the expanded data memory access bit (b4 of CPMB) to “1”. In this case, EDMA pin (port P40) goes “L” level during the read/write cycle of the LDA or STA instruction. The determination of which bank to access is done by using an I/O port to represent expanded addresses exceeding address bus (AB 15)16. This signal and the port output signal are put together, and it becomes the chip select (selecting a bank, expanded memory). In EDMA mode, the area from addresses 0000 16 to FFFF 16 can be accessed. When accessing a bank, follow this procedure (four banks are assumed): - Bank specification (Data output to the port for a bank setup 16 (AB16), and 16 (AB17)). The user must setup 16 (AB 16), and 16 (AB 17). __________ - Enabling EDMA output. (Set b4 of CPMB to “ 1 ” .) - Executing LDA ($zz), Y (indirect Y) (In the case of read data of expanded data memory) The data of the address (bank 0) + Y stored in the internal RAM address ($zz) are loaded to the accumulator. Figure 2.8.8 shows a connection example of memory access up to 256 Kbytes. Decoder CS0 7643 group E EDMA P80 P81 DB0 to DB7 AB0 to AB15 RD WR 8 16 CS1 CS2 CS3 74HC139 64K RAM BANK0 64K RAM BANK1 64K RAM BANK2 64K RAM BAN K3 Fig. 2.8.8 Connection example of memory access up to 256 Kbytes Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 181 of 202 APPLICATION 7643 Group 2.8 External device connection 2.8.7 External devices connection example Connection example for controlling external memory is shown bellow. (1) External memory connection example : No Wait function Outline: I n microprocessor mode the external memory is accessed. Figure 2.8.9 shows the external ROM and RAM example. 7643 Group CNVss RDY 2 AD15 74F04 M5M27C256AK-10 CE AD14 to AD0 15 A0 to A14 EPROM M5M5256BP-10 S P31, P32 5 P4 A0 to A14 SRAM 8 P5 DB0 to DB7 8 D0 to D7 DQ1 to DQ8 Memory map 000016 SFR area 000816 External RAM area 001016 SFR area 007016 Internal RAM area 047016 External RAM area 8 P6 5 P7 8 OE OE W P8 RD WR Vcc = 4.15 to 5.25 V 24 MHz 800016 External ROM area FFFF16 Fig. 2.8.9 External ROM and RAM example Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 182 of 202 APPLICATION 7643 Group 2.8 External device connection (2) External memory connection example : RDY function (one wait) in use Outline: RDY function is used because the external memory has a slow-memory-access speed. Specifications: •In read/write status of the CPU, input “L” to the RDY(P30) pin will cause extension of 1 to 3 φ c ycles on its read/write cycle. •When the slow memory wait select bit (b1, b0) is = “01”, it is extended by one cycle. ______ ______ •RD/WR signal holds “L” level during the extended time. •Usable RAM and ROM at f(X IN) = 24 MHz, Vcc = 5 V are given bellow: - OE access time : ta(OE) ≤ 1 07 ns - Data setup time at write : tsu(D) ≤ 1 00 ns - Examples satisfying these specifications: M5M27C256AK-10 (EPROM), M5M5256BP-10 (SRAM) Figure 2.8.10 shows the RDY function use example, and Figures 2.8.11 to 2.8.13 show the read and write cycles. 7643 Group CNVss AD15 74F04 2 M5M27C256AK-10 CE M5M5256BP-10 S P31, P32 RDY AD14 to AD0 15 5 P4 A0 to A14 EPROM A0 to A14 SRAM 8 P5 DB0 to DB7 8 D0 to D7 DQ1 to DQ8 Memory map OE W 000016 SFR area 000816 External RAM area 001016 SFR area 007016 Internal RAM area 047016 External RAM area 8 P6 5 P7 8 OE P8 RD WR Vcc = 4.15 to 5.25 V 24 MHz 800016 External ROM area FFFF16 Fig. 2.8.10 RDY function use example Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 183 of 202 APPLICATION 7643 Group 2.8 External device connection AB0 to AB7 (Port P0) Lower address AB8 to AB14 (Port P1) Upper address S (AB15) OE (RD of 7643) td(AH-RD): 0.5 • 83.33 ns – 28 ns (min.) td(AL-RD): 0.5 • 83.33 ns – 30 ns (min.) DB0 to DB7 (Port P2) twl(RD) (1 + 0.5) • 83.33 ns – 5 ns (min.) ta(OE) 50 ns (max.) tsu(DB-RD) 13 ns (min.) WR “H” level td(AH-RD), td(AL-RD) : AB15-AB8, AB7-AB0 valid time before RD of 7643 group twl(RD) : RD pulse width of 7643 group ta(OE) : Output enable access time of M5M5256BP-10 tsu(DB-RD) : Data bus setup time before RD of 7643 group f(XIN) = 24 MHz Vcc = 5 V Fig. 2.8.11 Read cycle (OE access, SRAM) AB0 to AB7 (Port P0) Lower address AB8 to AB14 (Port P1) Upper address CE tPHL 5.8 ns (max.) twl(RD) (1 + 0.5) • 83.33 ns – 5 ns (min.) ta(OE) 50 ns (max.) tsu(DB-RD) 13 ns (min.) OE (RD of 7643) td(AH-RD): 0.5 • 83.33 ns – 28 ns (min.) td(AL-RD): 0.5 • 83.33 ns – 30 ns (min.) DB0 to DB7 (Port P2) WR “H” level td(AH-RD), td(AL-RD) : AB15-AB8, AB7-AB0 valid time before RD of 7643 group twl(RD) : RD pulse width of 7643 group tPHL : Output delay time of 74F04 ta(OE) : Output enable access time of M5M27C256AK-10 tsu(DB-RD) : Data bus setup time before RD of 7643 group f(XIN) = 24 MHz Vcc = 5 V Fig. 2.8.12 Read cycle (OE access, EPROM) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 184 of 202 APPLICATION 7643 Group 2.8 External device connection AB0 to AB7 (Port P0) Lower address AB8 to AB14 (Port P1) Upper address S (AB15) W (WR of 7643) twl(WR) (1 + 0.5) • 83.33 ns – 5 ns (min.) td(AH-RD): 0.5 • 83.33 ns – 28 ns (min.) td(AL-RD): 0.5 • 83.33 ns – 30 ns (min.) td(WR-DB) 20 ns (max.) DB0 to DB7 (Port P6) tsu(D) 35 ns (min.) OE (RD of 7643) “H” level td(AH-WR), td(AL-WR) : AB15-AB8, AB7-AB0 valid time before WR of 7643 group twl(WR) : WR pulse width of 7643 group td(WR-DB) : Data bus delay time after WR of 7643 group tsu(D) : Data setup time of M5M5256BP-10 f(XIN) = 24 MHz Vcc = 5 V Fig. 2.8.13 Write cycle (W control, SRAM) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 185 of 202 APPLICATION 7643 Group 2.8 External device connection 2.8.8 Notes on external devices connection (1) Rewrite port P3 latch In both memory expansion mode and microprocessor mode, ports P3 1 a nd P32 c an be used as output ports. We recommend to use the L DM i nstruction or S TA i nstruction to write to port P3 register (address 000E16). If using the Read-Modify-Write instruction (SEB instruction, CLB instruction) you will need to map a memory that the CPU can read from and write to. [Reason] The access to address 000E 16 i s performed: • Read from external memory • Write to both port P3 latch and external memory. It is because address 000E16 is assigned on an external area In the memory expansion mode and microprocessor mode. Accordingly, if a Read-Modify-Write instruction is executed to address 000E16, the external memory contents is read out and after its modification it will be written into both port P3 latch and an external memory. As a result, if an external memory is not allocated in address 000E 16 then, the MCU will read an undefined value and write its modified value into the port P3 latch. Therefore port P3 latch value will become undefined. (2) overlap of internal and external memories In the memory expansion mode, if the internal and external memory areas overlap, the internal memory becomes the valid memory for the overlapping area. When the CPU performs a read or a write operation on this overlapped area, the following things happen: •Read The CPU reads out the data in the internal memory instead of in the external memory. Note that, since the CPU will output a proper read signal, address signal, etc., the memory data at the respective address will appear on the external data bus. •Write The CPU writes data to both the internal and external memories. _____ ______ (3) RD, WR pins In the memory expansion mode or microprocessor mode, a read-out control signal is output from ______ ______ the RD pin (P36), and a write-in control signal is output from the WR pin (P3 7). “L” level is output ______ ______ from the RD pin at CPU read-out and from the WR pin at CPU write-in. These signals function for internal access and external access. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 186 of 202 APPLICATION 7643 Group 2.8 External device connection (4) RDY function When using RDY function in usual connection, it does not operate at 12 MHz of φ o r faster. [Reason] td( φ-AH) + tsu(RDY- φ ) = 31 ns (max.) + 21 ns (min.) = 52 ns. twh ( φ ), twl ( φ ) = 0.5 ✕ 8 3.33 – 5 = 3 6.665 ns Therefore, it becomes 52 ns > 36.665 ns, so that the timing to enter RDY wait does not match. ________ However, if the timings can match owing to RDY pin by “L” fixation and others, the RDY function can be used even at φ = 1 2 MHz. In this situation the slow memory wait always functions. (5) Wait function The Wait function is serviceable at accessing an external memory in the memory expansion mode and microprocessor mode. However, in these modes even if an external memory is assigned to addresses 0008 16 t o 000F 16, the Wait function cannot function to these areas. (6) Processor mode switch Note when the processor mode is switched by setting of the processor mode bits (b1, b0 of CPMA), that will immediately switch the accessible memory from external to internal or from internal to external. If this is done, the first cycle of the next instruction will be operated from the accidental memory. To prevent this problem, follow the procedure below: (a) Duplicate the next instruction at the same address both in internal and external memories. (b) Switch from single-chip mode to memory expansion mode, jump to external memory, and then switch from memory expansion mode to microprocessor mode. (Because in general, the problem will not occur when switching the modes as long as the same memory is accessed after the switch. (c) Load a simple program in RAM that switches the modes, jump to RAM and execute the program, then jump to the location of the code to run after the processor mode has switched. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 187 of 202 APPLICATION 7643 Group 2.9 Reset 2.9 Reset 2.9.1 Connection example of reset IC Figure 2.9.1 shows the system example which switches to the RAM backup mode by detecting a drop of the system power source voltage with the INT interrupt. System power source voltage +5 V + VCC1 RESET VCC RESET VCC2 INT INT VSS V1 GND Cd 7643 Group M62009L, M62009P, M62009FP Fig. 2.9.1 RAM backup system 2.9.2 Notes on reset (1) Connecting capacitor In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the V SS pin. Use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following : • M ake the length of the wiring which is connected to a capacitor as short as possible. • B e sure to verify the operation of application products on the user side. q R eason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may cause a microcomputer failure. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 188 of 202 APPLICATION 7643 Group 2.10 Clock generating circuit 2.10 Clock generating circuit This paragraph explains the registers setting method and the notes related to the clock generating circuit. Besides, two modes to realize less power dissipation due to the CPU and some peripherals halted are explained: Stop mode due to STP instruction, Wait mode due to WIT instruction. 2.10.1 Memory map Address 000016 001F16 006C16 006D16 006E16 006F16 CPU mode register A (CPMA) Clock control register (CCR) Frequency synthesizer control register (FSC) Frequency synthesizer multiply register 1 (FSM1) Frequency synthesizer multiply register 2 (FSM2) Frequency synthesizer divide register (FSD) Fig. 2.10.1 Memory map of registers related to clock generating circuit Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 189 of 202 APPLICATION 7643 Group 2.10 Clock generating circuit 2.10.2 Related registers CPU mode register A b7 b6 b5 b4 b3 b2 b1 b0 1 CPU mode register A (CPMA : address 0016) b Name b1b0 Functions At reset R W 0 0 1 1 0 Processor mode bits 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 1 0 : Microprocessor mode (Note 1) 1 1 : Not available 2 Stack page select bit 0 : Page 0 1 : Page 1 3 Nothing is arranged for this bit. Fix this bit to “1”. 4 Sub-clock (XCIN-XCOUT) stop bit 5 Main clock (XIN-XOUT) stop bit 6 Internal system clock select bit (Note 2) 7 External clock select bit 0 0 : Stopped 1 : Oscillating 0 : Oscillating 0 1 : Stopped 0 0 : External clock (XIN-XOUT or XCIN-XCOUT) 1 : fsyn 0 0 : XIN-XOUT 1 : XCIN-XCOUT Notes 1: This is not available in the flash memory version. 2: When (CPMA 7, 6) = (0, 0), the internal system clock can be selected between f(XIN) and f(XIN)/2 by CCR7. The internal clock φ is the internal system clock divided by 2. Fig. 2.10.2 Structure of CPU mode register A Clock control register b7 b6 b5 b4 b3 b2 b1 b0 00000 Clock control register (CCR : address 1F16) b Name Functions At reset R W 0 0 0 0 0 0 0 Nothing is arranged for these bits. 1 Fix these bits to “0”. 2 3 4 5 XCOUT oscillation drive 0 : XCOUT oscillation drive is enabled. disable bit (CCR5) (When XCIN oscillation is enabled.) 1 : XCOUT oscillation drive is disabled. 0 : XOUT oscillation drive is enabled. 6 XOUT oscillation drive disable bit (CCR6) (When XIN oscillation is enabled.) 1 : XOUT oscillation drive is disabled. 0 : f(XIN)/2 is used for the system clock. 7 XIN divider select bit (CCR7) (Note) 1 : f(XIN) is used for the system clock. Note: This bit is valid when (b7, b6 of CPMA) = “00”. 0 0 Fig. 2.10.3 Structure of Clock control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 190 of 202 APPLICATION 7643 Group 2.10 Clock generating circuit Frequency synthesizer control register b7 b6 b5 b4 b3 b2 b1 b0 0 00 Frequency synthesizer control register (FSC : address 6C16) b Name Functions At reset R W 0 0 0 0 0 1 1 0 0 Frequency synthesizer enable bit (FSE) 0 : Disabled 1 : Enabled 1 Nothing is arranged for these bits. 2 Fix these bits to “0”. 0 : f(XIN) 3 Frequency synthesizer 1 : f(XCIN) input bit (FIN) 4 Nothing is arranged for this bit. Fix this bit to “0”. 5 LPF current control bit (CHG1, CHG0) (Note) 6 7 Frequency synthesizer lock status bit b1b0 0 0 : Not available 0 1 : Low current 1 0 : Intermediate current (recommended) 1 1 : High current 0 : Unlocked 1 : Locked Note: Bits 6 and 5 are set to (bit 6, bit 5) = (1, 1) at reset. When using the frequency synthesizer, we recommend to set to (bit 6, bit 5) = (1, 0) after locking the frequency synthesizer. Fig. 2.10.4 Structure of Frequency synthesizer control register Frequency synthesizer multiply register 1 b7 b6 b5 b4 b3 b2 b1 b0 Frequency synthesizer multiply register 1 (FSM1: address 6D16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qfVCO clock is generated by multiplying fPIN clock, which is generated by FSM2, by the contents of this register: 1 2 fVCO = fPIN • {2(n +1)}, n: value set to FSM1. 3 4 5 6 7 Fig. 2.10.5 Structure of Frequency synthesizer multiply register 1 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 191 of 202 APPLICATION 7643 Group 2.10 Clock generating circuit Frequency synthesizer multiply register 2 b7 b6 b5 b4 b3 b2 b1 b0 Frequency synthesizer multiply register 2 (FSM2: address 6E16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qfPIN clock is generated by dividing fIN clock by the contents of this register. 1 Either f(XIN) or f(XCIN) as an input clock fIN for the frequency 2 synthesizer is selectable. 3 4 fPIN = fIN / {2(n +1)}, n: value set to FSM2 5 6 7 Fig. 2.10.6 Structure of Frequency synthesizer multiply register 2 Frequency synthesizer divide register b7 b6 b5 b4 b3 b2 b1 b0 Frequency synthesizer divide register (FSD: address 6F16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qfSYN clock is generated by dividing fVCO clock by the contents of this register: 1 2 fSYN = fVCO / {2(m +1)}, m: value set to FSD 3 4 5 6 7 Fig. 2.10.7 Structure of Frequency synthesizer divide register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 192 of 202 APPLICATION 7643 Group 2.10 Clock generating circuit 2.10.3 Stop mode The Stop mode is set by executing the STP instruction. In Stop mode, the oscillation of both clocks (XIN– XOUT, XCIN–XCOUT) stop and the internal clock φ stops at the “H” level. The CPU stops and peripheral units stop operating. As a result, power dissipation is reduced. (1) State in Stop mode Table 2.10.1 shows the state in Stop mode. Table 2.10.1 State in Stop mode Item Oscillation CPU Internal clock φ I/O ports Timer UART DMAC Serial I/O USB RAM SFR CPU registers Stopped. Stopped. Stopped at “ H ” l evel. Retains the state at the STP instruction execution. Stopped. Stopped. Stopped. When using internal syncronous clock: Stopped. When using external syncronous clock: Operating. Stopped. Retained. Retained (except for Timer 1, Timer 2). Retained: Accumulator, Index register X, Index register Y, Stack pointer, Program counter, Processor status register. State in Stop mode (2) Release of Stop mode The Stop mode is released by a reset input or by the occurrence of an interrupt request. These interrupt sources can be used for restoration: • INT 0, INT 1 • Serial I/Os using an external clock •Key-on wake-up • USB function resume However, when using any of these interrupt requests for restoration from Stop mode, i n order to enable the selected interrupt, set the following conditions before execution of STP instruction. [Necessary register setting] ➀ T imer 1 interrupt enable bit (b6 of ICONB) = “ 0 ” ( interrupt disabled) ➁ T imer 2 interrupt enable bit (b7 of ICONB) = “ 0 ” ( interrupt disabled) ➂ T imer 1 interrupt request bit (b6 of IREQB) = “ 0 ” ( no interrupt request issued) ➃ T imer 2 interrupt request bit (b7 of IREQB) = “ 0 ” ( no interrupt request issued) ➄ Interrupt request bit of interrupt source to be used for restoration = “0” (no interrupt request issued) ➅ I nterrupt enable bit of interrupt source to be used for restoration = “ 1 ” ( interrupts enabled) ➆ I nterrupt disable flag I = “ 0 ” ( interrupt enabled) (3) Notes on STP instruction •Execution of STP instruction clears the timer 123 mode register (address 2916) except bit 4 to “0”. • When using fSYN as the internal system clock, switch to f(XIN) or f(X CIN) before execution of STP instruction. • Execution of STP instruction clears bit 7 of clock control register to “ 0 ” ( f(X IN)/2). Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 193 of 202 APPLICATION 7643 Group 2.10 Clock generating circuit 2.10.4 Wait mode The Wait mode is set by execution of the WIT instruction. In Wait mode, oscillation continues, but the internal clock φ s tops at the “ H ” l evel. The CPU stops, but most of the peripheral units continue operating. (1) State in Wait mode Table 2.10.2 shows the state in Wait mode. Table 2.10.2 State in Wait mode Item Oscillation CPU Internal clock φ I/O ports Timer UART DMAC Serial I/O USB RAM SFR CPU registers Oparating. Stopped. Stopped at “ H ” l evel. Retains the state at the WIT instruction execution. Operating. Operating. Stopped. Operating. Operating. Retained. Retained. Retained: Accumulator, Index register X, Index register Y, Stack pointer, Program counter, Processor status register. State in Wait mode (2) Release of wait mode The Wait mode is released by reset input or by the occurrence of an interrupt request. In Wait mode oscillation is continued, so that an instruction can be executed immediately after the Wait mode is released. These interrupt sources can be used for restoration: • INT0, INT1 •Timers • Serial I/Os •UART •DMAC •Key-on wake-up •USB function However, when using any of these interrupt requests for restoration from Stop mode, i n order to enable the selected interrupt, set the following conditions before execution of WIT instruction. [Necessary ➀ I nterrupt issued) ➁ I nterrupt ➂ I nterrupt register setting] request bit of interrupt source to be used for restoration = “ 0 ” ( no interrupt request enable bit of interrupt source to be used for restoration = “ 1 ” ( interrupts enabled) disable flag I = “ 0 ” ( interrupt enabled) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 194 of 202 APPLICATION 7643 Group 2.10 Clock generating circuit 2.10.5 Clock generating circuit application examples (1) Status transition during power failure Outline: T he clock is counted up every one second by using the timer interrupt during a power failure. Input port (Note) Power failure detection signal 7643 Group Note: A signal is detected when input to input port, interrupt input pin, or analog input pin. Fig. 2.10.8 Connection diagram Specifications: •Reducing power dissipation as low as possible while maintaining clock function • Clock: f(X IN) = 4.19 MHz, f(X CIN) = 32.768 kHz •Port processing Input port: Fixed to “ H ” o r “ L ” l evel on the external Output port: Fixed to output level that does not cause current flow to the external (Example) When a circuit turns on LED at “L” output level, fix the output level to “ H ” . I/O port: Input port → F ixed to “ H ” o r “ L ” l evel on the external Output port → O utput of data that does not consume current Figure 2.10.9 shows the status transition diagram during power failure and Figure 2.10.10 shows the setting of relevant registers. Reset released Power failure detected XIN XCIN Internal system clock Middle-speed mode High-speed mode Low-speed mode Change internal system clock to high-speed mode After detection, change internal system clock to low-speed mode and stop oscillating XIN-XOUT XCIN-XCOUT oscillation function selected Fig. 2.10.9 Status transition diagram during power failure Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 195 of 202 APPLICATION 7643 Group 2.10 Clock generating circuit Clock control register (address 1F16) b7 b0 CCR 00000 0 : Middle-speed mode (f(XIN)/2) 1 : High-speed mode (f(XIN)) CPU mode register A (address 0016) b7 b0 CPMA 00011 Sub-clock f(XCIN) oscillating Main-clock f(XIN) oscillating Main-clock f(XIN) selected CPU mode register A (address 0016) b7 b0 CPMA 1 0 1 1 1 Sub-clock f(XCIN) oscillating Main-clock f(XIN) stopped Sub-clock f(XCIN) selected Fig. 2.10.10 Setting of relevant registers Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 196 of 202 APPLICATION 7643 Group 2.10 Clock generating circuit Control procedure: S et the relevant registers in the order shown below to prepare for a power failure. RESET qX: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization CCR (address 1F16) CPMA (address 0016) CPMA (address 0016), bit 7 CPMA (address 0016), bit5 Set timer interrupt to occurs every second. Execute WIT instruction. •••• 100000002 00011XXX2 When selecting main clock f(XIN) (high-speed mode) •••• Detect power failure ? Y 1 (Note) 1 (Note) f(XCIN) (low-speed mode) selected as internal system clock Main clock f(XIN) oscillation stopped N At power failure, clock count is performed during timer interrupt processing (every second). N Return condition from power failure completed ? Y Return processing from power failure Note: Do not switch simultaneously. Fig. 2.10.11 Control procedure Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 197 of 202 APPLICATION 7643 Group 2.10 Clock generating circuit (2) Counting without clock error during power failure Outline: I t keeps counting without clock error during a power failure. Specifications: •Reducing power consumption as low as possible while maintaining clock function • Clock: f(X IN) = 24 MHz • Sub clock: f(X CIN) = 32.768 kHz • Use of Timer 2 interrupt For the peripheral circuit and the status transition during a power failure, refer to Figures 2.10.8 and 2.10.9. Figure 2.10.12 shows the structure of clock counter, Figures 2.10.13 and 2.10.14 show the setting of relevant registers. Timer 1 interrupt Timer 1 Base counter 1 second counter 1 minute counter f(XIN) = 24 MHz 1/2 1/8 1/255 170 µs 1/245 1/24 1s 1/60 Minute/Time/Day/Month/Year When the system returns from a power failure, add the time taken for the switching processing for the return. Timer 2 interrupt Timer 1 Timer 2 f(XCIN) = 32.768 kHz 1/2 1/3 183 µs 1/228 1/24 : Software timer : Hardware timer Fig. 2.10.12 Structure of clock counter Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 198 of 202 APPLICATION 7643 Group 2.10 Clock generating circuit CPU mode register A (address 0016) b7 b0 CPMA 00011 XCIN-XCOUT oscillating XIN-XOUT oscillating External clock selected as internal system clock f(XIN) selected as external clock; f(XCIN) selected at power failure Clock control register (address 1F16) b7 b0 CCR 1 00000 XIN division: f(XIN) (high-speed mode) Timer 1 (address 2416) b7 b0 T1 254 Set (Division ratio -1); 254 (FE16) Timer 123 mode register (address 2916) b7 b0 T123M 0 000 Timer 1 count: Operating Timer 1 count source: φ/8 Timer 2 count source: Timer 1 output Timer 1, 2 write: Write value in latch and counter Interrupt request register B (address 0316) b7 b0 IREQB 00 Set “0” to timer 1 interrupt request bit Set “0” to timer 2 interrupt request bit Interrupt control register B (address 0616) b7 b0 ICONB 0100000 Timer 1 interrupt: Enabled Timer 2 interrupt: Disbled Fig. 2.10.13 Initial setting of relevant registers Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 199 of 202 APPLICATION 7643 Group 2.10 Clock generating circuit Timer 123 mode register (address 2916) b7 b0 T123M 0 010 Timer 1 count: Operating Timer 1 count source: f(XCIN)/2 Timer 2 count source: Timer 1 output Timer 1, 2 write: Write value in latch and counter Interrupt control register B (address 0616) b7 b0 ICONB 100 0000 Timer 1 interrupt: Disabled Timer 2 interrupt: Enbled CPU mode register A (address 0016) b7 b0 CPMA 10111 XCIN-XCOUT oscillating XIN-XOUT stopped External clock selected as internal system clock f(XCIN) selected as external clock Timer 1 (address 2416) b7 b0 T1 02 Set (Division ratio -1) (T1 = 2 (0216), T2 = 227 (E216) Timer 2 (address 2516) b7 b0 T2 227 Fig. 2.10.14 Setting of relevant registers after detecting power failure Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 200 of 202 APPLICATION 7643 Group 2.10 Clock generating circuit Control procedure: S et the relevant registers in the order shown below to prepare for a power failure. RESET qX: This bit is not used here. Set it to “0” or “1” arbitrarily. Initialization CPMA (address 0016) CCR (address 1F16) T1 (address 2416) T123M (address 2916) IREQB (address 3C16), bit 7, bit 6 Base counter (internal RAM) 1 second counter (internal RAM) ICONB (address 0616), bit 6 •••• •••• 00011XXX2 1XX000002 FE16 0XX0X00X2 0,0 F516 1816 1 When selecting main clock f(XIN) (high-speed mode) Setting for making base and one second counters activate during timer 1 interrupt In the normal power state, these software counters generate one second. CLI Detect power failure ? Y T123M (address 2916), bit 2 ICONB (address 0616), bit 6 CPMA (address 0016), bit 7 CPMA (address 0016), bit 5 IREQB (address 0616), bit 7, bit 6 T1 (address 2416) T2 (address 2516) 1 0 1 (Note) 1 (Note) 0, 0 0216 E216 N Timer 1 count source: f(XCIN) Timer 1 interrupt: Disabled Internal system clock: f(XCIN) (low-speed mode) Main clock f(XIN): Oscillation stopped Setting for generating timer 2 interrupt every second Generation of one second by hardware timer during power failure ICONB (address 0616), bit 7 1 Execute WIT instruction Timer 2 interrupt: Enabled N Return condition for power failure is satisfied ? Y Return processing from power failure Timer 2 interrupt occurs every second (return from wait mode) Note: Do not switch at one time. Fig. 2.10.15 Control procedure (1) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 201 of 202 APPLICATION 7643 Group 2.10 Clock generating circuit Timer 2 interrupt routine Push registers to stack etc. •••• Count 1 minute (internal RAM) counter 1 minute counter overflow ? N Y Modify time, day, month, year ∼ RTI Fig. 2.10.16 Control procedure (2) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 202 of 202 CHAPTER 3 APPENDIX 3.1 Electrical characteristics 3.2 Standard characteristics 3.3 Notes on use 3.4 Countermeasures against noise 3.5 Control registers 3.6 Package outline 3.7 Machine instructions 3.8 List of instruction code 3.9 SFR memory area 3.10 Pin configuration APPENDIX 7643 Group 3.1 Electrical characteristics 3.1 Electrical characteristics 3.1.1 Absolute maximum ratings Table 3.1.1 Absolute maximum ratings Symbol VCC AVCC VI Parameter Power source voltage Analog power source voltage AVcc, Ext.Cap Input voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 Input voltage RESET, XIN, XCIN Input voltage CNVSS Mask ROM version Flash memory version Input voltage USB D+, USB D– Output voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87, XOUT, XCOUT, LPF Output voltage USB D+, USB D–, Ext. Cap Power dissipation (Note) Operating temperature Storage temperature Conditions All voltages are based on Vss. Output transistors are cut off. Ratings –0.3 to 6.5 –0.3 to VCC+0.3 –0.3 to VCC+0.3 Unit V V V VI VI VI VO –0.3 to VCC+0.3 –0.3 to Vcc + 0.3 –0.3 to 6.5 –0.5 to 3.8 –0.3 to VCC+0.3 V V V V V VO Pd Topr Tstg Ta = 25°C –0.5 to 3.8 750 –20 to 70 –40 to 125 V mW °C °C Note: The maximum power dissipation depends on the MCU’s power dissipation and the specific heat consumption of the package. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 2 of 98 APPENDIX 7643 Group 3.1 Electrical characteristics 3.1.2 Recommended operating conditions (In Vcc = 5 V) Table 3.1.2 Recommended operating conditions (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) Symbol VCC AVcc VSS AVSS VIH Power source voltage Analog reference voltage Power source voltage Analog reference voltage “H” input voltage Parameter Limits Min. 4.15 4.15 Typ. 5.0 5.0 0 0 Max. 5.25 VCC Unit V V V V V VIH VIH VIH VIL VIL VIL VIL ΣIOH(peak) ΣIOL(peak) ΣIOH(avg) ΣIOL(avg) IOH(peak) IOL(peak) IOH(avg) IOL(avg) f(XIN) f(XCIN) P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” input voltage (Selecting VIHL level input) P20–P27 “H” input voltage RESET, XIN, XCIN, CNVss “H” input voltage USB D+, USB D– “L” input voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” input voltage (Selecting VIHL level input) P20–P27 “L” input voltage RESET, XIN, XCIN, CNVss “L” input voltage USB D+, USB D– “H” total peak output current P00–P07, P10–P17, P20–P27, (Note 1) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” total peak output current P00–P07, P10–P17, P20–P27, (Note 1) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” total average output current P00–P07, P10–P17, P20–P27, (Note 1) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” total average output current P00–P07, P10–P17, P20–P27, (Note 1) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” peak output current P00–P07, P10–P17, P20–P27, (Note 2) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” peak output current P00–P07, P10–P17, P20–P27, (Note 2) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” average output current P00–P07, P10–P17, P20–P27, (Note 3) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” average output current P00–P07, P10–P17, P20–P27, (Note 3) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 Main clock input frequency (Notes 4, 5) Sub-clock input frequency (Notes 4, 6) 0.8VCC VCC 0.5VCC 0.8VCC 2.0 0 VCC VCC 3.8 0.2VCC V V V V 0 0 0.16VCC 0.2VCC 0.8 –80 V V V mA 80 mA –40 mA 40 mA –10 mA 10 mA –5.0 mA 5.0 mA 1 32.768 24 50/5.0 MHz kHz/MHz Notes 1: The total peak output current is the peak value of the peak currents flowing through all the applicable ports. The total average output current is the average value measured over 100 ms flowing through all the applicable ports. 2: The peak output current is the peak current flowing in each port. 3: The average output current is an average value measured over 100 ms. 4: The duty of oscillation frequency is 50 %. 5: Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins. Its maximum oscillation frequency must be 24 MHz. However, make sure to set φ to 12 MHz or slower. More faster clocks are required as the f(XIN) when using the frequency synthesizer as possible. 6: Connect a ceramic resonator or a quartz-crystal oscillator between the XCIN and XCOUT pins. Its maximum oscillation frequency must be 50 kHz. Input an external clock having 5 MHz frequency (max.) from the XCIN pin. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 3 of 98 APPENDIX 7643 Group 3.1 Electrical characteristics 3.1.3 Electrical characteristics (In Vcc = 5 V) Table 3.1.3 Electrical characteristics (1) (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) Symbol VOH Parameter “H” output voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” output voltage USB D+, USB DTest conditions IOH = –10 mA Min. VCC–2.0 Limits Typ. Max. Unit V VOH VOL VOL “L” output voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” output voltage USB D+, USB D- USB+, and USB- pins pull-down via a resistor of 15 kΩ ± 5 % USB+ pin pull-up to Ext. Cap. pin via a resistor of 1.5 kΩ ± 5 % IOL = 10 mA 2.8 3.6 V 2.0 V USB+, and USB- pins pull-down via a resistor of 15 kΩ ± 5 % USB+ pin pull-up to Ext. Cap. pin via a resistor of 1.5 kΩ ± 5 % 0.3 V VT+–VT- VT+–VT- VT+–VTIIH IIH IIH IIH IIL IIL IIL IIL IIL IIL Hysteresis INT0, INT1, RDY, HOLD, P20–P27 (Note 1) Hysteresis URXD, SCLK, SRXD, SRDY, CTS Hysteresis RESET “H” input current P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” input current RESET, CNVSS “H” input current XIN “H” input current XCIN “L” input current P00–P07, P10–P17, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” input current RESET “L” input current CNVSS “L” input current XIN “L” input current XCIN “L” input current P20–P27 0.5 V 0.5 V 0.5 VI = VCC 5.0 V µA 9.0 VI = VSS 5.0 20 5.0 –5.0 µA µA µA µA –9.0 VI = VSS Pull-ups “off” VCC = 5.0 V, VI = VSS Pull-ups “on” When clock is stopped –5.0 –20 –20 –5.0 –5.0 –140 5.25 µA µA µA µA µA µA V –30 2.0 –65 VRAM RAM hold voltage Note 1: This spec is hysteresis of key input interrupt. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 4 of 98 APPENDIX 7643 Group 3.1 Electrical characteristics In Vcc = 5 V Table 3.1.4 Electrical characteristics (2) (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) Symbol ICC Parameter Power source current (Output transistor is isolated.) Test conditions Normal mode (Note 1) f(XIN) = 24 MHz, φ = 12 MHz USB operating Frequency synthesizer ON Wait mode (Note 2) f(XIN) = 24 MHz, φ = 12 MHz USB block enabled, USB clock stopped, Frequency synthesizer ON Wait mode (Note 3) f(XCIN) = 32 kHz, φ = 16 kHz USB block disabled Frequency synthesizer OFF USB transceiver DC-DC converter OFF Stop mode USB transceiver DC-DC converter ON Low current mode (USBC3 = “1”) Stop mode USB transceiver DC-DC converter OFF Ta = 25 °C Stop mode USB transceiver DC-DC converter OFF Ta = 70 °C Min. Limits Typ. 40 Max. 90 Unit mA 5.0 11 mA 10 µA 100 250 µA 1.0 µA µA 10 Notes 1: Operating in single-chip mode Clock input from XIN pin (XOUT oscillator stopped) USB operating with USB transceiver DC-DC converter enabled Operating functions: Frequency synthesizer, CPU, UART, DMAC, Timers Disabled functions: Serial I/O 2: Operating in single-chip mode with Wait mode Clock input from XIN pin (XOUT oscillator stopped) USB suspended due to USB clock stopped with USB transceiver DC-DC converter enabled Operating functions: Frequency synthesizer, Timers Disabled functions: CPU, UART, DMAC and Serial I/O 3: Operating in single-chip mode with Wait mode XIN - XOUT oscillator stopped Clock input from XCIN pin (XCOUT oscillator stopped) USB stopped, USB clock stopped and USB transceiver DC-DC converter disabled Operating functions: Timers Disabled functions: Frequency synthesizer, CPU, UART, DMAC and Serial I/O Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 5 of 98 APPENDIX 7643 Group 3.1 Electrical characteristics 3.1.4 Timing requirements (In Vcc = 5 V) Table 3.1.5 Timing requirements (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(XCIN) Parameter Min. 2 41.66 0.4•tc(XIN) 0.4•tc(XIN) 200 0.4•tc(XCIN) 0.4•tc(XCIN) 200 90 90 15 400 190 180 15 10 25 26 166.66 0.5•tc(SCLKI) – 5 0.5•tc(SCLKI) – 5 20 5 5 Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Reset input “L” pulse width Main clock input cycle time (Note) Main clock input “H” pulse width Main clock input “L” pulse width Sub-clock input cycle time tWH(XCIN) Sub-clock input “H” pulse width tWL(XCIN) Sub-clock input “L” pulse width tC(INT) INT0, INT1 input cycle time tWH(INT) INT0, INT1 input “H” pulse width tWL(INT) INT0, INT1 input “L” pulse width td(φ -TOUT) Timer TOUT delay time tC(SCLKE) Serial I/O external clock input cycle time tWH(SCLKE) Serial I/O external clock input “H” pulse width tWL(SCLKE) Serial I/O external clock input “L” pulse width tsu(SRXD-SCLKE) Serial I/O input setup time (external clock) th(SCLKE-SRXD) Serial I/O input hold time (external clock) td(SCLKE-STXD) Serial I/O output delay time (external clock) tv(SCLKE-SRDY) Serial I/O SRDY valid time (external clock) tc(SCLKI) Serial I/O internal clock output cycle time tWH(SCLKI) Serial I/O internal clock output “H” pulse width tWL(SCLKI) Serial I/O internal clock output “L” pulse width tsu(SRXD-SCLKI) Serial I/O input setup time (internal clock) th(SCLKI-SRXD) Serial I/O input hold time (internal clock) td(SCLKI-STXD) Serial I/O output delay time (internal clock) Note: Make sure not to exceed 12 MHz of φ, in other words, tc(φ) ≥ 83.33 ns). For example, set bit 7 of the clock control register (CCR) to “0” in the case of tc(XIN) < 41.66 ns. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 6 of 98 APPENDIX 7643 Group 3.1 Electrical characteristics 3.1.5 Timing requirements and switching characteristics in memory expansion and microprocessor modes (In Vcc = 5 V) Table 3.1.6 Timing requirements and switching characteristics in memory expansion and microprocessor modes (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted) Symbol tC(φ) tWH(φ) tWL(φ) td(φ -AH) tv(φ -AH) td(φ -AL) tv(φ -AL) td(φ -WR) tv(φ -WR) td(φ -RD) tv(φ -RD) td(φ -SYNC) tv(φ -SYNC) td(φ -DMA) tv(φ -DMA) tsu(RDY- φ) th(φ -RDY) tsu(HOLD- φ) th(φ -HOLD) td(φ -HLDAL) td(φ -HLDAH) tsu(DB- φ) th(φ -DB) td(φ -DB) tV(φ -DB) td(φ -EDMA) tv(φ -EDMA) tWL(WR) (Note 2) tWL(RD) (Note 2) td(AH-WR) td(AL-WR) tv(WR-AH) tv(WR-AL) td(AH-RD) td(AL-RD) tv(RD-AH) tv(RD-AL) tsu(RDY-WR) th(WR-RDY) tsu(RDY-RD) th(RD-RDY) tsu(DB-RD) th(RD-DB) td(WR-DB) tv(WR-DB) tv(WR-EDMA) tv(RD-EDMA) tr(D+), tr(D-) tf(D+), tf(D-) Parameter φ clock cycle time φ clock “H” pulse width φ clock “L” pulse width AB15–AB8 delay time AB15–AB8 valid time AB7–AB0 delay time AB7–AB0 valid time WR delay time WR valid time RD delay time RD valid time SYNCOUT delay time SYNCOUT valid time DMAOUT delay time DMAOUT valid time RDY setup time RDY hold time HOLD setup time HOLD hold time HOLD “L” delay time HOLD “H” delay time Data bus setup time Data bus hold time Data bus delay time Data bus valid time (Note 1) EDMA delay time EDMA valid time WR pulse width RD pulse width AB15–AB8 valid time before WR AB7–AB0 valid time before WR AB15–AB8 valid time after WR AB7–AB0 valid time after WR AB15–AB8 valid time before RD AB7–AB0 valid time before RD AB15–AB8 valid time after RD AB7–AB0 valid time after RD RDY setup time before WR RDY hold time after WR RDY setup time before RD RDY hold time after RD Data bus setup time before RD Data bus hold time after RD Data bus delay time before WR Data bus valid time after WR (Note 1) EDMA delay time after WR EDMA valid time after RD USB output rise time, CL = 50 pF USB output fall time, CL = 50 pF Min. 83.33 0.5•tc(φ) – 5 0.5•tc(φ) – 5 0 33 0 6 0 6 0 6 0 25 0 21 0 21 0 25 25 7 0 22 13 12 0 0.5•tc(φ) – 5 0.5•tc(φ) – 5 0.5•tc(φ) – 28 0.5•tc(φ) – 30 0 0 0.5•tc(φ) – 28 0.5•tc(φ) – 30 0 0 27 0 27 0 13 0 20 10 0 0 4 4 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 31 20 20 Notes 1: Test conditions: IOHL = ± 5mA, CL = 50 pF 2: twL(RD) = ((n + 0.5) • tc(PHI)) – 5 ns (n = wait number) twL(WR) = ((n + 0.5) • tc(PHI)) – 5 ns (n = wait number) For example, two software waits, PHI = 12 MHz operating: twL(RD) = 2.5 • tc(PHI) – 5 ns = 203.33 ns Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 7 of 98 APPENDIX 7643 Group 3.1 Electrical characteristics 3.1.6 Recommended operating conditions In Vcc = 3 V Table 3.1.7 Recommended operating conditions (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) Symbol VCC AVcc VSS AVSS Ext. Cap. VIH Power source voltage Analog reference voltage Power source voltage Analog reference voltage DC-DC converter voltage “H” input voltage Parameter Limits Min. 3.0 3.0 Typ. 3.3 3.3 0 0 3.3 Max. 3.6 VCC Unit V V V V V VIH VIH VIH VIL P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” input voltage (Selecting VIHL level input) P20–P27 “H” input voltage RESET, XIN, XCIN, CNVss “H” input voltage USB D+, USB D– “L” input voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” input voltage (Selecting VIHL level input) P20–P27 “L” input voltage RESET, XIN, XCIN, CNVss “L” input voltage USB D+, USB D– “H” total peak output current P00–P07, P10–P17, P20–P27, (Note 1) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” total peak output current P00–P07, P10–P17, P20–P27, (Note 1) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” total average output current P00–P07, P10–P17, P20–P27, (Note 1) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” total average output current P00–P07, P10–P17, P20–P27, (Note 1) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” peak output current P00–P07, P10–P17, P20–P27, (Note 2) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” peak output current P00–P07, P10–P17, P20–P27, (Note 2) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” average output current P00–P07, P10–P17, P20–P27, (Note 3) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” average output current P00–P07, P10–P17, P20–P27, (Note 3) P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 Main clock input frequency (Notes 4, 5) Sub-clock input frequency (Notes 4, 6) 3.0 0.8VCC 3.6 VCC 0.5VCC 0.8VCC 2.0 0 VCC VCC 0.2VCC V V V V V V V V mA mA VIL VIL VIL ΣIOH(peak) ΣIOL(peak) ΣIOH(avg) ΣIOL(avg) 0 0 0.16VCC 0.2VCC 0.8 –80 80 mA –40 mA 40 mA IOH(peak) –10 mA IOL(peak) 10 mA IOH(avg) –5.0 mA IOL(avg) 5.0 mA f(XIN) f(XCIN) 1 32.768 24 50/5.0 MHz kHz/MHz Notes 1: The total peak output current is the peak value of the peak currents flowing through all the applicable ports. The total average output current is the average value measured over 100 ms flowing through all the applicable ports. 2: The peak output current is the peak current flowing in each port. 3: The average output current is an average value measured over 100 ms. 4: The duty of oscillation frequency is 50 %. 5: Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins. Its maximum oscillation frequency must be 24 MHz. However, make sure to set φ to 6 MHz or slower. More faster clocks are required as the f(XIN) when using the frequency synthesizer as possible. 6: Connect a ceramic resonator or a quartz-crystal oscillator between the XCIN and XCOUT pins. Its maximum oscillation frequency must be 50 kHz. Input an external clock having 5 MHz (max.) frequency from the XCIN pin. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 8 of 98 APPENDIX 7643 Group 3.1 Electrical characteristics 3.1.7 Electrical characteristics In Vcc = 3 V Table 3.1.8 Electrical characteristics (1) (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) Symbol VOH Parameter “H” output voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” output voltage USB D+, USB DTest conditions IOH = –1 mA Min. VCC–1.0 Limits Typ. Max. Unit V VOH VOL VOL “L” output voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” output voltage USB D+, USB D- USB+, and USB- pins pull-down via a resistor of 15 kΩ ± 5 % USB+ pin pull-up to Ext. Cap. pin via a resistor of 1.5 kΩ ± 5 % IOL = 1 mA 2.8 3.6 V 1.0 V USB+, and USB- pins pull-down via a resistor of 15 kΩ ± 5 % USB+ pin pull-up to Ext. Cap. pin via a resistor of 1.5 kΩ ± 5 % 0 0.3 V VT+–VT- VT+–VT- VT+–VTIIH IIH IIH IIH IIL IIL IIL IIL IIL IIL Hysteresis INT0, INT1, RDY, HOLD, P20–P27 (Note 1) Hysteresis URXD, SCLK, SRXD, SRDY, CTS Hysteresis RESET “H” input current P00–P07, P10–P17, P20–P27, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “H” input current RESET, CNVSS “H” input current XIN “H” input current XCIN “L” input current P00–P07, P10–P17, P30–P37, P40–P44, P50–P57, P60–P67, P70–P74, P80–P87 “L” input current RESET “L” input current CNVSS “L” input current XIN “L” input current XCIN “L” input current P20–P27 0.3 V 0.3 V 0.3 VI = VCC 5.0 V µA 9.0 VI = VSS 5.0 20 5.0 –5.0 µA µA µA µA –9.0 VI = VSS Pull-ups “off” VCC = 3.0 V, VI = VSS Pull-ups “on” When clock is stopped –5.0 –20 –20 –5.0 –5.0 –50 µA µA µA µA µA µA V –10 2.0 –20 VRAM RAM hold voltage Note 1: This spec is hysteresis of key input interrupt. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 9 of 98 APPENDIX 7643 Group 3.1 Electrical characteristics In Vcc = 3 V Table 3.1.9 Electrical characteristics (2) (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) Symbol ICC Parameter Power source current (Output transistor is isolated.) Test conditions Normal mode (Note 1) f(XIN) = 24 MHz, φ = 6 MHz USB operating Frequency synthesizer ON Wait mode (Note 2) f(XIN) = 24 MHz, φ = 6 MHz USB block enabled, USB clock stopped, Frequency synthesizer ON Wait mode (Note 3) f(XCIN) = 32 kHz, φ = 16 kHz USB block disabled Frequency synthesizer OFF USB transceiver DC-DC converter OFF Stop mode USB transceiver DC-DC converter OFF Ta = 25 °C Stop mode USB transceiver DC-DC converter OFF Ta = 70 °C Min. Limits Typ. 25 Max. 45 Unit mA 2.5 6 mA 6 µA 1.0 µA 10 µA Notes 1: Operating in single-chip mode Clock input from XIN pin (XOUT oscillator stopped) USB operating with USB transceiver DC-DC converter enabled Operating functions: Frequency synthesizer, CPU, UART, DMAC, Timers Disabled functions: Serial I/O 2: Operating in single-chip mode with Wait mode Clock input from XIN pin (XOUT oscillator stopped) USB suspended due to USB clock stopped with USB transceiver DC-DC converter enabled Operating functions: Frequency synthesizer, Timers Disabled functions: CPU, UART, DMAC and Serial I/O 3: Operating in single-chip mode with Wait mode XIN - XOUT oscillator stopped Clock input from XCIN pin (XCOUT oscillator stopped) USB stopped, USB clock stopped and USB transceiver DC-DC converter disabled Operating functions: Timers Disabled functions: Frequency synthesizer, CPU, UART, DMAC and Serial I/O Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 10 of 98 APPENDIX 7643 Group 3.1 Electrical characteristics 3.1.8 Timing requirements In Vcc = 3 V Table 3.1.10 Timing requirements (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(XCIN) tWH(XCIN) tWL(XCIN) tC(INT) tWH(INT) tWL(INT) td(φ -TOUT) tC(SCLKE) tWH(SCLKE) tWL(SCLKE) tsu(SRXD-SCLKE) th(SCLKE-SRXD) td(SCLKE-STXD) tv(SCLKE-SRDY) tc(SCLKI) tWH(SCLKI) tWL(SCLKI) tsu(SRXD-SCLKI) th(SCLKI-SRXD) td(SCLKI-STXD) Parameter Reset input “L” pulse width Main clock input cycle time (Note) Main clock input “H” pulse width Main clock input “L” pulse width Sub-clock input cycle time Sub-clock input “H” pulse width Sub-clock input “L” pulse width INT0, INT1 input cycle time INT0, INT1 input “H” pulse width INT0, INT1 input “L” pulse width Timer TOUT delay time Serial I/O external clock input cycle time Serial I/O external clock input “H” pulse width Serial I/O external clock input “L” pulse width Serial I/O input setup time (external clock) Serial I/O input hold time (external clock) Serial I/O output delay time (external clock) Serial I/O SRDY valid time (external clock) Serial I/O internal clock output cycle time Serial I/O internal clock output “H” pulse width Serial I/O internal clock output “L” pulse width Serial I/O input setup time (internal clock) Serial I/O input hold time (internal clock) Serial I/O output delay time (internal clock) Min. 2 41.66 0.4•tc(XIN) 0.4•tc(XIN) 200 0.4•tc(XCIN) 0.4•tc(XCIN) 250 110 110 450 220 190 20 15 34 35 300 0.5•tc(SCLKI) – 5 0.5•tc(SCLKI) – 5 20 5 5 Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 17 Note: Make sure not to exceed 6 MHz of φ, in other words, tc(φ) ≥ 166.66 ns). Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 11 of 98 APPENDIX 7643 Group 3.1 Electrical characteristics 3.1.9 Timing requirements and switching characteristics in memory expansion and microprocessor modes ( In Vcc = 3 V ) Table 3.1.11 Timing requirements and switching characteristics in memory expansion and microprocessor modes ( Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = – 20 to 70 ° C, unless otherwise noted) Symbol tC(φ) tWH(φ) tWL(φ) td(φ -AH) tv(φ -AH) td(φ -AL) tv(φ -AL) td(φ -WR) tv(φ -WR) td(φ -RD) tv(φ -RD) td(φ -SYNC) tv(φ -SYNC) td(φ -DMA) tv(φ -DMA) tsu(RDY- φ) th(φ -RDY) tsu(HOLD- φ) th(φ -HOLD) td(φ -HLDAL) td(φ -HLDAH) tsu(DB- φ) th(φ -DB) td(φ -DB) tV(φ -DB) td(φ -EDMA) tv(φ -EDMA) tWL(WR) (Note 2) tWL(RD) (Note 2) td(AH-WR) td(AL-WR) tv(WR-AH) tv(WR-AL) td(AH-RD) td(AL-RD) tv(RD-AH) tv(RD-AL) tsu(RDY-WR) th(WR-RDY) tsu(RDY-RD) th(RD-RDY) tsu(DB-RD) th(RD-DB) td(WR-DB) tv(WR-DB) tv(WR-EDMA) tv(RD-EDMA) tr(D+), tr(D-) tf(D+), tf(D-) Parameter φ clock cycle time φ clock “H” pulse width φ clock “L” pulse width AB15–AB8 delay time AB15–AB8 valid time AB7–AB0 delay time AB7–AB0 valid time WR delay time WR valid time RD delay time RD valid time SYNCOUT delay time SYNCOUT valid time DMAOUT delay time DMAOUT valid time RDY setup time RDY hold time HOLD setup time HOLD hold time HOLD “L” delay time HOLD “H” delay time Data bus setup time Data bus hold time Data bus delay time Data bus valid time (Note 1) EDMA delay time EDMA valid time WR pulse width RD pulse width AB15–AB8 valid time before WR AB7–AB0 valid time before WR AB15–AB8 valid time after WR AB7–AB0 valid time after WR AB15–AB8 valid time before RD AB7–AB0 valid time before RD AB15–AB8 valid time after RD AB7–AB0 valid time after RD RDY setup time before WR RDY hold time after WR RDY setup time before RD RDY hold time after RD Data bus setup time before RD Data bus hold time after RD Data bus delay time after WR Data bus valid time after WR (Note 1) EDMA delay time after WR EDMA valid time after RD USB output rise time, CL = 50 pF USB output fall time, CL = 50 pF Min. 166.66 0.5•tc(φ) – 5 0.5•tc(φ) – 5 0 47 0 8 0 8 0 11 0 26 0 35 0 21 0 30 30 9 0 30 15 15 0 0.5•tc(φ) – 6 0.5•tc(φ) – 6 0.5•tc(φ) – 33 0.5•tc(φ) – 35 0 0 0.5•tc(φ) – 33 0.5•tc(φ) – 35 0 0 45 0 45 0 18 0 28 12 0 0 4 4 Limits Typ. Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 45 20 20 Notes 1: Test conditions: IOHL = ± 5mA, CL = 50 pF 2: twL(RD) = ((n + 0.5) • tc(PHI)) – 5 ns (n = wait number) twL(WR) = ((n + 0.5) • tc(PHI)) – 5 ns (n = wait number) For example, two software waits, PHI = 12 MHz operating: twL(RD) = 2.5 • tc(PHI) – 5 ns = 203.33 ns Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 12 of 98 APPENDIX 7643 Group 3.1 Electrical characteristics Measurement output pin 100 pF Measurement output pin 1 kΩ CMOS output 100 pF Fig. 3.1.1 Circuit for measuring output switching characteristics (1) N-channel open-drain output (Note) Note: This diagram applies when bit 7 of the serial I/O control register 1 is “1”. Fig. 3.1.2 Circuit for measuring output switching characteristics (2) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 13 of 98 APPENDIX 7643 Group 3.1 Electrical characteristics q Timing diagram [Interrupt] tC(INT) tWH(INT) tWL(INT) 0.2VCC INT0, INT1 [Input] RESET 0.8VCC tW(RESET) 0.2VCC 0.8VCC tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC XIN 0.8VCC tC(XCIN) tWH(XCIN) tWL(XCIN) 0.2VCC XCIN 0.8VCC [Timer] φ 0.5VCC td(φ – TOUT) TOUT 0.5VCC Fig. 3.1.3 Timing diagram (1) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 14 of 98 APPENDIX 7643 Group 3.1 Electrical characteristics q Timing diagram [Serial I/O] tC(SCLKE,I) tWL(SCLKE, I) tWH(SCLKE,I) 0.8VCC SCLK 0.2VCC tsu(SRXD – SCLKE, I) th(SCLKE, I – SRXD) SRXD td(SCLKE, I – STXD) 0.8VCC 0.2VCC STXD 0.5VCC tv(SCLKE – SRDY) SRDY 0.8VCC Fig. 3.1.4 Timing diagram (2) tf(D+) tf(D-) tr(D+) tr(D-) 0.9VOH USBD+, USBD- 0.1VOH Fig. 3.1.5 Timing diagram (3) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 15 of 98 APPENDIX 7643 Group 3.1 Electrical characteristics tC(φ) tWH(φ) tWL(φ) φ 0.5VCC td(φ-AH) tv(φ-AH) 0.5VCC td(φ-AL) tv(φ-AL) 0.5VCC td(φ-SYNC) tv(φ-SYNC) AB15 to AB8 AB7 to AB0 SYNCOUT 0.5VCC td(φ-WR) td(φ-RD) 0.5VCC td(φ-DMA) tv(φ-WR) tv(φ-RD) RD,WR tv(φ-DMA) n cycles of φ tsu(RDY-φ) th(φ-RDY) DMAOUT 0.5VCC RDY 0.8VCC 0.2VCC tsu(HOLD-φ) th(φ-HOLD) HOLD (at entering) 0.8VCC 0.2VCC td(φ-HLDAL) HLDA tsu(HOLD-φ) th(φ-HOLD) 0.5VCC HOLD (at releasing) 0.8VCC 0.2VCC td(φ-HLDAH) HLDA tsu(DB-φ) 0.5VCC th(φ-DB) DB0 to DB7 td(φ-DB) 0.8VCC 0.2VCC tv(φ-DB) 0.5VCC td(φ-EDMA) tv(φ-EDMA) 0.5VCC DB0 to DB7 0.5VCC EDMA Fig. 3.1.6 Timing diagram (4); Memory expansion and microprocessor modes Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 16 of 98 APPENDIX 7643 Group 3.1 Electrical characteristics tWL(RD) tWL(WR) RD,WR td(AH-RD) td(AH-WR) 0.5VCC tv(RD-AH) tv(WR-AH) AB15 to AB8 0.5VCC td(AL-RD) td(AL-WR) tv(RD-AL) tv(WR-AL) AB7 to AB0 0.5VCC tsu(RDY-WR) tsu(RDY-RD) th(WR-RDY) th(RD-RDY) RDY 0.8VCC 0.2VCC DB0 to DB7 tSU(DB-RD) 0.8VCC 0.2VCC th(RD-DB) DB0 to DB7 td(WR-DB) 0.5VCC tv(WR-DB) tv(WR-EDMA) tv(RD-EDMA) EDMA 0.5VCC Fig. 3.1.7 Timing diagram (5); Memory expansion and microprocessor modes Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 17 of 98 APPENDIX 7643 Group 3.2 Standard characteristics 3.2 Standard characteristics Standard characteristics described below are just examples of the 7643 Group’s characteristics and are not guaranteed. For rated values, refer to “ 3.1 Electrical characteristics ”. 3.2.1 Power source current standard characteristics Figure 3.2.1 shows power source current standard characteristics. Measuring conditions: Ta = 25 °C, Normal mode, φ = f(XIN)/2, USB operating, frequency synthesizer circuit connecting 60 55 50 45 40 Vcc = 5.25 V Vcc = 5.0 V Icc(mA) 35 30 25 20 15 10 5 0 0 3 6 9 12 15 Xin(MHz) 18 21 24 27 30 Vcc = 4.15 V Vcc = 3.6 V Vcc = 3.3 V Vcc = 3.0 V Fig. 3.2.1 Power source current standard characteristics (Ta = 25 ° C) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 18 of 98 APPENDIX 7643 Group 3.2 Standard characteristics 3.2.2 Port standard characteristics Figure 3.2.2 to Figure 3.2.7 show port standard characteristics. M37643M8 IOH-VOH characteristics CMOS output (P-channel drive) [Ta=25°C] -100 -90 -80 -70 IOH(mA) -60 Vcc = 5.25 V -50 Vcc = 5.0 V -40 -30 -20 -10 0 0 Vcc = 4.15 V Vcc = 3.6 V Vcc = 3.3 V Vcc = 3.0 V 0.6 1.2 1.8 2.4 3 3.6 VOH(V) 4.2 4.8 5.4 6 Fig. 3.2.2 CMOS output port P-channel side characteristics (Ta = 25 °C) M37643M8 IOH-VOH characteristics CMOS output (P-channel drive) [Ta=70°C] -100 -90 -80 -70 IOH(mA) -60 -50 -40 -30 -20 -10 0 0 0.6 1.2 1.8 2.4 3 3.6 VOH(V) 4.2 4.8 5.4 6 Vcc = 5.25 V Vcc = 5.0 V Vcc = 4.15 V Vcc = 3.6 V Vcc = 3.3 V Vcc = 3.0 V Fig. 3.2.3 CMOS output port P-channel side characteristics (Ta = 70 °C) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 19 of 98 APPENDIX 7643 Group 3.2 Standard characteristics M37643M8 IOL-VOL characteristics CMOS output (N-channel drive) [Ta=25°C] 100 90 80 70 IOL(mA) 60 50 40 30 20 10 0 0 0.6 1.2 1.8 2.4 3 VOL(V) 3.6 4.2 4.8 5.4 6 Vcc = 4.15 V Vcc = 3.6 V Vcc = 3.3 V Vcc = 3.0 V Vcc = 5.25 V Vcc = 5.0 V Fig. 3.2.4 CMOS output port N-channel side characteristics (Ta = 25 °C) M37643M8 IOL-VOL characteristics CMOS output (N-channel drive) [Ta=70°C] 100 90 80 70 IOL(mA) 60 50 40 30 20 10 0 0 0.6 1.2 1.8 2.4 3 VOL(V) 3.6 4.2 4.8 5.4 6 Vcc = 4.15 V Vcc = 3.6 V Vcc = 3.3 V Vcc = 3.0 V Vcc = 5.25 V Vcc = 5.0 V Fig. 3.2.5 CMOS output port N-channel side characteristics (Ta = 70 °C) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 20 of 98 APPENDIX 7643 Group 3.2 Standard characteristics M37643M8 Port P20–P27 IIL-VIL characteristics (at pull-up) [Ta=25°C] -100 -90 -80 -70 -60 IIL(µA) Vcc = 5.25 V Vcc = 5.0 V -50 Vcc = 4.15 V -40 Vcc = 3.6 V -30 Vcc = 3.3 V -20 -10 0 0.0 0.6 1.2 1.8 2.4 3.0 3.6 VIL(V) 4.2 4.8 5.4 6.0 Vcc = 3.0 V Fig. 3.2.6 Port P20–P27 at pull-up characteristics (Ta = 25 °C) M37643M8 Port P20–P27 IIL-VIL characteristics (at pull-up) [Ta=70°C] -100 -90 -80 -70 Vcc = 5.25 V -60 IIL(µA) Vcc = 5.0 V -50 -40 -30 -20 -10 0 0.0 0.6 1.2 1.8 2.4 3.0 VIL(V) 3.6 4.2 4.8 5.4 6.0 Vcc = 4.15 V Vcc = 3.6 V Vcc = 3.3 V Vcc = 3.0 V Fig. 3.2.7 Port P20–P27 at pull-up characteristics (Ta = 70 °C) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 21 of 98 APPENDIX 7643 Group 3.3 Notes on use 3.3 Notes on use 3.3.1 Notes on interrupts (1) When setting external interrupt active edge When setting the external interrupt active edge (INT 0, INT1), the interrupt request bit may be set to “ 1 ” . When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. •Interrupt polarity select register (address 0011 16) Set the above listed registers or bits as the following sequence. Set the corresponding interrupt enable bit to “0” (disabled) . ↓ Set the interrupt edge select bit (active edge switch bit) to “1”. ↓ NOP (one or more instructions) ↓ Set the corresponding interrupt request bit to “0” (no interrupt request issued). ↓ Set the corresponding interrupt enable bit to “1” (enabled). Fig. 3.3.1 Sequence of setting external interrupt active edge Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 22 of 98 APPENDIX 7643 Group 3.3 Notes on use 3.3.2 Notes on serial I/O (1) Clock When the external clock (SCLK pin input) is selected as the transfer clock, its transfer clock needs to be controlled by the external source because the serial I/O shift register will keep being shifted while transfer clock is input even after transfer completion. (2) Reception When the external clock (SCLK pin input) is selected as the transfer clock for reception, the receiving operation will start owing to the shift clock input even if write operation to the serial I/ O shift register (SIOSHT) is not performed. The serial I/O interrupt request also occurs at completion of receiving. However, we recommend to write dummy data in the serial I/O shift register. Because this will cause followings and improve transfer reliability. •Write to SIOSHT puts the SRDY pin to “L”. This enables shift clock output of an external device. • Write to SIOSHT clears the internal serial I/O counter. Note : Do not read the serial I/O shift register which is shifting. Because this will cause incorrectdata read. (3) STXD output •When the internal synchronous clock is selected as the transfer clock, the STXD pin goes a highimpedance state after transfer completion. • When the external clock (SCLK pin input) is selected as the transfer clock, the STXD pin does not go a high-impedance state after transfer completion. (4) SPI compatible mode • When using the SPI compatible mode, set the SRDY select bit to “ 1 ” ( SRDY signal output). •When the external clock is selected in SPI compatible mode, the SRXD pin functions as a data output pin and the STXD pin functions as a data input pin. • Do not write to the serial I/O shift register (SIOSHT) during a transfer as slave when in SPI compatible mode. • Master operation of SPI compatible mode requires the timings: -From write operation to the SIOSHT to SRDY pin put to “ L ” Requires 2 cycles of internal clock φ + 2 c ycles of serial I/O synchronous clock + 35 ns -From SRDY pin put to “ L ” t o SCLK switch Requires 35 ns -From the last pulse of SCLK to SRDY pin put to “ H ” Requires 35 ns. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 23 of 98 APPENDIX 7643 Group 3.3 Notes on use 3.3.3 N otes on UART (1) Receive •When any one of errors occurs, the summing error flag is set to “1” and the UART summing error interrupt request bit is also set to “ 1 ” . If a receive error occurs, the reception does not set the UART receive buffer full interrupt request bit to “ 1 ” . •If the receive enable bit (REN) is set to “0” (disabled) while a data is being received, the receiving operation will stop after the data has been received. •Setting the receive initialization bit (RIN) to “1” resets the UART RTS control register (URTS) to “ 80 16” . After setting the RIN bit to “ 1 ” , set this URTS. (2) Transmit • Once the transmission starts, it continues until the last bit has been transmitted even though clearing the transmit enable bit (TEN) to “ 0 ” ( disabled) or inputting “ H ” t o the CTS pin. After completion of the current transmission, the transmission is disabled. •The transmit complete flag (TCM) is changed from “1” to “0” later than 0.5 to 1.5 clocks of the shift clock. Accordingly, take it in consideration to transmit data confirming the TCM flag after the data is written into the transmit buffer register. (3) Register settings •If updating a value of UART baud rate generator while the data is being transmitted or received, be sure to disable the transmission and reception before updating. If the former data remains in the UART transmit buffer registers 1 and 2 at retransmission, an undefined data might be output. • The all error flags PER, FER, OER and SER are cleared to “ 0 ” w hen the UART status register is read, at the hardware reset or initialization by setting the Transmit Initialization Bit. These flags are also cleared to “ 0 ” b y execution of bit test instructions such as B BC a nd B CS . •The transmit buffer empty flag (TBE) is set to “0” when the low-order byte of transmitted data is written into the UART transmit buffer register 1. When using 9-bit character length, set the data into the UART transmit buffer register 2 (high-order byte) first before the UART transmit buffer register 1 (low-order byte). •The receive buffer full flag (RBF) is set to “0” when the contents of UART receive buffer register 1 is read out. When using 9-bit character length, read the data from the UART receive buffer register 2 (high-order byte) first before the UART receive buffer register 1 (low-order byte). • If a character bit length is 7 bits, bit 7 of the UART transmit/receive buffer register 1 and bits 0 to 7 of the UART transmit/receive buffer register 2 are ignored at transmitting; they are invalid at receiving. If a character bit length is 8 bits, bits 0 to 7 of the UART transmit/receive buffer register 2 are ignored at transmitting; they are invalid at receiving. If a character bit length is 9 bits, bits 1 to 7 of the UART transmit/receive buffer register 2 are ignored at transmitting; they are “ 0 ” a t receiving. • The reset cannot affect the contents of baud rate generator. (4) UART address mode •When the MSB of the incoming data is “0” in the UART address mode, the receive buffer full flag (RBF) is set to “ 1 ” , but the receive buffer full interrupt request bit is not set to “ 1 ” . •An overrun error cannot be detected after the first data has been received in UART address mode. •The UART address mode can be used in either an 8-bit or 9-bit character length. 7-bit character length cannot be used. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 24 of 98 APPENDIX 7643 Group 3.3 Notes on use (5) Receive error flag The all error flags PER, FER, OER and SER are cleared to “ 0 ” w hen the UART status register is read, at the hardware reset or initialization by setting the Transmit Initialization Bit. Accordingly, note that these flags are also cleared to “0” by execution of bit test instructions such as BBC and BBS, not only LDA. (6) CTS function When the CTS function is enabled, the transmitted data is not transferred to the transmit shift register until “L” is input to the CTS pin (P8 6/CTS). As the result, do not set the following data to the transmit buffer register. (7) RTS function • If the start bit is detected in the term of “ H ” a ssertion of RTS, its assertion count is suspended and the RTS pin remains “ H ” o utput. After receiving the last stop bit, the count is resumed. •Setting the receive initialization bit (RIN) to “1” resets the UART RTS control register (URTS) to “ 80 16” . After setting the RIN bit to “ 1 ” , set this URTS. (8) Interrupt •When setting the transmit initialization bit (TIN) to “1”, both the transmit buffer empty flag (TBE) and the transmit complete flag (TCM) are set to “1”, so that the transmit interrupt request occurs independent of its interrupt source. After setting the transmit initialization bit (TIN) to “ 1 ” , clear the transmit interrupt request bit to “ 0 ” b efore setting the transmit enable bit (TEN) to “ 1 ” . • The transmit interrupt request bit is set and the interrupt request is generated by setting the transmit enable bit (TIN) to “1” even when selecting timing that either of the following flags is set to “ 1 ” a s timing where the transmission interrupt is generated: (1) Transmit buffer empty flag is set to “ 1 ” (2) Transmit complete flag is set to “ 1 ” . Therefore, when the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as the following sequence: (1) Transmit enable bit is set to “ 1 ” (2) Transmit interrupt request bit is set to “ 0 ” (3) Transmit interrupt enable bit is set to “ 1 ” . Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 25 of 98 APPENDIX 7643 Group 3.3 Notes on use 3.3.4 N otes on DMAC (1) Transfer time • One-byte data transfer requires 2 cycles of φ ( read and write cycles). •To perform DMAC transfer due to the different transfer requests on the same DMAC channel or DMAC transfer between both DMAC channels, 1 cycle of φ o r more is needed before transfer is started. (2) Priority • The DMAC places a higher priority on channel-0 transfer requests than on channel-1 transfer requests. If a channel-0 transfer request occurs during a channel-1 burst transfer operation, the DMAC completes the next transfer source and destination read/write operation first, and then stops the channel-1 transfer operation. The channel-1 transfer operation which has been suspended is automatically resumed from the point where it was suspended so that channel-1 transfer can complete its one-burst transfer unit. This will be performed even if another channel-0 transfer request occurs. • The suspended transfer due to the interrupt can also be resumed during its interrupt process routine by writing “ 1 ” t o the DMAC channel x enable bit (DxCEN). (3) Related registers •A read/write must be performed to the source registers, transfer destination registers and transfer count registers as follows: Read from each higher byte first, then the lower byte Write to each lower byte first, then the higher byte. Note that if the lower byte is read out first, the values are the higher byte ’ s. • Do not access the DMAC-related registers by using a DMAC transfer. The destination address data and the source address data will collide in the DMAC internal bus. •When setting the DMAC channel x enable bit (bit 7 of address 41 16) to “1”, be sure simultaneously to set the DMAC channel x transfer initiation source capture register reset bit (bit 6 of address 41 16) to “ 1 ” . If this is not performed, an incorrect data will be transferred at the same time when the DMAC is enabled. (4) DMA OUT p in In the memory expansion mode and microprocessor mode, the DMA OUT pin (P3 3/DMAOUT) outputs “ H ” d uring a DMA transfer. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 26 of 98 APPENDIX 7643 Group 3.3 Notes on use 3.3.5 N otes on USB (1) USB reception •When the OUT FIFO contains 2-data packets in the endpoints 1 to 2 used, one-data packet will still remain in the OUT FIFO even after the data of the OUT max. packet size has been read. In this case the OUT_PKT_RDY flag is not cleared even if it is set to “0”. (The flag returns from “ 0 ” t o “ 1 ” 8 3 ns later (Vcc = 5 V, f(X IN) = 24 MHz) than the clearing.) • Read one packet data from the OUT FIFO before clearing the OUT_PKT_RDY flag. If the OUT_PKT_RDY flag is cleared while one-data packet is being read, the internal read pointer cannot operate normally. (2) USB transmission • The IN FIFO status can be checked by monitoring the IN_PKT_RDY bit and the TX_NOT_EPT flag. • When NULL packet transmission is required in the endpoints 1 to 2 used, perform it under the conditions of the IN_PKT_RDY bit set to “ 1 ” a nd no data in FIFO. (3) External circuit •Connect a capacitor between the Ext. Cap. pin and the Vss pin. The capacitor should have a 2.2 µF capacitor (Tantalum capacitor) and a 0.1 µF capacitor (ceramic capacitor) connected in parallel. Additionally, connect a 1.5 k Ω ( ± 5 % ) resistor between the Ext. Cap. pin and the D+ pin. •The Full-Speed USB 2.0 requires a driver -impedance 28 to 44 Ω. (Refer to Clause 7.1.1.1 Fullspeed (12 Mb/s) Driver Characteristics in the USB specification.) In order to meet the USB specification impedance requirements, connect a resistor (27 to 33 Ω recommended) in series to the USB D+ pin and the USB D- pin. In addition, in order to reduce the ringing and control the falling/rising timing of USB D+/D- and a crossover point, connect a capacitor between the USB D+/D- pins and the Vss pin if necessary. The values and structure of those peripheral elements depend on the impedance characteristics and the layout of the printed circuit board. Accordingly, evaluate your system and observe waveforms before actual use and decide use of elements and the values of resistors and capacitors. Figure 3.3.2 shows the circuit example for the proper positions of the peripheral components. • In Vcc = 3.3 V operation, connect the Ext. Cap. pin directly to the Vcc pin in order to supply power to the USB transceiver. In addition, you will need to disable the DC-DC converter in this operation (set bit 4 of the USB control register to “0”.) If you are using the bus powered supply in Vcc = 3.3 V operation, the DC-DC converter must be placed outside the MCU. • In Vcc = 5 V operation, do not connect the external DC-DC converter to the Ext. Cap. pin. Use the built-in DC-DC converter by enabling the USB line driver. •Make sure the USB D+/D- lines do not cross any other wires. Keep a large GND area to protect the USB lines. Also, make sure you use a USB specification compliant connecter for the connection. •All passive components must be located as close as possible to the LPF pin. Figure. 3.3.3 shows the passive components near LPF pin • An insulation connector (Ferrite Beads) must be connected between AVss and Vss pins and between AVcc and Vcc pins. (See Figure 3.3.4.) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 27 of 98 APPENDIX 7643 Group 3.3 Notes on use M37643 USBC5 enable enable FSE LS USBC4 USBC3 Ext. Cap. Note 1 XIN Frequency Synthesizer DC-DC converter current mode enable lock USB Clock (48 MHz) USB FCU enable USB transceiver D+ enable See the circuit example below. USBC7 USBC7 D- (1) Vcc = 5 V (Using built-in DC-DC converter) 5V M37643 Vcc Ext. Cap. 2.2 µF 0.1 µF 1.5 kΩ (2) Vcc = 3.3 V (Not using built-in DC-DC converter) 3.3 V M37643 Vcc Ext. Cap. 2.2 µF 0.1 µF 1.5 kΩ AVcc C2 Vcc D+ DNote 2 D+ DNote 2 Notes 1: In Vcc = 3.3 V, connect to Vcc. In Vcc =5 V, do not connect the external DC-DC converter to the Ext. Cap pin. 2: The resistors values depend on the layout of the printed circuit board. Fig. 3.3.2 Circuit example for the proper positions of the peripheral components Ferrite Beads LPF pin Vcc 1 kΩ 680 pF C3 C1 C4 0.1 µF AVSS pin Vss Decoupling Capacitors AVss •Capacitor C1, C2: 0.1 µF C3, C4: 4.7 µF Fig. 3.3.3 Passive components near LPF pin Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 28 of 98 Fig. 3.3.4 Insulation connector connection APPENDIX 7643 Group 3.3 Notes on use (4) USB Communication •In applications requiring high-reliability, we recommend providing the system with protective measures such as USB function initialization by software or USB reset by the host to prevent USB communication from being terminated unexpectedly, for example due to external causes such as noise. (5) Registers and bits •When using the endpoint 0, use the USB endpoint 0 IN max. packet size register for transmission and reception (IN packet size and OUT packet size). •When not using the USB endpoint x (x = 0 to 2) IN max. packet size register and USB endpoint x OUT max. packet size register, set them to “0”. •To write to/read from the USB interrupt status registers 1 and 2, perform it for the USB interrupt status register 1 first and then the register 2. •Make sure the index indicated by the USB endpoint index register is correct when accessing the registers: USB endpoint x (x = 0 to 2) IN control register, USB endpoint x OUT control register, USB endpoint x IN max. packet size register, USB endpoint x OUT max. packet size register, USB endpoint x (x = 0 to 2) OUT write count registers Low and High, USB endpoint FIFO mode register. •When the USB reset interrupt status flag is kept at “1”, all other flags in the USB internal registers (addresses 005016 to 005F16) will return to their reset status. However, the following registers are not affected by the USB reset: USB control register (address 0013 16), Frequency synthesizer control register (address 006C 16), Clock control register (address 001F 16), and USB endpoint x FIFO register (addresses 0060 16 t o 0062 16). •When not using the USB function, set the USB line driver supply enable bit of the USB control register (address 0013 16 ) to “1” for power supply to the internal circuits (at Vcc = 5 V). •The IN_PKT_RDY Bit can be set by software even when using the AUTO_SET function. •Do not write to USB-related registers (addresses 0050 16 t o 0062 16) except the USBC, CCR and FSC until the USB clock is enabled. •When the MCU is in the USB-suspend state, the USB enable bit is kept “1”; the USB block is enabled. To write to USB-related registers (addresses 005016 to 006216) except the USBC, CCR and FSC after returning from the USB-suspend state; after enabling the USB clock, wait for 4 or more φ c ycles and then set those registers. •When using the MCU at Vcc = 3.3V, set the USB line driver supply enable bit to “0” (line driver disable). Note that setting the USB line driver current control bit (USBC3) doesn’t affect the USB operation. •Setting the FLUSH bit to “1” eliminates the data in IN FIFO and OUT FIFO. If there are 2 or moredata packets in them, the oldest data is eliminated. The FLUSH bit setting also affects the IN_PKT_RDY bit or the OUT_PKT_RDY flag. •If the FLUSH bit is set to “1” while transmission/reception is being performed, the data might be corrupted. When receiving, setting the FLUSH bit must be done while the OUT_PKT_RDY flag is “1”. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 29 of 98 APPENDIX 7643 Group 3.3 Notes on use • Use the transfer instructions such as L DA a nd S TA t o set the registers: USB interrupt status registers 1, 2 (addresses 0052 16, 0053 16); USB endpoint 0 IN control register (address 0059 16); USB endpoint x IN control register (address 005916); USB endpoint x OUT control register (address 005A 16). Do not use the read-modify-write instructions such as the S EB o r the C LB i nstruction. When writing to bits shown by Table 32 using the transfer instruction such as L DA o r S TA , a value which never affect its bit state is required. Take the following sequence to change these bits contents: (1) Store the register contents onto a variable or a data register. (2) Change the target bit on the variable or the data register. Simultaneously mask the bit so that its bit state cannot be changed. (See to Table 3.3.1.) (3) Write the value from the variable or the data register to the register using the transfer instruction such as L DA o r S TA. • To use the AUTO_SET function for an IN transfer when the AUTO_SET bit is set to 1, set the FIFO to single buffer mode. Table 3.3.1 Bits of which state might be changed owing to software write Register name USB endpoint 0 IN control register Bit name IN_PKT_RDY (b1) DATA_END (b3) FORCE_STALL (b4) IN_PKT_RDY (b0) OUT_PKT_RDY (b0) FORCE_STALL (b4) Value not affecting state (Note) “0” “0” “1” “0” “1” “1” USB endpoint x (x = 1 to 2) IN control register USB endpoint x (x = 1 to 2) OUT control register Note: Writing this value will not change the bit state, because this value cannot be written to the bit by software. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 30 of 98 APPENDIX 7643 Group 3.3 Notes on use 3.3.6 N otes on frequency synthesizer • Bits 6 and 5 of the frequency synthesizer control register (address 006C 16) are initialized to (b6, b5) = “ 11 ” a fter reset release. Make sure to set bits 6 and 5 to “ 10 ” a fter the frequency synthesizer lock status bit goes to “ 1 ” . •Use the frequency synthesizer output clocks 2 ms to 5 ms later than setting the frequency synthesizer enable bit to “1” (enabled). After that do not change any register values because it might cause output clocks unstabilized temporarily. • Make sure to connect a low-pulse filter to the LPF pin when using the frequency synthesizer. • The frequency synthesizer divide register set value never affects f USB f requency. •When using the fSYN as an internal system clock, set the frequency synthesizer divide register so that f SYN c ould be 24 MHz or less. • When using the frequency synthesized clock function, we recommend using the fastest frequency possible of f(X IN) or f(XCIN) as an input clock for the PLL. • Set the value of frequency synthesizer multiply register 2 (FSM2) so that the f PIN i s 1 MHZ or higher. 3.3.7 N otes on external devices connection (1) Rewrite port P3 latch In both memory expansion mode and microprocessor mode, ports P3 1 a nd P3 2 c an be used as output ports. We recommend to use the L DM i nstruction or S TA i nstruction to write to port P3 register (address 000E16). If using the Read-Modify-Write instruction (SEB instruction, CLB instruction) you will need to map a memory that the CPU can read from and write to. [Reason] The access to address 000E16 i s performed: • Read from external memory • Write to both port P3 latch and external memory. It is because address 000E16 is assigned on an external area In the memory expansion mode and microprocessor mode. Accordingly, if a Read-Modify-Write instruction is executed to address 000E16, the external memory contents is read out and after its modification it will be written into both port P3 latch and an external memory. As a result, if an external memory is not allocated in address 000E16 then, the MCU will read an undefined value and write its modified value into the port P3 latch. Therefore port P3 latch value will become undefined. (2) overlap of internal and external memories In the memory expansion mode, if the internal and external memory areas overlap, the internal memory becomes the valid memory for the overlapping area. When the CPU performs a read or a write operation on this overlapped area, the following things happen: •Read The CPU reads out the data in the internal memory instead of in the external memory. Note that, since the CPU will output a proper read signal, address signal, etc., the memory data at the respective address will appear on the external data bus. •Write The CPU writes data to both the internal and external memories. _____ ______ (3) RD, WR pins In the memory expansion mode or microprocessor mode, a read-out control signal is output from ______ ______ the RD pin (P36), and a write-in control signal is ______ output from the WR pin (P3 7). “L” level is output ______ from the RD pin at CPU read-out and from the WR pin at CPU write-in. These signals function for internal access and external access. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 31 of 98 APPENDIX 7643 Group 3.3 Notes on use (4) RDY function When using RDY function in usual connection, it does not operate at 12 MHz of φ o r faster. [Reason] td( φ -AH) + tsu(RDY- φ ) = 31 ns (max.) + 21 ns (min.) = 52 ns. twh ( φ ), twl ( φ ) = 0.5 ✕ 8 3.33 – 5 = 3 6.665 ns Therefore, it becomes 52 ns > 36.665 ns, so that the timing to enter RDY wait does not match. ________ However, if the timings can match owing to RDY pin by “L” fixation and others, the RDY function can be used even at φ = 1 2 MHz. In this situation the slow memory wait always functions. (5) Wait function The Wait function is serviceable at accessing an external memory in the memory expansion mode and microprocessor mode. However, in these modes even if an external memory is assigned to addresses 0008 16 t o 000F 16, the Wait function cannot function to these areas. (6) Processor mode switch Note when the processor mode is switched by setting of the processor mode bits (b1, b0 of CPMA), that will immediately switch the accessible memory from external to internal or from internal to external. If this is done, the first cycle of the next instruction will be operated from the accidental memory. To prevent this problem, follow the procedure below: (a) Duplicate the next instruction at the same address both in internal and external memories. (b) Switch from single-chip mode to memory expansion mode, jump to external memory, and then switch from memory expansion mode to microprocessor mode. (Because in general, the problem will not occur when switching the modes as long as the same memory is accessed after the switch. (c) Load a simple program in RAM that switches the modes, jump to RAM and execute the program, then jump to the location of the code to run after the processor mode has switched. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 32 of 98 APPENDIX 7643 Group 3.3 Notes on use 3.3.8 Notes on timer (1) Read/Write for timer • The timer division ratio is : 1 / (n + 1) (n = “ 0 ” t o “ 255 ” w ritten into the timer) • When the value is loaded only in the latch, the value is loaded in the timer at the count pulse following the count where the timer reaches “ 00 16” . • In the timers 1 to 3, switching of the count sources of timers 1 to 3 does not affect the values of reload latches. However, that may make count operation started. Therefore, write values again in the order of timers 1, 2 and then timer 3 after their count sources have been switched. • The timer current count value can be read out by reading the timer. (2) Pulse output • When using the T OUT o utput of timer 1 or timer 2, set bit 1 of port P5 direction register to “ 1 ” (output mode). • The T OUT o utput pin is shared with the XCOUT p in. Accordingly, when using f(XCIN)/2 as the timer 1 count source (bit 2 of timer 123 mode register = “0”), X COUT oscillation drive must be disabled (bit 5 of clock control register = “ 1 ” ) to input clocks from the X CIN p in. •The P51/XCOUT/TOUT pin cannot function as an ordinary I/O port while XCIN-XCOUT is oscillating. When XCIN-XCOUT oscillation is stopped or XCOUT oscillation drive is disabled, this can be used as the TOUT output pin of timer 1 or 2. (3) At STP instruction executed When the STP instruction is executed or Reset occurs, the timer 1 is set to “FF16” and the internal clock φ divided by 8 is automatically selected as its count source. Additionally, the timer 2 is set to “ 01 16” a nd the timer 1 ’ s output is automatically selected as its count source. When the S TP instruction is being executed, all bits except bit 4 of the timer 123 mode register (address 002916) are initialized to “ 0 ” . It is not necessary to set T123M1 (timer 1 count stop bit) to “ 0 ” b efore executing the STP instruction. After returning from Stop mode, reset the timer 1 (address 002416), timer 2 (address 002516), and the timer 123 mode register (address 0029 16). 3.3.9 Notes on Stop mode • When the STP instruction is executed, bit 7 of the clock control register (address 001F 16) goes to “ 0 ” . To return from stop mode, reset CCR7 to “ 1 ” . •When using fSYN (set internal system clock select bit (CPMA6) to “1”) as the internal system clock, switch CPMA6 to “ 0 ” b efore executing the S TP i nstruction. Reset CPMA6 after the system returns from Stop Mode and the frequency synthesizer has stabilized. CPMA6 does not need to be switched to “ 0 ” w hen using the W IT i nstruction. •When the STP instruction is executed or Reset occurs, the timer 1 is set to “FF16” and the internal clock φ divided by 8 is automatically selected as its count source. Additionally, the timer 2 is set to “ 01 16” a nd the timer 1 ’ s output is automatically selected as its count source. When the S TP instruction is being executed, all bits except bit 4 of the timer 123 mode register (address 0029 16) are initialized to “ 0 ” . It is not necessary to set T123M1 (timer 1 count stop bit) to “ 0 ” b efore executing the STP instruction. After returning from Stop mode, reset the timer 1 (address 002416), timer 2 (address 0025 16), and the timer 123 mode register (address 002916). Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 33 of 98 APPENDIX 7643 Group 3.3 Notes on use 3.3.10 Notes on reset (1) Connecting capacitor In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the V SS pin. Use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following : • M ake the length of the wiring which is connected to a capacitor as short as possible. • B e sure to verify the operation of application products on the user side. q R eason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may cause a microcomputer failure. 3.3.11 Notes on I/O port (1) Notes in standby state In standby state✽1 for low-power dissipation, do not make input levels of an I/O port “undefined”. Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor. When determining a resistance value, note the following points: • E xternal circuit • V ariation of output levels during the ordinary operation When using built-in pull-up resistor, note on varied current values: • W hen setting as an input port : Fix its input level • When setting as an output port : Prevent current from flowing out to external q Reason The potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an I/O port are “ undefined ” . This may cause power source current. ✽ 1 standby state: stop mode by executing S TP i nstruction wait mode by executing W IT i nstruction (2) Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction✽2, the value of the unspecified bit may be changed. q R eason The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an I/O port, the following is executed to all bits of the port latch. • As for bit which is set for input port: The pin state is read in the CPU, and is written to this bit after bit managing. • As for bit which is set for output port: The bit value is read in the CPU, and is written to this bit after bit managing. Note the following: •Even when a port which is set as an output port is changed for an input port, its port latch holds the output data. •As for a bit of which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. ✽ 2 Bit managing instructions: S EB a nd C LB i nstructions Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 34 of 98 APPENDIX 7643 Group 3.3 Notes on use (3) Pull-up control When using port P2, which includes a pull-up resistor, as an output port, its port pull-up control is invalidated, that is, pull-up cannot be enabled. q R eason Pull-up/pull-down control is valid only when each direction register is set to the input mode. 3.3.12 Notes on programming (1) Processor status register ➀ Initializing of processor status register Flags which affect program execution must be initialized after a reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations. q Reason After a reset, the contents of the processor status register (PS) are undefined except for the I flag which is “ 1 ” . Reset ↓ Initializing of flags ↓ Main program Fig. 3.3.5 Initialization of processor status register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 35 of 98 APPENDIX 7643 Group 3.3 Notes on use ➁ How to reference the processor status register To reference the contents of the processor status register (PS), execute the P HP i nstruction once then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its original status. A N OP i nstruction should be executed after every P LP i nstruction. Be sure to execute the SEI instruction before the PLP instruction. If executing the CLI instruction, do it after the N OP i nstruction PLP instruction execution ↓ NOP (S) (S)+1 Stored PS Fig. 3.3.6 Sequence of PLP instruction execution Fig. 3.3.7 Stack memory contents after PHP instruction execution (2) BRK Instruction It can be detected that the B RK i nstruction interrupt event or the least priority interrupt event by referring the stored B flag state. Refer to the stored B flag state in the interrupt routine. (3) Decimal Calculations When decimal mode is selected, the values of the V flags are invalid. The carry flag (C) is set to “ 1 ” i f a carry is generated as a result of the calculation, or is cleared to “ 0 ” i f a borrow is generated. To determine whether a calculation has generated a carry, the C flag must be initialized to “ 0 ” b efore each calculation. To check for a borrow, the C flag must be initialized to “ 1 ” b efore each calculation. (4) Multiplication and Division Instructions The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. (5) Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock φ b y the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 36 of 98 APPENDIX 7643 Group 3.3 Notes on use 3.3.13 Termination of unused pins (1) Terminate unused pins ➀ I /O ports : • S et the I/O ports for the input mode and connect them to V CC o r V SS t hrough each resistor of 1 k Ω t o 10 k Ω . Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/O ports for the output mode and open them at “ L ” o r “ H ” . • When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. • S ince the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. (2) Termination remarks ➀ I /O ports : Do not open in the input mode. q R eason • T he power source current may increase depending on the first-stage circuit. • An effect due to noise may be easily produced as compared with proper termination ➁ and shown on the above. ➁ I /O ports : When setting for the input mode, do not connect to V CC o r V SS d irectly. q R eason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and V CC ( or V SS ). ➂ I /O ports : When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through a resistor. q R eason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. • A t the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 37 of 98 APPENDIX 7643 Group 3.3 Notes on use 3.3.14 Notes on CPU rewrite mode for flash memory version The below notes applies when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the internal clock φ to 6 MHz or less using the XIN divider select bit (bit 7 of address 001F 16). (2) Instructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during CPU rewrite mode . (3) Interrupts inhibited against use The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. (4) Reset Reset is always valid. When CNVSS i s “ H ” a t reset release, the program starts from the address stored in addresses FFFA16 and FFFB16 of the boot ROM area in order that CPU may start in boot mode. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 38 of 98 APPENDIX 7643 Group 3.4 Countermeasure against noise 3.4 Countermeasures against noise Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 3.4.1 Shortest wiring length The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm). q Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise Reset circuit VSS N.G. RESET VSS Reset circuit VSS RESET VSS O.K. Fig. 3.4.1 Wiring for the RESET pin (2) Wiring for clock input/output pins • Make the length of wiring which is connected to clock I/O pins as short as possible. • Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the V SS p in of a microcomputer as short as possible. • Separate the VSS p attern only for oscillation from other VSS p atterns. q Reason If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. Noise XIN XOUT VSS N.G. XIN XOUT VSS O.K. Fig. 3.4.2 Wiring for clock I/O pins Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 39 of 98 APPENDIX 7643 Group 3.4 Countermeasure against noise 3.4.2 Connection of bypass capacitor across V SS l ine and V CC line Connect an approximately 0.1 µ F bypass capacitor across the V SS l ine and the V CC l ine as follows: • C onnect a bypass capacitor across the V SS p in and the VCC p in at equal length. • C onnect a bypass capacitor across the V SS p in and the V CC p in with the shortest possible wiring. • U se lines with a larger diameter than other signal lines for V SS l ine and V CC l ine. • C onnect the power source wiring via a bypass capacitor to the V SS p in and the V CC p in. In use of the 7643 group it is recommended to connect 0.1 µF and 4.7 µF capacitors in parallel between pins Vcc and Vss, and pins AVss and AVcc. However, their capacitors must not be allocated near the LPF pin. VCC VCC VSS VSS N.G. O.K. VSS (AVSS) 4.7 µS 0.1 µS VCC (AVCC) Fig. 3.4.3 Bypass capacitor across the V SS l ine and the V CC l ine Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 40 of 98 APPENDIX 7643 Group 3.4 Countermeasure against noise 3.4.3 Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. q Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. Microcomputer Mutual inductance M Large current GND XIN XOUT VSS Fig. 3.4.4 Wiring for a large current signal line (2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. q Reason Signal lines where potential levels change frequently (such as the T OUT p in signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. N.G. Do not cross TOUT XIN XOUT VSS Fig. 3.4.5 Wiring for signal lines where potential levels change frequently Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 41 of 98 APPENDIX 7643 Group 3.4 Countermeasure against noise (3) Oscillator protection using VSS p attern As for a two-sided printed circuit board, print a V SS p attern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the VSS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides, separate this V SS p attern from other V SS p atterns. An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example XIN XOUT VSS Separate the VSS line for oscillation from other VSS lines Fig. 3.4.6 V SS p attern on the underside of an oscillator 3.4.4 Setup for I/O ports Setup I/O ports using hardware and software as follows: • C onnect a resistor of 100 Ω o r more to an I/O port in series. • As for an input port, read data several times by a program for checking whether input levels are equal or not. • A s for an output port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods. • R ewrite data to direction registers at fixed periods. Note: When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise pulse. O.K. Noise Data bus Direction register N.G. Port latch I/O port pins Noise Fig. 3.4.7 Setup for I/O ports Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 42 of 98 APPENDIX 7643 Group 3.4 Countermeasure against noise 3.4.5 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. • Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N+1 ≥ ( Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. • W atches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set. • Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents do not change after interrupt processing. • D ecrements the SWDT contents by 1 at each interrupt processing. • Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count). • Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less. Main routine (SWDT) ← N CLI Main processing ≠N (SWDT) =N? N Interrupt processing routine (SWDT) ← (SWDT)—1 Interrupt processing >0 RTI Return Main routine errors (SWDT) ≤0? ≤0 Interrupt processing routine errors Fig. 3.4.8 Watchdog timer by software Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 43 of 98 APPENDIX 7643 Group 3.5 Control registers 3.5 Control registers CPU mode register A b7 b6 b5 b4 b3 b2 b1 b0 1 CPU mode register A (CPMA : address 0016) b Name b1b0 Functions At reset R W 0 0 1 1 0 Processor mode bits 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 1 0 : Microprocessor mode (Note 1) 1 1 : Not available 2 Stack page select bit 0 : Page 0 1 : Page 1 3 Nothing is arranged for this bit. Fix this bit to “1”. 4 Sub-clock (XCIN-XCOUT) stop bit 5 Main clock (XIN-XOUT) stop bit Internal system clock 6 select bit (Note 2) 7 External clock select bit 0 0 : Stopped 1 : Oscillating 0 : Oscillating 0 1 : Stopped 0 0 : External clock (XIN-XOUT or XCIN-XCOUT) 1 : fsyn 0 0 : XIN-XOUT 1 : XCIN-XCOUT Notes 1: This is not available in the flash memory version. 2: When (CPMA 7, 6) = (0, 0), the internal system clock can be selected between f(XIN) and f(XIN)/2 by CCR7. The internal clock φ is the internal system clock divided by 2. Fig. 3.5.1 Structure of CPU mode register A CPU mode register B b7 b6 b5 b4 b3 b2 b1 b0 10 CPU mode register B (CPMB : address 0116) b Name b1b0 Functions 0 0 : No wait 0 1 : One-time wait 1 0 : Two-time wait 1 1 : Three-time wait b3b2 At reset R W 1 1 0 0 0 Slow memory wait select bits 1 2 Slow memory wait mode select bits 3 0 0 : Software wait 0 1 : Not available 1 0 : RDY wait 1 1 : Software wait plus RDY input anytime wait 0 : EDMA output disabled 1 : EDMA output enabled 0 : HOLD function disabled 1 : HOLD function enabled 6 Nothing is arranged for this bit. Fix this bit to “0”. 7 Nothing is arranged for this bit. Fix this bit to “1”. 4 Expanded data memory access bit 5 HOLD function enable bit 0 0 0 1 Fig. 3.5.2 Structure of CPU mode register B Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 44 of 98 APPENDIX 7643 Group 3.5 Control registers Interrupt request register A b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register A (IREQA : address 0216) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 ✽ ✽ ✽ ✽ ✽ ✽ ✽ 0 USB function interrupt request bit 1 Nothing is arranged for this bit. When this bit is read out, the contents are undefined. This bit is “0” at write. 0 : No interrupt request issued 2 INT0 interrupt request bit 1 : Interrupt request issued 3 INT1 interrupt request bit 4 DMAC0 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 5 DMAC1 interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit 0 : No interrupt request issued 6 UART receive buffer full 1 : Interrupt request issued interrupt request bit UART transmit interrupt 0 : No interrupt request issued 7 request bit 1 : Interrupt request issued ✽: “0” can be set by software, but “1” cannot be set. Fig. 3.5.3 Structure of Interrupt request register A Interrupt request register B b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register B (IREQB : address 0316) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 ✽ 0 UART summing error interrupt request bit 1 2 3 4 5 6 Nothing is arranged for these bits. When these bits are read out, the contents are undefined. These bits are “0” at write. 0 : No interrupt request issued Timer 1 interrupt request 1 : Interrupt request issued bit Timer 2 interrupt request 0 : No interrupt request issued 7 bit 1 : Interrupt request issued ✽: “0” can be set by software, but “1” cannot be set. ✽ ✽ Fig. 3.5.4 Structure of Interrupt request register B Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 45 of 98 APPENDIX 7643 Group 3.5 Control registers Interrupt request register C b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register C (IREQC : address 0416) b Name Functions 0 : No interrupt request issued 1 : Interrupt request issued At reset R W 0 0 0 0 0 0 0 0 ✽ ✽ ✽ 0 Timer 3 interrupt request bit 1 Nothing is arranged for these bits. When these bits are read out, the contents are undefined. 2 These bits are “0” at write. 3 Serial I/O interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit 4 Nothing is arranged for these bits. When these bits are read out, the contents are undefined. 5 These bits are “0” at write. 6 Key input interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit 7 Nothing is arranged for this bit. Fix this bit to “0”. ✽: “0” can be set by software, but “1” cannot be set. Fig. 3.5.5 Structure of Interrupt request register C Interrupt control register A b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt control register A (ICONA : address 0516) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 0 0 0 0 0 0 USB function interrupt enable bit 1 Nothing is arranged for this bit. Fix this bit to “0”. 0 : Interrupt disabled 2 INT0 interrupt enable bit 1 : Interrupt enabled 3 INT1 interrupt enable bit 4 DMAC0 interrupt enable bit 5 DMAC1 interrupt enable bit 6 UART receive buffer full interrupt enable bit 7 UART transmit interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Fig. 3.5.6 Structure of Interrupt control register A Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 46 of 98 APPENDIX 7643 Group 3.5 Control registers Interrupt control register B b7 b6 b5 b4 b3 b2 b1 b0 00000 Interrupt control register B (ICONB : address 0616) b Name Functions 0 : Interrupt disabled 1 : Interrupt enabled At reset R W 0 0 0 0 0 0 0 0 0 UART summing error interrupt enable bit 1 Nothing is arranged for these bits. 2 Fix these bits to “0”. 3 4 5 6 Timer 1 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 7 Timer 2 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled Fig. 3.5.7 Structure of Interrupt control register B Interrupt control register C b7 b6 b5 b4 b3 b2 b1 b0 0 00 00 Interrupt control register C (ICONC : address 0716) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 Timer 3 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 1 Nothing is arranged for these bits. 2 Fix these bits to “0”. 3 Serial I/O interrupt enable 0 : Interrupt disabled 1 : Interrupt enabled bit 4 Nothing is arranged for these bits. 5 Fix these bits to “0”. 6 Key input interrupt enable 0 : Interrupt disabled 1 : Interrupt enabled bit 7 Nothing is arranged for this bit. Fix this bit to “0”. Fig. 3.5.8 Structure of Interrupt control register C Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 47 of 98 APPENDIX 7643 Group 3.5 Control registers Port Pi b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (i = 0, 1, 2, 3, 5, 6, 8) (Pi : addresses 0816, 0A16, 0C16, 0E16, 1616, 1416, 1C16) b 0 Port Pi0 1 Port Pi1 2 Port Pi2 3 Port Pi3 4 Port Pi4 5 Port Pi5 6 Port Pi6 7 Port Pi7 Name Functions qIn output mode Write •••••••• Port latch Read •••••••• Port latch qIn input mode Write •••••••• Port latch Read •••••••• Value of pin At reset R W 0 0 0 0 0 0 0 0 Fig. 3.5.9 Structure of Port Pi Port P4, Port P7 b7 b6 b5 b4 b3 b2 b1 b0 Port P4, Port P7 (P4, P7 : addresses 1816, 1A16) b Name Functions qIn output mode Write •••••••• Port latch Read •••••••• Port latch qIn input mode Write •••••••• Port latch Read •••••••• Value of pin At reset R W 0 0 0 0 0 Undefined ✕ ✕ Undefined ✕ ✕ Undefined ✕ ✕ 0 Port P40 or Port P70 1 Port P41 or Port P71 2 Port P42 or Port P72 3 Port P43 or Port P73 4 Port P44 or Port P74 5 Nothing is arranged for these bits. 6 When these bits are read out, the contents are undefined. 7 Fig. 3.5.10 Structure of Port P4, Port P7 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 48 of 98 APPENDIX 7643 Group 3.5 Control registers Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (i = 0, 1, 2, 3, 5, 6, 8) (PiD : addresses 0916, 0B16, 0D16, 0F16, 1716, 1516, 1D16) b Name Functions 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode At reset R W 0 0 0 0 0 0 0 0 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ 0 Port Pi direction register 1 2 3 4 5 6 7 Fig. 3.5.11 Structure of Port Pi direction register Port P4, P7 direction registers b7 b6 b5 b4 b3 b2 b1 b0 Port P4 direction register, Port P7 direction register (P4D, P7D : addresses 1916, 1B16) b Name Functions 0 : Port P40 or P70 input mode 1 : Port P40 or P70 output mode 0 : Port P41 or P71 input mode 1 : Port P41 or P71 output mode 0 : Port P42 or P72 input mode 1 : Port P42 or P72 output mode 0 : Port P43 or P73 input mode 1 : Port P43 or P73 output mode 0 : Port P44 or P74 input mode 1 : Port P44 or P74 output mode At reset R W 0 0 0 0 0 ✕ ✕ ✕ ✕ ✕ 0 Port P4 direction register Port P7 direction register 1 2 3 4 5 Nothing is arranged for these bits. 6 When these bits are read out, the contents are undefined. 7 Undefined ✕ ✕ Undefined ✕ ✕ Undefined ✕ ✕ Fig. 3.5.12 Structure of Port P4, Port P7 direction registers Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 49 of 98 APPENDIX 7643 Group 3.5 Control registers Port control register b7 b6 b5 b4 b3 b2 b1 b0 0 Port control register (PTC : address 1016) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 Port P0 to P3 slew rate 0 : Disabled control bit (Note 1) 1 : Enabled 1 Port P4 slew rate control 0 : Disabled bit (Note 1) 1 : Enabled 2 Port P5 slew rate control 0 : Disabled bit (Note 1) 1 : Enabled 3 Port P6 slew rate control 0 : Disabled bit (Note 1) 1 : Enabled 0 : Disabled 4 Port P7 slew rate control bit (Note 1) 1 : Enabled 5 Port P8 slew rate control 0 : Disabled bit (Note 1) 1 : Enabled 6 Port P2 input level select 0 : Reduced VIHL level input (Note 2) bit 1 : CMOS level input 7 Nothing is arranged for this bit. Fix this bit to “0”. Notes 1: The slew rate function can reduce di/dt by modifying an internal buffer structure. 2: The characteristics of VIHL level is basically the same as that of TTL level. But, its switching center point is a little higher than TTL’s. Fig. 3.5.13 Structure of Port control register Interrupt polarity select register b7 b6 b5 b4 b3 b2 b1 b0 000000 Interrupt polarity select register (IPOL : address 1116) b Name Functions 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active At reset R W 0 0 0 0 0 0 0 0 0 INT0 interrupt edge select bit 1 INT1 interrupt edge select bit 2 Nothing is arranged for these bits. 3 Fix these bits to “0”. 4 5 6 7 Fig. 3.5.14 Structure of Interrupt polarity select register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 50 of 98 APPENDIX 7643 Group 3.5 Control registers Port P2 pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Port P2 pull-upt control register (PUP2 : address 1216) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 Port P20 pull-up control bit 0 : Disabled 1 : Enabled 1 Port P21 pull-up control bit 0 : Disabled 1 : Enabled 2 Port P22 pull-up control bit 0 : Disabled 1 : Enabled 3 Port P23 pull-up control bit 0 : Disabled 1 : Enabled 4 Port P24 pull-up control bit 0 : Disabled 1 : Enabled 5 Port P25 pull-up control bit 0 : Disabled 1 : Enabled 6 Port P26 pull-up control bit 0 : Disabled 1 : Enabled 7 Port P27 pull-up control bit 0 : Disabled 1 : Enabled Fig. 3.5.15 Structure of Port P2 pull-up control register USB control register b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 USB control register (USBC : address 1316) b Name Functions At reset R W 0 0 0 Nothing is arranged for this bit. Fix this bit to “0”. 1 USB default state selection 0 : In default state after power-on/reset bit (USBC1) 1 : In default state after USB reset signal received (Note 1) 2 Nothing is arranged for this bit. Fix this bit to “0”. 3 USB line driver current 0 : High current mode 1 : Low current mode control bit (USBC3) 0 : Line driver disabled 4 USB line driver supply enable bit (USBC4) (Note 2) 1 : Line driver enabled 0 : 48 MHz clock to the USB block disabled 5 USB clock enable bit 1 : 48 MHz clock to the USB block enabled (USBC5) 6 Nothing is arranged for this bit. Fix this bit to “0”. 0 : USB block disabled (Note 3) 7 USB enable bit (USBC7) 1 : USB block enabled 0 0 0 0 0 0 Notes 1: Without regard to this bit, USB internal registers (address 005016 to 005F16) go into the states at reset (default) at the same time when USB reset is detected. 2: When using the MCU in Vcc = 3.3 V, set this bit to “0” and disable the built-in DCDC converter. 3: Setting this bit to 0” causes the contents of all USB registers to have the values at reset. Fig. 3.5.16 Structure of USB control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 51 of 98 APPENDIX 7643 Group 3.5 Control registers Clock control register b7 b6 b5 b4 b3 b2 b1 b0 00000 Clock control register (CCR : address 1F16) b Name Functions At reset R W 0 0 0 0 0 0 0 Nothing is arranged for these bits. 1 Fix these bits to “0”. 2 3 4 5 XCOUT oscillation drive 0 : XCOUT oscillation drive is enabled. disable bit (CCR5) (When XCIN oscillation is enabled.) 1 : XCOUT oscillation drive is disabled. 0 : XOUT oscillation drive is enabled. 6 XOUT oscillation drive disable bit (CCR6) (When XIN oscillation is enabled.) 1 : XOUT oscillation drive is disabled. 0 : f(XIN)/2 is used for the system clock. 7 XIN divider select bit (CCR7) (Note) 1 : f(XIN) is used for the system clock. Note: This bit is valid when (b7, b6 of CPMA) = “00”. 0 0 Fig. 3.5.17 Structure of Clock control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 52 of 98 APPENDIX 7643 Group 3.5 Control registers Timer i (i = 1 to 3) b7 b6 b5 b4 b3 b2 b1 b0 Timer 1, Timer 2, Timer 3 (T1, T2, T3: addresses 2416, 2516, 2616) b Functions At reset R W (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) 0 qTimer i’s count value is set through this register. qTimer 1 and Timer 2 Writing operation depends on the timers 1, 2 write control bit. 1 When it is “0”, the values are simultaneously written into their 2 latches and counters. When it is “1”, the values are written into only their latches. 3 qTimer 3 The values are simultaneously written into their latches and 4 counters. 5 qWhen reading this register’s address, its timer’s count values are read out. 6 qThe timer causes an underflow at the count pulse following the count where the timer contents reaches “0016”. Then The contents of latches are automatically reloaded into the timer. 7 Note: Timer 1 and Timer 3’s values are “FF16”. Timer 2 ’s value are “0116”. Fig. 3.5.18 Structure of Timer i Timer 123 mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer 123 mode register (T123M : address 2916) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 TOUT factor select bit 1 2 3 4 5 6 7 0 : Timer 1 output 1 : Timer 2 output 0 : Count start Timer 1 count stop bit 1 : Count stop Timer 1 count source 0:φ/8 select bit 1 : f(XCIN) / 2 Timer 2 count source 0 : Timer 1 output select bit 1:φ 0 : Timer 1 output Timer 3 count source 1:φ/8 select bit TOUT output active edge 0 : Start at “H” output switch bit 1 : Start at “L” output TOUT output control bit 0 : TOUT output disabled 1 : TOUT output enabled Timers 1, 2 write control bit 0 : Write value in latch and counter 1 : Write value in latch only Fig. 3.5.19 Structure of Timer 123 mode register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 53 of 98 APPENDIX 7643 Group 3.5 Control registers Serial I/O shift register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O shift register (SIOSHT: address 2A16) b Functions At reset R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 qAt transmitting Writing transmitted data to this register starts transmitting operation. 1 2 qAt receiving Read received data through this register. 3 4 5 6 7 Fig. 3.5.20 Structure of Serial I/O shift register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 54 of 98 APPENDIX 7643 Group 3.5 Control registers Serial I/O control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O control register 1 (SIOCON1 : address 2B16) b Name b2b1b0 Functions 0 0 0 : φ/2 0 0 1 : φ/4 0 1 0 : φ/8 0 1 1 : φ/16 1 0 0 : φ/32 1 0 1 : φ/64 1 1 0 : φ/128 1 1 1 : φ/256 At reset R W 0 0 Internal synchronous clock select bits (Note) 1 2 3 Serial I/O port select bit 4 5 6 7 0 0 0 : I/O port 1 : STXD, SCLK signal output 0 : I/O port SRDY output select bit 1 : SRDY signal output Transfer direction select bit 0 : LSB first 1 : MSB first Synchronous clock select 0 : External input (SCLK pin input) 1 : Internal synchronous clock bit STXD output channel 0 : CMOS output control bit 1 : N-channel open drain output 0 0 0 1 0 Note: The source of serial I/O internal sysnchronous clock can be selected by bit 1 of serial I/O control register 2. Fig. 3.5.21 Structure of Serial I/O control register 1 Serial I/O control register 2 b7 b6 b5 b4 b3 b2 b1 b0 000 0 Serial I/O control register 2 (SIOCON2 : address 2C16) b Name Functions At reset R W 0 0 0 1 1 0 SPI mode select bit 1 2 3 4 5 6 7 0 : Normal serial I/O mode 1 : SPI compatible mode (Note) Nothing is arranged for this bit. Fix this bit to “0”. SRXD input enable bit 0 : SRXD input disabed 1 : SRXD input enabed Clock polarity select bit 0 : SCLK starting at “L” (CPoL) 1 : SCLK starting at “H” 0 : Serial transfer starting at falling edge Clock phase select bit of SRDY (CPha) 1 : Serial transfer starting after a half cycle of SCLK passed at falling edge of SRDY Nothing is arranged for these bits. Fix these bits to “0”. 0 0 0 Note: To set the slave mode, also set bit 4 of serial I/O control register 1 to “1”. Fig. 3.5.22 Structure of Serial I/O control register 2 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 55 of 98 APPENDIX 7643 Group 3.5 Control registers UART mode register b7 b6 b5 b4 b3 b2 b1 b0 0 UART mode register (UMOD : address 3016) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 Nothing is arranged for this bit. Fix this bit to “0”. b2b1 UART clock prescaling 1 0 0 : φ/1 select bits (PS) 0 1 : φ/8 2 1 0 : φ/32 1 1 : φ/256 Stop bit length select bit 0 : 1 stop bit 3 (STB) 1 : 2 stop bits 0 : Even parity 4 Parity select bit (PMD) 1 : Odd parity 5 Parity enable bit (PEN) 0 : Parity checking disabled 1 : Parity checking enabled b7b6 6 UART character length 0 0 : 7 bits select bit (LE1, 0) 0 1 : 8 bits 7 1 0 : 9 bits 1 1 : Not available Fig. 3.5.23 Structure of Timer UART mode register UART baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 UART baud rate generator (UBRG: address 3116) b Functions At reset R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 qThe UBRG determines the baud rate for transfer. 1 qThis is a 8-bit counter with its reload register. This generator divides the frequency of the count source by 1/(n + 1), where “n” is the 2 value written to the UBRG. 3 4 5 6 7 Fig. 3.5.24 Structure of UART baud rate generator Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 56 of 98 APPENDIX 7643 Group 3.5 Control registers UART status register b7 b6 b5 b4 b3 b2 b1 b0 UART status register (USTS : address 3216) b Name Functions At reset R W 1 1 0 0 0 0 0 0 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ 0 Transmit complete flag (TCM) 1 Transmit buffer empty flag (TBE) 2 Receive buffer full flag (RBF) 3 4 5 6 7 0 : Transmit shift in progress 1 : Transmit shift completed 0 : Buffer full 1 : Buffer empty 0 : Buffer empty 1 : Buffer full 0 : No error Parity error flag (PER) 1 : Parity error Framing error flag (FER) 0 : No error 1 : Framing error 0 : No error Overrun error flag (OER) 1 : Overrun error Summing error flag (SER) 0 : (PER) U (FER) U (OER) = 0 1 : (PER) U (FER) U (OER) = 1 Nothing is arranged for this bit. This is a write disable bit. When this bit is read out, the contents are “0”. Fig. 3.5.25 Structure of UART status regiseter UART control register b7 b6 b5 b4 b3 b2 b1 b0 UART control register (UCON : address 3316) b Name Functions 0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled 0 : No action 1 : Initializing (Note 1) 0 : No action 1 : Initializing (Note 2) 0 : Interrupt when transmit buffer has emptied 1 : Interrupt when transmit shift operation is completed 0 : CTS function disabled (Note 3) 1 : CTS function enabled 0 : RTS function disabled (Note 4) 1 : RTS function enabled 0 : Address mode disabled 1 : Address mode enabled At reset R W 0 0 0 0 0 0 Transmit enable bit (TEN) 1 Receive enable bit (REN) 2 Transmit initialization bit (TIN) 3 Receive initialization bit (RIN) 4 Transmit interrupt source select bit (TIS) 5 CTS function enable bit (CTS_SEL) 6 RTS function enable bit (RTS_SEL) UART address mode 7 enable bit (AME) 0 0 0 Notes 1: When setting the TIN bit to “1”, the TEN bit is set to “0” and the UART status register will be set to “0316” after the data has been transmitted. To retransmit, set the TEN bit to “1” and set a data to the transmit buffer register again. The TIN bit will be cleared to “0” one cycle later after the TIN bit has been set to “1”. 2: Setting the RIN bit to “1” suspends the receiving operation and will set all of the REN, RBF and the receive error flags (PER, FER, OER, SER) to “0”. The RIN bit will be cleared to “0” one cycle later after the RIN bit has been set to “1”. 3: When CTS function is disabled (CTS_SEl = “0”), P86 pin can be used as ordinary I/O ports. 4: When RTS function is disabled (RTS_SEl = “0”), P83 pin can be used as ordinary I/O ports. Fig. 3.5.26 Structure of UART control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 57 of 98 APPENDIX 7643 Group 3.5 Control registers UART transmit/receive buffer registers 1, 2 b7 b6 b5 b4 b3 b2 b1 b0 UART transmit/receive buffer register 1 (UTRB1: address 3416) b 0 1 2 3 4 5 6 Functions The transmit buffer register and the receive buffer register are located at the same address. Writing a transmitting data and reading a received data are performed through the UTRB. This is its low-order byte. •At write The data is written into the transmit buffer register. It is not done into the receive buffer register. •At read The contents of receive buffer register is read. If a character bit length is 7 bits, the MSB of received data is invalid. At reset R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 Note that the contents of transmit buffer register cannot be read. b7 b6 b5 b4 b3 b2 b1 b0 UART transmit/receive buffer register 2 (UTRB2: address 3516) b Functions At reset R W 0 The transmit buffer register and the receive buffer register are located Undefined at the same address. Writing a transmitting data and reading a received data are performed through the UTRB. This is its high-order byte. •At write The data is written into the transmit buffer register. It is not done into the receive buffer register. •At read The contents of receive buffer register is read. If a character bit length is 9 bits, the received high-order 7 bits of UTRB2 are “0” Note that the contents of transmit buffer register cannot be read. If a character bit length is 7 or 8 bits, the received contents of UTRB2 are invalid. 1 Nothing is arranged for these bits. These are write disable bits. 2 When these bits are read out, the contents are “0”. 3 4 5 6 7 Undefined Undefined Undefined Undefined Undefined Undefined Undefined ✕ ✕ ✕ ✕ ✕ ✕ ✕ Fig. 3.5.27 Structure of UART transmit/receive buffer registers 1, 2 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 58 of 98 APPENDIX 7643 Group 3.5 Control registers UART RTS control register b7 b6 b5 b4 b3 b2 b1 b0 0000 UART RTS control register (URTSC : address 3616) b Name Functions At reset R W 0 0 0 0 0 0 Nothing is arranged for these bits. 1 Fix these bits to “0”. 2 3 4 RTS assertion delay count b7b6b5b4 0 0 0 0 : No delay; Assertion immediately select bits (RTS) 0 0 0 1 : 8-bit term assertion at “H” 0 0 1 0 : 16-bit term assertion at “H” 0 0 1 1 : 24-bit term assertion at “H” 5 0 1 0 0 : 32-bit term assertion at “H” 0 1 0 1 : 40-bit term assertion at “H” 0 1 1 0 : 48-bit term assertion at “H” 0 1 1 1 : 56-bit term assertion at “H” 6 1 0 0 0 : 64-bit term assertion at “H” 1 0 0 1 : 72-bit term assertion at “H” 1 0 1 0 : 80-bit term assertion at “H” 1 0 1 1 : 88-bit term assertion at “H” 7 1 1 0 0 : 96-bit term assertion at “H” 1 1 0 1 : 104-bit term assertion at “H” 1 1 1 0 : 112-bit term assertion at “H” 1 1 1 1 : 120-bit term assertion at “H” 0 0 1 Fig. 3.5.28 Structure of UART RTS control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 59 of 98 APPENDIX 7643 Group 3.5 Control registers DMAC index and status register b7 b6 b5 b4 b3 b2 b1 b0 0 DMAC index and status register (DMAIS : address 3F16) b Name Functions At reset R W 0 0 0 0 0 ✽ 0 : No underflow 1 : Underflow generated 0 : Not suspended 1 : Suspended 0 : No underflow 1 : Underflow generated 0 : Not suspended 1 : Suspended 0 :Suspending only burst transfers during interrupt process 1 : Suspending both burst and cycle steal transfers during interrupt process 0 :Enabling reload of source and 5 DMAC register reload destination registers of both channels disable bit (DRLDD) 1 : Disabling reload of source and (Note 3) destination registers of both channels 6 Nothing is arranged for this bit. Fix this bit to “0”. 7 Channel index bit (DCI) 0 : Channel 0 accessible 1 : Channel 1 accessible Accessed registers: Mode register, 0 DMAC channel 0 count register underflow flag (D0UF) 1 DMAC channel 0 suspend flag (D0SFI) (Note 1) 2 DMAC channel 1 count register underflow flag (D1UF) 3 DMAC channel 1 suspend flag (D1SFI) (Note 1) 4 DMAC transfer suspend control bit (DTSC) (Note 2) ✕ ✽ ✕ 0 0 0 source register, destination register, transfer count register. ✽: “0” can be set by software, but “1” cannot be set. Notes 1: Suspended by an interrupt. 2: Transfer suspended during interrupt process 3: This settings affect the source and destination registers of both channels. Fig. 3.5.29 Structure of DMAC index and status register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 60 of 98 APPENDIX 7643 Group 3.5 Control registers DMAC channel x mode register 1 (x = 0, 1) b7 b6 b5 b4 b3 b2 b1 b0 DMAC channel x mode register 1 (DMAxM1 : address 4016) (Note 1) b Name Functions 0 : Increment after transfer 1 : Decrement after transfer 0 : Disabled (No change after transfer) 1 : Enabled 0 : Increment after transfer 1 : Decrement after transfer 0 : Disabled (No change after transfer) 1 : Enabled At reset R W 0 0 : Writing data in reload latches and 0 registers 1 : Writing data in reload latches only DMAC channel x disable after 0 : Channel x enabled after count 5 0 register underflow count register underflow 1 : Channel x disabled after count enable bit (DxDAUE) register underflow 0 6 DMAC channel x register 0 : Not reloaded (Note 2) 1 : Source, destination, and transfer reload bit (DxRLD) count registers contents of channel x to be reloaded 0 : Cycle steal transfer mode 7 DMAC channel x transfer 0 mode selection bit (DxTMS) 1 : Burst transfer mode Notes 1: Channels 1 and 2 share this register. The channel selection which can use this register depends on channel index bit, bit 7 of DMAC index and status register. 2: These bits’ contents are “0” at read. 0 DMAC channel x source register increment/decrement selection bit (DxSRID) 1 DMAC channel x source register increment/decrement enable bit (DxSRCE) 2 DMAC channel x destination register increment/decrement selection bit (DxDRID) 3 DMAC channel x destination register increment/decrement enable bit (DxDRCE) DMAC channel x data 4 write control bit (DxDWC) 0 0 0 Fig. 3.5.30 Structure of DMAC channel x mode register 1 (x = 0, 1) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 61 of 98 APPENDIX 7643 Group 3.5 Control registers DMAC channel 0 mode register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 DMAC channel 0 mode register 2 (DMA0M2 : address 4116) (Note 1) b Name Functions At reset R W 0 0 DMAC channel 0 hardware b3b2b1b0 0 0 0 0 : Not used transfer request source 0 0 0 1 : UART receive interrupt bits (D0HR) 0 0 1 0 : UART transmit interrupt 0 0 1 1 : Not used 0 1 0 0 : INT0 interrupt 0 1 0 1 : USB endpoint 1 IN_PKT_RDY signal (falling edge active) 1 0 1 1 0 : USB endpoint 2 IN_PKT_RDY signal (falling edge active) 0 1 1 1 : Not used 1 0 0 0 : USB endpoint 1 OUT_PKT_RDY signal (rising edge active) 2 1 0 0 1 : USB endpoint 1 OUT_FIFO_NOT_EMPTY signal (rising edge active) 1 0 1 0 : USB endpoint 2 OUT_PKT_RDY signal (rising edge active) 1 0 1 1 : Not used 3 1 1 0 0 : Not used 1 1 0 1 : Not used 1 1 1 0 : Serial I/O transmit/receive interrupt 1 1 1 1 : Not used 4 DMAC channel 0 software 0 : No action 1 : Request of channel 0 transfer by transfer trigger (D0SWT) writing “1” 5 Nothing is arranged for this bit. Fix this bit to “0”. 6 DMAC channel 0 transfer 0 : No action 1 : Reset of channel 0 capture register by initiation source capture writing “1” register reset bit (D0CRR) 0 : Channel 0 disabled DMAC channel 0 enable 7 1 : Channel 0 enabled (Note 3) bit (D0CEN) 0 0 0 0 (Note 2) 0 0 (Note 2) 0 Notes 1: DMAC channel 0 mode register 2 and DMAC channel 1 mode register 2 are assigned at the same address 4116. The accessible register depends on channel index bit, bit 7 of DMAC index and status register. 2: These bits’ contents are “0” at read. This bit is automatically cleared to “0” after writing “1”. 3: When setting this bit to “1”, simultaneously set the DMAC channel 0 transfer initiation source capture register reset bit (bit 6 of DMA0M2) to “1”. Fig. 3.5.31 Structure of DMAC channel 0 mode register 2 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 62 of 98 APPENDIX 7643 Group 3.5 Control registers DMAC channel 1 mode register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 DMAC channel 1 mode register 2 (DMA1M2 : address 4116) (Note 1) b Name Functions At reset R W 0 0 DMAC channel 1 hardware b3b2b1b0 0 0 0 0 : Not used transfer request source 0 0 0 1 : Not used bits (D1HR) 0 0 1 0 : Not used 0 0 1 1 : Not used 0 1 0 0 : INT1 interrupt 0 1 0 1 : USB endpoint 1 IN_PKT_RDY 1 signal (falling edge active) 0 1 1 0 : USB endpoint 2 IN_PKT_RDY signal (falling edge active) 0 1 1 1 : Not used 1 0 0 0 : USB endpoint 1 OUT_PKT_RDY signal (rising 2 edge active) 1 0 0 1 : USB endpoint 1 OUT_FIFO_NOT_EMPTY signal (rising edge active) 1 0 1 0 : USB endpoint 2 OUT_PKT_RDY signal 3 (rising edge active) 1 0 1 1 : Not used 1 1 0 0 : Not used 1 1 0 1 : Not used 1 1 1 0 : Timer 1 interrupt 1 1 1 1 : Not used 4 DMAC channel 1 software 0 : No action 1 : Request of channel 1 transfer by transfer trigger (D1SWT) writing “1” 5 Nothing is arranged for this bit. Fix this bit to “0”. 6 DMAC channel 1 transfer 0 : No action 1 : Reset of channel 1 capture register by initiation source capture writing “1” register reset bit (D1CRR) 0 : Channel 1 disabled 7 DMAC channel 1 enable 1 : Channel 1 enabled (Note 3) bit (D1CEN) 0 0 0 0 (Note 2) 0 0 (Note 2) 0 Notes 1: DMAC channel 0 mode register 2 and DMAC channel 1 mode register 2 are assigned at the same address 4116. The accessible register depends on channel index bit, bit 7 of DMAC index and status register. 2: These bits’ contents are “0” at read. This bit is automatically cleared to “0” after writing “1”. 3: When setting this bit to “1”, simultaneously set the DMAC channel 1 transfer initiation source capture register reset bit (bit 6 of DMA1M2) to “1”. Fig. 3.5.32 Structure of DMAC channel 1 mode register 2 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 63 of 98 APPENDIX 7643 Group 3.5 Control registers DMAC channel x source registers Low, High b7 b6 b5 b4 b3 b2 b1 b0 DMAC channel x source registers Low, High (DMAxSL,DMAxSH : addresses 4216, 4316) b Functions At reset R W 0 qThis is a 16-bit register with a latch. 0 1 0 2 qThis register indicates the source address for data transfer. 0 3 0 4 0 5 0 6 0 7 0 Notes 1: DMAC channel x source registers low, high of channels 0 and 1 are assigned at the same addresses. The accessible register depends on channel index bit, bit 7 of DMAC index and status register. 2: Write data into the lower bytes first, and then the higher bytes. 3: Read the contents from the higher bytes first, and then the lower bytes. Fig. 3.5.33 Structure of DMAC channel x source registers Low, High DMAC channel x destination registers Low, High b7 b6 b5 b4 b3 b2 b1 b0 DMAC channel x destination registers Low, High (DMAxDL,DMAxDH : addresses 4416, 4516) b Functions At reset R W 0 qThis is a 16-bit register with a latch. 0 1 0 2 qThis register indicates the destination address for data transfer. 0 3 0 4 0 5 0 6 0 7 0 Notes 1: DMAC channel x destination registers low, high of channels 0 and 1 are assigned at the same addresses. The accessible register depends on channel index bit, bit 7 of DMAC index and status register. 2: Write data into the lower bytes first, and then the higher bytes. 3: Read the contents from the higher bytes first, and then the lower bytes. Fig. 3.5.34 Structure of DMAC channel x destination registers Low, High Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 64 of 98 APPENDIX 7643 Group 3.5 Control registers DMAC channel x transfer count registers Low, High b7 b6 b5 b4 b3 b2 b1 b0 DMAC channel x transfer count registers Low (DMAxCL : address 4616) b 0 1 2 3 4 5 6 7 b7 b6 b5 b4 b3 b2 b1 b0 Functions qThis is the lower 8-bit register with a latch. Set the lower 8 bits of transfer numbers. qThis register indicates the remaining transfer numbers while transfer is continuing. qThis contents are decreased by 1 at every transfer operation. qWhen this register underflows, the DMAC interrupt request bit and the count register underflow flag (Note 2) are set to “1”. At reset R W 0 0 0 0 0 0 0 0 DMAC channel x transfer count registers High (DMAxCH : address 4716) b Functions At reset R W 0 qThis is the higher 8-bit register with a latch. Set the higher 8 bits of 0 transfer numbers. 1 0 2 qThis register indicates the remaining transfer numbers while 0 transfer is continuing. 3 0 qThis contents are decreased by 1 at every transfer operation. 4 0 5 0 6 0 7 0 Notes 1: DMAC channel x transfer count registers low, high of channels 0 and 1 are assigned at the same addresses 4616 and 4716. The accessible channel depends on channel index bit, bit 7 of DMAC index and status register. 2: Channel 0 used: Bit 0 of DMAC index and status register Channel 1 used: Bit 2 of DMAC index and status register 3: Write data into the lower byte first, and then the higher byte. 4: Read the contents from the higher byte first, and then the lower byte. Fig. 3.5.35 Structure of DMAC channel x transfer count registers Low, High (x = 0, 1) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 65 of 98 APPENDIX 7643 Group 3.5 Control registers USB address register b7 b6 b5 b4 b3 b2 b1 b0 0 USB address register (USBA : address 5016) b Name Functions At reset R W 0 0 0 0 0 0 0 0 0 This register maintains the 7-bit USB function control unit address assigned by the host CPU. 1 2 3 4 5 6 7 Nothing is arranged for this bit. Fix this bit to “0”. Fig. 3.5.36 Structure of USB address register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 66 of 98 APPENDIX 7643 Group 3.5 Control registers USB power management register b7 b6 b5 b4 b3 b2 b1 b0 00000 USB power management register (USBPM : address 5116) b Name Functions 0 : No USB suspend detected 1 : USB suspend detected (Note 1) 0 : No USB resume signal detected 1 : USB resume signal detected 0 : End of remote resume signal 1 : Transmitting of remote resume signal (only when SUSPEND = “1”) (Note 2) At reset R W 0 0 0 ✕ ✕ 0 USB suspend detection flag (SUSPEND) 1 USB resume detection flag (RESUME) 2 USB remote wake-up bit (WAKEUP) 3 Nothing is arranged for these bits. Fix these bits to “0”. 4 5 6 7 0 0 0 0 0 Notes 1: This bit is cleared when the WAKEUP bit is “1”. 2: When the SUSPEND bit is “1”, set this bit to “1” and keep “1” for 10 ms to 15 ms. Fig. 3.5.37 Structure of USB power management register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 67 of 98 APPENDIX 7643 Group 3.5 Control registers USB interrupt status register 1 b7 b6 b5 b4 b3 b2 b1 b0 00 0 USB interrupt status register 1 (USBIS1 : address 5216) b Name Functions 0 : Except the following conditions 1 : Set at any one of the following conditions: • A packet data of endpoint 0 is successfully received • A packet data of endpoint 0 is successfully sent • DATA_END bit of endpoint 0 is cleared to “0” • FORCE_STALL bit of endpoint 0 is set to “1” • SETUP_END bit of endpoint 0 is set to “1”. At reset R W 0 ✽ 0 USB endpoint 0 interrupt status flag (INTST0) 1 Nothing is arranged for this bit. Fix this bit to “0”. 2 USB endpoint 1 IN 0 : Except the following conditions interrupt status flag 1 : Set at which of the following (INTST2) condition: • A packet data of endpoint 1 is successfully sent 3 USB endpoint 1 OUT interrupt status flag (INTST3) 0 : Except the following conditions 1 : Set at any one of the following conditions: • A packet data of endpoint 1 is successfully received • FORCE_STALL bit of endpoint 1 is set to “1”. 0 : Except the following conditions 1 : Set at which of the following condition: • A packet data of endpoint 2 is successfully sent 0 : Except the following conditions 1 : Set at any one of the following conditions: • A packet data of endpoint 2 is successfully received • FORCE_STALL bit of endpoint 2 is set to “1”. 0 0 ✽ 0 ✽ 4 USB endpoint 2 IN interrupt status flag (INTST4) 0 ✽ 5 USB endpoint 2 OUT interrupt status flag (INTST5) 0 ✽ 6 Nothing arranged for these bits. 7 Fix these bits to “0”. ✽: “0” can be set by software, but “1” cannot be set. To clear the bit set to “1”, write “1” to the bit. 0 0 Fig. 3.5.38 Structure of USB interrupt status register 1 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 68 of 98 APPENDIX 7643 Group 3.5 Control registers USB interrupt status register 2 b7 b6 b5 b4 b3 b2 b1 b0 00000 USB interrupt status register 2 (USBIS2 : address 5316) b Name Functions At reset R W 0 0 0 0 0 0 0 ✽ ✽ 0 Nothing is arranged for these bits. Fix these bits to “0”. 1 2 3 4 5 USB reset interrupt status 0 : Except the following conditions 1 : Set at receiving of USB reset signal flag (INTST13) 6 USB resume signal interrupt status flag (INTST14) 7 USB suspend signal interrupt status flag (INTST15) 0 : Except the following conditions 1 : Set at receiving of resume signal 0 : Except the following conditions 1 : Set at receiving of suspend signal 0 ✽ ✽: “0” can be set by software, but “1” cannot be set. To clear the bit set to “1”, write “1” to the bit. Fig. 3.5.39 Structure of USB interrupt status register 2 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 69 of 98 APPENDIX 7643 Group 3.5 Control registers USB interrupt enable register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 USB interrupt enable register 1 (USBIE1 : address 5416) b Name Functions At reset R W 1 1 1 1 1 1 ✕ ✕ 0 USB endpoint 0 interrupt enable bit (INTEN0) 1 2 3 4 5 6 7 0 : Disabled 1 : Enabled Nothing arranged for this bit. Fix this bit to “0”. USB endpoint 1 IN interrupt 0 : Disabled 1 : Enabled enable bit (INTEN2) USB endpoint 1 OUT inter- 0 : Disabled 1 : Enabled rupt enable bit (INTEN3) USB endpoint 2 IN interrupt 0 : Disabled 1 : Enabled enable bit (INTEN4) USB endpoint 2 OUT inter- 0 : Disabled 1 : Enabled rupt enable bit (INTEN5) Nothing is arranged for these bits. When these bits are read out, the contents are undefined. These bits are “0” at write. Fig. 3.5.40 Structure of USB interrupt enable register 1 USB interrupt enable register 2 b7 b6 b5 b4 b3 b2 b1 b0 01 00 USB interrupt enable register 2 (USBIE2 : address 5516) b Name Functions At reset R W ✕ ✕ 0 0 ✕ 1 0 0 0 Nothing is arranged for these bits. When these bits are read out, 1 the contents are undefined. These bits are “0” at write. 2 Nothing is arranged for these bits. Fix these bits to “0”. 3 4 Nothing is arranged for this bit. When this bit is read out, the contents are undefined. This bit is “0” at write. 5 Nothing is arranged for this bit. Fix this bit to “1”. 6 Nothing is arranged for this bit. Fix this bit to “0”. 0 : Disabled 7 USB suspend/resume interrupt enable bit (INTEN15) 1 : Enabled Fig. 3.5.41 Structure of USB interrupt enable register 2 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 70 of 98 APPENDIX 7643 Group 3.5 Control registers USB endpoint index register b7 b6 b5 b4 b3 b2 b1 b0 00000 USB endpoint index register (USBINDEX : address 5816) b Name b2b1b0 Functions 0 0 0 : Endpoint 0 0 0 1 : Endpoint 1 0 1 0 : Endpoint 2 0 1 1 : Not used 1 0 0 : Not used 1 0 1 : Not used 1 1 0 : Not used 1 1 1 : Not used At reset R W 0 0 Endpoint index bit (EPINDEX) 1 2 0 0 0 0 0 0 0 3 Nothing is arranged for these bits. Fix these bits to “0”. 4 5 6 7 Fig. 3.5.42 Structure of USB endpoint index register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 71 of 98 APPENDIX 7643 Group 3.5 Control registers USB endpoint 0 IN control register b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint 0 IN control register (IN_CSR : address 5916) b Name Functions 0 : Except the following condition (Cleared to “0” by writing “1” into SERVICED_OUT_PKT_RDY bit) 1 : End of a data packet reception 0 : End of a data packet transmission 1 : Write “1” at completion of writing a data packet into IN FIFO. 0 : Except the following condition 1 : Transmitting STALL handshake signal At reset R W 0 ✽1 0 OUT_PKT_RDY flag (IN0CSR0) 1 IN_PKT_RDY bit (IN0CSR1) 0 ✽2 2 SEND_STALL bit (IN0CSR2) 3 DATA_END bit (IN0CSR3) 0 : Except the following condition (Cleared to “0” after completion of status phase) 1 : Write “1” at completion of writing or reading the last data packet to/from FIFO. 0 : Except the following condition 4 FORCE_STALL flag (IN0CSR4) 1 : Protocol error detected 0 : Except the following condition 5 SETUP_END flag (Cleared to “0” by writing “1” into (IN0CSR5) SERVICED_SETUP_END bit) 1 : Control transfer ends before the specific length of data is transferred during the data phase. 6 SERVICED_OUT_PKT_R 0 : Except the following condition DY bit (IN0CSR6) 1 : Writing “1” to this bit clears OUT_ PKT_RDY flag to “0”. 7 SERVICED_SETUP_END 0 : Except the following condition bit (IN0CSR7) 1 : Writing “1” to this bit clears SETUP_ END flag to “0”. 0 0 ✽2 0 0 ✽1 ✽1 0 0 USB endpoint 1, 2 IN control register b7 b6 b5 b4 b3 b2 b1 b0 0 USB endpoint 1, 2 IN control register (IN_CSR : address 5916) b Name Functions 0 : End of a data packet transmission 1 : Write “1” at completion of writing a data packet into IN FIFO. (Note 2) At reset R W 0 ✽2 0 INT_PKT_RDY bit (INXCSR0) 1 Nothing is arranged for this bit. Fix this bit to “0”. 0 : Except the following condition 2 SEND_STALL bit (INXCSR2) 1 : Transmitting STALL handshake signal 3 TOGGLE_INIT bit (INXCSR3) 0 : Except the following condition 1 : Initializing the data toggle sequence bit 0 : Except the following condition 1 : Initializing to endpoint used for interrupt transfer, rate feedback 0 0 0 4 INTPT bit (INXCSR4) 0 0 : Empty in IN FIFO 1 : Full in IN FIFO 0 : Except the following condition 1 : Flush FIFO 7 AUTO_SET bit (INXCSR7) 0 : AUTO_SET disabled 1 : AUTO_SET enabled ✽3 5 TX_NOT_EPT flag (INXCSR5) 6 FLUSH bit (INXCSR6) 0 0 0 ✕ ✽1 ✽ 1: “1” can be set by software, but “0” cannot be set. ✽ 2: When INXCSR7=“1”, this bit is automatically set to “1”. When INXCSR7=“0”, writing data to FIFO, and then write “1” to this bit. ✽ 3: To use the AUTO_SET function for an IN transfer when the AUTO_SET bit is set to “1”, set the FIFO to single buffer mode. Fig. 3.5.43 Structure of USB endpoint x IN control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 72 of 98 APPENDIX 7643 Group 3.5 Control registers USB endpoint x OUT control register b7 b6 b5 b4 b3 b2 b1 b0 0 0 USB endpoint x OUT control register (OUT_CSR : address 5A16) b Name Functions At reset R W 0 0 0 0 ✽2 0 : Except the following condition (Note) 0 OUT_PKT_RDY flag (OUTXCSR0) 1 : End of a data packet reception 1 Nothing is arranged for this bit. Fix this bit to “0”. 0 : Except the following condition 2 SEND_STALL bit (OUTXCSR2) 1 : Transmitting STALL handshake signal 3 TOGGLE_INIT bit (OUTXCSR3) 0 : Except the following condition 1 : Enabling reception of DATA0 and DATA1 as PID (Initializing the toggle) 0 : Except the following condition 4 FORCE_STALL flag 1 : Protocol error detected (OUTXCSR4) 5 Nothing is arranged for this bit. Fix this bit to “0”. 0 : Except the following condition 6 FLUSH bit (OUTXCSR6) 1 : Flush FIFO 7 AUTO_SET bit 0 : AUTO_SET disabled (OUTXCSR7) 1 : AUTO_SET enabled ✽ 1: “0” can be set by software, but “1” cannot be set. ✽ 2: When OUTXCSR7=“1”, this bit is automatically set to “1”. When OUTXCSR7=“0”, writing data to FIFO, and then write “0” to this bit. 0 0 0 0 ✽1 Fig. 3.5.44 Structure of USB endpoint x OUT control register (x = 1, 2) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 73 of 98 APPENDIX 7643 Group 3.5 Control registers USB endpoint x IN max. packet size register b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint x IN max. packet size register (IN_MAXP: address 5B16) b Functions At reset R W (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) 0 The maximum packet size (MAXP) of endpoint x IN is contained. 1 qMAXP = n for endpoints 0, 2 2 qMAXP = n ✕ 8 for endpoint 1 “n” is a written value into this register. 3 4 5 6 7 Note: The value is “0116” in the endpoint 1 used. The value is “0816” in the endpoint 0 or 2 used. Fig. 3.5.45 Structure of USB endpoint x IN max. packet size register (x = 0 to 2) USB endpoint x OUT max. packet size register b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint x OUT max. packet size register (OUT_MAXP: address 5C16) b Functions At reset R W (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) 0 The maximum packet size (MAXP) of endpoint x OUT is contained. 1 qMAXP = n for endpoints 0, 2 2 qMAXP = n ✕ 8 for endpoint 1 “n” is a written value into this register. 3 4 5 6 7 Note: The value is “0816” in the endpoint 0 or 2 used. The value is “0116” in the endpoint 1 used. Fig. 3.5.46 Structure of USB endpoint x OUT max. packet size register (x = 0 to 2) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 74 of 98 APPENDIX 7643 Group 3.5 Control registers USB endpoint x OUT write count register b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint x (x=0 to 2) OUT write count register (WRT_CNT : address 5D16) b Name Functions At reset R W 0 0 0 0 0 0 0 0 ✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕ 0 Contains the number of bytes in endpoint x OUT FIFO. 1 2 3 4 5 6 7 Fig. 3.5.47 Structure of USB endpoint x OUT write control register (x = 0 to 2) USB endpoint FIFO mode register b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint FIFO mode register (USBFIFOMR : address 5F16) b Name For endpoint 1 b3b2b1b0 Functions ✕ 0 0 0 : IN 128-byte, OUT 128-byte For endpoint 2 At reset R W 0 0 0 0 0 0 0 0 0 FIFO size selection bit (Note) 1 2 3 b3b2b1b0 0 ✕ ✕ ✕ : IN 32-byte, OUT 32-byte 1 ✕ ✕ ✕ : IN 128-byte, OUT 128-byte 4 Nothing is arranged for these bits. When these bits are read out, the 5 contents are undefined. These bits are “0” at write. 6 7 Note: The value set into “x” is invalid. Fig. 3.5.48 Structure of USB endpoint FIFO mode register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 75 of 98 APPENDIX 7643 Group 3.5 Control registers USB endpoint x FIFO register b7 b6 b5 b4 b3 b2 b1 b0 USB endpoint x (x=0 to 2) FIFO register (USBFIFOx: addresses 6016, 6116, 6216) b Functions At reset R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 qThis is Endpoint x IN/OUT FIFO. 1 qWrite a data to be transmitted into this IN FIFO. 2 qRead a received data from this OUT FIFO. 3 4 5 6 7 Fig. 3.5.49 Structure of USB endpoint x FIFO register (x = 0 to 2) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 76 of 98 APPENDIX 7643 Group 3.5 Control registers Flash memory control register b7 b6 b5 b4 b3 b2 b1 b0 Flash memory control register (FMCR : address 6A16) b Name Functions 0 : Busy (being programmed or erased) 1 : Ready 0 : Normal mode (Software commands invalid) 1 : CPU rewrite mode (Software commands acceptable) 0 : Normal mode 1 : CPU rewrite mode 0 : Normal operation 1 : Reset 0 : Interrupt disabled 1 : Interrupt enabled Indefinite at read. Write “0” at write. At reset R W 1 0 0 RY/BY status flag (FLCA0) 1 CPU rewrite mode select bit (FLCA1) (Note 2) 2 CPU rewrite mode entry flag (FLCA2) 3 Flash memory reset bit (FLCA3) (Note 3) 4 User ROM area / Boot ROM area select bit (FLCA4) (Note 4) 5 Reserved bits 5 6 5 7 0 ✕ 0 0 0 0 0 Notes 1: The contents of flash memory control register are “XXX00001” just after reset release. In the mask ROM version this area is reserved, so that do not write any data to this address. 2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. If it is not this procedure, this bit will not be set to ”1”. Additionally, it is required to ensure that no interrupt will be generated during that interval. Use the control program in the area except the built-in flash memory for write to this bit. 3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently after setting bit 3 to “1”. 4: Use the control program in the area except the built-in flash memory for write to this bit. Fig. 3.5.50 Structure of Flash memory control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 77 of 98 APPENDIX 7643 Group 3.5 Control registers Frequency synthesizer control register b7 b6 b5 b4 b3 b2 b1 b0 0 00 Frequency synthesizer control register (FSC : address 6C16) b Name Functions At reset R W 0 0 0 0 0 1 1 0 0 Frequency synthesizer enable bit (FSE) 0 : Disabled 1 : Enabled 1 Nothing is arranged for these bits. 2 Fix these bits to “0”. 0 : f(XIN) 3 Frequency synthesizer 1 : f(XCIN) input bit (FIN) 4 Nothing is arranged for this bit. Fix this bit to “0”. 5 LPF current control bit (CHG1, CHG0) (Note) 6 7 Frequency synthesizer lock status bit b1b0 0 0 : Not available 0 1 : Low current 1 0 : Intermediate current (recommended) 1 1 : High current 0 : Unlocked 1 : Locked Note: Bits 6 and 5 are set to (bit 6, bit 5) = (1, 1) at reset. When using the frequency synthesizer, we recommend to set to (bit 6, bit 5) = (1, 0) after locking the frequency synthesizer. Fig. 3.5.51 Structure of Frequency synthesizer control register Frequency synthesizer multiply register 1 b7 b6 b5 b4 b3 b2 b1 b0 Frequency synthesizer multiply register 1 (FSM1: address 6D16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qfVCO clock is generated by multiplying fPIN clock, which is generated by FSM2, by the contents of this register: 1 2 fVCO = fPIN • {2(n +1)}, n: value set to FSM1. 3 4 5 6 7 Fig. 3.5.52 Structure of Frequency synthesizer multiply register 1 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 78 of 98 APPENDIX 7643 Group 3.5 Control registers Frequency synthesizer multiply register 2 b7 b6 b5 b4 b3 b2 b1 b0 Frequency synthesizer multiply register 2 (FSM2: address 6E16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qfPIN clock is generated by dividing fIN clock by the contents of this register. 1 Either f(XIN) or f(XCIN) as an input clock fIN for the frequency 2 synthesizer is selectable. 3 4 fPIN = fIN / {2(n +1)}, n: value set to FSM2 5 6 7 Fig. 3.5.53 Structure of Frequency synthesizer multiply register 2 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 79 of 98 APPENDIX 7643 Group 3.5 Control registers Frequency synthesizer divide register b7 b6 b5 b4 b3 b2 b1 b0 Frequency synthesizer divide register (FSD: address 6F16) b Functions At reset R W 1 1 1 1 1 1 1 1 0 qfSYN clock is generated by dividing fVCO clock by the contents of this register: 1 2 fSYN = fVCO / {2(m +1)}, m: value set to FSD 3 4 5 6 7 Fig. 3.5.54 Structure of Frequency synthesizer divide register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 80 of 98 APPENDIX 7643 Group 3.5 Control registers ROM code protect control register b7 b6 b5 b4 b3 b2 b1 b0 11 ROM code protect control register (ROMCP : address FFC916) (Note 1) b Name Functions Indefinite at read. Write “0” at write. b3b2 At reset R W 1 1 1 1 1 1 1 1 0 Reserved bits. 1 2 ROM code protect level 2 set bits (ROMCP2) (Notes 2, 3) 3 4 ROM code protect reset bits (ROMCR) (Note 4) 5 6 ROM code protect level 1 set bits (ROMCP1) (Note 2) 7 0 0 : Protect enabled 0 1 : Protect enabled 1 0 : Protect enabled 1 1 : Protect disabled b5b4 0 0 : Protect removed 0 1 : Protect set bits effective 1 0 : Protect set bits effective 1 1 : Protect set bits effective b7b6 0 0 : Protect enabled 0 1 : Protect enabled 1 0 : Protect enabled 1 1 : Protect disabled Notes 1: This area is on the ROM in the mask ROM version. 2: When ROM code protect is turned on, the internal flash memory is protected against readout or modification in parallel I/O mode. 3: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc. also is inhibited. 4: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, since these bits cannot be modified in parallel I/O mode, they need to be rewritten in standard serial I/O mode or CPU rewrite mode. Fig. 3.5.55 Structure of ROM code protect control register Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 81 of 98 APPENDIX 7643 Group 3.6 Package outline 3.6 Package outline PRQP0080GB-A JEITA Package Code P-QFP80-14x20-0.80 RENESAS Code PRQP0080GB-A Previous Code 80P6N-A MASS[Typ.] 1.6g HD *1 D 41 64 65 NOTE) 1. * *2" HE E ZE *2 * INCLUDE TRIM OFFSET. 80 25 Dimension in Millimeters Symbol 1 ZD 24 Index mark F c D E A2 D HE A A1 bp c L Detail F Min Nom 19.8 13.8 14.0 2.8 22.5 22.8 16.5 16.8 0.1 0 0.3 0.35 0.13 0.15 0° 0.65 0.8 0.8 1.0 0.6 Max 14.2 23.1 17.1 3.05 0.2 0.2 10 ° 0.10 A *3 A1 e y bp A2 y ZD ZE L 0.4 0.8 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 82 of 98 APPENDIX 7643 Group 3.6 Package outline PLQP0080KB-A JEITA Package Code P-LQFP80-12x12-0.50 RENESAS Code PLQP0080KB-A Previous Code 80P6Q-A MASS[Typ.] 0.5g HD *1 D 41 NOTE) 1. DIMENSIONS "*1" AND "*2" 0 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 1 *2 HE E c1 Reference Dimension in Millimeters Symbol Terminal cross section D E A HD E 20 F A1 p b1 c c1 e x y ZD ZE L L1 L L1 Detail F Min Nom Max 11.9 12.0 12.1 11.9 12.0 12.1 1.4 13.8 14.0 14.2 13.8 14.0 14.2 1.7 0.1 0.2 0 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0° 10 ° 0.5 0.08 0.08 1.25 1.25 0.3 0.5 0.7 1.0 ZE A2 A Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 83 of 98 A1 c APPENDIX 7643 Group 3.7 Machine instructions 3.7 Machine instructions Addressing mode Symbol Function Details IMP OP n ADC (Note 1) (Note 7) When T = 0 A←A+M+C When T = 1 M(X) ← M(X) + M + C When T = 0, this instruction adds the contents M, C, and A; and stores the results in A and C. When T = 1, this instruction adds the contents of M(X), M and C; and stores the results in M(X) and C. When T=1, the contents of A remain unchanged, but the contents of status flags are changed. M(X) represents the contents of memory where is indicated by X. When T = 0, this instruction transfers the contents of A and M to the ALU which performs a bit-wise AND operation and stores the result back in A. When T = 1, this instruction transfers the contents M(X) and M to the ALU which performs a bit-wise AND operation and stores the results back in M(X). When T = 1, the contents of A remain unchanged, but status flags are changed. M(X) represents the contents of memory where is indicated by X. This instruction shifts the content of A or M by one bit to the left, with bit 0 always being set to 0 and bit 7 of A or M always being contained in C. This instruction tests the designated bit i of M or A and takes a branch if the bit is 0. The branch address is specified by a relative address. If the bit is 1, next instruction is executed. This instruction tests the designated bit i of the M or A and takes a branch if the bit is 1. The branch address is specified by a relative address. If the bit is 0, next instruction is executed. This instruction takes a branch to the appointed address if C is 0. The branch address is specified by a relative address. If C is 1, the next instruction is executed. This instruction takes a branch to the appointed address if C is 1. The branch address is specified by a relative address. If C is 0, the next instruction is executed. This instruction takes a branch to the appointed address when Z is 1. The branch address is specified by a relative address. If Z is 0, the next instruction is executed. This instruction takes a bit-wise logical AND of A and M contents; however, the contents of A and M are not modified. The contents of N, V, Z are changed, but the contents of A, M remain unchanged. This instruction takes a branch to the appointed address when N is 1. The branch address is specified by a relative address. If N is 0, the next instruction is executed. This instruction takes a branch to the appointed address if Z is 0. The branch address is specified by a relative address. If Z is 1, the next instruction is executed. 24 3 2 IMM # OP n 69 2 A # OP n 2 BIT, A BIT, A, R # OP n ZP BIT, ZP BIT, ZP, R # OP n 2 # # OP n 65 3 ASL C← 7 0 ←0 BBC Ai or Mi = 0? BBS Ai or Mi = 1? BCC (Note 5) (Note 9) C = 0? BCS (Note 5) (Note 9) C = 1? BEQ (Note 5) (Note 8) Z = 1? BIT A M BMI (Note 5) (Note 8) N = 1? BNE (Note 5) (Note 8) Z = 0? Rev.2.00 Aug 28, 2006 REJ09B0133-0200 V When T = 1 M(X) ← M(X) V AND (Note 1) When T = 0 A←A M M 29 2 2 25 3 2 0A 1 1 06 5 2 13 4 2 + 20i (Note 4) 17 5 3 + 20i (Note 6) 03 4 2 + 20i (Note 4) 07 5 3 + 20i (Note 6) V page 84 of 98 APPENDIX 7643 Group 3.7 Machine instructions Addressing mode ZP, X OP n 75 4 ZP, Y # OP n 2 ABS # OP n 6D 4 ABS, X # OP n 3 7D 5 ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 Processor status register 6 V V 5 T • 4 B • 3 D • 2 I • 1 Z Z 0 C C # OP n 3 79 5 # OP n 3 # OP n 61 6 # OP n 2 71 6 # OP n 2 N N 35 4 2 2D 4 3 3D 5 3 39 5 3 21 6 2 31 6 2 N • • • • • Z • 16 6 2 0E 6 3 1E 7 3 N • • • • • Z C • • • • • • • • • • • • • • • • 90 2 2 • • • • • • • • B0 2 2 • • • • • • • • F0 2 2 • • • • • • • • 2C 4 3 M7 M6 • • • • Z • 30 2 2 • • • • • • • • D0 2 2 • • • • • • • • Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 85 of 98 APPENDIX 7643 Group 3.7 Machine instructions Addressing mode Symbol Function Details IMP OP n BPL (Note 5) (Note 8) N = 0? This instruction takes a branch to the appointed address if N is 0. The branch address is specified by a relative address. If N is 1, the next instruction is executed. This instruction branches to the appointed address. The branch address is specified by a relative address. When the BRK instruction is executed, the CPU pushes the current PC contents onto the stack. The BADRS designated in the interrupt vector table is stored into the PC. 00 7 1 IMM # OP n A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n # BRA (Note 6) PC ← PC ± offset BRK B←1 (PC) ← (PC) + 2 M(S) ← PCH S←S–1 M(S) ← PCL S←S–1 M(S) ← PS S←S–1 I← 1 PCL ← ADL PCH ← ADH V = 0? BVC (Note 5) This instruction takes a branch to the appointed address if V is 0. The branch address is specified by a relative address. If V is 1, the next instruction is executed. This instruction takes a branch to the appointed address when V is 1. The branch address is specified by a relative address. When V is 0, the next instruction is executed. This instruction clears the designated bit i of A or M. This instruction clears C. 18 1 1 1B 1 + 20i 1 1F 5 + 20i 2 BVS (Note 5) V = 1? CLB Ai or Mi ← 0 C←0 D←0 I←0 T←0 V←0 When T = 0 A–M When T = 1 M(X) – M CLC CLD This instruction clears D. D8 1 1 CLI This instruction clears I. 58 2 1 CLT This instruction clears T. 12 1 1 CLV This instruction clears V. B8 1 1 CMP (Note 3) When T = 0, this instruction subtracts the contents of M from the contents of A. The result is not stored and the contents of A or M are not modified. When T = 1, the CMP subtracts the contents of M from the contents of M(X). The result is not stored and the contents of X, M, and A are not modified. M(X) represents the contents of memory where is indicated by X. This instruction takes the one’s complement of the contents of M and stores the result in M. This instruction subtracts the contents of M from the contents of X. The result is not stored and the contents of X and M are not modified. This instruction subtracts the contents of M from the contents of Y. The result is not stored and the contents of Y and M are not modified. This instruction subtracts 1 from the contents of A or M. C9 2 2 C5 3 2 COM M←M __ 44 5 2 CPX X–M E0 2 2 E4 3 2 CPY Y–M C0 2 2 C4 3 2 DEC A ← A – 1 or M←M–1 1A 1 1 C6 5 2 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 86 of 98 APPENDIX 7643 Group 3.7 Machine instructions Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n ABS, X # OP n ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n 2 # 7 Processor status register 6 V • 5 T • 4 B • 3 D • 2 I • 1 Z • 0 C • # OP n # OP n # OP n # OP n # OP n 10 2 N • 80 3 2 • • • • • • • • • • • 1 • 1 • • 50 2 2 • • • • • • • • 70 2 2 • • • • • • • • • • • • • • • • • • • • • • • 0 • • • • 0 • • • • • • • • 0 • • • • 0 • • • • • • D5 4 2 CD 4 3 DD 5 3 D9 5 3 C1 6 2 D1 6 2 0 • • • • • • N • • • • • Z C N EC 4 3 • • • • • Z • N • • • • • Z C CC 4 3 N • • • • • Z C D6 6 2 CE 6 3 DE 7 3 N • • • • • Z • Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 87 of 98 APPENDIX 7643 Group 3.7 Machine instructions Addressing mode Symbol Function Details IMP OP n DEX X←X–1 Y←Y–1 A ← (M(zz + X + 1), M(zz + X )) / A M(S) ← one's complement of Remainder S←S–1 When T = 0 – A← AVM When T = 1 – M(X) ← M(X) V M This instruction subtracts one from the current CA 1 contents of X. This instruction subtracts one from the current contents of Y. This instruction divides the 16-bit data in M(zz+(X)) (low-order byte) and M(zz+(X)+1) (high-order byte) by the contents of A. The quotient is stored in A and the one's complement of the remainder is pushed onto the stack. When T = 0, this instruction transfers the contents of the M and A to the ALU which performs a bit-wise Exclusive OR, and stores the result in A. When T = 1, the contents of M(X) and M are transferred to the ALU, which performs a bitwise Exclusive OR and stores the results in M(X). The contents of A remain unchanged, but status flags are changed. M(X) represents the contents of memory where is indicated by X. This instruction adds one to the contents of A or M. This instruction adds one to the contents of X. E8 1 C8 1 1 49 2 2 45 3 2 88 1 IMM # OP n 1 A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n # DEY 1 DIV EOR (Note 1) INC A ← A + 1 or M←M+1 X←X+1 Y←Y+1 If addressing mode is ABS PCL ← ADL PCH ← ADH If addressing mode is IND PCL ← M (ADH, ADL) PCH ← M (ADH, ADL + 1) If addressing mode is ZP, IND PCL ← M(00, ADL) PCH ← M(00, ADL + 1) M(S) ← PCH S←S–1 M(S) ← PCL S←S–1 After executing the above, if addressing mode is ABS, PCL ← ADL PCH ← ADH if addressing mode is SP, PCL ← ADL PCH ← FF If addressing mode is ZP, IND, PCL ← M(00, ADL) PCH ← M(00, ADL + 1) When T = 0 A←M When T = 1 M(X) ← M 3A 1 1 E6 5 2 INX INY JMP This instruction adds one to the contents of Y. This instruction jumps to the address designated by the following three addressing modes: Absolute Indirect Absolute Zero Page Indirect Absolute 1 JSR This instruction stores the contents of the PC in the stack, then jumps to the address designated by the following addressing modes: Absolute Special Page Zero Page Indirect Absolute LDA (Note 2) When T = 0, this instruction transfers the contents of M to A. When T = 1, this instruction transfers the contents of M to (M(X)). The contents of A remain unchanged, but status flags are changed. M(X) represents the contents of memory where is indicated by X. This instruction loads the immediate value in M. This instruction loads the contents of M in X. This instruction loads the contents of M in Y. A9 2 2 A5 3 2 LDM M ← nn X←M Y←M 3C 4 3 LDX LDY A2 2 A0 2 2 2 A6 3 A4 3 2 2 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 88 of 98 APPENDIX 7643 Group 3.7 Machine instructions Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n ABS, X # OP n ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 Processor status register 6 V • 5 T • 4 B • 3 D • 2 I • 1 Z Z 0 C • # OP n # OP n # OP n # OP n # OP n N N N • • • • • Z • E2 16 2 NV • • • • Z C 55 4 2 4D 4 3 5D 5 3 59 5 3 41 6 2 51 6 2 N • • • • • Z • F6 6 2 EE 6 3 FE 7 3 N • • • • • Z • N • • • • • Z • N 4C 3 3 6C 5 3 B2 4 2 • • • • • • • • • • • Z • • • 20 6 3 02 7 2 22 5 2 • • • • • • • • B5 4 2 AD 4 3 BD 5 3 B9 5 3 A1 6 2 B1 6 2 N • • • • • Z • • • • • • • • • B6 4 B4 4 2 2 AE 4 AC 4 3 3 BC 5 3 BE 5 3 N N • • • • • • • • • • Z Z • • Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 89 of 98 APPENDIX 7643 Group 3.7 Machine instructions Addressing mode Symbol Function Details IMP OP n LSR 7 0→ 0 →C This instruction shifts either A or M one bit to the right such that bit 7 of the result always is set to 0, and the bit 0 is stored in C. This instruction multiply Accumulator with the memory specified by the Zero Page X address mode and stores the high-order byte of the result on the Stack and the low-order byte in A. This instruction adds one to the PC but does EA 1 no other operation. When T = 0, this instruction transfers the contents of A and M to the ALU which performs a bit-wise “OR”, and stores the result in A. When T = 1, this instruction transfers the contents of M(X) and the M to the ALU which performs a bit-wise OR, and stores the result in M(X). The contents of A remain unchanged, but status flags are changed. M(X) represents the contents of memory where is indicated by X. This instruction pushes the contents of A to the memory location designated by S, and decrements the contents of S by one. This instruction pushes the contents of PS to the memory location designated by S and decrements the contents of S by one. This instruction increments S by one and stores the contents of the memory designated by S in A. This instruction increments S by one and stores the contents of the memory location designated by S in PS. This instruction shifts either A or M one bit left through C. C is stored in bit 0 and bit 7 is stored in C. 48 3 1 1 09 2 2 05 3 2 IMM # OP n A # OP n 4A 1 BIT, A # OP n 1 ZP # OP n 46 5 BIT, ZP # OP n 2 # MUL M(S) • A ← A ✽ M(zz + X) S←S–1 NOP PC ← PC + 1 When T = 0 A←AVM When T = 1 M(X) ← M(X) V M ORA (Note 1) PHA M(S) ← A S←S–1 PHP M(S) ← PS S←S–1 S←S+1 A ← M(S) S←S+1 PS ← M(S) 08 3 1 PLA 68 4 1 PLP 28 4 1 ROL 7 ← 0 ←C ← 2A 1 1 26 5 2 ROR 7 C→ 0 → This instruction shifts either A or M one bit right through C. C is stored in bit 7 and bit 0 is stored in C. 6A 1 1 66 5 2 RRF 7 → S←S+1 PS ← M(S) S←S+1 PCL ← M(S) S←S+1 PCH ← M(S) 0 → This instruction rotates 4 bits of the M content to the right. 82 8 2 RTI This instruction increments S by one, and stores the contents of the memory location designated by S in PS. S is again incremented by one and stores the contents of the memory location designated by S in PC L . S is again incremented by one and stores the contents of memory location designated by S in PCH. This instruction increments S by one and stores the contents of the memory location d e s i g n a t e d b y S i n P C L. S i s a g a i n incremented by one and the contents of the memory location is stored in PC H . PC is incremented by 1. 40 6 1 RTS S←S+1 PCL ← M(S) S←S+1 PCH ← M(S) (PC) ← (PC) + 1 60 6 1 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 90 of 98 APPENDIX 7643 Group 3.7 Machine instructions Addressing mode ZP, X OP n 56 6 ZP, Y # OP n 2 ABS # OP n 4E 6 ABS, X # OP n 3 5E 7 ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 Processor status register 6 V • 5 T • 4 B • 3 D • 2 I • 1 Z Z 0 C C # OP n 3 # OP n # OP n # OP n # OP n N 0 62 14 2 N • • • • • Z • • • • • • • • • 15 4 2 0D 4 3 1D 5 3 19 5 3 01 6 2 11 6 2 N • • • • • Z • • • • • • • • • • • • • • • • • N • • • • • Z • (Value saved in stack) 36 6 2 2E 6 3 3E 7 3 N • • • • • Z C 76 6 2 6E 6 3 7E 7 3 N • • • • • Z C • • • • • • • • (Value saved in stack) • • • • • • • • Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 91 of 98 APPENDIX 7643 Group 3.7 Machine instructions Addressing mode Symbol Function Details IMP OP n SBC (Note 1) (Note 7) When T = 0 _ A←A–M–C When T = 1 _ M(X) ← M(X) – M – C When T = 0, this instruction subtracts the value of M and the complement of C from A, and stores the results in A and C. When T = 1, the instruction subtracts the contents of M and the complement of C from the contents of M(X), and stores the results in M(X) and C. A remain unchanged, but status flag are changed. M(X) represents the contents of memory where is indicated by X. This instruction sets the designated bit i of A or M. This instruction sets C. 38 1 F8 1 78 2 32 1 1 IMM # OP n E9 2 A # OP n 2 BIT, A # OP n ZP # OP n E5 3 BIT, ZP # OP n 2 # SEB Ai or Mi ← 1 C←1 D←1 I←1 T←1 M←A 0B 1 + 20i 1 0F 5 + 20i 2 SEC SED This instruction set D. 1 SEI This instruction set I. 1 SET This instruction set T. 1 85 3 2 STA This instruction stores the contents of A in M. The contents of A does not change. This instruction resets the oscillation control F/ F and the oscillation stops. Reset or interrupt input is needed to wake up from this mode. 42 2 1 STP STX M←X M←Y X←A Y←A M = 0? X←S A←X S←X A←Y This instruction stores the contents of X in M. The contents of X does not change. This instruction stores the contents of Y in M. The contents of Y does not change. This instruction stores the contents of A in X. AA 1 The contents of A does not change. This instruction stores the contents of A in Y. The contents of A does not change. This instruction tests whether the contents of M are “0” or not and modifies the N and Z. This instruction transfers the contents of S in BA 1 X. This instruction stores the contents of X in A. 8A 1 1 A8 1 1 86 3 84 3 2 STY 2 TAX TAY 1 64 3 2 TST TSX TXA 1 TXS This instruction stores the contents of X in S. 9A 1 1 TYA This instruction stores the contents of Y in A. 98 1 1 WIT The WIT instruction stops the internal clock but not the oscillation of the oscillation circuit is not stopped. CPU starts its function after the Timer X over flows (comes to the terminal count). All registers or internal memory contents except Timer X will not change during this mode. (Of course needs VDD). C2 2 1 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 92 of 98 APPENDIX 7643 Group 3.7 Machine instructions Addressing mode ZP, X OP n F5 4 ZP, Y # OP n 2 ABS # OP n ED 4 ABS, X # OP n 3 FD 5 ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 Processor status register 6 V V 5 T • 4 B • 3 D • 2 I • 1 Z Z 0 C C # OP n 3 F9 5 # OP n 3 # OP n E1 6 # OP n 2 F1 6 # OP n 2 N N • • • • • • • • • • • • • • • 1 • • • • 1 • • • • • • • • 1 • • • 95 4 2 8D 4 3 9D 5 3 99 5 3 81 6 2 91 6 2 • • • 1 • • • • • • • • • • • • • • • • • • • 96 4 94 4 2 8E 4 3 • • • • • • • • 2 8C 4 3 • • • • • • • • N • • • • • Z • N • • • • • Z • N • • • • • Z • N • • • • • Z • N • • • • • Z • • • • • • • • • N • • • • • Z • • • • • • • • • Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 93 of 98 APPENDIX 7643 Group 3.7 Machine instructions Notes 1 2 3 4 5 6 7 8 : : : : : 9 The number of cycles “n” is increased by 3 when T is 1. The number of cycles “n” is increased by 2 when T is 1. The number of cycles “n” is increased by 1 when T is 1. The number of cycles “n” is increased by 2 when branching has occurred. The number of cycles “n” is increased by 1 when branching to the same page has occurred. The number of cycles “n” is increased by 2 when branching to the other page has occurred. : The number of cycles “n” is increased by 1 when branching to the other page has occurred. : V flag is invalid in decimal operation mode. : When this instruction is executed immediately after executing DEX, DEY, INX, INY, TAX, TSX, TXA, TYA, DEC, INC, ASL, LSR, ROL, or ROR instructions, the number of cycles “n” becomes “3”. Furthermore, the number of cycles “n” is increased by 1 (number of cycles “n” is “4”) when branching to the same page has occurred. The number of cycles “n” is increased by 2 (number of cycles “n” is “5”) when branching to the other page has occurred. : When this instruction is executed immediately after executing ASL, LSR, ROL, or ROR instructions, the number of cycles “n” becomes “3”. Furthermore, the number of cycles “n” is increased by 1 (number of cycles “n” is “4”) when branching to the same page has occurred. The number of cycles “n” is increased by 2 (number of cycles “n” is “5”) when branching to the other page has occurred. Contents Implied addressing mode Immediate addressing mode Accumulator or Accumulator addressing mode Accumulator bit addressing mode Accumulator bit relative addressing mode Zero page addressing mode Zero page bit addressing mode Zero page bit relative addressing mode Zero page X addressing mode Zero page Y addressing mode Absolute addressing mode Absolute X addressing mode Absolute Y addressing mode Indirect absolute addressing mode Zero page indirect absolute addressing mode Indirect X addressing mode Indirect Y addressing mode Relative addressing mode Special page addressing mode Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag X-modified arithmetic mode flag Overflow flag Negative flag + – ✽ / V V – V – ← X Y S PC PS PCH PCL ADH ADL FF nn zz M M(X) M(S) M(ADH, ADL) Symbol Contents Addition Subtraction Multiplication Division Logical OR Logical AND Logical exclusive OR Negation Shows direction of data flow Index register X Index register Y Stack pointer Program counter Processor status register 8 high-order bits of program counter 8 low-order bits of program counter 8 high-order bits of address 8 low-order bits of address FF in Hexadecimal notation Immediate value Zero page address Memory specified by address designation of any addressing mode Memory of address indicated by contents of index register X Memory of address indicated by contents of stack pointer Contents of memory at address indicated by ADH and ADL, in ADH is 8 high-order bits and ADL is 8 low-order bits. Contents of address indicated by zero page ADL Bit i (i = 0 to 7) of accumulator Bit i (i = 0 to 7) of memory Opcode Number of cycles Number of bytes Symbol IMP IMM A BIT, A BIT, A, R ZP BIT, ZP BIT, ZP, R ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP C Z I D B T V N M(00, ADL) Ai Mi OP n # Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 94 of 98 APPENDIX 7643 Group 3.8 List of instruction code 3.8 List of instruction code D3 – D0 Hexadecimal notation 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 D7 – D4 0 1 2 3 4 5 ORA ZP ORA ZP, X AND ZP AND ZP, X EOR ZP EOR ZP, X ADC ZP ADC ZP, X STA ZP STA ZP, X LDA ZP LDA ZP, X CMP ZP CMP ZP, X SBC ZP SBC ZP, X 6 ASL ZP ASL ZP, X ROL ZP ROL ZP, X LSR ZP LSR ZP, X ROR ZP ROR ZP, X STX ZP STX ZP, Y LDX ZP LDX ZP, Y DEC ZP DEC ZP, X INC ZP INC ZP, X 7 BBS 0, ZP BBC 0, ZP BBS 1, ZP BBC 1, ZP BBS 2, ZP BBC 2, ZP BBS 3, ZP BBC 3, ZP BBS 4, ZP BBC 4, ZP BBS 5, ZP BBC 5, ZP BBS 6, ZP BBC 6, ZP BBS 7, ZP BBC 7, ZP 8 9 ORA IMM ORA ABS, Y AND IMM AND ABS, Y EOR IMM EOR ABS, Y ADC IMM ADC ABS, Y — STA ABS, Y LDA IMM LDA ABS, Y CMP IMM CMP ABS, Y SBC IMM SBC ABS, Y A ASL A DEC A ROL A INC A LSR A — ROR A — B SEB 0, A CLB 0, A SEB 1, A CLB 1, A SEB 2, A CLB 2, A SEB 3, A CLB 3, A SEB 4, A CLB 4, A SEB 5, A CLB 5, A SEB 6, A CLB 6, A SEB 7, A CLB 7, A C D ORA ABS E ASL ABS F SEB 0, ZP 0000 BRK BBS ORA JSR IND, X ZP, IND 0, A ORA IND, Y AND IND, X AND IND, Y EOR IND, X EOR IND, Y CLT JSR SP SET BBC 0, A BBS 1, A BBC 1, A BBS 2, A BBC 2, A BBS 3, A BBC 3, A BBS 4, A BBC 4, A BBS 5, A — PHP — 0001 1 BPL JSR ABS BMI — BIT ZP — COM ZP — TST ZP — STY ZP STY ZP, X LDY ZP LDY ZP, X CPY ZP — CPX ZP — CLC — BIT ABS ASL CLB ORA ABS, X ABS, X 0, ZP AND ABS ROL ABS SEB 1, ZP 0010 2 PLP 0011 3 SEC ROL CLB LDM AND ZP ABS, X ABS, X 1, ZP JMP ABS — JMP IND — STY ABS — LDY ABS EOR ABS LSR ABS SEB 2, ZP 0100 4 RTI STP PHA 0101 5 BVC — CLI LSR CLB EOR ABS, X ABS, X 2, ZP ADC ABS ROR ABS SEB 3, ZP 0110 6 RTS MUL ADC IND, X ZP, X ADC IND, Y STA IND, X STA IND, Y LDA IND, X — RRF ZP — LDX IMM PLA 0111 7 BVS SEI ROR CLB ADC ABS, X ABS, X 3, ZP STA ABS STA ABS, X LDA ABS STX ABS — LDX ABS SEB 4, ZP CLB 4, ZP SEB 5, ZP 1000 8 BRA DEY TXA 1001 9 BCC LDY IMM BCS CPY IMM BNE CPX IMM BEQ TYA TXS 1010 A TAY TAX 1011 B JMP BBC LDA IND, Y ZP, IND 5, A CMP IND, X CMP IND, Y WIT BBS 6, A BBC 6, A BBS 7, A BBC 7, A CLV TSX LDX CLB LDY LDA ABS, X ABS, X ABS, Y 5, ZP CPY ABS — CPX ABS — CMP ABS DEC ABS SEB 6, ZP 1100 C INY DEX 1101 D — CLD — DEC CLB CMP ABS, X ABS, X 6, ZP SBC ABS INC ABS SEB 7, ZP 1110 E DIV SBC IND, X ZP, X SBC IND, Y — INX NOP 1111 F SED — INC CLB SBC ABS, X ABS, X 7, ZP : 3-byte instruction : 2-byte instruction : 1-byte instruction Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 95 of 98 APPENDIX 7643 Group 3.9 SFR memory map 3.9 SFR memory map 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 CPU mode register A (CPUA) CPU mode register B (CPUB) Interrupt request register A (IREQA) Interrupt request register B (IREQB) Interrupt request register C (IREQC) Interrupt control register A (ICONA) Interrupt control register B (ICONB) Interrupt control register C (ICONC) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port control register (PTC) Interrupt polarity select register (IPOL) Port P2 pull-up control register (PUP2) USB control register (USBC) Port P6 (P6) Port P6 direction register (P6D) Port P5 (P5) Port P5 direction register (P5D) Port P4 (P4) Port P4 direction register (P4D) Port P7 (P7) Port P7 direction register (P7D) Port P8 (P8) Port P8 direction register (P8D) Reserved (Note 1) Clock control register (CCR) Reserved (Note 1) Reserved (Note 1) Reserved (Note 1) Reserved (Note 1) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Reserved (Note 1) Reserved (Note 1) Timer 123 mode register (T123M) Serial I/O shift register (SIOSHT) Serial I/O control register 1 (SIOCON1) Serial I/O control register 2 (SIOCON2) Reserved (Note 1) Reserved (Note 1) Reserved (Note 1) UART mode register (UMOD) UART baud rate generator (UBRG) UART status register (USTS) UART control register (UCON) UART transmit/receive buffer register 1 (UTRB1) UART transmit/receive buffer register 2 (UTRB2) UART RTS control register (URTSC) Reserved (Note 1) 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 Reserved (Note 1) Reserved (Note 1) Reserved (Note 1) Reserved (Note 1) Reserved (Note 1) Reserved (Note 1) Reserved (Note 1) DMAC index and status register (DMAIS) DMAC channel x mode register 1 (DMAx1) DMAC channel x mode register 2 (DMAx2) DMAC channel x source register Low (DMAxSL) DMAC channel x source register High (DMAxSH) DMAC channel x destination register Low (DMAxDL) DMAC channel x destination register High (DMAxDH) DMAC channel x transfer count register Low (DMAxCL) DMAC channel x transfer count register High (DMAxCH) Reserved (Note 1) Reserved (Note 1) Reserved (Note 1) Reserved (Note 1) Reserved (Note 1) Reserved (Note 1) Reserved (Note 1) Reserved (Note 1) USB address register (USBA) USB power management register (USBPM) USB interrupt status register 1 (USBIS1) USB interrupt status register 2 (USBIS2) USB interrupt enable register 1 (USBIE1) USB interrupt enable register 2 (USBIE2) Reserved (Note 1) Reserved (Note 1) USB endpoint index register (USBINDEX) USB endpoint x IN control register (IN_CSR) USB endpoint x OUT control register (OUT_CSR) USB endpoint x IN max. packet size register (IN_MAXP) USB endpoint x OUT max. packet size register (OUT_MAXP) USB endpoint x OUT write count register (WRT_CNT) Reserved (Note 1) USB endpoint FIFO mode register (USBFIFOMR) USB endpoint 0 FIFO (USBFIFO0) USB endpoint 1 FIFO (USBFIFO1) USB endpoint 2 FIFO (USBFIFO2) Reserved (Note 1) Reserved (Note 1) Reserved (Note 1) Reserved (Note 1) Reserved (Note 1) Reserved (Note 1) Reserved (Note 1) Flash memory control register (FMCR) (Note 2) Reserved (Note 1) Frequency synthesizer control register (FSC) Frequency synthesizer multiply register 1 (FSM1) Frequency synthesizer multiply register 2 (FSM2) Frequency synthesizer divide register (FSD) FFC916 ROM code protect control register (ROMCP) (Note 3) Notes 1: Do not write any data to this addresses, because these areas are reserved. 2: This area is reserved in the mask ROM version. 3: This area is on the ROM in the mask ROM version. Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 96 of 98 APPENDIX 7643 Group 3.10 Pin configuration 3.10 Pin configuration 59 58 57 56 55 54 53 52 60 64 63 62 61 51 50 49 48 47 46 45 44 43 42 41 P20/DB0 P21/DB1 P22/DB2 P23/DB3 P24/DB4 P25/DB5 P26/DB6 P27/DB7 P00/AB0 P01/AB1 P02/AB2 P03/AB3 P04/AB4 P05/AB5 P06/AB6 P07/AB7 P10/AB8 P11/AB9 P12/AB10 P13/AB11 P14/AB12 P15/AB13 P16/AB14 P17/AB15 P74 P73/HLDA P72 P71/HOLD P70 USB D+ USB DExt.Cap VSS VCC P67 P66 P65 P64 P63 P62 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 M37643M8-XXXFP M37643F8FP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P30/RDY P31 P32 P33/DMAOUT P34/φ OUT P35/SYNCOUT P36/WR P37/RD P80/SRDY P81/SCLK P82/SRXD P83/STXD P84/UTXD P85/URXD P86/CTS P87/RTS 19 20 21 22 13 14 15 16 18 10 11 12 P61 P60 P57 P56 P55 P54 P53 P52 CNVSS/VPP RESET P51/TOUT/XCOUT P50/XCIN VSS XIN Package type: PRQP0080GB-A (Top view) Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 97 of 98 XOUT VCC AVCC LPF AVSS P44 P43 P42/INT1 P41/INT0 P40/EDMA 17 23 24 5 6 7 8 9 3 4 1 2 APPENDIX 7643 Group 3.10 Pin configuration 59 58 57 56 55 50 49 48 54 53 52 51 47 46 45 44 43 P21/DB1 P20/DB0 P74 P73/HLDA P72 P71/HOLD P70 USB D+ USB DExt.Cap VSS VCC P67 P66 P65 P64 P63 P62 P61 P60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 60 42 41 P22/DB2 P23/DB3 P24/DB4 P25/DB5 P26/DB6 P27/DB7 P00/AB0 P01/AB1 P02/AB2 P03/AB3 P04/AB4 P05/AB5 P06/AB6 P07/AB7 P10/AB8 P11/AB9 P12/AB10 P13/AB11 P14/AB12 P15/AB13 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P16/AB14 P17/AB15 P30/RDY P31 P32 P33/DMAOUT P34/φ OUT P35/SYNCOUT P36/WR P37/RD P80/SRDY P81/SCLK P82/SRXD P83/STXD P84/UTXD P85/URXD P86/CTS P87/RTS P40/EDMA P41/INT0 M37643M8-XXXHP M37643F8HP 13 14 10 11 Rev.2.00 Aug 28, 2006 REJ09B0133-0200 page 98 of 98 P57 P56 P55 P54 P53 P52 CNVSS/VPP RESET P51/TOUT/XCOUT P50/XCIN VSS XIN XOUT VCC AVCC LPF AVSS P44 P43 P42/INT1 Package type: PLQP0080KB-A (Top view) 12 15 16 17 18 19 20 6 7 3 4 1 2 8 9 5 REVISION HISTORY Rev. Date Page 1.00 Jan 30, 2004 – First edition issued 7643 Group User’s Manual Description Summary 2.00 Aug 28, 2006 All pages Package names “80P6N-A” → “PRQP0080GB-A” revised Package names “80P6Q-A” → “PLQP0080KB-A” revised Chapter 1 52 Fig. 44 “5: To use the AUTO_SET function .... to single buffer mode.” added 61 CLOCK GENERATING CIRCUIT; “No external resistor is needed .... resistor exists on-chip.” → “No external resistor is needed .... depending on conditions.) Fig. 56; Pulled up added, NOTE added 98 UART; “•Do not update .... an undefined data might be output.”added 99 USB; “•To use the AUTO_SET function .... to single buffer mode.” added 101 Power Source Voltage added 102 USB Communication added “For the mask ROM confirmation .... http://www.infomicom.maec.co.jp/indexe.htm” → “For the mask ROM confirmation .... (http://www.renesas.com).” Chapter 2 91 2.5.6 “64-byte”, “64 bytes” → “128-byte”, “128 bytes” “USB endpoint 1” → “USB endpoint 2” 92-94 Fig. 2.5.16, Fig. 2.5.17, Fig. 2.5.18 revised 113 (8) USB endpoint 1, 2 IN control register; “(this bit is automatically set to “1” when AUTO_SET bit is “1”)” deleted 115 Fig. 2.6.14 “3: To use the AUTO_SET function .... to single buffer mode.” added 124 2.6.4 “- When AUTO_SET bit = “1”.....packet size) is transferred” deleted 165 2.6.10 (4) USB Communication added 166 (5) Registers and bits; “• To use the AUTO_SET function .... to single buffer mode.” added Chapter 3 29 3.3.5 (4) USB Communication added (5) “•To read from the USB endpoint x .... then the higher byte.” deleted 30 (5) Registers and bits; “• To use the AUTO_SET function .... to single buffer mode.” added 72 Fig. 3.5.43 “3: To use the AUTO_SET function .... to single buffer mode.” added 82, 83 3.6 Package outline revised (1/1) RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER USER’S MANUAL 7643 Group Publication Data : Published by : Rev.1.00 Jan 30, 2004 Rev.2.00 Aug 28, 2006 Sales Strategic Planning Div. Renesas Technology Corp. © 2 006. Renesas Technology Corp., All rights reserved. Printed in Japan. 7643 Group User's Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan