7905

To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER 7700 FAMILY / 7900 SERIES 7905 Group User’s Manual http://www.infomicom.maec.co.jp/indexe.htm Before using this material, please visit the above website to confirm that this is the most current document available. Rev. 1.0 Revision date: Nov. 28, 2001 Keep safety first in your circuit designs! q Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials q q q q q q q q These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http:// www.mitsubishichips.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. REVISION HISTORY Rev. 1.0 Date Page 11/28/01 — First Edition 7905 GROUP USER’S MANUAL Description Summary (1/1) Preface This manual describes the hardware of the Mitsubishi CMOS 16-bit microcomputers 7905 Group. After reading this manual, the user will be able to understand the functions, so that they can utilize their capabilities fully. For details of software, refer to the “7900 Series Software Manual.” For details of development support tools, refer to the “Mitsubishi Microcomputer Development Support Tools” Homepage (http://www.tool-spt.maec.co.jp/index_e.htm). BEFORE USING THIS MANUAL 1. Constitution This user’s manual consists of the following chapters. Refer to the chapters relevant to the products and processor mode. In this manual, “M37905” means all of or one of the 7905 Group products, unless otherwise noted. Each chapter, except for Chapter 19, describes functions of the 7905 Group product at MD0 and MD1 = Vss level. q C hapter 1. DESCRIPTION to Chapter 17. DEBUG FUNCTION Functions which are common to all products is described. q C hapter 18. APPLICATIONS Example of application are described. q C hapter 19. FLASH MEMORY VERSION Characteristics information for the flash memory version is described. q A ppendix Practical information for using the 7906 Group is described. 2. Remark q P roduct expansion Refer to the latest datasheets or catalogs. q Electrical characteristics Refer to the latest datasheets. q S oftware Refer to the “ 7900 Series Software Manual.” q D evelopment support tools Refer to the latest datasheets or catalogs. Please Visit Our Web Site. • Mitsubishi MCU Technical Information (http://www.infomicom.maec.co.jp/indexe.htm) • Mitsubishi Microcomputer Development Support Tools (http://www.tool-spt.maec.co.jp/index_e.htm) 3. Signal levels in Figure As a rule, signal levels in each operation example and timing diagram are as follows. • Signal levels The upper line indicates “1,” and the lower line indicates “0.” • Input/Output levels of pin The upper line indicates “H,” and the lower line indicates “L.” Foe the exception, the level is shown on the left side of a signal. 1 4. Register structure The view of the register structure is described below: ✽2 XXX register (address XX16) Bit 0 Bit name • • • select bit ✽1 b7 b6 b5 b4 b3 b2 b1 b0 ✽5 Function 0:… 1:… The value is “0” at reading. b2 b1 X0 At reset Undefined R/W WO ✽3 1 2 3 4 5 6 7 • • • select bit 00:… 01:… 10:… 11:… 0:… 1:… 0 0 0 0 0 Undefined 0 RW RW RO RW RW — — • • • flag Fix this bit to “0.” This bit is invalid in … mode. Nothing is assigned. The value is “0” at reading. ✽6 ✽1 Blank 0 1 ✕ ✽2 0 1 Undefined ✽3 RW RO WO : “0” immediately after reset. : “1” immediately after reset. : Undefined immediately after reset. : Set to “0” or “1” according to the usage. : Set to “0” at writing. : Set to “1” at writing. : Invalid depending on the mode or state. It may be “0” or “1.” : Nothing is assigned. ✽4 — : It is possible to read the bit state at reading. The written value becomes valid. : It is possible to read the bit state at reading. The written value becomes invalid. Accordingly, the written value may be “0” or “1.” : The written value becomes valid. It is impossible to read the bit state. The value is undefined at reading. However, when [“0” at reading”] is indicated in the “Function” or “Note” column, the bit is always “0” at reading. (See ] 5 above.) : It is impossible to read the bit state. The value is undefined at reading. However, when [“0” at reading”] is indicated in the “Function” or “Note” column, the bit is always “0” at reading. (See ] 6 above.) The written value becomes invalid. Accordingly, the written value may be “0” or “1.” ✽4 Invalid for that function or mode. 2 Table of contents Table of contents CHAPTER 1. DESCRIPTION 1.1 1.2 1.3 1.4 Performance overview .......................................................................................................... 1-2 Pin configuration ................................................................................................................... 1-3 Pin description ....................................................................................................................... 1-5 Block diagram ........................................................................................................................ 1-7 CHAPTER 2. CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (CPU) ........................................................................................... 2-2 2.1.1 Accumulator (Acc) .......................................................................................................... 2-3 2.1.2 Index register X (X) ....................................................................................................... 2-3 2.1.3 Index register Y (Y) ....................................................................................................... 2-3 2.1.4 Stack pointer (S) ............................................................................................................ 2-4 2.1.5 Program counter (PC) ................................................................................................... 2-5 2.1.6 Program bank register (PG) ......................................................................................... 2-5 2.1.7 Data bank register (DT) ................................................................................................ 2-5 2.1.8 Direct page register 0 to 3 (DPR0 to DPR3) ............................................................ 2-6 2.1.9 Processor status register (PS) ..................................................................................... 2-8 2.2 Bus interface unit (BIU) ..................................................................................................... 2-10 2.2.1 Instruction prefetch ...................................................................................................... 2-11 2.2.2 Data Transfer (read and write) .................................................................................. 2-12 2.3 Access space ....................................................................................................................... 2-14 2.4 Memory assignment ............................................................................................................ 2-15 2.4.1 Memory assignment in internal area ......................................................................... 2-15 2.5 Processor modes ................................................................................................................. 2-19 2.5.1 Single-chip mode .......................................................................................................... 2-19 2.5.2 Setting of processor mode .......................................................................................... 2-20 [Precautions for setting of processor mode] ...................................................................... 2-21 CHAPTER 3. RESET 3.1 Reset operation ...................................................................................................................... 3-2 3.1.1 Hardware reset ............................................................................................................... 3-2 3.1.2 Software reset ................................................................................................................ 3-3 3.1.3 Power-on reset ............................................................................................................... 3-4 3.2 Pin state .................................................................................................................................. 3-5 3.3 State of internal area ............................................................................................................ 3-6 3.4 Internal processing sequence after reset ...................................................................... 3-15 CHAPTER 4. CLOCK GENERATING CIRCUIT 4.1 Oscillation circuit examples ............................................................................................... 4-2 4.1.1 Connection example with resonator/oscillator ............................................................ 4-2 4.1.2 Externally generated clock input example .................................................................. 4-2 4.1.3 Connection example of filter circuit ............................................................................. 4-3 7 905 Group User’s Manual Rev.1.0 i Table of contents 4.2 Clocks ...................................................................................................................................... 4-4 4.2.1 Clocks generated in clock generating circuit ............................................................. 4-5 4.2.2 Clock control register 0 ................................................................................................. 4-6 4.2.3 Particular function select register 0 ............................................................................. 4-9 [Precautions for clock generating circuit] ........................................................................... 4-11 CHAPTER 5. INPUT/OUTPUT PINS 5.1 Overview .................................................................................................................................. 5-2 5.2 Programmable I/O ports ....................................................................................................... 5-2 5.2.1 Direction register ............................................................................................................ 5-3 5.2.2 Port register .................................................................................................................... 5-4 5.2.3 Pin P4OUT CUT/INT0 ( Port-P4-output-cutoff signal input pin) ..................................... 5-7 5.2.4 Pin P6OUT CUT/INT4 ( Port-P6-output-cutoff signal input pin) ..................................... 5-7 5.3 Examples of handling unused pins .................................................................................. 5-8 CHAPTER 6. INTERRUPTS 6.1 Overview .................................................................................................................................. 6-2 6.2 Interrupt sources ................................................................................................................... 6-3 6.3 Interrupt control ..................................................................................................................... 6-5 6.3.1 Interrupt disable flag (I) ................................................................................................ 6-7 6.3.2 Interrupt request bit ....................................................................................................... 6-7 6.3.3 Interrupt priority level select bits and Processor interrupt priority level (IPL) ...... 6-7 6.4 Interrupt priority level .......................................................................................................... 6-9 6.5 Interrupt priority level detection circuit ......................................................................... 6-10 6.6 Interrupt priority level detection time ............................................................................ 6-12 6.7 Sequence from acceptance of interrupt request until execution of interrupt routine ... 6-13 6.7.1 Change in IPL at acceptance of interrupt request .................................................. 6-14 6.7.2 Push operation for registers ....................................................................................... 6-15 6.8 Return from interrupt routine ........................................................................................... 6-16 6.9 Multiple interrupts ............................................................................................................... 6-16 6.10 External interrupts ............................................................................................................ 6-18 6.10.1 INTi i nterrupt ............................................................................................................... 6-18 6.10.2 Functions of INTi i nterrupt request bit .................................................................... 6-20 6.10.3 Switching of INTi t o interrupt request occurrence factor ...................................... 6-21 [Precautions for interrupts] ..................................................................................................... 6-22 CHAPTER 7. TIMER A 7.1 Overview .................................................................................................................................. 7-2 7.2 Block description .................................................................................................................. 7-3 7.2.1 Counter and Reload register (timer Ai register) ........................................................ 7-4 7.2.2 Timer A clock division select register ......................................................................... 7-5 7.2.3 Count start register ........................................................................................................ 7-6 7.2.4 Timer Ai mode register ................................................................................................. 7-7 7.2.5 Timer Ai interrupt control register ................................................................................ 7-8 7.2.6 Port P2, port P4 and port P6 direction registers ...................................................... 7-9 7.3 Timer mode ........................................................................................................................... 7-11 7.3.1 Setting for timer mode ................................................................................................ 7-13 7.3.2 Operation in timer mode ............................................................................................. 7-14 ii 7 905 Group User’s Manual Rev.1.0 Table of contents 7.3.3 Select function .............................................................................................................. 7-15 [Precautions for timer mode] .................................................................................................. 7-17 7.4 Event counter mode ........................................................................................................... 7-18 7.4.1 Setting for event counter mode ................................................................................. 7-21 7.4.2 Operation in event counter mode .............................................................................. 7-23 7.4.3 Switching between countup and countdown ............................................................ 7-24 7.4.4 Selectable functions ..................................................................................................... 7-26 [Precautions for event counter mode] .................................................................................. 7-28 7.5 One-shot pulse mode ......................................................................................................... 7-29 7.5.1 Setting for one-shot pulse mode ............................................................................... 7-31 7.5.2 Trigger ........................................................................................................................... 7-33 7.5.3 Operation in one-shot pulse mode ............................................................................ 7-35 [Precautions for one-shot pulse mode] ................................................................................ 7-37 7.6 Pulse width modulation (PWM) mode ............................................................................ 7-38 7.6.1 Setting for PWM mode ................................................................................................ 7-41 7.6.2 Trigger ........................................................................................................................... 7-43 7.6.3 Operation in PWM mode ............................................................................................. 7-44 [Precautions for pulse width modulation (PWM) mode] ................................................... 7-48 CHAPTER 8. TIMER B 8.1 Overview .................................................................................................................................. 8-2 8.2 Block description .................................................................................................................. 8-2 8.2.1 Counter and Reload register (timer Bi register) ........................................................ 8-3 8.2.2 Count start register ........................................................................................................ 8-4 8.2.3 Timer Bi mode register ................................................................................................. 8-4 8.2.4 Timer Bi interrupt control register ................................................................................ 8-5 8.2.5 Port P2 direction register, Port P5 direction register ............................................... 8-6 8.2.6 Count source (in timer mode and pulse period/pulse width measurement mode) ......... 8-7 8.3 Timer mode ............................................................................................................................. 8-8 8.3.1 Setting for timer mode ................................................................................................ 8-10 8.3.2 Operation in timer mode ............................................................................................. 8-11 [Precautions for timer mode] .................................................................................................. 8-12 8.4 Event counter mode ........................................................................................................... 8-13 8.4.1 Count source ................................................................................................................ 8-15 8.4.2 Setting for event counter mode ................................................................................. 8-16 8.4.3 Operation in event counter mode .............................................................................. 8-17 [Precautions for event counter mode] .................................................................................. 8-18 8.5 Pulse period/Pulse width measurement mode ............................................................. 8-19 8.5.1 Setting for pulse period/pulse width measurement mode ...................................... 8-22 8.5.2 Operation in pulse period/pulse width measurement mode ................................... 8-23 [Precautions for pulse period/pulse width measurement mode] .................................... 8-29 CHAPTER 9. PULSE OUTPUT PORT MODE 9.1 Overview .................................................................................................................................. 9-2 9.2 Block description of pulse output port 0 ........................................................................ 9-4 9.2.1 Waveform output mode register ................................................................................... 9-5 9.2.2 Three-phase output data registers 0, 1 ...................................................................... 9-8 9.2.3 Port P5 direction register ............................................................................................ 9-11 9.2.4. Timers A0 to A4 .......................................................................................................... 9-12 9.2.5. Pin P6OUT CUT ( pluse-output-cutoff signal input pin) .............................................. 9-14 7 905 Group User’s Manual Rev.1.0 iii Table of contents 9.3 Block description of pulse output port 1 ...................................................................... 9-15 9.3.1 Pluse output control register ...................................................................................... 9-16 9.3.2 Pulse output data registers 0, 1 ................................................................................ 9-19 9.3.3 Port P5 direction register ............................................................................................ 9-22 9.3.4. Timers A5 to A9 .......................................................................................................... 9-23 9.3.5. Pin P4OUT CUT ( pulse-output-cutoff signal input pin) .............................................. 9-25 9.4 Setting of pulse output port mode ................................................................................. 9-26 9.5 Pulse output port mode operation .................................................................................. 9-31 9.5.1 Pulse output trigger ..................................................................................................... 9-31 9.5.2 Operation at internal trigger ....................................................................................... 9-32 9.5.3 Operation at external trigger ...................................................................................... 9-35 [Precautions for pulse output mode] .................................................................................... 9-36 CHAPTER 10. THERR-PHASE WAVEFORM MODE 10.1 Overview .............................................................................................................................. 10-2 10.2 Block description .............................................................................................................. 10-4 10.2.1 Waveform output mode register ............................................................................... 10-5 10.2.2 Dead-time timer register ........................................................................................... 10-7 10.2.3 Three-phase output data register 0 ......................................................................... 10-9 10.2.4 Three-phase output data register 1 ....................................................................... 10-10 10.2.5 Position-data-retain function control register ........................................................ 10-12 10.2.6 Port P5 direction register ........................................................................................... 10-13 10.2.7 Timers A0 through A2 ............................................................................................. 10-13 10.2.8 Timer A3 .................................................................................................................... 10-15 10.2.9 Output polarity set toggle flip-flop ......................................................................... 10-16 10.2.10 Three-phase waveform mode I/O pins ................................................................ 10-17 10.2.11 Pin P6OUT CUT (three-phase waveform-output-forcibly-cutoff signal input pin) .. 10-17 10.3 Three-phase mode 0 ....................................................................................................... 10-18 10.3.1 Setting for three-phase mode 0 ............................................................................. 10-18 10.3.2 Operation in three-phase wave mode 0 ............................................................... 10-22 10.4 Three-phase mode 1 ....................................................................................................... 10-27 10.4.1 Setting for three-phase mode 1 ............................................................................. 10-27 10.4.2 Operation in three-phase wave mode 1 ............................................................... 10-31 10.5 Three-phase waveform output fixation ...................................................................... 10-34 10.6 Position-data-retain function ........................................................................................ 10-36 10.6.1 Operation of position-data-retain function ............................................................. 10-36 [Precautions for three-phase waveform mode] ................................................................. 10-37 CHAPTER 11. SERIAL I/O 11.1 Overview .............................................................................................................................. 11-2 11.2 Block description .............................................................................................................. 11-3 11.2.1 UARTi transmit/receive mode register .................................................................... 11-4 11.2.2 UARTi transmit/receive control register 0 ............................................................... 11-6 11.2.3 UARTi transmit/receive control register 1 ............................................................... 11-8 11.2.4 UARTi transmit register and UARTi transmit buffer register ............................. 11-10 11.2.5 UARTi receive register and UARTi receive buffer register ................................ 11-12 11.2.6 UARTi baud rate register (BRGi) ........................................................................... 11-14 11.2.7 UARTi transmit interrupt control and UARTi receive interrupt control registers . 11-15 11.2.8 Serial I/O pin control register ................................................................................. 11-17 11.2.9 Port P1 direction register, port P8 direction register .......................................... 11-18 iv 7 905 Group User’s Manual Rev.1.0 Table of contents 11.2.10 CTS/RTS function .................................................................................................. 11-19 11.3 Clock synchronous serial I/O mode ........................................................................... 11-21 11.3.1 Transfer clock (Synchronizing clock) ..................................................................... 11-21 11.3.2 Transfer data format ................................................................................................ 11-23 11.3.3 Method of transmission ........................................................................................... 11-24 11.3.4 Transmit operation ................................................................................................... 11-27 11.3.5 Method of reception ................................................................................................. 11-29 11.3.6 Receive operation .................................................................................................... 11-32 11.3.7 Processing on detecting overrun error .................................................................. 11-35 [Precautions for clock synchronous serial I/O mode] .................................................... 11-36 11.4 Clock asynchronous serial I/O (UART) mode ........................................................... 11-37 11.4.1 Transfer rate (Frequency of transfer clock) ......................................................... 11-38 11.4.2 Transfer data format ................................................................................................ 11-40 11.4.3 Method of transmission ........................................................................................... 11-41 11.4.4 Transmit operation ................................................................................................... 11-45 11.4.5 Method of reception ................................................................................................. 11-48 11.4.6 Receive operation .................................................................................................... 11-51 11.4.7 Processing on detecting error ................................................................................ 11-53 11.4.8 Sleep mode ............................................................................................................... 11-54 [Precautions for clock asynchronous serial I/O (UART) mode] .................................... 11-55 CHAPTER 12. A-D CONVERTER 12.1 Overview .............................................................................................................................. 12-2 12.2 Block description .............................................................................................................. 12-4 12.2.1 A-D control registers 0, 1, and 2 ............................................................................ 12-5 12.2.2 A-D register i (i = 0 to 11) ..................................................................................... 12-10 12.2.3 Comparator function select register 0, 1 and comparator result register 0, 1 ............. 12-12 12.2.4 A-D conversion interrupt control register .............................................................. 12-14 12.2.5 Port P7 direction register, port P8 direction register .......................................... 12-15 12.3 A-D conversion method ................................................................................................. 12-16 12.4 Absolute accuracy and Differential non-linearity error .......................................... 12-19 12.4.1 Absolute accuracy .................................................................................................... 12-19 12.4.2 Differential non-linearity error ................................................................................. 12-20 12.5 Comparison voltage in 8-bit resolution mode .......................................................... 12-21 12.6 Comparator function ....................................................................................................... 12-22 12.7 One-shot mode ................................................................................................................. 12-23 12.7.1 Settings for one-shot mode .................................................................................... 12-23 12.7.2 One-shot mode operation ....................................................................................... 12-25 12.8 Repeat mode ..................................................................................................................... 12-26 12.8.1 Settings for repeat mode ........................................................................................ 12-26 12.8.2 Repeat mode operation ........................................................................................... 12-28 12.9 Single sweep mode ......................................................................................................... 12-29 12.9.1 Settings for single sweep mode ............................................................................ 12-29 12.9.2 Single sweep mode operation ................................................................................ 12-31 12.10 Repeat sweep mode 0 .................................................................................................. 12-32 12.10.1 Settings for repeat sweep mode 0 ...................................................................... 12-32 12.10.2 Repeat sweep mode 0 operation ........................................................................ 12-34 12.11 Repeat sweep mode 1 .................................................................................................. 12-35 12.11.1 Settings for repeat sweep mode 0 ...................................................................... 12-35 12.11.2 Repeat sweep mode 1 operation ........................................................................ 12-39 [Precautions for A-D converter] ............................................................................................ 12-40 7 905 Group User’s Manual Rev.1.0 v Table of contents CHAPTER 13. D-A CONVERTER 13.1 Overview .............................................................................................................................. 13-2 13.2 Block description .............................................................................................................. 13-2 13.2.1 D-A control register ................................................................................................... 13-3 13.2.2 D-A Register i (i = 0, 1) ........................................................................................... 13-3 13.3 D-A conversion method ................................................................................................... 13-4 13.4 Setting method ................................................................................................................... 13-5 13.5 Operation description ....................................................................................................... 13-5 [Precautions for D-A converter] .............................................................................................. 13-6 CHAPTER 14. WATCHDOG TIMER 14.1 Block description .............................................................................................................. 14-2 14.1.1 Watchdog timer .......................................................................................................... 14-3 14.1.2 Watchdog timer frequency select register .............................................................. 14-3 14.1.3 Particular function select register 2 ......................................................................... 14-4 14.2 Operation description ....................................................................................................... 14-5 14.2.1 Basic operation ........................................................................................................... 14-5 14.2.2 Stop period ................................................................................................................. 14-7 14.2.3 Operations in stop mode .......................................................................................... 14-7 [Precautions for watchdog timer] ........................................................................................... 14-8 CHAPTER 15. STOP AND WAIT MODES 15.1 Overview .............................................................................................................................. 15-2 15.2 Block description .............................................................................................................. 15-3 15.2.1 Particular function select register 0 ......................................................................... 15-4 15.2.2 Particular function select register 1 ......................................................................... 15-6 15.2.3 Watchdog timer frequency select register .............................................................. 15-7 15.3 Stop mode ........................................................................................................................... 15-8 15.3.1 Terminate operation at interrupt request occurrence (when using watchdog timer) ... 15-8 15.3.2 Terminate operation at interrupt request occurrence (when not using watchdog timer) 15-9 15.3.3 Terminate operation at hardware reset ................................................................. 15-11 15.4 Wait mode ......................................................................................................................... 15-12 15.4.1 Terminate operation at interrupt request occurrence .......................................... 15-12 15.4.2 Terminate operation at hardware reset ................................................................. 15-12 CHAPTER 16. POWER SAVING FUNCTIONS 16.1 Overview .............................................................................................................................. 16-2 16.1.1 Particular function select register 0 ......................................................................... 16-3 16.1.2 Particular function select register 1 ......................................................................... 16-5 16.2 I nactivity of system clock in wait mode ....................................................................... 16-6 16.3 Stop of oscillation circuit ................................................................................................ 16-7 16.4 Pin VREF d isconnection ..................................................................................................... 16-7 CHAPTER 17. DEBUG FUNCTION 17.1 Overview .............................................................................................................................. 17-2 vi 7 905 Group User’s Manual Rev.1.0 Table of contents 17.2 Block description .............................................................................................................. 17-2 17.2.1 Debug control register 0 ........................................................................................... 17-3 17.2.2 Debug control register 1 ........................................................................................... 17-4 17.2.3 Address compare registers 0 and 1 ........................................................................ 17-5 17.3 Address matching detection mode ............................................................................... 17-6 17.3.1 Setting procedure for address matching detection mode ..................................... 17-6 17.3.2 Operations in address matching detection mode .................................................. 17-7 17.4 Out-of-address-area detection mode ............................................................................... 17-10 17.4.1 Setting procedure for out-of-address-area detection mode ............................... 17-10 17.4.2 Operations in out-of-address-area detection mode ............................................. 17-11 [Precautions for debug function] ......................................................................................... 17-12 CHAPTER 18. APPLICATIONS 18.1 Application examples of A-D converter ....................................................................... 18-2 18.1.1 Application example of A-D converter, using single sweep mode with pins AN 0 to AN11 .. 18-2 CHAPTER 19. FLASH MEMORY VERSION 19.1 Overview .............................................................................................................................. 19-2 19.1.1 Memory assignment ................................................................................................... 19-4 19.1.2 Single-chip mode ........................................................................................................ 19-6 19.1.3 Boot mode ................................................................................................................... 19-8 19.2 Flash memory CPU reprogramming mode .................................................................. 19-9 19.2.1 Flash memory control register ............................................................................... 19-10 19.2.2 Status register .......................................................................................................... 19-12 19.2.3 Setting and Terminate procedure for flash memory CPU reprogramming mode ..... 19-13 19.2.4 Software commands ................................................................................................ 19-14 19.2.5 Full status check ...................................................................................................... 19-16 19.2.6 Electrical characteristics .......................................................................................... 19-17 [Precautions for flash memory CPU reprogramming mode] ......................................... 19-18 19.3 Flash memory serial I/O mode ..................................................................................... 19-19 19.3.1 Pin description .......................................................................................................... 19-19 19.3.2 Example of handling control pins in flash memory serial I/O mode ................ 19-23 [Precautions for flash memory serial I/O mode] .............................................................. 19-25 19.4 Flash memory parallel I/O mode ................................................................................. 19-26 [Precautions for flash memory parallel I/O mode] ........................................................... 19-27 APPENDIX Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix 1. Memory assignment in SFR area .................................................................... 20-2 2. Control registers ............................................................................................... 20-10 3. Package outline ................................................................................................. 20-52 4. Examples of handling unused pins .............................................................. 20-53 5. Hexadecimal instruction code table ............................................................. 20-54 6. Machine instructions ........................................................................................ 20-62 7. Countermeasure against noise .................................................................... 20-104 8. 7905 Group Q & A .......................................................................................... 20-110 9. M37905M4C-XXXFP electrical characteristics .......................................... 20-117 10. M37905M4C-XXXFP Standard characteristics ........................................ 20-126 11. Memory assignment of 7905 Group ......................................................... 20-131 7 905 Group User’s Manual Rev.1.0 vii Blank Page CHAPTER 1 DESCRIPTION 1.1 1.2 1.3 1.4 Performance overview Pin configuration Pin description Block diagram DESCRIPTION 1.1 Performance overview 1.1 Performance overview Table 1.1.1 lists the performance overview of the M37905M4C-XXXFP/SP. Table 1.1.1 M37905M4C-XXXFP/SP performance overview Items Number of basic instructions Instruction execution time External clock input frequency f(XIN) System clock frequency f(fsys) Memory sizes ROM RAM Programmable P1, P2, P4, P6, P7 Input/Output ports P5 P8 Multifunctional TA0–TA9 timer TB0–TB2 Serial I/O UART0, UART1, UART2 A-D converter D-A converter Watchdog timer Interrupt Maskable Performance 203 50 ns (the minimum instruction at f(fsys) = 20 MHz) 20 MHz (maximum) 20 MHz (maximum) 32 Kbyte 1024 bytes 8 bits ✕ 5 6 bits ✕ 1 4 bits ✕ 1 16 bits ✕ 10 16 bits ✕ 3 (UART or clock synchronous serial I/O) ✕ 3 10-bit successive approximation method ✕ 1 (12 channels) 8 bits ✕ 2 12 bits ✕ 1 8 external, 20 internal (Any of priority levels 0 through 7 can be set for each interrupt, by software.) Non-maskable 3 internal Clock generating circuit Built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) PLL frequency multiplier Double, Triple, or Quadruple Power source voltage 5 V ± 0.5 V Power dissipation 125 mW (at f(fsys) = 20 MHz Port Input/Output Input/Output withstand voltage 5 V characteristics Output current 5 mA Memory expansion Not available. (Single-chip mode only) Operating ambient temperature range –20 °C to 85 °C Device structure CMOS high-performance silicon gate process Package M37905M4C-XXXFP 64-pin plastic molded QFP (64P6N-A) M37905M4C-XXXSP 64-pin shrink plastic molded SDIP (64P4B) 1-2 7905 Group User’s Manual Rev.1.0 DESCRIPTION 1.2 Pin configuration 1.2 Pin configuration Figure 1.2.1 shows the M37905M4C-XXXSP pin configuration, and Figure 1.2.2 shows the M37905M4CXXXFP pin configuration. (Note) P83/AN11/TXD2 P82/AN10/RXD2 P8 1/AN9/CTS2/CLK2 P80/AN8/CTS2/RTS2/DA1 P77/AN7/DA0 P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 P67/TA3IN/RTP13 P66/TA3OUT/RTP12 P65/TA2IN/U/RTP11 P64/TA2OUT/V/RTP10 P63/TA1IN/W/RTP03 P62/TA1OUT/U/RTP02 P61/TA0IN/V/RTP01 P60/TA0OUT/W/RTP00 P57/INT7/TB2IN/IDU P56/INT6/TB1IN/IDV P55/INT5/TB0IN/IDW P6OUTCUT/INT4 MD0 RESET XIN XOUT VCONT Vss P53/INT3/RTPTRG0 P52/INT2/RTPTRG1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Vss AVss VREF AVcc Vcc P10/CTS0/RTS0 P11/CTS0/CLK0 P12/RXD0 P13/TXD0 P14/CTS1/RTS1 P15/CTS1/CLK1 P16/RXD1 P17/TXD1 P20/TA4OUT P21/TA4IN P22/TA9OUT P23/TA9IN P24(/TB0IN) P25(/TB1IN) P26(/TB2IN) P27 MD1 P40/TA5OUT/RTP20 P41/TA5IN/RTP21 P42/TA6OUT/RTP22 P43/TA6IN/RTP23 P44/TA7OUT/RTP30 P45/TA7IN/RTP31 P46/TA8OUT/RTP32 P47/TA8IN/RTP33 P4OUTCUT/INT0 P51/INT1 (Note) Note: Allocation of pins TB0IN to TB2IN can be switched by software. Outline 64P4B Fig. 1.2.1 M37905M4C-XXXSP pin configuration (outline 64P4B, top view) 7905 Group User’s Manual Rev.1.0 1-3 DESCRIPTION 1.2 Pin configuration P73/AN3 P72/AN2 P71/AN1 P70/AN0 P67/TA3IN/RTP13 P66/TA3OUT/RTP12 P65/TA2IN/U/RTP11 P64/TA2OUT/V/RTP10 P63/TA1IN/W/RTP03 P62/TA1OUT/U/RTP02 P61/TA0IN/V/RTP01 P60/TA0OUT/W/RTP00 P57/INT7/TB2IN/IDU P56/INT6/TB1IN/IDV P55/INT5/TB0IN/IDW P6OUTCUT/INT4 P74/AN4 P75/AN5 P76/AN6 P77/AN7/DA0 P80/AN8/CTS2/RTS2/DA1 P81/AN9/CTS2/CLK2 P82/AN10/RXD2 P83/AN11/TXD2 Vss AVss VREF AVcc Vcc P10/CTS0/RTS0 P11/CTS0/CLK0 P12/RXD0 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P13/TXD0 P14/CTS1/RTS1 P15/CTS1/CLK1 P16/RXD1 P17/TXD1 P20/TA4OUT P21/TA4IN P22/TA9OUT P23/TA9IN P24(/TB0IN) P25(/TB1IN) P26(/TB2IN) P27 MD1 P40/TA5OUT/RTP20 P41/TA5IN/RTP21 (Note) (Note) MD0 RESET XIN XOUT VCONT Vss P53/INT3/RTPTRG0 P52/INT2/RTPTRG1 P51/INT1 Outline 64P6N-A Fig. 1.2.2 M37905M4C-XXXFP pin configuration (outline 64P6N-A, top view) 1-4 7905 Group User’s Manual Rev.1.0 P4OUTCUT/INT0 P47/TA8IN/RTP33 P46/TA8OUT/RTP32 P45/TA7IN/RTP31 P44/TA7OUT/RTP30 P43/TA6IN/RTP23 P42/TA6OUT/RTP22 Note: Allocation of pins TB0IN to TB2IN can be switched by software. DESCRIPTION 1.3 Pin description 1.3 Pin description Tables 1.3.1 and 1.3.2 list the pin description. Table 1.3.1 Pin description (1) Pin Vcc, Vss MD0 MD1 RESET XIN MD0 MD1 Reset input Clock input Input Input Name Power source input Input/Output — Input Function Apply 5 V ± 0.5 V to pin Vcc and 0 V to pin Vss. This pin switches the operating mode. This is only for the single-chip mode, so connect this pin to V SS. The microcomputer is reset when “L” level is input to this pin. Pins X IN a nd X OUT a re the input and output pins of the clock generating circuit, respectively. Connect these pins via a XOUT VCONT AVcc AVss VREF P1 0–P17 Reference voltage input I/O port P1 Input I/O Clock output Filter circuit connection Analog power source input Output — — ceramic resonator or a quartz-crystal oscillator. When an external clock is input, this clock should be input to pin X IN, and pin X OUT s hould be left open. To use the PLL frequency multiplier, be sure to connect this pin to the filter circuit. The power source input pin for the A-D converter. Connect this pin to Vcc. The power source input pin for the A-D and D-A converters. Connect this pin to Vss. This is the reference voltage input pin for the A-D and D-A converters. P0 is an 8-bit CMOS I/O port and has an I/O direction register. Each pin can function as an input or output port pin. By software, these pins can function as I/O pins for serial I/O. P2 0–P27 I/O port P2 I/O P2 is an 8-bit I/O port with the same function as port P1. By software, these pins can function as I/O pins for timers A4 and A9. Also, these pins can function as input pins for timers B0 to B2. P40–P47 I/O port P4 I/O P4 is an 8-bit I/O port with the same function as port P1. By software, these pins can function as I/O pins for timers A5 to A8, or as motor drive waveform output pins. P5 1–P5 3, P55–P57 I/O port P5 I/O P5 is a 6-bit I/O port with the same function as port P1. By software, these pins can function as input pins for timers B0 to B2, input pins for external interrupts, position data input pins in the three-phrase waveform mode, or trigger input pins in the pulse output port mode. P60–P67 I/O port P6 I/O P6 is an 8-bit I/O port with the same function as port P1. By software, these pins can function as I/O pins for timers A0 to A3, or as motor drive waveform output pins. 7905 Group User’s Manual Rev.1.0 1-5 DESCRIPTION 1.3 Pin description Table 1.3.2 Pin description (2) Pin P7 0–P77 Name I/O port P7 Input/Output I/O Function P7 is an 8-bit I/O port with the same function as port P1. By software, these pins can function as input pins for the A-D converter, or output pins for the D-A converter. P80–P83 I/O port P8 I/O P8 is a 4-bit I/O port with the same function as port P1. By software, these pins can function as input pins for the A-D converter, output pins for the D-A converter, or as I/O pins for serial I/O. P4OUTCUT P4OUT CUT input Input This pin has the function to forcibly place port P4 pins in the input mode (port-output-cutoff function). Also, this pin functions as an input pin for INT0, and as an input pin for the port-outputcutoff function in the motor drive waveform output mode. P6OUTCUT P6OUT CUT input Input This pin has the function to forcibly place port P6 pins in the input mode (port-output-cutoff function). Also, this pin functions as an input pin for INT4, and as an input pin for the port-outputcutoff function in the motor drive waveform output mode. 1-6 7905 Group User’s Manual Rev.1.0 DESCRIPTION 1.4 Block diagram 1.4 Block diagram Figure 1.4.1 shows the M37905 block diagram. Data Bus (Even) Data Bus (Odd) Data Buffer DQ0 (8) Data Buffer DQ1 (8) Data Buffer DQ2 (8) Data Buffer DQ3 (8) Address Bus Instruction Queue Buffer Q0 (8) P6OUTCUT Instruction Queue Buffer Q1 (8) Instruction Queue Buffer Q2 (8) Instruction Queue Buffer Q3 (8) P4OUTCUT Instruction Queue Buffer Q4 (8) Instruction Queue Buffer Q5 (8) Reference voltage input VREF Instruction Queue Buffer Q6 (8) D-A1 converter (8) Instruction register (8) Instruction Queue Buffer Q7 (8) Instruction Queue Buffer Q8 (8) Instruction Queue Buffer Q9 (8) AVCC A-D converter (12) D-A0 converter (8) Incrementer (24) (0V) AVSS Program Address Register PA (24) Data Address Register DA (24) Bus Interface Unit (BIU) Incrementer/Decrementer (24) Program Counter PC (16) Watchdog timer Timer TB2 (16) Timer TB1 (16) Timer TB0 (16) MD0 Program Bank Register PG (8) Data bank Register DT (8) (0V) VSS Input Buffer Register IB (16) Timer TA9 (16) Timer TA8 (16) Timer TA7 (16) Timer TA6 (16) Timer TA5 (16) VCC Direct Page Register DPR0 (16) Direct Page Register DPR1 (16) Timer TA4 (16) Timer TA3 (16) Timer TA2 (16) Timer TA1 (16) Timer TA0 (16) P5(6) Processor Status Register PS (11) Reset input RESET Direct Page Register DPR3 (16) Stack Pointer S (16) Clock output XOUT Clock Generating Circuit Index Register X (16) Accumulator B (16) Accumulator A (16) Clock input XIN VCONT Arithmetic Logic Unit (16) Fig. 1.4.1 M37905 block diagram 7905 Group User’s Manual Rev.1.0 Input/Output port P8 ROM P8(4) Input/Output port P7 Index Register Y (16) Central Processing Unit (CPU) RAM P7(8) P6(8) Direct Page Register DPR2 (16) Input/Output port P6 Input/Output port P5 Input/Output port P4 P4(8) Input/Output port P2 UART2 (9) UART1 (9) UART0 (9) MD1 P2(8) Input/Output port P1 P1(8) 1-7 DESCRIPTION 1.4 Block diagram MEMORANDUM 1-8 7905 Group User’s Manual Rev.1.0 CHAPTER 2 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (CPU) 2.2 Bus interface unit (BIU) 2.3 Access space 2.4 Memory assignment 2.5 Processor modes [Precautions for setting of processor mode] CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (CPU) 2.1 Central processing unit (CPU) The CPU (Central Processing Unit) has 13 registers shown in Figure 2.1.1. b15 b8 b7 b0 AH b15 b8 b7 b0 AL Accumulator A (A) Accumulator B (B) b0 BH b31 BL E b15 b8 b7 b0 Accumulator E (E) Index register X (X) b0 XH b15 b8 b7 XL YH b15 b8 b7 YL b0 Index register Y (Y) Stack pointer (S) Data bank register (DT) SH b7 b0 SL DT b23 b16 b15 b8 b7 b0 PG b7 b0 PCH PCL Program counter (PC) Program bank register (PG) b15 b8 b7 b0 DPR0H b15 b8 b7 DPR0L b0 Direct page register 0 (DPR0) Direct page register 1 (DPR1) b0 DPR1H b15 b8 b7 DPR1L DPR2H b15 b8 b7 DPR2L b0 Direct page register 2 (DPR2) Direct page register 3 (DPR3) b0 DPR3H b15 b8 b7 DPR3L PSL PSH Processor status register (PS) b15 b10 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 IPL NVm x D I Z C Carry flag Zero flag Interrupt disable flag Decimal mode flag Index register length flag Data length flag Overflow flag Negative flag Processor interrupt priority level Fig. 2.1.1 CPU registers 2-2 7 905 Group User’s Manual Rev.1.0 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (CPU) 2.1.1 Accumulator (Acc) Accumulators A and B are available. Also, accumulators A and B can be connected in series in order to be used as a 32-bit accumulator (accumulator E). (1) Accumulator A (A) Accumulator A is the main register of the microcomputer. The transaction of data such as calculation, data transfer, and input/output are performed mainly through accumulator A. It consists of 16 bits, and the low-order 8 bits can also be used separately. The data length flag (m) determines whether the register is used as a 16-bit register or as an 8-bit register. Flag m is a part of the processor status register, which is described later. When an 8-bit register is selected, only the low-order 8 bits of accumulator A are used, and the contents of the high-order 8 bits is unchanged. (2) Accumulator B (B) Accumulator B is a 16-bit register with the same function as accumulator A. Accumulator B can be used instead of accumulator A. The use of accumulator B, however except for some instructions, requires more instruction bytes and execution cycles than those of accumulator A. Accumulator B is also affected by flag m just as in accumulator A. (3) Accumulator E (E) This 32-bit accumulator consists of accumulator A located in the low-order 16 bits and accumulator B located in the high-order 16 bits. This accumulator is used by an instruction that handles 32-bit data. It is not affected by flag m. 2.1.2 Index register X (X) Index register X consists of 16 bits and the low-order 8 bits can also be used separately. The index register length flag (x) determines whether the register is used as a 16-bit register or as an 8-bit register. Flag x is a part of the processor status register, which is described later. When an 8-bit register is selected, only the low-order 8 bits of index register X are used, and the contents of the high-order 8 bits are not unchanged. In an addressing mode in which index register X is used as an index register, the address obtained by adding the contents of this register to the operand ’ s contents is accessed. Also, each of the M VP , M VN a nd R MPA i nstructions uses index register X. ❈ R efer to “ 7900 Series Software Manual” f or addressing modes and instructions. 2.1.3 Index register Y (Y) Index register Y is a 16-bit register with the same function as index register X. Just as in index register X, this register is affected by flag X. 7 905 Group User ’ s Manual Rev.1.0 2-3 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (CPU) 2.1.4 Stack pointer (S) The stack pointer (S) is a 16-bit register. It is used for a subroutine call or an interrupt. It is also used when addressing modes using the stack are executed. The contents of S indicate an address (stack area) for storing registers during subroutine calls and interrupts. Bank 016 is specified for the stack area. (Refer to section “ 2.3 Access space.” ) When an interrupt request is accepted, the microcomputer stores the contents of the program bank register (PG) at the address indicated by the contents of S and decrements the contents of S by 1. Then the contents of the program counter (PC) and the processor status register (PS) are stored. The contents of S after accepting an interrupt request is equal to the contents of S decremented by 5 before accepting of the interrupt request. (See Figure 2.1.2.) When completing the process in the interrupt routine and returning to the original routine, the contents of Stack area registers stored in the stack area are restored into Address the original registers in the reverse sequence S–5 (PS→PC→PG) by executing the RTI instruction. The contents of S is returned to the state before accepting S–4 Processor status register’s low-order byte (PSL) an interrupt request. S–3 Processor status register’s high-order byte (PSH) The same operation is performed during a subroutine Program counter’s low-order byte (PCL) S–2 call, however, the contents of PS is not automatically stored. (The contents of PG may not be stored. Program counter’s high-order byte (PCH) S–1 This depends on the addressing mode.) Program bank register (PG) S During interrupts or subroutine calls, the other registers are not automatically stored. Therefore, if the contents of these registers need to be held on, q “S” is the initial address that the stack pointer (S) indicates at accepting an interrupt request. be sure to store them by software. The S’s contents become “S – 5” after storing the Additionally, the S ’ s contents become “ 0FFF 16 ” a t above registers. reset. The stack area changes when subroutines are nested or when multiple interrupt requests are accepted. Therefore, make sure of the subroutine’s Fig. 2.1.2 Contents of stack area after accepting interrupt request nesting depth not to destroy the necessary data. ❈ R efer to “7900 Series Software Manual ” f or addressing modes and instructions. 2-4 7 905 Group User ’ s Manual Rev.1.0 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (CPU) 2.1.5 Program counter (PC) The program counter is a 16-bit counter that indicates the low-order 16 bits of the address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out from an instruction queue buffer next) is stored. The contents of the high-order program counter (PCH) become “FF16,” and the low-order program counter (PC L) becomes “FE 16” at reset. The contents of the program counter becomes the contents of the reset ’ s vector address (addresses FFFE 16, FFFF16) just after reset. Figure 2.1.3 shows the program counter and the program bank register. (b23) b7 (b16) b0 b15 b8 b7 b0 PG PCH PCL Fig. 2.1.3 Program counter and Program bank register 2.1.6 Program bank register (PG) The memory space is divided into units of 64 Kbytes. This unit is called “ bank. ” ( Refer to section “ 2.3 Access space.” ) The program bank register is an 8-bit register that indicates the high-order 8 bits of the address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out from an instruction queue buffer next) is stored. These 8 bits indicate a bank. When a carry occurs after adding the contents of the program counter or adding the offset value to the contents of the program counter in the branch instruction and others, the contents of the program bank register is automatically incremented by 1. When a borrow occurs after subtracting the contents of the program counter, the contents of the program bank register is automatically decremented by 1. Therefore, there is no need to consider bank boundaries during programming, usually. This register is cleared to “ 00 16” a t reset. 2.1.7 Data bank register (DT) The data bank register is an 8-bit register. In the following addressing modes using the data bank register, the contents of this register is used as the high-order 8 bits (bank) of a 24-bit address to be accessed. Use the L DT i nstruction when setting a value to this register. This register is cleared to “ 00 16” a t reset. q A ddressing modes using data bank register •Direct indirect • Direct indexed X indirect • Direct indirect indexed Y •Absolute • Absolute indexed X • Absolute indexed Y • Absolute bit relative • Stack pointer relative indirect indexed Y •Multiplied accumulation ❈ R efer to “ 7900 Series Software Manual” f or addressing modes. 7 905 Group User ’ s Manual Rev.1.0 2-5 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (CPU) 2.1.8 Direct page register 0 to 3 (DPR0 to DPR3) Each of direct page registers 0 to 3 (hereafter called the “DPRi”) is a 16-bit register. The contents of this register specify the direct page area in bank 0 16 o r in the space across banks 0 16 a nd 1 16. The following addressing modes use DPRi. The contents of the DPRi indicate the base address (the lowest address) of the direct page area. The direct page area is specified in the space above this address. After reset, whether to use DPR0 only or DPR0 to DPR3 can be selected by the direct page register switch bit. (See Figure 2.1.5). This selection specifies the direct page area. Table 2.1.1 lists the selection of the direct page register. Figure 2.1.4 shows setting examples of the direct page area. At reset, DPR0 = “ 0000 16, ” a nd each of DPR1 to DPR3 becomes undefined. q A ddressing modes using direct page register • D irect • D irect indexed X • D irect indexed Y • D irect indirect • D irect indexed X indirect • D irect indirect indexed Y • D irect indirect long • D irect indirect long indexed Y • D irect bit relative Table 2.1.1 Selection of direct page register Direct page register switch bit 0 1 Usable DPRi Direct page area DPR0 256 bytes DPR0 to DPR3 64 bytes at each DPRi ❈ R efer to “ 7900 Series Software Manual” f or addressing modes and instructions. s Direct page register switch bit = 0 s Direct page register switch bit = 1 016 016 When DPR0 = 000016 FF16 12316 22216 FF1016 016 Bank 016 When DPR0 = 012316 Bank 016 016 3F16 4016 7F16 80016 83F16 When DPR0 = 000016 When DPR1 = 004016 When DPR2 = 080016 FFFF16 1000016 Bank 116 When DPR0 = FF1016 1000F16 FFFF16 1000016 Bank 116 FFD016 1000F16 When DPR3 = FFD016 The direct page area is specified in space across banks 016 and 116 when DPR0 is “FF0116” or more. The direct page area is specified in the space across banks 016 and 116 when DPRi is “FFC116” or more. Note: When the low-order 8 bits of DPRi = “00,” the number of cycles required for address generation becomes 1 cycle smaller. Fig. 2.1.4 Setting examples of direct page area 2-6 7 905 Group User ’ s Manual Rev.1.0 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (CPU) Processor mode register 1 (Address 5F16) Bit 0 1 6 to 2 7 Bit name This bit may be either “0” or “1.” Direct page register switch bit Fix these bits to “00000.” Internal ROM bus cycle select bit 0 : 3φ 1 : 2φ (Note 2) 0 : Only DPR0 is used. 1 : DPR0 through DPR3 are used. Function b7 b6 b5 b4 b3 b2 b1 b0 00000 At reset 1 0 0 0 X R/W RW RW (Note 1) RW RW X : It may be either “0” or “1.” Notes 1: After reset, this bit is allowed to be changed only once. (During the software execution, be sure not to change this bit’s content.) 2: To reprogram the internal flash memory by using the CPU reprogramming mode, clear this bit to “0.” (Refer to section “19.2 Flash memory CPU reprogramming mode.”) Fig. 2.1.5 Structure of processor mode register 1 7 905 Group User ’ s Manual Rev.1.0 2-7 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (CPU) 2.1.9 Processor status register (PS) PS is an 11-bit register. Figure 2.1.6 shows the structure of PS. Refer to “ 7900 Series Software Manual ” f or detale about the change of each bit. b15 b14 b13 b12 b11 b10 b9 0 0 0 0 0 IPL b8 b7 N b6 V b5 m b4 x b3 D b2 I b1 Z b0 C Processor status register (PS) Note: Be sure to fix bits 15 through 11 to “0.” Fig. 2.1.6 Structure of PS (1) Bit 0: Carry flag (C) This flag retains a carry or a borrow generated in the arithmetic and logic unit (ALU) during an arithmetic operation. This flag is also affected by shift and rotate instructions. Be sure to use the SEC or SEP instruction to set this flag to “1”; and be sure to use the CLC or CLP instruction to clear it to “ 0 ” . The contents of this flag is undefined at reset. (2) Bit 1: Zero flag (Z) This flag is set to “1” when the result of an arithmetic operation or data transfer is “0,” and cleared to “ 0 ” w hen otherwise. T his flag is invalid in the decimal arithmetic operation. Be sure to use the SEP instruction to set this flag to “1”; and be sure to use the CLP instruction to clear it to “ 0. ” The contents of this flag is undefined at reset. (3) Bit 2: Interrupt disable flag (I) This flag disables all maskable interrupts except the following: the address matching detection, watchdog timer, and 0 division interrupts. Interrupts are disabled when this flag is “ 1. ” W hen an interrupt request has been accepted, this flag is automatically set to “ 1, ” a nd multiple interrupts become disabled. Be sure to use the S EI o r S EP i nstruction to set this flag to “ 1 ” ; and be sure to use the C LI o r C LP i nstruction to clear this flag to “ 0. ” This flag is set to “ 1 ” a t reset. (4) Bit 3: Decimal mode flag (D) This flag determines whether addition and subtraction are performed in binary or decimal. Binary arithmetic operation is performed when this flag is “ 0. ” W hen it is “ 1, ” d ecimal arithmetic operation is performed with each 8 bits treated as 2-digit decimal (at m = 1) or each 16 bits treated as 4-digit decimal (at m = 0). Decimal adjust is automatically performed. Decimal operation is possible only with the A DC, ADCB, SBC a nd S BCB i nstructions. Be sure to use the S EP i nstruction to set this flag to “ 1 ” ; and be sure to use the C LP i nstruction to clear it to “ 0. ” This flag is cleared to “ 0 ” a t reset. (5) Bit 4: Index register length flag (x) This flag determines whether each of index register X and index register Y is used as a 16-bit register or an 8-bit register. That register is used as a 16-bit register when this flag is “ 0, ” a nd as an 8-bit register when it is “1” (Note) . Be sure to use the SEP instruction to set this flag to “1”; and be sure to use the C LP i nstruction to clear it to “ 0. ” This flag is cleared to “ 0 ” a t reset. 2-8 7 905 Group User ’ s Manual Rev.1.0 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (CPU) (6) Bit 5: Data length flag (m) This flag determines whether to use data as a 16-bit unit or as an 8-bit unit. Each data is treated as a 16-bit unit when this flag is “ 0, ” a nd as an 8-bit unit when it is “ 1 ” ( Note). Be sure to use the S EM o r S EP i nstruction to set this flag to “ 1, ” a nd be sure to use the C LM o r CLP i nstruction to clear it to “ 0. ” This flag is cleared to “ 0 ” a t reset. Note: When transferring data between registers which are different in bit length, this data is transferred with the length of the transfer destination register, except for the case where the T XA, T YA, TXB , T YB , a nd T XS i nstructions used. Refer to “ 7900 series software manual ” f or detail. (7) Bit 6: Overflow flag (V) This flag is used when addition or subtraction is performed with a word regarded as signed binary. The overflow flag is set to “1” when the result of addition or subtraction exceeds the range between – 2147483648 and +2147483647 (when 32-bit length operation), the range between – 32768 and +32767 (when 16-bit length operation), or the range between – 128 and +127 (when 8-bit length operation). The overflow flag is also set to “1” when the operation result of the DIV or DIVS instruction exceeds the length of the register which will store that result. This flag is invalid in the decimal mode. Be sure to use the S EP i nstruction to set this flag to “ 1, ” a nd be sure to use the C LV o r C LP i nstruction to clear it to “ 0. ” The contents of this flag is undefined at reset. (8) Bit 7: Negative flag (N) This flag is set to “1” when the result of arithmetic operation or data transfer is negative. (The most significant bit of the result is “ 1. ” ) It is cleared to “ 0 ” i n all other cases. T his flag is invalid in the decimal mode. Be sure to use the SEP instruction to set this flag to “1,” and be sure to use the CLP instruction to clear it to “ 0. ” The contents of this flag is undefined at reset. (9) Bits 10 to 8: Processor interrupt priority level (IPL) These 3 bits can determine the processor interrupt priority level to one of levels 0 through 7. When the interrupt priority level of a requested interrupt, which has been set in the corresponding interrupt control register, is higher than IPL, that interrupt becomes enabled. When an interrupt request is accepted, IPL is stored in the stack area, and IPL is replaced by the interrupt priority level of the accepted interrupt request. There are no instruction to directly set or clear the bits of IPL. IPL can be changed by storing the new IPL into the stack area and updating PS with the P UL o r P LP i nstruction. The contents of IPL is cleared to “ 0002” a t reset. 7 905 Group User ’ s Manual Rev.1.0 2-9 C ENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit (BIU) 2.2 Bus interface unit (BIU) The bus interface unit (hereafter called “BIU”) performs the following two operations: q I nstruction prefetch q D ata transfer (read and write) Figure 2.2.1 shows the bus and BIU. BIU is structured with four kinds of registers shown in Figure 2.2.2. Table 2.2.1 lists the function of the BIU registers. M37905 Internal buses CPU bus Central processing unit (CPU) Internal code bus (CB0 to CB31) Bus interface unit (BIU) Internal data bus (DB0 to DB15) Internal address bus (AD0 to AD23) Internal control signal Internal memory Internal peripheral devices (SFR) SFR : Special Function Register ❈ The CPU bus and internal bus are independent of one another. Fig. 2.2.1 Bus and BIU Table 2.2.1 Functions of BIU registers Name Functions Program Indicates a storage address of the address instruction to be fetched into an register instruction queue buffer, next. Instruction Temporarily stores an instruction queue buffer which has been fetched. Data address Indicates an address from which data register will be read or to which data will be written, next. Data buffer Temporarily stores data which has been read from memory • I/O device by BIU or which will be written to memory • I/O device by the CPU. b23 b0 PA b7 b0 Program address register Q0 Instruction queue buffer Q9 b23 b0 DA b31 b0 Data address register DQ Data buffer Fig. 2.2.2 BIU registers’ structure In the M37905, the internal buses are used when the CPU accesses the internal area (the internal memory and SFR). 2-10 7905 Group User’s Manual Rev.1.0 C ENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit (BIU) 2.2.1 Instruction prefetch While the CPU does not use the internal buses, the BIU reads instructions from the memory and then stores them in the instruction queue buffer. The CPU reads instructions from the instruction queue buffer and executes them, so that the CPU can operate at high speed without access to the memory, which requires a long access time. The instruction queue buffer can store instructions up to 10 bytes. The contents of the instruction queue buffer is initialized when a branch is made, and the BIU reads a new instruction from the branch destination address. When instructions in the instruction queue buffer are insufficient for the CPU’s needs, the BIU extends the low-level duration of φ CPU ( See Figure 4.2.1.) in order to keep the CPU waiting until the BIU fetches instructions of the required byte number or more. Figure 2.2.3 shows operating waveform examples at instruction prefetch. Note that the operation of Table 2.2.2 Store address of prefetched instruction BIU’s instruction prefetch also varies with the store Low-order 3 bits addresses of instructions. Table 2.2.2 lists the store at store address address of prefetched instructions. AD2 AD1 AD0 When the instruction prefetch from internal memory, Even-numbered address ✕ ✕ 0 the instructions are fetched from 4-byte boundaries, ✕ 0 0 4-byte boundaries 4 bytes at a time. (See Figure 2.2.3.) 0 0 0 8-byte boundaries Also, at branch, regardless of the low-order 2 bits’ contents (AD1 and AD0) of the branch destination X: It may be either “ 0 ” o r “ 1. ” address, 4 bytes are fetched at time from the 4byte boundaries. (See Figure 2.2.3.) In this case, out of the data (instructions) which will be output onto the internal code buses, 4 bytes at a time, the instructions assigned at the branch destination address and the following addresses will be fetched into the instruction queue buffer. Accordingly, as listed in Table 2.2.3, the number of bytes to be fetched into the instruction queue buffer varies according to the branch destination address. Table 2.2.3 Number of bytes to be fetched into instruction queue buffer Low-order 2 bits of branch destination address AD1 0 0 1 1 AD0 0 1 0 1 Low-order 2 bits of address to be output onto address bus AD1 0 0 0 0 AD0 0 0 0 0 Number of bytes to be fetched into instruction queue buffer 4 3 2 1 φBIU Internal address bus (AD0–AD23) Internal code bus (CB0–CB31) Address Data (instruction) φBIU: Operation clock of BIU (Refer to “CHAPTER 4. CLOCK GENERATING CIRCUIT.”) Note: T his waveform applies when bus cycle = 2 φ . For details of the bus cycle at access to the internal area, see Table 2.2.4. Fig. 2.2.3 Operation waveform examples at instruction prefetch 7905 Group User ’ s Manual Rev.1.0 2-11 C ENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit (BIU) 2.2.2 Data Transfer (read and write) When the CPU reads or writes data from or to the internal area, it requests the BIU to read or write data. The BIU outputs control signals in order to control the internal address and data buses in response to the request from the CPU. The cycle where the following are performed is referred to “ bus cycle ” : • T he BIU controls buses. • D ata transfer is performed between the internal area and BIU. Table 2.2.4 lists the bus cycles at access to the internal area. Figure 2.2.4 shows operating waveform examples at reading from or writing to the internal area. (1) Reading data The CPU informs the BIU’s data address register of the address where the data to be read is stored, so the CPU requests the data. In this case, the CPU waits until the requested data is ready in the BIU. The BIU outputs the address informed by the CPU onto the internal address bus. Then, the CPU reads the contents of the informed address and takes them into the data buffer. The CPU continues processing using data in the data buffer. (2) Writing data The CPU informs the BIU ’ s data address register of the address to which the data will be written, so the CPU writes the data into the data buffer. The BIU outputs the address informed by the CPU onto the internal address bus. Then, the BIU writes the data in the data buffer into the informed address. Table 2.2.4 Bus cycles at access to internal area Bus cycle = 3φ (Note) (Internal ROM bus cycle select bit = 0) 1 bus cycle = 3φ φBIU φBIU Address Bus cycle = 2φ (Note) (Internal ROM bus cycle select bit = 1) 1 bus cycle = 2φ ROM Internal address bus Internal data bus Internal address bus Data Address Internal data bus Data 1 bus cycle = 2φ RAM φBIU Internal address bus Address SFR Internal data bus Data Internal ROM bus cycle select bit: Bit 7 at address 5F 16 Note: We usually recommend to select “bus cycle = 2 φ.” When reprogramming the internal flash memory in the CPU reprogramming mode, be sure to select bus cycle = 3 φ . (Refer to section “ 19.2 Flash memory CPU reprogramming mode. ”) 2-12 7905 Group User ’ s Manual Rev.1.0 C ENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit (BIU) (a) When accessing 8-bit data (Note 1) or accessing 16-bit data starting from an even-numbered address φBIU Internal address bus (AD0–AD23) Internal data bus (DB0–DB7) Address RD (even) WD (even) RD (odd) Internal data bus (DB8–DB15) Note 1: When reading 8-bit data at an even-numbered address, only RD (even) will be taken into a data buffer. When reading 8-bit data at an odd-numbered address, only RD (odd) will be taken into a data buffer. When writing 8-bit data to an even-numbered address, only WD (even) will be written to the address. When writing 8-bit data to an odd-numbered address, only WD (odd) will be written to the address. WD (odd) (b) When accessing 16-bit data starting from an odd-numbered address φBIU Internal address bus (AD0–AD23) Internal data bus (DB0–DB7) Address Address + 1 RD (even) WD (even) RD (odd) Internal data bus (DB8–DB15) WD (odd) (c) When accessing 32-bit data starting from an even-numbered address φBIU Internal address bus (AD0–AD23) Internal data bus (DB0–DB7) Address RD (even) Address + 2 RD (even) WD (even) RD (odd) WD (even) RD (odd) Internal data bus (DB8–DB15) WD (odd) WD(odd) (d) When accessing 32-bit data starting from an odd-numbered address φBIU Internal address bus (AD0–AD23) Internal data bus (DB0–DB7) Address Address + 1 RD (even) Address + 3 RD (even) WD (even) RD (odd) RD (odd) WD (even) Internal data bus (DB8–DB15) WD (odd) WD (odd) RD: Data to be read, WD: Data to be written Note 2: The above waveforms apply when bus cycle = 2φ. For the bus cycles at access to the internal area, see Table 2.2.4. Fig. 2.2.4 Operation waveform examples at reading from or writing to internal area 7905 Group User ’ s Manual Rev.1.0 2-13 CENTRAL PROCESSING UNIT (CPU) 2.3 Access space 2.3 Access space The access space of the M37905 is assigned to a 16-Mbyte space from addresses 0 16 t o FFFFFF16. (See Figure 2.3.1.) Note that only the internal memory can be accessed because the M37905 operates only in the single-chip mode. The memory and I/O devices are assigned in the same access space. Accordingly, it is possible to perform transfer and arithmetic operations using the same instructions, without discrimination of the memory from I/O devices. 016 FF16 SFR area Internal RAM area (Note 1) Bank 016 Internal ROM area (Note 2) : Memory assignment of internal area : Nothing is assigned. Notes 1: When the internal RAM area is followed by an unused area, do not assign a program to the last 8 bytes of the internal RAM area. 2: Do not assign a program to the last 8 bytes of the internal ROM area. 3: The memory assignment of the internal area varies according to the product type. Refer to section “Appendix 11. Memory assignment of 7905 Group,” or the latest datasheets, catalogs. 4: Refer to section “19.1.1 Memory assignment,” about the flash memory version. SFR : Special Function Register Fig. 2.3.1 M37905’s access space 2-14 7 905 Group User’s Manual Rev.1.0 CENTRAL PROCESSING UNIT (CPU) 2.4 Memory assignment 2.4 Memory assignment This section describes the memory assignment in the internal area. 2.4.1 Memory assignment in internal area SFR (Special Function Register), internal RAM, and internal ROM are assigned to the internal area. Figure 2.4.1 shows the memory assignment in the internal area. (1) SFR area The registers used to set the internal peripheral devices are assigned to addresses 016 to FF16. This area is called SFR. Figures 2.4.2 and 2.4.3 show the SFR area ’ s memory assignment. For each register in the SFR area, refer to each functional description in this manual. For the state of the SFR area immediately after reset, refer to section “3.3 State of internal area.” (2) Internal RAM area The internal RAM area is used as a stack area, as well as an area to store data. Accordingly, be sure to set the nesting depth of a subroutine and multiple interrupts’ level not to destroy the necessary data. When the internal RAM area is followed by an unused area, d o not assign a program to the last 8 bytes of the internal RAM area. (Data is allowed to be assigned there. Also, when the internal RAM area is followed by the internal ROM area succeedingly, a program is allowed to be assigned there.) (3) Internal ROM area Addresses FFB4 16 t o FFFF16 a re the vector addresses for reset and interrupts. (This is called the interrupt vector table.) Do not assign a program to the last 8 bytes of the internal ROM area. (Data is allowed to be assigned there.) 7 905 Group User ’ s Manual Rev.1.0 2-15 CENTRAL PROCESSING UNIT (CPU) 2.4 Memory assignment 016 FF16 SFR area → See Figures 2.4.2 and 2.4.3. FFB416 FFB616 FFB816 FFBA16 FFBC16 FFBE16 FFC016 FFC216 FFC416 FFC616 FFC816 FFCA16 FFCC16 FFCE16 FFD016 FFD216 FFD416 FFD616 FFD816 Interrupt vector table L H L UART2 receive H L Timer A9 H L Timer A8 H L Timer A7 H L Timer A6 H L Timer A5 H L INT7 H L INT6 H L INT5 H L Reserved area H L Address matching detection H L Reserved area H L Reserved area H L INT4 H L INT3 H L A-D conversion H L UART1 transmit H L UART1 receive H L UART0 transmit H L UART0 receive H L Timer B2 H L Timer B1 H L Timer B0 H L Timer A4 H L Timer A3 H L Timer A2 H L Timer A1 H L Timer A0 H L INT2 H L INT1 H L INT0 H L Reserved area H L Watchdog timer H L DBC (Note 1) H L BRK instruction (Note 1) H L Zero divide H L RESET H UART2 transmit Internal RAM area Internal ROM area FFDA16 FFDC16 FFDE16 FFE016 FFE216 FFE416 FFE616 FFE816 FFEA16 FFEC16 FFEE16 FFF016 FFF216 FFF416 FFF616 FFF816 FFFA16 FFFC16 FFFE16 FFB416 FFFF16 : The internal memory is not assigned. Notes 1: These are interrupts only for debugging; do not use these interrupts. 2: Memory assignment of the internal area varies according to the product type. Refer to section “Appendix 11. Memory assignment of 7905 Group” or the latest datasheets, catalogues. Fig. 2.4.1 Memory assignment in internal area 2-16 7 905 Group User ’ s Manual Rev.1.0 CENTRAL PROCESSING UNIT (CPU) 2.4 Memory assignment Address 8016 (Note 2) 8116 (Note 2) 8216 (Note 2) 8316 (Note 2) 8416 (Note 2) 8516 (Note 2) 8616 (Note 2) 8716 (Note 2) 8816 8916 8A16 (Note 2) 8B16 8C16 (Note 2) 8D16 8E16 (Note 2) 8F16 9016 (Note 2) 9116 9216 (Note 2) 9316 9416 9516 External interrupt input read register 9616 D-A control register 9716 9816 D-A register 0 9916 D-A register 1 9A16 9B16 9C16 (Note 2) 9D16 (Note 2) 9E16 Flash memory control register (Note 4) 9F16 Address 016 116 216 316 416 516 616 716 816 916 A16 B16 C16 D16 E16 F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 1A16 1B16 1C16 1D16 1E16 1F16 2016 2116 2216 2316 2416 2516 2616 2716 2816 2916 2A16 2B16 2C16 2D16 2E16 2F16 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C16 3D16 3E16 3F16 (Note 1) (Note 1) (Note 2) Port P1 register (Note 2) Port P1 direction register Port P2 register (Note 2) Port P2 direction register (Note 2) Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P8 direction register (Note 2) (Note 2) (Note 2) (Note 2) A-D control register 0 A-D control register 1 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 UART0 transmit/receive mode register UART0 baud rate register (BRG0) UART0 transmit buffer register UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 baud rate register (BRG1) UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register Address 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 4A16 4B16 4C16 4D16 4E16 4F16 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C16 5D16 5E16 5F16 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 6A16 6B16 6C16 6D16 6E16 6F16 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C16 7D16 7E16 7F16 Count start flag 0 Count start flag 1 One-shot start flag 0 One-shot start flag 1 Up-down flag 0 Timer A clock division select register Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 Watchdog timer register Watchdog timer frequency select register Particular function select register 0 Particular function select register 1 Particular function select register 2 (Note 2) Debug control register 0 Debug control register 1 Address compare register 0 (Note 3) Address compare register 1 (Note 3) INT3 interrupt control register INT4 interrupt control register A-D conversion interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register Notes 1: Do not read from and write to this register. 2: Do not write to this register. 3: When these registers are accessed, set the address compare register access enable bit (bit 2 at address 6716) to “1.” (Refer to “CHAPTER 17. DEBUG FUNCTION.”) 4: This register is assigned only to the flash memory version. (Refer to “CHAPTER 19. FLASH MEMORY VERSION.”) Nothing is assigned here in the mask ROM version. Fig. 2.4.2 SFR area ’ s memory map (1) 7 905 Group User ’ s Manual Rev.1.0 2-17 CENTRAL PROCESSING UNIT (CPU) 2.4 Memory assignment Address Pulse output control register A016 A116 Pulse output data register 0 A216 A316 Pulse output data register 1 A416 A516 Waveform output mode register A616 Dead-time timer A716 Three-phase output data register 0 A816 Three-phase output data register 1 A916 AA16 Position-data-retain function control register AB16 AC 16 Serial I/O pin control register AD16 Port P2 pin function control register AE16 AF16 UART2 transmit/receive mode register B016 UART2 baud rate register (BRG2) B116 B216 UART2 transmit buffer register B316 B416 UART2 transmit/receive control register 0 B516 UART2 transmit/receive control register 1 B616 UART2 receive buffer register B716 (Note 5) B816 B916 (Note 5) BA16 (Note 5) BB16 Clock control register 0 BC16 (Note 5) BD16 (Note 5) BE16 (Note 5) BF16 Address C0 16 C1 16 C2 16 C3 16 C4 16 C5 16 C6 16 C7 16 C8 16 C9 16 CA 16 CB 16 CC 16 CD 16 CE 16 CF 16 D0 16 D1 16 D2 16 D3 16 D4 16 D5 16 D6 16 D7 16 D8 16 D9 16 DA 16 DB16 DC16 DD16 DE16 DF16 E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F0 16 F1 16 F2 16 F3 16 F4 16 F5 16 F6 16 F7 16 F8 16 F9 16 FA16 FB16 FC16 FD16 FE16 FF16 Up-down flag 1 Timer A5 register Timer A6 register Timer A7 register Timer A8 register Timer A9 register Timer A01 register Timer A11 register Timer A21 register Timer A5 mode register Timer A6 mode register Timer A7 mode register Timer A8 mode register Timer A9 mode register A-D control register 2 Comparator function select register 0 Comparator function select register 1 Comparator result register 0 Comparator result register 1 A-D register 8 A-D register 9 A-D register 10 A-D register 11 (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) UART2 transmit interrupt control register UART2 receive interrupt control register Timer A5 interrupt control register Timer A6 interrupt control register Timer A7 interrupt control register Timer A8 interrupt control register Timer A9 interrupt control register INT5 interrupt control register INT6 interrupt control register INT7 interrupt control register Note 5: Do not write to this register. Fig. 2.4.3 SFR area ’ s memory map (2) 2-18 7 905 Group User ’ s Manual Rev.1.0 CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes 2.5 Processor modes The M37905 operates only in the single-chip mode. Figure 2.5.1 shows the memory assignment of the M37905. Single-chip mode 016 SFR area FF16 Unused area Internal RAM area (Note 1) Unused area Internal ROM area (Note 2) Notes 1: When the internal RAM area is followed by an unused area, do not assign a program to the last 8 bytes of the internal RAM area. 2: Do not assign a program to the last 8 bytes of the internal ROM area. 3: The memory assignment of the internal area varies according to the product type. Refer to section “Appendix 11. Memory assignment of 7905 Group,” or the latest datasheets, catalogs. Fig. 2.5.1 Memory assignment of M37905 2.5.1 Single-chip mode In this mode, ports P1, P2, P4 to P8 serve as programmable I/O ports. (When an internal peripheral device is used, the corresponding port pin serves as the device ’ s I/O pin). In this mode, only the internal area (SFR, internal RAM, and internal ROM) can be accessed. 7 905 Group User’s Manual Rev.1.0 2-19 CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes 2.5.2 Setting of processor mode The processor mode is set by the following: • V oltage level applied to the MD0 and MD1 pins • P rocessor mode bits (bits 1 and 0 at address 5E 16) The VSS– level voltage must be applied to the MD0 and MD1 pins, because the M37905 operates only in the single-chip mode. Also, the processor mode bit must be “ 00. ” Figure 2.5.2 shows the structure of the processor mode register 0 (address 5E 16 ). b7 b6 b5 b4 b3 b2 b1 b0 Processor mode register 0 (Address 5E16) Bit 0 1 2 3 4 5 6 7 Software reset bit Fix this bit to “0.” Interrupt priority detection time select bits b5 b4 0 Function XX00 At reset 0 0 0 1 R/W RW RW RW RW RW RW WO RW Bit name Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Do not select. 1 0 : Do not select. 1 1 : Do not select. Any of these bits may be either “0” or “1.” 0 0 : 7 cycles of fsys 0 1 : 4 cycles of fsys 1 0 : 2 cycles of fsys 1 1 : Do not select. The microcomputer is reset by writing “1” to this bit. The value is “0” at reading. 0 0 0 0 X : It may be either “0” or “1.” Fig. 2.5.3 Structure of processor mode register 0 2-20 7 905 Group User ’ s Manual Rev.1.0 CENTRAL PROCESSING UNIT (CPU) [Precautions for setting of processor mode] [Precautions for setting of processor mode] The M37905 operates only in the single-chip mode. Therefore, for the M37905, do as follows: • T he MD0 and MD1 pins must be connected to Vss. • T he processor mode bits (bits 0 and 1 at address 5E 16) must be fixed to “ 00 2. ” 7 905 Group User ’ s Manual Rev.1.0 2-21 CENTRAL PROCESSING UNIT (CPU) [Precautions for setting of processor mode] MEMORANDUM 2-22 7 905 Group User ’ s Manual Rev.1.0 CHAPTER 3 RESET 3.1 3.2 3.3 3.4 Reset operation Pin state State of internal area Internal processing sequence after reset RESET 3.1 Reset operation There are 3 ways to reset the microcomputer: Hardware reset : Apply “L” level of voltage to pin RESET while the power source voltage (Vcc) meets the recommended operating conditions. Software reset : Write “1” to the software reset bit (bit 6 at address 5E 16) while the power source voltage (Vcc) meets the recommended operating conditions. Power-on reset : After power-on, raise the voltage level at pin Vcc to the level, which meets the recommend operating conditions, with “L” level of voltage applied to pin RESET. 3.1 Reset operation Operations of hardware, software, and power-on reset are described below. 3.1.1 Hardware reset Figure 3.1.1 shows an example of hardware reset timing. RESET (Note) 10 µs or more 8 to 9 cycles of fsys Internal processing sequence after reset Program is executed. ➁ ➀ ➂ ➃ Note: The above is applied when the oscillator is stably oscillating or when an external clock is stably input from pin XIN. When the oscillator is not stably oscillating (including the case at the stop mode’s termination; refer to section “15.3 Stop mode.”), apply “L” level of voltage for 10 µs or more after the oscillation becomes stable. Fig. 3.1.1 Example of hardware reset timing The following explains how the microcomputer operates in the above periods, ➀ t o ➃. ➀ After applying “L” level of voltage to pin RESET, the microcomputer initializes pins within a period of several ten cycles of fsys. (Refer to section “3.2 Pin state.”) ➁ The microcomputer initializes the central processing unit (CPU) and SFR area in the following periods. (Refer to section “3.3 State of internal area.”) • While pin RESET is at “L” level. • In the period of 8 to 9 cycles of fsys a fter pin RESET goes from “L” to “H.” ➂ A fter ➁, the microcomputer performs “Internal processing sequence after reset.” (Refer to section “3.4 Internal processing sequence after reset.”) ➃ T he microcomputer executes a program beginning with the address which has been set into the reset vector addresses (addresses FFFE 16 a nd FFFF 16). 3-2 7905 Group User’s Manual Rev.1.0 RESET 3.1 Reset operation 3.1.2 Software reset The microcomputer initializes pins, CPU, and SFR area just as in the case of hardware reset (Refer to sections “ 3.2 Pin state ” a nd “ 3.3 State of internal area. ” ) by writing “ 1 ” t o the software reset bit. (See Figure 3.1.2.) After initialization is completed, the microcomputer performs “ Internal processing sequence after reset. ” (Refer to section “ 3.4 Internal processing sequence after reset. ” ) After that, it executes a program beginning with the address which has been set into the reset vector addresses (addresses FFFE 16 a nd FFFF 16). Processor mode register 0 (Address 5E16) Bit 0 1 2 3 4 5 6 7 Software reset bit Fix this bit to “0.” Interrupt priority detection time select bits b5 b4 b7 b6 b5 b4 b3 b2 b1 b0 0 Function XX00 At reset 0 0 0 1 R/W RW RW RW RW RW RW WO RW Bit name Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Do not select. 1 0 : Do not select. 1 1 : Do not select. Any of these bits may be either “0” or “1.” 0 0 : 7 cycles of fsys 0 1 : 4 cycles of fsys 1 0 : 2 cycles of fsys 1 1 : Do not select. The microcomputer is reset by writing “1” to this bit. The value is “0” at reading. 0 0 0 0 X: It may be either “0” or “1.” Fig. 3.1.2 Structure of processor mode register 0 7905 Group User ’ s Manual Rev.1.0 3-3 RESET 3.1 Reset operation 3.1.3 Power-on reset The following describes the operation of the microcomputer at power-on reset. ➀ After powered on, within the several ten cycles of fsys after the voltage level at pin Vcc meets the recommended operating conditions with the voltage level at pin RESET = “L,” the microcomputer initializes pins; refer to section “3.2 Pin state.” ➁ A fter the voltage level at pin RESET goes from “ L ” t o “ H, ” t he microcomputer initializes the CPU and SFR area within a period of 8 to 9 cycles of fsys. (Contents of the internal RAM area become undefined; refer to section “3.3 State of internal area.”) ➂ A fter ➁, the microcomputer performs “Internal processing sequence after reset. ”; refer to section “3.4 Internal processing sequence after reset.” ➃ T he microcomputer executes a program beginning with the address which has been set into the reset vector addresses (addresses FFFE 16 a nd FFFF 16). F igure 3.1.3 shows the power-on reset conditions. Figure 3.1.4 shows an example of a power-on reset circuit. After the voltage level at pin Vcc meets the recommended operating conditions and the oscillator’s operation is stabilized (See Figure 3.1.3.), apply “L” level of voltage to pin RESET for 10 µ s or more. When an oscillator is used, the time required for stabilizing oscillation depends on the oscillator. For details, contact the oscillator manufacturer. VCC level VCC 0V RESET 0V 0.2 V CC level 10 µs X IN 0V Powered on there Oscillation stabilized Fig. 3.1.3 Power-on reset conditions 5V M37905 1 M51957AL 27 k Ω 2 10 k Ω IN VCC VCC OUT 5 RESET 47 Ω VSS Cd SW 4 Delay capacity GND 3 ✽ The delay time is about 11 ms when Cd = 0.033 µF. td ≈ 0.34 ✕ Cd [µs], Cd: [pF] GND Fig. 3.1.4 Example of power-on reset circuit 3-4 7905 Group User ’ s Manual Rev.1.0 RESET 3.2 Pin state 3.2 Pin state Table 3.2.1 lists the microcomputer ’ s pin state while the voltage level at pin RESET is “ L. ” Table 3.2.1 Pin state while voltage level at pin RESET is “ L ” Pin (Bus, Port) name Pin MD1’s level Pin MD0’s level Vss P1, P2, P4–P8 MASK ROM version, Vss Flash memory version (Note 1) Flash memory version Vcc (Note 1) Vss Vcc P1, P2, P4–P8 P1, P2, P4–P8 Floating. Floating (Note 2). Pin state Floating. Notes 1: Refer to “CHAPTER 19. FLASH MEMORY VERSION.” 2: Pins P56, P57 and P60 to P65 output “H” or “L” level when “H” level of voltage is applied to pin VCONT and “L” level to pins P70, P71. 7905 Group User ’ s Manual Rev.1.0 3-5 RESET 3.3 State of internal area 3.3 State of internal area Figure 3.3.1 shows the state of CPU registers immediately after reset. Figures 3.3.2 to 3.3.9 show the state of the SFR and internal RAM areas immediately after reset. 0 : “0” immediately after reset. 1 : “1” immediately after reset. ? : Undefined immediately after reset. 0 : “0” immediately after reset. Fix this bit to “0.” Register name b15 Accumulator A (A) State immediately after reset b8 b7 b0 ? b15 b8 b7 ? b0 Accumulator B (B) ? b15 b8 b7 ? b0 Index register X (X) ? b15 b8 b7 ? b0 Index register Y (Y) ? b15 b8 b7 ? b0 Stack pointer (S) 0F16 b7 FF16 b0 Data bank register (DT) 0016 b7 b0 Program bank register (PG) 0016 b15 b8 b7 b0 Program counter (PC) Contents at address FFFF16 b15 b8 Contents at address FFFE16 b7 b0 Direct page register 0 (DPR0) b15 Direct page register i (DPRi) (i = 1 to 3) b15 Processor status register (PS) 0016 b8 b7 0016 b0 ? b8 b7 ? b0 0 0 0 0 0 0 0 IPL 0 ? N ? V 0 m 0 x 0 D 1 I ? Z ? C Fig. 3.3.1 State of CPU registers immediately after reset 3-6 7905 Group User ’ s Manual Rev.1.0 RESET 3.3 State of internal area qSFR area (Addresses 016 to FF16) Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : “0” immediately after reset. 1 : “1” immediately after reset. ? : Undefined immediately after reset. 0 1 ? 0 : Always “0” at reading. : Always “1” at reading. : Always undefined at reading. : “0” immediately after reset. Fix this bit to “0.” Address 016 116 216 316 416 516 616 716 816 916 A16 B16 C16 D16 E16 F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 1A16 1B16 1C16 1D16 1E16 1F16 Register name b7 Access characteristics b0 State immediately after reset b7 b0 Port P1 register Port P1 direction register Port P2 register Port P2 direction register Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P8 direction register (Note 1) (Note 1) (Note 2) RW (Note 2) RW RW (Note 2) RW (Note 2) RW RW RW RW RW RW RW RW RW RW (Note 2) (Note 2) (Note 2) (Note 2) ? ? ? ? ? ? RW 0 0 0 RW ? ? ? A-D control register 0 A-D control register 1 RW RW 0 0 0 0 0 0 ? ? ? ? ? 0016 ? ? 0016 ? ? ?? 0016 ?0 ? ? 0016 0016 ?0 ? ?0 ? ? ? ? ? ? ? ? ? 00 00 ? 0 ? 0 ? ? 0 0 0 0 0 0 ? 0 ? 1 ? 1 Notes 1: Do not read from and write to this register. 2: Do not write to this register. Fig. 3.3.2 State of SFR and internal RAM areas immediately after reset (1) 7905 Group User ’ s Manual Rev.1.0 3-7 RESET 3.3 State of internal area Address 2016 2116 2216 2316 2416 2516 2616 2716 2816 2916 2A16 2B16 2C16 2D16 2E16 2F16 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C16 3D16 3E16 3F16 Register name b7 Access characteristics b0 State immediately after reset b7 b0 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 UART0 transmit/receive mode register UART0 baud rate register (BRG0) UART0 transmit buffer register UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 baud rate register (BRG1) UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register RW RO RW RO (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) RW WO WO RO RO RO RW WO WO RO RO RO WO RW RW RO RW ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 00 0016 ? ? ? 01 00 ? 00 0016 ? ? ? 01 00 ? 00 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 ? WO RW RW RO RW 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 ? Note 3: The access characteristics at addresses 2016 to 2F16 vary according to the contents of the comparator function select register 0 (address DC16). (Refer to “CHAPTER 12. A-D CONVERTER.”) Fig. 3.3.3 State of SFR and internal RAM areas immediately after reset (2) 3-8 7905 Group User ’ s Manual Rev.1.0 RESET 3.3 State of internal area Address 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 4A16 4B16 4C16 4D16 4E16 4F16 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C16 5D16 5E16 5F16 Register name b7 Count start register 0 Count start register 1 One-shot start register 0 One-shot start register 1 Up-down register 0 Timer A clock division select register Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 Access characteristics b0 State immediately after reset b7 b0 RW RW RW WO (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) RW RW RW RW RW RW (Note 6) RW (Note 6) RW (Note 6) RW WO RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 ? ? ? 0 0 RW WO WO RW RW RW ? 0 0 0 0 ? ? 0 0 0 0 0016 00 00 00 00 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0016 0016 0016 0016 0016 00 00 00 01 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Notes 4: The access characteristics at addresses 4616 to 4F16 vary according to the timer A’s operating mode. (Refer to “CHAPTER 7. TIMER A.”) 5: The access characteristics at addresses 5016 to 5516 vary according to the timer B’s operating mode. (Refer to “CHAPTER 8. TIMER B.”) 6: The access characteristics for bit 5 at addresses 5B16 to 5D16 vary according to the timer B’s operating mode. (Refer to “CHAPTER 8. TIMER B.”) Fig. 3.3.4 State of SFR and internal RAM areas immediately after reset (3) 7905 Group User ’ s Manual Rev.1.0 3-9 RESET 3.3 State of internal area Address 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 6A16 6B16 6C16 6D16 6E16 6F16 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C16 7D16 7E16 7F16 Register name b7 Access characteristics b0 b7 State immediately after reset b0 Watchdog timer register Watchdog timer frequency select register Particular function select register 0 Particular function select register 1 Particular function select register 2 Debug control register 0 Debug control register 1 Address comparison register 0 (Note 7) RW RW RW RW RW (Note 9) RW RW RW RW (Note 10) 0 0 0 Address comparison register 1 INT3 interrupt control register INT4 interrupt control register A-D conversion interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register (Note 12) RW RO RO RW RW RO RW RW (Note 13) RW (Note 13) RW (Note 13) RW (Note 13) RW (Note 13) RW (Note 13) RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 1 0 ? ? ? ? ? ? (Note 8) 0 0 ? 0000000 0 0 0 0 0 (Note 11) ? ? 0 (Note 11) 0 0 (Note 11) 0 0? 0000 ? ? ? ? ? ? 000000 000000 ?000 ? 0000 ? 0000 ? 0000 ? 0000 ? 0000 ? ? 0000 0000 ? 0000 ? 0000 ? 0000 ? 0000 ? 0000 ? 000000 000000 000000 Notes 7 : By writing dummy data to address 6016, a value of “FFF16” is set to the watchdog timer. The dummy data is not retained anywhere. 8 : A value of “FFF16” is set to the watchdog timer. (Refer to “CHAPTER 14. WATCHDOG TIMER.”) 9 : After writing “5516” to address 6216, each bit must be set. 10 : It is possible to read the bit state at reading. By writing “0” to this bit, this bit becomes “0.” But when writing “1” to this bit, this bit will not change. 11 : This bit becomes “0” at power-on reset. This bit retains the state immediately before reset in the case of hardware reset and software reset. 12 : Do not write to this register. 13 : When these registers are accessed, set the address comparison register access enable bit (bit 2 at address 6716) to “1.” (Refer to “CHAPTER 17. DEBUG FUNCTION.”) Fig. 3.3.5 State of SFR and internal RAM areas immediately after reset (4) 3-10 7905 Group User ’ s Manual Rev.1.0 RESET 3.3 State of internal area Address Register name b7 Access characteristics b0 State immediately after reset b7 b0 8016 8116 8216 8316 8416 8516 8616 8716 8816 8916 8A16 8B16 8C16 8D16 8E16 8F16 9016 9116 9216 9316 9416 9516 External interrupt input read-out register D-A control register 9616 9716 9816 D-A register 0 D-A register 1 9916 9A16 9B16 9C16 9D16 9E16 Flash memory control register (Note 15) 9F16 (Note 14) (Note 14) (Note 14) (Note 14) (Note 14) (Note 14) (Note 14) (Note 14) (Note 14) (Note 14) (Note 14) (Note 14) (Note 14) RO RW RW RW RW ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 ? 0016 0016 ? ? ? ? 00 ? 0 (Note 14) (Note 14) RW RW RW RO 0 0 0 0 0 1 Notes 14 : Do not write to this register. 15 : This register is assigned only to the flash memory version. (Refer to “CHAPTER 19. FLASH MEMORY VERSION.”) Nothing is assigned here in the mask ROM version. Fig. 3.3.6 State of SFR and internal RAM areas immediately after reset (5) 7905 Group User ’ s Manual Rev.1.0 3-11 RESET 3.3 State of internal area Address Register name b7 Pulse output control register Access characteristics b0 State immediately after reset b7 b0 A016 A116 Pulse output data register 0 RW A216 A316 Pulse output data register 1 RW A416 A516 Waveform output mode register RW A616 Dead-time timer WO A716 Three-phase output data register 0 RW A816 Three-phase output data register 1 RW A916 RW RO RO RO AA16 Position-data-retain function control register AB16 Serial I/O pin control register RW RW RW RW RW RW AC16 AD16 Port P2 pin function control register RW RW RW RW AE16 AF16 RW UART2 transmit/receive mode register B016 UART2 baud rate register (BRG2) WO B116 WO B216 UART2 transmit buffer register WO B316 B416 UART2 transmit/receive control register 0 RO RW RW RO B516 UART2 transmit/receive control register 1 RW RO RW B616 RO UART2 receive buffer register B716 RO B816 (Note 16) B916 BA16 (Note 16) BB16 (Note 16) Clock control register 0 BC16 RW RW RW RW (Note 17) RW RW (Note 16) BD16 BE16 (Note 16) BF16 (Note 16) RW ? 0 0 0 ? 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0016 ? 0016 ? 0016 ? 0016 ? 0016 0016 0 ? 00 ? ?? ? 0016 ? ? ? 01 00 ? 00 ? ? ? ? 10 ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 ? 1 1 1 Notes 16 : Do not write to this register. 17 : After reset, these bits are allowed to be changed only once. Fig. 3.3.7 State of SFR and internal RAM areas immediately after reset (6) 3-12 7905 Group User ’ s Manual Rev.1.0 RESET 3 .3 State of internal area Address Register name b7 Access characteristics b0 State immediately after reset b7 b0 C016 C116 C216 C316 Up-down register 1 C416 C516 C616 Timer A5 register C716 C816 Timer A6 register C916 CA16 Timer A7 register CB16 CC16 Timer A8 register CD16 CE16 Timer A9 register CF16 D016 Timer A01 register D116 D216 Timer A11 register D316 D416 Timer A21 register D516 D616 Timer A5 mode register D716 Timer A6 mode register D816 Timer A7 mode register D916 Timer A8 mode register Timer A9 mode register DA16 DB16 A-D control register 2 Comparator function select register 0 DC16 DD16 Comparator function select register 1 DE16 Comparator result register 0 Comparator result register 1 DF16 ? ? ? ? WO RW (Note 18) (Note 18) (Note 18) (Note 18) (Note 18) (Note 18) (Note 18) (Note 18) (Note 18) (Note 18) WO WO WO WO WO WO RW RW RW RW RW RW RW RW RW RW 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0016 0016 0016 0016 0016 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 18: The access characteristics at addresses C616 to CF16 vary according to the timer A’s operating mode. (Refer to “CHAPTER 7. TIMER A.”) Fig. 3.3.8 State of SFR and internal RAM areas immediately after reset (7) 7905 Group User ’ s Manual Rev.1.0 3-13 RESET 3.3 State of internal area Address Register name b7 Access characteristics b0 State immediately after reset b7 b0 E016 A-D register 8 E116 E216 A-D register 9 E316 E416 A-D register 10 E516 E616 A-D register 11 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 UART2 transmit interrupt control register F216 UART2 receive interrupt control register F316 F416 Timer A5 interrupt control register F516 Timer A6 interrupt control register F616 F716 Timer A7 interrupt control register F816 Timer A8 interrupt control register F916 Timer A9 interrupt control register FA16 FB16 FC16 INT5 interrupt control register FD16 INT6 interrupt control register FE16 INT7 interrupt control register FF16 (Note 19) (Note 19) (Note 19) (Note 19) (Note 19) (Note 19) (Note 19) (Note 19) (Note 20) (Note 20) (Note 20) (Note 20) (Note 20) (Note 20) (Note 20) (Note 20) RW RW ? 0 0 0 0 0 0 0 0 0 0 0 0 0 ? 0 ? 0 ? 0 ? ? ? ? ? ? ? ? ? ? ? ? ? RW RW RW RW RW ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? 0 0 ? 0 0 ? 0 0 ? (Note 20) (Note 20) (Note 20) RW RW RW Notes 19: The access characteristics at addresses E016 to E716 vary according to the contents of the comparator function select register 1 (address DD16). (Refer to “CHAPTER 12. A-D CONVERTER.”) 20: Do not write to this register. q Internal RAM area At hardware reset ................................................................................. Retains the state immediately before reset (Note 21). At software reset.................................................................................................... Retains the state immediately before reset. At termination of the stop or wait mode (when hardware reset is used for the termination.)....................................Retains the state immediately before the STP or WIT instruction is executed. At power-on reset..................................................................................................................................................... Undefined. Notes 21 : When a reset operation starts while writing to the internal RAM area is in process, the microcomputer will be reset before the completion of writing. Accordingly, the contents of the area where the writing was in process will become undefined. Fig. 3.3.9 State of SFR and internal RAM areas immediately after reset (8) 3-14 7905 Group User ’ s Manual Rev.1.0 RESET 3.4 Internal processing sequence after reset 3.4 Internal processing sequence after reset Figure 3.4.1 shows the internal processing sequence after reset. fsys ✽ AH(CPU) ✽ ✽ 0016 000016 Undefined IPL, Vector addresses of reset 0016 FFFE16 AD15 to AD 0 0016 AD15 to AD 0 Next op-code ALAM(CPU) DATA(CPU) ✽ fsys : System clock (See Figure 4.3.1.) AD0 to AD 15 : Internal address bus IPL : Processor interrupt priority level ✽ This is an internal signal and is not output to the external. Fig. 3.4.1 Internal processing sequence after reset 7905 Group User ’ s Manual Rev.1.0 3-15 RESET 3.4 Internal processing sequence after reset MEMORANDUM 3-16 7905 Group User ’ s Manual Rev.1.0 CHAPTER 4 CLOCK GENERATING CIRCUIT 4.1 Oscillation circuit examples 4.2 Clocks [Precautions for clcok generating circuit] C LOCK GENERATING CIRCUIT 4.1 Oscillation circuit examples 4.1 Oscillation circuit examples To the oscillation circuit, a ceramic resonator or a quartz-crystal oscillator can be connected, or the clock which is externally generated can be input. Oscillation circuit examples are shown below. 4.1.1 Connection example with resonator/oscillator Figure 4.1.1 shows an example where pins XIN and XOUT connect across a ceramic resonator/quartz-crystal oscillator. The circuit constants such as R f, Rd, C IN, and COUT ( shown in “ Figure 4.1.1”) depend on the resonator/ oscillator. These values shall be set to the values recommended by the resonator/oscillator manufacturer. M37905 XIN XOUT Rf Rd CIN COUT Fig. 4.1.1 Connection example of resonator/oscillator 4.1.2 Externally generated clock input example Figure 4.1.2 shows an input example of a clock which is externally generated. An external clock must be input from pin X IN, and pin X OUT m ust be left open. When an externally generated clock is input, the power source current consumption can be saved by the stop of internal circuit’s operation between pins XIN and XOUT. (Refer to “CHAPTER 16. POWER SAVING FUNCTION.”) M37905 XIN XOUT Open Externally generated clock Vcc Vss Fig. 4.1.2 Externally generated clock input example 4-2 7905 Group User’s Manual Rev.1.0 C LOCK GENERATING CIRCUIT 4.1 Oscillation circuit examples 4.1.3 Connection example of filter circuit In the usage of the PLL frequency multiplier, be sure to connect a filter circuit with pin VCONT. Figure 4.1.3 shows a connection example of the filter circuit. M37905 VCONT 1 kΩ 220 pF 0.1 µF Note: Connect the elements of the filter circuit as close as possible and enclose the whole circuit with a Vss pattern. Fig. 4.1.3 Connection example of filter circuit 7905 Group User ’ s Manual Rev.1.0 4-3 4-4 Peripheral device’s clocks Peripheral device’s clock select bit 1 φ1 0 0 4.2 Clocks 4.2 Clocks System clock stop select bit at WIT Wait mode PLL circuit operation enable bit Peripheral device’s clock select bit 0 Operating clock for serial I/O, timer B Operating clock for timer A A-D conversion frequency (φAD) clock source PLL multiplication ratio select bits f1 f2 f16 f64 f512 1/8 1/4 1/8 1/8 f4096 1/2 PLL frequency fPLL multiplier 1 1 Interrupt request 1 0 S Q System clock select bit STP instruction R fXIN 1/2 Wait mode 0 1 fsys 1/16 1/16 0 Watchdog timer frequency select bit Wf32 1 External clock input select bit f/n fX16 fX32 fX64 fX128 Wf512 VCONT Reset S Q Wait mode STP instruction R CPU wait request Watchdog timer ❈ Interrupt request Fig. 4.2.1 Clock generating circuit block diagram φ BIU (Clock for BIU) Watchdog timer clock source select bits at STP termination XIN XOUT C LOCK GENERATING CIRCUIT Interrupt request S Q Wait mode φ CPU (Clock for CPU) fX16 fX32 fX64 fX128 1 Figure 4.2.1 shows the clock generating circuit block diagram. 7905 Group User ’ s Manual Rev.1.0 External clock input select bit System clock frequency select bit • Watchdog timer frequency select bit • Watchdog timer clock source select bits at STP termination • External clock input select bit • System clock stop select bit at WIT • PLL circuit operation enable bit • PLL multiplication ratio select bits • System clock select bit • Peripheral device’s clock select bits 0, 1 : bit 0 at address 6116 : bits 6, 7 at address 6116 : bit 1 at address 6216 : bit 3 at address 6316 : bit 1 at address BC16 : bits 2, 3 at address BC16 : bit 5 at address BC16 : bits 6, 7 at address BC16 BIU : Bus interface Unit CPU : Central Processing Unit ❈ : Signal generated when the watchdog timer’s most significant bit becomes “0.” WIT instruction R 0 C LOCK GENERATING CIRCUIT 4.2 Clocks 4.2.1 Clocks generated in clock generating circuit (1) fX IN It is the input clock from pin X IN. (2) f PLL It is the output clock from the PLL frequency multiplier. (3) f sys It is the system clock which becomes the clock source of CPU, BIU, and internal peripheral devices. Whether fX IN = f sys o r f PLL = f sys c an be selected by software. (4) φ CPU It is the operating clock of CPU. (5) φ BIU It is the operating clock of BIU. (6) Clock φ1 It has the same period as f sys. (7) f 1, f 2, f 16, f 64, f 512, f 4096 Each of them is the internal peripheral device ’ s operating clock. (8) Wf 32, Wf 512 These are the operating clocks of the watchdog timer, and their clock source is f 2. (9) fX16 , fX 32, fX 64, fX 128 Each of them is the divide clock of fX IN a nd becomes the watchdog timer ’ s clock source at STP termination. 7905 Group User ’ s Manual Rev.1.0 4-5 C LOCK GENERATING CIRCUIT 4.2 Clocks 4.2.2 Clock control register 0 Figure 4.2.2 shows the structure of the clock control register 0, and Figure 4.2.3 shows the setting procedure for the clock control register 0 when using the PLL frequency multiplier. Clock control register 0 (Address BC16) Bit 0 1 Bit name Fix this bit to “1.” PLL circuit operation enable bit (Note 1) Function b7 b6 b5 b4 b3 b2 b1 b0 1 At reset 1 0 : PLL frequency multiplier is inactive, and pin VCONT is invalid. (Floating) 1 : PLL frequency multiplier is active, and pin VCONT is valid. b3 b2 1 R/W RW RW 1 2 3 4 5 6 7 PLL multiplication ratio select bits (Note 2) 0 0 : Do not select. 01:✕2 10:✕3 11:✕4 1 0 1 RW RW RW RW RW RW Fix this bit to “1.” System clock select bit 0 : fXIN (Note 3) 1 : fPLL 0 0 0 Peripheral device’s clock select bit 0 See Table 4.2.2. Peripheral device’s clock select bit 1 Notes 1: Clear this bit to “0” if the PLL frequency multiplier needs not to be active. In the stop and flash memory parallel I/O modes, the PLL frequency multiplier is inactive and pin VCONT is invalid regardless of the contents of this bit. 2: Rewriting of these bits must be performed simultaneously with clearance of the system clock select bit (bit 5) to “0.” Then, set bit 5 to “1” 2 ms after the rewriting of these bits. (After reset, these bits are allowed to be changed only once.) 3: Clearance of the PLL circuit operation enable bit (bit 1) to “0” clears the system clock select bit to “0.” Also, while the PLL circuit operation enable bit = “0,” nothing can be written to the system clock select bit. (Fixed to be “0.”) Before setting of set the system clock select bit to “1” after reset, it is necessary to insert an interval of 2 ms after the stabilization of f(XIN). Fig. 4.2.2 Structure of clock control register (1) PLL circuit operation enable bit (bit 1) Setting this bit to “ 1 ” e nables the PLL frequency multiplier to be active and pin V CONT t o be valid. This bit = “ 1 ” w hile pin RESET = “ L ” l evel and after reset, so that, in this case, the PLL frequency multiplier is active. Clear this bit to “ 0 ” i f the PLL frequency multiplier need not to be active. Note that, in the stop and flash memory parallel I/O modes, the PLL frequency multiplier is in active and pin VCONT is invalid regardless of the contents of this bit. (Refer to sections “15.3 Stop mode” and “ 19.4 Flash memory parallel I/O mode. ”) (2) PLL multiplication ratio select bits (bits 2, 3) These bits select the multiplication ratio of the PLL frequency multiplier. (See Table 4.2.1.) To rewrite these bits, clear the system clock select bit (bit 5) to “0” simultaneously. Then, set the system clock select bit to “ 1 ” 2 m s after the rewriting of this bit. (See Figure 4.2.3.) Note that, after reset, these bits are allowed to be changed only once. 4-6 7905 Group User ’ s Manual Rev.1.0 C LOCK GENERATING CIRCUIT 4.2 Clocks (3) System clock select bit (bit 5) This bit selects a clock source of fsys. When this bit = “ 0, ” f XIN i s selected as f sys; and when this bit = “ 1, ” f PLL a s the one. (See Table 4.2.1.) Clearing the PLL circuit operation enable bit (bit 1) to “0” clears the system clock select bit to “0.” Also, while the PLL circuit operation enable bit = “0,” nothing can be written to the system clock select bit. (Fixed to be “ 0. ” ) In order to set the system clock select bit to “ 1 ” a fter reset, it is necessary to wait 2 ms after the stabilization of f(XIN). To rewrite the PLL multiplication ratio select bits (bits 2 and 3), clear the system clock select bit to “0” simultaneously. Then, set this bit to “1” 2 ms after the rewriting of the PLL multiplication ratio select bits. (See Figure 4.2.3.) Table 4.2.1 f sys s election System clock select bit (bit 5) 0 1 PLL circuit operation enable bit (bit 1) – 1 fsys PLL multiplication ratio select bits (bits 3, 2) (Note 1) Clock source Frequency (Note 2) – 01 (double) 10 (triple) 11 (quadruple) fXIN f PLL f PLL f PLL f(XIN) f(XIN) ✕ 2 f(XIN) ✕ 3 f(XIN) ✕ 4 Notes 1: The PLL multiplication ratio select bits must be set so that fsys is in the range from 10 MHz to 20 MHz. After reset, these bits are allowed to be changed only once. 2: Be sure that fsys does not exceed 20 MHz. (4) Peripheral device ’ s clock select bits 1, 0 (bits 7, 6) These bits select the internal peripheral device ’ s operation clock frequency listed in Table 4.2.2. Table 4.2.2 Internal peripheral device’ s operation clock frequency Internal peripheral device’s operation clock f1 f2 f 16 f 64 f512 f 4096 fsys fsys/2 fsys/16 fsys/64 fsys/512 fsys/4096 Peripheral device’s clock select bits 1, 0 00 fsys fsys fsys/8 fsys/32 fsys/256 fsys/2048 01 (Note) fsys/2 fsys/4 fsys/32 fsys/128 fsys/1024 fsys/8192 Do not select. 10 11 Note: To set the peripheral device’s clock select bits 1, 0 to “012,” be sure that a frequency of fsys must be 10 MHz or less. 7905 Group User ’ s Manual Rev.1.0 4-7 C LOCK GENERATING CIRCUIT 4.2 Clocks b7 b0 00 1 1 Clock control register 0 (Address BC16) PLL frequency multiplier is active, and pin VCONT is valid. PLL multiplication ratio select bits (Note 1) b3 b2 01:✕2 10:✕3 11:✕4 System clock select bit 0 : fXIN (Note 2) 2 ms elapsed ? Y N Setting of system clock select bit to “1.” b7 b0 1 1 1 1 Clock control register 0 (Address BC16) System clock select bit 0 : fPLL Notes 1: After reset, these bits are allowed to be changed only once. If it is necessary to write a certain value to these bits, be sure to write the same value that has been written after the latest reset. 2: This decision is unnecessary If double is selected and the period of RESET = “L” is “the oscillation stabilizing time of an oscillator + 2 ms” or more. Fig. 4.2.3 Setting procedure for clock control register 0 when using PLL frequency multiplier 4-8 7905 Group User ’ s Manual Rev.1.0 C LOCK GENERATING CIRCUIT 4.2 Clocks 4.2.3 Particular function select register 0 Figure 4.2.4 shows the structure of the particular function select register 0, and Figure 4.2.5 shows the writing procedure for the particular function select register 0. Particular function select register 0 (Address 6216) Bit 0 1 Bit name Function b7 b6 b5 b4 b3 b2 b1 b0 000000 At reset 0 0 R/W RW (Note) RW (Note) STP instruction invalidity select bit 0 : STP instruction is valid. 1 : STP instruction is invalid. External clcok input select bit 0 : Oscillation circuit is active. (Oscillator is connected.) Watchdog timer is used at stop mode termination. 1 : Oscillation circuit is inactive. (External clock is input.) When the system clock select bit (bit 5 at address BC16) = “0,” watchdog timer is not used at stop mode termination. When the system clock select bit = “1,” watchdog timer is used at stop mode termination. 7 to 2 Fix this bit to “0.” 0 RW Note: Writing to these bits requires the following procedure: • Write “5516” to this register. (The bit status does not change only by this writing.) • Succeedingly, write “0” or “1” to each bit. Also, use the MOVMB (MOVM when m = 1) instruction or STAB (STA when m = 1) instruction. If an interrupt occurs between writing of “5516” and next writing of “0” or “1,” latter writing may be ignored. When there is a possibility that an interrupt occurs at the above timing, be sure to read this bit’s contents after writing of “0” or “1,” and verify whether “0” or “1” has correctly been written or not. Fig. 4.2.4 Structure of particular function select register 0 7905 Group User ’ s Manual Rev.1.0 4-9 C LOCK GENERATING CIRCUIT 4.2 Clocks (1) External clock input select bit (bit 1) When this bit is “0,” the oscillation driver circuit between pins XIN and XOUT operates. At the stop mode termination owing to an interrupt request occurrence, the watching timer is used. Setting this bit to “1” stops the oscillation driver circuit between pins XIN and XOUT and keeps the output level at pin X OUT b eing “ H. ” ( Refer to section “ 16.3 Stop of oscillation circuit. ” ) At the stop mode termination owing to an interrupt request occurrence, the watchdog timer is not used if the system clock select bit (bit 5 at address BC16) = “0,” where as the watchdog timer is used if the system clock select bit = “ 1. ” To rewrite this bit, write “ 0 ” o r “ 1 ” j ust after writing of “ 55 16” t o address 62 16. (See Figure 4.2.5.) Note that if an interrupt occurs between writing of “ 55 16” a nd next writing of “ 0 ” o r “ 1, ” l atter writing may be ignored. When there is a possibility that an interrupt occurs at the above timing, be sure to read this bit ’ s contents after writing of “ 0 ” o r “ 1, ” a nd verify whether “ 0 ” o r “ 1 ” h as correctly been written or not. In addition, even when the watchdog timer is disabled by the particular function select register 2 (address 64 16), the watchdog timer can be active only at the stop mode termination if this bit = “ 0. ” (Refer to section “ 15.3 Stop mode. ” ) Writing of “5516” b7 b0 0 1 01 0 1 0 1 Particular function select register 0 (Address 6216) Note: Bits’ state does not change only by writing of “5516.” Next instruction Writing to bits 0, 1 b7 b0 00 0 0 0 0 Particular function select register 0 (Address 6216) STP instruction invalidity select bit 0 : STP instruction is valid. 1 : STP instruction is invalid. External clock input select bit 0 : Oscillation circuit is active. (Oscillator is connected.) Watchdog timer is used at stop mode termination. 1 : Oscillation circuit is inactive. (External clock is input.) When the system clock select bit (bit 5 at address BC16) = “0,” watchdog timer is not used at stop mode termination. When the system clock select bit = “1,” watchdog timer is used at stop mode termination. Setting completed Fig. 4.2.5 Writing procedure for particular function select register 0 4-10 7905 Group User ’ s Manual Rev.1.0 C LOCK GENERATING CIRCUIT [Precautions for clock generating circuit] [Precautions for clock generating circuit] 1. While pin RESET = “L” level and after reset, the PLL frequency multiplier is inactive. Clear the PLL circuit operation enable bit (bit 1 at address BC16) to “0” if the PLL frequency multiplier needs not to be active. 2. To select f PLL a s fsys a fter reset, set the system clock select bit (bit 5 at address BC16) to “ 1 ” 2 m s after f(XIN) has been stabilized. (See Figure 4.2.3.) 3. To change the multiplication ratio for the PLL frequency multiplier, clear the system clock select bit (bit 5 at address BC 16) to “ 0 ” s imultaneously. Then, set the system clock select bit to “ 1 ” 2 m s after the rewriting of the PLL multiplication ratio select bits (bits 2, 3 at address BC 16). (See Figure 4.2.3.) After reset, the PLL multiplication ratio select bits are allowed to be changed only once. If it is necessary to write a certain value to these bits, be sure to write the same value that has been written after the latest reset. 7905 Group User ’ s Manual Rev.1.0 4-11 C LOCK GENERATING CIRCUIT [Precautions for clock generating circuit] MEMORANDUM 4-12 7905 Group User ’ s Manual Rev.1.0 CHAPTER 5 INPUT/OUTPUT PINS 5.1 Overview 5.2 Programmable I/O ports 5.3 Examples of handling unused pins INPUT/OUTPUT PINS 5.1 Overview, 5.2 Programmable I/O ports 5.1 Overview Input/output pins (hereafter called I/O pins) have functions as programmable I/O port pins, internal peripheral devices’s I/O pins, etc. For the basic functions of each I/O pin, refer to section “1.3 Pin description.” For the I/O functions of the internal peripheral devices, refer to relevant sections of each internal peripheral device. This chapter describes the programmable I/O ports and examples of handling unused pins. 5.2 Programmable I/O ports The programmable I/O ports have direction registers and port registers in the SFR area. Figure 5.2.1 shows the memory map of direction registers and port registers. Addresses 316 416 516 616 716 816 916 A16 B16 C16 D16 E16 F16 1016 1116 1216 1316 1416 Port P1 register (Note) Port P1 direction register Port P2 register (Note) Port P2 direction register (Note) Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register (Note) Port P8 direction register Note: Do not write to this address. Fig. 5.2.1 Memory map of direction registers and port registers 5-2 7905 Group User’s Manual Rev.1.0 INPUT/OUTPUT PINS 5.2 Programmable I/O ports 5.2.1 Direction register This register determines the I/O direction of programmable I/O ports. One bit of this register corresponds to one pin of the microcomputer, and this is the one-to-one relationship. Figure 5.2.2 shows the structure of port Pi (i = 1, 2, 4 to 8) direction register. Port Pi direction register (i = 1, 2, 4 to 8) (Addresses 516, 816, C16, D16, 1016, 1116, 1416) Bit 0 1 2 3 4 5 6 7 Bit name Port Pi0 direction bit Port Pi1 direction bit Port Pi2 direction bit Port Pi3 direction bit Port Pi4 direction bit Port Pi5 direction bit Port Pi6 direction bit Port Pi7 direction bit 0 : Input mode (The port functions as an input port.) 1 : Output mode (The port functions as an output port.) Function b7 b6 b5 b4 b3 b2 b1 b0 At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Notes 1: Nothing is assigned for bits 0 and 4 of the port P5 direction register. These bits are undefined at reading. 2: Nothing is assigned for bits 4 to 7 of the port P8 direction register. These bits are undefined at reading. 3: Any of bits 0 to 7 of the port P4 direction register becomes “0” by input of a falling edge to pin P4OUTCUT/INT0. (Refer to section “5.2.3 Pin P4OUTCUT/INT0.”) 4: Any of bits 0 to 7 of the port P6 direction register becomes “0” by input of a falling edge to pin P6OUTCUT/INT4. (Refer to section “5.2.4 Pin P6OUTCUT/INT4.”) Fig. 5.2.2 Structure of port Pi (i = 1, 2, 4 to 8) direction register 7905 Group User ’ s Manual Rev.1.0 5-3 INPUT/OUTPUT PINS 5.2 Programmable I/O ports 5.2.2 Port register Data is input from or output to the external by writing/reading data to/from a port register. A port register consists of a port latch which holds the output data and a circuit which reads the pin state. One bit of the port register corresponds to one pin of the microcomputer. (This is the one-to-one relationship.) Figure 5.2.3 shows the structure of the port Pi (i = 1, 2, 4 to 8) register. q W hen outputting data from programmable I/O port which has been set to output mode ➀ B y writing data to the corresponding bit of the port register, the data is written into the port latch. ➁ T he data is output from the pin according to the contents of the port latch. By reading the port register of a port which has been set to the output mode, the contents of the port latch is read out, instead of the pin state. Accordingly, the output data can be correctly read out without being affected by an external load, etc. (See “ Figures 5.2.4 and 5.2.5. ”) q W hen inputting data from programmable I/O port which has been set to input mode ➀ A pin which has been set to the input mode enters the floating state. ➁ By reading the corresponding bit of the port register, the data which has been input from the pin can be read out. By writing data to a port register of a programmable I/O port which has been set to the input mode, the data is written only into the port latch and is not output to the external ( Note) . This pin remains floating state. Note: When executing a read-modify-write instruction to a port register of a programmable I/O port which has been set to the input mode, the instruction will be executed to the data which has been input from the pin and the result will be written into the port register. Port Pi register (i = 1, 2, 4 to 8) (Addresses 316, 616, A16, B16, E16, F16, 1216) Bit 0 1 2 3 4 5 6 7 Port pin Pi0 Port pin Pi1 Port pin Pi2 Port pin Pi3 Port pin Pi4 Port pin Pi5 Port pin Pi6 Port pin Pi7 Bit name Funtion b7 b6 b5 b4 b3 b2 b1 b0 At reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W RW RW RW RW RW RW RW RW Data is input from or output to a pin by reading from or writing to the corresponding bit. 0 : “L” level 1 : “H” level Notes 1: Nothing is assigned for bits 0 and 4 of the port P5 register. These bits are undefined at reading. 2: Nothing is assigned for bits 4 to 7 of the port P8 register. These bits are undefined at reading. Fig. 5.2.3 Structure of port Pi (i = 1, 2, 4 to 8) register 5-4 7905 Group User ’ s Manual Rev.1.0 INPUT/OUTPUT PINS 5.2 Programmable I/O ports Figures 5.2.4 to 5.2.6 show the port peripheral circuits. [Inside dotted-line not included] P2 7 [Inside dotted-line included] P12/RXD0, P16/RXD1 P21/TA4 IN, P2 3/TA9 IN P24(/TB0IN), P25(/TB1IN) P26(/TB2IN), P5 1/INT1 P52/INT2/RTPTRG1 P53/INT3/RTPTRG0 P55/INT5/TB0IN/IDW P56/INT6/TB1IN/IDV P57/INT7/TB2IN/IDU Direction register Data bus Port latch Direction register [Inside dotted-line not included] P13 /TXD0, P17/TXD1 Data bus Port latch 1 Output (internal peripheral device) [Inside dotted-line included] P20/TA4 OUT, P2 2/TA9 OUT P4 0/TA5 OUT/RTP20 P4 1/TA5 IN/RTP21 P4 2/TA6 OUT/RTP22 P4 3/TA6 IN/RTP23 P4 4/TA7 OUT/RTP30 P4 5/TA7 IN/RTP31 P4 6/TA8 OUT/RTP32 P4 7/TA8 IN/RTP33 P4OUTCUT Reset Data bus Direction register R 1 Output (internal peripheral device) Port latch P6 0/TA0 OUT/W/RTP00 P6 1/TA0 IN/V/RTP01 P6 2/TA1 OUT/U/RTP02 P6 3/TA1 IN/W/RTP03 P6 4/TA2 OUT/V/RTP10 P6 5/TA2 IN/U/RTP11 P6 6/TA3 OUT/RTP12 P6 7/TA3 IN/RTP13 P6OUTCUT Reset Data bus Direction register R 1 Output (internal peripheral device) Port latch Fig. 5.2.4 Port peripheral circuits (1) 7905 Group User ’ s Manual Rev.1.0 5-5 INPUT/OUTPUT PINS 5.2 Programmable I/O ports Direction register P70/AN0, P7 1/AN1 P72/AN2, P7 3/AN3 P74/AN4, P7 5/AN5 P76/AN6 Data bus Port latch Analog input Direction register P77/AN7/DA0 Data bus Port latch Analog input Analog output Enable D-A output 1 0 P10/CTS0/RTS0 P11/CTS0/CLK0 P14/CTS1/RTS1 P15/CTS1/CLK1 Direction register Output (internal peripheral device) Data bus Port latch Direction register 1 0 P80/AN8/CTS2/RTS2/DA1 Output (internal peripheral device) Data bus Port latch Analog input Analog output Enable D-A output 1 0 P81/AN9/CTS2/CLK2 Direction register Output (internal peripheral device) Data bus Port latch Analog input Fig. 5.2.5 Port peripheral circuits (2) 5-6 7905 Group User ’ s Manual Rev.1.0 INPUT/OUTPUT PINS 5.2 Programmable I/O ports Direction register P8 2/AN10/RXD0 Data bus Port latch Analog input Direction register 1 P8 3/AN11 /TXD2 Output (internal peripheral device) Data bus Port latch Analog input P4OUTCUT/INT0, P6OUTCUT/INT4 Fig. 5.2.6 Port peripheral circuits (3) 5.2.3 Pin P4OUTCUT/INT0 ( Port-P4-output-cutoff signal input pin) Any of bits 0 through 7 of the port P4 direction register (address C16) are forcibly cleared to “ 0 ” b y input of a falling edge to pin P4OUTCUT/INT0, regardless of the mode of port pins P40 through P47; therefore, port pins P4 0 through P47 enter the input mode. After that, if it is necessary to output data from port pins P40 through P4 7, be sure to do as follows: ➀ R eturn the input level at pin P4OUT CUT/INT 0 t o “ H ” l evel. ➁ Write data to the port P4 register (address A16)’s bits, corresponding to the port P4 pins which will output data. ➂ S et the port P4 direction register ’ s bits, corresponding to the port P4 pins in ➁, to “ 1 ” i n order to set these port pins to the output mode. When input level at pin P4OUT CUT/INT 0 i s “ L ” , no bit of the port P4 direction register can be set to “ 1. ” When using port pins P4 0 t hrough P47 a s output port pins at all the time, connect pin P4OUTCUT /INT0 t o Vcc via a resistor. Pin P4OUT CUT/INT 0 c annot serve as pin INT 0. Also, when using pin P4OUTCUT/INT 0 as an input pin of an external interrupt (pin INT0), use port pins P4 0 through P4 7 i n the input mode. 5.2.4 Pin P6OUTCUT/INT4 ( Port-P6-output-cutoff signal input pin) Any of bits 0 through 7 of the port P6 direction register (address 1016) are forcibly cleared to “0” by input of a falling edge to pin P6OUTCUT/INT4, regardless of the mode of port pins P60 through P67; therefore, port pins P6 0 through P67 enter the input mode. After that, if it is necessary to output data from port pins P60 through P6 7, be sure to do as follows: ➀ R eturn the input level at pin P6OUT CUT/INT 4 t o “ H ” l evel. ➁ Write data to the port P6 register (address E16)’s bits, corresponding to the port P6 pins which will output data. ➂ S et the port P6 direction register ’ s bits, corresponding to the port P6 pins in ➁, to “ 1 ” i n order to set these port pins to the output mode. When input level at pin P6OUT CUT/INT 4 i s “ L ” , no bit of the port P6 direction register can be set to “ 1. ” When using port pins P6 0 t hrough P67 a s output port pins at all the time, connect pin P6OUTCUT /INT4 t o Vcc via a resistor. Pin P6OUT CUT/INT 4 c annot serve as pin INT 4. Also, when using pin P6OUTCUT/INT 4 as an input pin of an external interrupt (pin INT4), use port pins P6 0 through P6 7 i n the input mode. 7905 Group User ’ s Manual Rev.1.0 5-7 INPUT/OUTPUT PINS 5.3 Examples of handling unused pins 5.3 Examples of handling unused pins When unusing an I/O pin, some handling is necessary for this pin. Examples of handling unused pins are described below. The following are just examples. In actual use, the user shall modify them according to the user’s application and properly evaluate their performance. Table 5.3.1 Example of handling unused pins Pin name P1, P2, P4 to P8 Handling example Set these pins to the input mode and connect each pin to Vcc or Vss via a resistor; or set these pins to the output mode and leave them open ( Note 1). P4OUTCUT/INT 0, P6OUTCUT/INT 4 XOUT ( Note 2) , VCONT ( Note 3) AVCC AVSS, VREF Connect this pin to Vcc via a resistor. Select a falling edge for pins INT 0 a nd INT 4. Leave these pins open. Connect this pin to Vcc. Connect these pins to Vss. Notes 1: W hen leaving these pins open after they have been set to the output mode, note the following: these port pins are placed in the input mode from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these port pins are placed in the input mode. Software reliability can be enhanced by setting the contents of the above ports’ direction registers periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins). 2: This applies when a clock externally generated is input to pin X IN. 3: Be sure that the PLL circuit operation enable bit (bit 1 at address BC16) = “0.” s When setting port pins to input mode s When setting port pins to output mode P1, P2, P4 to P8 XOUT VCONT P1, P2, P4 to P8 XOUT VCONT Left open Left open VCC Left open VCC P4OUTCUT/INT0 P6OUTCUT/INT4 Fig. 5.3.1 Example of handling unused pins M37905 M37905 AV CC AV SS VREF VCC AV CC AV SS VREF VCC VSS VSS P4OUTCUT/INT0 P6OUTCUT/INT4 5-8 7905 Group User ’ s Manual Rev.1.0 CHAPTER 6 INTERRUPTS 6.1 6.2 6.3 6.4 6.5 Overview Interrupt sources Interrupt control Interrupt priority level Interrupt priority level detection circuit 6.6 Interrupt priority level detection time 6.7 Sequence from acceptance of interrupt request until execution of interrupt routine 6.8 Return from interrupt routine 6.9 Multiple interrupts 6.10 External interrupts [Precautions for interrupts] INTERRUPTS 6.1 Overview 6.1 Overview The M37905 provides 32 (including the reset) interrupt sources to generate interrupt requests. Figure 6.1.1 shows the interrupt processing sequence. When an interrupt request is accepted, a branch is made to the start address of the interrupt routine set in the interrupt vector table (addresses FFB4 16 to FFFF 16). Set the start address of each interrupt routine to the corresponding interrupt vector address in the interrupt vector table. Routine in progress dr t ad star e. to n hes outi anc rrupt r Br te of in ess Interrupt routine Interrupt processing Interrupt request is accepted. Processing is suspended. Processing is resumed. Retu rns t o ori ginal routi ne. RTI instruction Fig. 6.1.1 Interrupt processing sequence When an interrupt request is accepted, the following registers’ contents just before acceptance of an interrupt request are automatically pushed onto the stack area in ascending sequence from ➀ t o ➂. For other registers of which contents are necessary, be sure to push and pop them by software. ➀ P rogram bank register (PG) ➁ P rogram counter (PC L, PC H) ➂ P rocessor status register (PS L, PS H) Figure 6.1.2 shows the state of the stack area just before entering an interrupt routine. Execute the RTI instruction at the end of this interrupt routine in order to return to the routine that the microcomputer was executing just before the interrupt request was accepted. By executing the RTI instruction, the register contents pushed onto the stack area are pulled in descending sequence from ➂ t o ➀. Then, the suspended processing is resumed from where it left off. Stack area Address [S] – 5 [S] – 4 Processor status register’s low-order byte (PSL) [S] – 3 Processor status register’s high-order byte (PSH) [S] – 2 [S] – 1 [S]✽ Program counter’s low-order byte (PCL) Program counter’s high-order byte (PCH) Program bank register (PG) ✽ [S] is an initial address that the stack pointer (S) indicates when an interrupt request is accepted. The S’s contents become “[S] – 5” after all of the above registers are pushed. Fig. 6.1.2 State of stack area just before entering interrupt routine 6-2 7 905 Group User’s Manual Rev.1.0 INTERRUPTS 6.2 Interrupt sources 6.2 Interrupt sources Tables 6.2.1 and 6.2.2 list the interrupt sources and the interrupt vector addresses. When programming, set the start address of each interrupt routine to the vector addresses listed in these tables. Table 6.2.1 Interrupt sources and interrupt vector addresses (1) Interrupt vector addresses Interrupt source Reset Zero division BRK instruction (Note) High-order Low-order address address FFFF 16 FFFD16 FFFB 16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF 16 FFED 16 FFEB16 FFE9 16 FFE7 16 FFE5 16 FFE3 16 FFE1 16 FFDF16 FFDD 16 FFDB 16 FFD9 16 FFD7 16 FFD5 16 FFD3 16 FFD1 16 FFCF16 FFCD 16 FFCB 16 FFC9 16 FFC7 16 FFC5 16 FFC3 16 FFFE 16 FFFC16 FFFA 16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC 16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE 16 FFDC16 FFDA 16 FFD8 16 FFD6 16 FFD4 16 FFD2 16 FFD0 16 FFCE 16 FFCC16 FFCA 16 FFC8 16 FFC6 16 FFC4 16 FFC2 16 Do not use. Remarks Non-maskable Non-maskable software interrupt Do not use. Non-maskable internal interrupt Do not use. Maskable external interrupts Reference 3. RESET 7900 Series Software Manual DBC ( Note) Watchdog timer Reserved area INT0 INT1 INT2 Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 UART0 receive UART0 transmit UART1 receive UART1 transmit A-D conversion INT3 INT4 Reserved area Reserved area Address matching detection 14. WATCHDOG TIMER 6.10 External interrupts Maskable internal interrupts 7. TIMER A Maskable internal interrupts 8. TIMER B Maskable internal interrupts 11. SERIAL I/O Maskable internal interrupt Maskable external interrupts 12. A-D CONVERTER 6.10 External interrupts Non-maskable software interrupt 17. DEBUG FUNCTION Do not use. Maskable external interrupts 6.10 External interrupts Reserved area INT5 INT6 INT7 Note: T he B RK i nstruction and the DBC interrupt are used exclusively for a debugger. q M askable interrupt: A n interrupt of which request ’ s acceptance can be disabled by software. q Non-maskable interrupt (including zero division, watchdog timer, and address matching detection interrupts): An interrupt which is certain to be accepted when its request occurs. These interrupts do not have their interrupt control registers and are not affected by the interrupt disable flag (I). 7 905 Group User ’ s Manual Rev.1.0 6-3 INTERRUPTS 6.2 Interrupt sources Table 6.2.2 Interrupt sources and interrupt vector addresses (2) Interrupt vector addresses Interrupt source Timer A5 Timer A6 Timer A7 Timer A8 Timer A9 UART2 transmit UART2 receive High-order Low-order address address FFC1 16 FFBF 16 FFBD16 FFBB16 FFB916 FFB716 FFB516 FFC0 16 FFBE16 FFBC16 FFBA16 FFB816 FFB616 FFB416 Remarks Maskable internal interrupts Reference 7. TIMER A Maskable internal interrupts 11. SERIAL I/O q M askable interrupt: A n interrupt of which request ’ s acceptance can be disabled by software. 6-4 7 905 Group User ’ s Manual Rev.1.0 INTERRUPTS 6.3 Interrupt control 6.3 Interrupt control The maskable interrupts are controlled by the following : • Interrupt request bit Assigned to an interrupt control register of each interrupt. • Interrupt priority level select bits • Processor interrupt priority level (IPL) Assigned to the processor status register (PS). • Interrupt disable flag (I) } } Figure 6.3.1 shows the memory assignment of the interrupt control registers, and Figures 6.3.2 shows their structures. Address 6E16 6F16 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C16 7D16 7E16 7F16 INT3 interrupt control register INT4 interrupt control register A-D conversion interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register F116 F216 UART2 transmit interrupt control register UART2 receive interrupt control register F516 F616 F716 F816 F916 Timer A5 interrupt control register Timer A6 interrupt control register Timer A7 interrupt control register Timer A8 interrupt control register Timer A9 interrupt control register FD16 FE16 FF16 INT5 interrupt control register INT6 interrupt control register INT7 interrupt control register Fig. 6.3.1 Memory assignment of interrupt control registers 7 905 Group User ’ s Manual Rev.1.0 6-5 INTERRUPTS 6.3 Interrupt control INT0, INT1, INT2 interrupt control registers (Addresses 7D16, 7E16, 7F16) INT3, INT4 interrupt control registers (Addresses 6E16, 6F16) INT5, INT6, INT7 interrupt control registers (Addresses FD16, FE16, FF16) Bit 0 1 2 3 4 Interrupt request bit (Note 1) Polarity select bit Bit name Interrupt priority level select bits b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 Function 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested 0 : The interrupt request bit is set to “1” at “H” level when level sense is selected; this bit is set to “1” at falling edge when edge sense is selected. 1 : The interrupt request bit is set to “1” at “L” level when level sense is selected; this bit is set to “1” at rising edge when edge sense is selected. 0 : Edge sense 1 : Level sense At reset 0 0 0 0 0 R/W RW RW RW RW (Note 2) RW 5 7, 6 Level sense/Edge sense select bit Nothing is assigned. 0 Undefined RW — Notes 1: The interrupt request bits of INT0 to INT7 interrupts are invalid when the level sense is selected. 2: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2 interrupt control registers (Addresses 7016 to 7C16) UART2 transmit, UART2 receive interrupt control registers (Addresses F116, F216) Timers A5 to A9 interrupt control registers (Addresses F516 to F916) Bit 0 1 2 3 7 to 4 Interrupt request bit Nothing is assigned. Bit name Interrupt priority level select bits b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 Function 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested At reset 0 0 0 R/W RW RW RW RW 0 (Note 1) (Note 2) Undefined — Notes 1: The A-D conversion interrupt request bit is undefined after reset. 2: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. Fig. 6.3.2 Structure of interrupt control register 6-6 7 905 Group User ’ s Manual Rev.1.0 INTERRUPTS 6.3 Interrupt control 6.3.1 Interrupt disable flag (I) All maskable interrupts can be disabled by this flag. When this flag is set to “ 1, ” a ll maskable interrupts are disabled; when this flag is cleared to “0,” those interrupts are enabled. Because this flag is set to “1” at reset, clear this flag to “ 0 ” w hen enabling interrupts. 6.3.2 Interrupt request bit When an interrupt request occurs, this bit is set to “1.” This bit remains set to “1” until the interrupt request is accepted; it is cleared to “ 0 ” w hen the interrupt request is accepted. This bit can also be set to “ 0 ” o r “ 1 ” b y software. The INTi interrupt request bit (i = 0 to 7) is ignored when the corresponding INT i interrupt is used with the level sense. 6.3.3 Interrupt priority level select bits and Processor interrupt priority level (IPL) The interrupt priority level select bits are used to determine the priority level of each interrupt. When an interrupt request occurs, its interrupt priority level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled only when the comparison result meets the following condition. Accordingly, a ny interrupt can be disabled by setting its interrupt priority level to 0. Each interrupt priority level > Processor interrupt priority level (IPL) Table 6.3.1 lists the setting of interrupt priority levels, and Table 6.3.2 lists the enabled interrupt’ s levels according to the IPL contents. The interrupt disable flag (I), interrupt request bit, interrupt priority level select bits, and processor interrupt priority level (IPL) are independent of one another; they do not affect one another. Interrupt requests are accepted only when all of the following conditions are satisfied. • Interrupt disable flag (I) = “ 0 ” • Interrupt request bit = “ 1 ” • Interrupt priority level > Processor interrupt priority level (IPL) 7 905 Group User ’ s Manual Rev.1.0 6-7 INTERRUPTS 6.3 Interrupt control Table 6.3.1 Setting of interrupt priority level Interrupt priority level select bits b1 b0 b2 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 Interrupt priority level Level 0 (Interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High Priority — Low Table 6.3.2 Enabled interrupt’s levels according to IPL contents IPL 2 0 0 0 0 1 1 1 1 IPL1 0 0 1 1 0 0 1 1 IPL0 0 1 0 1 0 1 0 1 Enabled interrupt ’s level Level 1 and above are enabled. Level 2 and above are enabled. Level 3 and above are enabled. Level 4 and above are enabled. Level 5 and above are enabled. Levels 6 and 7 are enabled. Only level 7 is enabled. All maskable interrupts are disabled. IPL 0: B it 8 in processor status register (PS) IPL 1: B it 9 in processor status register (PS) IPL 2: B it 10 in processor status register (PS) 6-8 7 905 Group User ’ s Manual Rev.1.0 INTERRUPTS 6.4 Interrupt priority level 6.4 Interrupt priority level When the interrupt disable flag (I) = “0” (interrupts enabled) and more than one interrupt request is detected at the same sampling timing, which means a timing to check whether an interrupt request exists or not, they are accepted in descending sequence from the highest priority level. A maskable interrupt can be set to the desired priority level by using the interrupt priority level select bits. The priority levels of reset and a watchdog timer interrupt are set by hardware. Figure 6.4.1 shows the interrupt priority levels set by hardware. Note that software interrupts are not affected by the interrupt priority levels. Whenever an instruction is executed, a branch is certainly made to the interrupt routine. Reset Watchdog timer •••••••••••••••••• Maskable interrupts Priority levels determined by hardware The user can set the desired priority level to a maskable interrupt. High Priority level Low Fig. 6.4.1 Interrupt priority levels set by hardware 7 905 Group User ’ s Manual Rev.1.0 6-9 INTERRUPTS 6.5 Interrupt priority level detection circuit 6.5 Interrupt priority level detection circuit The interrupt priority level detection circuit is used to select the interrupt with the highest priority level from multiple interrupt requests sampled at the same timing. Figure 6.5.1 shows the interrupt priority level detection circuit. Level 0 (Initial value) Interrupt priority level Interrupt priority level UART2 transmit UART1 transmit UART2 receive UART1 receive Timer A9 UART0 transmit Timer A8 UART0 receive Timer A7 Timer B2 Timer A6 Timer B1 Timer A5 Timer B0 INT7 Timer A4 INT6 Timer A3 INT5 Timer A2 INT4 Timer A1 INT3 Timer A0 A-D conversion INT2 INT1 INT0 Interrupt with the highest priority level IPL Processor interrupt priority level Interrupt disable flag (I) Watchdog timer interrupt Reset Acceptance of interrupt request Fig. 6.5.1 Interrupt priority level detection circuit 6-10 7 905 Group User ’ s Manual Rev.1.0 INTERRUPTS 6.5 Interrupt priority level detection circuit The following explains the operation of the interrupt priority level detection circuit using Figure 6.5.2. The interrupt priority level of a requested interrupt (Y in Figure 6.5.2) is compared with the resultant priority level which is sent from the preceding comparator (X in Figure 6.5.2); the interrupt with the higher priority level will be sent to the next comparator (Z in Figure 6.5.2). (The initial value of the comparison level is “0.”) For an interrupt which is not requested, the comparison is not performed, and the priority level which is sent from the preceding comparator is sent to the next comparator as it is. When the two priority levels are found the same, as a resultant of the comparison, the priority level which is sent from the preceding comparator will be sent to the next comparator. Accordingly, when the same priority level is set to multiple interrupts by software, their interrupt priority levels are handled as follows: UART2 transmit > UART2 receive > Timer A9 > Timer A8 > Timer A7 > Timer A6 > Timer A5 > INT7 > INT6 > INT 5 > I NT 4 > I NT 3 > A -D conversion > UART1 transmit > UART1 receive > UART0 transmit > UART0 receive > Timer B2 > Timer B1 > Timer B0 > Timer A4 > Timer A3 > Timer A2 > Timer A1 > Timer A0 > INT 2 > I NT 1 > I NT0 Among the multiple interrupt requests sampled at the same timing, one request with the highest priority level is detected by the above comparison. Then, this highest interrupt priority level is compared with the processor interrupt priority level (IPL). When this interrupt priority level is higher than IPL and the interrupt disable flag (I) is “0,” the interrupt request is accepted. An interrupt request which is not accepted here is retained until it is accepted or its interrupt request bit is cleared to “ 0 ” b y software. The interrupt priority level is detected when the CPU fetches an op code, which is called the CPU’s op-code fetch cycle. However, when an op-code fetch cycle starts during detection of an interrupt priority, a new interrupt priority detection does not start. (See Figure 6.6.2.) Since the state of the interrupt request bit and interrupt priority levels are latched during the interrupt priority detection, even if they change, the interrupt priority detection is performed for the state just before the change occurs. The interrupt priority level is detected when the CPU fetches an op code. Therefore, in the following case, no interrupt request is accepted until the CPU fetches the op code of the next instruction after the following operation is completed: • Execution of an instruction which requires many cycles, such as the M VN a nd M VP i nstructions X Y Interrupt source Y Comparator (Priority level comparison) Z X : Priority level sent from the preceding comparator (Highest priority level at this point) Y : Priority level of interrupt source Y Z : Highest priority level at this point qWhen X ≥ Y then Z = X qWhen X < Y then Z = Y Time Fig. 6.5.2 Interrupt priority level detection model 7 905 Group User ’ s Manual Rev.1.0 6-11 INTERRUPTS 6.6 Interrupt priority level detection time 6.6 Interrupt priority level detection time When the interrupt priority level detection time has passed after sampling starts, an interrupt request is accepted. The interrupt priority level detection time can be selected by software. (See Figure 6.6.1.) Usually, select “2 cycles of f sys” as the interrupt priority level detection time. Figure 6.6.2 shows the interrupt priority level detection time. b7 b6 b5 b4 b3 b2 b1 b0 Processor mode register 0 (Address 5E16) Bit 0 1 2 3 4 5 6 7 Software reset bit Fix this bit to “0.” Interrupt priority detection time select bits b5 b4 0 Function XX00 At reset 0 0 0 1 R/W RW RW RW RW RW RW WO RW Bit name Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Do not select. 1 0 : Do not select. 1 1 : Do not select. Any of these bits may be either “0” or “1.” 0 0 : 7 cycles of fsys 0 1 : 4 cycles of fsys 1 0 : 2 cycles of fsys 1 1 : Do not select. The microcomputer is reset by writing “1” to this bit. The value is “0” at reading. 0 0 0 0 X : It may be either “0” or “1.” Fig. 6.6.1 Structure of processor mode register 0 fsys Op-code fetch cycle Sampling pulse (a) 7 cycles of fsys Interrupt priority level detection time (b) 4 cycles of fsys (c) 2 cycles of fsys Note: The pulse resides when “2 cycles of fsys” is selected. (Note) Fig. 6.6.2 Interrupt priority level detection time 6-12 7 905 Group User’s Manual Rev.1.0 INTERRUPTS 6.7 Sequence from acceptance of interrupt request until execution of interrupt routine 6.7 Sequence from acceptance of interrupt request until execution of interrupt routine The sequence from acceptance of an interrupt request until execution of the interrupt routine is described below. When an interrupt request is accepted, the interrupt request bit of the accepted interrupt is cleared to “0.” And then, the interrupt processing starts from the cycle just after completion of the instruction execution which was executed at acceptance of the interrupt request. Figure 6.7.1 shows the sequence from occurrence of an interrupt request until execution of the interrupt routine. After execution of an instruction at acceptance of the interrupt request is completed, an INTACK (Interrupt Acknowledge) sequence is executed, and a branch is made to the start address of the interrupt routine allocated in addresses 0 16 t o FFFF 16. In the INTACK sequence, the following are automatically performed in ascending sequence from ➀ t o ➅. ➀ The contents of the program bank register (PG) just before performing the INTACK sequence are pushed onto stack. ➁ The contents of the program counter (PC) just before performing the INTACK sequence are pushed onto stack. ➂ T he contents of the processor status register (PS) just before performing the INTACK sequence is pushed onto stack. ➃ T he interrupt disable flag (I) is set to “ 1. ” ➄ The interrupt priority level of the accepted interrupt is set into the processor interrupt priority level (IPL). ➅ The contents of the program bank register (PG) are cleared to “0016,” and the contents of the interrupt vector address are set into the program counter (PC). Performing the INTACK sequence requires at least 15 cycles of fsys. Figure 6.7.2 shows the INTACK sequence timing. After the INTACK sequence is completed, the instruction execution starts from the start address of the interrupt routine. Interrupt request is accepted. Interrupt request occurs. @ Instruction Instruction 1 2 @ INTACK sequence ➂ Interrupt response time Time Instructions in interrupt routine ➀ ➁ @ : Interrupt priority level detection time ➀ Time from occurrence of an interrupt request until comparison of an instruction execution which is in progress at that time. ➁ Time from execution start of an instruction next to ➀ until completion of execution of the instruction which was in progress at detection completed. ➂ Time required to perform the INTACK sequence (15 cycles of φ at minimum) Fig. 6.7.1 Sequence from occurrence of interrupt request until execution of interrupt routine 7 905 Group User ’ s Manual Rev.1.0 6-13 INTERRUPTS 6.7 Sequence from acceptance of interrupt request until execution of interrupt routine q When stack pointer (S)’s contents are even at acceptance of an interrupt request with bus cycle = 2 φ (Note) fsys φCPU AD23–AD16 (Note) (Note) Undefined 00 00 00 00 00 00 (Note) AD15–AD0 (Note) Undefined 0000 [S] [S] – 2 [S] – 4 FFXX16 AD15–AD0 DB15–DB8 (Note) Undefined IPL — PCH PSH AD15–AD8 Next instruction DB7–DB0 (Note) Undefined PG PCL PSL AD7–AD0 Next instruction RD (Note) Vector address (low-order) BLW BHW INTACK sequence [S]: Contents of stack pointer (S) FFXX16: Vector address fsys, φCPU: Internal clock (See Figure 4.3.1.) AD23–AD0: Internal address bus DB15–DB0: Internal data bus Note: These are internal signals and are not output to the external. Fig. 6.7.2 INTACK sequence timing (at minimum) 6.7.1 Change in IPL at acceptance of interrupt request When an interrupt request is accepted, the processor interrupt priority level (IPL) is replaced with the interrupt priority level of the accepted interrupt. This results in easy control of the processing for multiple interrupts. (Refer to section “ 6.9 Multiple interrupts.”) At acceptance of a watchdog timer interrupt request, a zero division request, or address matching detection interrupt request or at reset, a value in Table 6.7.1 is set into the IPL. Table 6.7.1 Change in IPL at acceptance of interrupt request Interrupts Reset Watchdog timer Zero division Address matching detection Other interrupts Level 0 ( “ 000 2” ) is set. Level 7 ( “ 111 2” ) is set. Not changed. Not changed. Accepted interrupt ’ s priority level is set. Change in IPL 6-14 7 905 Group User ’ s Manual Rev.1.0 INTERRUPTS 6.7 Sequence from acceptance of interrupt request until execution of interrupt routine 6.7.2 Push operation for registers The push operation for registers performed in the INTACK sequence depends on whether the contents of the stack pointer (S) at acceptance of an interrupt request are even or odd. When the contents of the stack pointer (S) are even, the contents of the program counter (PC) and the processor status register (PS) are simultaneously pushed in a unit of 16 bits. When the contents of the stack pointer (S) are odd, each of PC and PS is pushed in a unit of 8 bits. Figure 6.7.3 shows the push operation for registers. In the INTACK sequence, only the contents of the program bank register (PG), program counter (PC), and processor status register (PS) are pushed onto the stack area. Other necessary registers must be pushed by software at the start of the interrupt routine. By using the P SH i nstruction, all CPU registers, except the stack pointer (S), can be pushed with 1 instruction. (1) When contents of stack pointer (S) are even Address [S] – 5 (odd) [S] – 4 (even) [S] – 3 (odd) [S] – 2 (even) [S] – 1 (odd) [S] (even) Low-order byte of processor status register (PSL) Order for push ➂ Pushed in a unit of 16 bits. High-order byte of processor status register (PSH) Low-order byte of program counter (PCL) High-order byte of program counter (PCH) ➁ Pushed in a unit of 16 bits. ➀ Pushed in 3 times. Program bank register (PG) (2) When contents of stack pointer (S) are odd Address [S] – 5 (even) [S] – 4 (odd) [S] – 3 (even) [S] – 2 (odd) [S] – 1 (even) [S] (odd) Low-order byte of processor status register (PSL) High-order byte of processor status register (PSH) Order for push ➃ ➄ ➁ ➂ ➀ Pushed in 5 times. Pushed in a unit of 8 bits. Low-order byte of program counter (PCL) High-order byte of program counter (PCH) Program bank register (PG) ✽ [S] is the initial address that the stack pointer (S) indicates at acceptance of an interrupt request. The S’s contents become “[S] – 5” after all of the above registers are pushed. Fig. 6.7.3 Push operation for registers 7 905 Group User ’ s Manual Rev.1.0 6-15 INTERRUPTS 6.8 Return from interrupt routine, 6.9 Multiple interrupts 6.8 Return from interrupt routine When the RTI instruction is executed at the end of the interrupt routine, the contents of the program bank register (PG), program counter (PC), and processor status register (PS) which were pushed onto the stack area just before the INTACK sequence are automatically pulled. After this, the control returns to the original routine. And then, the suspended processing, which was in progress before acceptance of the interrupt request, is resumed. Before the RTI instruction is executed, registers which were pushed by software in the interrupt routine must be pulled in the same data length and register length as those in pushing, using the P UL i nstruction, etc. 6.9 Multiple interrupts Just after a branch is made to an interrupt routine, the following occur: • Interrupt disable flag (I) = “ 1 ” ( Interrupts are disabled.) • Interrupt request bit of accepted interrupt = “ 0 ” • Processor interrupt priority level (IPL) = Interrupt priority level of accepted interrupt Accordingly, as long as the IPL remains unchanged, an interrupt request, whose priority level is higher than that of the interrupt which is in progress, can be accepted by clearing the interrupt disable flag (I) to “0” in an interrupt routine. In this way, multiple interrupts are processed. Figure 6.9.1 shows the processing for multiple interrupts. An interrupt request which has not been accepted because its priority level is lower is retained. When the RTI i nstruction is executed, the interrupt priority level of the routine which was in progress just before acceptance of an interrupt request is pulled into the IPL. Therefore, if the following relationship is satisfied when interrupt priority level detection is performed next, the retained interrupt request will be accepted. Retained interrupt request ’ s priority level > Processor interrupt priority level (IPL) Note: When any of the following interrupt requests is generated while an interrupt routine is in progress, this interrupt request is accepted at once: zero division, watchdog timer, and address matching detection. 6-16 7 905 Group User ’ s Manual Rev.1.0 INTERRUPTS 6.9 Multiple interrupts Interrupt request generated Time Reset Main routine I=1 IPL = 0 Interrupt 1 I=0 Interrupt priority level = 3 Nesting Interrupt 1 I=1 IPL = 3 Interrupt 2 I=0 Interrupt priority level = 5 Multiple interrupts Interrupt 2 I=1 IPL = 5 Interrupt 3 RTI Interrupt priority level = 2 I=0 IPL = 3 Interrupt 3 RTI I=0 This request cannot be accepted because its priority level is lower than the interrupt 1’s one. IPL = 0 The instruction in the main routine is not executed. Interrupt 3 I=1 IPL = 2 RTI I=0 IPL = 0 I : Interrupt disable flag IPL : Processor interrupt priority level : They are automatically executed. : They must be set by software. Fig. 6.9.1 Processing for multiple interrupts 7 905 Group User ’ s Manual Rev.1.0 6-17 INTERRUPTS 6.10 External interrupts 6.10 External interrupts The external interrupts consist of INT i i nterrupts. 6.10.1 INTi i nterrupt An INTi (i = 0 to 7) interrupt request occurs by an input signal to pin INTi. Table 6.10.1 lists the occurrence factor of the INT i i nterrupt request. When using any of pins P5 1/INT 1, P5 2/INT2, P5 3/INT3, P55/INT5, P56/INT6, P57/INT7 a s an input pin of the external interrupt, be sure to clear the port P5 direction register ’ s bit. (See Figure 6.10.2.) When using pin P4OUTCUT/INT0 as an input pin of an external interrupt (pin INT0), be sure to use port pins P4 0 t o P47 i n the input mode. (Refer to section “ 5.2.3 Pin P4OUT CUT/INT0. ”) When using pin P6OUTCUT/INT4 as an input pin of an external interrupt (pin INT4), be sure to use port pins P6 0 t o P67 i n the input mode. (Refer to section “ 5.2.4 Pin P6OUT CUT/INT4. ”) The signal input to pin INT i r equires “ H ” o r “ L ” l evel width of 2 50 ns or more, independent of f(X IN). By reading out the INT i r ead bit (See Figure 6.10.1.), the state of pin INT i c an be read out. Note: S election of the interrupt occurrence factor requires the following conditions: • when an input signal’s falling edge or “L” level is selected, be sure that “L” level width ≥ 250 ns. • when an input signal’s rising edge or “H” level is selected, be sure that “H” level width ≥ 250 ns. Table 6.10.1 Occurrence factor of INT i i nterrupt request Occurrence factor of interrupt request Polarity select bit Level sense/Edge sense select bit (bit 5 at addresses 7D 16 t o 7F 16, (bit 4 at addresses 7D 16 t o (An interrupt request occurs when the 6E 16, 6F 16, FD16 t o FF 16) 7F16, 6E16, 6F16, FD16 to FF16) input signal of pin INT i i s as follows.) INT 0 t o INT 7 0 0 1 1 0 1 0 1 Falling edge (Edge sense) Rising edge (Edge sense) “ H ” l evel (Level sense) “ L ” l evel (Level sense) The INTi i nterrupt request occurs by detecting the state of pin INT i a ll the time. Therefore, when the user does not use an INT i i nterrupt, be sure to set the INT i i nterrupt ’ s priority level to 0. 6-18 7 905 Group User ’ s Manual Rev.1.0 INTERRUPTS 6.10 External interrupts b7 b6 b5 b4 b3 b2 b1 b0 External interrupt input read register (Address 9516) Bit 0 1 2 3 4 5 6 7 Bit name INT0 read out bit INT1 read out bit INT2 read out bit INT3 read out bit INT4 read out bit INT5 read out bit INT6 read out bit INT7 read out bit 0 : “L” level 1 : “H” level Function The input level at the corresponding pin is read out. At reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W RO RO RO RO RO RO RO RO Fig. 6.10.1 Structure of external interrupt input read register b7 b6 b5 b4 b3 b2 b1 b0 Port P5 direction register (Address D16) Bit 0 1 2 3 4 5 6 7 Corresponding pin Nothing is assigned. Pin INT1 Pin INT2 (RTPTRG1) Pin INT3 (RTPTRG0) Nothing is assigned. Pin INT5 (TB0IN/IDW) Pin INT6 (TB1IN/IDV) Pin INT7 (TB2IN/IDU) 0 : Input mode 1 : Output mode When using this pin as an external interrupt’s input pin, be sure to clear the corresponding bit to “0.” 0 : Input mode 1 : Output mode When using this pin as an external interrupt’s input pin, be sure to clear the corresponding bit to “0.” Function At reset Undefined 0 0 0 Undefined 0 0 0 R/W — RW RW RW — RW RW RW Note: ( ) shows the I/O pins of other internal peripheral devices which are multiplexed. Fig. 6.10.2 Relationship between port P5 direction register and external interrupt’ s input pins 7 905 Group User ’ s Manual Rev.1.0 6-19 INTERRUPTS 6.10 External interrupts 6.10.2 Functions of INT i i nterrupt request bit Figure 6.10.3 shows an INT i i nterrupt request. (1) Functions when edge sense is selected In this case, the interrupt request bit has the same function as that of an internal interrupt. That is, when an interrupt request occurs, the interrupt request bit is set to “1” and retains this state until the interrupt request is accepted. When this bit is cleared to “ 0 ” b y software, the interrupt request is cancelled; when this bit is set to “ 1 ” b y software, the interrupt request can occur. (2) Functions when level sense is selected In this case, the interrupt request bit is ignored. INTi interrupt requests continuously occur while the level at pin INTi is the valid level✽1; when the level at pin INTi changes from the valid level to the invalid level ✽2 before the corresponding INT i interrupt request is accepted, this interrupt request is not retained. (See Figure 6.10.4.) Valid level✽1: This means the level selected by the polarity select bit (bit 4 at addresses 7D16 to 7F16, 6E 16, 6F16, FD 16 t o FF16) Invalid level ✽2: This means the reversed level of “ valid level ” Data bus Level sense/Edge sense select bit Pin INTi Edge detection circuit Interrupt request bit 0 1 Interrupt request Fig. 6.10.3 INT i I nterrupt request Interrupt request is accepted. When the level at pin INTi changes to the invalid level before the INTi interrupt request is accepted, this interrupt request is not retained. Return to main routine. Valid Level at pin INTi Invalid Main routine First interrupt routine Second interrupt routine Third interrupt routine Main routine Fig. 6.10.4 Occurrence of INTi i nterrupt request when level sense is selected 6-20 7 905 Group User ’ s Manual Rev.1.0 INTERRUPTS 6.10 External interrupts 6.10.3 Switching of INTi t o interrupt request occurrence factor When the INT i i nterrupt request occurrence factor is switched in one of the following ways, there is a possibility that the corresponding interrupt request bit is set to “ 1 ” : • S witching the factor from the level sense to the edge sense • S witching the polarity Therefore, after this switching, make sure to clear the corresponding interrupt request bit to “ 0. ” F igure 6.10.5 shows an example of the switching procedure for the INT i i nterrupt request ’ s occurrence factor. (1) Switching the factor from the level sense to the edge sense (2) Switching the polarity Set the interrupt priority level to 0 or set the interrupt disable flag (I) to “1.” (INTi interrupt is disabled.) Set the interrupt priority level to 0 or set the interrupt disable flag (I) to “1.” (INTi interrupt is disabled.) Set the polarity select bit. Clear the level sense/Edge sense select bit to “0.” (Edge sense is selected.) Clear the interrupt request bit to “0.” Clear the interrupt request bit to “0.” Set the interrupt priority level to one of levels 1–7 or clear the interrupt disable flag (I) to “0.” (INTi interrupt request is acceptable.) Set the interrupt priority level to one of levels 1–7 or clear the interrupt disable flag (I) to “0.” (INTi interrupt request is acceptable.) Note: The above settings must be done separately. Multiple settings must not be done at the same time, in other words, they must not be done only by 1 instruction. Fig. 6.10.5 Example of switching procedure for INTi i nterrupt request ’ s occurrence factor 7 905 Group User ’ s Manual Rev.1.0 6-21 INTERRUPTS [Precautions for interrupts] [Precautions for interrupts] 1. In order to change the interrupt priority level select bits (bits 0 to 2 at addresses 6E16 to 7F16, F116, F2 16, F5 16 t o F9 16, FD 16 t o FF 16), 2 to 7 cycles of f sys a re required after execution of a write instruction until change of the interrupt priority level. Therefore, when the interrupt priority level of a certain interrupt source is repeatedly changed in a very short time, which consists of a few instructions, it is necessary to reserve the time required for the change by software. Figure 6.10.6 shows a program example to reserve the time required for the change. Note that the time required for the change depends on the contents of the interrupt priority detection time select bits (bits 4 and 5 at address 5E16). Table 6.10.2 lists the correspondence between the number of instructions inserted in Figure 6.10.6 and the interrupt priority detection time select bits. : MOVMB 00XXH, #0XH NOP NOP NOP MOVMB 00XXH, #0XH : ; Write instruction for the interrupt priority level select bits ; Inserted NOP instruction (Note) ; ; ; Write instruction for the interrupt priority level select bits Note: Except a write instruction for address XX16, any instruction which has the same cycles as the NOP instruction can also be inserted, instead of the NOP instruction. For the number of inserted NOP instructions, see Table 6.10.2. XX: any of 6E to 7F, F1, F2, F5 to F9, and FD to FF Fig. 6.10.6 Program example to reserve time required for change of interrupt priority level Table 6.10.2 Correspondence between number of instructions to be inserted in Figure 6.10.6 and interrupt priority detection time select bits Interrupt priority detection time select bits (Note) b4 b5 0 0 1 1 0 1 0 1 Interrupt priority level detection time 7 cycles of f sys 4 cycles of f sys 2 cycles of f sys Do not select. Number of inserted NOP instructions 7 or more 4 or more 2 or more Note: W e recommend [b5 = “ 1 ” , b4 = “ 0 ” ]. 2. When using pin P4OUTCUT/INT0 as an input pin of an external interrupt (pin INT0), be sure to use port pins P4 0 t o P4 7 i n the input mode. (Refer to section “ 5.2.3 Pin P4OUTCUT/INT 0. ” ) 3. When using pin P6OUTCUT/INT4 as an input pin of an external interrupt (pin INT4), be sure to use port pins P6 0 t o P6 7 i n the input mode. (Refer to section “ 5.2.4 Pin P6OUTCUT/INT 4. ” ) 6-22 7 905 Group User ’ s Manual Rev.1.0 CHAPTER 7 TIMER A 7.1 Overview 7.2 Block description 7.3 Timer mode [Precautions for timer mode] 7.4 Event counter mode [Precautions for event counter mode] 7.5 One-shot pulse mode [Precautions for one-shot pulse mode] 7.6 Pulse width modulation (PWM) mode [Precautions for pulse width modulation (PWM) mode] T IMER A 7.1 Overview 7.1 Overview Timer A consists of ten counters, Timers A0 to A9, each equipped with a 16-bit reload function. Timers A0 to A9 operate independently of one other. Timer Ai (i = 0 to 9) has four operating modes listed below. Except for the event counter mode, timer Ai has the same functions. Table 7.1.1 lists the functions of timer Ai. (1) Timer mode In this mode, the timer counts an internally generated count source. Following functions can be used in this mode: • Gate function • Pulse output function (2) Event counter mode In this mode, the timer counts an external signal. Following functions can be used in this mode: • Pulse output function • Two-phase pulse signal processing function (Timers A2 to A4, A7 to A9) (3) One-shot pulse mode In this mode, the timer outputs a pulse which has an arbitrary width once. (4) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses which have an arbitrary width in succession. In this mode, the timer serves as one of the following pulse width modulators: • 16-bit pulse width modulator • 8-bit pulse width modulator Table 7.1.1 Functions of timer Ai Functions of timers Timer mode Timer Gate function Pulse output function Event counter mode One-shot pulse mode Pulse width modulation (PWM) mode Note: Normal processing for TA2, TA3, TA7, TA8; and quadruple processing for TA4, TA9 Pulse output function Two-phase pulse signal processing function — (Note) — (Note) Timer Ai (i = 0 to 9) TA0 TA1 TA2 TA3 TA4 TA5 TA6 TA7 TA8 TA9 7-2 7905 Group User’s Manual Rev.1.0 T IMER A 7.2 Block description 7.2 Block description Figure 7.2.1 shows the block diagram of timer Ai (i = 0 to 9). Explanation of registers relevant to timer A is described below. Timer A clock division select bits (Note) f2 f1 f16 f64 f512 f4096 Count source select bit Data bus (odd) Data bus (even) (Low-order 8 bits) Timer mode One-shot pulse mode PWM mode (High-order 8 bits) Timer Ai reload register (16) Timer mode (Gate function) Polarity switching Event counter mode Count start bit Timer Ai counter (16) Timer Ai interrupt request bit TAiN Trigger Countdown Up-down bit Countup/Countdown switching (Always “countdown” except for in the event counter mode) Pulse output function select bit TAiOUT Toggle F.F. Note: Common to timers A0 to A9. Fig. 7.2.1 Block diagram of timer Ai (i = 0 to 9) 7905 Group User’s Manual Rev.1.0 7-3 T IMER A 7.2 Block description 7.2.1 Counter and Reload register (timer Ai register) Each of timer Ai counter and reload register consists of 16 bits. Countdown in the counter is performed each time the count source is input. In the event counter mode, it can also function as an up-counter. The reload register is used to store the initial value of the counter. When a counter underflow or overflow occurs, the reload register ’ s contents are reloaded into the counter. A value is set to the counter and reload register by writing the value to the timer Ai register. Table 7.2.1 lists the memory assignment of the timer Ai register. The value written into the timer Ai register while counting is not in progress is set to the counter and reload register. The value written into the timer Ai register while counting is in progress is set only to the reload register. In this case, the reload register ’ s updated contents are transferred to the counter at the next reload time. The value obtained when reading out the timer Ai register varies according to the operating mode. Table 7.2.2 lists reading from and writing to the timer Ai register. Table 7.2.1 Memory assignment of timer Ai register Timer Ai Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer A5 Timer A6 Timer A7 Timer A8 Timer A9 register register register register register register register register register register register High-order byte Address 4716 Address 4916 Address 4B16 Address 4D16 Address 4F16 Address C716 Address C916 Address CB16 Address CD16 Address CF16 Low-order byte Address 4616 Address 4816 Address 4A16 Address 4C16 Address 4E16 Address C616 Address C816 Address CA16 Address CC16 Address CE16 Note: A t reset, the contents of the timer Ai register are undefined. Table 7.2.2 Reading from and writing to timer Ai register Operating mode Timer mode Event counter mode One-shot pulse mode Pulse width modulation (PWM) mode (Note 1 ) Undefined value is read out. Read Counter value is read out. Write Written only to reload register. Written to both of the counter and reload register. Notes 1: Also refer to sections “ [Precautions for timer mode]” a nd “ [Precautions for event counter mode].” 2: When reading from and writing to the timer Ai register, perform it in a unit of 16 bits. 7-4 7905 Group User ’ s Manual Rev.1.0 T IMER A 7.2 Block description 7.2.2 Timer A clock division select register In the timer mode, one-shot pulse mode, and pulse width modulation (PWM) mode, the count source select bits (bits 6 and 7 at addresses 56 16 to 5A16, D616 to DA16), and timer A clock division select bits (bits 0 and 1 at address 45 16) select the count source. Figure 7.2.2 shows the structure of the timer A clock division select register. Table 7.2.3 lists the count source (in the timer mode, one-shot pulse mode, and pulse width modulation (PWM) mode). Timer A clock division select register (Address 4516) Bit 0 1 7 to 2 The value is “0” at reading. Bit name Timer A clock division select bits See Table 7.2.3. Function b7 b6 b5 b4 b3 b2 b1 b0 At reset 0 0 0 R/W RW RW – Fig. 7.2.2 Structure of timer A clock division select register Table 7.2.3 Count source (in timer mode, one-shot pulse mode, and pulse width modulation (PWM) mode) Count source select bits (bits 6 and 7 at addresses 5616 to 5A16, D616 to DA16) 00 01 10 11 Timer A clock division select bits (bits 0 and 1 at address 4516) 01 10 11 00 f1 f1 f2 f 16 f 16 f 64 Do not f 64 f 64 f 512 select. f 512 f4096 f4096 7905 Group User ’ s Manual Rev.1.0 7-5 T IMER A 7.2 Block description 7.2.3 Count start register This register is used to start and stop counting. One bit of this registar corresponds to one timer. (This is the one-to-one relationship.) Figure 7.2.3 shows the structures of the count start registers 0 and 1. Count start register 0 (Address 4016) Bit 0 1 2 3 4 5 6 7 Bit name Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit 0 : Stop counting 1 : Start counting Function b7 b6 b5 b4 b3 b2 b1 b0 At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Count start register 1 (Address 4116) Bit 0 1 2 3 4 7 to 5 Bit name Timer A5 count start bit Timer A6 count start bit Timer A7 count start bit Timer A8 count start bit Timer A9 count start bit Nothing is assigned. 0 : Stop counting 1 : Start counting Function At reset 0 0 0 0 0 Undefined R/W RW RW RW RW RW – Fig. 7.2.3 Structures of count start registers 0 and 1 7-6 7905 Group User ’ s Manual Rev.1.0 T IMER A 7.2 Block description 7.2.4 Timer Ai mode register Figure 7.2.4 shows the structure of the timer Ai mode register. The operating mode select bits are used to select the operating mode of timer Ai. Bits 2 to 7 have different functions according to the operating mode. These bits are described in the paragraph of each operating mode. Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) (i = 5 to 9) (Addresses D616 to DA16) Bit 0 1 2 3 4 5 6 7 Bit name Operating mode select bits b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 Function 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot pulse mode 1 1 : Pulse width modulation (PWM) mode At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW (Note) These bits have different functions according to the operating mode. Fig. 7.2.4 Structure of timer Ai mode register 7905 Group User ’ s Manual Rev.1.0 7-7 T IMER A 7.2 Block description 7.2.5 Timer Ai interrupt control register Figure 7.2.5 shows the structure of the timer Ai interrupt control register. For details about interrupts, refer to “ CHAPTER 6. INTERRUPTS.” Timer Ai interrupt control register (i = 0 to 4) (Addresses 7516 to 7916) (i = 5 to 9) (Addresses F516 to F916) Bit 0 1 2 3 7 to 4 Interrupt request bit Nothing is assigned. Bit name Interrupt priority level select bits b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 Function 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested At reset 0 0 0 0 Undefined R/W RW RW RW RW (Note) — Note: When writing to this bit, use the MOVM (MOVMB) instruction or STA (STAB, STAD) instruction. Fig. 7.2.5 Structure of timer Ai interrupt control register (1) Interrupt priority level select bits (bits 2 to 0) These bits are used to select a timer Ai interrupt ’ s priority level. When using timer Ai interrupts, select the priority level from levels 1 through 7. When a timer Ai interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL), so that the requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = “ 0. ” ) To disable timer Ai interrupts, set these bits to “ 000 2” ( level 0). (2) Interrupt request bit (bit 3) This bit is set to “1” when a timer Ai interrupt request occurs. This bit is automatically cleared to “0” when the timer Ai interrupt request is accepted. This bit can be set to “ 1 ” o r cleared to “ 0 ” b y software. 7-8 7905 Group User ’ s Manual Rev.1.0 T IMER A 7.2 Block description 7.2.6 Port P2, port P4 and port P6 direction registers The I/O pins of timers A0 to A3 are multiplexed with port P6 pins, and the I/O pins of timers A4 and A9 are multiplexed with port P2 pins, and the I/O pins of timers A5 to A8 are multiplexed with port P4 pins. When using these pins as timer Ai (i = 0 to 9)’s input pins, clear the corresponding bits of the port P6, port P2, and port P4 direction registers to “ 0 ” i n order to set these port pins for the input mode. When used as timer Ai’s output pins, these pins are forcibly set to the output pins of timer Ai regardless of the direction registers’ contents. Figure 7.2.6 shows the relationship between the port P6 direction register and the timer Ai’s I/O pins, Figure 7.2.7 shows the relationship between port P2 and port P4 direction registers and timer Ai ’ s I/O pins. Note that each bit of the port P4 direction register becomes “ 0 ” b y an input of a falling edge to pin P4OUT CUT. (Refer to section “5.2.3 Pin P4OUT CUT/INT0.”) When switching the output pins of timers A5 to A8 to the port output pins, the following procedure is required. ➀ R eturn the input level at pin P4OUT CUT t o “ H. ” y W rite data to the port P4 register ’ s bit corresponding to the port P4 pin, where data is to be output. ➂ Set “1” to the port P4 direction register’s bit corresponding to the above P4 register’s bit; therefore, this bit enters the output mode. When the input level at pin P4OUT CUT = “ L, ” n o bit of the port P4 direction register can be set to “ 1. ” Similarly, each bit of the port P6 direction register becomes “ 0 ” b y an input of a falling edge to pin P6OUT CUT. (Refer to section “5.2.4 Pin P6OUT CUT/INT4.”) When switching the output pins of timers A0 to A3 to the port output pins, the following procedure is required. ➀ R eturn the input level at pin P6OUT CUT t o “ H. ” y W rite data to the port P6 register ’ s bit corresponding to the port P6 pin, where data is to be output. ➂ Set “1” to the port P6 direction register’s bit corresponding to the above P6 register’s bit; therefore, this bit enters the output mode. When the input level at pin P6OUT CUT = “ L, ” n o bit of the port P6 direction register can be set to “ 1. ” b7 b6 b5 b4 b3 b2 b1 b0 Port P6 direction register (Address 1016) Bit 0 1 2 3 4 5 6 7 Corresponding pin Pin TA0OUT (Pin W/RTP00) Pin TA0IN (Pin V/RTP01) Pin TA1OUT (Pin U/RTP02) Pin TA1IN (Pin W/RTP03) Pin TA2OUT (Pin V/RTP10) Pin TA2IN (Pin U/RTP11) Pin TA3OUT (Pin RTP12) Pin TA3IN (Pin RTP13) When using this pin as timer Ai’s input pin, be sure to clear the corresponding bit to “0.” 0 : Input mode 1 : Output mode Functions At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Notes 1: Each of bits 0 to 7 becomes “0” by an input of the falling edge to pin P6OUTCUT/INT4. (Refer to section “5.2.4 Pin P6OUTCUT/ INT4.”) 2: The pins in ( ) are I/O pins of other internal peripheral devices, which are multiplexed. Fig. 7.2.6 Relationship between port P6 direction register and timer Ai’s I/O pins 7905 Group User ’ s Manual Rev.1.0 7-9 T IMER A 7.2 Block description b7 b6 b5 b4 b3 b2 b1 b0 Port P2 direction register (Address 816) Bit 0 1 2 3 4 5 6 7 Corresponding pin Pin TA4OUT Pin TA4IN Pin TA9OUT Pin TA9IN Pin TB0IN Pin TB1IN Pin TB2IN Pin P27 (Note 1) (Note 2) (Note 3) When using this pin as timer Ai’s input pin, be sure to clear the corresponding bit to “0.” 0 : Input mode 1 : Output mode Functions At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Notes 1: This applies when the TB0IN pin select bit (bit 0 at address AE16) = 1. 2: This applies when the TB1IN pin select bit (bit 1 at address AE16) = 1. 3: This applies when the TB2IN pin select bit (bit 2 at address AE16) = 1. b7 b6 b5 b4 b3 b2 b1 b0 Port P4 direction register (Address C16) Bit 0 1 2 3 4 5 6 7 Corresponding pin Pin TA5OUT (Pin RTP20) Pin TA5IN (Pin RTP21) Pin TA6OUT (Pin RTP22) Pin TA6IN (Pin RTP23) Pin TA7IN (Pin RTP30) Pin TA7IN (Pin RTP31) Pin TA8OUT (Pin RTP32) Pin TA8IN (Pin RTP33) When using this pin as timer Ai’s input pin, be sure to clear the corresponding bit to “0.” 0 : Input mode 1 : Output mode Functions At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Notes 1: Each of bits 0 to 7 becomes “0” by an input of the falling edge to pin P4OUTCUT/INT0. (Refer to section “5.2.3 Pin P4OUTCUT/ INT0.”) 2: The pins in ( ) are I/O pins of other internal peripheral devices, which are multiplexed. Fig. 7.2.7 Relationship between port P4 and port P2 direction registers and timer Ai’s I/O pins 7-10 7905 Group User ’ s Manual Rev.1.0 T IMER A 7.3 Timer mode 7.3 Timer mode In this mode, the timer counts an internally generated count source. Table 7.3.1 lists the specifications of the timer mode. Figure 7.3.1 shows the structures of the timer Ai register and timer Ai mode register in the timer mode. Table 7.3.1 Specifications of timer mode Item Count source f i Count operation f 1, f 2, f 16, f 64, f 512, or f 4096 • C ountdown • W hen a counter underflow occurs, reload register ’ s contents are reloaded, and counting continues. Division ratio Count start condition Count stop condition Interrupt request occurrence timing TAi IN p in function TAi OUT p in function Read from timer Ai register Write to timer Ai register 1 (n + 1) n : Timer Ai register setting value Specifications When count start bit is set to “ 1. ” When count start bit is cleared to “ 0. ” When a counter underflow occurs. Programmable I/O port pin or gate input pin Programmable I/O port pin or pulse output pin Counter value can be read out. q While counting is stopped When a value is written to the timer Ai register, it is written to both reload register and counter. q While counting is in progress When a value is written to the timer Ai register, it is written to only reload register. (Transferred to the counter at the next reload timing.) 7905 Group User ’ s Manual Rev.1.0 7-11 T IMER A 7.3 Timer mode Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Timer A5 register (Addresses C716, C616) Timer A6 register (Addresses C916, C816) Timer A7 register (Addresses CB16, CA16) Timer A8 register (Addresses CD16, CC16) Timer A9 register (Addresses CF16, CE16) (b15) b7 (b8) b0 b7 b0 Bit Function At reset R/W RW Undefined 15 to 0 Any value in the range from “000016” to “FFFF16” can be set. Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) Timer Ai mode register (i = 5 to 9) (Addresses D616 to DA16) Bit 0 1 2 Pulse output function select bit Bit name Operating mode select bits b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 0 At reset 0 0 00 R/W RW RW RW Function 0 0 : Timer mode 0 : No pulse output (TAiOUT pin functions as a programmable I/O port pin.) 1 : Pulse output (TAiOUT pin functions as a pulse output pin.) b4 b3 0 3 Gate function select bits 00: 01: 10: 4 11: No gate function (TAiIN pin functions as a programmable I/O port pin.) Gate function (Counter is active only while TAiIN pin’s input signal is at “L” level.) Gate function (Counter is active only while TAiIN pin’s input signal is at “H” level.) 0 RW 0 RW 5 6 7 Fix this bit to “0” in timer mode. Count source select bits See Table 7.2.3. 0 0 0 RW RW RW Fig. 7.3.1 Structures of timer Ai register and timer Ai mode register in timer mode 7-12 7905 Group User ’ s Manual Rev.1.0 T IMER A 7.3 Timer mode 7.3.1 Setting for timer mode Figure 7.3.2 shows an initial setting example for registers related to the timer mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to section “ CHAPTER 6. INTERRUPTS.” Selecting timer mode and each function b7 b0 0 00 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) (i = 5 to 9) (Addresses D616 to DA 16) Selection of timer mode Pulse output function select bit 0 : No pulse output 1 : Pulses output Gate function select bits b4 b3 0 0 1 1 0: No Gate function 1: 0 : Gate function (Counter counts only while TAi IN pin’s input signal level is “L.”) 1 : Gate function (Counter counts only while TAi IN pin’s input signal level is “H.”) Count source select bits See Table 7.2.3. Setting division ratio (b15) b7 (b8) b0 b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Timer A5 register (Addresses C716, C616) Timer A6 register (Addresses C916, C816) Timer A7 register (Addresses CB16, CA16) Timer A8 register (Addresses CD16, CC16) Timer A9 register (Addresses CF16, CE16) Can be set to “0000 16” to “FFFF 16” (n). Note: Counter divides the count source frequency by (n + 1). Setting interrupt priority level b7 b0 Timer Ai interrupt control register (i = 0 to 4) (Addresses 7516 to 7916) (i = 5 to 9) (Addresses F516 to F916) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Setting port P6, port P2, and port P4 direction registers b7 b0 Setting count start bit to “1.” b7 b0 Port P6 direction register (Address 1016) Pin TA0IN Pin TA1IN Pin TA2IN Pin TA3IN b7 b0 Count start register 0 (Address 4016) Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Port P2 direction register (Address 816) b7 b0 Pin TA4IN Pin TA9IN Count start register 1 (Address 4116) Timer A5 count start bit b7 b0 Timer A6 count start bit Port P4 direction register (Address C16) Pin TA5IN Pin TA6IN Pin TA7IN Pin TA8N Timer A7 count start bit Timer A8 count start bit Timer A9 count start bit When gate function is selected, clear the bit corresponding to the TAiIN pin to “0.” Count starts. Fig. 7.3.2 Initial setting example for registers relevant to timer mode 7905 Group User ’ s Manual Rev.1.0 7-13 T IMER A 7.3 Timer mode 7.3.2 Operation in timer mode ➀ W hen the count start bit is set to “ 1, ” t he counter starts counting of the count source. ➁ When a counter underflow occurs, the reload register’s contents are reloaded, and counting continues. ➂ T he timer Ai interrupt request bit is set to “ 1 ” a t the underflow in ➁ . The interrupt request bit remains set to “ 1 ” u ntil the interrupt request is accepted or until the interrupt request bit is cleared to “ 0 ” b y software. Figure 7.3.3 shows an example of operation in the timer mode. FFFF16 Counter contents (Hex.) Starts counting. (1 / fi) ✕ (n+1) Stops counting. n Restarts counting. 000016 Time Set to “1” by software. Cleared to “0” by software. Set to “1” by software. Count start bit Timer Ai interrupt request bit Cleared to “0” when interrupt request is accepted or cleared by software. fi : Frequency of count source n : Reload register’s contents Fig. 7.3.3 Example of operation in timer mode (without pulse output and gate functions) 7-14 7905 Group User ’ s Manual Rev.1.0 T IMER A 7.3 Timer mode 7.3.3 Select function The following describes the gate and pulse output functions. (1) Gate function The gate function is selected by setting the gate function select bits (bits 4 and 3 at addresses 5616 to 5A16, D616 to DA16) to “102” or “112.” The gate function makes it possible to start or stop counting depending on the TAi IN p in ’ s input signal. Table 7.3.2 lists the count valid levels. Figure 7.3.4 shows an example of operation with the gate function selected. When selecting the gate function, set the port P6, P2, and P4 direction registers’ bits which correspond to the TAi IN p ins for the input mode. Additionally, make sure that the TAi IN p in ’ s input signal has a pulse width equal to or more than two cycles of the count source. Table 7.3.2 Count valid levels Gate function select bits b4 1 1 b3 0 1 Count valid level (Duration while counter counts) While TAi IN p in ’ s input signal level is at “ L ” l evel While TAi IN p in ’ s input signal level is at “ H ” l evel Note: The counter does not count while the TAi IN p in ’ s input signal is not at the count valid level. FFFF16 n Counter contents (Hex.) ➀ Starts counting. ➁ Stops counting. 000016 Set to “1” by software. Count start bit Count valid TAiIN pin’s level input signal Invalid level Timer Ai interrupt request bit ➀ The counter counts while the count start bit = “1” and the TAiIN pin’s input signal is at the count valid level. ➁ The counter stops counting while the TAiIN pin’s input signal is not at the count valid level, and the counter value is retained. n : Reload register’s contents Time Cleared to “0” when interrupt request is accepted or cleared by software. Fig. 7.3.4 Example of operation with gate function selected 7905 Group User ’ s Manual Rev.1.0 7-15 T IMER A 7.3 Timer mode (2) Pulse output function The pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses 5616 to 5A 16, D616 to DA16) to “1.” When this function is selected, the TAi OUT pin is forcibly set for the pulse output pin regardless of the corresponding bits of the port P6, P2, and P4 direction registers. The TAi OUT p in outputs a pulse of which polarity is inverted each time a counter underflow occurs. When the count start bit (addresses 4016, 4116) is “0” (count stopped), the TAiOUT pin outputs “L” level. Figure 7.3.5 shows an example of operation with the pulse output function selected. FFFF16 Starts counting. Counter contents (Hex.) Starts counting. n Restarts counting. 000016 Time Set to “1” by software. Count start bit Cleared to “0” by software. Set to “1” by software. Pulse output from TAiOUT pin Timer Ai interrupt request bit Cleared to “0” when interrupt request is accepted or cleared by software. n : Reload register’s contents Fig. 7.3.5 Example of operation with pulse output function selected 7-16 7905 Group User ’ s Manual Rev.1.0 T IMER A [Precautions for timer mode] [Precautions for timer mode] 1. By reading the timer Ai register, the counter value can be read out at arbitrary timing. However, if the timer Ai register is read at the reload timing shown in Figure 7.3.6, the value “ FFFF16” i s read out. If reading is performed in the period from when a value is set into the timer Ai register with the counter stopped until the counter starts counting, the set value is correctly read out. Reload Counter value (Hex.) 2 1 0 n n–1 Read value (Hex.) 2 1 0 FFFF n – 1 Time n : Reload register’s contents Fig. 7.3.6 Reading timer Ai register 7905 Group User ’ s Manual Rev.1.0 7-17 T IMER A 7.4 Event counter mode 7.4 Event counter mode In this mode, the timer counts an external signal. Tables 7.4.1 and 7.4.2 list the specifications of the event counter mode. Figure 7.4.1 shows the structures of the timer Ai register and timer Ai mode register in the event counter mode. Table 7.4.1 Specifications of event counter mode (when not using two-phase pulse signal processing function) Item Count source Specifications q External signal input to the TAi IN p in q The count source’s valid edge can be selected from the falling edge and the rising edge by software. Count operation q Countup or countdown can be switched by external signal or software. q When a counter overflow or underflow occurs, reload register’s contents are reloaded, and counting continues. Division ratio q F or countdown q F or countup 1 (n + 1) 1 (FFFF 16 – n + 1 ) Count start condition Count stop condition Interrupt request occurrence timing TAi IN p in’s function TAi OUT p in’s function Read from timer Ai register Write to timer Ai register When the count start bit is set to “1.” When the count start bit is cleared to “0.” When a counter overflow or underflow occurs. Count source input Programmable I/O port pin, pulse output pin, or countup/countdown switch signal input pin Counter value can be read out. q While counting is stopped When a value is written to timer Ai register, it is written to both of the reload register and counter. q While counting is in progress When a value is written to timer Ai register, it is written only to the reload register. (Transferred to the counter at the next reload timing.) n: Timer Ai register’s set value 7-18 7905 Group User’s Manual Rev.1.0 T IMER A 7.4 Event counter mode Table 7.4.2 Specifications of event counter mode (when using two-phase pulse signal processing function in timers A2 to A4, A7 to A9) Item Count source Count operation Specifications External signal (two-phase pulse) input to the following pins: TAj IN, TAj OUT ( j = 2 to 4, 7 to 9) q C ountup or countdown can be switched by external signal (twophase pulse). q When a counter overflow or underflow occurs, reload register’s conDivision ratio tents are reloaded, and counting continues. 1 q F or countdown (n + 1) n: Timer Aj register’s set value q F or countup 1 (FFFF 16 – n + 1 ) Count start condition Count stop condition Interrupt request occurrence timing Function of the following pins: TAj IN, TAj OUT ( j = 2 to 4, 7 to 9) Read from timer Aj register Write to timer Aj register Counter value can be read out by reading timer Aj register. q W hile counting is stopped When a value is written to timer Aj register, it is written to both of the reload register and counter. q While counting is in progress When a value is written to timer Aj register, it is written only to the reload register. (Transferred to the counter at the next reload timing.) When the count start bit is set to “1.” When the count start bit is cleared to “0.” When a counter overflow or underflow occurs. Two-phase pulse input 7905 Group User’s Manual Rev.1.0 7-19 T IMER A 7.4 Event counter mode Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Timer A5 register (Addresses C716, C616) Timer A6 register (Addresses C916, C816) Timer A7 register (Addresses CB16, CA16) Timer A8 register (Addresses CD16, CC16) Timer A9 register (Addresses CF16, CE16) (b15) b7 (b8) b0 b7 b0 Bit Function At reset R/W RW 15 to 0 Any value in the range from “000016” to “FFFF16” can be set. Undefined Assuming that the set value = n, the counter divides the count source frequency by (n + 1) during countdown, or by (FFFF16 – n + 1) during countup. When reading, the register indicates the counter value. Note: Reading from or writing to this register must be performed in a unit of 16 bits. Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) Timer Ai mode register (i = 5 to 9) (Addresses D616 to DA16) Bit 0 1 2 Pulse output function select bit Bit name Operating mode select bits b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 XX0 At reset 0 0 01 R/W RW RW RW Function 0 1 : Event counter mode 0 : No pulse output (TAi OUT p in functions as a programmable I/O port pin.) 1 : Pulse output (TAiOUT pin functions as a pulse output pin.) 0 : Counts at falling edge of external signal 1 : Counts at rising edge of external signal 0 : Contents of up-down register 1 : Input signal to TAiOUT pin 0 3 4 5 6 7 Count polarity select bit Up-down switching factor select bit 0 0 0 0 0 RW RW RW RW RW Fix this bit to “0” in event counter mode. These bits are invalid in event counter mode. X : It may be either “0” or “1.” Fig. 7.4.1 Structures of timer Ai register and timer Ai mode register in event counter mode 7-20 7905 Group User’s Manual Rev.1.0 T IMER A 7.4 Event counter mode 7.4.1 Setting for event counter mode Figures 7.4.2 and 7.4.3 show an initial setting example for registers related to the event counter mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to “ CHAPTER 6. INTERRUPTS.” Selecting event counter mode and each function b7 b0 ✕✕ 0 01 Timer Ai mode register (i = 0 to 9) (Addresses 5616 to 5A16, D616 to DA16) Selection of event counter mode Pulse output function select bit 0: No pulse output 1: Pulse output Count polarity select bit 0: Counts at falling edge of external signal. 1: Counts at rising edge of external signal. Up-down switching factor select bit 0: Contents of up-down register 1: Input signal to TAiOUT pin X: It may be either “0” or “1.” Setting up–down register b7 b0 Up–down register 0 (Address 4416) Timer A0 up–down bit Timer A1 up–down bit Timer A2 up–down bit Timer A3 up–down bit Timer A4 up–down bit Timer A2 two–phase pulse signal processing select bit Timer A3 two–phase pulse signal processing select bit Timer A4 two–phase pulse signal processing select bit b7 b0 Set to the corresponding up–down bit when the contents of the up-down register are selected as the up-down switching factor. 0: Countdown 1: Countup Set the corresponding bit to “1” when the two–phase pulse signal processing function is selected for timers A2 to A4. 0: Two–phase pulse signal processing function disabled 1: Two–phase pulse signal processing function enabled Up–down register 1 (Address C416) Timer A5 up–down bit Timer A6 up–down bit Timer A7 up–down bit Timer A8 up–down bit Timer A9 up–down bit Timer A7 two–phase pulse signal processing select bit Timer A8 two–phase pulse signal processing select bit Timer A9 two–phase pulse signal processing select bit Set to the corresponding up–down bit when the contents of the up-down register are selected as the up-down switching factor. 0: Countdown 1: Countup Set the corresponding bit to “1” when the two–phase pulse signal processing function is selected for timers A7 to A9. 0: Two–phase pulse signal processing function disabled 1: Two–phase pulse signal processing function enabled Setting divide ratio (b15) b7 (b8) b0 b7 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Timer A5 register (Addresses C716, C616) Timer A6 register (Addresses C916, C816) Timer A7 register (Addresses CB16, CA16) Can be set to“000016” to ”FFFF16” (n). Timer A8 register (Addresses CD16, CC16) Timer A9 register (Addresses CF16, CE16) b0 ✻ The counter divides the count source frequency by (n + 1) when counting down, or by (FFFF 16 – n + 1) when counting up. Continued to Figure 7.4.3 on the next page Fig. 7.4.2 Initial setting example for registers related to event counter mode (1) 7905 Group User’s Manual Rev.1.0 7-21 T IMER A 7.4 Event counter mode Continued from preceding Figure 7.4.2 Setting interrupt priority level b7 b0 Timer Ai interrupt control register (j = 0 to 9) (Addresses 7516 to 7916, F516 to F916) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Setting port P6, port P2, and port P4 direction registers b7 b0 Port P6 direction register (Address 1016) Pin TA0 OUT Pin TA0 IN Pin TA1 OUT Pin TA1 IN Pin TA2 OUT Pin TA2 IN Pin TA3 OUT Pin TA3 IN b7 b0 Port P2 direction register (Address 816) Pin TA4 OUT Pin TA4 IN Pin TA9 OUT Pin TA9 IN b7 b0 Port P4 direction register (Address C16) Pin TA5 OUT Pin TA5 IN Pin TA6 OUT Pin TA6 IN Pin TA7 OUT Pin TA7 IN Pin TA8 OUT Pin TA8 IN Clear the bit corresponding to the TAi IN pin to “0.” When selecting the TAi OUT pin’s input signal as up-down switching factor, clear the bit corresponding to the TAi OUT pin to “0.” When selecting the two–phase pulse signal processing function, clear the bit corresponding to the TAj OUT (j = 2 to 4, 7 to 9) pin to “0.” Setting the count start bit to “1” b7 b0 Count start register 0 (Address 4016) Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit b7 b0 Count start register 1 (Address 4116) Timer A5 count start bit Timer A6 count start bit Timer A7 count start bit Timer A8 count start bit Timer A9 count start bit Count starts. Fig. 7.4.3 Initial setting example for registers relevant to event counter mode (2) 7-22 7905 Group User ’ s Manual Rev.1.0 T IMER A 7.4 Event counter mode 7.4.2 Operation in event counter mode ➀ W hen the count start bit is set to “ 1, ” t he counter starts counting of the count source ’ s valid edge. ➁ When a counter underflow or overflow occurs, the reload register’s contents are reloaded, and counting continues. ➂ T he timer Ai interrupt request bit is set to “ 1 ” a t the underflow or overflow in ➁. The interrupt request bit remains set to “ 1 ” u ntil the interrupt request is accepted or until the interrupt request bit is cleared to “ 0 ” b y software. Figure 7.4.4 shows an example of operation in the event counter mode. FFFF16 Starts counting. Counter contents (Hex.) n 000016 Time Set to “1” by software. Count start bit Set to “1” by software. Up-down bit Timer Ai interrupt request bit Cleared to “0” when interrupt request is accepted or cleared by software. n : Reload register’s contents Note: The above applies when the up-down bit’s contents are selected as the up-down switching factor (i.e., up-down switching factor select bit = “0” ). Fig. 7.4.4 Example of operation in event counter mode (without pulse output and two-phase pulse signal processing functions) 7905 Group User ’ s Manual Rev.1.0 7-23 T IMER A 7.4 Event counter mode 7.4.3 Switching between countup and countdown Figure 7.4.5 shows structures of the up-down registers 0 and 1. The up-down register or the input signal from the TAi OUT p in is used to switch countup from and to countdown. This switching is performed by the up-down bit when the up-down switching factor select bit (bit 4 at addresses 56 16 to 5A 16, D616 to DA16) is “0,” and by the input signal from the TAiOUT pin when the up-down switching factor select bit is “ 1. ” When the switching between countup and countdown is set while counting is in progress, this switching is actually performed when the count source ’ s next valid edge is input. (1) Switching by up-down bit Countdown is performed when the up-down bit is “0,” and countup is performed when the up-down bit is “ 1. ” F igure 7.4.5 shows the structures of the up-down registers 0 and 1. (2) Switching by TAiOUT p in ’ s input signal Countdown is performed when the TAiOUT pin’s input signal is at “L” level, and countup is performed when the TAi OUT p in ’ s input signal is at “ H ” l evel. When using the TAi OUT pin’s input signal to switch countup from and to countdown, set the port P6, port P2, and port P4 direction registers ’ bits which correspond to the TAi OUT pin for the input mode. 7-24 7905 Group User ’ s Manual Rev.1.0 T IMER A 7.4 Event counter mode b7 b6 b5 b4 b3 b2 b1 b0 Up-down register 0 (Address 4416) Bit 0 1 2 3 4 5 6 7 Bit name Timer A0 up-down bit Timer A1 up-down bit Timer A2 up-down bit Timer A3 up-down bit Timer A4 up-down bit Timer A2 two-phase pulse signal 0 : Two-phase pulse signal processing function disabled 1 : Two-phase pulse signal processing function enabled processing select bit Timer A3 two-phase pulse signal When not using the two-phase pulse signal processing processing select bit function, clear the bit to “0.” Timer A4 two-phase pulse signal The value is “0” at reading. processing select bit 0 : Countdown 1 : Countup This function is valid when the contents of the updown register is selected as the up-down switching factor. Function At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW WO (Note) WO (Note) WO (Note) Note: Use the MOVM (MOVMB) or STA(STAB, STAD) instruction for writing to bits 5 to 7. b7 b6 b5 b4 b3 b2 b1 b0 Up-down register 1 (Address C416) Bit 0 1 2 3 4 5 6 7 Bit name Timer A5 up-down bit Timer A6 up-down bit Timer A7 up-down bit Timer A8 up-down bit Timer A9 up-down bit Timer A7 two-phase pulse signal 0 : Two-phase pulse signal processing function disabled 1 : Two-phase pulse signal processing function enabled processing select bit Timer A8 two-phase pulse signal When not using the two-phase pulse signal processing processing select bit function, clear the bit to “0.” Timer A9 two-phase pulse signal The value is “0” at reading. processing select bit 0 : Countdown 1 : Countup This function is valid when the contents of the updown register is selected as the up-down switching factor. Function At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW WO (Note) WO (Note) WO (Note) Note: Use the MOVM (MOVMB) or STA(STAB, STAD) instruction for writing to bits 5 to 7. Fig. 7.4.5 Structures of up-down registers 0 and 1 7905 Group User ’ s Manual Rev.1.0 7-25 T IMER A 7.4 Event counter mode 7.4.4 Selectable functions The following describes the selectable pulse output, and two-phase pulse signal processing functions. (1) Pulse output function The pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses 5616 to 5A16, D616 to DA16) to “1.” When this function is selected, the TAiOUT pin is forcibly set for the pulse output pin regardless of the corresponding bits of the port P6, port P2, and port P4 direction registers. The TAi OUT pin outputs a pulse of which polarity is inverted each time a counter underflow or overflow occurs. (Refer to Figure 7.3.5). When the count start bit (addresses 4016, 4116) is “0” (count stopped), the TAiOUT pin outputs “L” level. (2) Two-phase pulse signal processing function (Timers Aj) For timer Aj (j = 2 to 4, 7 to 9), the two-phase pulse signal processing function is selected by setting the timer Aj two-phase pulse signal processing select bits (bits 5 to 7 at addresses 44 16 a nd C416) to “1.” (See Figure 7.4.5.) Figure 7.4.6 shows the timer Aj mode register when the two-phase pulse signal processing function is selected. For timers with two-phase pulse signal processing function selected, the timer counts two kinds of pulses of which phases differ by 90 degrees. There are two types of the two-phase pulse signal processing: normal processing and quadruple processing. In timer Am (m = 2, 3, 7, 8), normal processing is performed; in timer An (n = 4, 9), quadruple processing is performed. For the port P6, port P2, and P4 direction registers’ bits corresponding to the pins used for two-phase pulse input, be sure to set these bits for the input mode. b7 b6 b5 b4 b3 b2 b1 b0 ✕✕010001 X : It may be either “0” or “1.” Timer A2 mode register (Address 5816) Timer A3 mode register (Address 5916) Timer A4 mode register (Address 5A16) Timer A7 mode register (Address D816) Timer A8 mode register (Address D916) Timer A9 mode register (Address 5D16) Fig. 7.4.6 Timer Aj (j = 2 to 4, 7 to 9) mode register when two-phase pulse signal processing function is selected 7-26 7905 Group User ’ s Manual Rev.1.0 T IMER A 7.4 Event counter mode Countup is performed at the rising edges input to the TAmIN pin when the TAmIN (m = 2, 3, 7, 8) and TAmOUT have the relationship that the TAm IN p in ’ s input signal goes from “L” to “H” while the TAm OUT pin’s input signal is at “ H ” l evel. Countdown is performed at the falling edges input to the TAm IN pin when the TAm IN and TAmOUT have the relationship that the TAmIN pin’s input signal goes from “H” to “L” while the TAm OUT p in ’ s input signal is “ H. ” ( See Figure 7.4.7.) Countup is performed at all rising and falling edges input to the TAnOUT (n = 4, 9) and TAnIN pins when the TAnIN and TAnOUT have the relationship that the TAn IN p in ’ s input signal level goes from “ L ” t o “ H ” w hile the TAn OUT p in ’ s input signal is at “ H ” l evel. Countdown is performed at all rising and falling edges input to the TAnOUT and TAn IN pins when the TAn IN a nd TAn OUT h ave the relationship that the TAnIN pin’s input signal level goes from “H” to “L” while the TAn OUT pin’s input signal is at “H” level. (See Figure 7.4.8.) Table 7.4.3 lists the input signals on the TAnOUT and TAn IN pins when the quadruple processing is selected. “H” TAmOUT “L” “H” TAmIN (m = 2, 3, 7, 8) “L” Countup Countup Countup Countdown Countdown Countdown +1 +1 +1 –1 –1 –1 Fig. 7.4.7 Normal processing “H” TAnOUT “L” Counted up at all edges. +1 +1 +1 +1 +1 Counted down at all edges. –1 –1 –1 –1 –1 TAnIN “L” (n = 4, 9) “H” Counted up at all edges. +1 +1 +1 +1 +1 Counted down at all edges. –1 –1 –1 –1 –1 Fig. 7.4.8 Quadruple processing Table 7.4.3 TAn OUT a nd TAn IN p in ’ s input signals when quadruple processing is selected (n = 4, 9) Input signal to TAn OUT p in Countup “ H ” l evel “ L ” l evel Rising edge Falling edge “ H ” l evel “ L ” l evel Rising edge Falling edge Input signal to TAn IN p in Rising edge Falling edge “ L ” l evel “ H ” l evel Falling edge Rising edge “ H ” l evel “ L ” l evel Countdown 7905 Group User ’ s Manual Rev.1.0 7-27 T IMER A [Precautions for event counter mode] [Precautions for event counter mode] 1. While counting is in progress, by reading the timer Ai (i = 0 to 9) register, the counter value can be read out at any timing. However, if the timer Ai register is read at the reload timing shown in Figure 7.4.9, the value “FFFF16” (at an underflow) or “000016” (at the overflow) is read out. If reading is performed in the period from when a value is set into the timer Ai register with the counter stopped until the counter starts counting, the set value is correctly read out. (1) For countdown Reload (2) For countup Reload Counter value (Hex.) 2 1 0 n n–1 Counter value (Hex.) Read value (Hex.) FFFD FFFE FFFF n n+1 Read value (Hex.) 2 1 0 FFFF n – 1 Time FFFD FFFE FFFF 0000 n + 1 Time n : reload register’s contents n : reload register’s contents Fig. 7.4.9 Reading timer Ai register 2. The TAi OUT p in is used for all functions listed below. Accordingly, only one of these functions can be selected for each timer. q S witching between countup and countdown by TAi OUT p in ’ s input signal q P ulse output function q T wo-phase pulse signal processing function (Timers A2 to A4, A7 to A9) 7-28 7905 Group User ’ s Manual Rev.1.0 T IMER A 7.5 One-shot pulse mode 7.5 One-shot pulse mode In this mode, the timer outputs a pulse which has an arbitrary width once. When a trigger occurs, the timer outputs “H” level from the TAiOUT pin for an arbitrary time. Table 7.5.1 lists the specifications of the one-shot pulse mode. Figure 7.5.1 shows the structures of the timer Ai register and timer Ai mode register in the one-shot pulse mode. Table 7.5.1 Specifications of one-shot pulse mode Item Count source fi Count operation f 1, f 2, f 16, f 64, f 512, or f 4096 q Countdown q When the counter value becomes “0000 16,” reload register’s contents are reloaded, and counting stops. q If a trigger occurs during counting, reload register’s contents are reloaded, and counting continues. Output pulse width (“H”) Count start condition Count stop condition Interrupt request occurrence timing TAi IN p in’s function TAi OUT p in’s function Read from timer Ai register Write to timer Ai register [s] n : Timer Ai register’s set value fi q When a trigger occurs. ( Note) q Internal or external trigger can be selected by software. q When the counter value becomes “0000 16” q When the count start bit is cleared to “0” When counting stops. Programmable I/O port pin or trigger input pin One-shot pulse output An undefined value is read out. q While counting is stopped When a value is written to timer Ai register, it is written to both of the reload register and counter. q While counting is in progress When a value is written to timer Ai register, it is written only to the reload register. (Transferred to counter at the next reload timing.) Note: The trigger is generated with the count start bit = “1.” n Specifications 7905 Group User’s Manual Rev.1.0 7-29 T IMER A 7.5 One-shot pulse mode Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Timer A5 register (Addresses C716, C616) Timer A6 register (Addresses C916, C816) Timer A7 register (Addresses CB16, CA16) Timer A8 register (Addresses CD16, CC16) Timer A9 register (Addresses CF16, CE16) (b15) b7 (b8) b0 b7 b0 Bit Function At reset R/W WO Undefined 15 to 0 Any value in the range from “000016” to “FFFF16” can be set. Assuming that the set value = n, the “H” level width of the one-shot pulse which is n output from the TAiOUT pin is expressed as follows : fi. fi: Frequency of count source Note: Use the MOVM or STA(STAD) instruction for writing to this register. Writing to this register must be performed in a unit of 16 bits. Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) Timer Ai mode register (i = 5 to 9) (Addresses D616 to DA16) Bit 0 1 2 3 4 5 6 7 Fix this bit to “1” in one-shot pulse mode. Trigger select bits b4 b3 b7 b6 b5 b4 b3 b2 b1 b0 0 110 At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Bit name Operating mode select bits b1 b0 Function 1 0 : One-shot pulse mode Writing “1” to one-shot start bit (TAiIN pin functions as a programmable I/O port pin.) 1 0 : Falling edge of TAiN pin’s input signal 1 1 : Rising edge of TAiIN pin’s input signal See Table 7.2.3. 00: 01: Fix this bit to “0” in one-shot pulse mode. Count source select bits Fig. 7.5.1 Structures of timer Ai register and timer Ai mode register in one-shot pulse mode 7-30 7905 Group User’s Manual Rev.1.0 T IMER A 7.5 One-shot pulse mode 7.5.1 Setting for one-shot pulse mode Figures 7.5.2 and 7.5.3 show an initial setting example for registers related to the one-shot pulse mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to “ CHAPTER 6. INTERRUPTS.” Selecting one-shot pulse mode and each function b7 b0 0 110 Timer Ai mode register (i = 0 to 9) (Addresses 5616 to 5A16, D616 to DA16) Selection of one-shot pulse mode Trigger select bits b4 b3 00: 0 1 : Writing “1” to one-shot start bit: Internal trigger 1 0 : Falling of TAi IN pin’s input signal: External trigger 1 1 : Rising of TAi IN pin’s input signal: External trigger Count source select bits See Table 7.2.3. Setting “H” level width of one-shot pulse (b15) b7 (b8) b0 b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Timer A5 register (Addresses C716, C616) Timer A6 register (Addresses C916, C816) Timer A7 register (Addresses CB16, CA16) Timer A8 register (Addresses CD16, CC16) Timer A9 register (Addresses CF16, CE16) Can be set to “0000 16” to “FFFF 16” (n). Note. “H” level width = n fi fi = Frequency of count source However, if n = “0000 16”, the counter does not operate and the TAi OUT pin outputs “L” level. At this time, no timer Ai interrupt request occurs. Setting interrupt priority level b7 b0 Timer Ai interrupt control register (i = 0 to 9) (Addresses 7516 to 7916, F516 to F916) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Continued to Figure 7.5.3 on the next page Fig. 7.5.2 Initial setting example for registers related to one-shot pulse mode (1) 7905 Group User’s Manual Rev.1.0 7-31 T IMER A 7.5 One-shot pulse mode Continued from preceding Figure 7.5.2 When external trigger is selected Setting port P6, port P2, and port P4 direction registers b7 b0 When internal trigger is selected Setting count start bit to “1” b7 b0 Port P6 direction register (Address 1016) Pin TA0IN Pin TA1IN Pin TA2IN Pin TA3IN b7 b0 Count start register 0 (Address 4016) Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Port P2 direction register (Address 816) Pin TA4 Pin TA9 b7 b0 Count start register 1 (Address 4116) Timer A5 count start bit Timer A6 count start bit Timer A7 count start bit Timer A8 count start bit Timer A9 count start bit b7 b0 Port P4 direction register (Address C16) Pin TA5IN Pin TA6IN Pin TA7IN Pin TA8IN Clear the corresponding bit to “0.” Setting one-shot start bit to “1” b7 b0 0 Setting count start bit to “1” b7 b0 One-shot start register 0 (Address 4216) Timer A0 one-shot start bit Timer A1 one-shot start bit Timer A2 one-shot start bit Timer A3 one-shot start bit Timer A4 one-shot start bit Count start register 0 (Address 4016) Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit b7 b0 0 One-shot start register 1 (Address 4316) Timer A5 one-shot start bit Timer A6 one-shot start bit Timer A7 one-shot start bit Timer A8 one-shot start bit Timer A9 one-shot start bit b7 b0 Count start register 1 (Address 4116) Timer A5 count start bit Timer A6 count start bit Timer A7 count start bit Timer A8 count start bit Timer A9 count start bit Trigger input to TAi IN pin Trigger generated Count starts. Fig. 7.5.3 Initial setting example for registers related to one-shot pulse mode (2) 7-32 7905 Group User ’ s Manual Rev.1.0 T IMER A 7.5 One-shot pulse mode 7.5.2 Trigger The counter is enabled for counting when the count start bit (addresses 4016, 4116) has been set to “1.” The counter starts counting when a trigger is generated after counting has been enabled. An internal or external trigger can be selected as that trigger. An internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 56 16 to 5A 16, D616 to DA 16) are “ 00 2” o r “ 01 2” ; an external trigger is selected when the bits are “ 10 2” o r “ 11 2. ” If a trigger is generated during counting, the reload register ’ s contents are reloaded and the counter continues counting. If a trigger generated during counting, make sure that a certain time which is equivalent to one cycle of the timer’s count source or more has passed between the previously trigger occurrence and a new trigger occurrence. (1) When selecting internal trigger A trigger is generated when writing “1” to the one-shot start bit (addresses 4216, 4316). Figure 7.5.4 shows the structures of the one-shot start registers 0 and 1. (2) When selecting external trigger A trigger is generated at the falling edge of the TAiIN pin’s input signal when bit 3 at addresses 56 16 to 5A 16, D6 16 t o DA 16 i s “ 0, ” o r at its rising edge when bit 3 is “ 1. ” When using an external trigger, set the port P6, port P2, and port P4 direction registers ’ bits which correspond to the TAi IN p ins for the input mode. 7905 Group User ’ s Manual Rev.1.0 7-33 T IMER A 7.5 One-shot pulse mode b7 b6 b5 b4 b3 b2 b1 b0 One-shot start register 0 (Address 4216) Bit 0 1 2 3 4 6, 5 7 Bit name Timer A0 one-shot start bit Timer A1 one-shot start bit Timer A2 one-shot start bit Timer A3 one-shot start bit Timer A4 one-shot start bit Nothing is assigned. Fix this bit to “0.” Function 0 At reset 0 0 The value is “0” at reading. 0 0 0 Undefined 0 R/W WO WO WO WO WO – RW 1 : Start outputting one-shot pulse. (Valid when an internal trigger is selected.) b7 b6 b5 b4 b3 b2 b1 b0 One-shot start register 1 (Address 4316) Bit 0 1 2 3 4 6, 5 7 Bit name Timer A5 one-shot start bit Timer A6 one-shot start bit Timer A7 one-shot start bit Timer A8 one-shot start bit Timer A9 one-shot start bit Nothing is assigned. Fix this bit to “0.” Function 0 At reset 0 0 The value is “0” at reading. 0 0 0 Undefined 0 R/W WO WO WO WO WO – RW 1 : Start outputting one-shot pulse. (Valid when an internal trigger is selected.) Fig. 7.5.4 Structures of one-shot start registers 0 and 1 7-34 7905 Group User ’ s Manual Rev.1.0 T IMER A 7.5 One-shot pulse mode 7.5.3 Operation in one-shot pulse mode ➀ W hen the one-shot pulse mode is selected with the operating mode select bits, the TAiOUT p in outputs “ L ” l evel. ➁ When the count start bit is set to “1,” the counter is enabled for counting. After that, counting starts when a trigger is generated. ➂ W hen the counter starts counting, the TAiOUT p in outputs “ H ” l evel. (When a value of “ 0000 16” i s set to the timer Ai register, the counter stops operating, the output level at pin TAiOUT remains “L,” and no timer Ai interrupt request does not occur.) ➃ W hen the counter value becomes “ 0000 16, ” t he output from the TAi OUT p in becomes “ L ” l evel. Additionally, the reload register ’ s contents are reloaded and the counter stops counting there. ➄ S imultaneously with ➃ , the timer Ai interrupt request bit is set to “ 1. ” This interrupt request bit remains set to “ 1 ” u ntil the interrupt request is accepted or until the interrupt request bit is cleared to “ 0 ” b y software. Figure 7.5.5 shows an example of operation in the one-shot pulse mode. When a trigger is generated after ➃ a bove, the counter and TAi OUT p in perform the same operations beginning from ➁ a gain. Furthermore, if a trigger is generated during counting, the counter performs countdown once after this new trigger is generated, and then, it continues counting with the reload register’s contents reloaded. If generating a trigger during counting, make sure that a certain time which is equivalent to one cycle of the timer’s count source or more has passed between the previously trigger occurrence and a new trigger occurrence. The one-shot pulse output from the TAiOUT pin can be disabled by clearing the timer Ai mode register’s bit 2 to “ 0. ” A ccordingly, timer Ai can also be used as an internal one-shot timer that does not perform the pulse output. In this case, the TAi OUT p in functions as a programmable I/O port pin. 7905 Group User ’ s Manual Rev.1.0 7-35 T IMER A 7.5 One-shot pulse mode Counter contents (Hex.) Starts counting. n Reloaded counting. Starts counting. Stops counting. Reloaded 000116 Time Set to “1” by software. ➀ Count start bit ➁ Trigger during counting TAi IN pin input signal (1 / fi) ✕ (n) One-shot pulse output from TAi OUT pin Timer Ai interrupt request bit (1 / fi) ✕ (n + 1) fi : Frequency of count source n : Reload register’s contents Cleared to “0” when interrupt request is accepted or cleared by software. ➀ When the count start bit = “0” (counting stopped), the TAiOUT pin outputs “L” level. ➁ When a trigger is generated during counting, the counter counts the count source (n + 1) times after a new trigger is generated. Note: The above applies when an external trigger (rising edge of TAiIN pin’s input signal) is selected. Fig. 7.5.5 Example of operation in one-shot pulse mode (selecting external trigger) 7-36 7905 Group User ’ s Manual Rev.1.0 T IMER A [Precautions for one-shot pulse mode] [Precautions for one-shot pulse mode] 1. If the count start bit is cleared to “ 0 ” d uring counting, the counter becomes as follows: • The counter stops counting, and the reload register ’ s contents are reloaded into the counter. • The TAi OUT p in ’ s output level becomes “ L. ” • The timer Ai interrupt request bit is set to “ 1. ” 2. A one-shot pulse is output synchronously with an internally generated count source. Accordingly, when selecting an external trigger, there will be a delay equivalent to one cycle of the count source at maximum, in a period from when a trigger is input to the TAiIN p in until a one-shot pulse is output. Fig. 7.5.6 Output delay in one-shot pulse output Trigger input TAiIN pin’s input signal Count source One-shot pulse output from TAi OUT pin Starts outputting of one-shot pulse Note: The above applies when an external trigger (falling edge of TAiIN pin’s input signal) is selected. 3. When the timer’s operating mode has been set by one of the following procedures, the timer Ai interrupt request bit will be set to “ 1. ” q When the one-shot pulse mode is selected after reset q When the operating mode is switched from the timer mode to the one-shot pulse mode q When the operating mode is switched from the event counter mode to the one-shot pulse mode Accordingly, when using a timer Ai interrupt (interrupt request bit), be sure to clear the timer Ai interrupt request bit to “ 0 ” a fter the above setting. 7905 Group User ’ s Manual Rev.1.0 7-37 T IMER A 7.6 Pulse width modulation (PWM) mode 7.6 Pulse width modulation (PWM) mode In this mode, the timer continuously outputs pulses which have an arbitrary width. Table 7.6.1 lists the specifications of the PWM mode. Figure 7.6.1 shows the structure of the timer Ai register, and Figure 7.6.2 shows the structure of timer Ai mode register in the PWM mode. Table 7.6.1 Specifications of PWM mode Item Count source f i Count operation f 1, f 2, f 16, f 64, f 512, or f 4096 q C ountdown (operating as an 8-bit or 16-bit pulse width modulator) q Reload register’s contents are reloaded at rising edge of PWM pulse, and counting continues. q A t rigger generated during counting does not affect the counting. PWM period/ “ H ” l evel width (216–1) Period = [s] fi n : Timer Ai register ’ s set value n “ H ” l evel width = f i [s] m : Timer Ai register ’ s low-order 8 (m + 1)(28– 1) bits ’ s et value [s] Period = fi n : Timer Ai register ’ s high-order n(m + 1) “ H ” l evel width = [s] 8 bits ’ s et value fi q W hen a trigger is generated. ( Note) q I nternal or external trigger can be selected by software. Count stop condition When the count start bit is cleared to “ 0. ” Interrupt request occurrence timing At falling edge of PWM pulse Programmable I/O port pin or trigger input pin TAi IN p in ’ s function TAi OUT p in ’ s function Read from timer Ai register Write to timer Ai register PWM pulse output An undefined value is read out. q W hile counting is stopped When a value is written to the timer Ai register, it is written to both of the reload register and counter. q W hile counting is in progress When a value is written to the timer Ai register, it is written only to the reload register. (Transferred to the counter at the next reload time.) Note: T he trigger is generated with the count start bit = “ 1. ” Specifications Count start condition 7-38 7905 Group User ’ s Manual Rev.1.0 T IMER A 7.6 Pulse width modulation (PWM) mode Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Timer A5 register (Addresses C716, C616) Timer A6 register (Addresses C916, C816) Timer A7 register (Addresses CB16, CA16) Timer A8 register (Addresses CD16, CC16) Timer A9 register (Addresses CF16, CE16) (b15) b7 (b8) b0 b7 b0 Bit Function At reset R/W WO Undefined 15 to 0 Any value in the range from “000016” to “FFFE16” can be set. Assuming that the set value = n, the “H” level width of the PWM pulse which is output n from the TAiOUT pin is expressed as follows : fi (PWM pulse period = 216–1 ) fi fi: Frequency of count source Note: Use the MOVM or STA(STAD) instruction for writing to this register. Writing to this register must be performed in a unit of 16 bits. Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Timer A5 register (Addresses C716, C616) Timer A6 register (Addresses C916, C816) Timer A7 register (Addresses CB16, CA16) Timer A8 register (Addresses CD16, CC16) Timer A9 register (Addresses CF16, CE16) (b15) b7 (b8) b0 b7 b0 Bit 7 to 0 Function At reset R/W WO Undefined Any value in the range from “0016” to “FF16” can be set. Assuming that the set value = m, the period of the PWM pulse which is output from the TAiOUT pin is expressed as follows: (m + 1) (28 – 1) fi Undefined 15 to 8 Any value in the range from “0016” to “FF16” can be set. Assuming that the set value = n, the “H” level width of the PWM pulse which is output from the TAiOUT pin is expressed as follows: n(m + 1) fi fi: Frequency of count source Note: Use the MOVM or STA(STAD) instruction for writing to this register. Writing to this register must be performed in a unit of 16 bits. WO Fig. 7.6.1 Structures of timer Ai register in PWM mode 7905 Group User ’ s Manual Rev.1.0 7-39 T IMER A 7.6 Pulse width modulation (PWM) mode Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) Timer Ai mode register (i = 5 to 9) (Addresses D616 to DA16) b7 b6 b5 b4 b3 b2 b1 b0 111 Bit 0 1 2 3 4 5 6 7 16/8-bit PWM mode select bit Count source select bits Fix this bit to “1” in PWM mode. Trigger select bits b4 b3 Bit name Operating mode select bits b1 b0 Function 1 1 : PWM mode At reset 0 0 0 R/W RW RW RW RW RW RW RW RW Writing “1” to count start bit (TAiIN pin functions as a programmable I/O port pin.) 1 0 : Falling edge of TAiIN pin’s input signal 1 1 : Rising edge of TAiIN pin’s input signal 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator See Table 7.2.3. 00: 01: 0 0 0 0 0 Fig. 7.6.2 Structures of timer Ai mode register in PWM mode 7-40 7905 Group User ’ s Manual Rev.1.0 T IMER A 7.6 Pulse width modulation (PWM) mode 7.6.1 Setting for PWM mode Figures 7.6.3 and 7.6.4 show an initial setting example for registers relevant to the PWM mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to “ CHAPTER 6. INTERRUPTS.” Selecting PWM mode and each function b7 b0 111 Timer Ai mode register (i = 0 to 9) (Addresses 5616 to 5A16, D616 to DA16) Selection of PWM mode Trigger select bits b4 b3 00: Writing “1” to count start bit: Internal trigger 01: 1 0 : Falling edge of TAiIN pin’s input signal: External trigger 1 1 : Rising edge of TAiIN pin’s input signal: External trigger 16/8-bit PWM mode select bit 0 : Operates as 16-bit pulse width modulator 1 : Operates as 8-bit pulse width modulator Count source select bits See Table 7.2.3. Setting PWM pulse’s period and “H” level width q When operating as 16-bit pulse width modulator (b15) b7 (b8) b0 b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Timer A5 register (Addresses C716, C616) Timer A6 register (Addresses C916, C816) Timer A7 register (Addresses CB16, CA16) Timer A8 register (Addresses CD16, CC16) Timer A9 register (Addresses CF16, CE616) Can be set to “0000 16” to “FFFE 16” (n) q When operating as 8-bit pulse width modulator (b15) b7 (b8) b0 b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Timer A5 register (Addresses C716, C616) Timer A6 register (Addresses C916, C816) Timer A7 register (Addresses CB16, CA16) Timer A8 register (Addresses CD16, CC16) Timer A9 register (Addresses CF16, CE616) Can be set to “00 16” to “FF 16” (m) Can be set to “00 16” to “FE 16” (n) Note. When operating as 8-bit pulse width modulator (m+1) (28 – 1) (fi : Frequency of Period = fi count source) “H” level width = n(m+1) fi “H” level width = Note. When operating as 16-bit pulse width modulator 216 – 1 (fi : Frequency of count source) Period = fi n fi However, if n = “00 16”, the pulse width modulator does not operate and the TAi OUT pin outputs “L” level. At this time, no timer Ai interrupt request occurs. However, if n = “0000 16”, the pulse width modulator does not operate and the TAi OUT pin outputs “L” level. At this time, no timer Ai interrupt request occurs. Continued to Figure 7.6.4 on the next page Fig. 7.6.3 Initial setting example for registers related to PWM mode (1) 7905 Group User ’ s Manual Rev.1.0 7-41 T IMER A 7.6 Pulse width modulation (PWM) mode Continued from preceding Figure 7.6.3 Setting interrupt priority level b7 b0 Timer Ai interrupt control register (i = 0 to 9) (Addresses 7516 to 7916, F516 to F916 ) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. When external trigger is selected When internal trigger is selected Setting port P6, port P2, and port P4 direction registers b7 b0 Setting count start bit to “1” b7 b0 Port P6 direction register (Address 1016) Pin TA0IN Pin TA1IN Pin TA2IN Pin TA3IN (Address 4016) Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit b7 b0 b7 b0 Port P2 direction register (Address 816) Pin TA4IN Pin TA9IN b7 b0 Count start register 1 (Address 4116) Timer A5 count start bit Timer A6 count start bit Timer A7 count start bit Timer A8 count start bit Timer A9 count start bit Port P4 direction register (Address C16) Pin TA5IN Pin TA6IN Pin TA7IN Pin TA8IN Clear the corresponding bit to “0.” Setting count start bit to “1” b7 b0 Count start register 0 (Address 4016) Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit b7 b0 Count start register 1 (Address 4116) Timer A5 count start bit Timer A6 count start bit Timer A7 count start bit Timer A8 count start bit Timer A9 count start bit Trigger input to TAi IN pin Trigger generated Count starts. Fig. 7.6.4 Initial setting example for registers related to PWM mode (2) 7-42 7905 Group User ’ s Manual Rev.1.0 T IMER A 7.6 Pulse width modulation (PWM) mode 7.6.2 Trigger When a trigger is generated, the TAiOUT pin starts to output PWM pulses. An internal or an external trigger can be selected as that trigger. An internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 56 16 to 5A 16, D616 to DA16) are “ 00 2” o r “ 01 2” ; an external trigger is selected when these bits are “ 10 2” o r “ 11 2. ” A trigger generated during PWM pulse output is invalid, and it does not affect the pulse output operation. (1) When selecting internal trigger A trigger is generated when “ 1 ” i s written to the count start bit (addresses 40 16, 4116). (2) When selecting external trigger A trigger is generated at the falling edge of the TAi IN p in ’ s input signal when bit 3 at addresses 56 16 t o 5A16, D6 16 t o DA16 i s “ 0, ” o r at its rising edge when bit 3 is “ 1. ” H owever, the trigger input is acceptableonly when the count start bit is “ 1. ” When using an external trigger, set the port P6, port P2, and port P4 direction registers’ bits which correspond to the TAi IN p ins for the input mode. 7905 Group User ’ s Manual Rev.1.0 7-43 T IMER A 7.6 Pulse width modulation (PWM) mode 7.6.3 Operation in PWM mode ➀ W hen the PWM mode is selected with the operating mode select bits, the TAiOUT p in outputs “ L ” l evel. ➁ W hen a trigger is generated, the counter (pulse width modulator) starts counting and the TAi OUT p in outputs a PWM pulse (Notes 1 and 2 ). ➂ T he timer Ai interrupt request bit is set to “ 1 ” e ach time the PWM pulse level goes from “ H ” t o “ L. ” The interrupt request bit remains set to “ 1 ” u ntil the interrupt request is accepted or until the interrupt request bit is cleared to “ 0 ” b y software. ➃ Each time a PWM pulse has been output for one period, the reload register’s contents are reloaded and the counter continues counting. The following explains operations of the pulse width modulator. (1) 16-bit pulse width modulator When the 16/8-bit PWM mode select bit is cleared to “0,” the counter operates as a 16-bit pulse width modulator. Figures 7.6.5 and 7.6.6 show operation examples of the 16-bit pulse width modulator. (2) 8-bit pulse width modulator When the 16/8-bit PWM mode select bit is set to “1,” the counter is divided into 8-bit halves. Then, the high-order 8 bits operate as an 8-bit pulse width modulator, and the low-order 8 bits operate as an 8-bit prescaler. Figures 7.6.7 and 7.6.8 show operation examples of the 8-bit pulse width modulator. Notes 1: I f a value “ 0000 16” i s set into the timer Ai register when the counter operates as a 16-bit pulse width modulator, the pulse width modulator does not operate and the output from the TAiOUT p in remains “ L ” l evel. The timer Ai interrupt request does not occur. Similarly, if a value “ 00 16 ” i s set into the high-order 8 bits of the timer Ai register when the counter operates as an 8-bit pulse width modulator, the same is performed. 2: When the counter operates as an 8-bit pulse width modulator, after a trigger is generated, the TAi OUT p in outputs “ L ” l evel for a period of (1 / fi) ✕ ( m + 1) ✕ ( n + 1). After that, the PWM pulse output will start. 7-44 7905 Group User ’ s Manual Rev.1.0 T IMER A 7.6 Pulse width modulation (PWM) mode (1 / fi) ✕ (216 – 1) Count source TAi IN pin’s input signal Trigger is not generated by this signal. (1 / fi) ✕ (n) PWM pulse output from TAi OUT pin Timer Ai interrupt request bit fi: Frequency of count source n: Reload register Cleared to “0” when interrupt request is accepted or cleared by software. Note: The above applies when n = “0003 16” and an external trigger (rising edge of TAi IN pin’s input signal) is selected. Fig. 7.6.5 Operation example of 16-bit pulse width modulator n = Reload register’s contents (1 / fi) ✕ (216 –1) (1 / fi) ✕ (216 –1) 1 (1 / fi) ✕ (2 6 –1) Counter contents (Hex.) FFFE16 200016 (216 –1) – n n 000116 Stops counting. Restarts counting. Time TAi IN pin’s input signal PWM pulse output from TAi OUT pin ➀ fi: Frequency of count source n: Reload register’s contents “FFFE16” is set to timer Ai register. “0000 16” is set to timer Ai register. “200016” is set to timer Ai register. ➀ When an arbitrary value is set to the timer Ai register after setting “0000 16” to it, the timing when the PWM pulse goes “H” depends on the timing when the new value is set. Note: The above applies when an external trigger (rising edge of TAi IN pin’s input signal) is selected. Fig. 7.6.6 Operation example of 16-bit pulse width modulator (when counter value is updated during pulse output) 7905 Group User ’ s Manual Rev.1.0 7-45 T IMER A 7.6 Pulse width modulation (PWM) mode (1 / fi) ✕ (m + 1) ✕ (28 – 1) ➀ Count source TAi IN pin’s input signal (1 / fi) ✕ (m + 1) ➁ 8-bit prescaler’s underflow signal (1 / fi) ✕ (m + 1) ✕ (n) PWM pulse output from TAi OUT pin Timer Ai interrupt request bit Cleared to “0” when interrupt request is accepted or cleared by software. fi: Frequency of count source n: Reload register’s high-order 8 bits m: Reload register’s low-order 8 bits ➀ The 8-bit prescaler counts the count source. ➁ The 8-bit pulse width modulator counts the 8-bit prescaler’s underflow signal. Note: The above applies when n = “02 16”, m = “0216”, and an external trigger (falling edge of TAi IN pin’s input signal) is selected. Fig. 7.6.7 Operation example of 8-bit pulse width modulator 7-46 7905 Group User ’ s Manual Rev.1.0 (1 / fi) ✕ (m+1) ✕ (28 –1) (1 / fi) ✕ (m+1) ✕ (28 –1) (1 / fi) ✕ (m + 1) ✕ (28 –1) Count source TAi IN pin’s input signal 0216 Prescaler's contents (Hex.) 0016 Time 0A16 Counter’s contents (Hex.) 0416 0116 Time Stops counting. Restarts counting. Fig. 7.6.8 Operation example of 8-bit pulse width modulator (when counter value is updated during pulse output) ➀ “040216” is set to timer Ai register. “000216” is set to timer Ai register. “0A0216” is set to timer Ai register. 7905 Group User ’ s Manual Rev.1.0 PWM pulse output from TAi OUT pin fi: Frequency of count source m: Reload register’s low-order 8 bits ➀ When an arbitrary value is set to the timer Ai register after setting “00 16” to it, the timing when the PWM pulse level goes “H” depends on the timing when the new value is set. T IMER A 7.6 Pulse width modulation (PWM) mode Note: The above applies when an external trigger (falling edge of TAi IN pin’s input signal) is selected. 7-47 T IMER A [Precautions for pulse width modulation (PWM) mode] [Precautions for pulse width modulation (PWM) mode] 1. If the count start bit is cleared to “0” during PWM pulse output, the counter stops counting. If the TAiOUT pin outputs “ H ” l evel at that time, the output level will become “ L ” a nd the timer Ai interrupt request bit will be set to “1.” When the TAi OUT pin outputs “L” level at that time, the output level will not change and no timer Ai interrupt request will occur. 2. When the timer’s operating mode is set by one of the following procedures, the timer Ai interrupt request bit is set to “ 1. ” q When the PWM mode is selected after reset q When the operating mode is switched from the timer mode to the PWM mode q When the operating mode is switched from the event counter mode to the PWM mode Accordingly, when using a timer Ai interrupt (interrupt request bit), be sure to clear the timer Ai interrupt request bit to “ 0 ” a fter the above setting. 7-48 7905 Group User ’ s Manual Rev.1.0 CHAPTER 8 TIMER B 8.1 Overview 8.2 Block description 8.3 Timer mode [Precautions for timer mode] 8.4 Event counter mode [Precautions for event counter mode] 8.5 Pulse period/Pulse width measurement mode [Precautions for pulse period/pulse width measurement mode] TIMER B 8.1 Overview, 8.2 Block description 8.1 Overview Timer B consists of three counters (timers B0 to B2) each equipped with a 16-bit reload function. Timers B0 to B2 have identical functions and operate independently of one other. Timer Bi (i = 0 to 2) has three operating modes listed below. (1) Timer mode The timer counts an internally generated count source. (2) Event counter mode The timer counts an external signal. (3) Pulse period/Pulse width measurement mode The timer measures an external signal’s pulse period or pulse width. In this mode, the following count types are available: • Count clear type • Free-run type 8.2 Block description Figure 8.2.1 shows the block diagram of timer B. Explanation of registers relevant to timer B is described below. Count source select bits Data bus (odd) Data bus (even) (Low-order 8 bits) (High-order 8 bits) f2 f16 f64 f512 •Timer •Pulse period measurement/pulse width measurement Polarity selection and edge pulse generator Event counter mode fX32 Timer B2 clock source select bit (Note) Timer Bi counter (16) Timer Bi reload register (16) TBiIN Timer Bi interrupt request bit Count start register Timer Bi overflow flag (Valid in the pulse period/pulse width measurement mode.) Counter reset circuit Timer B2 clock source select bit : Bit 6 at address 6316 Note: Only for timer B2, a clock source in the event counter mode can be selected. Fig. 8.2.1 Block diagram of timer B 8-2 7 905 Group User’s Manual Rev.1.0 TIMER B 8.2 Block description 8.2.1 Counter and Reload register (timer Bi register) Each of timer Bi counter and reload register consists of 16 bits and has the following functions. (1) Functions in timer mode and event counter mode Countdown in the counter is performed each time the count source is input. The reload register is used to store the initial value of the counter. When a counter underflow occurs, the reload register’s contents are reloaded into the counter. A value is set to the counter and reload register by writing the value to the timer Bi register. Table 8.2.1 lists the memory assignment of the timer Bi register. The value written into the timer Bi register while counting is not in progress is set to the counter and reload register. The value written into the timer Bi register while counting is in progress is set only to the reload register. In this case, the reload register ’ s updated contents are transferred to the counter at the next underflow. The counter value is read out by reading out the timer Bi register. Note: When reading from or writing to the timer Bi register, perform it in a unit of 16 bits. For more information about the value obtained by reading the timer Bi register, refer to sections “[Precautions for timer mode]” a nd “ [Precautions for event counter mode].” (2) Functions in pulse period/pulse width measurement mode Countup in the counter is performed each time the count source is input. The reload register is used to retain the pulse period or pulse width measurement result. When a valid edge is input to the TBiIN pin, the counter value is transferred to the reload register. In this mode, the value obtained by reading the timer Bi register is the reload register ’ s contents, so that the measurement result is obtained. By using the count-type select bit (bit 4 at addresses 5B16 t o 5D 16), the count type can be selected from the counter clear type and free-run type. The operation of the counter after the counter value is transferred to the reload register is as follows; • In the case of the counter clear type, the counter value becomes “000016”; and counting continues. • In the case of the free-run type, the counter value does not become “000016”; and counting continues with this counter value kept. Note: W hen reading from the timer Bi register, perform it in a unit of 16 bits. Table 8.2.1 Memory assignment of timer Bi registers Timer Bi register High-order byte Low-order byte Timer B0 register Address 51 16 Address 5016 Address 53 16 Timer B1 register Address 5216 Timer B2 register Address 55 16 Address 5416 Note : At reset, the contents of the timer Bi register are undefined. 7 905 Group User ’ s Manual Rev.1.0 8-3 TIMER B 8.2 Block description 8.2.2 Count start register This register is used to start and stop counting. One bit of this register corresponds to one timer. (This is the one-to-one relationship.) Figure 8.2.2 shows the structure of the count start register 0. b7 b6 b5 b4 b3 b2 b1 b0 Count start register 0 (Address 4016) Bit 0 1 2 3 4 5 6 7 Bit name Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit 0 : Stop counting 1 : Start counting Function At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Fig. 8.2.2 Structure of count start register 0 8.2.3 Timer Bi mode register Figure 8.2.3 shows the structure of the timer Bi mode register. The operating mode select bits are used to select the operating mode of timer Bi. Bits 2 to 7 have different functions according to the operating mode. These bits are described in the paragraph of each operating mode. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Bit 0 1 2 3 4 5 6 7 Note: Bit 5 is invalid in the timer and event counter modes; its value is undefined at reading. Bit name Operating mode select bits b1 b0 Function 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/Pulse width measurement mode 1 1 : Do not select. At reset 0 0 0 0 0 Undefined 0 0 R/W RW RW RW RW RW RO (Note) RW RW These bits have different functions according to the operating mode. Fig. 8.2.3 Structure of timer Bi mode register 8-4 7 905 Group User ’ s Manual Rev.1.0 TIMER B 8.2 Block description 8.2.4 Timer Bi interrupt control register Figure 8.2.4 shows the structure of the timer Bi interrupt control register. For details about interrupts, refer to “ CHAPTER 6. INTERRUPTS.” b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A16 to 7C16) Bit 0 1 2 3 7 to 4 Interrupt request bit Nothing is assigned. Bit name Interrupt priority level select bits b2 b1 b0 Function 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested At reset 0 0 0 0 Undefined R/W RW RW RW RW (Note) — Note: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. Fig. 8.2.4 Structure of timer Bi interrupt control register (1) Interrupt priority level select bits (bits 2 to 0) These bits are used to select a timer Bi interrupt ’ s priority level. When using timer Bi interrupts, select the priority level from levels 1 through 7. When a timer Bi interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL), so that the requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable bit (I) = “ 0. ” ) To disable timer Bi interrupts, set these bits to “ 000 2” ( level 0). (2) Interrupt request bit (bit 3) This bit is set to “1” when a timer Bi interrupt request occurs. This bit is automatically cleared to “0” when the timer Bi interrupt request is accepted. This bit can be set to “ 1 ” o r cleared to “ 0 ” b y software. 7 905 Group User ’ s Manual Rev.1.0 8-5 TIMER B 8.2 Block description 8.2.5 Port P2 direction register, Port P5 direction register The input pins of timer Bi are multiplexed with port P5 pins. By using the TB0IN/TB1IN/TB2IN p in select bit (see Figure 8.2.5.), pin TB0 IN/TB1IN/TB2 IN c an be allocated to the corresponding port P2 pin. When using pins P5 5(P2 4)/TB0 IN, P56(P25)/TB1 IN, P57(P2 6)/TB2IN a s timer Bi ’ s input pins, be sure to clear the corresponding bits of the port direction register, which is multiplexed, to “0” in order to set these pins to the input mode. (See Figure 8.2.6.) b7 b6 b5 b4 b3 b2 b1 b0 Port P2 pin function control register (Address AE16) Bit 0 1 2 6 to 3 7 Bit name Pin TB0IN select bit Pin TB1IN select bit Pin TB2IN select bit Nothing is assigned. Fix this bit to “0.” Function 0 : Allocate pin TB0IN to P55. 1 : Allocate pin TB0IN to P24. 0 : Allocate pin TB1IN to P56. 1 : Allocate pin TB1IN to P25. 0 : Allocate pin TB2IN to P57. 1 : Allocate pin TB2IN to P26. 0 At reset 0 0 0 Undefined 0 R/W RW RW RW — RW Fig. 8.2.5 Structure of port P2 pin function control register 8-6 7 905 Group User ’ s Manual Rev.1.0 TIMER B 8.2 Block description b7 b6 b5 b4 b3 b2 b1 b0 Port P5 direction register (Address D16) Bit 0 1 2 3 4 5 6 7 Corresponding pin Nothing is assigned. Pin INT1 Pin INT2/RTPTRG1 Pin INT3/RTPTRG0 Nothing is assigned. Pin TB0IN (Pin INT5/IDW) Pin TB1IN (Pin INT6/IDV) Pin TB2IN (Pin INT7/IDU) (Note 1) (Note 2) (Note 3) 0 : Input mode 1 : Output mode When using this pin as timer Bi’s input pin, be sure to clear the corresponding bit to “0.” 0 : Input mode 1 : Output mode Functions At reset Undefined 0 0 0 Undefined 0 0 0 R/W – RW RW RW – RW RW RW Notes 1: This applies when the TB0IN pin select bit (bit 0 at address AE16) = 0. 2: This applies when the TB1IN pin select bit (bit 1 at address AE16) = 0. 3: This applies when the TB2IN pin select bit (bit 2 at address AE16) = 0. 4: The pins in ( ) are I/O pins of other internal peripheral devices, which are multiplexed with the corresponding port P5 pins. b7 b6 b5 b4 b3 b2 b1 b0 Port P2 direction register (Address 816) Bit 0 1 2 3 4 5 6 7 Corresponding pin Pin TA4OUT Pin TA4IN Pin TA9OUT Pin TA9IN Pin TB0IN Pin TB1IN Pin TB2IN Pin P27 (Note 1) (Note 2) (Note 3) When using this pin as timer Bi’s input pin, be sure to clear the corresponding bit to “0.” 0 : Input mode 1 : Output mode Functions At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Notes 1: This applies when the TB0IN pin select bit (bit 0 at address AE16) = 1. 2: This applies when the TB1IN pin select bit (bit 1 at address AE16) = 1. 3: This applies when the TB2IN pin select bit (bit 2 at address AE16) = 1. Fig. 8.2.6 Relationship between port P5 direction register, port P2 direction register, and timer Bi’s input pins 8.2.6 Count source (in timer mode and pulse period/pulse width measurement mode) In the timer mode and pulse period/pulse width measurement mode, the count source select bits (bits 6 and 7 at addresses 5B 16 to 5D16) are used to select the count source (f2, f 16, f64, or f 512). (See Figures 8.3.1 and 8.5.1.) 7 905 Group User ’ s Manual Rev.1.0 8-7 TIMER B 8.3 Timer mode 8.3 Timer mode In this mode, the timer counts an internally generated count source. Table 8.3.1 lists the specifications of the timer mode. Figure 8.3.1 shows the structures of the timer Bi register and timer Bi mode register in the timer mode. Table 8.3.1 Specifications of timer mode Item Count source f i Count operation f 2, f 16, f 64, or f 512 •Countdown • When a counter underflow occurs, reload register’s contents are reloaded, and counting continues. Division ratio Count start condition Count stop condition Interrupt request occurrence timing TBi IN p in ’ s function Read from timer Bi register Write to timer Bi register 1 (n + 1) n: Timer Bi register ’ s set value Specifications When the count start bit is set to “ 1. ” When the count start bit is cleared to “ 0. ” When a counter underflow occurs. Programmable I/O port pin Counter value can be read out. q While counting is stopped When a value is written to the timer Bi register, it is written to both of the reload register and counter. q While counting is in progress When a value is written to the timer Bi register, it is written only to the reload register. (Transferred to the counter at the next reload timing.) 8-8 7 905 Group User ’ s Manual Rev.1.0 TIMER B 8.3 Timer mode Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) Bit (b15) b7 (b8) b0 b7 b0 Function At reset R/W RW 15 to 0 Any value in the range from “000016” to “FFFF16” can be set. Undefined Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. Note: Reading from or writing to this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Bit 0 1 2 3 4 5 6 7 X : It may be either “0” or “1.” XXXX00 At reset 0 0 R/W RW RW RW RW — RO RW RW Bit name Operating mode select bits b1 b0 Function 0 0 : Timer mode These bits are invalid in timer mode. 0 0 0 This bit is invalid in timer mode; its value is undefined at reading. Count source select bits b7 b6 Undefined 0 0 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 Fig. 8.3.1 Structures of timer Bi register and timer Bi mode register in timer mode 7 905 Group User ’ s Manual Rev.1.0 8-9 TIMER B 8.3 Timer mode 8.3.1 Setting for timer mode Figure 8.3.2 shows an initial setting example for registers relevant to the timer mode. Note that when using interrupts, set up registers to enable the interrupts. For details, refer to “CHAPTER 6. INTERRUPTS.” Selecting timer mode and count source b7 b0 ✕✕✕✕0 0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Selection of timer mode Count source select bits b7 b6 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 ✕: It may be either “0” or “1.” Setting division ratio (b15) b7 (b8) b0 b7 b0 Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) Can be set to “000016” to “FFFF16” (n). Note: The counter divides the count source by (n + 1). Setting interrupt priority level b7 b0 Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A16 to 7C16) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Setting count start bit to “1” b7 b0 Count start register 0 (Address 4016) Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit Count starts. Fig. 8.3.2 Initial setting example for registers relevant to timer mode 8-10 7 905 Group User’s Manual Rev.1.0 TIMER B 8.3 Timer mode 8.3.2 Operation in timer mode ➀ W hen the count start bit is set to “ 1, ” t he counter starts counting of the count source. ➁ When a counter underflow occurs, the reload register’s contents are reloaded and counting continues. ➂ T he timer Bi interrupt request bit is set to “ 1 ” a t the counter underflow in ➁ . The interrupt request bit remains set to “ 1 ” u ntil the interrupt request is accepted or until the interrupt request bit is cleared to “ 0 ” b y software. Figure 8.3.3 shows an example of operation in the timer mode. FFFF16 Counter contents (Hex.) Starts counting. 1 / fi ✕ (n+1) Stops counting. n Restarts counting. 000016 Time Set to “1” by software. Cleared to “0” by software. Set to “1” by software. Count start bit Timer Bi interrupt request bit fi : Frequency of count source n : Reload register’s contents Cleared to “0” when interrupt request is accepted or cleared by software. Fig. 8.3.3 Example of operation in timer mode 7 905 Group User ’ s Manual Rev.1.0 8-11 TIMER B [Precautions for timer mode] [Precautions for timer mode] While counting is in progress, by reading the timer Bi register, the counter value can be read out at arbitrary timing. However, if the timer Bi register is read at the reload timing shown in Figure 8.3.4, the value “FFFF16” is read out. If reading is performed in the period from when a value is set into the timer Bi register with the counter stopped until the counter starts counting, the set value is correctly read out. Reload Counter value (Hex.) 2 1 0 n n–1 Read value (Hex.) 2 1 0 FFFF n – 1 Time n = Reload register’s contents Fig. 8.3.4 Reading timer Bi register 8-12 7 905 Group User ’ s Manual Rev.1.0 TIMER B 8.4 Event counter mode 8.4 Event counter mode In this mode, the timer counts an external signal. Table 8.4.1 lists the specifications of the event counter mode. Figure 8.4.1 shows the structures of the timer Bi register and the timer Bi mode register in the event counter mode. Table 8.4.1 Specifications of event counter mode Item Count source Specifications • External signal input to the TBi IN p in, or fX 32 ( Note 1) •The count source’s valid edge can be selected from the falling edge, the rising edge, and both of the falling and rising edges by software. Count operation •Countdown • When a counter underflow occurs, reload register ’ s contents are reloaded, and counting continues. 1 (n + 1) Division ratio Count start condition Count stop condition Interrupt request occurrence timing TBi IN p in ’ s function Read from timer Bi register Write to timer Bi register n: Timer Bi register ’ s set value When the count start bit is set to “ 1. ” When the count start bit is cleared to “ 0. ” When the counter underflow occurs. Count source input pin ( Note 2) Counter value can be read out. q While counting is stopped When a value is written to the timer Bi register, it is written to both of the reload register and counter. q While counting is in progress When a value is written to the timer Bi register, it is written only to the reload register. (Transferred to the counter at the next reload timing.) Notes 1: O nly for timer B2, fX 32 c an be selected. 2: When fX32 is selected as the count source in timer B2, the TB2IN pin can be used as a programmable I/O port pin or as I/O pins of other internal peripheral devices, which are multiplexed. 7 905 Group User ’ s Manual Rev.1.0 8-13 TIMER B 8.4 Event counter mode Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) Bit (b15) b7 (b8) b0 b7 b0 Function At reset R/W RW 15 to 0 Any value in the range from “000016” to “FFFF16” can be set. Undefined Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. Note: Reading from or writing to this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Bit 0 1 2 3 4 5 6 7 X : It may be either “0” or “1.” XXXX At reset 0 0 01 R/W RW RW RW RW — RO RW RW Bit name Operating mode select bits b1 b0 Function 0 1 : Event counter mode b3 b2 Count polarity select bits 0 0 : Count at falling edge of external signal 0 1 : Count at rising edge of external signal 1 0 : Count at both falling and rising edges of external signal 1 1 : Do not select. (Note) 0 0 0 Undefined 0 0 This bit is invalid in event counter mode. This bit is invalid in event counter mode; its value is undefined at reading. These bits are invalid in event counter mode. Note: When the timer B2 clock source select bit (bit 6 at address 6316) = “1,” be sure to fix these bits to “012” (count at the rising edge of the external signal). Fig. 8.4.1 Structures of timer Bi register and timer Bi mode register in event counter mode 8-14 7 905 Group User ’ s Manual Rev.1.0 TIMER B 8.4 Event counter mode 8.4.1 Count source For timer B2 in the event counter mode, a count source (an external signal into the TB2IN pin, or fX32) can be selected by using the timer B2 clock source select bit. (See Figure 8.4.2.) Timers B0 and B1 count the external signals input to the TB0 IN a nd TB1 IN p ins, respectively. When fX32 i s selected as the count source, the TB2 IN p in serves as a programmable I/O port pin or as I/ O pins of other internal peripheral devices, which are multiplexed. b7 b6 b5 b4 b3 b2 b1 b0 Particular function select register 1 (Address 6316) Bit 0 1 2 3 4 5 6 Bit name STP-instruction-execution status bit WIT-instruction-execution status bit Fix this bit to “0.” System clock stop select bit at WIT (Note 3) Fix this bit to “0.” The value is “0” at reading. Timer B2 clock source select bit 0 : External signal input to the TB2IN pin is counted. (Valid in event counter mode.) 1 : fX32 is counted. (Note 4) The value is “0” at reading. 0 : In the wait mode, system clock fsys is active. 1 : In the wait mode, system clock fsys is inactive. Function 0 : Normal operation. 1 : During execution of STP instruction 0 : Normal operation. 1 : During execution of WIT instruction 0 0 At reset (Note 1) (Note 1) 0 0 0 0 0 RW (Note 2) RW (Note 2) RW RW RW — RW 7 0 — Notes 1: At power-on reset, this bit becomes “0.” At hardware reset or software reset, this bit retains the value just before reset. 2: Even when “1” is written, the bit status will not change. 3: Setting this bit to “1” must be performed just before execution of the WIT instruction. Also, after the wait state is terminated, this bit must be cleared to “0” immediately. 4: When using timer B2 in the pulse period/pulse width measurement mode, be sure to clear this bit to “0.” Fig. 8.4.2 Structure of particular function select register 1 7 905 Group User ’ s Manual Rev.1.0 8-15 TIMER B 8.4 Event counter mode 8.4.2 Setting for event counter mode Figure 8.4.3 shows an initial setting example for registers relevant to the event counter mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to section “ CHAPTER 6. INTERRUPTS.” Selecting event counter mode and count polarity b7 b0 ✕✕✕ ✕ 01 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Selection of event counter mode Count polarity select bits b3 b2 0 0 : Count at falling edge of external signal. 0 1 : Count at rising edge of external signal. 1 0 : Count at both of falling and rising edges of external signal. 1 1 : Do not selected. ✕: It may be either “0” or “1.” Timers B0 and B1 Timer B2 Selecting clock source b7 b0 0 Particular function select register 1 (Address 6316) Timer B2 clock source select bit 0 : Count an external signal input to the TB2IN pin 1 : Count fX32 Setting division ratio (b15) b7 (b8) b0 b7 b0 Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) Can be set to “000016” to “FFFF16” (n). Note: The counter divides the count source by (n + 1). Setting interrupt priority level b7 b0 Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A16 to 7C16) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. When a pin is allocated to a port P5 pin (Note 1) Setting port P5 direction register b7 b0 When a pin is allocated to a port P2 pin (Note 1) Setting port P2 direction register b7 b0 P5 direction register (Address D16) Pin TB0IN Pin TB1IN Pin TB2IN Clear the corresponding bit to “0.” (Note 2) P2 direction register (Address 816) Pin TB0IN Pin TB1IN Pin TB2IN Clear the corresponding bit to “0.” (Note 2) Setting count start bit to “1” b7 b0 Count start register 0 (Address 4016) Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit Count starts. Notes 1: By using bits 0 to 2 of the port P2 pin function control register (address AE16), be sure to set the pin allocation. (See Figure 8.2.5.) 2: When fX32 is selected as the count source in timer B2 (in other words, when bit 6 at address 6316 = 1), this setting is unnecessary. Fig. 8.4.3 Initial setting example for registers relevant to event counter mode 8-16 7 905 Group User’s Manual Rev.1.0 TIMER B 8.4 Event counter mode 8.4.3 Operation in event counter mode ➀ W hen the count start bit is set to “ 1, ” t he counter starts counting of the count source. ➁ When a counter underflow occurs, the reload register’s contents are reloaded, and counting continues. ➂ T he timer Bi interrupt request bit is set to “ 1 ” a t the counter underflow in ➁. The interrupt request bit remains set to “ 1 ” u ntil the interrupt request is accepted or until the interrupt request bit is cleared to “ 0 ” b y software. Figure 8.4.4 shows an example of operation in the event counter mode. Counter contents (Hex.) FFFF16 Starts counting. Stops counting. n Restarts counting . 000016 Time Cleared to “0” by software. Set to “1” by software. Set to “1” by software. Count start bit Timer Bi interrupt request bit n : Reload ragister’s contents Cleared to “0” when interrupt request is accepted or cleared to “0” by software. Fig. 8.4.4 Example of operation in event counter mode 7 905 Group User ’ s Manual Rev.1.0 8-17 TIMER B [Precautions for event counter mode] [Precautions for event counter mode] While counting is in progress, by reading the timer Bi register, the counter value can be read out at arbitrary timing. However, if the timer Bi register is read at the reload timing shown in Figure 8.4.5, a value “FFFF16” is read out. If reading is performed in the period from when a value is set into the timer Bi register with the counter stopped until the counter starts counting, the set value is correctly read out. Reload Counter value (Hex.) 2 1 0 n n–1 Read value (Hex.) 2 1 0 FFFF n – 1 Time n = Reload register’s contents Fig. 8.4.5 Reading timer Bi register 8-18 7 905 Group User ’ s Manual Rev.1.0 TIMER B 8.5 Pulse period/Pulse width measurement mode 8.5 Pulse period/Pulse width measurement mode In this mode, the timer measures an external signal ’ s pulse period or pulse width. Tables 8.5.1 and 8.5.2 list the specifications of the pulse period/pulse width measurement mode. Figure 8.5.1 shows the structures of the timer Bi register and timer Bi mode register in the pulse period/pulse width measurement mode. (1) Pulse period measurement The timer measures the pulse period of the external signal that is input to the TBi IN p in. (2) Pulse width measurement The timer measures the pulse width (“L” level and “H” level widths) of the external signal that is input to the TBi IN p in. Table 8.5.1 Specifications of pulse period/pulse width measurement mode (when counter clear type is selected) Specifications Item Count source fi Count operation f 2, f 16, f 64, or f512 q Countup q Counter value is transferred to the reload register at valid edge of measurement pulse, and counting continues after clearing the counter value to “ 0000 16. ” Count start condition Count stop condition Interrupt request occurrence timing When the count start bit is set to “ 1. ” When the count start bit is cleared to “ 0. ” q When a valid edge of measurement pulse is input ( Note 1) . q When a counter overflow occurs (The timer Bi overflow flag is set to “ 1 ” s imultaneously.) TBiIN p in ’ s function Read from timer Bi register Write to timer Bi register Measurement pulse input pin ( Note 2) The value obtained by reading the timer Bi register is the reload register ’ s contents (Measurement result) ( Note 3) . Invalid Timer Bi overflow flag: This bit is used to identify the source of an interrupt request occurrence. Notes 1: N o interrupt request occurs when the first valid edge is input after the counter starts counting. 2: W hen using timer B2, make sure that the timer B2 clock source select bit (see Figure 8.4.2.) to “0.” 3: T he value read out from the timer Bi register is undefined in the period after the counter starts counting until the second valid edge is input. 7 905 Group User ’ s Manual Rev.1.0 8-19 TIMER B 8.5 Pulse period/Pulse width measurement mode Table 8.5.2 Specifications of pulse period/pulse width measurement mode (when free-run type is selected) Item Count source fi Count operation f 2, f 16, f 64, or f 512 q Countup q Counter value is transferred to the reload register at valid edge of measurement pulse, and counting continues. q When a counter overflow occurs, the timer Bi overflow flag is set to “1,” and counting continues after clearing the counter value to “000016.” Count start condition Count stop condition Interrupt request occurrence timing TBi IN p in ’ s function Read from timer Bi register Write to timer Bi register When the count start bit is set to “ 1. ” When the count start bit is cleared to “ 0. ” When a valid edge of measurement pulse is input ( Note 1) . Measurement pulse input pin ( Note 2) The value obtained by reading the timer Bi register is the reload register ’ s contents (Measurement result) ( Note 3). Invalid Timer Bi overflow flag: This bit is used to identify the source of an interrupt request occurrence. Notes 1: N o interrupt request occurs when the first valid edge is input after the counter starts counting. 2: W hen using timer B2, make sure that the timer B2 clock source select bit (see Figure 8.4.2.) = “0.” 3: T he value read out from the timer Bi register is undefined in the period after the counter starts counting until the second valid edge is input. Specifications 8-20 7 905 Group User ’ s Manual Rev.1.0 TIMER B 8.5 Pulse period/Pulse width measurement mode Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) Bit 15 to 0 (b15) b7 (b8) b0 b7 b0 Function The measurement result of pulse period or pulse width is read out. At reset Undefined R/W RO Note: Reading from this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Bit 0 1 2 Measurement mode select bits b3 b2 10 At reset 0 0 R/W RW RW RW Bit name Operating mode select bits b1 b0 Function 1 0 : Pulse period/Pulse width measurement mode 3 0 0 : Pulse period measurement (Interval between falling edges of measurement pulse) 0 1 : Pulse period measurement (Interval between rising edges of measurement pulse) 1 0 : Pulse width measurement (Interval from a falling edge to a rising edge, and from a rising edge to a falling edge of measurement pulse) 1 1 : Do not select. 0 : Counter clear type 1 : Free-run type 0 : No overflow 1 : Overflowed b7 b6 0 0 RW 4 5 6 7 Count-type select bit Timer Bi overflow flag (Note) Count source select bits 0 Undefined 0 0 RW RO RW RW 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 Note: The timer Bi overflow flag is cleared to “0” when a value is written to the timer Bi mode register with the count start bit = “1.” This flag cannot be set to “1” by software. Fig. 8.5.1 Structures of timer Bi register and timer Bi mode register in pulse period/pulse width measurement mode 7 905 Group User ’ s Manual Rev.1.0 8-21 TIMER B 8.5 Pulse period/Pulse width measurement mode 8.5.1 Setting for pulse period/pulse width measurement mode Figure 8.5.2 shows an initial setting example for registers relevant to the pulse period/pulse width measurement mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to “ CHAPTER 6. INTERRUPTS.” Selecting pulse period/pulse width measurement mode and each function b7 b0 10 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) (Note 1) Selection of pulse period/pulse width measurement mode Measurement mode select bits b3 b2 0 0 : Pulse period measurement (Interval between falling edges of measurement pulse) 0 1 : Pulse period measurement (Interval between rising edges of measurement pulse) 1 0 : Pulse width measurement 1 1 : Do not select. Count-type select bit 0: Counter clear type 1: Free-run type Timer Bi overflow flag (Note 2) 0: No overflow 1: Overflowed Count source select bits b7b6 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 Setting interrupt priority level b7 b0 Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A16 to 7C16) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. When a pin is allocated to a port P5 pin (Note 3) Setting port P5 direction register b7 b0 When a pin is allocated to a port P2 pin (Note 3) Setting port P2 direction register b7 b0 Port P5 direction register (Address D16) Pin TB0IN Pin TB1IN Pin TB2IN Clear the coressponding bit to “0.” Port P2 direction register (Address 816) Pin TB0IN Pin TB1IN Pin TB2IN Clear the coressponding bit to “0.” Setting count start bit to “1” b7 b0 Count start register 0 (Address 4016) Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit Count starts. Notes 1: When using timer B2, be sure to clear the timer B2 clock source select bit (See Figure 8.4.2.) to “0.” 2: The timer Bi overflow flag is a read-only bit. This bit is undefined after reset. When a value is written to the timer Bi mode register with the count start bit = “1,” this bit will be cleared to “0.” 3: By using bits 0 to 2 of the port P2 pin function control register (address AE16), be sure to set the pin allocation. (See Figure 8.2.5.) Fig. 8.5.2 Initial setting example for registers relevant to pulse period/pulse width measurement mode 8-22 7 905 Group User ’ s Manual Rev.1.0 TIMER B 8.5 Pulse period/pulse width measurement mode 8.5.2 Operation in pulse period/pulse width measurement mode s W hen counter clear type is selected ➀ W hen the count start bit is set to “ 1, ” t he counter starts counting of the count source. ➁ T he counter value is transferred to the reload register when a valid edge of the measurement pulse is detected. (Refer to section “ (1) Pulse period/Pulse width measurement. ” ) ➂ T he counter value is cleared to “ 0000 16” a fter the transfer in ➁, and the counter continues counting. ➃ The timer Bi interrupt request bit is set to “1” when the counter value is cleared to “000016” in ➂ (Note). The interrupt request bit remains set to “1” until the interrupt request is accepted or until the interrupt request bit is cleared to “ 0 ” b y software. ➄ T he timer repeats operations ➁ t o ➃ a bove. Note: No timer Bi interrupt request occurs when the first valid edge is input after the counter starts counting. s W hen free-run type is selected ➀ W hen the count start bit is set to “ 1, ” t he counter starts counting of the count source. ➁ T he counter value is transferred to the reload register when a valid edge of the measurement pulse is detected. (Refer to section “ (1) Pulse period/Pulse width measurement. ”) ➂ T he timer Bi interrupt request bit is set to “ 1 ” a fter the transfer in ➁ ( Note) . The interrupt request bit remains set to “1” until the interrupt request is accepted or until the interrupt request bit is cleared to “ 0 ” b y software. The counter continues counting w ith the counter value kept. ➃ When a counter overflow occurs, the timer Bi overflow flag is set to “1,” and counting continues after clearing the counter value to “000016 .” At this time, the timer Bi interrupt request bit does not change. ➄ T he timer repeats operations ➁ t o ➃ a bove. Note: No timer Bi interrupt request occurs when the first valid edge is input after the counter starts counting. (1) Pulse period/pulse width measurement The measurement mode select bits (bits 3 and 2 at addresses 5B 16 a nd 5D 16) specify whether the pulse period of an external signal is measured or its pulse width is done. Table 8.5.3 lists the relationship between the measurement mode select bits and the pulse period/pulse width measurements. Make sure that the measurement pulse interval from the falling edge to the rising edge, and vice versa are two cycles of the count source or more. Additionally, use software to identify whether the measurement result indicates the “ H ” l evel width or the “ L ” l evel width. Table 8.5.3 Relationship between measurement mode select bits and pulse period/pulse width measurements b3 0 0 1 b2 0 1 0 Pulse width measurement Pulse period/Pulse width measurement Pulse period measurement Measurement interval (Valid edges) From falling edge to falling edge (Falling edges) From rising edge to rising edge (Rising edges) From falling edge to rising edge, and vice versa (Falling and rising edges) 7 905 Group User ’ s Manual Rev.1.0 8-23 TIMER B 8.5 Pulse period/pulse width measurement mode (2) Timer Bi overflow flag s W hen counter clear type is selected A timer Bi interrupt request occurs when a measurement pulse ’ s valid edge is input or when a counter overflow occurs. The timer Bi overflow flag is used to identify the source of the interrupt request occurrence, that is, whether it is an overflow occurrence or a valid edge input. The timer Bi overflow flag is set to “1” at an overflow occurrence. Accordingly, the source of the interrupt request occurrence is identified by checking the timer Bi overflow flag in the interrupt routine. W hen a value is written to the timer Bi mode register after the next count timing of the count source with the count start bit = “ 1, ” t he timer Bi overflow flag will be cleared to “ 0 ” . The timer Bi overflow flag is a read-only bit. Use the timer Bi interrupt request bit to detect the overflow timing. Do not use the timer Bi overflow flag for this detection. s W hen free-run type is selected The timer Bi overflow flag is set to “1” at an overflow occurrence. (At this time, no timer Bi interrupt request is generated.) Accordingly, whether a counter overflow occurs between valid edges is identified by checking the timer Bi overflow flag in the interrupt routine owing to a valid edge input. When a value is written to the timer Bi mode register after the next count timing of the count source with the count start bit = “ 1, ” t he timer Bi overflow flag will be cleared to “ 0 ” . The timer Bi overflow flag is a read-only bit. Figure 8.5.3 shows the processing example of a timer Bi interrupt when a measurement pulse’s valid edge is detected by the timer Bi interrupt request. Timer Bi interrupt (Note 1) Measured value is read out. (Note 2) Timer Bi overflow flag ? 0 1 Timer Bi overflow flag is cleared to “0.” (Note 3) Processing with overflow Processing without overflow RTI Notes 1: The valid edge of the measurement pulse is detected. 2: Be sure to read out the timer Bi register. 3: After the timer Bi overflow flag is set to “1”, be sure to wait for one cycle of the count source to elapse. Then, write a value to the timer Bi mode register. Fig. 8.5.3 Processing example of timer Bi interrupt when free-run count type is selected 8-24 7 905 Group User ’ s Manual Rev.1.0 TIMER B 8.5 Pulse period/pulse width measurement mode Figures 8.5.4 and 8.5.5 show the operation examples during the pulse period measurement; Figures 8.5.6 and 8.5.7 show the operation examples during the pulse width measurement. Count source Measurement pulse FFFF16 Counter contents (Hex.) Undefined value 000016 Time Transferred (undefined value) Reload register Counter Transfer timing Timing at which counter is cleared to “000016” Transferred (measured value) ➀ ➀ ➁ Count start bit Timer Bi interrupt request bit Cleared to “0” when interrupt request is accepted or cleared to “0” by software. Undefined Timer Bi overflow flag Cleared to “0” by software. ➀ Counter is initialized by completion of measurement. ➁ Counter overflows. ✽The above applies when measurement is performed for an interval from one falling edge to the next falling edge of the measurement pulse. Fig. 8.5.4 Operation examples during pulse period measurement (when counter clear type is selected) 7 905 Group User ’ s Manual Rev.1.0 8-25 TIMER B 8.5 Pulse period/pulse width measurement mode Count source Measurement pulse FFFF16 Counter contents (Hex.) Undefined value 000016 Time Transferred (undefined value) Reload register Counter Transfer timing Timing at which counter is cleared to “000016” Transferred (measured value) ➀ ➁ Count start bit Timer Bi interrupt request bit Undefined Cleared to “0” by software. ➀ Counter is initialized by the first valid edge. ➁ Counter overflows. ✽The above applies when measurement is performed for an interval from one falling edge to the next falling edge of the measurement pulse. Cleared to “0” when interrupt request is accepted or cleared to “0” by software. Fig. 8.5.5 Operation examples during pulse period measurement (when free-run count type is selected) 8-26 7 905 Group User ’ s Manual Rev.1.0 TIMER B 8.5 Pulse period/pulse width measurement mode Count source Measurement pulse FFFF16 Counter contents (Hex.) Undefined value 000016 Time Transferred Transferred Transferred Transferred (undefined value) (measured value) (measured value) (measured value) Reload register Counter Transfer timing ➀ Timing at which counter is cleared to “000016” ➀ ➀ ➀ ➁ Count start bit Timer Bi interrupt request bit Undefined Timer Bi overflow flag Cleared to “0” by software. ➀ Counter is initialized by completion of measurement. ➁ Counter overflows. Cleared to “0” when interrupt request is accepted or cleared to “0” by software. Fig. 8.5.6 Operation example during the pulse width measurement (when counter clear type is selected) 7 905 Group User ’ s Manual Rev.1.0 8-27 TIMER B 8.5 Pulse period/pulse width measurement mode Count source Measurement pulse FFFF16 Counter contents (Hex.) Undefined value 000016 Time Transferred Transferred Transferred Transferred (undefined value) (measured value) (measured value) (measured value) Reload register Counter ➀ ➁ Transfer timing Timing at which counter is cleared to “000016” Count start bit Timer Bi interrupt request bit Undefined Cleared to “0” when interrupt request is accepted or cleared to “0” by software. Timer Bi overflow flag Cleared to “0” by software. ➀ Counter is initialized by the first valid edge. ➁ Counter overflows. Fig. 8.5.7 Operation example during the pulse width measurement (when free-run count type is selected) 8-28 7 905 Group User ’ s Manual Rev.1.0 TIMER B [Precautions for pulse period/pulse width measurement mode] [Precautions for pulse period/pulse width measurement mode] 1. When the counter clear type is selected, a timer Bi interrupt request is generated by one of the following sources: q V alid edge input of measured pulse q C ounter overflow When an overflow generates an interrupt request, the timer Bi overflow flag will be set to “ 1. ” 2. When the free-run type is selected, the timer Bi interrupt request is generated only by the valid edge input of the pulse to be measured. 3. After reset, the timer Bi overflow flag is undefined. When a value is written to the timer Bi mode register after the next count timing of the count source with the count start bit = “ 1, ” t his flag will be cleared to “0.” 4. An undefined value is transferred to the reload register at the first valid edge input after the count start. In this case, no timer Bi interrupt request will occur. 5. The counter value at count start is undefined. Therefore, there is a possibility that a counter overflow occurs immediately after the counting starts. In this case, the timer Bi overflow flag becomes “ 1 ” ; and when the counter clear type is selected, a timer Bi interrupt request is generated. 6. If the contents of the measurement mode select bits are changed after the count start, the timer Bi interrupt request bit is set to “ 1. ” W hen the value, which has been set in these bits before, are written again, the timer Bi interrupt request bit will not change. 7. When using timer B2, be sure to clear the timer B2 clock source select bit (bit 6 at address 63 16) to “0.” 8. If the input signal to the TBiIN pin is affected by noise, etc., there is a possibility that the counter cannot perform the exact measurement. We recommend to verify, by software, that the measurement values are within a constant range. 7 905 Group User ’ s Manual Rev.1.0 8-29 TIMER B [Precautions for pulse period/pulse width measurement mode] MEMORANDUM 8-30 7 905 Group User ’ s Manual Rev.1.0 CHAPTER 9 PULSE OUTPUT PORT MODE 9.1 Overview 9.2 Block description of pulse output port 0 9.3 Block description of pulse output port 1 9.4 Setting of pulse output port mode 9.5 Pulse output port mode operation [Precautions for pulse output port mode] P ULSE OUTPUT PORT MODE 9.1 Overview 9.1 Overview The pulse output port mode function is used to change the output levels at several pins simultaneously with the following: each underflow occurrence in timer A or each valid edge input of an external signal. The pulse output port mode consists of pulse output port 0 and pulse output port 1. These two circuits have the equivalent functions and operate independently each other. Each of pulse output port 0 and pulse output port 1 has two operation modes as listed in Table 9.1.1. Table 9.1.2 lists the overview of pulse output port 0; Table 9.1.3 lists the overview of pulse output port 1. Table 9.1.1 Overview of pulse output port mode Function Circuit Operation mode Pulse output port 0 Pulse mode 0 Pulse mode 1 Pulse output mode Pulse output port 1 Pulse mode 0 Pulse mode 1 Table 9.1.2 Overview of pulse output port 0 Operation mode Pulse output pins Pulse output trigger RTP0 0 t o RTP0 3 (P6 0 t o P6 3) Underflow occurrence in timer A0 or Valid edge of signal input to pin RTP TRG0 Three-phase output data register 0 (bits 0 to 3) Available (timer A1 used) Pulse mode 0 RTP1 0 t o RTP13 (P6 4 t o P6 7) RTP0 0 t o RTP0 3, RTP1 0, RTP11 (P6 0 t o P65) Pulse mode 1 RTP1 2, RTP13 (P6 4, P67) Underflow of timer A3 Underflow of timer A0 Underflow of timer A3 or Valid edge of signal input to pin RTP TRG0 Three-phase output data register 1 (bits 4 to 7) Not available Three-phase output data register 0 (bits 0 to 5) Available (Note) (timers A1, A2, A4 used) Available P6OUTCUT (Input of falling edge) Three-phase output data register 1 (bits 6, 7) Not available Register where output data is to be set Pulse width modulation Not available Available Negative pulse output Available — — Pulse-output- P6OUTCUT cutoff signal (Input of falling edge) input pin Note: The pulse output pins, where pulse width modulation is to be applied, determine the timer to be used. ➀ 6 pins RTP00 to RTP03, RTP10, RTP11: timer A1 ➁ 2 groups of 3 pins • RTP00 to RTP02: timer A1 • RTP03, RTP10, RTP11: timer A2 ➂ 3 groups of 2 pins • RTP00, RTP01: timer A1 • RTP02, RTP03: timer A2 • RTP10, RTP11: timer A4 9-2 7905 Group User’s Manual Rev.1.0 P ULSE OUTPUT PORT MODE 9.1 Overview Table 9.1.3 Overview of pulse output port 1 Operation mode Pulse output pins Pulse output trigger RTP2 0 t o RTP2 3 (P4 0 t o P4 3) Underflow occurrence in timer A5 or Valid edge of signal input to pin RTP TRG1 Pulse output data register 0 (bits 0 to 3) Available (timer A6 used) Pulse mode 0 RTP3 0 t o RTP3 3 (P4 4 t o P47) Underflow of timer A8 Pulse mode 1 RTP3 2, RTP33 RTP2 0 t o RTP2 3, (P46, P47) RTP3 0, RTP31 (P4 0 t o P4 5) Underflow of timer A5 Underflow of timer A8 or Valid edge of signal input to pin RTP TRG1 Pulse output data register 1 (bits 6, 7) Not available Pulse output data Pulse output data register 0 register 1 (bits 0 to 5) (bits 4 to 7) Not available Available (Note) (timers A6, A7, A9 used) Available Available Negative pulse output Available — Pulse-output- P4OUTCUT P4OUTCUT cutoff signal (Input of falling edge) (Input of falling edge) input pin Register where output data is to be set Pulse width modulation Not available — Note: The pulse output pins, where pulse width modulation is to be applied, determine the timer to be used. ➀ 6 pins RTP20 to RTP23, RTP30, RTP31: timer A6 ➁ 2 groups of 3 pins • RTP20 to RTP22: timer A6 • RTP23, RTP30, RTP31: timer A7 ➂ 3 groups of 2 pins • RTP20, RTP21: timer A6 • RTP22, RTP23: timer A7 • RTP30, RTP31: timer A9 7905 Group User’s Manual Rev.1.0 9-3 P ULSE OUTPUT PORT MODE 9.2 Block description of pulse output port 0 9.2 Block description of pulse output port 0 Figure 9.2.1 shows the block diagram of pulse output port 0. Also, the pulse-output-port-0-relevant registers are described below. In pulse output port 0 and three-phase waveform mode, the following registers are used in common: the waveform output mode register (address A616), three-phase output data register 0 (address A816), and threephase output data register 1 (address A9 16). After pulse output port 0 is set by the waveform output select bits (bits 2 to 0 at address A6 16), be sure to set the relevant registers. Note that, when not using pulse output port 0 and three-phase waveform mode, be sure to fix the waveform output select bits (bits 2 to 0 at address A6 16) to “000 2.” Pulse width modulation timer select bits (bits 5, 4 at address A616) Pulse width modulation output of timer A1 Pulse output trigger select bits (bits 7, 6 at address A816) Pulse width modulation output of timer A2 Pulse width modulation output of timer A4 Pulse width modulation circuit RTP TRG0 Timer A0 Pulse width modulation enable bits 0 through 2 (bits 0 through 2 at address A916) b0 b1 b2 Bits 0 through 3 of threephase output data register 0 (address A816) b0 Data bus (even-numbered) b1 Data bus (odd-numbered) b2 Pulse output mode select bit (bit 3 at address A616) b3 T DQ DQ DQ P6OUTCUT Reset T DQ DQ DQ DQ RTP0 0 RTP0 1 RTP0 2 RTP0 3 Waveform output control bit 1 (bit 7 at address A616) DQ R b4 b5 T DQ DQ RTP1 0 RTP1 1 Bits 4, 5 of three-phase output data register 0 (address A816) or Bits 4, 5 of three-phase output data register 1 (address A916) DQ b6 b7 Bits 6, 7 of three-phase output data register 1 (address A916) Timer 3 Reset DQ T Pulse output polarity select bit (bit 3 at address A916) Waveform output control bit 0 (bit 6 at address A616) DQ R RTP1 2 RTP1 3 Fig. 9.2.1 Block diagram of pulse output port 0 9-4 7905 Group User’s Manual Rev.1.0 P ULSE OUTPUT PORT MODE 9.2 Block description of pulse output port 0 9.2.1 Waveform output mode register Figure 9.2.2 shows the structure of the waveform output mode register (pulse output port 0). b7 b6 b5 b4 b3 b2 b1 b0 Waveform output mode register (Address A616) Bit 0 1 2 3 4 5 6 Pulse output mode select bit Pulse width modulation timer select bits Waveform output control bit 0 0 : Pulse mode 0 1 : Pulse mode 1 See Table 9.2.2. When pulse mode 0 is selected, 0: RTP10 to RTP13: pulse outputs are disabled. 1: RTP10 to RTP13: pulse outputs are enabled. When pulse mode 1 is selected, 0: RTP12, RTP13: pulse outputs are disabled. 1: RTP12, RTP13: pulse outputs are enabled. When pulse mode 0 is selected, 0 : RTP00 to RTP03: pulse outputs are disabled. 1 : RTP00 to RTP03: pulse outputs are enabled. When pulse mode 1 is selected, 0 : RTP00 to RTP03, RTP10, RTP11: pulse outputs are disabled. 1 : RTP00 to RTP03 RTP10, RTP11: pulse outputs are enabled. Bit name Waveform output select bits (Note) See Table 9.2.1. Function At reset 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW 7 Waveform output control bit 1 0 RW Note: When not using pulse output port 0 and three-phase waveform mode, be sure to fix these bits to “0002.” Fig. 9.2.2 Structure of waveform output mode register (pulse output port 0) 7905 Group User ’ s Manual Rev.1.0 9-5 P ULSE OUTPUT PORT MODE 9.2 Block description of pulse output port 0 (1) Waveform output select bits (bits 2 to 0) These bits are used to select whether a pin serves as a programmable I/O port pin or a pulse output pin. Table 9.2.1 lists the functions of the waveform output select bits. Table 9.2.1 Functions of waveform output select bits b2 b1 b0 Pulse mode 0 (Note) 000 P67/RTP13 P66/RTP12 Port P65/RTP11 P64/RTP10 P6 3/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 Pulse mode 1 (Note) P67/RTP1 3 P6 6/RTP12 P65/RTP1 1 P64/RTP1 0 P63/RTP0 3 P62/RTP0 2 P61/RTP0 1 P60/RTP0 0 001 P6 7/RTP13 P6 6/RTP12 Port P6 5/RTP11 P6 4/RTP10 P6 3/RTP03 P6 2/RTP02 P6 1/RTP01 P6 0/RTP00 P6 7/RTP13 P66/RTP1 2 P6 5/RTP11 P6 4/RTP10 P6 3/RTP03 P6 2/RTP02 P6 1/RTP01 P6 0/RTP00 010 P6 7/RTP13 P6 6/RTP12 RTP P6 5/RTP11 P6 4/RTP10 P6 3/RTP03 P6 2/RTP02 P6 1/RTP01 P6 0/RTP00 P6 7/RTP13 P6 6/RTP1 2 P6 5/RTP11 P6 4/RTP10 P6 3/RTP03 P6 2/RTP02 P6 1/RTP01 P6 0/RTP00 011 P6 7/RTP13 P6 6/RTP12 RTP P6 5/RTP11 P6 4/RTP10 P6 3/RTP03 P6 2/RTP02 P6 1/RTP01 P6 0/RTP00 P67/RTP1 3 P6 6/RTP12 P65/RTP1 1 P64/RTP1 0 P63/RTP0 3 P62/RTP0 2 P61/RTP0 1 P60/RTP0 0 RTP Port RTP Port Port Port Port RTP Port RTP Port RTP Port: This serves as a programmable I/O port pin or timer I/O pin. RTP: This serves as a pulse output pin regardless of the contents of the corresponding port direction register. Note: This is selected by the pulse output mode select bit (bit 3 at address A616). (2) Pulse output mode select bit (bit 3) This bit is used to select the operation mode of pulse output port 0: pulse mode 0 or pulse mode 1. (3) Pulse width modulation timer select bits (bits 5 and 4) These bits are used to select the type of the pulse width modulation of pulse output port 0. Table 9.2.2 lists the functions of the pulse width modulation timer select bits. Table 9.2.2 Functions of pulse width modulation timer select bits b5 b4 10 01 00 Pulse mode 0 P63/RTP03 P62/RTP02 (Note 1) Do not select. Timer A1 Do not select. P61/RTP01 P60/RTP00 Pulse mode 1 (Note 2) P6 5/RTP1 1 P6 4/RTP1 0 P6 3/RTP0 3 Timer A1 P6 2/RTP0 2 P6 1/RTP0 1 P6 0/RTP0 0 P6 5/RTP1 1 P6 4/RTP1 0 Timer A2 P6 3/RTP0 3 P6 2/RTP0 2 P6 1/RTP0 1 Timer A1 P6 0/RTP0 0 P65/RTP1 1 P64/RTP1 0 Timer A4 P63/RTP0 3 Timer A2 P62/RTP0 2 P61/RTP0 1 Timer A1 P60/RTP0 0 Do not select. 11 Do not select. Note 1: The pulse width modulation cannot be applied to pins RTP10 to RTP13. 2: The pulse width modulation cannot be applied to pins RTP12 and RTP13. 9-6 7905 Group User ’ s Manual Rev.1.0 P ULSE OUTPUT PORT MODE 9.2 Block description of pulse output port 0 (4) Waveform output control bits 1, 0 (bits 7, 6) These bits are used to control the waveform output of pulse output port 0. Table 9.2.3 lists the functions of waveform output control bits 1, 0. When a falling edge is input to pin P6OUTCUT, waveform output control bit 1 (bit 7) becomes “0.” (See Table 9.2.7.) Table 9.2.3 Functions of waveform output control bits 1, 0 b2 b1 b0 Pulse mode 0 001 000 P6 7/RTP13 P67/RTP13 P66/RTP12 Floating P6 6/RTP12 Pulse P6 5/RTP11 output P65/RTP11 state enabled P6 4/RTP10 P64/RTP10 P6 3/RTP03 P62/RTP02 P61/RTP01 P60/RTP00 Pulse mode 1 P6 7/RTP13 P66/RTP12 P6 5/RTP11 P6 4/RTP10 P6 3/RTP03 P6 2/RTP02 P6 1/RTP01 P6 0/RTP00 P6 3/RTP03 Floating P6 2/RTP02 state P6 1/RTP01 P6 0/RTP00 Floating P67/RTP13 state P6 6/RTP12 P65/RTP11 P64/RTP10 Floating P63/RTP03 state P62/RTP02 P61/RTP01 P60/RTP00 010 011 P67/RTP13 P6 7/RTP13 Pulse P66/RTP12 Floating P6 6/RTP12 output P65/RTP11 state P6 5/RTP11 enabled P64/RTP10 P6 4/RTP10 P6 3/RTP03 Pulse P6 2/RTP02 output enabled P6 1/RTP01 P6 0/RTP00 Floating P6 7/RTP1 3 state P66/RTP12 P6 5/RTP1 1 P6 4/RTP1 0 Pulse P6 3/RTP0 3 output enabled P6 2/RTP0 2 P6 1/RTP0 1 P6 0/RTP0 0 Pulse output enabled Pulse output enabled Pulse output enabled P63/RTP03 Floating P62/RTP02 state P61/RTP01 P60/RTP00 Pulse P67/RTP13 output P6 6/RTP12 enabled P65/RTP11 P64/RTP10 Floating P63/RTP03 state P62/RTP02 P61/RTP01 P60/RTP00 7905 Group User ’ s Manual Rev.1.0 9-7 P ULSE OUTPUT PORT MODE 9.2 Block description of pulse output port 0 9.2.2 Three-phase output data registers 0, 1 Figure 9.2.3 shows the structures of three-phase output data registers 0, 1 (pulse output port 0). b7 b6 b5 b4 b3 b2 b1 b0 Three-phase output data register 0 (Address A816) Bit 0 1 2 3 4 5 7, 6 Bit name RTP00 pulse output data bit RTP01 pulse output data bit RTP02 pulse output data bit RTP03 pulse output data bit RTP10 pulse output data bit (Valid in pulse mode 1.) (Note) RTP11 pulse output data bit (Valid in pulse mode 1.) (Note) Pulse output trigger select bits b7 b6 Function 0 : “L” level output 1 : “H” level output At reset 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW 0 0 : Underflow of timer A0 0 1 : Falling edge of input signal to pin RTPTRG0 1 0 : Rising edge of input signal to pin RTPTRG0 1 1 : Both falling and rising edges of input signal to pin RTPTRG0 0 Note: Invalid in pulse mode 0. b7 b6 b5 b4 b3 b2 b1 b0 Three-phase output data register 1 (Address A916) Bit 0 1 2 3 4 5 6 7 Bit name Pulse width modulation enable bit 0 Pulse width modulation enable bit 1 Pulse width modulation enable bit 2 Pulse output polarity select bit RTP10 pulse output data bit (Valid in pulse mode 0) (Note) RTP11 pulse output data bit (Valid in pulse mode 0) (Note) RTP12 pulse output data bit RTP13 pulse output data bit Function 0 : No pulse width modulation by timer A1 1 : Pulse width modulation by timer A1 0 : No pulse width modulation by timer A2 1 : Pulse width modulation by timer A2 0 : No pulse width modulation by timer A4 1 : Pulse width modulation by timer A4 0 : Positive 1 : Negative 0 : “L” level output 1 : “H” level output At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Note: Invalid in pulse mode 1. Fig. 9.2.3 Structures of three-phase output data registers 0, 1 (pulse output port 0) 9-8 7905 Group User ’ s Manual Rev.1.0 P ULSE OUTPUT PORT MODE 9.2 Block description of pulse output port 0 (1) RTP0 0 t o RTP0 3 p ulse output data bits (bits 0 to 3 at address A8 16) Each time when a pulse output trigger is generated, the contents written to these bits are output from the corresponding pulse output pins ( Note). T he pulse output trigger can be selected by the pulse output trigger select bits (bits 7, 6 at address A8 16). (2) RTP1 0, RTP11 p ulse output data bits (bits 4, 5 at address A816) These bits are valid in pulse mode 1. Each time when a pulse output trigger is generated, the contents written to these bits are output from the corresponding pulse output pins ( Note). T he pulse output trigger can be selected by the pulse output trigger select bits (bits 7, 6 at address A8 16). These bits are invalid in pulse mode 0. (3) Pulse output trigger select bits (bits 7, 6 at address A816) The pulse output trigger can be selected from an internal trigger and an external trigger. When using an external trigger (input signal to pin RTPTRG0), be sure to clear the port P5 direction register ’ s bit, corresponding to port P5 3 p in, in order to set this port P5 3 p in for the input mode. (4) Pulse width modulation enable bits 0 to 2 (bits 0 to 2 at Address A916) These bits are used to select the pins, where the pulse width modulation is to be applied. Synchronous with a pulse output trigger, the contents of these bits become valid. Table 9.2.4 lists the pulse-widthmodulation-relevant bits. (5) Pulse output polarity select bit (bit 3 at address A916) When this bit = “ 0, ” t he data corresponding to the contents which have been set in the RTP0 0 t o RTP03, RTP10 to RTP13 pulse output data bits are output from pins RTP00 to RTP03, RTP10 to RTP13. When this bit = “1,” the contents which have been set in the RTP0 0 to RTP03, RTP1 0 to RTP1 3 pulse output data bits are reversed (in other words, pulses with the negative polarity are generated here.); and then, these pulses with the negative polarity are output from pins RTP0 0 t o RTP0 3 , RTP1 0 t o RTP13. Note that, in pulse mode 1, the pulses with the negative polarity are not output from pins RTP12 and RTP13. (6) RTP1 0, RTP11 p ulse output data bits (bits 4, 5 at address A916) These bits are valid in pulse mode 0. Each time when an underflow occurs in timer A3, the contents which have been written to these bits are output from the corresponding pulse output pins ( Note) . These bits are invalid in pulse mode 1. (7) RTP1 2, RTP13 p ulse output data bits (bits 6, 7 at address A916) Each time when an underflow occurs in timer A3, the contents which have been written to these bits are output from the corresponding pulse output pins (Note). Note: T he output level at a pulse output pin is undefined in the period from when data is written to these bits until the first occurrence of a pulse output trigger. If it is necessary to avoid this state, perform “Processing of avoiding undefined output before starting pulse output” in Figure 9.4.2. 7905 Group User ’ s Manual Rev.1.0 9-9 P ULSE OUTPUT PORT MODE 9.2 Block description of pulse output port 0 Table 9.2.4 Pulse-width-modulation-relevant bits Pulse output pins where pulse width modulation is to be applied (Timers used for pulse width modulation) RTP0 3 t o RTP0 0 Pulse 4 pins (Timer A1) mode 0 RTP11, RTP10, 6 pins RTP0 3 t o RTP0 0 (Timer A1) RTP11, RTP10, In a RTP03 unit of (Timer A2) Pulse 3 pins mode 1 RTP0 2 t o RTP0 0 (Timer A1) RTP1 1, RTP10 (Timer A4) In a RTP0 3, RTP02 unit of (Timer A2) 2 pins RTP0 1, RTP00 (Timer A1) X: It may be either “0” or “1.” Pulse width moduPulse width modu- Pulse width modu- Pulse width modulation timer select bits lation enable bit 2 lation enable bit 1 lation enable bit 0 (bits 5, 4 at (bit 2 at address A916) (bit 1 at address A916) (bit 0 at address A916) address A616) 00 ✕ ✕ 1 00 ✕ ✕ 1 ✕ 01 ✕ 1 10 ✕ ✕ 1 ✕ ✕ ✕ 1 ✕ 1 ✕ ✕ 1 9-10 7905 Group User ’ s Manual Rev.1.0 P ULSE OUTPUT PORT MODE 9.2 Block description of pulse output port 0 9.2.3 Port P5 direction register The pulse output trigger input pin is multiplexed with port P53 pin. When using pin P5 3/RTP TRG0 a s a pulse output trigger input pin, be sure to clear the port P5 direction register ’ s bit, corresponding to port P5 3 p in, in order to set this port P5 3 p in for the input mode. Figure 9.2.4 shows the relationship between port P5 direction register and a pulse output trigger input pin. b7 b6 b5 b4 b3 b2 b1 b0 Port P5 direcition register (Address D16) Bit 0 1 2 3 4 5 6 7 Corresponding pin Nothing is assigned. Pin INT1 Pin INT2/RTPTRG1 Pin RTPTRG0 (Pin INT3) Nothing is assigned. Pin INT5/TB0IN/IDW Pin INT6/TB1IN/IDV Pin INT7/TB2IN/IDU 0 : Input mode 1 : Output mode 0 : Input mode 1 : Output mode When using this pin as a pulse output trigger input pin, be sure to clear the corresponding bit to “0.” Function At reset Undefined 0 0 0 Undefined 0 0 0 R/W — RW RW RW — RW RW RW Note: ( ) shows the I/O pin of another internal peripheral device which is multiplexed. Fig. 9.2.4 Relationship between port P5 direction register and pulse output trigger input pin 7905 Group User ’ s Manual Rev.1.0 9-11 P ULSE OUTPUT PORT MODE 9.2 Block description of pulse output port 0 9.2.4 Timers A0 to A4 Timers A0 and A3 are used as control registers; each generates a pulse output trigger. When using timers A0 and A3, be sure to use them in the timer mode. (Refer to section “ 7.3 Timer mode.” ) When performing the pulse width modulation, be sure to use timers A1, A2, A4 in the pulse width modulation mode. (Refer to section “7.6 Pulse width modulation (PWM) mode.”) Note that, from pin P2 0/TA4 OUT, a PWM pulse by timer A4 is output. When it is unnecessary to output a PWM pulse, be sure to clear bit 2 of the timer A4 mode register (address 5A 16) to “0.” At this time, pin P2 0 can be used as a programmable I/O port pin. Figure 9.2.5 shows the structure of the timer A0 and A3 mode registers (pulse output port 0); Figure 9.2.6 shows the structures of the timer A1, A2, A4 mode registers (pulse output port 0 with pulse width modulation used). Timer A0 mode register (Address 5616) Timer A3 mode register (Address 5916) Bit 0 1 2 3 4 5 6 7 Count source select bits See Table 7.2.3. Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 000000 At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Fix these bits to “0000002” in the pulse output port mode. Fig. 9.2.5 Structure of timer A0 and A3 mode registers (pulse output port 0) 9-12 7905 Group User ’ s Manual Rev.1.0 P ULSE OUTPUT PORT MODE 9.2 Block description of pulse output port 0 Timer A1 mode register (Address 5716) Timer A2 mode register (Address 5816) Bit 0 1 2 3 4 5 6 7 16/8-bit PWM mode select bit Count source select bits 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator See Table 7.2.3. Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 00011 At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Fix these bits to “000112” in the pulse output port mode. b7 b6 b5 b4 b3 b2 b1 b0 Timer A4 mode register (Address 5A16) Bit 0 1 2 Pulse output function select bit 0 : No pulse output (TA4OUT pin functions as a programmable I/O port pin.) 1 : Pulse output (TA4OUT pin functions as a PWM pulse output pin.) Bit name Fix these bits to “112” in the pulse output port mode. Functions 00 At reset 0 0 0 11 R/W RW RW RW 3 4 5 6 7 Fix these bits to “002” in the pulse output port mode. 0 0 RW RW RW RW RW 16/8-bit PWM mode select bit Count source select bits 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator See Table 7.2.3. 0 0 0 Fig. 9.2.6 Structures of timer A1, A2, A4 mode registers (pulse output port 0 with pulse width modulation used) 7905 Group User ’ s Manual Rev.1.0 9-13 P ULSE OUTPUT PORT MODE 9.2 Block description of pulse output port 0 9.2.5 Pin P6OUTCUT ( pulse-output-cutoff signal input pin) When a falling edge is input to pin P6OUT CUT, the waveform output control bit 1 (bit 7 at address A6 16) becomes “ 0 ” a nd the pulse output pins enter the floating state. (In other words, pulse output becomes disabled.) The pulse output pins where pulse output is to be inactive depend on the pulse output mode. • P ulse mode 0: RTP00 t o RTP0 3 • P ulse mode 1: RTP0 0 t o RTP0 3, RTP10, RTP1 1 When restarting pulse output after the pulse output becomes inactive, be sure to return the input level at pin P6OUTCUT to “H” level; and then, be sure to set the waveform output control bit 1 to “1.” When the input level at pin P6OUT CUT i s “ L ” l evel, the waveform output control bit 1 cannot be “ 1. ” Also, at this time, bits 0 through 7 of the port P6 direction register (address 10 16) become “ 000000002. ” (Refer to section “5.2.4 Pin P6OUTCUT/INT4.”) Therefore, if it is necessary to switch port pins P6 0 through P6 7 t o port output pins, be sure to do as follows: ➀ R eturn the input level at pin P6OUT CUT t o “ H ” l evel. ➁ W rite data to the port P6 register (address E 16) ’ s bits, corresponding to the port P6 pins which will output data. ➂ Set the port P6 direction register’s bits, corresponding to the port P6 pins in ➁, to “1” in order to set these port pins to the output mode. When the input level at pin P6OUT CUT i s “ L ” l evel, no bit of the port P6 direction register can be “ 1. ” Figure 9.2.7 shows the relationship between the P6OUTCUT input, waveform output control bit 1, and pulse output pin. Note that, when not making the pulse output inactive by using pin P6OUT CUT , be sure to connect pin P6OUT CUT t o Vcc via a resistor. Selection of pulse output port mode (selected by bit s 3 to 0 at address A616) ➀ P6OUTCUT input ➁ ➁ ➂ Waveform output control bit 1 (bit 7 at address A616) Pulse output pin Programmable I/O port Floating Pulse output Floating Pulse output ➀ When the pulse output port mode is selected, the pulse outpit pins become floating. ➁ The pulse is output by writing of “1” with the input level at pin P6OUTCUT = “H.” ➂ When a falling edge is input to pin P6OUTCUT, this bit becomes “0.” Fig. 9.2.7 Relationship between P6OUTCUT input, waveform output control bit 1, and pulse output pin 9-14 7905 Group User ’ s Manual Rev.1.0 P ULSE OUTPUT PORT MODE 9.3 Block description of pulse output port 1 9.3 Block description of pulse output port 1 Figure 9.3.1 shows the block diagram of pulse output port 1. Also, the pulse-output-port-1-relevant registers are described below. After pulse output port 1 is set by the waveform output select bits (bits 2 to 0 at address A016), be sure to set the relevant registers. Note that, when not using pulse output port 1, be sure to fix the waveform output select bits (bits 2 to 0 at address A0 16) to “ 000 2. ” Pulse width modulation timer select bits (bits 5, 4 at address A016) Pulse width modulation output of timer A6 Pulse output trigger select bits Pulse width modulation (bits 7, 6 at address A216) output of timer A7 Pulse width modulation output of timer A9 Pulse width modulation circuit RTP TRG1 Timer A5 Pulse width modulation enable bits 0 through 2 (bits 0 through 2 at address A416) b0 b1 b2 Bits 0 through 3 of pulse output data register 0 (address A216) b0 b1 b2 Pulse output mode select bit (bit 3 at address A016) b3 T DQ DQ DQ P4OUTCUT Reset T DQ DQ DQ DQ RTP2 0 RTP2 1 RTP2 2 RTP2 3 Waveform output control bit 1 (bit 7 at address A016) DQ R Data bus (even-numbered) b4 b5 T DQ DQ RTP3 0 RTP3 1 Bits 4, 5 of pulse output data register 0 (address A216) or Bits 4, 5 of pulse output data register 1 (address A416) DQ b6 b7 Bits 6, 7 of pluse output data register 1 (address A416) Timer 8 Reset DQ T Pulse output polarity select bit (bit 3 at address A416) Waveform output control bit 0 (bit 6 at address A016) DQ R RTP3 2 RTP3 3 Fig. 9.3.1 Block diagram of pulse output port 1 7905 Group User ’ s Manual Rev.1.0 9-15 P ULSE OUTPUT PORT MODE 9.3 Block description of pulse output port 1 9.3.1 Pluse output control register Figure 9.3.2 shows the structure of the pluse output control register. b7 b6 b5 b4 b3 b2 b1 b0 Pluse output control register (Address A016) Bit 0 1 2 3 4 5 6 Pulse output mode select bit Pulse width modulation timer select bits Waveform output control bit 0 0 : Pulse mode 0 1 : Pulse mode 1 See Table 9.3.2. When pulse mode 0 is selected, 0: RTP30 to RTP33: pulse outputs are disabled. 1: RTP30 to RTP33: pulse outputs are enabled. When pulse mode 1 is selected, 0: RTP32, RTP33: pulse outputs are disabled. 1: RTP32, RTP33: pulse outputs are enabled. When pulse mode 0 is selected, 0 : RTP20 to RTP23: pulse outputs are disabled. 1 : RTP20 to RTP23: pulse outputs are enabled. When pulse mode 1 is selected, 0 : RTP20 to RTP23, RTP30, RTP31: pulse outputs are disabled. 1 : RTP20 to RTP23 RTP30, RTP31: pulse outputs are enabled. Bit name Waveform output select bits (Note) See Table 9.3.1. Function At reset 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW 7 Waveform output control bit 1 0 RW Note: When not using pulse output port 1, be sure to fix these bits to “0002.” Fig. 9.3.2 Structure of pluse output control register 9-16 7905 Group User ’ s Manual Rev.1.0 P ULSE OUTPUT PORT MODE 9.3 Block description of pulse output port 1 (1) Waveform output select bits (bits 2 to 0) These bits are used to select whether a pin serves as a programmable I/O port pin or a pulse output pin. Table 9.3.1 lists the functions of the waveform output select bits. Table 9.3.1 Functions of waveform output select bits b2 b1 b0 Pulse mode 0 (Note) 000 P4 7/RTP3 3 P4 6/RTP3 2 Port P4 5/RTP3 1 P4 4/RTP3 0 P43/RTP23 P4 2/RTP2 2 P4 1/RTP2 1 P4 0/RTP2 0 Pulse mode 1 (Note) P4 7/RTP33 P46/RTP3 2 P4 5/RTP31 P4 4/RTP30 P4 3/RTP23 P4 2/RTP22 P4 1/RTP21 P4 0/RTP20 001 P47/RTP33 P46/RTP32 Port P45/RTP31 P44/RTP30 P43/RTP23 P42/RTP22 P41/RTP21 P40/RTP20 P47/RTP33 P4 6/RTP32 P45/RTP31 P44/RTP30 P43/RTP23 P42/RTP22 P41/RTP21 P40/RTP20 010 P47/RTP3 3 P46/RTP3 2 RTP P45/RTP3 1 P44/RTP3 0 P43/RTP2 3 P42/RTP2 2 P41/RTP2 1 P40/RTP2 0 P47/RTP3 3 P4 6/RTP32 P45/RTP3 1 P44/RTP3 0 P43/RTP2 3 P42/RTP2 2 P41/RTP2 1 P40/RTP2 0 011 P47/RTP33 P46/RTP32 RTP P45/RTP31 P44/RTP30 P43/RTP23 P42/RTP22 P41/RTP21 P40/RTP20 P4 7/RTP33 P46/RTP3 2 P4 5/RTP31 P4 4/RTP30 P4 3/RTP23 P4 2/RTP22 P4 1/RTP21 P4 0/RTP20 RTP Port RTP Port Port Port RTP RTP Port RTP Port RTP Port: This serves as a programmable I/O port pin or timer I/O pin. RTP: This serves as a pulse output pin regardless of the contents of the corresponding port direction register. Note: This is selected by the pulse output mode select bit (bit 3 at address A016). (2) Pulse output mode select bit (bit 3) This bit is used to select the operation mode of pulse output port 1: pulse mode 0 or pulse mode 1. (3) Pulse width modulation timer select bits (bits 5 and 4) These bits are used to select the type of the pulse width modulation of pulse output port 1. Table 9.3.2 lists the functions of the pulse width modulation timer select bits. Table 9.3.2 Functions of pulse width modulation timer select bits b5 b4 Pulse mode 0 (Note 1) 00 P4 3/RTP2 3 P4 2/RTP2 2 Timer A6 P4 1/RTP2 1 P4 0/RTP2 0 P4 5/RTP31 P4 4/RTP30 P4 3/RTP23 Timer A6 P4 2/RTP22 P4 1/RTP21 P4 0/RTP20 01 Do not select. 10 Do not select. 11 Do not select. Pulse mode 1 (Note 2) P4 5/RTP31 P4 4/RTP30 Timer A7 P4 3/RTP23 P4 2/RTP22 P4 1/RTP21 Timer A6 P4 0/RTP20 P4 5/RTP31 P4 4/RTP30 Timer A9 P4 3/RTP23 Timer A7 P4 2/RTP22 P4 1/RTP21 Timer A6 P4 0/RTP20 Do not select. Note 1: The pulse width modulation cannot be applied to pins RTP30 to RTP33. 2: The pulse width modulation cannot be applied to pins RTP32 and RTP33. 7905 Group User ’ s Manual Rev.1.0 9-17 P ULSE OUTPUT PORT MODE 9.3 Block description of pulse output port 1 (4) Waveform output control bits 1, 0 (bits 7, 6) These bits are used to control the waveform output of pulse output port 1. Table 9.3.3 lists the functions of waveform output control bits 1, 0. When a falling edge is input to pin P4OUTCUT, waveform output control bit 1 (bit 7) becomes “0.” (See Table 9.3.7.) Table 9.3.3 Functions of waveform output control bits 1, 0 b2 b1 b0 Pulse mode 0 01 00 P4 7/RTP33 P47/RTP33 P46/RTP32 Floating P4 6/RTP32 Pulse P4 5/RTP31 output P45/RTP31 state enabled P4 4/RTP30 P44/RTP30 P4 3/RTP23 P42/RTP22 P41/RTP21 P40/RTP20 Pulse mode 1 P4 7/RTP3 3 P46/RTP32 P4 5/RTP3 1 P4 4/RTP3 0 P4 3/RTP2 3 P4 2/RTP2 2 P4 1/RTP2 1 P4 0/RTP2 0 P4 3/RTP23 Floating P4 2/RTP22 state P4 1/RTP21 P4 0/RTP20 Floating P4 7/RTP33 state P4 6/RTP3 2 P4 5/RTP31 P4 4/RTP30 Floating P4 3/RTP23 state P4 2/RTP22 P4 1/RTP21 P4 0/RTP20 10 11 P47/RTP33 P4 7/RTP33 Pulse P46/RTP32 Floating P4 6/RTP32 output P45/RTP31 state P4 5/RTP31 enabled P44/RTP30 P4 4/RTP30 P4 3/RTP23 Pulse P4 2/RTP22 output enabled P4 1/RTP21 P4 0/RTP20 Floating P4 7/RTP3 3 state P46/RTP32 P4 5/RTP3 1 P4 4/RTP3 0 Pulse P4 3/RTP2 3 output enabled P4 2/RTP2 2 P4 1/RTP2 1 P4 0/RTP2 0 Pulse output enabled Pulse output enabled Pulse output enabled P43/RTP23 Floating P42/RTP22 state P41/RTP21 P40/RTP20 Pulse P47/RTP33 output enabled P4 6/RTP32 P45/RTP31 P44/RTP30 Floating P43/RTP23 state P42/RTP22 P41/RTP21 P40/RTP20 9-18 7905 Group User ’ s Manual Rev.1.0 P ULSE OUTPUT PORT MODE 9.3 Block description of pulse output port 1 9.3.2 Pulse output data registers 0, 1 Figure 9.3.3 shows the structures of pulse output data registers 0, 1. b7 b6 b5 b4 b3 b2 b1 b0 Pulse output data register 0 (Address A216) Bit 0 1 2 3 4 5 7, 6 Bit name RTP20 pulse output data bit RTP21 pulse output data bit RTP22 pulse output data bit RTP23 pulse output data bit RTP30 pulse output data bit (Valid in pulse mode 1.) (Note) RTP31 pulse output data bit (Valid in pulse mode 1.) (Note) Pulse output trigger select bits b7 b6 Function 0 : “L” level output 1 : “H” level output At reset 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW 0 0 : Underflow of timer A5 0 1 : Falling edge of input signal to pin RTPTRG1 1 0 : Rising edge of input signal to pin RTPTRG1 1 1 : Both falling and rising edges of input signal to pin RTPTRG1 0 Note: Invalid in pulse mode 0. b7 b6 b5 b4 b3 b2 b1 b0 Pulse output data register 1 (Address A416) Bit 0 1 2 3 4 5 6 7 Bit name Pulse width modulation enable bit 0 Pulse width modulation enable bit 1 Pulse width modulation enable bit 2 Pulse output polarity select bit RTP30 pulse output data bit (Valid in pulse mode 0) (Note) RTP31 pulse output data bit (Valid in pulse mode 0) (Note) RTP32 pulse output data bit RTP33 pulse output data bit Function 0 : No pulse width modulation by timer A6 1 : Pulse width modulation by timer A6 0 : No pulse width modulation by timer A7 1 : Pulse width modulation by timer A7 0 : No pulse width modulation by timer A9 1 : Pulse width modulation by timer A9 0 : Positive 1 : Negative 0 : “L” level output 1 : “H” level output At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Note: Invalid in pulse mode 1. Fig. 9.3.3 Structures of pulse output data registers 0, 1 7905 Group User ’ s Manual Rev.1.0 9-19 P ULSE OUTPUT PORT MODE 9.3 Block description of pulse output port 1 (1) RTP2 0 t o RTP2 3 p ulse output data bits (bits 0 to 3 at address A2 16) Each time when a pulse output trigger is generated, the contents written to these bits are output from the corresponding pulse output pins ( Note). T he pulse output trigger can be selected by the pulse output trigger select bits (bits 7, 6 at address A2 16). (2) RTP3 0, RTP3 1 p ulse output data bits (bits 4, 5 at address A2 16) These bits are valid in pulse mode 1. Each time when a pulse output trigger is generated, the contents written to these bits are output from the corresponding pulse output pins ( Note). T he pulse output trigger can be selected by the pulse output trigger select bits (bits 7, 6 at address A2 16). These bits are invalid in pulse mode 0. (3) Pulse output trigger select bits (bits 7, 6 at address A2 16) The pulse output trigger can be selected from an internal trigger and an external trigger. When using an external trigger (input signal to pin RTP TRG1), be sure to clear the port P5 direction register ’ s bit, corresponding to port P5 2 p in, in order to set this port P5 2 p in for the input mode. (4) Pulse width modulation enable bits 0 to 2 (bits 0 to 2 at Address A416) These bits are used to select the pins, where the pulse width modulation is to be applied. Synchronous with a pulse output trigger, the contents of these bits become valid. Table 9.3.4 lists the pulse-widthmodulation-relevant bits. (5) Pulse output polarity select bit (bit 3 at address A4 16) When this bit = “ 0, ” t he data corresponding to the contents which have been set in the RTP2 0 t o RTP23, RTP30 to RTP33 pulse output data bits are output from pins RTP20 to RTP23, RTP30 to RTP33. When this bit = “1,” the contents which have been set in the RTP2 0 to RTP23, RTP30 to RTP3 3 pulse output data bits are reversed (in other words, pulses with the negative polarity are generated here.); and then, these pulses with the negative polarity are output from pins RTP2 0 t o RTP2 3, RTP3 0 t o RTP33. Note that, in pulse mode 1, the pulses with the negative polarity are not output from pins RTP32 and RTP33. (6) RTP3 0, RTP3 1 p ulse output data bits (bits 4, 5 at address A4 16) These bits are valid in pulse mode 0. Each time when an underflow occurs in timer A8, the contents which have been written to these bits are output from the corresponding pulse output pins ( Note) . These bits are invalid in pulse mode 1. (7) RTP3 2, RTP3 3 p ulse output data bits (bits 6, 7 at address A4 16) Each time when an underflow occurs in timer A8, the contents which have been written to these bits are output from the corresponding pulse output pins (Note). Note: T he output level at a pulse output pin is undefined in the period from when data is written to these bits until the first occurrence of a pulse output trigger. If it is necessary to avoid this state, perform “Processing of avoiding undefined output before starting pulse output” in Figure 9.4.2. 9-20 7905 Group User ’ s Manual Rev.1.0 P ULSE OUTPUT PORT MODE 9.3 Block description of pulse output port 1 Table 9.3.4 Pulse-width-modulation-relevant bits Pulse output pins where pulse width modulation is to be applied (Timers used for pulse width modulation) RTP2 3 t o RTP20 Pulse 4 pins (Timer A6) mode 0 RTP3 1, RTP30, 6 pins RTP2 3 t o RTP20 (Timer A6) RTP3 1, RTP30, In a RTP23 unit of (Timer A7) Pulse 3 pins mode 1 RTP2 2 t o RTP20 (Timer A6) RTP3 1, RTP30 (Timer A9) In a RTP2 3, RTP22 unit of (Timer A7) 2 pins RTP2 1, RTP20 (Timer A6) X: It may be either “0” or “1.” Pulse width moduPulse width modu- Pulse width modu- Pulse width modulation timer select bits lation enable bit 2 lation enable bit 1 lation enable bit 0 (bits 5, 4 at (bit 2 at address A416) (bit 1 at address A416) (bit 0 at address A416) address A016) 00 ✕ ✕ 1 00 ✕ ✕ 1 ✕ 01 ✕ 1 10 ✕ ✕ 1 ✕ ✕ ✕ 1 ✕ 1 ✕ ✕ 1 7905 Group User ’ s Manual Rev.1.0 9-21 P ULSE OUTPUT PORT MODE 9.3 Block description of pulse output port 1 9.3.3 Port P5 direction register The pulse output trigger input pin is multiplexed with port P52 pin. When using pin P5 2/RTP TRG1 a s a pulse output trigger input pin, be sure to clear the port P5 direction register ’ s bit, corresponding to port P5 2 p in, in order to set this port P5 2 p in for the input mode. Figure 9.3.4 shows the relationship between port P5 direction register and a pulse output trigger input pin. b7 b6 b5 b4 b3 b2 b1 b0 Port P5 direcition register (Address D16) Bit 0 1 2 3 4 5 6 7 Corresponding pin Nothing is assigned. Pin INT1 Pin RTPTRG1 (Pin INT2) Pin INT3/RTPTRG0 Nothing is assigned. Pin INT5/TB0IN/IDW Pin INT6/TB1IN/IDV Pin INT7/TB2IN/IDU 0 : Input mode 1 : Output mode 0 : Input mode 1 : Output mode When using this pin as a pulse output trigger input pin, be sure to clear the corresponding bit to “0.” Function At reset Undefined 0 0 0 Undefined 0 0 0 R/W — RW RW RW — RW RW RW Note: ( ) shows the I/O pin of another internal peripheral device which is multiplexed. Fig. 9.3.4 Relationship between port P5 direction register and pulse output trigger input pin 9-22 7905 Group User ’ s Manual Rev.1.0 P ULSE OUTPUT PORT MODE 9.3 Block description of pulse output port 1 9.3.4 Timers A5 to A9 Timers A5 and A8 are used as control registers; each generates a pulse output trigger. When using timers A5 and A8, be sure to use them in the timer mode. (Refer to section “ 7.3 Timer mode.” ) When performing the pulse width modulation, be sure to use timers A6, A7, A9 in the pulse width modulation mode. (Refer to section “7.6 Pulse width modulation (PWM) mode.”) Note that, from pin P2 2/TA9 OUT, a PWM pulse by timer A9 is output. When it is unnecessary to output a PWM pulse, be sure to clear bit 2 of the timer A9 mode register (address DA16) to “0.” At this time, pin P2 2 can be used as a programmable I/O port pin. Figure 9.3.5 shows the structure of the timer A5 and A8 mode registers (pulse output port 1); Figure 9.3.6 shows the structures of the timer A6, A7, A9 mode registers (pulse output port 1 with pulse width modulation used). Timer A5 mode register (Address D616) Timer A8 mode register (Address D916) Bit 0 1 2 3 4 5 6 7 Count source select bits See Table 7.2.3. Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 000000 At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Fix these bits to “0000002” in the pulse output port mode. Fig. 9.3.5 Structure of timer A5 and A8 mode registers (pulse output port 1) 7905 Group User ’ s Manual Rev.1.0 9-23 P ULSE OUTPUT PORT MODE 9.3 Block description of pulse output port 1 Timer A6 mode register (Address D716) Timer A7 mode register (Address D816) Bit 0 1 2 3 4 5 6 7 16/8-bit PWM mode select bit Count source select bits 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator See Table 7.2.3. Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 00011 At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Fix these bits to “000112” in the pulse output port mode. b7 b6 b5 b4 b3 b2 b1 b0 Timer A9 mode register (Address DA16) Bit 0 1 2 Pulse output function select bit 0 : No pulse output (TA9OUT pin functions as a programmable I/O port pin.) 1 : Pulse output (TA9OUT pin functions as a PWM pulse output pin.) Bit name Fix these bits to “112” in the pulse output port mode. Functions 00 At reset 0 0 0 11 R/W RW RW RW 3 4 5 6 7 Fix these bits to “002” in the pulse output port mode. 0 0 RW RW RW RW RW 16/8-bit PWM mode select bit Count source select bits 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator See Table 7.2.3. 0 0 0 Fig. 9.3.6 Structures of timer A6, A7, A9 mode registers (pulse output port 1 with pulse width modulation used) 9-24 7905 Group User ’ s Manual Rev.1.0 P ULSE OUTPUT PORT MODE 9.3 Block description of pulse output port 1 9.3.5 Pin P4OUTCUT ( pulse-output-cutoff signal input pin) When a falling edge is input to pin P4OUT CUT, the waveform output control bit 1 (bit 7 at address A0 16) becomes “ 0 ” a nd the pulse output pins enter the floating state. (In other words, pulse output becomes disabled.) The pulse output pins where pulse output is to be inactive depend on the pulse output mode. • P ulse mode 0: RTP20 t o RTP2 3 • P ulse mode 1: RTP2 0 t o RTP2 3, RTP3 0, RTP3 1 When restarting pulse output after the pulse output becomes inactive, be sure to return the input level at pin P4OUTCUT to “H” level; and then, be sure to set the waveform output control bit 1 to “1.” When the input level at pin P4OUT CUT i s “ L ” l evel, the waveform output control bit 1 cannot be “ 1. ” Also, at this time, bits 0 through 7 of the port P4 direction register (address C 16) become “ 00000000 2. ” (Refer to section “5.2.3 Pin P4OUTCUT/INT0.”) Therefore, if it is necessary to switch port pins P6 0 through P6 7 t o port output pins, be sure to do as follows: ➀ R eturn the input level at pin P4OUT CUT t o “ H ” l evel. ➁ W rite data to the port P4 register (address A 16) ’ s bits, corresponding to the port P4 pins which will output data. ➂ Set the port P4 direction register’s bits, corresponding to the port P4 pins in ➁, to “1” in order to set these port pins to the output mode. When the input level at pin P4OUT CUT i s “ L ” l evel, no bit of the port P4 direction register can be “ 1. ” Figure 9.3.7 shows the relationship between the P4OUTCUT input, waveform output control bit 1, and pulse output pin. Note that, when not making the pulse output inactive by using pin P4OUT CUT , be sure to connect pin P4OUT CUT t o Vcc via a resistor. Selection of pulse output port mode (selected by bit s 3 to 0 at address A016) ➀ P4OUTCUT input ➁ ➁ ➂ Waveform output control bit 1 (bit 7 at address A016) Pulse output pin Programmable I/O port Floating Pulse output Floating Pulse output ➀ When the pulse output port mode is selected, the pulse outpit pins become floating. ➁ The pulse is output by writing of “1” with the input level at pin P4OUTCUT = “H.” ➂ When a falling edge is input to pin P4OUTCUT, this bit becomes “0.” Fig. 9.3.7 Relationship between P4OUTCUT input, waveform output control bit 1, and pulse output pin 7905 Group User ’ s Manual Rev.1.0 9-25 P ULSE OUTPUT PORT MODE 9.4 Setting of pulse output port mode 9.4 Setting of pulse output port mode Figures 9.4.1 to 9.4.5 show an initial setting example for registers relevant to the pulse output port mode, where pins RTP0 0 to RTP03, RTP1 0, RTP1 1 are used as pulse output pins and an underflow of timer A0 is used as a pulse output trigger (pulse mode 1 of pulse output port 0). Note that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 6. INTERRUPTS.” The above setting example is also applied to the case of pulse output port 1. Each right side of Figures 9.4.1 to 9.4.5 shows registers used in pulse output port 1. Registers used in pulse output port 1 Selecting pulse output mode and Selecting each function b7 b0 0 0 10 0 1 Waveform output mode register (Address A616) Pulse mode 1 Pulse width modulation timer select bits See Table 9.2.2. Waveform output control bit 0 RTP12, RTP13: pulse output is disabled. Waveform output control bit 1 Pulse output is disabled. Pulse output control register (Address A016) ✽ Pulse output pins are floating until the pulse output becomes enabled. Continued on Figure 9.4.2. Fig. 9.4.1 Initial setting example for registers relevant to pulse output port 0 (pulse mode 1) (1) 9-26 7905 Group User’s Manual Rev.1.0 P ULSE OUTPUT PORT MODE 9.4 Setting of pulse output port mode Continued from preceding Figure 9.4.1. Registers used in pulse output port 1 Processing of avoiding undefined output before starting pulse output (Note) b7 b0 0 0 Three-phase output data register 0 (Address A816) RTP0 0 RTP01 RTP02 RTP03 RTP10 RTP11 Pulse output trigger select bits Underflow of Timer A0 Pulse output data register 0 (Address A216) Initial output data is set. b7 b0 ✕✕✕✕ Three-phase output data register 1 (Address A916) Pulse width modulation enable bit 0 Pulse width modulation enable bit 1 Pulse width modulation enable bit 2 Pulse output polarity select bit 0 : Positive 1 : Negative b0 Pulse output data register 1 (Address A416) See Table 9.2.3. X : It may be either “0” or “1.” b7 00 0 0 0 0 0 0 Timer A0 mode register (Address 5616) Selection of count source f2 Timer A5 mode register (Address D16) (b15) b7 (b8) b0 b7 b0 0016 0016 Timer A0 register (Addresses 4716 and 4616) Timer A5 register (Addresses C716, C616) A value of “000016” is set. b7 b0 0 0 0 0 Timer A0 interrupt control register (Address 7516) Interrupt disabled No interrupt request Timer A5 interrupt control register (Address F516) b7 b0 Count start register 0 (Address 4016) Timer A0 count start bit 1 : Start counting When an underflow occurs in timer A0, the contents of three-phase output data register 0 are output from the filp-flop. (Pulse output pins are floating until the pulse output becomes enabled.) b7 b0 Count start register 1 (Address 4116) Count start register 0 (Address 4016) Timer A0 count start bit 0 : Stop counting This processing can be omitted when the system is not affected by the undefined output. Count start register 1 (Address 4116) Continued on Figure 9.4.3. Fig. 9.4.2 Initial setting example for registers relevant to pulse output port 0 (pulse mode 1) (2) 7905 Group User ’ s Manual Rev.1.0 9-27 P ULSE OUTPUT PORT MODE 9.4 Setting of pulse output port mode Continued from preceding Figure 9.4.2. Registers used in pulse output port 1 Selecting pulse output data, pulse output mode, pulse width modulation b7 b0 0 0 Three-phase output data register 0 (Address A816) RTP00 RTP01 RTP02 RTP03 RTP10 RTP11 Pulse output data register 0 (Address A216) The output data is set. Pulse output trigger select bits Underflow of Timer A0 b7 b0 ✕✕✕✕ Three-phase output data register 1 (Address A916) Pulse width modulation enable bit 0 Pulse width modulation enable bit 1 Pulse width modulation enable bit 2 Pulse output polarity select bit 0 : Positive 1 : Negative Pulse output data register 1 (Address A416) See Table 9.2.3. X : It may be either “0” or “1.” Setting of timer A0 b7 b0 0 0 0 0 0 0 Timer A0 mode register (Address 5616) Count source select bits See Table 7.2.3. Timer A5 mode register (Address D616) (b15) b7 (b8) b0 b7 b0 0016 0016 Timer A0 register (Addresses 4716 and 4616) A value in the range from “000016” to “FFFF16” (n) is set. Timer A5 register (Addresses C716, C616) b7 b0 0 Timer A0 interrupt control register (Address 7516) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. No interrupt request Timer A5 interrupt control register (Address F516) Continued on Figure 9.4.4. Fig. 9.4.3 Initial setting example for registers relevant to pulse output port 0 (pulse mode 1) (3) 9-28 7905 Group User ’ s Manual Rev.1.0 P ULSE OUTPUT PORT MODE 9.4 Setting of pulse output port mode Continued from preceding Figure 9.4.3. When pulse width modulation is not performed When pulse width modulation is performed b7 b0 Registers used in pulse output port 1 00 11 Timer Aj mode register (j = 1, 2, 4) (Addresses 5716, 5816, 5A16) j = 1, 2 : Fix this bit to “0. j = 4 : When not using pin TA4OUT (in other words, when using pin P20 as a programmable I/O port pin), clear this bit to “0.” 16/8-bit PWM mode select bit 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator Count source select bit See Table 7.2.3. Timer Ak mode register (k = 6, 7, 9) (Addresses D716, D816, DA16) Setting of PWM pulse period and “H” level width s When 16-bit pulse width modulator (b15) b7 (b8) b0 b7 b0 Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A4 register (Addresses 4F16, 4E16) Timer A6 register (Addresses C916, C816) Timer A7 register (Addresses CB16, CA16) Timer A9 register (Addresses CF16, CE16) A value in the range from “000016” to “FFFE16 ” (n) is set. s When 8-bit pulse width modulator (b15) b7 (b8) b0 b7 b0 Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A4 register (Addresses 4F16, 4E16) Timer A6 register (Addresses C916, C816) Timer A7 register (Addresses CB16, CA16) Timer A9 register (Addresses CF16, CE16) A value in the range from “0016” to “FF16” (m) is set. A value in the range from “0016” to “FE16” (n) is set. ✽ When operating as 8-bit pulse width modulator Period = (m + 1)(2 – 1) fi “H” level width = n (m + 1) fi fi : Frequency of count source However, if n = “0016,” the pulse width modulator does not operate and pin TAjOUT pin outputs “L” level. At this time, no timer Aj interrupt request occurs. 8 ✽ When operating as 16-bit pulse width modulator 16 Period = 2 – 1 fi “H” level width = n fi fi : Frequency of count source However, if n = “000016,” the pulse width modulator does not operate and pin TAjOUT pin outputs “L” level. At this time, no timer Aj interrupt request occurs. Continued on Figure 9.4.5. Fig. 9.4.4 Initial setting example for registers relevant to pulse output port 0 (pulse mode 1) (4) 7905 Group User ’ s Manual Rev.1.0 9-29 P ULSE OUTPUT PORT MODE 9.4 Setting of pulse output port mode Continued from preceding Figure 9.4.4. Registers used in pulse output port 1 Enabling pulse output b7 b0 1 Waveform output mode register (Address A616) Waveform output control bit 1 Pulse output is enabled. Pulse output control register (Address A016) ✽ When pulse output becomes enabled, the initial output data is output from pulse output pins. Setting count start bit to “1.” b7 b0 Count start register 0 (Address 4016) Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Count start register 1 (Address 4116) Pulse output starts after an underflow of timer A0. Fig. 9.4.5 Initial setting example for registers relevant to pulse output port 0 (pulse mode 1) (5) 9-30 7905 Group User ’ s Manual Rev.1.0 P ULSE OUTPUT PORT MODE 9.5 Pulse output port mode operation 9.5 Pulse output port mode operation The operation of pulse output port 0 is described below and is also applied to the operation of pulse output port 1. 9.5.1 Pulse output trigger (1) RTP0 0 t o RTP0 3 i n pulse mode 0; RTP0 0 t o RTP0 3, RTP1 0, RTP1 1 i n pulse mode 1 The pulse output trigger can be selected from an internal trigger and an external trigger. When the pulse output trigger select bits (bits 7, 6 at address A8 16) = “ 00 2 , ” a n internal trigger is selected; when these bits = “ 01 2, ” “ 102, ” o r “ 112, ” a n external trigger is selected. s I nternal trigger A trigger occurs at an underflow of timer A0. This trigger occurrence can be confirmed by using the timer A0 interrupt request bit. s E xternal trigger A trigger occurs at a valid edge input to pin RTPTRG0 (Note) . This trigger occurrence can be confirmed by using the INT3 interrupt request bit. Table 9.5.1 lists the setting of INT3 according to valid edges. When using pin P53/RTPTRG0 as an input pin for an external trigger, be sure to clear the port P5 direction register ’s bit, corresponding to port P53 pin, in order to set the port P53 pin to the input mode. Note: T his is set by the pulse output trigger select bits (bits 7, 6 at address A8 16). Table 9.5.1 Setting of INT3 a ccording to valid edges Valid edge input to pin RTP TRG0 Falling Rising Falling and Rising Setting of INT 3 ( Note) Falling (edge sense) Rising (edge sense) Falling and Rising (edge sense): used alternately Note: Refer to section “6.10 External interrupts.” (2) RTP1 0 t o RTP1 3 i n pulse mode 0; RTP1 2, RTP1 3 i n pulse mode 1 The pulse output trigger is an internal trigger. A trigger occurs at an underflow of timer A3. This trigger occurrences can be confirmed by using the timer A3 interrupt request bit. 7905 Group User ’ s Manual Rev.1.0 9-31 P ULSE OUTPUT PORT MODE 9.5 Pulse output port mode operation 9.5.2 Operation at internal trigger ➀ W hen the timer Ai (i = 0, 3) count start bit is set to “ 1, ” t he counter starts counting of a count source. ➁ The contents of the pulse output data bits of three-phase output data registers 0, 1 are output from the corresponding pulse output pins at each underflow of timer Ai. While the pulse width modulation is selected, the pulse width modulation is performed for “ H ” l evel output. The timer reloads the contents of the reload register and continues counting. ➂ T he timer Ai interrupt request bit is set to “ 1 ” w hen the counter underflows in ➁ . The interrupt request bit retains “ 1 ” u ntil the interrupt request is accepted or it is cleared to “ 0 ” b y software. ➃ Write the next output data into three-phase output data registers 0, 1 during a timer Ai interrupt routine (or after the confirmation of a timer Ai interrupt request occurrence.) Figures 9.5.1 to 9.5.3 show examples of pulse output port mode operations. n : Reloaded value Timer A0’s counter contents (Hex.) FFFF16 ✽1 Starts counting n Starts pulse outputting 000016 ✽1 ✽1 ✽1 ✽1 ✽1 Contents of bits 3 to 0 of three-phase output data register 0 RTP00 output 00112 01102 11002 10012 Undefined ✽2 RTP01 output Undefined ✽2 RTP02 output Undefined ✽2 RTP03 output Timer A0 interrupt request bit Undefined ✽2 ✽3 ✽3 ✽3 ✽3 ✽1 : Written by software ✽2 : When avoiding undefined output in these terms (in other words, when stabilizing these output level), be sure to follow the procedure “Processing of avoiding undefined output before starting pulse output” in Figure 9.4.2. ✽3 : Cleared to “0” by an interrupt request acceptance or cleared by software. The above applies when the following conditions are satisfied: • Pulse mode 0 selected • RTP00 to RTP03 selected • No pulse width modulation • Positive polarity Fig. 9.5.1 Example of pulse output port mode operation (1) 9-32 7905 Group User ’ s Manual Rev.1.0 P ULSE OUTPUT PORT MODE 9.5 Pulse output port mode operation n : Reloaded value Timer A0’s counter contents (Hex.) FFFF16 ✽1 Starts counting n Starts pulse outputting 000016 ✽1 ✽1 ✽1 ✽1 ✽1 Contents of bits 3 to 0 of three-phase output data register 0 RTP00 output 00112 01102 11002 10012 Undefined ✽2 RTP01 output Undefined ✽2 Undefined ✽2 RTP02 output RTP03 output Timer A0 interrupt request bit Undefined ✽2 ✽3 ✽3 ✽3 ✽3 ✽1 : Written by software ✽2 : When avoiding undefined output in these terms (in other words, when stabilizing these output level), be sure to follow the procedure “Processing of avoiding undefined output before starting pulse output” in Figure 9.4.2. ✽3 : Cleared to “0” by an interrupt request acceptance or cleared by software. The above applies when the following conditions are satisfied: • Pulse mode 0 selected • RTP00 to RTP03 selected • No pulse width modulation • Negative polarity Fig. 9.5.2 Example of pulse output port mode operation (2) 7905 Group User ’ s Manual Rev.1.0 9-33 P ULSE OUTPUT PORT MODE 9.5 Pulse output port mode operation n : Reloaded value Timer A0’s counter contents (Hex.) FFFF16 ✽1 Starts counting n Starts pulse outputting 000016 Contents of bits 5 to 0 of three-phase output data register 0 PWM signal by timer A1 PWM signal by timer A2 PWM signal by timer A4 RTP00 output Undefined ✽2 Undefined ✽2 Undefined ✽2 Undefined ✽2 Undefined ✽2 Undefined ✽2 ✽3 ✽3 ✽3 ✽3 ✽1 ✽1 ✽1 ✽1 ✽1 0011002 0110002 1100002 1000012 RTP01 output RTP02 output RTP03 output RTP10 output RTP11 output Timer A0 interrupt request bit ✽1 : Written by software ✽2 : When avoiding undefined output in these terms (in other words, when stabilizing these output level), be sure to follow the procedure “Processing of avoiding undefined output before starting pulse output” in Figure 9.4.2. ✽3 : Cleared to “0” by an interrupt request acceptance or cleared by software. The above applies when the following conditions are satisfied: • Pulse mode 1 selected • Pulse width modulation applied (in a unit of 2 pins; timers A1, A2, and A4 are used.) • Positive polarity Fig. 9.5.3 Example of pulse output port mode operation (3) 9-34 7905 Group User ’ s Manual Rev.1.0 P ULSE OUTPUT PORT MODE 9.5 Pulse output port mode operation 9.5.3 Operation at external trigger ➀ Each time when a valid edge of a signal input to pin RTP TRG0 (Note) is input, the contents of the pulse output data bits of three-phase output data register 0 are output from the corresponding pulse output pins. When the pulse width modulation is selected, the pulse width modulation is applied to “ H ” l evel output. ➁ The INT3 interrupt request bit is set to “1” when a valid edge (➀) is input. (Refer to section “9.5.1 Pulse output trigger. ” ) The interrupt request bit retains “ 1 ” u ntil the interrupt request is accepted or it is cleared by software. ➂ W rite the next output data into three-phase output data register 0 during an INT 3 i nterrupt routine (or after the confirmation of an INT3 i nterrupt request occurrence). Note: T his is set by the pulse output trigger select bits (bits 7, 6 at address A8 16). 7905 Group User ’ s Manual Rev.1.0 9-35 P ULSE OUTPUT PORT MODE [Precautions for pulse output port mode] [Precautions for pulse output port mode] 1. When using pulse output port 0, be sure to set the relevant registers after setting the waveform output select bits (bits 2 to 0 at address A616). When not using pulse output port 0 and three-phase waveform mode, be sure to fix the waveform output select bits (bits 2 to 0 at address A616) to “0002.” 2. When using pulse output port 1, be sure to set the relevant registers after setting the waveform output select bits (bits 2 to 0 at address A016). When not using pulse output port 1, be sure to fix the waveform output select bits (bits 2 to 0 at address A016) to “0002.” 3. When performing the pulse width modulation in pulse output port 0, be sure to use timers A1, A2, A4 in the pulse width modulation mode. (Refer to section “7.6 Pulse width modulation (PWM) mode.”) Note that, from pin P20/ TA4OUT, a PWM pulse by timer A4 is output. When it is unnecessary to output a PWM pulse, be sure to clear bit 2 of the timer A4 mode register (address 5A16) to “0.” At this time, pin P20 can be used as a programmable I/O port pin. 4. When performing the pulse width modulation in pulse output port 1, be sure to use timers A6, A7, A9 in the pulse width modulation mode. (Refer to section “7.6 Pulse width modulation (PWM) mode.”) Note that, from pin P22/ TA9OUT, a PWM pulse by timer A9 is output. When it is unnecessary to output a PWM pulse, be sure to clear bit 2 of the timer A9 mode register (address DA16) to “0.” At this time, pin P22 can be used as a programmable I/O port pin. 5. Note that, when not making the pulse output inactive by input of a falling edge to pin P6OUTCUT or P4OUTCUT, be sure to connect pin P6OUTCUT or P4OUTCUT to Vcc via a resistor. 9-36 7905 Group User ’ s Manual Rev.1.0 CHAPTER 10 THREE-PHASE WAVEFORM MODE 10.1 Overview 10.2 Block description 10.3 Three-phase mode 0 10.4 Three-phase mode 1 10.5 Three-phase waveform output fixation 10.6 Position-data-retain function [Precautions for three-phase waveform mode] THREE-PHASE WAVEFORM MODE 10.1 Overview 10.1 Overview The three-phase waveform mode serves as follows: three-phase waveforms (3 positive waveforms and 3 negative waveforms) are output from the three-phase waveform output pins. The three-phase waveform mode consists of “three-phase mode 0” and “three-phase mode 1.” Table 10.1.1 lists the specifications of the three-phase waveform mode, Table 10.1.2 lists the comparison of operations in three-phase mode 0 and 1, and Figure 10.1.1 shows the comparison of waveforms in threephase mode 0 and 1. Table 10.1.1 Specifications of three-phase waveform mode Item 6 pins (U, U, V, V, W, W) Three-phase-waveform-output- P6OUTCUT (Input of falling edge) forcibly-cutoff signal input pin Operation modes Three-phase mode 0 A timer A3 interrupt request occurs at each timer A3 underflow. Three-phase mode 1 A timer A3 interrupt request occurs at each second timer A3 underflow or forth one. Timer to be used Timers A0 through A2 (Used in the one-shot pulse mode) • Timer A0 : W- and W-phase waveform control • Timer A1 : V- and V-phase waveform control • Timer A2 : U- and U-phase waveform control Timer A3 (Used in the timer mode) • Output period control Three-phase waveform period Output waveform and Output width 1 f1 to 1 f 4096 ✕ 65536 1 f1 1 f1 to 1 f4096 ✕ 65535 (Note) 1 ✕ 65535 ✕ 2 (Note) f 4096 Three-phase waveform output pins Specifications Saw-tooth-wave modulation output Triangular wave modulation output Fixed level output ✕ 2 to Each of the U, V, W phases is fixed to an arbitrary level. Each of the U, V, W phases is fixed to the reversed level of the corresponding positive phase (the U, V, W phases). Dead time (width) Dead-time timer is used. See Table 10.2.1. Note: T his value does not include the dead time. Table 10.1.2 Comparison of operations in three-phase mode 0 and 1 Three-phase mode 0 Timer A3 interrupt request Each timer A3 underflow occurrence interval Timers A0 through A2 Output polarity Each timer uses one register. Three-phase mode 1 Each second timer A3 underflow or forth one is selected by software. Each timer uses two registers alternately. • By software, the output polarity can be set to the • By software, the output polarity can be set output polarity set buffer of the U, V, or W phases. to the three-phase output polarity set buffer. • If necessary, the contents of each output • At each period, the contents of the threepolarity set buffer are reversed by software. phase output polarity set buffer are reversed by hardware. 10-2 7905 Group User’s Manual Rev.1.0 T HREE-PHASE WAVEFORM MODE 10.1 Overview Timer A3 underflow signal Three-phase mode 0 : Saw-tooth-wave modulation Timer A3 interrupt request signal Timer A2 one-shot pulse output Phase U Phase U By software at each timer A3 interrupt, • Data is written to timer A2. Three-phase mode 0 : Triangular wave modulation Timer A3 interrupt request signal Timer A2 one-shot pulse output Phase U Phase U By software at each timer A3 interrupt, • Waveform output polarity is reversed. • Data is written to timer A2. Three-phase mode 1 : Triangular wave modulation Timer A3 interrupt request signal Timer A2 one-shot pulse output Contets of timer A2 register Contets of timer A21 register Contets of timer A2 register Contets of timer A21 register Phase U Phase U By software at each timer A3 interrupt, • Data is written to timer A2 register. • Data is written to timer A21 register. Waveform output polarity is reversed by hardware. Note: This applies when a timer A3 interrupt request occurs at each second timer A3 underflow. Fig. 10.1.1 Comparison of waveforms in three-phase mode 0 and 1 7905 Group User’s Manual Rev.1.0 10-3 Data bus (even-numbered) Figure 10.2.1 shows the block diagram of the three-phase waveform mode, and explanation of registers relevant to the three-phase waveform mode is described below. The following registers are common to pulse output port 0 and three-phase waveform mode: • W aveform output mode register (address A6 16) • T hree-phase output data register 0 (address A8 16) • T hree-phase output data register 1 (address A9 16) When using the three-phase waveform mode, be sure to fix the waveform output select bits (bits 2 through 0 at address A6 16) to “ 100 2, ” a nd then, set the relevant registers. When not using pulse output port 0 and three-phase waveform mode, be sure to fix the waveform output select bits (bits 2 through 0 at address A6 16) to “ 0002. ” 10-4 Interrupt request interval set bit (bit 4 at address A916) DQ Reset R Interval control circuit “1” Interrupt validity output select bit (bit 5 at address A916) Timer A3 interrupt request signal “0” DQ R DQ Reset Clock-source-of-dead-time-timer select bits (bits 7, 6 at address A816) DQ P6OUTCUT Reset T Dead-time timer (8) U R 1/2 1/2 f8 f4 Reload register Waveform output control bit (bit 7 at address A616) 10.2 Block description Three-phase output polarity set buffer (bit 3 at address A616) TR Timer A3 (16) f2 10.2 Block description (Timer mode) Timer A2 DQ T U Reload Timer A21 T Timer A2 counter (16) (One-shot pulse mode) DQ T Dead-time timer (8) T Trigger generating circuit U-phase output fix bit (bit 2 at address DQ A816) T U-phase U-phase output fix polarity set bit output control (bit 2 at address DQ circuit A916) U-phase output polarity set buffer (bit 5 at address A916) DQ “0” Output polarity set toggle flip-flop 2 SQ T RQ “1” Timer A1 DQ T Reload Timer A11 V T Timer A1 counter (16) (One-shot pulse mode) Output polarity set toggle flip-flop 1 Trigger generating circuit V-phase output fix bit (bit 1 at address A816) DQ T V-phase V-phase output fix polarity set bit output (bit 1 at address D Q control A916) circuit “0” Fig. 10.2.1 Block diagram of three-phase waveform mode SQ T RQ DQ Trigger generating circuit V-phase output polarity set buffer (bit 4 at address A916) T Dead-time timer (8) T DQ V THREE-PHASE WAVEFORM MODE “1” 7905 Group User ’ s Manual Rev.1.0 W-phase output fix bit (bit 0 at address A816) DQ T W-phase output fix polarity set bit (bit 0 at address D Q A916) W-phase output control circuit DQ T W DQ T T b2 T b1 T b0 QD IDW QD IDV Bits 2 through 0 of positiondata-retain function control register (address AA16) QD IDU Q D Three-phase mode select bit R (bit 4 at address A616) W Output polarity set toggle flip-flop 0 Timer A0 Reload Timer A01 T Timer A0 counter (16) (One-shot pulse mode) “0” W-phase output polarity set buffer (bit 3 at address A816) DQ SQ T RQ “1” Reset T HREE-PHASE WAVEFORM MODE 10.2 Block description 10.2.1 Waveform output mode register Figure 10.2.2 shows the structure of the waveform output mode register (the three-phase waveform mode). Note that writing to bits 0 through 6 of this register must be performed when the counting in timers A0 through A3 is halts. b7 b6 b5 b4 b3 b2 b1 b0 Waveform output mode register (Address A616) Bit 0 1 2 3 4 5 6 Three-phase output polarity set buffer 0 : “H” output (Valid in three-phase mode 1) (Note 2) 1 : “L” output Three-phase mode select bit 0 : Three-phase mode 0 1 : Three-phase mode 1 Bit name Waveform output select bits (Note 1) b2 b1 b0 X Function 100 At reset 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW 1 0 0 : Three-phase waveform mode Invalid in the three-phase waveform mode. Dead-time timer trigger select bit (Note 3) 0: Both falling and rising edges of one-shot pulse for timers A0 to A2 1: Only the falling edge of one-shot pulse for timers A0 to A2 0 : Waveform output disabled 1 : Waveform output enabled 7 Waveform output control bit 0 RW X: It may be either “0” or “1.” Notes 1: When not using pulse output port 0 and three-phase waveform mode, be sure to fix these bits to “0002.” 2: This bit is invalid in three-phase mode 0. 3: When the saw-tooth-wave modulation output is performed, be sure to fix this bit to “0.” 4: Writing to any of bits 0 to 6 must be performed while counting for timers A0 to A3 halts. Fig. 10.2.2 Structure of waveform output mode register (three-phase waveform mode) 7905 Group User ’ s Manual Rev.1.0 10-5 THREE-PHASE WAVEFORM MODE 10.2 Block description (1) Three-phase output polarity set buffer (bit 3) This bit serves as the buffer to set the output polarity of the three-phase waveform and is used in three-phase mode 1. (Refer to section “ 10.2.9 Output polarity set toggle flip-flop.”) (2) Three-phase mode select bit (bit 4) This bit is used to select three-phase mode 0 or 1. (3) Dead-time timer trigger select bit (bit 6) This bit is used to select a trigger of the dead-time timer. The saw-tooth-wave modulation requires that this bit is fixed to “ 0. ” (4) Waveform output control bit (bit 7) Setting of this bit to “1” allows the three-phase waveform output from the three-phase waveform output pins. Clearance of this bit to “ 0 ” m akes the three-phase waveform output pins floating. When a falling edge is input to pin P6OUT CUT, this bit becomes “ 0. ” ( See Figure 10.2.15.) 10-6 7905 Group User ’ s Manual Rev.1.0 T HREE-PHASE WAVEFORM MODE 10.2 Block description 10.2.2 Dead-time timer register Figure 10.2.3 shows the structure of the Dead-time timer register. b7 b0 Dead-time timer (Address A716) Bit 7 to 0 Function A value in the range from “0016” to “FF16” can be set. At reset Undefined R/W WO Note: Use the MOVMB (MOVM when m = 1) or STAB (STA when m = 1) instruction for writing to this register. Additionally, make sure writing to this register does not overlap with a trigger-occurrence timing of the dead-time timer. Fig. 10.2.3 Structure of dead-time timer register The dead-time timer is used to count the time to prevent “ L ” l evel of positive waveform outputs from overlapping with “ L ” l evel of their negative waveform outputs. (This time is referred to as “ dead time. ” ) Figure 10.2.4 shows the structure of the dead-time timer. Dead-time timer register (Address A716) Dead-time timer reload register Clock-source-of-dead-time-timer select bits (Bits 7, 6 at address A816) f2 (Common to 3 dead-time timers) Timer A2 Trigger Dead-time timer 1/2 1/2 Timer A1 Trigger Dead-time timer Timer A0 Trigger Dead-time timer Fig. 10.2.4 Structure of dead-time timer 7905 Group User ’ s Manual Rev.1.0 10-7 THREE-PHASE WAVEFORM MODE 10.2 Block description When a certain value is written to the dead-time timer register, this value is written to the dead-time reload register. The M37905 has three dead-time timers, and they are independent each other. When a trigger is generated due to each of timers A0 through A2, the contents of the dead-time timer reload register are reloaded; and then, the selected count source is counted down. Simultaneously, the one-shot pulse is output. A trigger is selected by the dead-time timer trigger select bit (bit 6 at address A6 16), and the count source is selected by the clock-source-of-dead-time-timer select bits (bits 7, 6 at address A8 16). When an underflow occurs, the counting becomes inactive. Figure 10.2.5 shows the relationship between the dead-time timer ’ s pulse and trigger, and Table 10.2.1 lists the pulse width of the dead-time timer. s When dead-time timer trigger select bit = “0” Timer Ai’s one-shot pulse Internal signal Dead-time timer ’s pulse (Reversed signal) s When dead-time timer trigger select bit = “1” Timer Ai’s one-shot pulse Internal signal Dead-time timer ’s pulse (Reversed signal) s When re-triggering Timer Ai’s one-shot pulse Internal signal Dead-time timer ’s pulse (Reversed signal) Re-trigger Re-trigger Fig. 10.2.5 Relationship between dead-time timer’s pulse and trigger Table 10.2.1 Pulse width of dead-time timer Trigger State at trigger input Edge Dead-time timer: inactive Rising edge of timer Ai one-shot pulse Falling edge of timer Ai one-shot pulse Dead-time timer: active Rising edge of timer Ai one-shot pulse (Re-trigger) Falling edge of timer Ai one-shot pulse (Re-trigger) n: A value which is set in the dead-time timer (address A716) fi: The dead-time timer ’s clock source (f2, f2/2, f2/4) Note: Width of pulse starting from a re-trigger occurrence timing 257 ✕ 1 fi (n+1) ✕ (Note) 1 fi n : 0016 258 ✕ 257 ✕ 1 fi 1 fi Pulse width n : 0116 through FF16 (n+2) ✕ (n+1) ✕ 1 fi 1 fi (Note) 10-8 7905 Group User ’ s Manual Rev.1.0 T HREE-PHASE WAVEFORM MODE 10.2 Block description 10.2.3 Three-phase output data register 0 Figure 10.2.6 shows the structure of the three-phase output data register 0 (the three-phase waveform mode). For bits 7 and 6, refer to section “ 10.2.2 Dead-time timer.” b7 b6 b5 b4 b3 b2 b1 b0 Three-phase output data register 0 (Address A816) Bit 0 1 2 3 Bit name W-phase output fix bit V-phase output fix bit U-phase output fix bit Function 0 : Released from output fixation 1 : Output fixed 0 : Released from output fixation 1 : Output fixed 0 : Released from output fixation 1 : Output fixed XX At reset 0 0 0 0 R/W RW RW RW RW W-phase output polarity set buffer 0 : “H” output (Valid in three-phase mode 0.) 1 : “L” output (Note) Invalid in the three-phase waveform mode. Clock-source-of-dead-time-timer b7 b6 : f2 00 0 1 : f2/2 select bits 1 0 : f2/4 1 1 : Do not select. 5, 4 6 7 0 0 0 RW RW RW X: It may be either “0” or “1.” Note: This bit is invalid in three-phase mode 1. Fig. 10.2.6 Structure of three-phase output data register 0 (three-phase waveform mode) (1) W-phase output fix bit (bit 0) Setting of this bit to “1” fixes the output level at the W-phase waveform output pin to the level which is selected by the W-phase fixed output’s polarity set bit (bit 0 at address A916); vice versa, the output level at the W-phase waveform output pin is reversed. (2) V-phase output fix bit (bit 1) Setting of this bit to “ 1 ” f ixes the output level at the V-phase waveform output pin to the level which is selected by the V-phase fixed output’s polarity set bit (bit 1 at address A9 16); vice versa, the output level at the V-phase waveform output pin is reversed. (3) U-phase output fix bit (bit 2) Setting of this bit to “ 1 ” f ixes the output level at the U-phase waveform output pin to the level which is selected by the U-phase fixed output’s polarity set bit (bit 2 at address A916); vice versa, the output level at the U-phase waveform output pin is reversed. (4) W-phase output polarity set buffer (bit 3) This bit serves as the buffer to set the W-phase output polarity and is used in three-phase mode 0. (Refer to section “ 10.2.9 Output polarity set toggle flip-flop.”) 7905 Group User ’ s Manual Rev.1.0 10-9 THREE-PHASE WAVEFORM MODE 10.2 Block description 10.2.4 Three-phase output data register 1 Figure 10.2.7 shows the structure of the three-phase output data register 1 (the three-phase waveform mode). b7 b6 b5 b4 b3 b2 b1 b0 Three-phase output data register 1 (Address A916) Bit 0 1 2 3 4 Bit name W-phase fixed output’s polarity set bit (Note 1) V-phase fixed output’s polarity set bit (Note 2) U-phase fixed output’s polarity set bit (Note 3) 0 : “H” output fixed 1 : “L” output fixed 0 : “H” output fixed 1 : “L” output fixed 0 : “H” output fixed 1 : “L” output fixed Function XX X At reset 0 0 0 0 0 R/W RW RW RW RW RW Invalid in the three-phase waveform mode. V-phase output polarity set buffer 0 : “H” output 1 : “L” output (in three-phase mode 0) Interrupt request interval set bit (in three-phase mode 1) 0 : Every second time 1 : Every forth time 5 U-phase output polarity set buffer 0 : “H” output 1 : “L” output (in three-phase mode 0) Interrupt validity output select bit 0 : An interrupt request occurs at each even-numbered underflow of timer A3 (in three-phase mode 1) 1 : An interrupt request occurs at each odd-numbered underflow of timer A3 0 RW 7, 6 Invalid in the three-phase waveform mode. 0 RW X: It may be either “0” or “1.” Notes 1: Valid when the W-phase output fix bit (bit 0 at address A816) = “1.” Be sure not to change the value during output of a fixed value. 2: Valid when the V-phase output fix bit (bit 1 at address A816) = “1.” Be sure not to change the value during output of a fixed value. 3: Valid when the U-phase output fix bit (bit 2 at address A816) = “1.” Be sure not to change the value during output of a fixed value. Fig. 10.2.7 Structure of three-phase output data register 1 (three-phase waveform mode) 10-10 7905 Group User ’ s Manual Rev.1.0 T HREE-PHASE WAVEFORM MODE 10.2 Block description (1) W-phase fixed output’s polarity set bit (bit 0) Clearance of this bit to “ 0 ” f ixes the output level at the W-phase waveform output pin to “ H ” ; vice versa, setting of this bit to “ 1 ” f ixes the output level at the W-phase waveform output pin to “ L. ” The output level at the W-phase waveform output pin is reversed. Note that this bit is valid only when the W-phase output fix bit (bit 0 at address A8 16) = “ 1. ” (2) V-phase fixed output’s polarity set bit (bit 1) Clearance of this bit to “0” fixes the output level at the V-phase waveform output pin to “H”; vice versa, setting of this bit to “ 1 ” f ixes the output level at the V-phase waveform output pin to “ L. ” The output level at the V-phase waveform output pin is reversed. Note that this bit is valid only when the V-phase output fix bit (bit 1 at address A8 16 ) = “ 1. ” (3) U-phase fixed output’s polarity set bit (bit 2) Clearance of this bit to “0” fixes the output level at the U-phase waveform output pin to “H”; vice versa, setting of this bit to “ 1 ” f ixes the output level at the U-phase waveform output pin to “ L. ” The output level at the U-phase waveform output pin is reversed. Note that this bit is valid only when the U-phase output fix bit (bit 2 at address A8 16) = “ 1. ” (4) V-phase output polarity set buffer (bit 4) (in three-phase mode 0) This bit serves as the buffer to set the V-phase output polarity. (Refer to section “ 10.2.9 Output polarity set toggle flip-flop.”) Interrupt request Clearance of this setting of this bit (Refer to section interval set bit (bit 4) (in three-phase mode 1) bit to “0” generates a timer A3 interrupt request at every second time; vice versa, to “ 1 ” g enerates a timer A3 interrupt request at every forth time. “ 10.4 Three-phase mode 1.”) (5) U-phase output polarity set buffer (bit 5) (in three-phase mode 0) This bit serves as the buffer to set the U-phase output polarity. (Refer to section “ 10.2.9 Output polarity set toggle flip-flop.”) Interrupt validity output select bit (bit 5) (in three-phase mode 1) Clearance of this bit to “0” generates a timer A3 interrupt request at every even-numbered underflow of timer A3; vice versa, setting of this bit to “1” generates a timer A3 interrupt request at every oddnumbered underflow of timer A3. (Refer to section “ 10.4 Three-phase mode 1.”) 7905 Group User ’ s Manual Rev.1.0 10-11 THREE-PHASE WAVEFORM MODE 10.2 Block description 10.2.5 Position-data-retain function control register Figure 10.2.8 shows the structure of the position-data-retain function control register. For details of the position-data-retain function, refer to section “ 10.6 Position-data-retain function.” b7 b6 b5 b4 b3 b2 b1 b0 Position-data-retain function control register (Address AA16) Bit 0 Bit name W-phase position data retain bit V-phase position data retain bit U-phase position data retain bit Retain-trigger polarity select bit Nothing is assigned. Function Input level at pin IDW is read out. 0 : “L” level 1 : “H” level Input level at pin IDV is read out. 0 : “L” level 1 : “H” level Input level at pin IDU is read out. 0 : “L” level 1 : “H” level 0 : Falling edge of positive phase 1 : Rising edge of positive phase At reset 0 R/W RO 1 2 3 7 to 4 0 RO 0 0 Undefined RO RW — Note: This register is valid only in the three-phase mode. Fig. 10.2.8 Structure of position-data-retain function control register (1) W-phase position data retain bit (bit 0) This bit is used to retain the input level at pin IDW. (2) V-phase position data retain bit (bit 1) This bit is used to retain the input level at pin IDV. (3) U-phase position data retain bit (bit 2) This bit is used to retain the input level at pin IDU. (4) Retain-trigger polarity select bit (bit 3) This bit is used to select the trigger polarity to retain the position data. When this bit = “ 0, ” t he falling edge of each positive phase is selected. When this bit = “ 1, ” t he rising edge of each positive phase is selected. 10-12 7905 Group User ’ s Manual Rev.1.0 T HREE-PHASE WAVEFORM MODE 10.2 Block description 10.2.6 Port P5 direction register The position-data input pins are multiplexed with port P5 pin. When using these pins as position-data-input pins, clear the corresponding bits of the port P5 direction register to “0” in order to set these port pins for the input mode. Figure 10.2.9 shows the relationship between the port P5 direction register and position-data-input pins. b7 b6 b5 b4 b3 b2 b1 b0 Port P5 direction register (Address D16) Bit 0 1 2 3 4 5 6 7 Corresponding pin Nothing is assigned. Pin INT1 Pin INT2/RTPTRG1 Pin INT3/RTPTRG0 Nothing is assigned. Pin IDW (Pin INT5/TB0IN) Pin IDV (Pin INT6/TB1IN) Pin IDU (Pin INT7/TB2IN) 0 : Input mode 1 : Output mode When using this pin as a position-data input pin, be sure to clear the corresponding bit to “0.” 0 : Input mode 1 : Output mode Functions At reset Undefined 0 0 0 Undefined 0 0 0 R/W — RW RW RW — RW RW RW Note: The pins in ( ) are I/O pins of other internal peripheral devices, which are multiplexed. Fig. 10.2.9 Relationship between port P5 direction register and position-data-input pins 10.2.7 Timers A0 through A2 Each of timers A0 through A2 is used to control the output width of each phase, and these timers are used in the one-shot pulse mode. Figure 10.2.10 shows the structure of timer A0/A1/A2 mode register (in the three-phase waveform mode). Because the underflow signal of timer A3 serves as a trigger for timers A0 through A3, it is unnecessary to set the one-shot start bit to “1.” Note that, in three-phase mode 1, each of timers A0 through A2 has the following two registers: timer A0/ A1/A2 register (addresses 46 16 a nd 47 16, 48 16 a nd 49 16, 4A 16 a nd 4B 16) and timer A0 1/A1 1/A2 1 r egister (addresses D016 and D116, D216 and D3 16, D416 and D516). These two registers are used to control the output width. Figure 10.2.11 shows the structures of the timer A0/A1/A2 mode register and timer A01/A11/A21 r egister. 7905 Group User’s Manual Rev.1.0 10-13 THREE-PHASE WAVEFORM MODE 10.2 Block description Timer A0/A1/A2 mode register (Addresses 5616 to 5816) b7 b6 b5 b4 b3 b2 b1 b0 011010 Function At reset 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Bit 0 1 2 3 4 5 6 7 Bit name Fix these bits to “0110102” in the three-phase waveform mode. Count source select bits See Table 7.2.3. 0 0 Fig. 10.2.10 Structure of timer A0/A1/A2 mode register (three-phase waveform mode) Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Bit (b15) b7 (b8) b0 b7 b0 Function At reset R/W WO Undefined 15 to 0 Any value in the range from “000016” to “FFFF16” can be set. Assuming that the set value = n, the “H” level width of the one-shot pulse is expressed as follows : n fi. fi: Frequency of count source Note: Use the MOVM or STA(STAD) instruction for writing to this register. Writing to this register must be performed in a unit of 16 bits. Timer A01 register (Addresses D116, D016) Timer A11 register (Addresses D316, D216) Timer A21 register (Addresses D516, D416) Bit (b15) b7 (b8) b0 b7 b0 Function At reset R/W WO Undefined 15 to 0 Any value in the range from 000016 to FFFF16 can be set. Assuming that the set value = n, the “H” level width of the one-shot pulse is expressed as follows: n/fi. fi: Frequency of a count source Notes 1: Use the MOVM or STA (STAD) instruction for writing to this register. Additionally, make sure writing to this register must be performed in a unit of 16 bits. 2: This register is valid only in three-phase mode 1 of the three-phase waveform mode. Fig. 10.2.11 Structures of timer A0/A1/A2 register and timer A0 1/A11/A21 r egister 10-14 7905 Group User’s Manual Rev.1.0 T HREE-PHASE WAVEFORM MODE 10.2 Block description 10.2.8 Timer A3 Timer A3 is used to control the carrier’s period of the whole three-phase waveform and is used in the timer mode. Note that a pulse is output, due to timer A3, from pin P66/TA3 OUT. (Refer to section “7.3.3 Select function; (2) Pulse output function.” ) When not outputing the pulse, be sure to clear bit 2 of the timer A3 mode register (address 59 16) to “0.” At this time, pin P66 c an be used as a programmable I/O port pin. Figure 10.2.12 shows the structure of the timer A3 mode register (the three-phase waveform mode). b7 b6 b5 b4 b3 b2 b1 b0 Timer A3 mode register (Address 5916) Bit 0 1 2 Pulse output function select bit Bit name Function 000 At reset 0 0 0 : No pulse output (TA3OUT pin functions as a programmable I/O port pin.) 1 : Pulse output (TA3OUT pin functions as a pulse outpt pin.) 0 00 R/W RW RW RW Fix these bits to “00 2” in the three-phase waveform mode. 3 4 5 6 7 Fix these bits to “0002” in the three-phase waveform mode. 0 0 0 RW RW RW RW RW Count source select bits See Table 7.2.3. 0 0 Fig. 10.2.12 Structure of timer A3 mode register (three-phase waveform mode) 7905 Group User’s Manual Rev.1.0 10-15 THREE-PHASE WAVEFORM MODE 10.2 Block description 10.2.9 Output polarity set toggle flip-flop The output polarity set toggle flip-flops 0 through 2 are used to control the output polarity of the positive and negative phases of the three-phase waveform. In three-phase mode 0, values are set into the U-, V-, W-phase output polarity set buffer (bits 5 and 4 at address A9 16 a nd bit 3 at address A8 16). In three-phase mode 1, a value is set into the three-phase output polarity set buffer (bit 3 at address A616). These bits are transferred to the output polarity set toggle flip-flop at an underflow of timer A3. The contents of the output polarity set toggle flip-flop are reversed at the end of the timer A0/A1/A2 oneshot pulse. Table 10.2.2 lists the relationship between the contents of the output polarity set toggle flip-flop and the output level, and Figure 10.2.13 shows the operations of the output polarity set buffer and output polarity set toggle flip-flop. Table 10.2.2 Relationship between contents of output polarity set toggle flip-flop and output level Contents of output polarity set toggle flip-flop 0 1 Output level of positive phase Output level of negative phase H L L H Timer A3 underflow signal Timer A2 one-shot pulse Internal signals Contents of U-phase output polarity set buffer Contents of output polarity set toggle-flip flop 2 1 0 Transferred Transferred Transferred Reversed Transferred Reversed From buffer 1 0 Reversed Reversed Fig. 10.2.13 Operations of output polarity set buffer and output polarity set toggle flip-flop 10-16 7905 Group User’s Manual Rev.1.0 T HREE-PHASE WAVEFORM MODE 10.2 Block description 10.2.10 Three-phase waveform mode I/O pins When the three-phase waveform mode is selected, port P6 0 t hrough P6 5 p ins become the three-phase waveform output pins, pin P6OUTCUT becomes the three-phase-waveform-output-forcibly-cutoff signal input pin. Figure 10.2.14 shows the pins used in the three-phase waveform mode. M37905 P65/TA2IN/U/RTP11 P64/TA2OUT/V/RTP10 P63/TA1IN/W/RTP03 U-phase position data input → V-phase position data input → W-phase position data input → P57/INT7/TB2IN/IDU P56/INT6/TB1IN/IDV P55/INT5/TB0IN/IDW P62/TA1OUT/U/RTP02 P61/TA0IN/V/RTP01 P60/TA0OUT/W/RTP00 P6OUTCUT/INT4 → U-phase waveform output → V-phase waveform output → W-phase waveform output → U-phase waveform output → V-phase waveform output → W-phase waveform output ← Three-phase-waveform-outputforcibly-cutoff signal input Fig. 10.2.14 Pins used in three-phase waveform mode 10.2.11 Pin P6OUTCUT (three-phase-waveform-output-forcibly-cutoff signal input pin) When a falling edge is input to pin P6OUT CUT, the waveform output control bit (bit 7 at address A6 16) becomes “0”; and then the three-phase waveform output pins enter the floating state. (In other words, the three-phase waveform output becomes inactive.) When restarting the three-phase waveform output after this output becomes inactive, be sure to return the input level at pin P6OUTCUT t o “ H ” ; and then, be sure to set the waveform output control bit to “ 1. ” W hen the input level at pin P6OUT CUT i s “ L, ” t he waveform output control bit cannot be “ 1. ” Also, at this time, bits 0 through 7 of the port P6 direction register (address 1016) become “0000002.” (Refer to section “5.2.4 Pin P6OUTCUT/INT4.”) Therefore, if it is necessary to switch port pins P60 through P65 to the port output pins, be sure to do as follows: ➀ R eturn the input level at pin P6OUT CUT t o “ H ” l evel. ➁ Write data to the port P6 register (address E16)’s bits, corresponding to the port P6 pins which will output data. ➂ S et the port P6 direction register ’ s bits, corresponding to the port P6 pins in ➁, to “ 1 ” i n order to set these port pins to the output mode. When the input level at pin P6OUT CUT i s “ L, ” e ach bit of the port P6 direction register cannot be “ 1. ” Figure 10.2.15 shows the relationship between the P6OUTCUT input, waveform output control bit, and threephase waveform output pin. Note that, when not inactivating the three-phase waveform output by using pin P6OUT CUT, be sure to connect pin P6OUTCUT t o Vcc via a resistor. Three-phase waveform mode is selected (Bit 2 through 0 at address A616 = 1002) ➀ P6OUTCUT input ➁ ➁ ➂ Waveform output control bit (bit 7 at address A616) Three-phase waveform output pin Programmable I/O port Floating Three-phase waveform output Floating Three-phase waveform output ➀ When the three-phase waveform mode is selected, the three-phase waveform output pins enter the floating state. ➁ Due to writing of “1” when the input level at pin P6OUTCUT = “H,” a pulse is output. ➂ Due to an input of a falling edge to P6OUTCUT, this bit becomes “0.” Fig. 10.2.15 Relationship between P6OUT CUT i nput, waveform output control bit, and three-phase waveform output pin 7905 Group User ’ s Manual Rev.1.0 10-17 THREE-PHASE WAVEFORM MODE 10.3 Three-phase mode 0 10.3 Three-phase mode 0 10.3.1 Setting for three-phase mode 0 Explanation of the triangular wave modulation output and saw-tooth-wave modulation output in three-phase mode 0 is described below. Table 10.3.1 lists the differences between the triangular wave modulation output and the saw-tooth-wave modulation output (in view of software). Table 10.3.1 Differences between triangular wave modulation output and saw-tooth-wave modulation output (in view of software) Saw-tooth-wave modulation output Triangular wave modulation output Trigger of dead-time timer Contents of output polarity set buffer Falling edge of timers A0 through A2 Falling and Rising edges of timers A0 through A2 Reversed at each timer A3 interrupt Not reversed. request occurrence. Figures 10.3.1 and 10.3.2 show an initial setting example for registers relevant to three-phase mode 0, Figure 10.3.3 shows a data-updating example in three-phase mode 0. Note that the initial output level at the three-phase waveform output pin is undefined. Be sure to start the three-phase waveform output (in other words, the waveform output is enabled.) after the output level at the three-phase waveform output pin is stabilized. 10-18 7905 Group User ’ s Manual Rev.1.0 T HREE-PHASE WAVEFORM MODE 10.3 Three-phase mode 0 Setting of timers A0 through A2 to one-shot pulse mode Timers A0 through A3 are inactive. b7 b0 b7 b0 0000 Count start register 0 (address 4016) Stops counting in timer A0. Stops counting in timer A1. Stops counting in timer A2. Stops counting in timer A3. 0 1 1 0 1 0 (addresses 5616 to 5816) Timer A0/A1/A2 mode register Count source select bits (See Table 7.2.3.) Setting of timer A3 to timer mode b7 b0 000 Setting of waveform output mode register b7 b0 0 0 (address 5916) Timer A3 mode register 0 ✕ 0 ✕ 1 0 0 (address A616) Waveform output mode register Three-phase mode 0 Dead-time timer trigger select bit 0 : Falling and Rising edges of one-shot pulse 1 : Falling edge of one-shot pulse Waveform outout is disabled. ✕ : It may be either “0” or “1.” When not using the TA3OUT pin (in other words, the TA3OUT pin is used as a programmable I/O port pin.), be sure to clear this bit to “0.” Count source select bits (See Table 7.2.3.) Setting of timer A0/A1/A2 interrupt request to “disabled” b7 b0 0 0 0 0 control register Timer A0/A1/A2 interrupt (addresses 7516 to 7716) Setting of dead-time timer b7 b0 Dead-time timer (address A716) A value in the range from “0016” to “FF16” is set. Interrupt disabled No Interrupt request Setting of timer A3 interrupt priority level b7 b0 0 Setting of three-phase output data register 0, 1 b7 b0 Timer A3 interrupt control register (address 7816) ✕✕ 0 0 0 Three-phase output data register 0 (address A816) Released from W-phase output fixation. Released from V-phase output fixation. Released from U-phase output fixation. W-phase output polarity set buffer 0 : “H” output 1 : “L” output Clock-source-of-dead-time-timer select bits b7 b6 Timer A3 interrupt priority level Set to one of levels 1 through 7. No Interrupt request Setting of period of timer A3’s carrier wave (b15) b7 (b8) b0 b7 b0 Timer A3 register (addresses 4D16, 4C16) A value in the range from “000016” to “FFFF16” is set. 0 0 : f2 0 1 : f2/2 1 0 : f2/4 b7 b0 Setting of output width of each phase of timers A0 through A2 (b15) b7 (b8) b0 b7 b0 ✕✕ ✕✕✕✕ Three-phase output data register 1 (address A916) V-phase output polarity set buffer 0 : “H” output 1 : “L” output U-phase output polarity set buffer 0 : “H” output 1 : “L” output Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) A value in the range from “000016” to “FFFF16” is set. ✕ : It may be either “0” or “1.” Continues to the next page. Fig. 10.3.1 Initial setting example for registers relevant to three-phase mode 0 (1) 7905 Group User ’ s Manual Rev.1.0 10-19 THREE-PHASE WAVEFORM MODE 10.3 Three-phase mode 0 Continued from the preceding page. Internal output for stabilization of output level b7 b0 1111 Count start register 0 (address 4016) Starts counting in timer A0. Starts counting in timer A1. Starts counting in timer A2. Starts counting in timer A3. Check whether the timer Ai interrupt request bit is “1” or not. (Note that the first one-shot pulse width of timer Ai must be the maximum among those of timers A0 through A2.) Waiting for the dead time, which was previously set, to elapse ❈ The output level is stabilized. Three-phase waveform output is enabled. b7 b0 1 Waveform output mode register (address A616) Three-phase waveform output is enabled. Three-phase waveform output starts. Fig. 10.3.2 Initial setting example for registers relevant to three-phase mode 0 (2) 10-20 7905 Group User ’ s Manual Rev.1.0 T HREE-PHASE WAVEFORM MODE 10.3 Three-phase mode 0 Timer A3 interrupt Setting of output width of each phase of timers A0 through A2 (b15) b7 (b8) b0 b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) A value in the range from “000016” to “FFFF16” is set. Saw-tooth-wave modulation Triangular wave modulation Setting of U-,V-,W-phase output polarity set buffer : reversed b7 b0 Three-phase output data register 0 (address A816) W-phase output polarity set buffer 0 : “H” output 1 : “L” output Bit 3 is reversed. b7 b0 Three-phase output data register 1 (address A916) V-phase output polarity set buffer 0 : “H” output 1 : “L” output U-phase output polarity set buffer 0 : “H” output 1 : “L” output Bits 4 and 5 are reversed. Timer A0/A1/A2 data calculation for the next time Interrupt processing is completed. Fig. 10.3.3 Data-updating example in three-phase mode 0 7905 Group User ’ s Manual Rev.1.0 10-21 THREE-PHASE WAVEFORM MODE 10.3 Three-phase mode 0 10.3.2 Operation in three-phase wave mode 0 Figure 10.3.4 shows a triangular wave modulation output example (three-phase mode 0), and Figure 10.3.5 shows a saw-tooth-wave modulation output example (three-phase mode 0) ➀ W hen an underflow occurs in the timer A3 counter, a timer A3 interrupt request is generated; simultaneously, the one-shot pulse outputs of timer A0 through A2 are started. Also, the contents of the output polarity set buffer of each phase are transferred to the output polarity set toggle flip-flop. In the case of the saw-tooth-wave modulation output, the one-shot pulse of the dead-time timer is output. Also, each of the positive and negative waveform outputs is not allowed to become “L” level from “ H ” l evel until the reversed signal of the one-shot pulse output of the dead-time timer rises. ➁ T he contents of the output polarity set toggle flip-flop are reversed at each falling edge of the one shot pulse output of timer A0/A1/A2. Simultaneously, the one-shot pulse of the dead-time timer is output. ➂ Each of the positive and negative waveform outputs is not allowed to become “L” level from “H” level until the reversed signal of the one-shot pulse output of the dead-time timer rises. ➃ I n the case of the triangular wave modulation output, before an underflow occurs in the timer A3 counter again, be sure to write the next data to the output polarity set buffer of each phase. Repeat procedures from ➀ t hrough ➃ f or the three-phase waveform output control. Figure 10.3.6 shows the triangular wave modulation output model (for one period), and Figure 10.3.7 shows the saw-tooth-wave modulation output model (for one period). 10-22 7905 Group User ’ s Manual Rev.1.0 T HREE-PHASE WAVEFORM MODE 10.3 Three-phase mode 0 ➀ ➁➂ ➃ Carrier wave Timer A3 interrupt request Timer A3 underflow signal Contents of timer A0/A1/A2 register One-shot pulse output of timer A0/A1/A2 Contents of U/V/W output polarity set buffer Contents of output polarity set toggle flip-flop Reversed signal of pulse output of dead-time timer Positive waveform output Negative waveform output ❈2 Transferred Reversed ❈2 ❈2 ❈1 ❈1 ❈1 ❈1 n1 n2 n3 n4 1/fi ✕ n1 1/fi ✕ n2 1/fi ✕ n3 1/fi ✕ n4 ❈1 Transferred ❈1 ❈1 Transferred Reversed Transferred Reversed ❈2 ❈1 : Written by software ❈2 : This is an internal signal, which cannot be read from the external. fi : Count source of timer A0/A1/A2 Fig. 10.3.4 Triangular wave modulation output example (three-phase mode 0) 7905 Group User ’ s Manual Rev.1.0 10-23 THREE-PHASE WAVEFORM MODE 10.3 Three-phase mode 0 ➀ ➁➂ Carrier wave Timer A3 interrupt request Timer A3 underflow signal Contents of timer A0/A1/A2 register One-shot pulse output of timer A0/A1/A2 Contents of U/V/W output polarity set buffer Contents of output polarity ❈2 set toggle flip-flop Reversed signal of pulse output of dead-time timer Positive waveform output Negative waveform output ❈2 ❈2 ❈2 ❈1 ❈1 ❈1 ❈1 n1 n2 n3 n4 1/fi ✕ n1 1/fi ✕ n2 1/fi ✕ n3 1/fi ✕ n4 L Transferred Reversed Reversed Transferred Transferred Reversed Transferred ❈1 : Written by software ❈2 : This is an internal signal, which cannot be read from the external. fi : Count source of timer A0/A1/A2 Fig. 10.3.5 Saw-tooth wave modulation output example (three-phase mode 0) 10-24 7905 Group User ’ s Manual Rev.1.0 T HREE-PHASE WAVEFORM MODE 10.3 Three-phase mode 0 U’ Sine wave V’ W’ Carrier wave U U V V W W ❈ Timer A3 ❈ Timer A2 ❈ Timer A1 ❈ Timer A0 ❈ This is an internal signal, which cannot be read from the external. Note: The dead time is executed. Fig. 10.3.6 Triangular wave modulation output model (for one period) 7905 Group User ’ s Manual Rev.1.0 10-25 THREE-PHASE WAVEFORM MODE 10.3 Three-phase mode 0 U’ Sine wave V’ W’ Carrier wave U U V V W W ❈ Timer A3 ❈ Timer A2 ❈ Timer A1 ❈ Timer A0 ❈ This is an internal signal, which cannot be read from the external. Note: The dead time is executed. Fig. 10.3.7 Saw-tooth-wave modulation output model (for one period) 10-26 7905 Group User ’ s Manual Rev.1.0 T HREE-PHASE WAVEFORM MODE 10.4 Three-phase mode 1 10.4 Three-phase mode 1 10.4.1 Setting for three-phase mode 1 In the triangular wave modulation, three-phase mode 1 is more efficiently controllable than three-phase mode 0. Therefore, three-phase mode 1 can mitigates the software’s load. Figure 10.4.1 and Figure 10.4.2 show an initial setting example of registers relevant to three-phase mode 1, and Figure 10.4.3 shows a data-updating example in three-phase mode 1. Note that the initial output level at the three-phase waveform output pin is undefined. Be sure to start the three-phase waveform output (in other words, the waveform output is enabled.) after the output level at the three-phase waveform output pin is stabilized. 7905 Group User’s Manual Rev.1.0 10-27 THREE-PHASE WAVEFORM MODE 10.4 Three-phase mode 1 Timers A0 through A3 are inactive. b7 Setting of timers A0 through A2 to one-shot pulse mode b7 b0 00 Count start register 0 0 0 (address 4016) Stops counting in timer A0. Stops counting in timer A1. Stops counting in timer A2. Stops counting in timer A3. b0 0 1 1 0 1 0 (addresses 5616 to 5816) Timer A0/A1/A2 mode register Count source select bits (See Table 7.2.3.) Setting of timer A3 to timer mode b7 b0 000 Setting of waveform output mode register b7 b0 0 0 (address 5916) Timer A3 mode register When not using the TA3OUT pin (in other words, the TA3OUT pin is used as a programmable I/O port pin.), be sure to clear this bit to “0.” Count source select bits (See Table 7.2.3.) 01✕1 1 0 0 (address A616) Waveform output mode register Three-phase mode 1 Three-phase output polarity set buffer (Note) 0 : “H” output 1 : “L” output Dead-time timer trigger select bit Falling edge of one-shot pulse Waveform output is disabled. ✕ : It may be either “0” or “1.” Setting of timer A0/A1/A2/A3 interrupt request to “disabled” b7 b0 0 0 0 0 control register Timer A0/A1/A2/A3 interrupt (addresses 7516 to 7816) Interrupt disabled No Interrupt request Setting of dead-time timer b7 b0 Dead-time timer (address A716) Setting of timer A3 carrier wave’s period A value in the range from “0016” to “FF16” is set. (b15) b7 (b8) b0 b7 b0 Timer A3 register (addresses 4D16, 4C16) Setting of three-phase output data register 0, 1 b7 b0 A value in the range from “000016” to “FFFF16” is set. ✕ ✕ ✕ 0 0 0 (address A816) Three-phase output data register 0 Released from W-phase output fixation. Released from V-phase output fixation. Released from U-phase output fixation. Clock-source-of-dead-time-timer select bits b7 b6 Setting of output width of each phase of timers A0 through A2 (b15) b7 (b8) b0 b7 b0 0 0 : f2 0 1 : f2/2 1 0 : f2/4 b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A01 register (addresses D116, D016) Timer A11 register (addresses D316, D216) Timer A21 register (addresses D516, D416) ✕✕ ✕ ✕ ✕ ✕ (address A916) Three-phase output data register 1 A value in the range from “000016” to “FFFF16” is set. Interrupt request interval set bit 0 : Every second time 1 : Every forth time Interrupt validity output select bit 0 : At each even-numbered underflow of timer A3 1 : At each odd-numbered underflow of timer A3 ✕ : It may be either “0” or “1.” Internal output for stabilization of output level b7 b0 1111 Count start register 0 (address 4016) Starts counting in timer A0. Starts counting in timer A1. Starts counting in timer A2. Starts counting in timer A3. Continues to the next page. Note: The contents of the three-phase output polarity set buffer are reversed once before the output level is stabilized. Therefore, at this time, be sure to set the reversed level of the level which the user desires to output. Fig. 10.4.1 Initial setting example for registers relevant to three-phase mode 1 (1) 10-28 7905 Group User’s Manual Rev.1.0 T HREE-PHASE WAVEFORM MODE 10.4 Three-phase mode 1 Continued from the preceding page. Check whether the timer Ai interrupt request bit is “1” or not. (Note that the first one-shot pulse width of timer Ai must be the maximum among those of timers A0 through A2.) Waiting for the dead time, which was previously set, to elapse ❈ The output level is stabilized. Setting of timer A3 interrupt priority level b7 b0 0 Timer A3 interrupt control register (address 7816) Timer A3 interrupt priority level Set to one of levels 1 through 7. No interrupt request Three-phase waveform output is enabled. b7 b0 1 Waveform output mode register (address A616) Three-phase waveform output is enabled. Three-phase waveform output starts. Fig. 10.4.2 Initial setting example for registers relevant to three-phase mode 1 (2) 7905 Group User ’ s Manual Rev.1.0 10-29 THREE-PHASE WAVEFORM MODE 10.4 Three-phase mode 1 Timer A3 interrupt Setting of output width of each phase of timers A0 through A2 (b15) b7 (b8) b0 b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A01 register (addresses D116, D016) Timer A11 register (addresses D316, D216) Timer A21 register (addresses D516, D416) A value in the range from “000016” to “FFFF16” is set. Timer A0/A1/A2 data calculation for the next time Interrupt processing is completed. Fig. 10.4.3 Data-updating example in three-phase mode 1 10-30 7905 Group User ’ s Manual Rev.1.0 T HREE-PHASE WAVEFORM MODE 10.4 Three-phase mode 1 10.4.2 Operation in three-phase mode 1 Figure 10.4.4 shows a triangular wave modulation output example (three-phase mode 1). ➀ W hen an underflow occurs in the timer A3 counter, a timer A3 interrupt request is generated; simultaneously, the one-shot pulse outputs of timers A0 through A2 are started. Also, the contents of the three-phase output polarity set buffer are transferred to the output polarity set toggle flip-flop, and then, the contents of the three-phase output polarity set buffer are reversed. ➁ T he contents of the output polarity set toggle flip-flop are reversed at each falling edge of the oneshot pulse output of timer A0/A1/A2. Simultaneously, the one-shot pulse of the dead-time timer is output. ➂ Each of the positive and negative waveform outputs is not allowed to become “L” level from “H” level until the reversed signal of the one-shot pulse output of the dead-time timer rises. Repeat procedures from ➀ t hrough ➂ f or the three-phase waveform output control. In the case of three-phase mode 1, the value of timer Ai ( i = 0 through 2) and the value of timer Ai1 a re counted alternately. Immediately after the count start in timer Ai, however, the value of the timer Ai register is counted twice in succession. (It is a limitation to the case immediately after the count start in timer Ai.) At this time, the timer Ai ’ s one-shot pulse becomes the same length twice in succession, also. Figure 10.4.5 shows an output example at start of three-phase mode 1. For the triangular wave modulation output model (for one period), see Figure 10.3.6. 7905 Group User ’ s Manual Rev.1.0 10-31 THREE-PHASE WAVEFORM MODE 10.4 Three-phase mode 1 ➀ Carrier wave Timer A3 interrupt request Timer A3 underflow signal Contents of timer A0/A1/A2 register Contents of timer A01/A11/A21 register One-shot pulse output of timer A0/A1/A2 Contents of three-phase output polarity set buffer Contents of output polarity ❈2 set toggle flip-flop Reversed signal of pulse output of dead-time timer Positive waveform output Negative waveform output ❈2 Transferred ❈2 ❈2 ➁➂ ❈1 ❈1 ❈1 ❈1 n1 ❈1 n3 ❈1 n5 ❈1 n7 ❈1 n9 n10 n2 n4 n6 n8 1/fi ✕ n1 Reversed 1/fi ✕ n2 Reversed Transferred Reversed Reversed 1/fi ✕ n3 Reversed Transferred 1/fi ✕ n4 Reversed Transferred Reversed 1/fi ✕ n5 Reversed Transferred 1/fi ✕ n6 Reversed Transferred Reversed 1/fi ✕ n7 Reversed Trans- Reverferred sed Reversed Reversed ❈1 : Written by software ❈2 : This is an internal signal, which cannot be read from the external. fi : Count source of timer A0/A1/A2 This applies under the following conditions: • Timer A3 interrupt request: every second time • Timer A3 interrupt validity output: even-numbered underflow in time A3 Fig. 10.4.4 Triangular wave modulation output example (three-phase mode 1) 10-32 7905 Group User ’ s Manual Rev.1.0 T HREE-PHASE WAVEFORM MODE 10.4 Three-phase mode 1 Carrier wave Timer A0/A1/A2/A3 count start bit Timer A3 interrupt request Timer A3 underflow signal Contents of timer A0/A1/A2 register Contents of timer A01/A11/A21 register One-shot pulse output of timer A0/A1/A2 Contents of three-phase output polarity set buffer Contents of output polarity set toggle flip-flop Reversed signal of pulse output of dead-time timer Positive waveform output Negative waveform output ❈2 Undefined ❈2 ❈2 ❈1 ❈1 ❈1 n1 ❈1 n3 ❈1 n5 ❈1 n2 n4 n6 1/fi ✕ n1 Reversed Transferred 1/fi ✕ n1 Reversed 1/fi ✕ n2 Reversed 1/fi ✕ n3 Reversed Transferred 1/fi ✕ n4 Reversed Transferred Reversed 1/fi ✕ n5 Reversed Transferred Transferred Trans- ReverReverferred sed sed Reversed ❈2 Undefined Undefined ❈1 : Written by software ❈2 : This is an internal signal, which cannot be read from the external. fi : Count source of timer A0/A1/A2 This applies under the following conditions: • Timer A3 interrupt request: every second time • Timer A3 interrupt validity output: even-numbered underflow in time A3 Fig. 10.4.5 Output example at start of three-phase mode 1 7905 Group User ’ s Manual Rev.1.0 10-33 THREE-PHASE WAVEFORM MODE 10.5 Three-phase waveform output fixation 10.5 Three-phase waveform output fixation In the three-phase waveform output, by setting of the U/V/W-phase output fix bit (bits 2 through 0 at address A816) to “1,” the output level of each phase can be fixed. The output level to be fixed (positive phase) is set by the U/V/W-phase fixed output’s polarity set bit (bits 2 through 0 at address A9 16); in the case of the negative phase, the output level is fixed to the reversed level. The U/V/W-phase output fix bit serves synchronously with a timer A3 interrupt request. While the fixed level is output, be sure not to change the value of the U/V/W-phase fixed output’s polarity set bit (bits 2 through 0 at address A9 16 ). Figure 10.5.1 shows a triangular wave modulation output example using the U/V/W-phase output fix bit (three-phase mode 1). ➀ B y software, set the following bits: • the U/V/W-phase output fix bit (bits 2 through 0 at address A8 16) • the U/V/W-phase fixed output’s polarity set bit (bits 2 through 0 at address A9 16) ➁ The contents of the above bits become valid synchronously with the next timer A3 interrupt request, and then, the output level of the positive waveform is fixed to the level which was set by the U/V/W-phase fixed output’s polarity set bit. In the case of the negative phase, the output level is fixed to the reversed level. ➂ E ach of the positive and negative waveform outputs is not allowed to become “L” level from “H” level until the reversed signal of the one-shot pulse output of the dead-time timer rises. ➃ T he output fixation is also terminated synchronous with a timer A3 interrupt request. 10-34 7905 Group User’s Manual Rev.1.0 T HREE-PHASE WAVEFORM MODE 10.5 Three-phase waveform output fixation ➀ Carrier wave Timer A3 interrupt request Timer A3 underflow signal Contents of timer A0/A1/A2 register Contents of timer A01/A11/A21 register U/V/W-phase output fix bit U/V/W-phase fixed output’s polarity set bit One-shot pulse output of timer A0/A1/A2 Contents of three-phase output polarity set buffer Contents of output polarity ❈2 set toggle flip-flop Reversed signal of pulse output of dead-time timer Positive waveform output Negative waveform output ❈2 Transferred ❈2 ➁➂ ➃ ❈1 ❈1 ❈1 ❈1 n1 ❈1 n3 ❈1 n5 ❈1 n7 ❈1 n9 n10 n2 ❈1 n4 n6 ❈1 n8 ❈1 ❈2 1/fi ✕ n1 Reversed 1/fi ✕ n2 Reversed Transferred Reversed 1/fi ✕ n3 Reversed Transferred 1/fi ✕ n4 Reversed 1/fi ✕ n5 1/fi ✕ n6 1/fi ✕ n7 Reversed Trans- Reverferred sed Reversed ReverReversed sed Transferred Transferred TransReverRever- Rever- ferred Reversed sed sed sed ❈1 : Written by software ❈2 : This is an internal signal, which cannot be read from the external. fi : Count source of timer A0/A1/A2 This applies under the following conditions: • Timer A3 interrupt request: every second time • Timer A3 interrupt validity output: every even-numbered underflow in time A3 Fig. 10.5.1 Triangular wave modulation output example using U/V/W-phase output fix bit (three-phase mode 1) 7905 Group User’s Manual Rev.1.0 10-35 THREE-PHASE WAVEFORM MODE 10.6 Position-data-retain function 10.6 Position-data-retain function This function is used to retain the position data synchronously with the three-phase waveform output; and there are three position-data input pins for the U, V, and W phases. A trigger to retain the position data (hereafter, this trigger is referred to as “retain trigger.”) can be selected by the retain-trigger polarity select bit (bit 3 at address AA 16); this bits selects the falling edge of each positive phase or rising edge of one. 10.6.1 Operation of position-data-retain function Figure 10.6.1 shows a usage example of the position-data-retain function (U phase) when a retain trigger is the falling edge of the positive signal. ➀ At the falling edge of the U-phase waveform output, the state at pin IDU is transferred to the U-phase position data retain bit (bit 2 at address AA16). ➁ U ntil the next falling edge of the U-phase waveform output, the above value is retained. ➀ Carrier wave ➁ U-phase waveform output U-phase waveform output Pin IDU U-phase position data retain bit (bit 2 at address AA16) Transferred Transferred Transferred Transferred Note: The retain trigger is the falling edge of the positive signal. Fig. 10.6.1 Usage example of position-data-retain function (U phase) 10-36 7905 Group User ’ s Manual Rev.1.0 T HREE-PHASE WAVEFORM MODE [Precautions for three-phase waveform mode] [Precautions for three-phase waveform mode] 1. When using the three-phase waveform mode, be sure to fix the waveform output select bits (bits 2 to 0 at address A6 16) to “ 100 2, ” a nd then, set the relevant registers. When not using pulse output port 0 and three-phase waveform mode, be sure to fix the waveform output select bits (bits 2 through 0 at address A6 16) to “ 0002. ” 2. When not inactivating the three-phase waveform output by using a falling edge input to pin P6OUT CUT, be sure to connect pin P6OUT CUT t o Vcc via a resistor. 3. While the fixed level is output, be sure not to change the value of the U/V/W-phase fixed output’s polarity set bit (bits 2 through 0 at address A9 16). 7905 Group User ’ s Manual Rev.1.0 10-37 THREE-PHASE WAVEFORM MODE [Precautions for three-phase waveform mode] MEMORANDUM 10-38 7905 Group User ’ s Manual Rev.1.0 CHAPTER 11 SERIAL I/O 11.1 Overview 11.2 Block description 11.3 Clock synchronous serial I/O mode [Precautions for clock synchronous serial I/O mode] 11.4 Clock asynchronous serial I/O (UART) mode [Precautions for clock asynchronous serial I/O (UART) mode] SERIAL I/O 11.1 Overview 11.1 Overview Serial I/O consists of 3 channels: UART0, UART1 and UART2. They each have a transfer clock generating timer for the exclusive use of them and can operate independently. UARTi (i = 0 to 2) has the following 2 operating modes: (1) Clock synchronous serial I/O mode Transmitter and receiver use the same clock as the transfer clock. Transfer data has a length of 8 bits. (2) Clock asynchronous serial I/O (UART) mode Transfer rate and transfer data format can arbitrarily be set. The user can select one transfer data length from the following: 7 bits, 8 bits, and 9 bits. Figure 11.1.1 shows the transfer data formats in each operating mode. q C lock synchronous serial I/O mode Transfer data length of 8 bits (LSB first) Transfer data length of 8 bits (MSB first) Transfer data length of 7 bits Transfer data length of 8 bits Transfer data length of 9 bits q U ART mode Fig. 11.1.1 Transfer data formats in each operating mode 11-2 7905 Group User’s Manual Rev.1.0 SERIAL I/O 11.2 Block description 11.2 Block description Figure 11.2.1 shows the block diagram of serial I/O. Registers relevant to serial I/O are described below. Data bus (odd) Data bus (even) Bit converter 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTi receive buffer register RxDi UART Clock synchronous 1/16 UART Clock synchronous 1/2 Clock synchronous (internal clock selected) Clock synchronous (internal clock selected) UARTi receive register BRG count source select bits f2 f16 f64 f512 1/16 Receive control circuit Transfer clock BRGi 1 / (n+1) Transmit control circuit Transfer clock UARTi transmit register UARTi transmit buffer register D8 D7 D6 D5 D4 D3 D2 D1 D0 TxDi Clock synchronous (external clock selected) CLKi Bit converter Data bus (odd) CTSi/CLKi CTSi CTSi/RTSi Data bus (even) n: Values set in UARTi baud rate register (BRGi) Fig. 11.2.1 Block diagram of serial I/O 7905 Group User’s Manual Rev.1.0 11-3 SERIAL I/O 11.2 Block description 11.2.1 UARTi transmit/receive mode register Figure 11.2.2 shows the structure of UARTi transmit/receive mode register. UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) UART2 transmit/receive mode register (Address B016) Bit 0 Bit name Serial I/O mode select bits b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 Function 0 0 0 : Serial I/O is invalid. (P1 and P8 function as programmable I/O ports.) 0 0 1 : Clock synchronous serial I/O mode 010: 0 1 1 : Do not select. 1 0 0 : UART mode (Transfer data length = 7 bits) 1 0 1 : UART mode (Transfer data length = 8 bits) 1 1 0 : UART mode (Transfer data length = 9 bits) 1 1 1 : Do not select. 0 : Internal clock 1 : External clock 0 : One stop bit 1 : Two stop bits 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode terminated (Invalid) 1 : Sleep mode selected At reset 0 R/W RW 1 0 RW 2 Internal/External clock select bit Stop bit length select bit (Valid in UART mode) (Note) Odd/Even parity select bit (Valid in UART mode when parity enable bit = “1.”) (Note) Parity enable bit (Valid in UART mode) (Note) Sleep select bit (Valid in UART mode) (Note) 0 RW 3 4 5 0 0 0 RW RW RW 6 7 0 0 RW RW Note: Bits 4 to 6 are invalid in the clock synchronous serial I/O mode. (They may be either “0” or “1.”) Additionally, fix bit 7 to “0.” Fig. 11.2.2 Structure of UARTi transmit/receive mode register 11-4 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.2 Block description (1) Serial I/O mode select bits (bits 0 to 2) These bits select a UARTi ’ s operating mode. (2) Internal/External clock select bit (bit 3) s Clock synchronous serial I/O mode By clearing this bit to “0” in order to select an internal clock, the clock which is selected with the BRG count source select bits (bits 0 and 1 at addresses 3416, 3C 16 and B416) becomes the count source of the BRGi. (Refer to section “ 11.2.6 UARTi baud rate register (BRGi).” ) The BRGi ’ s output divided by 2 becomes the transfer clock. Additionally, the transfer clock is output from the CLK i p in. By setting this bit to “ 1 ” i n order to select an external clock, the clock input to the CLK i p in becomes the transfer clock. s UART mode By clearing this bit to “0” in order to select an internal clock, the clock which is selected with the BRG count source select bits (bits 0 and 1 at addresses 3416, 3C 16 and B416) becomes the count source of the BRGi. (Refer to section “11.2.6 UARTi baud rate register (BRGi).”) Then, the CLKi pin functions as a programmable I/O port pin. By setting this bit to “ 1 ” i n order to select an external clock, the clock input to the CLK i p in becomes the count source of BRGi. Always in the UART mode, the BRGi ’ s output divided by 16 becomes the transfer clock. (3) Stop bit length select bit, Odd/Even parity select bit, Parity enable bit (bits 4 to 6) Refer to section “ 11.4.2 Transfer data format.” (4) Sleep select bit (bit 7) Refer to section “ 11.4.8 Sleep mode.” 7905 Group User ’ s Manual Rev.1.0 11-5 SERIAL I/O 11.2 Block description 11.2.2 UARTi transmit/receive control register 0 Figure 11.2.3 shows the structure of UARTi transmit/receive control register 0. UART0 transmit/receive control register (Address 3416) UART1 transmit/receive control register (Address 3C16) UART2 transmit/receive control register (Address B416) Bit 0 1 2 3 CTS/RTS function select bit (Note 1) Transmit register empty flag Bit name BRG count source select bits b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 Function 0 0 : Clock f2 0 1 : Clock f16 1 0 : Clock f64 1 1 : Clock f512 0 : The CTS function is selected. 1 : The RTS function is selected. 0 : Data is present in the transmit register. (Transmission is in progress.) 1 : No data is present in the transmit register. (Transmission is completed.) 0 : The CTS/RTS function is enabled. 1 : The CTS/RTS function is disabled. At reset 0 0 0 1 R/W RW RW RW RO 4 5 6 CTS/RTS enable bit 0 0 0 RW RW RW UARTi receive interrupt mode 0 : Reception interrupt 1 : Reception error interrupt select bit CLK polarity select bit 0 : At the falling edge of the transfer clock, transmit data is output; at the rising edge of the transfer (This bit is used in the clock clock, receive data is input. synchronous serial I/O mode.) When not in transferring, pin CLKi’s level is “H.” (Note 2) 1 : At the falling edge of the transfer clock, transmit data is output; at the falling edge of the transfer clock, receive data is input. When not in transferring, pin CLKi’s level is “L.” 0 : LSB (Least Significant Bit) first Transfer format select bit (This bit is used in the clock 1 : MSB (Most Significant Bit) first synchronous serial I/O mode.) (Note 2) 7 0 RW Notes 1: Valid when the CTS/RTS enable bit (bit 4) is “0” and CTSi/RTSi separate select bit (bit 0, 1, or 4 at address AC16) is “0.” 2: Fix these bits to “0” in the UART mode or when serial I/O is disabled. Fig. 11.2.3 Structure of UARTi transmit/receive control register 0 11-6 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.2 Block description (1) BRG count source select bits (bits 0 and 1) Refer to section “ 11.2.1 (2) Internal/External clock select bit.” ____ ____ (2) CTS/RTS function select ____(bit 2) bit ____ Refer to section “ 11.2.10 CTS/RTS function.” (3) Transmit register empty flag (bit 3) This flag is cleared to “0” when the UARTi transmit buffer register’s contents have been transferred to the UARTi transmit register. When transmission has been completed and the UARTi transmit register becomes empty, this flag is set to “ 1. ” ____ ____ (4) CTS/RTS enable bit (bit 4) ____ ____ Refer to section “ 11.2.10 CTS/RTS function.” (5) UARTi receive interrupt mode select bit (bit 5) Refer to section “ 11.2.7 (2) Interrupt request bit.” (6) CLK polarity select bit (bit 6) Refer to section “ 11.3.1 (3) Polarity of transfer clock.” (7) Transfer format select bit (bit 7) Refer to section “ 11.3.2 Transfer data format.” 7905 Group User ’ s Manual Rev.1.0 11-7 SERIAL I/O 11.2 Block description 11.2.3 UARTi transmit/receive control register 1 Figure 11.2.4 shows the structure of UARTi transmit/receive control register 1. UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) UART2 transmit/receive control register 1 (Address B516) Bit 0 1 2 3 4 5 6 7 Bit name Transmit enable bit Transmit buffer empty flag Receive enable bit Receive complete flag Overrun error flag Framing error flag (Valid in UART mode) Parity error flag (Valid in UART mode) Error sum flag (Valid in UART mode) (Note) (Note) (Note) Function 0 : Transmission disabled 1 : Transmission enabled b7 b6 b5 b4 b3 b2 b1 b0 At reset 0 1 0 0 0 0 0 0 R/W RW RO RW RO RO RO RO RO 0 : Data is present in the transmit buffer register 1 : No data is present in the transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data is present in the receive buffer register 1 : Data is present in the receive buffer register 0 : No overrun error 1 : Overrun error detected 0 : No framing error 1 : Framing error detected 0 : No parity error 1 : Parity error detected 0 : No error 1 : Error detected Note: Bits 5 to 7 are invalid in the clock synchronous serial I/O mode. Fig. 11.2.4 Structure of UARTi transmit/receive control register 1 11-8 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.2 Block description (1) Transmit enable bit (bit 0) By setting this bit to “ 1, ” U ARTi enters the transmission-enabled state. By clearing this bit to “ 0 ” during transmission, UARTi enters the transmission-disabled state after the transmission which was in progress at that time is completed. (2) Transmit buffer empty flag (bit 1) This flag is set to “1” when data set in the UARTi transmit buffer register has been transferred from the UARTi transmit buffer register to the UARTi transmit register. This flag is cleared to “0” when data has been set in the UARTi transmit buffer register. (3) Receive enable bit (bit 2) By setting this bit to “1,” UARTi enters the reception-enabled state. By clearing this bit to “0” during reception, UARTi quits the reception immediately and enters the reception-disabled state. (4) Receive complete flag (bit 3) This flag is set to “ 1 ” w hen data has been ready in the UARTi receive register and that has been transferred to the UARTi receive buffer register (i.e., when reception is completed). This flag is cleared to “ 0 ” i n one of the following cases: • W hen the low-order byte of the UARTi receive buffer register has been read out • W hen the receive enable bit (bit 2) has been cleared to “ 0 ” (5) Overrun error flag (bit 4) Refer to section “ 11.3.7 Processing on detecting overrun error” a nd “ 11.4.7 Processing on detecting error.” (6) Framing error flag, Parity error flag, Error sum flag (bits 5 to 7) Refer to section “ 11.4.7 Processing on detecting error.” 7905 Group User ’ s Manual Rev.1.0 11-9 SERIAL I/O 11.2 Block description 11.2.4 UARTi transmit register and UARTi transmit buffer register Figure 11.2.5 shows the block diagram for the transmitter; Figure 11.2.6 shows the structure of UARTi transmit buffer register. Data bus (odd) Data bus (even) D8 SP : Stop bit PAR : Parity bit Parity enabled D7 8-bit UART 9-bit UART Clock sync. D6 D5 D4 D3 D2 D1 D0 UARTi transmit buffer register 2SP SP SP 1SP PAR 7-bit UART 9-bit UART Clock sync. UART Parity disabled TxDi Clock sync. 8-bit UART 7-bit UART UARTi transmit register 0 Fig. 11.2.5 Block diagram for transmitter UART0 transmit buffer register (Addresses 3316, 3216) (b15) b7 UART1 transmit buffer register (Addresses 3B16, 3A16) UART2 transmit buffer register (Addresses B316, B216) Bit 8 to 0 Transmit data is set. Function (b8) b0 b7 b0 At reset Undefined Undefined R/W WO — 15 to 9 Nothing is assigned. Note: Use the MOVM (MOVMB) or STA (STAB, STAD) instruction for writing to this register. Fig. 11.2.6 Structure of UARTi transmit buffer register 11-10 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.2 Block description Transmit data is set into the UARTi transmit buffer register. Set the transmit data into the low-order byte of this register when the microcomputer operates in the clock synchronous serial I/O mode or when a 7bit or 8-bit length of transfer data is selected in the UART mode. When a 9-bit length of transfer data is selected in the UART mode, set the transmit data into the UARTi transmit buffer register as follows: • Bit 8 of the transmit data into bit 0 of high-order byte of this register. • Bits 7 to 0 of the transmit data into the low-order byte of this register. The transmit data which has been set in the UARTi transmit buffer register is transferred to the UARTi transmit register when the transmission conditions are satisfied, and then it is output from the TxDi pin synchronously with the transfer clock. The UARTi transmit buffer register becomes empty when the data set in the UARTi transmit buffer register has been transferred to the UARTi transmit register. Accordingly, the user can set the next transmit data. When the “ MSB first ” i s selected in the clock synchronous serial I/O mode, bit position of set data is reversed, and then the data of which bit position was reversed will be written, as a transmit data, into the UARTi transmit buffer register. (Refer to section “11.3.2 Transfer data format.” ) Transmit operation itself is the same whichever format is selected, “ LSB first ” o r “ MSB first. ” When quitting the transmission which is in progress and setting the UARTi transmit buffer register again, follow the procedure described bellow: ➀ C lear the serial I/O mode select bits (bits 2 to 0 at addresses 30 16, 3816 a nd B0 16) to “ 000 2” ( serial I/O disabled). ➁ S et the serial I/O mode select bits again. ➂ Set the transmit enable bit (bit 0 at addresses 3516, 3D16 and B516) to “1” (transmission enabled) and set transmit data in the UARTi transmit buffer register. 7905 Group User ’ s Manual Rev.1.0 11-11 SERIAL I/O 11.2 Block description 11.2.5 UARTi receive register and UARTi receive buffer register Figure 11.2.7 shows the block diagram of the receiver; Figure 11.2.8 shows the structure of UARTi receive buffer register. Data bus (odd) Data bus (even) 0 SP : Stop bit PAR : Parity bit 2SP 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTi receive buffer register Parity enabled UART 9-bit UART 8-bit UART 9-bit UART Clock sync. RxDi SP 1SP SP PAR Parity disabled Clock sync. 7-bit UART 8-bit UART Clock sync. 7-bit UART UARTi receive register Fig. 11.2.7 Block diagram of receiver UART0 receive buffer register (Addresses 3716, 3616) (b15) b7 UART1 receive buffer register (Addresses 3F16, 3E16) UART2 receive buffer register (Addresses B716, B616) Bit 8 to 0 Receive data is read out from here. Function (b8) b0 b7 b0 At reset Undefined 0 R/W RO — 15 to 9 The value is “0” at reading. F ig. 11.2.8 Structure of UARTi receive buffer register 11-12 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.2 Block description The UARTi receive register is used to convert serial data, which is input to the RxD i pin, into parallel data. This register takes in the signal input to the RxD i p in, bit by bit, synchronously with the transfer clock. The UARTi receive buffer register is used to read out receive data. When reception has been completed, the receive data taken in the UARTi receive register is automatically transferred to the UARTi receive buffer register. Note that the contents of the UARTi receive buffer register is updated when the next data has been ready in the UARTi receive register before the data transferred to the UARTi receive buffer register is read out. (i.e., an overrun error occurs.) When “ MSB first ” i s selected in the clock synchronous serial I/O mode, bit position of data in the UARTi receive buffer register is reversed, and then the data of which bit position was reversed will be read out as receive data. (Refer to section “ 11.3.2 Transfer data format. ”) Receive operation itself is the same whichever format is selected, “ LSB first ” o r “ MSB first. ” The UARTi receive buffer register is initialized by setting the receive enable bit (bit 2 at addresses 35 16, 3D 16 a nd B5 16) to “ 1 ” a fter clearing it to “ 0. ” Figure 11.2.9 shows the contents of the UARTi receive buffer register at reception completed. Low-order byte High-order byte (addresses 3716, 3F16, B716) (addresses 3616, 3E16, B616) b7 b0 b7 b0 UART mode (Transfer data length : 9 bits) Clock synchronous serial I/O mode, UART mode (Transfer data length : 8 bits) UART mode (Transfer data length : 7 bits) 0 000000 Receive data (9 bits) 0 000000 Same value as bit 7 in low-order byte Receive data (8 bits) 0 000000 Same value as bit 6 in low-order byte Receive data (7 bits) Fig. 11.2.9 Contents of UARTi receive buffer register at reception completed 7905 Group User ’ s Manual Rev.1.0 11-13 SERIAL I/O 11.2 Block description 11.2.6 UARTi baud rate register (BRGi) The UARTi baud rate register (BRGi) is an 8-bit timer exclusively used for UARTi to generate a transfer clock. It has a reload register. Assuming that the value set in the BRGi is “n” (n = “0016” to “FF16”), the BRGi divides the count source frequency by (n + 1). In the clock synchronous serial I/O mode, the BRGi is valid when an internal clock is selected, and the BRGi’s output divided by 2 becomes the transfer clock. In the UART mode, the BRGi is always valid, and the BRGi ’ s output divided by 16 becomes the transfer clock. The data written to the BRGi is written to both the timer and the reload register whichever transmission/ reception is in progress or not. Accordingly, writing to these register must be performed while transmission/ reception halts. Figure 11.2.10 shows the structure of the UARTi baud rate register (BRGi); Figure 11.2.11 shows the block diagram of transfer clock generating section. UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) UART2 baud rate register (BRG2) (Address B116) Bit 7 to 0 Function b7 b0 At reset Undefined R/W WO Any value in the range from “0016” to “FF16” can be set. Assuming that the set value = n, BRGi divides the count source frequency by (n + 1). Note: Writing to this register must be performed while the transmission/reception halts. Use the MOVM (MOVMB) or STA (STAB, STAD) instruction for writing to this register. Fig. 11.2.10 Structure of UARTi baud rate register (BRGi) fi fEXT BRGi 1/2 Transmit control circuit Transfer clock for transmit operation Transfer clock for receive operation Receive control circuit fi fEXT 1/16 Transmit control circuit Transfer clock for transmit operation Transfer clock for receive operation BRGi 1/16 Receive control circuit fi : Clock selected by BRG count source select bits (f2, f16, f64, or f512) fEXT : Clock input to CLKi pin (external clock) Fig. 11.2.11 Block diagram of transfer clock generating section 11-14 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.2 Block description 11.2.7 UARTi transmit interrupt control and UARTi receive interrupt control registers When using UARTi, 2 types of interrupts (UARTi transmit and UARTi receive interrupts) can be used. Each interrupt has its corresponding interrupt control register. Figure 11.2.12 shows the structure of UARTi transmit interrupt control and UARTi receive interrupt control registers. For details about these interrupts, refer to “ CHAPTER 6. INTERRUPTS. ” For the UARTi receive interrupt, a receive or receive error interrupt can be selected by the UARTi receive interrupt mode selected bit (bit 5 at addresses 34 16, 3C 16 a nd B4 16). UART0 transmit interrupt control register (Address 7116) UART0 receive interrupt control register (Address 7216) UART1 transmit interrupt control register (Address 7316) UART1 receive interrupt control register (Address 7416) UART2 transmit interrupt control register (Address F116) UART2 receive interrupt control register (Address F216) Bit 0 1 2 3 7 to 4 Interrupt request bit Nothing is assigned. Bit name Interrupt priority level select bits b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 Function 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested At reset 0 0 0 0 Undefined R/W RW RW RW RW (Note) — Note: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. Fig. 11.2.12 Structure of UARTi transmit interrupt control and UARTi receive interrupt control registers 7905 Group User ’ s Manual Rev.1.0 11-15 SERIAL I/O 11.2 Block description (1) Interrupt priority level select bits (bits 0 to 2) These bits select a priority level of the UARTi transmit interrupt or UARTi receive interrupt. When using UARTi transmit/receive interrupts, select one of the priority levels (1 to 7). When a UARTi transmit/receive interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = “ 0. ” ) To disable UARTi transmit/ receive interrupts, be sure to set these bits to “ 000 2” ( level 0). (2) Interrupt request bit (bit 3) The UARTi transmit interrupt request bit is set to “1” when data has been transferred from the UARTi transmit buffer register to the UARTi transmit register. The UARTi receive interrupt request bit functions as below: s W hen receive interrupt is selected (bit 5 = 0 at addresses 34 16, 3C16, B4 16) The UARTi receive interrupt request bit is set to “ 1 ” w hen data has been transferred from the UARTi receive register to the UARTi receive buffer register. (However, the UARTi receive interrupt request bit does not change when an overrun error has occurred.) s W hen receive error interrupt is selected (bit 5 = 1 at addresses 34 16, 3C 16, B4 6) The UARTi receive interrupt request bit is set to “1” when an error (an overrun error in the clock synchronous serial I/O mode; an overrun error, framing error, or parity error in UART mode) has occurred. Each interrupt request bit is automatically cleared to “0” when its corresponding interrupt request has been accepted. This bit can be set to “ 1 ” o r cleared to “ 0 ” b y software. 11-16 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.2 Block description 11.2.8 Serial I/O pin control register Figure 11.2.13 shows the structure of the seral I/O pin control register. b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O pin control register (Address AC16) Bit 0 1 2 3 4 Bit name CTS0/RTS0 separate select bit (Note) CTS1/RTS1 separate select bit (Note) TxD0/P13 switch bit TxD1/P17 switch bit CTS2/RTS2 separate select bit (Note) TxD2/P83 switch bit The value is “00” at reading. Function 0 : CTS0/RTS0 are used together. 1 : CTS0/RTS0 are separated. 0 : CTS1/RTS1 are used together. 1 : CTS1/RTS1 are separated. 0 : Functions as TxD0. 1 : Functions as P13. 0 : Functions as TxD1. 1 : Functions as P17. 0 : CTS2/RTS2 are used together. 1 : CTS2/RTS2 are separated. 0 : Functions as TxD2. 1 : Functions as P83. At reset 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW — 5 7, 6 Note: Valid when the CTS/RTS enable bit (bit 4 at addresses 3416, 3C16, and B416) is “0.” Fig. 11.2.13 Structure of serial I/O pin control register (1) CTS 0/RTS 0 s eparate select bit (bit 0) Refer to section “ 11.2.10 CTS/RTS function. ” (2) CTS 1/RTS 1 s eparate select bit (bit 1) Refer to section “ 11.2.10 CTS/RTS function. ” (3) TxD 0/P1 3 s witch bit (bit 2) When this bit is set to “1,” the TxD0 pin functions as a programmable I/O port pin (P1 3). When only reception is performed, the TxD0 pin can be used as the P13 pin. When performing transmission, be sure to clear this bit to “ 0. ” (4) TxD 1/P1 7 s witch bit (bit 3) When this bit is set to “1,” the TxD1 pin functions as a programmable I/O port pin (P1 7). When only reception is performed, the TxD1 pin can be used as the P17 pin. When preforming transmission, be sure to clear this bit to “ 0. ” (5) CTS 2/RTS 2 s eparate select bit (bit 4) Refer to section “ 11.2.10 CTS/RTS function. ” (6) TxD 2/P8 3 s witch bit (bit 5) When this bit is set to “1,” the TxD2 pin functions as a programmable I/O port pin (P8 3). When only reception is performed, the TxD2 pin can be used as the P83 pin. When preforming transmission, be sure to clear this bit to “ 0. ” 7905 Group User ’ s Manual Rev.1.0 11-17 SERIAL I/O 11.2 Block description 11.2.9 Port P1 direction register, Port P8 direction register I/O pins for serial I/O are multiplexed with port P1 and P8 pins. When using pins P1 1, P12, P1 5, P1 6, P8 1, and P8 2 a s serial I/O ’ s input pins (CTS i, RxD i), clear the corresponding bits of the port P1 and port P8 direction registers to “0” in order to set these pins for the input mode. When using these pins as other serial I/O ’ s pins (CTS i/RTS i, CLK i, TxD i), these pins are forcibly set as I/O pins for serial I/O regardless of the port P1 and port P8 direction registers’ contents. Figure 11.2.14 shows the relationship between the port P1 and port P8 direction registers and serial I/O ’ s I/O pins. For details, refer to the description of each operating mode. Port P1 direction register (Address 516) Bit 0 1 2 3 4 5 6 7 Corresponding pin name Pin CTS0/RTS0 Pin CTS0/CLK0 Pin RxD0 Pin TxD0 Pin CTS1/RTS1 Pin CTS1/CLK1 Pin RxD1 Pin TxD1 0 : Input mode 1 : Output mode Function b7 b6 b5 b4 b3 b2 b1 b0 At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW When using pins P11, P12, P15, and P16 as serial I/O’s input pins (CTS0, RxD0, CTS1, RxD1), clear the corresponding bits to “0.” Port P8 direction register (Address 1416) Bit 0 Corresponding pin name Pin CTS2/RTS2 (Pin AN8/DA1) 0 : Input mode (Note 1) 1 : Output mode Function b7 b6 b5 b4 b3 b2 b1 b0 At reset 0 R/W RW 1 2 3 7 to 4 Pin CTS2/CLK2 (Pin AN9) When using pins P81 and P82 as serial I/O’s input Pin RxD2 (Pin AN10) Pin TxD2 (Pin AN11) Nothing is assigned. pins (CTS2, RxD2), clear the corresponding bits to “0.” 0 0 0 Undefined RW RW RW – Notes 1: When using pin CTS2/RTS2, be sure that the D-A1 output enable bit (bit 1 at address 9616) = “0” (output disabled). 2: ( ) shows the I/O pins of other internal peripheral devices which are multiplexed. Fig. 11.2.14 Relationship between port P1 and port P8 direction registers and serial I/O ’ s I/O pins 11-18 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.2 Block description 11.2.10 CTS/RTS function When the CTS function is selected, the signal input to the CTS i p in must be at “ L ” l evel. (This is one of the transmit conditions.) When the RTS function is selected, the RTSi p in outputs the following signals: (1) Clock synchronous serial I/O mode When the receive enable bit (bit 2 at addresses 3516, 3D16, B5 16) = “0” (reception disabled), the RTSi pin outputs “ H ” l evel. When the receive enable bit = “0” (reception disabled), the RTSi pin outputs “L” level by setting the receive enable bit to “ 1, ” o r by reading the low-order byte of the UARTi receive buffer register. When the receive enable bit = “1” (continuously reception), the RTSi pin outputs “L” level by reading the low-order byte of the UARTi receive buffer register. When reception has started, the RTS i p in outputs “ H ” l evel. When an internal clock is selected (bit 3 at addresses 30 16, 3816, B0 16 = “0”), do not select the RTS function because the RTS output is undefined. (2) UART mode When the receive enable bit (bit 2 at addresses 3516, 3D16, B5 16) = “0” (reception disabled), the RTSi pin outputs “ H ” l evel. When the receive enable bit = “0” (reception disabled), the RTSi pin outputs “L” level by setting the receive enable bit to “ 1, ” o r by reading the low-order byte of the UARTi receive buffer register. When the receive enable bit = “1” (continuously reception), the RTSi pin outputs “L” level by reading the low-order byte of the UARTi receive buffer register. When reception has started, the RTS i p in outputs “ H ” l evel. Selection of the CTS/RTS function depends on the following bits. • CTS/RTS function select bit (bit 2 at addresses 34 16, 3C16, B4 16: see Figure 11.2.3.) • CTS/RTS enable bit (bit 4 at addresses 34 16, 3C 16, B416: see Figure 11.2.3.) • CTS 0/RTS 0 s eparate select bit (bit 0 at address AC 16: see Figure 11.2.13.) • CTS 1/RTS 1 s eparate select bit (bit 1 at address AC 16: see Figure 11.2.13.) • CTS 2/RTS 2 s eparate select bit (bit 4 at address AC 16: see Figure 11.2.13.) Table 11.2.1 lists the selection of the CTS/RTS function. 7905 Group User ’ s Manual Rev.1.0 11-19 SERIAL I/O 11.2 Block description Table 11.2.1 Selection of CTS/RTS function CTS/RTS enable bit CTSi/RTSi separate select bit CTS/RTS function select bit P10/CTS0/RTS0 pin 0 CTS0 P11 or CLK0 CTS1 P15 or CLK1 CTS2 0 1 RTS0 P11 or CLK0 RTS1 P15 or CLK1 RTS2 0 1 ✕ RTS0 CTS0 (Notes 2, 3) RTS1 CTS1 (Notes 2, 3) RTS2 1 ✕ ✕ P10 P11 or CLK0 P14 P15 or CLK1 P80, AN8, or DA1 Functions P11/CTS0/CLK0 pin P14/CTS1/RTS1 pin P15/CTS1/CLK1 pin P80/AN8/CTS2/RTS2/DA1 pin (Note1) P81/AN9/CTS2/CLK2 pin P81, AN9 or CLK2 P81, AN9 or CLK2 CTS2 (Notes 2, 3) P81, AN9, or CLK2 ✕ : It may be either “ 0 ” o r “ 1. ” Notes 1 : W hen using the CTS 2/RTS 2 p in, be sure that the D-A1 o utput enable bit (bit 1 at address 96 16) = “ 0 ” ( output disabled). 2: When using the P1 1, P1 5, or P8 1 pin as the CTSi pin, be sure to clear the corresponding bit of the port P1 or port P8 direction register to “ 0. ” 3: W hen CTSi/RTS i s eparation is selected, the CLK i p in cannot be used. Accordingly, CTS i/RTSi cannot be separated in the clock synchronous serial I/O mode. When separating CTS i/RTS i i n UART mode, be sure to select an internal clock. 11-20 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.3 Clock synchronous serial I/O mode 11.3 Clock synchronous serial I/O mode Table 11.3.1 lists the performance overview in the clock synchronous serial I/O mode, and Table 11.3.2 lists the functions of I/O pins in this mode. Table 11.3.1 Performance overview in clock synchronous serial I/O mode Item Transfer data format Transfer rate When selecting internal clock When selecting external clock Transmit/Receive control Functions Transfer data has a length of 8 bits. LSB first or MSB first can be selected by software. BRGi’s output divided by 2 Maximum 5 Mbps CTS function or RTS function can be selected by software. Table 11.3.2 Functions of I/O pins in clock synchronous serial I/O mode Pin name Functions Method of selection (Dummy data is output when performing only reception.) (Note) Programmable I/O port pin TxD 0/P13, TxD1/P1 7, or TxD 2/P83 s witch bit = “1” RxDi (P12, P16, P82) Serial data input pin Port P1 or P8 direction register’s corresponding bit = “0” Programmable I/O port pin – (Can be used as an I/O port pin when performing only transmission.) CLKi (P11, P15, P81) Transfer clock output pin Internal/External clock select bit = “0” Transfer clock input pin Internal/External clock select bit = “1” CTSi, RTSi CTS input pin See Table 11.2.1. (P10, P11, P14, P15, RTS output pin P8 0, P81) Programmable I/O port Port P1 direction register: address 05 16 Port P8 direction register: address 14 16 Internal/External clock select bit: bit 3 at addresses 3016, 38 16, B0 16 TxD 0/P1 3 s witch bit: bit 2 at address AC 16 TxD 1/P1 7 s witch bit: bit 3 at address AC 16 TxD 2/P8 3 s witch bit: bit 5 at address AC 16 Note: T he TxD i p in outputs “H” level until transmission starts after UARTi’s operating mode is selected. 11.3.1 Transfer clock (Synchronizing clock) Data transfer is performed synchronously with a transfer clock. For the transfer clock, the following selection is possible: q W hether to generate a transfer clock internally or to input it from the external. q P olarity of transfer clock. The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when performing only reception, set the transmit enable bit to “1,” and set dummy data in the UARTi transmit buffer register in order to m ake the transmit control circuit active. (1) Internal generation of transfer clock The count source selected with the BRG count source select bits is divided by the BRGi, and the BRGi output is further divided by 2. This divided output is the transfer clock. The transfer clock is output from the CLK i p in. Transfer clock’s frequency = fi 2 (n+1) f i: Frequency of BRGi’s count source (f2, f16, f64, or f512) n: Setting value of BRGi 11-21 TxDi (P13, P17, P83) Serial data output pin TxD 0/P13, TxD 1/P1 7, o r TxD 2/P83 s witch bit = “0” 7905 Group User’s Manual Rev.1.0 SERIAL I/O 11.3 Clock synchronous serial I/O mode (2) Input of transfer clock from the external A clock input from the CLKi p in becomes the transfer clock. (3) Porarity of transfer clock As shown in Figure 11.3.1, the polarity of the transfer clock can be selected by the CLK polarity select bit (bit 6 at addresses 34 16, 3C 166, B4 16). s CLK polarity select bit = 0 CLKi TxDi D0 D1 D2 D3 D4 D5 D6 D7 RxDi D0 D1 D2 D3 D4 D5 D6 D7 ❈The transmit data is output to the TxDi pin at the falling edge of a transfer clock, and the receive data is input from the RxDi pin at the rising edge of the transfer clock. The level at the CLKi pin is “H” when the transfer is not performed. s CLK polarity select bit = 1 CLKi TxDi D0 D1 D2 D3 D4 D5 D6 D7 RxDi D0 D1 D2 D3 D4 D5 D6 D7 ❈The transmit data is output to the TxDi pin at the rising edge of a transfer clock, and the receive data is input from the RxDi pin at the falling edge of the transfer clock. The level at the CLKi pin is “L” when the transfer is not performed. Fig. 11.3.1 Polarity of transfer clock 11-22 7905 Group User’s Manual Rev.1.0 SERIAL I/O 11.3 Clock synchronous serial I/O mode 11.3.2 Transfer data format LSB first or MSB first can be selected as the transfer data format. Table 11.3.3 lists the relationship between the transfer data format and writing/reading to and from the UARTi transmit/receive buffer register. The transfer format select bit (bit 7 at addresses 3416, 3C 16, B4 16) selects the transfer data format. When this bit is cleared to “0,” the set data is written to the UARTi transmit buffer register as the transmit data, as it is. Similarly, the data in the UARTi receive buffer register is read out as the receive data, as it is. (See the upper row in Table 11.3.3.) When this bit is set to “1,” each bit’s position of set data is reversed, and the resultant data will be written to the UARTi transmit buffer register as the transmit data. Similarly, each bit’s position of data in the UARTi receive buffer register is reversed, and the resultant data will be read out as the receive data. (See the lower row in Table 11.3.3.) Note that only the method of writing/reading to and from the UARTi transmit/receive buffer register is affected by selection of the transfer data format, and that t he transmit/receive operation is unaffected by it. Table 11.3.3 Relationship between transfer data format and writing/reading to and from UARTi transmit/ receive buffer register Transfer format select bit Transfer data format Writing to UARTi transmit buffer register Data bus DB7 UARTi transmit buffer register D7 D6 D5 D4 D3 D2 D1 D0 UARTi transmit buffer register D7 D6 D5 D4 D3 D2 D1 D0 Reading from UARTi receive buffer register Data bus DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Data bus DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 UARTi receive buffer register D7 D6 D5 D4 D3 D2 D1 D0 UARTi receive buffer register D7 D6 D5 D4 D3 D2 D1 D0 0 LSB (Least Significant Bit) first DB6 DB5 DB4 DB3 DB2 DB1 DB0 Data bus DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 MSB (Most Significant Bit) first 7905 Group User ’ s Manual Rev.1.0 11-23 SERIAL I/O 11.3 Clock synchronous serial I/O mode 11.3.3 Method of transmission Figure 11.3.2 shows an initial setting example for relevant registers when transmitting. Transmission is started when all of the following conditions (➀ to ➂) has been satisfied. When an external clock is selected, satisfy conditions ➀ t o ➂ w ith the following preconditions satisfied. The CLK i p in ’ s input is at “ H ” l evel (External clock selected, when the CLK polarity select bit = “ 0 ” ) The CLK i p in ’ s input is at “ L ” l evel (External clock selected, when the CLK polarity select bit = “ 1 ” ) Note: W hen an internal clock is selected, the above preconditions are ignored. ➀ T ransmit data is present in the UARTi transmit buffer register (transmit buffer empty flag = “ 0 ” ) ➁ T ransmission is enabled (transmit enable bit = “ 1 ” ). ➂ T he CTS i p in ’ s input is at “ L ” l evel (when the CTS function selected). Note : When the CTS function is not selected, condition ➂ i s ignored. By connecting the RTS i pin (receiver side) and CTS i pin (transmitter side), the timing of transmission and that of reception can be matched. For details, refer to section “ 11.3.6 Receive operation.” When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer to “ CHAPTER 6. INTERRUPTS.” Figure 11.3.3 shows the write operation of data after transmission start, and Figure 11.3.4 shows the detect operation of transmit completion. 11-24 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.3 Clock synchronous serial I/O mode UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) UART2 transmit/receive mode register (Address B016) b7 b0 When external clock is selected When internal clock is selected UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) UART2 baud rate register (BRG2) (Address B116) b7 b0 0✕✕✕ 001 Selection of clock synchronous serial I/O mode Internal/External clock select bit 0: Internal clock 1: External clock ✕: It may be either “0” or “1.” Can be set to “0016” to “FF16.” UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) UART2 transmit/receive control register 0 (Address B416) b7 b0 UART0 transmit interrupt control register (Address 7116) UART1 transmit interrupt control register (Address 7316) UART2 transmit interrupt control register (Address F116) b7 b0 BRG count source select bits b1 b0 0 0: f2 0 1: f16 1 0: f64 1 1: f512 CTS/RTS function select bit 0: CTS function selected 1: RTS function selected CTS/RTS enable bit 0: CTS/RTS function is enabled. 1: CTS/RTS function is disabled. CLK polarity select bit 0: At the falling edge of the transfer clock, transmit data is output 1: At the rising edge of the transfer clock, transmit data is output Transfer format select bit 0: LSB first 1: MSB first Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. UART0 transmit buffer register (Address 3216) UART1 transmit buffer register (Address 3A16) UART2 transmit buffer register (Address B216) b7 b0 Transmit data is set. UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) UART2 transmit/receive control register 1 (Address B516) b7 b0 Serial I/O pin control register (Address AC16) 16 b7 b0 1 CTS0/RTS0 separate select bit 0: CTS0 /RTS0 are used together (Note) CTS1/RTS1 separate select bit 0: CTS1/RTS1 are used together (Note) TxD0/P13 switch bit 0: Functions as TxD0. TxD1/P17 switch bit 0: Functions as TxD1. CTS2/RTS2 separate select bit 0: CTS2/RTS2 are used together (Note) TxD2/P83 switch bit 0: Functions as TxD2. Transmit enable bit 1: Transmission is enabled. Transmission starts. (In the case of selecting the CTS function, transmission starts when the CTS0 pin’s input level is “L.”) Note: In the clock synchronous serial I/O mode, CTSi/RTSi separation cannot be selected. (Refer to section “[Precautions for clock synchronous serial I/O mode].”) Fig. 11.3.2 Initial setting example for relevant registers when transmitting 7905 Group User ’ s Manual Rev.1.0 11-25 SERIAL I/O 11.3 Clock synchronous serial I/O mode [When not using interrupts] [When using interrupts] A UARTi transmit interrupt request occurs when the transbission starts (when the UARTi transmit buffer register becomes empty). Checking state of UARTi transmit buffer register UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) UART2 transmit/receive control register 1 (Address B516) b7 b0 b0 UARTi transmit interrupt 1 Transmit buffer empty flag 0: Data is present in transmit buffer register. 1: No data is present in transmit buffer register. (Writing of next transmit data is possible.) Writing of next transmit data UART0 transmit buffer register (Address 3216) UART1 transmit buffer register (Address 3A16) UART2 transmit buffer register (Address B216) b7 b0 Note: This figure shows the bits and registers required for processing. See Figures 11.3.6 and 11.3.7 for the change of flag state and the occurrence timing of an interrupt request. Transmit data is set. Fig. 11.3.3 Write operation of data after transmission start [When using interrupts] [When not using interrupts] A UARTi transmit interrupt request occurs when the transmission starts. Checking start of transmission UART0 transmit interrupt control register (Address 7116) UART1 transmit interrupt control register (Address 7316) UART2 transmit interrupt control register (Address F116) b7 b0 UARTi transmit interrupt Interrupt request bit 0: No interrupt requested 1: Interrupt requested (Transmission has started.) Checking completion of transmission UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) UART2 transmit/receive control register 0 (Address B416) b7 b0 Note: This figure shows the bits and registers required for processing. See Figures 11.3.6 and 11.3.7 for the change of flag state and the occurrence timing of an interrupt request. Transmit register empty flag 0: Transmission is in progress. 1: Transmission is completed. Processing at completion of transmission Fig. 11.3.4 Detect operation of transmit completion 11-26 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.3 Clock synchronous serial I/O mode 11.3.4 Transmit operation When the transmit conditions described in section “11.3.3 Method of transmission” have been satisfied in the case of an internal clock selected, a transfer clock is generated and the following operations are automatically performed after 1 cycle of the transfer clock or less has passed. In the case of an external clock selected, when the transmit conditions have been satisfied and then an external clock is input to the CLKi p in, the following operations are automatically performed: • The UARTi transmit buffer register ’ s contents are transferred to the UARTi transmit register. • The transmit buffer empty flag is set to “ 1. ” • The transmit register empty flag is cleared to “ 0. ” • 8 transfer clocks are generated (in the case of an internal clock selected). • A UARTi transmit interrupt request occurs, and the interrupt request bit is set to “ 1. ” The transmit operations are described below: ➀ Data in the UARTi transmit register is transmitted from the TxD i pin synchronously with the valid edge✼ of the clock output from or input to the CLK i p in. ➁ T his data is transmitted, bit by bit, sequentially beginning with the least significant bit. ➂ When 1-byte data has been transmitted, the transmit register empty flag is set to “1.” This indicates the completion of transmission. Valid edge ✼ : A f alling edge is selected when the CLK polarity select bit = “ 0. ” A rising edge is selected when the CLK polarity select bit = “ 1. ” Figure 11.3.5 shows the transmit operation. When an internal clock is selected, if the transmit conditions for the next data are satisfied at completion of the transmission, the transfer clock is generated continuously. Accordingly, when performing transmission continuously, set the next transmit data to the UARTi transmit buffer register during transmission (when the transmit register empty flag = “ 0 ” ). When the transmit conditions for the next data are not satisfied, the transfer clock stops at “H” level (when the CLK polarity select bit = “0”), or “L” level (when the CLK polarity select bit = “ 1 ” ). Figures 11.3.6 and 11.3.7 show examples of transmit timing. b7 b0 UARTi transmit buffer register Transfer clock output from or input to the CLKi pin (Note) MSB UARTi transmit register D7 D6 Transmit data LSB D5 D4 D3 D2 D1 D0 D1 D0 D1 D2 D7 D6 D5 D4 D3 D2 D7 D6 D5 D4 D3 D2 D3 D7 D6 D5 D4 • • • • • • D7 Note: This applies when the CLK polarity select bit = “0.” When the CLK polarity select bit = “1,” data is shifted at the rising edge of the transfer clock. Fig. 11.3.5 Transmit operation 7905 Group User ’ s Manual Rev.1.0 11-27 SERIAL I/O 11.3 Clock synchronous serial I/O mode Tc Transfer clock Transmit enable bit Transmit buffer empty flag Data is set in UARTi transmit buffer register. UARTi transmit register ← UARTi transmit buffer register. CTSi TCLK Stopped because CTSi = “H.” Stopped because transmit enable bit = “0.” CLKi TENDi TxDi D0 D1 D2 D 3 D4 D 5 D6 D7 D0 D 1 D2 D3 D4 D 5 D6 D7 D 0 D1 D 2 D3 D 4 D5 D6 D 7 Transmit register empty flag UARTi transmit interrupt request bit Cleared to “0” when interrupt request is accepted or cleared to “0” by software. The above timing diagram applies when the following conditions are satisfied: q Internal clock selected q CTS function selected q CLK polarity select bit = 0 TENDi: Next transmit conditions are examined when this signal level is “H.” (TENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc = TCLK = 2(n+1) /fi fi: BRGi count source frequency n: Value set in BRGi Fig. 11.3.6 Example of transmit timing (when internal clock and CTS function selected) Tc Transfer clock Transmit enable bit Data is set in UARTi transmit buffer register. Transmit buffer empty flag UARTi transmit register←UARTi transmit buffer register. TCLK Stopped because transmit enable bit = “0.” CLKi TENDi TxDi D0 D1 D2 D3 D4 D5 D 6 D7 D0 D 1 D2 D3 D4 D5 D6 D7 D 0 D1 D 2 D3 D 4 D5 D 6 D 7 Transmit register empty flag UARTi transmit interrupt request bit Cleared to “0” when interrupt request is accepted or cleared to “0” by software. The above timing diagram applies when the following conditions are satisfied: q Internal clock selected q CTS function not selected q CLK polarity select bit = 0 TENDi: Next transmit conditions are examined when this signal level is “H.” (TENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc = TCLK = 2(n+1) /fi fi: BRGi count source frequency n: Value set in BRGi Fig. 11.3.7 Example of transmit timing (when internal clock selected and CTS function not selected) 11-28 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.3 Clock synchronous serial I/O mode 11.3.5 Method of reception Figure 11.3.8 shows an initial setting example for relevant registers when receiving. Reception is started when all of the following conditions ( ➀ t o ➂ ) have been satisfied. When an external clock is selected, satisfy conditions ➀ t o ➂ w ith the following preconditions satisfied. The CLK i p in ’ s input is at “ H ” l evel (External clock selected, when the CLK polarity select bit = “ 0 ” ) . The CLK i p in ’ s input is at “ L ” l evel (External clock selected, when the CLK polarity select bit = “ 1 ” ). Note: W hen an internal clock is selected, the above preconditions are ignored. ➀ D ummy data is present in the UARTi transmit buffer register (transmit buffer empty flag = “ 0 ” ) ➁ R eception is enabled (receive enable bit = “ 1 ” ). ➂ T ransmission is enabled (transmit enable bit = “ 1 ” ). By connecting the RTSi pin (receiver side) and CTS i pin (transmitter side), the timing of transmission and that of reception can be matched. For details, refer to section “ 11.3.6 Receive operation. ” When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer to “ CHAPTER 6. INTERRUPTS. ” Figure 11.3.9 shows processing after reception is completed. 7905 Group User ’ s Manual Rev.1.0 11-29 SERIAL I/O 11.3 Clock synchronous serial I/O mode UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) UART2 transmit/receive mode register (Address B016) b7 b0 When external clock is selected. When internal clock is selected. UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) UART2 baud rate register (BRG2) (Address B116) b7 b0 0✕✕✕ 001 Selection of clock synchronous serial I/O mode Internal/External clock select bit 0: Internal clock 1: External clock ✕: It may be either “0” or “1.” Can be set to “0016” to “FF16”. UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) UART2 transmit/receive control register 0 (Address B416) b7 b0 Port P1 direction register (Address 516) b7 b0 0 0 Pin RxD0 BRG count source select bits b1 b0 Pin RxD1 0 0: f2 0 1: f16 1 0: f64 1 1: f512 CTS/RTS function select bit 0: CTS function selected 1: RTS function selected CTS/RTS enable bit 0: CTS/RTS function is enabled. 1: CTS/RTS function is disabled UARTi receive interrupt mode select bit 0: Reception interrupt 1: Reception error interrupt CLK polarity select bit 0: At the rising edge of the transfer clock, receive data is input. 1: At the falling edge of the transfer clock, receive data is input. Transfer format select bit 0: LSB first 1: MSB first Port P8 direction register (Address 1416) b7 b0 0 Pin RxD2 UART0 receive interrupt control register (Address 7216) UART1 receive interrupt control register (Address 7416) UART2 receive interrupt control register (Address F216) b7 b0 Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Serial I/O pin control register (Address AC16) b7 b0 UART0 transmit buffer register (Address 3216) UART1 transmit buffer register (Address 3A16) UART2 transmit buffer register (Address B216) b7 b0 CTS0/RTS0 separate select bit 0: CTS0/RTS0 are used together (Note 1) CTS1/RTS1 separate select bit 0: CTS1/RTS1 are 1 used together (Note 1) TxD0/P13 switch bit (Note 2) 0: Functions as TxD0. 1: Functions as P13. TxD1/P17 switch bit (Note 2) 0: Functions as TxD1. 1: Functions as P17. 7 CTS2/RTS2 separate select bit 0: CTS2/RTS2 are used together (Note 1) TxD2/P83 switch bit (Note 2) 3 0: Functions as TxD2. 1: Functions as P83. Dummy data is set. UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) UART2 transmit/receive control register 1 (Address B516) b7 b0 1 1 Transmit enable bit 1: Transmission enabled Reception enable bit 1: Reception enabled Note: Set the receive enable bit and the transmit enable bit to “1” simultaneously. Notes 1: In the clock synchronous serial I/O mode, CTSi/RTSi separation cannot be selected. (Refer to section “[Precautions for clock synchronous serial I/O mode].”) 2: When only reception is performed, if i these bits = “1,” the TxDi pin can be used as a programmable I/O port pin. Reception starts. Fig. 11.3.8 Initial setting example for relevant registers when receiving 11-30 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.3 Clock synchronous serial I/O mode [When not using interrupts] [When using interrupts] (Note 1) A UARTi receive interrupt request occurs when reception is completed. Checking completion of reception UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) UART2 transmit/receive control register 1 (Address B516) b7 b0 UARTi receive interrupt 1 1 Receive complete flag 0 : Reception not completed 1 : Reception completed Reading of receive data (Note 2) UART0 receive buffer register (Address 3616) UART1 receive buffer register (Address 3E16) UART2 receive buffer register (Address B616) b7 b0 Read out receive data. Checking error UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) UART2 transmit/receive control register 1 (Address B516) b7 b0 1 1 Overrun error flag 0 : No overrun error 1 : Overrun error detected Processing after reading out receive data Notes 1: When performing the processing after reception is completed, using an interrupt, be sure to select a receive interrupt (UARTi receive interrupt mode select bit = “0.”) 2: In the case of an external clock and the RTS function selected, the RTSi output level becomes “L” when the UARTi receive buffer register is read out. Accordingly, when performing reception continuously, be sure to write the dummy data to the UARTi transmit buffer register before reading out the UARTi receive buffer register. 3: This figure shows the bits and registers required for the processing. See Figure 11.3.12 for the change of flag state and the occurrence timing of an interrupt request. Fig. 11.3.9 Processing after reception is completed 7905 Group User ’ s Manual Rev.1.0 11-31 SERIAL I/O 11.3 Clock synchronous serial I/O mode 11.3.6 Receive operation In the case of an internal clock selected, when the receive conditions described in section “11.3.5 Method of reception” have been satisfied, a transfer clock is generated and the reception is started after 1 cycle of the transfer clock or less has passed. In the case of an external clock selected, when the receive conditions have been satisfied, the UARTi enters the receive-enabled state, and then reception will be started when an external clock is input to the CLKi pin. In the case of an external clock selected, when connecting the RTSi pin to the CTS i pin of the transmitter side, the timing of transmission and that of reception can be matched. In the case of an internal clock selected, do not use the RTS function. It is because the RTS output is undefined in the case of an internal clock selected. In the case of an external clock and the RTS function selected, the RTS i p in ’ s output level becomes as described below. When the receive enable bit = “0,” if one of the following is performed, the RTSi pin’s output level becomes “ L ” a nd informs of the transmitter side that reception has become enabled: • T he receive enable bit is set to “ 1. ” • T he low-order byte of the UARTi receive buffer register is read out. When the receive enable bit = “ 1, ” i f the low-order byte of the UARTi receive buffer register is read out, the RTS i p in ’ s output level becomes “ L. ” Accordingly, when performing reception continuously, an overrun occurrence can be avoided because the RTS output level does not become “ L ” u ntil the receive data is read out. When reception has started, the RTS i p in ’ s output level becomes “ H. ” Figure 11.3.10 shows a connection example. Transmitter side TxDi RxDi CLKi Receiver side TxDi RxDi CLKi CTSi RTSi Fig. 11.3.10 Connection example 11-32 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.3 Clock synchronous serial I/O mode The receive operations are described below: ➀ T he signal input to the RxD i p in is taken into the most significant bit of the UARTi receive register synchronously with the valid edge✼ o f the clock output from the CLK i p in or input to the CLK i p in. ➁ T he contents of the UARTi receive register are shifted, bit by bit, to the right. ➂ S teps ➀ a nd ➁ a re repeated at each valid edge of the clock output from the CLK i p in or input to the CLKi p in. ➃ W hen 1-byte data has been prepared in the UARTi receive register, the contents of this register are transferred to the UARTi receive buffer register. ➄ S imultaneously with step ➃ , the receive complete flag is set to “ 1. ” A dditionally, when the receive interrupt is selected (UARTi receive interrupt mode select bit = “0”), a UARTi receive interrupt request occurs and its interrupt request bit is set to “ 1. ” Valid edge ✼ : A r ising edge is selected when the CLK polarity select bit = “ 0. ” A falling edge is selected when the CLK polarity select bit = “ 1. ” The receive complete flag is cleared to “ 0 ” w hen the low-order byte of the UARTi receive buffer register is read out. Figure 11.3.11 shows the receive operation, and Figure 11.3.12 shows an example of receive timing (when an external clock is selected). When the transfer format select bit is “ 1 ” ( MSB first), each bit ’ s position of this register ’ s contents is reversed, and then the resultant data is read out. 7905 Group User ’ s Manual Rev.1.0 11-33 SERIAL I/O 11.3 Clock synchronous serial I/O mode Transfer clock output from or input to CLKi pin (Note). MSB UARTi receive register D0 D1 D0 D2 D1 D0 • • • D7 D6 b7 LSB • • • D5 D4 D3 D2 D1 D0 b0 UARTi receive buffer register Receive data Note: This applies when the CLK polarity select bit = “0.” When the CLK polarity select bit = “1,” data is shifted at the rising edge of the transfer clock. Fig. 11.3.11 Receive operation Receive enable bit Transmit enable bit Dummy data is set to UARTi transmit buffer register. Transmit buffer empty flag UARTi transmit register←UARTi transmit buffer RTSi 1/fEXT CLKi Receive data is taken in. RxDi D0 D1 D 2 D 3 D4 D 5 D6 D 7 D0 D1 D2 D3 D 4 D5 UARTi receive register→UARTi receive buffer register Receive complete flag UARTi receive buffer register is read o UARTi receive interrupt request bit Cleared to “0” when interrupt request is accepted or cleared to “0” by software. The above timing diagram applies when the following conditions are satisfied: q External clock selected q RTS function selected q CLK polarity select bit = “0” fEXT: Frequency of external clock When the CLKi pin’s input level is “H,” be sure to sati the following conditions: q Writing of dummy data to UARTi transmit buffer re q Transmit enable bit = “1” q Receive enable bit = “1” Fig. 11.3.12 Example of receive timing (when external clock selected) 11-34 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.3 Clock synchronous serial I/O mode 11.3.7 Processing on detecting overrun error In the clock synchronous serial I/O mode, an overrun error can be detected. An overrun error occurs when the next data has been prepared in the UARTi receive register with the receive complete flag = “ 1 ” ( i.e. data is present in the UARTi receive buffer register) and next data is transferred to the UARTi receive buffer register. In other words, an overrun error occurs when the next data has been prepared before reading out the contents of the UARTi receive buffer register. When an overrun error has occurred, the next receive data is written into the UARTi receive buffer register. Additionally, when the receive error interrupt is selected (UARTi receive interrupt mode select bit = “1”), a UARTi receive interrupt request occurs and its interrupt request bit is set to “ 1. ” W hen the receive interrupt is selected (UARTi receive interrupt mode select bit = “0”), the UARTi receive interrupt request bit does not change. An overrun error is detected when data is transferred from the UARTi receive register to the UARTi receive buffer register, and the overrun error flag is set to “1.” The overrun error flag is cleared to “0” by clearing the receive enable bit to “ 0. ” When an overrun error occurs during reception, be sure to initialize the overrun error flag and UARTi receive buffer register, and then perform reception again. When it is necessary to perform retransmission owing to a receiver-side overrun error which has occurred during transmission, be sure to set the UARTi transmit buffer register again, and start transmission again. The methods of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer register again are described below. (1) Method of initializing UARTi receive buffer register ➀ C lear the receive enable bit to “ 0 ” ( reception disabled). ➁ S et the receive enable bit to “ 1 ” a gain (reception enabled). (2) Method of setting UARTi transmit buffer register again ➀ C lear the serial I/O mode select bits to “ 000 2” ( serial I/O invalidated). ➁ S et the serial I/O mode select bits to “ 001 2” a gain. ➂ Set the transmit enable bit to “1” (transmission enabled), and set the transmit data to the UARTi transmit buffer register. 7905 Group User ’ s Manual Rev.1.0 11-35 SERIAL I/O [Precautions for clock synchronous serial I/O mode] [Precautions for clock synchronous serial I/O mode] 1. A transfer clock is generated by operation of the transmit control circuit. Accordingly, even when performing only reception, the transmit operation (in other words, setting for transmission) must be performed. In this case, be sure to set as follows. Additionally, in this case, dummy data is output from the TxD i pin to the external: • W hen performing reception, be sure to enable the reception after dummy data is set to the low-order byte of the UARTi transmit buffer register. Also, be sure to set dummy data at each 1-byte data reception. • A t reception, be sure to set the receive enable bit and transmit enable bit to “ 1 ” s imultaneously. When performing only reception, if any of the TxD 0/P13, TxD1/P17 and TxD2/P83 switch bits (bits 2, 3 and 5 at address AC16) is set to “1,” the corresponding TxD i pin can be used as a programmable I/O port pin. 2. When an external clock is selected, with the input level at the CLKi pin = “H” (the CLK polarity select bit = “ 0 ” ) or “ L ” ( the CLK polarity select bit = “ 1 ” ), be sure to satisfy all of the following three conditions: ➀ T ransmit data is written to the UARTi transmit buffer register. ➁ T he transmit enable bit is set to “ 1. ” ➂ “ L ” l evel is input to the CTSi p in (when the CTS function selected). ➀ D ummy data is written to the UARTi transmit buffer register. ➁ T he receive enable bit is set to “ 1. ” ➂ T he transmit enable bit is set to “ 1. ” 3. When using the CTS2/RTS2 pin, be sure that the D-A1 output enable bit (bit 1 at address 9616) = “0” (output disabled). 4. While the CTS i/RTS i s eparation is selected, the CLK i p in cannot be used. Accordingly, in the clock synchronous serial I/O mode, the CTS i/RTSi s eparation cannot be selected. 5. Writing to the UARTi baud rate register (BRGi) must be performed while transmission/reception halts. 6. When an internal clock is selected, do not use the RTS function because the RTS output is undefined. 7. When performing transmission, be sure to clear any of the TxD 0/P1 3, TxD 1/P1 7, and TxD2/P83 switch bits to “ 0 ” ( bits 2, 3, and 5 at address AC 16). 11-36 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode 11.4 Clock asynchronous serial I/O (UART) mode Table 11.4.1 lists the performance overview in the UART mode, and Table 11.4.2 lists the functions of I/O pins in this mode. Table 11.4.1 Performance overview in UART mode Item Transfer data format Start bit Character bit (Transfer data) Parity bit Stop bit Transfer rate Error detection When selecting internal clock When selecting external clock 1 bit 7 bits, 8 bits, or 9 bits 0 bit or 1 bit (Odd or Even can be selected.) 1 bit or 2 bits BRGi’s output divided by 16 Maximum 312.5 kbps 4 types (overrun, framing, parity, and summing): presence of an error can be detected only by check of the error sum flag. Functions Table 11.4.2 Functions of I/O pins in UART mode Method of selection Functions Pin name TxD 0/P13, TxD1/P17, or TxD 2/P8 3 s witch bit = “0.” ( Note) Serial data output pin TxD i ( P1 3, P1 7, P8 3) RxD i ( P1 2, P1 6, P82) Programmable I/O port pin TxD 0/P13, TxD1/P17, or TxD2/P8 3 s witch bit = “1.” Serial data input pin Port P1 or P8 direction register’s corresponding bit = “0” Programmable I/O port pin CLKi ( P1 1, P1 5, P81) – (Can be used as a programmable I/O port pin when performing only transmission.) BRGi’s count source input pin Internal/External clock select bit = “1” Programmable I/O port pin Internal/External clock select bit = “0” See Table 11.2.1. RTS output pin Programmable I/O port pin CTS i / RTS i ( P1 0 , P1 1 , CTS input pin P1 4, P1 5, P8 0, P8 1) Port P1 direction register: address 05 16 Port P8 direction register: address 14 16 Internal/External clock select bit: bit 3 at addresses 3016, 38 16, and B016 TxD 0/P13 s witch bit: bit 2 at address AC16 TxD 1/P17 s witch bit: bit 3 at address AC16 TxD 2/P83 s witch bit: bit 5 at address AC16 Note: The TxDi pin outputs “H” level while transmission is not performed after the UARTi’s operating mode is selected. 7 905 Group User’s Manual Rev.1.0 11-37 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode 11.4.1 Transfer rate (Frequency of transfer clock) The transfer rate is determined by the BRGi (addresses 31 16, 3916, B1 16). When “n” is set into BRGi, BRGi divides the count source frequency by (n + 1). The BRGi’s output is further divided by 16, and the resultant clock becomes the transfer clock. Accordingly, “n” is expressed by the following formula. F n= 16 ✕ B n: Value set in BRGi (00 16 t o FF 16) F: BRGi’s count source frequency (Hz) B: Transfer rate (bps) —1 An internal clock or an external clock can be selected as the BRGi’s count source with the internal/external clock select bit (bit 3 at addresses 30 16, 3816, B016). When an internal clock is selected, the clock selected with the BRG count source select bits (bits 0 and 1 at addresses 34 16 , 3C 16, B4 16) becomes the BRGi’s count source. When an external clock is selected, the clock input to the CLKi pin becomes the BRGi’s count source. Be sure to set the same transfer rate for both transmitter and receiver sides. Tables 11.4.3 and 11.4.4 list the setting examples of transfer rate. Each of the values, listed in these tables, realizes the actual transfer rate of which error toward an ideal transfer rate is within 1 %. Table 11.4.3 Setting examples of transfer rate (1) f sys = 1 9.6608 MHz Transfer Actual time BRGi’s set BRGi’s rate (bps) value: n ( Note) (bps) count source 63 (3F 16) 300.00 300 f 64 600 1200 2400 4800 9600 14400 19200 31250 f 16 f 16 f 16 f2 f2 f2 f2 127 (7F 16) 63 (3F 16) 31 (1F 16) 127 (7F 16) 63 (3F 16) 42 (2A 16) 31 (1F 16) 600.00 1200.00 2400.00 4800.00 9600.00 14288.37 19200.00 f2 19 (1316) 31250.00 f2 f2 f2 129 (8116) 64 (4016) 42 (2A16) 4807.69 9615.38 14534.88 BRGi’s count source value: n ( Note) 64 (4016) f 64 f 16 f 16 129 (8116) 64 (4016) f sys = 2 0 MHz BRGi’s set Actual time (bps) 300.48 600.96 1201.92 15 (0F 16) 38400.00 38400 f2 Note: T his applies when the peripheral device’s clock select bits 1, 0 (bits 7, 6 at address BC 16) = “00 2.” Table 11.4.4 Setting examples of transfer rate (2) Transfer rate (bps) 300 600 1200 2400 4800 9600 14400 19200 31250 BRGi’s count source f 64 f 16 f 16 f2 f2 f2 f2 f2 f2 f sys = 1 5.9744 MHz Actual time BRGi’s set value: n ( Note) BRGi’s f sys = 1 6 MHz BRGi’s set Actual time (bps) 300.48 600.96 1201.92 2403.85 4807.69 9615.38 19230.77 31250.00 38461.51 (bps) 300.00 600.00 1200.00 2400.00 4800.00 9600.00 14262.86 19200.00 31200.00 51 (33 16) 103 (67 16) 51 (33 16) 207 (CF 16) 103 (67 16) 51 (33 16) 34 (22 16) 25 (19 16) 15 (0F 16) count source value: n ( Note) 51 (3316) f 64 f 16 f 16 f2 f2 f2 f2 f2 103 (6716) 51 (3316) 207 (CF16) 103 (6716) 51 (3316) 25 (1916) 15 (0F 16) 12 (0C 16) 12 (0C 16) 38400.00 f2 38400 f2 Note: T his applies when the peripheral device’s clock select bits 1, 0 (bits 7, 6 at address BC 16) = “00 2.” 11-38 7905 Group User’s Manual Rev.1.0 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode s Error-permitted range of transfer baud During reception, the receive data input to the RxDi p in is taken at the rising edge of the transfer clock. (Refer to section “11.4.6 Receive operation.”) Accordingly, in order to receive data correctly, the stop bit must be input when the transfer clock of one-set receive data rises last. Figure 11.4.1 shows the relationship between the transfer clock and receive data. When the transfer rate of the receive data is faster than the rate of the transfer clock on the receiver side When the transfer rate of the receive data is slower than the rate of the transfer clock on the receiver side Transfer clock (Receiver side) ST ST D0 D0 D7 D7 SP SP SP must be detected at this last rising edge of the transfer clock. RxDi (Receive data) At the falling edge of ST, the transfer clock is generated, and reception starts. ✻ 1 clock 8 clocks 9.5 clocks 1 clock ✻ 1 period of BRGi’s count source (Maximum) According to the condition of the input timing, a maximum of this period (✻) can be omitted. ST : Start bit SP : Stop bit Fig. 11.4.1 Relationship between transfer clock and receive data Accordingly, the transfer rate of the receiver and transmitter sides must satisfy the following formula in order to receive data correctly. 1 1 ✕ (b – 1) + Bt F Br: Bt: F: b: < 1 1 ✕ (b – 0.5) + F Br < 1 ✕b Bt Transfer rate on receiver side (bps) Transfer rate on transmitter side (bps) BRGi ’ s count source frequency on receiver side (Hz) Entire bit number of one-set data (ex: 12 bits in the case of 1ST-8DATA-1PAR-2SP; See Figure 11.4.2.) Be sure to satisfy the above formula, and set the timing with enough margin. Also, the user shall make sufficient evaluation before actually using it. 7 905 Group User’s Manual Rev.1.0 11-39 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode 11.4.2 Transfer data format The transfer data format can be selected from formats shown in Figure 11.4.2. Bits 4 to 6 at addresses 3016, 3816 and B0 16 select the transfer data format. (See Figure 11.2.2.) Set the same transfer data format for both transmitter and receiver sides. Figure 11.4.3 shows an example of transfer data format. Table 11.4.5 lists each bit in transmit data. Transfer data length of 7 bits 1ST—7DATA 1SP 1ST—7DATA 2SP 1ST—7DATA—1PAR— 1SP 1ST—7DATA—1PAR— 2SP 1ST—8DATA 1SP 1ST—8DATA 2SP 1ST—8DATA—1PAR— 1SP 1ST—8DATA—1PAR— 2SP 1ST—9DATA 1SP 1ST—9DATA 2SP 1ST—9DATA—1PAR— 1SP 1ST—9DATA—1PAR— 2SP Transfer data length of 8 bits Transfer data length of 9 bits ST DATA PAR SP : Start bit : Character bit (Transfer data) : Parity bit : Stop bit Fig. 11.4.2 Transfer data format • 1ST–8DATA–1PAR–1SP Time Transmit/Receive data DATA (8 bits) ST LSB MSB PAR SP Next transmit/receive data (When continuously transferred) ST Fig. 11.4.3 Example of transfer data format Table 11.4.5 Each bit in transmit data Name ST Start bit DATA Character bit PAR Parity bit A signal that is added immediately after the character bits in order to improve data reliability. The level of this signal changes according to selection of odd/even parity in such a way that the sum of “1”s in the sum of this bit and character bits is always an odd or even number. SP Stop bit “H” level signal equivalent to 1 or 2 character bits. This is added immediately after the character bits (or parity bit when parity is enabled). It indicates completion of data transmission. Functions “L” signal equivalent to 1 character bit. This is added immediately before the character bits. It indicates start of data transmission. Transmit data which is set in the UARTi transmit buffer register. 11-40 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode 11.4.3 Method of transmission Figure 11.4.4 shows an initial setting example for relevant registers when transmitting. The difference depending on the transfer data length (7 bits, 8 bits, or 9 bits) is the transmit data ’s length only. When selecting a 7- or 8-bit data length, be sure to set the transmit data into the low-order byte of the UARTi transmit buffer register. When selecting a 9-bit data length, be sure to set the transmit data into the low-order byte and bit 0 of the high-order byte. Transmission is started when all of the following conditions ( ➀ t o ➂ ) are satisfied: ➀ T ransmit data is present in the UARTi transmit buffer register (transmit buffer empty flag = “ 0 ” ). ➁ T ransmit is enabled (transmit enable bit = “ 1 ” ). ➂ T he CTS i p in ’ s input level is “ L ” ( when the CTS function selected). Note: W hen the CTS function is not selected, condition ➂ i s ignored. By connecting the RTSi pin (receiver side) and CTS i pin (transmitter side), the timing of transmission and that of reception can be matched. For details, refer to section “ 11.4.6 Receive operation.” When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer to “ CHAPTER 6. INTERRUPTS.” Figure 11.4.5 shows writing data after transmission is started, and Figure 11.4.6 shows detection of transmit completion. 7 905 Group User ’ s Manual Rev.1.0 11-41 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) UART2 transmit/receive mode register (Address B016) b7 b0 UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) UART2 baud rate register (BRG2) (Address B116) b7 b0 1 Selection of clock synchronous serial I/O mode b2 b1 b0 1 0 0: UART mode (7 bits) 1 0 1: UART mode (8 bits) 1 1 0: UART mode (9 bits) Internal/External clock select bit 0: Internal clock 1: External clock Stop bit length select bit 0: 1 stop bit 1: 2 stop bits Odd/Even parity select bit 0: Odd parity 1: Even parity Parity enable bit 0: Parity is disabled. 1: Parity is enabled. Sleep select bit 0: Sleep mode cleared (invalid) 1: Sleep mode selected Can be set to “0016” to “FF16” i CTSi/RTSi are used together. CTSi/RTSi are separated. Port P1 direction register (Address 516) b7 b0 0 0 Pin CTS0 Pin CTS1 Port P8 direction register (Address 1416) b7 b0 0 Pin CTS2 UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) UART2 transmit/receive control register 0 (Address B416) b7 b0 UART0 transmit interrupt control register (Address 7116) UART1 transmit interrupt control register (Address 7316) UART2 transmit interrupt control register (Address F116) b7 b0 00 BRG count source select bits b1 b0 0 0: f2 0 1: f16 1 0: f64 1 1: f512 CTS/RTS function select bit 0: CTS function selected 1: RTS function selected CTS/RTS enable bit 0: CTS/RTS function is enabled. 1: CTS/RTS function is disabled Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. UART0 transmit buffer register (Addresses 3316, 3216) UART1 transmit buffer register (Addresses 3B16, 3A16) UART2 transmit buffer register (Addresses B316, B216) b15 b8 b7 b0 Serial I/O pin control register (Address AC16) b7 b0 Transmit data is set. CTS0/RTS0 separate select bit 0: CTS0/RTS0 are used together. 1: CTS0/RTS0 are separated (Note). CTS1/RTS1 separate select bit 0: CTS1/RTS1 are used together. 1: CTS1/RTS1 are separated (Note). TxD0/P13 switch bit 0: Functions as TxD0. TxD1/P17 switch bit 0: Functions as TxD1. CTS2/RTS2 separate select bit 0: CTS2/RTS2 are used together. 1: CTS2/RTS2 are separated (Note). TxD2/P83 switch bit 0: Functions as TxD2. Note: The CLKi pin cannot be used when the CTSi/RTSi separation is selected. (Refer to “[Precaution for clock asynchronous serial I/O (UART) mode].”) UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) UART2 transmit/receive control register 1 (Address B516) b7 b0 1 Transmit enable bit 1: Transmission enabled Transmission starts. (If the CTS function selected, transmission starts when the CTSi pin’s input level becomes “L.”) Fig. 11.4.4 Initial setting example for relevant registers when transmitting 11-42 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode [When not using interrupts] [When using interrupts] A UARTi transmit interrupt request occurs when the transmission starts. (when the UARTi transmit buffer register becomes empty.) Checking state of UARTi transmit buffer register UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) UART2 transmit/receive control register 1 (Address B516) b7 b0 b0 UARTi transmit interrupt 1 Transmit buffer empty flag 0: Data is present in transmit buffer register. 1: No data is present in transmit buffer register. (Writing of next transmit data is possible.) Writing of next transmit data UART0 transmit buffer register (Addresses 3316, 3216) UART1 transmit buffer register (Addresses 3B16, 3A16) UART2 transmit buffer register (Addresses B316, B216) b15 b8 b7 b0 Note: This figure shows the bits and registers required for processing. See Figures 11.4.7 to 11.4.9 for the change of flag state and the occurrence timing of an interrupt request. Transmit data is set. Fig. 11.4.5 Write operation of data after transmission start 7 905 Group User ’ s Manual Rev.1.0 11-43 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode [When not using interrupts] [When using interrupts] A UARTi transmit interrupt request occurs when the transmission starts. Checking start of transmission UART0 transmit interrupt control register (Address 7116) UART1 transmit interrupt control register (Address 7316) UART2 transmit interrupt control register (Address F116) b7 b0 UARTi transmit interrupt Interrupt request bit 0: No interrupt requested 1: Interrupt requested (Transmission has started.) Checking completion of transmission. UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) UART2 transmit/receive control register 0 (Address B416) b7 b0 Note: This figure shows the bits and registers required for processing. See Figures 11.4.7 to 11.4.9 for the change of flag state and the occurrence timing of an interrupt request. 0 0 Transmit register empty flag 0: Transmission is in progress. 1: Transmission is completed. Processing at completion of transmission Fig. 11.4.6 Detect operation of transmit completion 11-44 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode 11.4.4 Transmit operation When the receive conditions described in section “11.4.3 Method of transmission” have been satisfied, a transfer clock is generated, and the following operations are automatically performed after 1 cycle of the transfer clock or less has passed. •The UARTi transmit buffer register ’ s contents are transferred to the UARTi transmit register. • The transmit buffer empty flag is set to “ 1. ” • The transmit register empty flag is cleared to “ 0. ” • A UARTi transmit interrupt request occurs, and the interrupt request bit is set to “ 1. ” The transmit operations are described below: ➀ D ata in the UARTi transmit register is transmitted from the TxD i p in. ➁ T his data is transmitted bit by bit sequentially in order of ST → DATA (LSB) → ••• →DATA (MSB) → PAR →SP according to the transfer data format. ➂ The transmit register empty flag is set to “1” at the center of the stop bit (or the second stop bit if 2 stop bits selected). This indicates completion of transmission. Additionally, whether the transmit conditions for the next data are satisfied or not is examined. When the transmit conditions for the next data are satisfied in step ➂, the start bit is generated following the stop bit, and the next data is transmitted. When performing transmission continuously, be sure to set the next transmit data in the UARTi transmit buffer register during transmission (i.e. when the transmit register empty flag = “ 0 ” ). When the transmit conditions for the next data are not satisfied, the TxD i p in outputs “ H ” l evel and the transfer clock stops. Figures 11.4.7 and 11.4.8 show examples of transmit timing when the transfer data length = 8 bits, and Figure 11.4.9 shows an example of transmit timing when the transfer data length = 9 bits. 7 905 Group User ’ s Manual Rev.1.0 11-45 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode Tc Transfer clock Transmit enable bit Data is set in UARTi transmit buffer register. Transmit buffer empty flag UARTi transmit register ← UARTi transmit buffer register TENDi Stopped because transmit enable bit = “0” TxDi Transmit register empty flag UARTi transmit interrupt request bit ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 Cleared to “0” when interrupt request is accepted or cleared to “0” by software. The above timing diagram applies when the following conditions are satisfied: q Parity enabled q 1 stop bit q CTS function not selected TENDi: Next transmit conditions are examined when this signal level becomes “H.” (TENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc: 16 (n + 1)/fi or 16 (n + 1)/fEXT fi: BRGi’s count source frequency (internal clock) fEXT: BRGi’s count source frequency (external clock) n: Value set in BRGi ST: Start bit D0 to D7: Transfer data P: Parity bit ST: Stop bit Fig. 11.4.7 Example of transmit timing when transfer data length = 8 bits (when parity enabled, 1 stop bit selected, CTS function not selected) Tc Transfer clock Transmit enable bit Data is set in UARTi transmit buffer register. Transmit buffer empty flag UARTi transmit register ← UARTi transmit buffer register CTSi TENDi Stopped because CTSi = “H” Stopped because transmit enable bit = “0” P SP ST D0 D1 TxDi Transmit register empty flag ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 UARTi transmit interrupt request bit Cleared to “0” when interrupt request is accepted or cleared to “0” by software. The above timing diagram applies when the following conditions are satisfied: q Parity enabled q 1 stop bit q CTS function selected TENDi: Next transmit conditions are examined when this signal level becomes “H.” (TENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc = 16 (n + 1)/fi or 16 (n + 1)/fEXT fi: BRGi’s count source frequency (internal clock) fEXT: BRGi’s count source frequency (external clock) n: Value set in BRGi ST: Start bit D0 to D7: Transfer data P: Parity bit ST: Stop bit Fig. 11.4.8 Example of transmit timing when transfer data length = 8 bits (when parity enabled, 1 stop bit and selecting CTS function selected) 11-46 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode Tc Transfer clock Transmit enable bit Data is set in UARTi transmit buffer register. Transmit buffer empty flag UARTi transmit register ← UARTi transmit buffer register Stopped because transmit enable bit = “0” TENDi TxDi Transmit register empty flag UARTi transmit interrupt request bit ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 Cleared to “0” when interrupt request is accepted or cleared to “0” by software. The above timing diagram applies when the following conditions are satisfied: q Parity disabled q 2 stop bits q CTS function not selected TENDi: Next transmit conditions are examined when this signal level becomes “H.” (TENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc = 16 (n + 1)/fi or 16 (n + 1)/fEXT fi: BRGi count source frequency (internal clock) fEXT: BRGi count source frequency (external clock) n: Value set in BRGi ST: Start bit D0 to D7: Transfer data P: Parity bit ST: Stop bit Fig. 11.4.9 Example of transmit timing when transfer data length = 9 bits (when parity disabled, 2 stop bits selected, CTS function not selected) 7 905 Group User ’ s Manual Rev.1.0 11-47 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode 11.4.5 Method of reception Figure 11.4.10 shows an initial setting example for relevant registers when receiving. Reception is started when all of the following conditions ( ➀ a nd ➁) have been satisfied: ➀ R eception is enabled (receive enable bit = “ 1 ” ). ➁ T he start bit (its falling edge) is detected. By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched. For details, refer to section “ 11.4.6 Receive operation. ” When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer to “ CHAPTER 6. INTERRUPTS. ” Figure 11.4.11 shows processing after reception is completed. 11-48 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) UART2 transmit/receive mode register (Address B016) b7 b0 1 Selection of clock synchronous serial I/O mode b2 b1 b0 UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) UART2 baud rate register (BRG2) (Address B116) b7 b0 1 0 0: UART mode (7 bits) 1 0 1: UART mode (8 bits) 1 1 0: UART mode (9 bits) Internal/External clock select bit 0: Internal clock 1: External clock Stop bit length select bit 0: 1 stop bit 1: 2 stop bits Odd/Even parity select bit 0: Odd parity 1: Even parity Parity enable bit 0: Parity is disabled. 1: Parity is enabled. Sleep select bit 0: Sleep mode cleared (invalid) 1: Sleep mode selected ✻ Set the same transfer data format as that of the transmitter side. Can be set to “0016” to “FF16” Port P1 direction register (Address 516) b7 b0 0 0 Pin RxD0 Pin RxD1 Port P8 direction register (Address 1416) b7 b0 0 Pin RxD2 UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) UART2 transmit/receive control register 0 (Address B416) b7 b0 UART0 receive interrupt control register (Address 7216) UART1 receive interrupt control register (Address 7416) UART2 receive interrupt control register (Address F216) b7 b0 00 BRG count source select bits b1 b0 0 0: f2 0 1: f16 1 0: f64 1 1: f512 CTS/RTS function select bit 0: CTS function selected 1: RTS function selected CTS/RTS enable bit 0: CTS/RTS function is enabled. 1: CTS/RTS function is disabled. UARTi receive interrupt mode select bit 0: Reception interrupt 1: Reception error interrupt Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) UART2 transmit/receive control register 1 (Address B516) b7 b0 1 Transmit enable bit 1: Transmission enabled Serial I/O pin control register (Address AC16) b7 b0 CTS0/RTS0 separate select bit 0: CTS0/RTS0 are used together. 1: CTS0/RTS0 are separated (Note 1). CTS1/RTS1 separate select bit 0: CTS1/RTS1 are used together. 1: CTS1/RTS1 are separated (Note 1). TxD0/P13 switch bit (Note 2) 0: Functions as TxD0. 1: Functions as P13. TxD1/P17 switch bit (Note 2) 0: Functions as TxD1. 1: Functions as P17. CTS2/RTS2 separate select bit 0: CTS2/RTS2 are used together. 1: CTS2/RTS2 are separated (Note 1). TxD2/P83 switch bit (Note 2) 0: Functions as TxD2. 1: Functions as P83. Reception will start when the start bit (’s falling edge) is detected. Note 1: The CLKi pin cannot be used when the CTSi/RTSi separation is selected. (Refer to “[Precaution for clock asynchronous serial I/O (UART) mode].”) 2: When performing reception only, if these bits are set to “1,” the TxDi pin can be used as a programmable I/O port pin. Fig. 11.4.10 Initial setting example for relevant registers when receiving 7 905 Group User ’ s Manual Rev.1.0 11-49 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode [When not using interrupts] [When using interrupts] (Note 1) A UARTi receive interrupt request occurs when reception is completed. Checking completion of reception UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) UART2 transmit/receive control register 1 (Address B516) b7 b0 UARTi receive interrupt 1 Receive complete flag 0 : Reception not completed 1 : Reception completed Checking error UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) UART2 transmit/receive control register 1 (Address B516) b7 b0 1 Framing error flag Parity error flag Error sum flag 0 : No error 1 : Error detected Reading of receive data UART0 receive buffer register (Addresses 3716, 3616) UART1 receive buffer register (Addresses 3F16, 3E16) UART2 receive buffer register (Addresses B716, B616) b15 b8 b7 b0 0000000 Read out receive data. Checking error UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) UART2 transmit/receive control register 1 (Address B516) b7 b0 1 Overrun error flag 0 : No overrun error 1 : Overrun error detected Processing after reading out receive data Notes 1: When performing the processing after the reception is completed, using an interrupt, be sure to select the receive interrupt (UARTi receive interrupt mode select bit = “0”). 2: This figure shows the bits and registers required for the processing. See Figure 11.4.13 for the change of flag state and the occurrence timing of an interrupt request. Fig. 11.4.11 Processing after reception is completed 11-50 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode 11.4.6 Receive operation When the receive enable bit is set to “1,” the UARTi enters the receive-enabled state. Then, reception will start when ST ( ’ s falling edge) is detected and a transfer clock is generated. If the RTS function selected, when connecting the RTS i p in to the CTSi p in of the transmitter side, the timing of transmission and that of reception can be matched. If the RTS function selected, the RTS i pin’s output level becomes as described below. When the receive enable bit = “0,” if one of the following is performed, the RTSi pin’s output level becomes “ L ” a nd informs of the transmitter side that reception has become enabled: • T he receive enable bit is set to “ 1. ” • T he low-order byte of the UARTi receive buffer register is read out. When the receive enable bit = “ 1, ” i f the low-order byte of the UARTi receive buffer register is read out, the RTS i p in ’ s output level becomes “ L. ” Accordingly, when performing reception continuously, an overrun occurrence can be avoided because the RTS output level does not become “ L ” u ntil the receive data is read out. When reception has started, the RTS i p in ’ s output level becomes “ H. ” Figure 11.4.12 shows a connection example. Transmitter side TxDi RxDi Receiver side TxDi RxDi CTSi RTSi Fig. 11.4.12 Connection example The receive operation is described below. ➀ T he signal input to the RxD i p in is taken into the most significant bit of the UARTi receive register, synchronously with the transfer clock ’ s rising edge. ➁ T he contents of the UARTi receive register are shifted, bit by bit, to the right. ➂ S teps ➀ a nd ➁ a re repeated at each rising edge of the transfer clock. ➃ When one set of data has been prepared, in other words, when the shift operation has been performed several times according to the selected data format, the UARTi receive register’s contents are transferred to the UARTi receive buffer register. ➄ S imultaneously with step ➃ , the receive complete flag is set to “ 1. ” A dditionally, when the receive interrupt is selected (UARTi receive interrupt mode select bit = “ 0 ” ), a UARTi receive interrupt request occurs and its interrupt request bit is set to “ 1. ” The receive complete flag is cleared to “ 0 ” w hen the low-order byte of the UARTi receive buffer register has been read out. Figure 11.4.13 shows an example of receive timing when the transfer data length = 8 bits. 7 905 Group User ’ s Manual Rev.1.0 11-51 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode BRGi’s count source Receive enable bit Stop bit RxDi Start bit D0 D1 D7 Sampled “L” Transfer clock Receive complete flag At falling edge of start bit, the transfer clock is generated and reception started. Received data taken in UARTi receive register → UARTi receive buffer register RTSi UARTi receive interrupt request bit UARTi receive buffer register’s reading out The above timing diagram applies when the following conditions are satisfied: q Parity disabled q 1 stop bit q RTS function selected Cleared to “0” when interrupt request is accepted or cleared to “0” by software. Fig. 11.4.13 Example of receive timing when transfer data length = 8 bits (when parity disabled, 1 stop bit and RTS function selected) 11-52 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode 11.4.7 Processing on detecting error In the UART mode, 3 types of errors can be detected. Each error can be detected when the data in the UARTi receive register is transferred to the UARTi receive buffer register, and the corresponding error flag is set to “ 1. ” W hen any error occurs, the error sum flag is set to “ 1. ” A ccordingly, presence of errors can be judged by using the error sum flag. Table 11.4.6 lists the conditions for setting each error flag to “ 1 ” a nd method to clear it to “ 0. ” Additionally, when the receive error interrupt is selected (UARTi receive interrupt mode select bit = “ 1 ” ), the UARTi receive interrupt request bit is set to “1” only when each error has occurred. When the receive interrupt is selected (UARTi receive interrupt mode select bit = “ 0 ” ), the UARTi receive interrupt request bit is set to “1” when reception has been completed or when a framing or parity error has occurred. (Even when an overrun error has occurred, this bit does not change). Table 11.4.6 Conditions for setting each error flag to “ 1 ” a nd method to clear it to “ 0 ” Error flag Overrun error flag Conditions for setting Method to clear When the next data is prepared in the • C lear the receive enable bit to “ 0. ” UARTi receive register with the receive complete flag = “ 1 ” ( i.e. data is present in the UARTi receive buffer register). In other words, when the next data is prepared before the contents of the UARTi receive buffer register are read out (Note). Framing error flag When the number of detected stop bits • C lear the receive enable bit to “ 0. ” does not match the set number of stop • Read out the low-order byte of the UARTi bits. receive buffer register. When the sum of “ 1 ” s in the sum of the • C lear the receive enable bit to “ 0. ” parity bit and character bits does not match • Read out the low-order byte of the UARTi the set number of “ 1 ” s. receive buffer register. When any error listed above has occurred. • C lear the all error flags, which are overrun, framing and parity error flags. Note: T he next data is written into the UARTi receive buffer register. When an error occurs during reception, be sure to initialize the error flag and the UARTi receive buffer register, and then perform reception again. When it is necessary to perform retransmission owing to an error which has occurred on the receiver side during transmission, be sure to set the UARTi transmit buffer register again, and then perform the retransmission. The method to initialize the UARTi receive buffer register and that to set the UARTi transmit buffer register again are described below. (1) Method to initialize UARTi receive buffer register ➀ C lear the receive enable bit to “ 0 ” ( reception disabled). ➁ S et the receive enable bit to “ 1 ” a gain (reception enabled). (2) Method to set UARTi transmit buffer register again ➀ C lear the serial I/O mode select bits to “ 000 2” ( serial I/O invalid). ➁ S et the serial I/O mode select bits again. ➂ Set the transmit enable bit to “1” (transmission enabled), and set the transmit data to the UARTi transmit buffer register. Parity error flag Error sum flag 7 905 Group User ’ s Manual Rev.1.0 11-53 SERIAL I/O 11.4 Clock asynchronous serial I/O (UART) mode 11.4.8 Sleep mode This mode is used to transfer data between the specified microcomputers, which are connected by using UARTi. The sleep mode is selected by setting the sleep select bit (bit 7 at addresses 3016, 3816 and B0 16) to “ 1 ” w hen receiving. In the sleep mode, receive operation is performed when the MSB (D8 when the transfer data = 9-bit length, D 7 w hen it is 8-bit length, D 6 w hen it is 7-bit length) of the receive data is “ 1. ” R eceive operation is not performed when the MSB is “0.” (The UARTi receive register ’s contents are not transferred to the UARTi receive buffer register. Additionally, the receive complete flag and each error flag do not change, and no UARTi receive interrupt request occurs.) The following shows an usage example of the sleep mode when the transfer data = 8-bit length. ➀ Be sure to set the same transfer data format for the master and slave microcomputers. Additionally, be sure to select the sleep mode for the slave microcomputers. ➁ T hen, transmit the data, of which structure is as follows, from the master microcomputer: • B it 7 = “ 1 ” • B its 6 to 0 indicate the address of the slave microcomputer to be communicated ➂ Each slave microcomputer receives the data described in step ➁. (At this time, a UARTi receive interrupt request occurs.) ➃ Be sure to check for each slave microcomputer, in the interrupt routine, whether bits 6 to 0 of the receive data match its own address. ➄ F or the slave microcomputer of which address matches bits 6 to 0 of the receive data, terminate the sleep mode. (Do not terminate the sleep mode for the other slave microcomputers.) By performing steps ➁ t o ➄, “ the microcomputer which performs transfer ” i s specified. ➅ T ransmit the data of which bit 7 = “ 0 ” f rom the master microcomputer. (Only one slave microcomputer specified in steps ➁ t o ➄ c an receive this data. The other microcomputers do not receive this data.) ➆ By repeating step ➅, continuous transfer can be performed between two specific microcomputers. When communicating with another slave microcomputer, perform steps ➁ t o ➄ i n order to specify the new slave microcomputer. Master Data is transferred between the master microcomputer and one specific slave microcomputer selected from multiple slave microcomputers. Slave A Slave B Slave C Slave D Fig. 11.4.14 Sleep mode 11-54 7905 Group User ’ s Manual Rev.1.0 SERIAL I/O [Precautions for clock asynchronous serial I/O (UART) mode] [Precautions for clock asynchronous serial I/O (UART) mode] 1. When using pin CTS2/RTS 2, be sure that the D-A 1 output enable bit (bit 1 at address 96 16) = “0” (output disabled). 2. When separating CTSi/RTSi, the CLK i p in cannot be used. Accordingly, when separating CTS i/RTS i i n UART mode, be sure to select an internal clock. 3. Writing to the UARTi baud rate register (BRGi) must be performed while transmission/reception halts. 4. When transmitting, be sure to clear the TxD 0/P1 3, TxD 1/P1 7, or TxD 2/P8 3 s witch bit (bit 2, 3, or 5 at address AC16) to “ 0. ” 7 905 Group User ’ s Manual Rev.1.0 11-55 SERIAL I/O [Precautions for clock asynchronous serial I/O (UART) mode] MEMORANDUM 11-56 7905 Group User ’ s Manual Rev.1.0 CHAPTER 12 A-D CONVERTER 12.1 12.2 12.3 12.4 Overview Block description A-D conversion method Absolute accuracy and Differential non-linearity error 12.5 Comparison voltage in 8-bit resolution mode 12.6 Comparator function 12.7 One-shot mode 12.8 Repeat mode 12.9 Single sweep mode 12.10 Repeat sweep mode 0 12.11 Repeat sweep mode 1 [Precautions for A-D converter] A -D CONVERTER 12.1 Overview 12.1 Overview The A-D conversion is performed in the 8-bit resolution mode or the 10-bit resolution mode. Also, the input voltage can be compared with the set value by using the A-D converter (in other words, the comparator function). Whether to perform the A-D conversion or comparison can be selected for each pin. ❈ In chapter 12, the operations common to the A-D converter’s functions (8-bit resolution, 10-bit resolution, comparator) are simply referred to as “operation.” Table 12.1.1 lists the performance specifications of the A-D converter. Table 12.1.1 Performance specifications of A-D converter Item Performance specifications A-D conversion method Successive approximation conversion method Resolution Either of 8-bit or 10-bit resolution can be selected by software. Absolute accuracy 8-bit resolution mode : ±2 LSB 10-bit resolution mode : ±3 LSB Analog input pin (Note) 12 pins (AN0 to AN11) Conversion rate per analog input pin 8-bit resolution mode : 49 φAD cycles 10-bit resolution mode : 59 φAD cycles Comparator function Comparison operation Comparison between the set value and analog input voltage Comparison rate per analog input pin 14 φAD cycles φ AD : A -D converter’s operation clock Note: For each of analog input pin ANi (i = 0 to 11), whether to use pin ANi as an input pin of the A-D converter or as that of the comparator can be selected by using the comparator function select register 0 (address DC16) or the comparator function select register 1 (address DD16). (1) 8-bit resolution mode The input voltage from pin AN i ( i = 0 to 11) is A-D converted, and the 8-bit A-D conversion result is stored in A-D register i. (Refer to sections “ 12.3 A-D conversion method” a nd “ 12.5 Comparison voltage in 8-bit resolution mode.”) (2) 10-bit resolution mode The input voltage from pin AN i i s A-D converted, and the 10-bit A-D conversion result is stored in A-D register i. (Refer to section “ 12.3 A-D conversion method.”) (3) Comparator function The 8-bit value which has been set in A-D register i is compared with the voltage input from pin ANi; and then, the result of comparison is stored into the ANi p in comparator result bit. (Refer to section “12.6 Comparator function.”) 12-2 7905 Group User’s Manual Rev.1.0 A -D CONVERTER 12.1 Overview (4) Operation modes The A-D converter is equipped with the following 4 modes. The A-D conversion and comparison (in other words, the comparator function) are performed in the same operation modes. The operation mode depends on the analog input pin. s O ne-shot mode This mode is used to perform the operation once for a voltage input from one selected analog input pin. This mode can be used with analog input pin AN i ( i = 0 to 11). s R epeat mode This mode is used to perform the operation repeatedly for a voltage input from one selected analog input pin. This mode can be used with analog input pin AN i ( i = 0 to 11). s S ingle sweep mode This mode is used to perform the operation for voltages input from multiple pins selected from analog input pins AN j ( j = 0 to 7), one at a time. This mode can be used with analog input pins ANj ( j = 0 to 7). s R epeat sweep mode 0 This mode is used to perform the operation repeatedly for voltages input from multiple pins selected from analog input pins AN j ( j = 0 to 7) . s R epeat sweep mode 1 This mode is used to perform the operation repeatedly for voltages input from analog input pins ANj (j = 0 to 7). In this mode, analog input pins are divided into two groups: frequently-used pins and nonfrequently-used pins. This mode can be used with analog input pins AN j ( j = 0 to 7). 7905 Group User’s Manual Rev.1.0 12-3 A -D CONVERTER 12.2 Block description 12.2 Block description Figure 12.2.1 shows the block diagram of the A-D converter. Registers relevant to the A-D converter are described below. f1 Selection of A-D conversion frequency (1 ,1) (1 ,0) f2 VREF connection select bit 1/ 2 1/ 2 Vref (0 ,1) (0 ,0) φAD VR EF AV SS 0 1 A-D conversion frequency (φAD) select bits 1, 0 A-D control register 2 Comparator function select register 1 Comparator function select register 0 Resistor ladder network A-D control register 1 Selector 1 A-D control register 0 Control circuit Selector Successive approximation register Comparator result register 1 Comparator result register 0 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 A-D register 8 A-D register 9 A-D register 10 A-D register 11 Comparator Decoder Data bus (odd) Data bus (even) AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 AN 8 AN 9 AN 10 AN 11 Selector Fig. 12.2.1 Block diagram of A-D converter 12-4 7905 Group User’s Manual Rev.1.0 A -D CONVERTER 12.2 Block description 12.2.1 A-D control registers 0, 1, and 2 Figures 12.2.2, 12.2.3 and 12.2.4 show the structures of the A-D control registers 0, 1 and 2, respectively. b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 0 (Address 1E16) Bit 0 1 2 3 4 5 6 7 Fix this bit to “0.” A-D conversion start bit 0 : A-D conversion halts. 1 : A-D conversion starts. Bit name b2 b1 b0 0 Function At reset Undefined Undefined Undefined (Note 2) 0 0 0 0 0 RW RW RW RW (Note 3) RW R/W RW RW RW Analog input pin select bits 0 0 0 : AN0 is selected. (Valid in the one-shot and repeat 0 0 1 : AN1 is selected. 0 1 0 : AN2 is selected. modes.) (Note 1) 0 1 1 : AN3 is selected. 1 0 0 : AN4 is selected. 1 0 1 : AN5 is selected. 1 1 0 : AN6 is selected. 1 1 1 : AN7 is selected. b4 b3 A-D operation mode select bits 0 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 or 1 A-D conversion frequency ( φ AD ) See Table 12.2.1. select bit 0 Notes 1: When using pins AN0 to AN7, be sure to fix bit 3 of the analog input pin select bits 1 (bits 3 to 0 at address DB16) to “0.” Setting bit 3 of the analog input pin select bits 1 to “1” invalidates these bits. Also, these bits are invalid in the single sweep mode, repeat sweep mode 0 and repeat sweet mode 1. (Each may be either “0” or “1.”) 2: When using pin AN7, be sure that the D-A0 output enable bit (bit 0 at address 9616) = “0” (output disabled). 3: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. 4: Writing to each bit (except writing of “0” to bit 6) of the A-D control register 0 must be performed while the A-D converter halts, regardless of the A-D operation mode. Fig. 12.2.2 Structure of A-D control register 0 7905 Group User ’ s Manual Rev.1.0 12-5 A -D CONVERTER 12.2 Block description b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 1 (Address 1F16) Bit 0 Bit name A-D sweep pin select bits (Valid in the single sweep mode, b1 b0 0 Function Single sweep mode/Repeat sweep mode 0 At reset 1 R/W RW 1 0 0 : Pins AN0 and AN1 (2 pins) repeat sweep mode 0 and 0 1 : Pins AN0 to AN3 (4 pins) repeat sweep mode 1.) (Note 1) 1 0 : Pins AN0 to AN5 (6 pins) 1 1 : Pins AN0 to AN7 (8 pins) (Note 2) Repeat sweep mode 1 (Note 3) b1 b0 1 RW 0 0 : Pin AN0 (1 pin) 0 1 : Pins AN0 and AN1 (2 pins) 1 0 : Pins AN0 to AN2 (3 pins) 1 1 : Pins AN0 to AN3 (4 pins) 2 A-D operation mode select bit 1 0 : Repeat sweep mode 0 (Used in the repeat sweep mode 0 1 : Repeat sweep mode 1 and repeat sweep mode 1.)(Note 4) Resolution select bit 0 : 8-bit resolution mode 1 : 10-bit resolution mode A-D conversion frequency (φAD) select bit 1 See Table 12.2.1. Fix this bit to “0.” VREF connection select bit (Note 5) The value is “0” at reading. 0 : Pin VREF is connected. 1 : Pin VREF is disconnected. 0 RW 3 4 5 6 7 0 0 0 0 0 RW RW RW RW – Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either “0” or “1.”) 2: When using pin AN7, be sure that the D-A0 output enable bit (bit 0 at address 9616) = “0” (output disabled). 3: Be sure to select frequently-used analog input pins in the repeat sweep mode 1. 4: Fix this bit to “0” in the one-shot mode, repeat mode, and single sweep mode. 5: When this bit is cleared from “1” to “0,” be sure to start the A-D conversion after an interval of 1 µs or more has elapsed. 6: Writing to each bit of the A-D control register 1 must be performed while the A-D converter halts, regardless of the A-D operation mode. Fig. 12.2.3 Structure of A-D control register 1 12-6 7905 Group User ’ s Manual Rev.1.0 A -D CONVERTER 12.2 Block description b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 2 (Address DB16) Bit 0 1 2 3 7 to 4 Fix these bits to “0000.” Bit name Analog input pin select bits 1 (Note 1) b3 b2 b1 b0 0000 Function 0 ✕✕✕ : Pins AN0 to AN7 are selected. 1 0 0 0 : Pin AN8 is selected. 1 0 0 1 : Pin AN9 is selected. 1 0 1 0 : Pin AN10 is selected. 1 0 1 1 : Pin AN11 is selected. 1 1 0 0 : Do not select. (Note 2) (Note 3) (Note 4) (Note 5) (Note 6) At reset 0 0 0 0 0 R/W RW RW RW RW RW 1 1 1 1 : Do not select. ✕ : They may be either “0” or “1.” Note 1: When using pins AN0 to AN7, regardless of the A-D operation mode, be sure to fix bit 3 to “0.” Also, pins AN8 to AN11 are used only in the one-shot mode and repeat mode. 2: Select pins AN0 to AN7 at bits 2 to 0 of A-D control register 0 (address 1E16). 3: When using pin AN8, be sure that the D-A1 output enable bit (bit 1 at address 9616) = “0” (output disabled). Also, be sure not to use pin CTS2/RTS2. 4: When using pin AN9, be sure not to use pin CTS2/CLK2. 5: When using pin AN10, be sure not to use pin RXD2. 6: When using pin AN11, be sure not to use pin TXD2. 7: Writing to each bit of A-D control register 2 must be performed while the A-D conversion halts, regardless of the A-D operation mode. Fig. 12.2.4 Structure of A-D control register 2 7905 Group User ’ s Manual Rev.1.0 ••• 12-7 A -D CONVERTER 12.2 Block description (1) Analog input pin select bits 0 (bits 0 to 2 at address 1E16), analog input pin select bits 1 (bits 3 to 0 at address DB 16) These bits are used to select an analog input pin. Pins which are not selected as analog input pins serve as programmable I/O port pins or I/O pins of other internal peripheral devices, which are multiplexed. When using pins AN0 t o AN 7, be sure to fix bit 3 of the analog input pin select bits 1 (bits 3 to 0 at address DB 16) to “ 0, ” r egardless of the A-D operation mode. Pins AN 8 t o AN 11 c an be used only in the one-shot mode and repeat mode. Also, these bits must be specified again if the user switches the operation mode to the one-shot mode or repeat mode after the operation is performed in the single sweep mode, repeat sweep mode 0, or repeat sweep mode 1. (2) A-D operation mode select bits 0 (bits 3 and 4 at address 1E16), A-D operation mode select bit 1 (bit 2 at address 1F 16) These bits are used to select the operation mode of the A-D converter. When using the one-shot mode, repeat mode, or single sweep mode, be sure to fix the A-D operation mode select bit 1 to “ 0 ” . (3) A-D conversion start bit (bit 6 at address 1E 16) Setting this bit to “ 1 ” g enerates a trigger, causing the A-D converter to start its operation. Clearing this bit to “ 0 ” c auses the A-D converter to halt its operation. In the one-shot mode or single sweep mode, this bit is cleared to “0” when the operation is completed. In the repeat mode, repeat sweep mode 0, or repeat sweep mode 1, the A-D converter continues its operation until this bit is cleared to “ 0 ” b y software. (4) A-D conversion frequency ( φAD ) select bit 0 (bit 7 at address 1E16), A-D conversion frequency (φ AD) select bit 1 (bit 4 at address 1F 16) These bits are used to select the operation clock (φ AD) of the A-D converter. Table 12.2.1 lists the conversion time per one analog input pin. Since the A-D converter’s comparator consists of capacity coupling amplifiers, be sure to keep that Table 12.2.1 Conversion time per one analog input pin A-D conversion frequency (φAD) select bit 1 0 0 1 1 A-D conversion frequency (φAD) select bit 0 0 1 0 1 Conversion time (µs) (Note) fsys = 20 MHz Comparator 8-bit resolution 10-bit resolution function mode mode 19.60 23.60 5.60 9.80 11.80 2.80 4.90 5.90 1.40 2.45 Do not select. 0.70 φAD f2 divided by 4 f2 divided by 2 f2 f1 Note: T his applies when the peripheral devices ’ c lock select bits 0, 1 (bits 6, 7 at address BC 16) = “ 00 2. ” φ AD ≥ 2 50 kHz while the A-D converter is active. (5) A-D sweep pin select bits (bits 0 and 1 at address 1F 16) These bits are used to select analog input pins in the single sweep mode, repeat sweep mode 0, or repeat sweep mode 1. Pins which are not selected as analog input pins serve as programmable I/O port pins or as I/O pins of other internal peripheral devices, which are multiplexed. (6) Resolution select bit (bit 3 at address 1F 16) This bit is used to select a resolution. 12-8 7905 Group User ’ s Manual Rev.1.0 A -D CONVERTER 12.2 Block description (7) VREF c onnection select bit (bit 6 at address 1F16) When the A-D converter is not used, this bit is used to disconnect the resistor ladder network of the A-D converter from the reference voltage input pin (V REF). When the resistor ladder network is disconnected from pin V REF, the current is not flowed from pin V REF t o resistor ladder network. Accordingly, the power dissipation can be saved. When this bit changes from “ 1 ” ( V REF d isconnected) to “ 0 ” ( V REF c onnected), start of the operation must be 1 µ s or more later. 7905 Group User ’ s Manual Rev.1.0 12-9 A -D CONVERTER 12.2 Block description 12.2.2 A-D register i (i = 0 to 11) Figures 12.2.5 and 12.2.6 show the structures of the A-D register i. When the A-D conversion is completed, the conversion result (contents of the successive approximation register) is stored into this register. When the comparator function is selected, the value to be compared is stored in this register. Each A-D register i corresponds to an analog input pin (AN i). s When 8-bit resolution mode is selected A-D register 0 (Addresses 2116, 2016) A-D register 1 (Addresses 2316, 2216) A-D register 2 (Addresses 2516, 2416) A-D register 3 (Addresses 2716, 2616) A-D register 4 (Addresses 2916, 2816) A-D register 5 (Addresses 2B16, 2A16) A-D register 6 (Addresses 2D16, 2C16) A-D register 7 (Addresses 2F16, 2E16) Bit 7 to 0 Reads an A-D conversion result. A-D register 8 (Addresses E116, E016) A-D register 9 (Addresses E316, E216) A-D register 10 (Addresses E516, E416) A-D register 11 (Addresses E716, E616) (b15) b7 (b8) b0 b7 b0 Function At reset Undefined 0 R/W RO – 15 to 8 The value is “0” at reading. s When 10-bit resolution mode is selected A-D register 0 (Addresses 2116, 2016) A-D register 1 (Addresses 2316, 2216) A-D register 2 (Addresses 2516, 2416) A-D register 3 (Addresses 2716, 2616) A-D register 4 (Addresses 2916, 2816) A-D register 5 (Addresses 2B16, 2A16) A-D register 6 (Addresses 2D16, 2C16) A-D register 7 (Addresses 2F16, 2E16) Bit 9 to 0 Reads an A-D conversion result. A-D register 8 (Addresses E116, E016) A-D register 9 (Addresses E316, E216) A-D register 10 (Addresses E516, E416) A-D register 11 (Addresses E716, E616) (b15) b7 (b8) b0 b7 b0 Function At reset Undefined 0 R/W RO – 15 to 10 The value is “0” at reading. Fig. 12.2.5 Structure of A-D register i (1) 12-10 7905 Group User ’ s Manual Rev.1.0 A -D CONVERTER 12.2 Block description s When comparator function is selected A-D register 0 (Addresses 2116, 2016) A-D register 1 (Addresses 2316, 2216) A-D register 2 (Addresses 2516, 2416) A-D register 3 (Addresses 2716, 2616) A-D register 4 (Addresses 2916, 2816) A-D register 5 (Addresses 2B16, 2A16) A-D register 6 (Addresses 2D16, 2C16) A-D register 7 (Addresses 2F16, 2E16) A-D register 8 (Addresses E116, E016) A-D register 9 (Addresses E316, E216) A-D register 10 (Addresses E516, E416) A-D register 11 (Addresses E716, E616) (b15) b7 (b8) b0 b7 b0 Bit 7 to 0 15 to 8 Function Any value in the range from “0016” to “FF16” can be set. The set value is compared with the input voltage. The value is undefined at reading. The value is “0” at reading. At reset Undefined 0 R/W RO – Note: When the comparator function is selected, writing to and reading from A-D register i must be performed while the A-D converter halts. Fig. 12.2.6 Structure of A-D register i (2) 7905 Group User ’ s Manual Rev.1.0 12-11 A -D CONVERTER 12.2 Block description 12.2.3 Comparator function select register 0, 1 and comparator result register 0, 1 Figure 12.2.7 shows the structures of comparator function select register 0 and 1; Figure 12.2.8 shows the structures of comparator result register 0 and 1. When the AN i p in comparator function select bit is set to “ 1, ” t he comparator function is selected. When the A-D conversion is performed, be sure to clear the corresponding bit to “ 0. ” For details of the comparator function, refer to section “ 12.6 Comparator function.” b7 b6 b5 b4 b3 b2 b1 b0 Comparator function select register 0 (Address DC16) Bit 0 1 2 3 4 5 6 7 Bit name AN0 pin comparator function select bit AN1 pin comparator function select bit AN2 pin comparator function select bit AN3 pin comparator function select bit AN4 pin comparator function select bit AN5 pin comparator function select bit AN6 pin comparator function select bit AN7 pin comparator function select bit Function 0 : The comparator function is not selected. 1 : The comparator function is selected. At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Note: Writing to comparator function select register 0 must be performed while the A-D converter halts. b7 b6 b5 b4 b3 b2 b1 b0 Comparator function select register 1 (Address DD16) Bit 0 1 2 3 7 to 4 Bit name AN8 pin comparator function select bit AN9 pin comparator function select bit AN10 pin comparator function select bit AN11 pin comparator function select bit Fix these bits to “0000.” Function 0000 At reset 0 0 0 0 0 R/W RW RW RW RW RW 0 : The comparator function is not selected. 1 : The comparator function is selected. Note: Writing to comparator function select register 1 must be performed while the A-D converter halts. Fig. 12.2.7 Structures of comparator function select register 0 and 1 12-12 7905 Group User ’ s Manual Rev.1.0 A -D CONVERTER 12.2 Block description b7 b6 b5 b4 b3 b2 b1 b0 Comparator result register 0 (Address DE16) Bit 0 1 2 3 4 5 6 7 Bit name AN0 pin comparator result bit AN1 pin comparator result bit AN2 pin comparator result bit AN3 pin comparator result bit AN4 pin comparator result bit AN5 pin comparator result bit AN6 pin comparator result bit AN7 pin comparator result bit Function 0 : The set value > The input level at pin ANi 1 : The set value < The input level at pin ANi At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Note: Writing to comparator result register 0 must be performed while the A-D converter halts. b7 b6 b5 b4 b3 b2 b1 b0 Comparator result register 1 (Address DF16) Bit 0 1 2 3 7 to 4 Bit name AN8 pin comparator result bit AN9 pin comparator result bit AN10 pin comparator result bit AN11 pin comparator result bit Fix these bits to “0000.” Function 0000 At reset 0 0 0 0 0 R/W RW RW RW RW RW 0 : The set value > The input level at pin ANi 1 : The set value < The input level at pin ANi Note: Writing to comparator result register 1 must be performed while the A-D converter halts. Fig. 12.2.8 Structures of comparator result register 0 and 1 7905 Group User ’ s Manual Rev.1.0 12-13 A -D CONVERTER 12.2 Block description 12.2.4 A-D conversion interrupt control register Figure 12.2.9 shows the structure of the A-D conversion interrupt control register. For details about interrupts, refer to “ CHAPTER 6 . INTERRUPTS.” A-D conversion interrupt control register (Address 7016) b7 b6 b5 b4 b3 b2 b1 b0 Bit 0 1 2 3 7 to 4 Bit name Interrupt priority level select bits b2 b1 b0 Function 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested At reset 0 0 0 R/W RW RW RW Interrupt request bit Nothing is assigned. Undefined RW (Note 1) (Note 2) Undefined — Notes 1: Before using an A-D conversion interrupt, be sure to clear this bit to “0” by software. 2: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. Fig. 12.2.9 Structure of A-D conversion interrupt control register (1) Interrupt priority level select bits (bits 2 to 0) These bits are used to select an A-D conversion interrupt’s priority level. When using an A-D conversion interrupt, be sure to select one of the priority levels (1 to 7). When an A-D conversion interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = “ 0. ” ) To disable an A-D conversion interrupt, set these bits to “ 000 2” ( level 0). (2) Interrupt request bit (bit 3) This bit is set to “1” when an A-D conversion interrupt request has occurred. This bit is automatically cleared to “0” when the A-D conversion interrupt request has accepted. This bit can be set to “1” or cleared to “ 0 ” b y software. 12-14 7905 Group User ’ s Manual Rev.1.0 A -D CONVERTER 12.2 Block description 12.2.5 Port P7 direction register, port P8 direction register The A-D converter ’ s input pins are multiplexed with the port P7 and P8 pins. When using these pins as A-D converter ’s input pins, be sure to clear the port P7, P8 direction registers ’ bits, corresponding to the A-D converter’s input pins, in order to set these pins to the input mode. Figure 12.2.10 shows the correspondence between the port P7, P8 direction registers and the A-D converter ’ s input pins. b7 b6 b5 b4 b3 b2 b1 b0 Port P7 direction register (Address 1116) Bit 0 1 2 3 4 5 6 7 Pin AN0 Pin AN1 Pin AN2 Pin AN3 Pin AN4 Pin AN5 Pin AN6 Pin AN7 (Pin DA0) (Note 1) Bit name 0 : Input mode 1 : Output mode When using any of these pins as A-D converter’s input pin, be sure to clear its corresponding bit to “0.” Function At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Notes 1: When using pin AN7, be sure to clear the D-A0 output enable bit (bit 0 at address 9616) = “0” (output disabled). 2: The pins in ( ) is I/O pins of other internal peripheral devices, which are multiplexed with the corresponding port P7 pin. Port P8 direction register (Address 1416) Bit 0 1 2 3 Bit name Function b7 b6 b5 b4 b3 b2 b1 b0 At reset 0 0 0 0 Undefined R/W RW RW RW RW – Pin AN8 (Pin CTS2/RTS2/DA1) (Note 1) 0 : Input mode 1 : Output mode Pin AN9 (Pin CTS2/CLK2) (Note 2) Pin AN10 (Pin RXD2) (Note 3) When using any of these pins as A-D converter’s input pin, be sure to clear its corresponding bit to “0.” (Note 4) Pin AN11 (Pin TXD2) 7 to 5 Nothing is assigned. Notes 1: When using pin AN8 be sure to clear the D-A1 output enable bit (bit 1 at address 9616) = “0” (output disabled). Also, be sure not to use pin CTS2/RTS2. 2: When using pin AN9, be sure not to use pin CTS2/CLK2. 3: When using pin AN10, be sure not to use pin RXD2. 4: When using pin AN11, be sure not to use pin TXD2. 5: The pins in ( ) are I/O pins of other internal peripheral devices, which are multiplexed with the corresponding port P8 pins. Fig. 12.2.10 Correspondence between port P7, P8 derection registers and A-D converter’s input pins 7905 Group User ’ s Manual Rev.1.0 12-15 A -D CONVERTER 12.3 A-D conversion method 12.3 A-D conversion method The A-D converter compares the comparison voltage (V ref), which is internally generated according to the contents of the successive approximation register, with the analog input voltage (VIN), which is input from the analog input pin (ANi). By reflecting the comparison result on the successive approximation register, VIN is converted into a digital value. When a trigger is generated, the A-D converter performs the following processing: ➀ D etermining bit 9 of the successive approximation register The A-D converter compares V ref w ith V IN. At this time, the contents of the successive approximation register is “ 1000000000 2” ( initial value). Bit 9 of the successive approximation register depends on the comparison result as follows: When V ref < V IN, bit 9 = “ 1 ” When V ref > V IN, bit 9 = “ 0 ” ➁ D etermining bit 8 of the successive approximation register After setting bit 8 of the successive approximation register to “1,” the A-D converter compares V ref with VIN. Bit 8 depends on the comparison result as follows: When V ref < V IN, bit 8 = “ 1 ” When V ref > V IN, bit 8 = “ 0 ” ➂ D etermining bits 7 to LSB of the successive approximation register Operation ➁ i s performed for each of bits 7 to 0 in the 10-bit resolution mode. Operation ➁ i s performed for each of bits 7 to 2 in the 8-bit resolution mode. When the LSB is determined, the contents of the successive approximation register (in order words, conversion result) are transferred to the A-D register i. Vref is generated according to the latest contents of the successive approximation register. Table 12.3.1 lists the relationship between the successive approximation register’s contents and Vref. Tables 12.3.2 and 12.3.3 list the changes of the successive approximation register and Vref during the A-D conversion, respectively. Figure 12.3.1 shows the ideal A-D conversion characteristics in the 10-bit resolution mode. Table 12.3.1 Relationship between successive approximation register’s contents and Vref Successive approximation register’s contents: n 0 1 to 1023 VREF: Reference voltage VREF 1024 Vref ( V) 0 × ( n – 0 .5) 12-16 7905 Group User ’ s Manual Rev.1.0 A -D CONVERTER 12.3 A-D conversion method Table 12.3.2 Change of successive approximation register and Vref during A-D conversion (8-bit resolution) Successive approximation register b9 A-D converter halt 1st comparison 2nd comparison 3rd comparison Change of Vref VREF [V] 2 VREF – VREF [V] 2 2048 b0 1000000000 1000000000 n9 1 0 0 0 0 0 0 0 0 1st comparison result n9 n8 1 0 0 0 0 0 0 0 2nd comparison result 4 VREF VREF VREF [V] ± – VREF 4 2 2048 •n9 = 0 – 4 VREF •n8 = 1 + VREF VREF – VREF VREF 8 [V] ± ± 2048 8 2 4 – VREF •n8 = 0 •n9 = 1 + VREF : : : : : : 8 8th comparison Conversion completed n9 n8 n7 n6 n5 n4 n3 1 0 0 n9 n8 n7 n6 n5 n4 n3 n2 0 0 REF REF VREF VREF VREF [V] ±V ±V ± ...... ± – 2 4 8 256 2048 Table 12.3.3 Change of successive approximation register and V ref d uring A-D conversion (10-bit resolution) Successive approximation register b9 A-D converter halt 1st comparison 2nd comparison 3rd comparison Change of Vref VREF [V] 2 VREF – VREF [V] 2 2048 VREF ± VREF – VREF [V] 4 2 2048 •n9 = 1 •n9 = 0 b0 1000000000 1000000000 n9 1 0 0 0 0 0 0 0 0 1st comparison result + VREF 4 – VREF n9 n8 1 0 0 0 0 0 0 0 2nd comparison result : : VREF ± VREF ± VREF – VREF [V] 8 4 2 2048 : : 4 VREF •n8 = 1 + 8 •n8 = 0 – VREF 8 : : 10th comparison Conversion completed n9 n8 n7 n6 n5 n4 n3 n2 n1 1 n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 VREF ± VREF ± VREF ± ...... ± VREF REF [V] –V 8 2 4 1024 2048 7905 Group User ’ s Manual Rev.1.0 12-17 A -D CONVERTER 12.3 A-D conversion method A-D conversion result ldeal A-D conversion characteristics 3FF16 3FE16 3FD16 00316 00216 00116 00016 0 VREF 1024 ✕ 0.5 VREF ✕1 1024 VREF ✕2 1024 VREF ✕3 1024 VREF VREF VREF ✕ 1021 ✕ 1022 ✕ 1023 1024 1024 1024 VREF Analog input voltage Fig. 12.3.1 Ideal A-D conversion characteristics in 10-bit resolution mode 12-18 7905 Group User ’ s Manual Rev.1.0 A -D CONVERTER 12.4 Absolute accuracy and Differential non-linearity error 12.4 Absolute accuracy and Differential non-linearity error The A-D converter’s accuracy is described below. Refer to section “Appendix 10. 4. A-D converter standard characteristics,” also. 12.4.1 Absolute accuracy The absolute accuracy is the difference expressed in the LSB between the actual A-D conversion result and the output code of an A-D converter with ideal characteristics. (See Figure 12.4.1 for more details.) The analog input voltage at measurement of the absolute accuracy is assumed to be the mid point of the analog input voltage width that outputs the same output code from an A-D converter with ideal characteristics. For example, in the case of the 10-bit resolution mode, when V REF = 5 .12 V, 1 LSB width is 5 mV, and 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, ... are selected as the analog input voltages. The absolute accuracy = ±3 LSB indicates that when the analog input voltage is 25 mV, the output code expected from an ideal A-D conversion characteristics is “ 00516 , ” b ut the actual A-D conversion result is between “ 002 16” t o “ 008 16. ” The absolute accuracy includes the zero error and the full-scale error. The absolute accuracy degrades when VREF is lowered. Any of the output codes for analog input voltages in the range from V REF t o Vcc is “ 3FF 16 . ” Output code (A-D conversion result) 00B16 00A16 00916 00816 00716 00616 00516 00416 00316 00216 –3 LSB 00116 00016 0 5 10 15 20 25 30 35 40 45 50 55 +3 LSB Ideal A-D conversion characteristics Analog input voltage (mV) Fig. 12.4.1 Absolute accuracy of A-D converter (10-bit resolution mode) 7905 Group User ’ s Manual Rev.1.0 12-19 A -D CONVERTER 12.4 Absolute accuracy and Differential non-linearity error 12.4.2 Differential non-linearity error The differential non-linearity error indicates the difference between the 1 LSB step width (the ideal analog input voltage width while the same output code is expected to output) of an A-D converter with ideal characteristics and the actual measured step width (the actual analog input voltage width while the same output code is output). (See Figure 12.4.2 for more details.) For example, in the case of the 10-bit resolution mode and V REF = 5.12 V, the 1 LSB width of an A-D converter with ideal characteristics is 5 mV; but if the differential non-linearity error is ±1 LSB, the actual measured 1 LSB width is in the range from 0 to 10 mV. Output code (A-D conversion result) 00916 00816 00716 00616 00516 00416 00316 00216 00116 Differential non-linearity error 00016 0 5 10 15 20 25 30 35 40 45 1 LSB width with ideal A-D conversion characteristics Analog input voltage (mV) Fig. 12.4.2 Differential non-linearity error (10-bit resolution mode) 12-20 7905 Group User ’ s Manual Rev.1.0 A -D CONVERTER 12.5 Comparison voltage in 8-bit resolution mode 12.5 Comparison voltage in 8-bit resolution mode In the 8-bit resolution mode, which is selected by the resolution select bit, the high-order 8 bits of the 10bit successive approximation register are treated as the A-D conversion result. Accordingly, when compared with the 8-bit A-D converter, a comparison reference voltage is different by 3V REF/2048. (Refer to the underlined portions in Table 12.5.1). The difference of the output code change point is generated as shown in Figure 12.5.1. Table 12.5.1 Comparison voltage M37905’s 8-bit resolution mode Comparison voltage Vref VREF : Reference voltage n : Contents of successive approximation register VREF 2 8 8-bit A-D converter VREF 2 8 ✕n– VREF 2 10 ✕ 0.5 ✕n– VREF 28 ✕ 0.5 q8-bit A-D converter’s ideal characteristics (when VREF = 5.12 V) Output code (A-D conversion result) 02 01 00 10 30 Analog input voltage (mV) qM37905’s A-D converter’s ideal characteristics (when VREF = 5.12 V) Output code (A-D conversion result) 10-bit 8-bit resolution resolution mode mode 09 08 02 07 06 05 04 01 03 02 01 00 00 10-bit resolution mode 8-bit resolution mode (Note) (Note) 17.5 37.5 Analog input voltage (mV) Note: Difference of output code change point VREF: Reference voltage Fig. 12.5.1 Difference of output code change point 7905 Group User’s Manual Rev.1.0 12-21 A -D CONVERTER 12.6 Comparator function 12.6 Comparator function By setting the ANi pin comparator function select bit (See Figure 12.2.7.) to “1,” the comparator function can be selected for each pin AN i. For pin ANi w here the comparator function is selected, the following comparison operation is performed. ➀ A 1 0-bit value (a set value), of which high-order 8 bits consist of the corresponding A-D register i (at an even-numbered address) ’ s contents and of which low-order 2 bits = “ 10 2, ” i s D-A converted. ➁ The result of the D-A conversion (that is to say, comparison voltage V ref) is compared with an analog voltage input from an analog input pin. ➂ T he value to be stored into the AN i p in comparator result bit (see Figure 12.2.8.) depends on the comparison result as follows: When V ref > a nalog input voltage, “ 0 ” i s stored. When V ref < a nalog input voltage, “ 1 ” i s stored. 12-22 7905 Group User ’ s Manual Rev.1.0 A -D CONVERTER 12.7 One-shot mode 12.7 One-shot mode In the one-shot mode, the operation for an input voltage from one selected analog input pin is performed once, and an A-D conversion interrupt request occurs at completion of the operation. This mode can be used with analog input pin AN i ( i = 0 to 11). 12.7.1 Settings for one-shot mode Figures 12.7.1 and 12.7.2 show initial setting examples for related registers in the one-shot mode. When using an interrupt, it is necessary to set the related registers to enable an interrupt. Refer to “CHAPTER 6. INTERRUPTS” f or more details. A-D control registers 0, 1, and 2 b7 b0 0000 b2 b1 b0 A-D control register 0 (Address 1E16) Analog input pin select bits 0 0 0 0 : AN0 selected 0 0 1 : A N1 selected 0 1 0 : A N2 selected 0 1 1 : A N3 selected 1 0 0 : A N4 selected 1 0 1 : A N5 selected 1 1 0 : A N6 selected 1 1 1 : A N7 selected One-shot mode A-D conversion start bit 0 : A-D conversion halts. A-D conversion frequency (φAD) select bit 0 See Table 12.2.1. b7 b0 00 0✕✕ A-D control register 1 (Address 1F16) Resolution select bit 0 : 8-bit resolution mod 1 : 10-bit resolution mode A-D conversion frequency (φAD) select bit 1 See Table 12.2.1. VREF connection select bit 0 : Pin VREF connected b7 b0 00 00 A-D control register 2 (Address DB16) Analog input pin select bits 1 b3 b2 b1 b0 0 X X X : AN0 to AN7 selected 1 0 0 0 : AN8 selected 1 0 0 1 : AN9 selected 1 0 1 0 : AN10 selected 1 0 1 1 : AN11 selected 1 1 0 0 : Do not select. 1 1 1 1 : Do not select. ✕ : It may be either “0” or “1.” Continued on Figure 12.7.2. Fig. 12.7.1 Initial setting example for related registers in one-shot mode (1) 7905 Group User ’ s Manual Rev.1.0 •••• 12-23 A -D CONVERTER 12.7 One-shot mode Continued from preceding Figure 12.7.1. Selection of comparator function b7 b0 b7 b0 Comparator function select register 0 (Address DC16) AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 0 : Comparator function is not selected 1 : Comparator function is selected. 0000 Comparator function select register 1 (Address DD16) AN 8 0 : Comparator function is not selected AN 9 1 : Comparator function is selected. AN 10 AN 11 When comparator function is not selected When comparator function is selected A-D register i (b15) b7 (b 8) b0 b7 b0 A-D register 0 (Addresses 2116, 2016) A-D register 1 (Addresses 2316, 2216) A-D register 2 (Addresses 2516, 2416) A-D register 3 (Addresses 2716, 2616) A-D register 4 (Addresses 2916, 2816) A-D register 5 (Addresses 2B16, 2A16) A-D register 6 (Addresses 2D16, 2C16) A-D register 7 (Addresses 2F16, 2E16) A-D register 8 (Addresses E116, E016) A-D register 9 (Addresses E316, E216) A-D register 10 (Addresses E516, E416) A-D register 11 (Addresses E716, E616) A value (comparison value) in the range from 0016 through FF16 is set. Interrupt priority level b7 b0 0 A-D conversion interrupt control register (Address 7016) Interrupt priority level select bits Set the level to one of 1 through 7 when using this interrupt Set the level to 0 when disabling interrupts. No interrupt requested Port P7, P8 direction register b7 b0 b7 b0 Port P7 direction register (Address 1116) AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 Clear the bits, corresponding to the selected analog input pins, to “0.” Port P8 direction register (Address 1416) AN 8 AN 9 AN 10 AN 11 Clear the bits, corresponding to the selected analog input pins, to “0.” Setting of A-D conversion start bit to “1.” b7 b0 1 A-D control register 0 (Address 1E16) A-D conversion start bit Trigger generated Operation starts. Note: Writing to the following must be performed while the A-D converter halts (in other words, before a trigger is generated); this must be done independent of the operation mode of the A-D converter. • Each bit of the A-D control register 0, except writing of “0” to bit 6 • Each bit of the A-D control register 1 • Each bit of the A-D control register 2 • A-D register i (when the comparator function is selected) • Comparator function select register 0 • Comparator function select register 1 Especially, when the VREF connection select bit is cleared from “1” to “0,” an interval of 1 µs or more must be elapsed before occurrence of a trigger. Fig. 12.7.2 Initial setting example for related registers in one-shot mode (2) 12-24 7905 Group User ’ s Manual Rev.1.0 A -D CONVERTER 12.7 One-shot mode 12.7.2 One-shot mode operation ➀ T he A-D converter starts its operation when the A-D conversion start bit is set to “ 1. ” ➁ The A-D conversion is completed after 49 cycles of φ AD in the 8-bit resolution mode, or 59 cycles of φ AD i n the 10-bit resolution mode. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register i. When the comparator function is selected, the comparison is completed after 14 cycles of φAD. Then, the result of the comparison is stored into the AN i p in comparator result bit. ➂ A t the same time as step ➁ , the A-D conversion interrupt request bit is set to “ 1. ” ➃ T he A-D conversion start bit is cleared to “ 0, ” a nd the A-D converter halts. Figure 12.7.3 shows the operation in the one-shot mode. s 8-bit and 10-bit resolution modes Trigger generated Conversion result Convert input voltage at pin ANi. A-D register i A-D conversion interrupt request occurs. A-D converter halts. s Comparator function Trigger generated Comparison result Compare input voltage at pin ANi. ANi pin comparator result bit A-D conversion interrupt request occurs. A-D converter halts. Fig. 12.7.3 Operation in one-shot mode 7905 Group User ’ s Manual Rev.1.0 12-25 A -D CONVERTER 12.8 Repeat mode 12.8 Repeat mode In the repeat mode, the A-D conversion for an input voltage from one selected analog input pin is performed repeatedly. In this mode, no A-D conversion interrupt request occurs. Additionally, the A-D conversion start bit (bit 6 at address 1E 16) remains set to “ 1 ” u ntil it is cleared to “ 0 ” b y software, and the A-D converter repeats its operation while the A-D conversion start bit = “ 1. ” This mode can be used with analog input pin AN i ( i = 0 to 11). 12.8.1 Settings for repeat mode Figures 12.8.1 and 12.8.2 show initial setting examples for related registers in the repeat mode. A-D control registers 0, 1, and 2 b7 b0 0001 A-D control register 0 (Address 1E16) Analog input pin select bits 0 b2 b1 b0 0 0 0 : AN0 selected 0 0 1 : AN1 selected 0 1 0 : AN2 selected 0 1 1 : AN3 selected 1 0 0 : AN4 selected 1 0 1 : AN5 selected 1 1 0 : AN6 selected 1 1 1 : AN7 selected Repeat mode A-D conversion start bit 0 : A-D conversion halts. A-D conversion frequency (φAD) select bit 0 See Table 12.2.1. b7 b0 00 0✕✕ A-D control register 1 (Address 1F16) Resolution select bit 0 : 8-bit resolution mod 1 : 10-bit resolution mode A-D conversion frequency (φAD) select bit 1 See Table 12.2.1. VREF connection select bit 0 : Pin VREF connected b7 b0 00 00 A-D control register 2 (Address DB16) Analog input pin select bits 1 b3 b2 b1 b0 0 X X X : AN0 to AN7 selected 1 0 0 0 : AN8 selected 1 0 0 1 : AN9 selected 1 0 1 0 : AN10 selected 1 0 1 1 : AN11 selected 1 1 0 0 : Do not select. 1 1 1 1 : Do not select. ✕ : It may be either “0” or “1.” Continued on Figure 12.8.2. Fig. 12.8.1 Initial setting example for related registers in repeat mode (1) 12-26 7905 Group User ’ s Manual Rev.1.0 •••• A -D CONVERTER 12.8 Repeat mode Continued from preceding Figure 12.8.1. Selection of comparator function b7 b0 b7 b0 Comparator function select register 0 (Address DC16) AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 0 : Comparator function is not selected 1 : Comparator function is selected. 0000 Comparator function select register 0 (Address DD16) AN 8 AN 9 AN 10 AN 11 0 : Comparator function is not selected 1 : Comparator function is selected. When comparator function is not selected When comparator function is selected A-D register i (b 15 ) b7 (b 8) b0 b7 b0 A-D register 0 (Addresses 2116, 2016) A-D register 1 (Addresses 2316, 2216) A-D register 2 (Addresses 2516, 2416) A-D register 3 (Addresses 2716, 2616) A-D register 4 (Addresses 2916, 2816) A-D register 5 (Addresses 2B16, 2A16) A-D register 6 (Addresses 2D16, 2C16) A-D register 7 (Addresses 2F16, 2E16) A-D register 8 (Addresses E116, E016) A-D register 9 (Addresses E316, E216) A-D register 10 (Addresses E516, E416) A-D register 11 (Addresses E716, E616) A value (comparison value) in the range from 0016 through FF16 is set. Port P7, P8 direction register b7 b0 b7 b0 Port P7 direction register (Address 1116) AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 Clear the bits, corresponding to the selected analog input pins, to “0.” Port P8 direction register (Address 1416) AN 8 AN 9 AN 10 AN 11 Clear the bits, corresponding to the selected analog input pins, to “0.” Setting of A-D conversion start bit to “1.” b7 b0 1 A-D control register 0 (Address 1E16) A-D conversion start bit Trigger generated Operation starts. Note: Writing to the following must be performed while the A-D converter halts (in other words, before a trigger is generated); this must be done independent of the operation mode of the A-D converter. • Each bit of the A-D control register 0, except writing of ”0” to bit 6 • Each bit of the A-D control register 1 • Each bit of the A-D control register 2 • A-D register i (when the comparator function is selected) • Comparator function select register 0 • Comparator function select register 1 Especially, when the VREF connection select bit is cleared from “1” to “0,” an interval of 1 µs or more must be elapsed before occurrence of a trigger. Fig. 12.8.2 Initial setting example for related registers in repeat mode (2) 7905 Group User ’ s Manual Rev.1.0 12-27 A -D CONVERTER 12.8 Repeat mode 12.8.2 Repeat mode operation ➀ T he A-D converter starts its operation when the A-D conversion start bit is set to “ 1. ” ➁ The 1st A-D conversion is completed after 49 cycles of φAD in the 8-bit resolution mode, or 59 cycles of φAD i n the 10-bit resolution mode. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register i. When the comparator function is selected, the 1st comparison is completed after 14 cycles of φAD. Then, the result of the comparison is stored into the AN i p in comparator result bit. ➂ T he A-D converter repeats its operation until the A-D conversion start bit is cleared to “ 0 ” b y software. The conversion result is transferred to the A-D register i each time the conversion is completed. When the comparator function is selected, the comparison result is stored into the ANi pin comparator result bit each time the comparison is completed. Figure 12.8.3 shows the operation in the repeat mode. s 8-bit and 10-bit resolution modes Trigger generated Conversion result Convert input voltage at pin ANi. A-D register i s Comparator function Trigger generated Comparison result Compare input voltage at pin ANi. ANi pin comparator result bit Fig. 12.8.3 Operation in repeat mode 12-28 7905 Group User ’ s Manual Rev.1.0 A -D CONVERTER 12.9 Single sweep mode 12.9 Single sweep mode In the single sweep mode, the operation for the input voltages from multiple selected analog input pins are performed, one at a time. The operation is performed in ascending sequence from pin AN 0 to pin AN 7. An A-D conversion interrupt request occurs when the operations for all selected analog input pins are completed. This mode can be used with analog input pins AN j ( j = 0 to 7). 12.9.1 Settings for single sweep mode Figures 12.9.1 and 12.9.2 show initial setting examples for related registers in the single sweep mode. When using an interrupt, it is necessary to set the related registers to enable an interrupt. Refer to “ CHAPTER 6. INTERRUPTS ” f or more details. A-D control registers 0, 1, and 2 b7 b0 0 0 1 0 ✕✕ ✕ A-D control register 0 (Address 1E16) Single sweep mode A-D conversion start bit 0 : A-D conversion halts. A-D conversion frequency (φAD) select bit 0 See Table 12.2.1. b7 b0 00 0 A-D control register 1 (Address 1F16) A-D sweep pin select bits b1 b0 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) Resolution select bit 0 : 8-bit resolution mode 1 : 10-bit resolution mode A-D conversion frequency (φAD) select bit 1 See Table 12.2.1. VREF connection select bit 0 : Pin VREF connected b7 b0 0 0 0 0 0 ✕ ✕ ✕ (Address DB16) b3 b2 b1 b0 A-D control register 2 Analog input pin select bits 1 0 X X X : AN0 to AN7 selected ✕ : It may be either “0” or “1.” Selection of comparator function b7 b0 Comparator function select register 0 (Address DC16) AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 0 : Comparator function is not selected 1 : Comparator function is selected. Continued on Figure 12.9.2. Fig. 12.9.1 Initial setting example for related registers in single sweep mode (1) 7905 Group User ’ s Manual Rev.1.0 12-29 A -D CONVERTER 12.9 Single sweep mode Continued from preceding Figure 12.9.1. When comparator function is not selected When comparator function is selected A-D register j (b 15) b7 (b 8) b0 b7 b0 A-D register 0 (Addresses 2116, 2016) A-D register 1 (Addresses 2316, 2216) A-D register 2 (Addresses 2516, 2416) A-D register 3 (Addresses 2716, 2616) A-D register 4 (Addresses 2916, 2816) A-D register 5 (Addresses 2B16, 2A16) A-D register 6 (Addresses 2D16, 2C16) A-D register 7 (Addresses 2F16, 2E16) A value (comparison value) in the range from 0016 through FF16 is set. Interrupt priority level b7 b0 0 A-D conversion interrupt control register (Address 70 Interrupt priority level select bits Set the level to one of 1 through 7 when using this interrupt Set the level to 0 when disabling interrupts. No interrupt requested Port P7 direction register b7 b0 Port P7 direction register (Address 1116) AN 0 AN 1 Clear the bits, corresponding to the AN 2 selected analog input pins, to “0.” AN 3 AN 4 AN 5 AN 6 AN 7 Setting of A-D conversion start bit to “1.” b7 b0 1 A-D control register 0 (Address 1E16) A-D conversion start bit Trigger generated Operation starts. Note: Writing to the following must be performed while the A-D converter halts (in other words, before a trigger is generated); this must be done independent of the operation mode of the A-D converter. • Each bit of the A-D control register 0, except writing of “0” to bit 6 • Each bit of the A-D control register 1 • Each bit of the A-D control register 2 • A-D register j (when the comparator function is selected) • Comparator function select register 0 Especially, when the VREF connection select bit is cleared from “1” to “0,” an interval of 1 µs or more must be elapsed before occurrence of a trigger. Fig. 12.9.2 Initial setting example for related registers in single sweep mode (2) 12-30 7905 Group User ’ s Manual Rev.1.0 A -D CONVERTER 12.9 Single sweep mode 12.9.2 Single sweep mode operation ➀ The A-D converter starts its operation for the input voltage at pin AN0 when the A-D conversion start bit is set to “ 1. ” ➁ T he A-D conversion for the input voltage at pin AN 0 i s completed after 49 cycles of φAD i n the 8bit resolution mode, or 59 cycles of φ AD i n the 10-bit resolution mode. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register 0. When the comparator function is selected, the comparison for pin AN0 is completed after 14 cycles of φ AD. Then, the result of the comparison is stored into the AN 0 p in comparator result bit. ➂ T he operations for all selected analog input pins are performed. In the 8-bit and 10-bit resolution modes, the conversion result is transferred to the corresponding A-D register j each time when the A-D conversion per one pin is completed. When the comparator function is selected, the comparison result is stored into the AN j pin comparator result bit each time the comparison for one pin is completed. ➃ W hen step ➂ i s completed, the A-D conversion interrupt request bit is set to “ 1. ” ➄ T he A-D conversion start bit is cleared to “ 0, ” a nd the A-D converter halts. Figure 12.9.3 shows the operation in the single sweep mode. Trigger generated Conversion result A-D register 0 Convert input voltage at pin AN0 Comparison result or Compare input voltage at pin AN0 AN0 pin comparator result bit Conversion result A-D register 1 Convert input voltage at pin AN1 Comparison result or AN1 pin comparator result bit Compare input voltage at pin AN1 Conversion result Convert input voltage at pin ANj or Compare input voltage at pin ANj A-D register j Comparison result ANj pin comparator result bit A-D converter interrupt request occurs. A-D converter halts. Fig. 12.9.3 Operation in single sweep mode 7905 Group User ’ s Manual Rev.1.0 12-31 A -D CONVERTER 12.10 Repeat sweep mode 0 12.10 Repeat sweep mode 0 In the repeat sweep mode, the A-D conversions for input voltages from multiple selected analog input pins are performed repeatedly. The A-D conversion is performed in ascending sequence from pin AN0 to pin AN7. In this mode, no A-D conversion interrupt request occurs. Additionally, the A-D conversion start bit (bit 6 at address 1E 16) remains set to “ 1 ” u ntil it is cleared to “ 0 ” b y software, and the A-D converter repeats its operation while the A-D conversion start bit = “ 1. ” This mode can be used with analog input pins AN j ( j = 0 to 7). 12.10.1 Settings for repeat sweep mode 0 Figures 12.10.1 and 12.10.2 show initial setting examples for related registers in the repeat sweep mode 0. A-D control registers 0, 1, and 2 b7 b0 0 0 11✕✕✕ A-D control register 0 (Address 1E16) Repeat sweep mode 0 A-D conversion start bit 0 : A-D conversion halts. A-D conversion frequency (φAD) select bit 0 See Table 12.2.1. b7 b0 00 0 A-D control register 1 (Address 1F16) A-D sweep pin select bits b1 b0 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) Repeat sweep mode 0 Resolution select bit 0 : 8-bit resolution mode 1 : 10-bit resolution mode A-D conversion frequency (φAD) select bit 1 See Table 12.2.1. VREF connection select bit 0 : Pin VREF connected b7 b0 0 000 0✕✕✕ (Address DB16) b3 b2 b1 b0 A-D control register 2 Analog input pin select bits 1 0 X X X : AN0 to AN7 selected ✕ : It may be either “0” or “1.” Selection of comparator function b7 b0 Comparator function select register 0 (Address DC16) AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 0 : Comparator function is not selected. 1 : Comparator function is selected. Continued on Figure 12.10.2. Fig. 12.10.1 Initial setting example for related registers in repeat sweep mode 0 (1) 12-32 7905 Group User ’ s Manual Rev.1.0 A -D CONVERTER 12.10 Repeat sweep mode 0 Continued from preceding Figure 12.10.1. When comparator function is not selected When comparator function is selected A-D register j (b 15) b7 (b 8) b0 b7 b0 A-D register 0 (Addresses 2116, 2016) A-D register 1 (Addresses 2316, 2216) A-D register 2 (Addresses 2516, 2416) A-D register 3 (Addresses 2716, 2616) A-D register 4 (Addresses 2916, 2816) A-D register 5 (Addresses 2B16, 2A16) A-D register 6 (Addresses 2D16, 2C16) A-D register 7 (Addresses 2F16, 2E16) A value (comparison value) in the range from 0016 through FF16 is set. Port P7 direction register b7 b0 Port P7 direction register (Address 1116) AN 0 Clear the bits, corresponding to the AN 1 selected analog input pins, to “0.” AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 Setting of A-D conversion start bit to “1.” b7 b0 1 A-D control register 0 (Address 1E16) A-D conversion start bit Trigger generated Operation starts. Note: Writing to the following must be performed while the A-D converter halts (in other words, before a trigger is generated); this must be done independent of the operation mode of the A-D converter. • Each bit of the A-D control register 0, except writing of “0” to bit 6 • Each bit of the A-D control register 1 • Each bit of the A-D control register 2 • A-D register j (when the comparator function is selected) • Comparator function select register 0 Especially, when the VREF connection select bit is cleared from “1” to “0,” an interval of 1 µs or more must be elapsed before occurrence of a trigger. Fig. 12.10.2 Initial setting example for related registers in repeat sweep mode 0 (2) 7905 Group User ’ s Manual Rev.1.0 12-33 A -D CONVERTER 12.10 Repeat sweep mode 0 12.10.2 Repeat sweep mode 0 operation ➀ The A-D converter starts its operation for the input voltage at pin AN0 when the A-D conversion start bit is set to “ 1. ” ➁ T he A-D conversion for the input voltage at pin AN0 i s completed after 49 cycles of φ AD i n the 8bit resolution mode, or 59 cycles of φ AD i n the 10-bit resolution mode. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register 0. When the comparator function is selected, the comparison for pin AN0 is completed after 14 cycles of φ AD. Then, the result of the comparison is stored into the AN0 p in comparator result bit. ➂ T he operations for all selected analog input pins are performed. The conversion result is transferred to the corresponding A-D register j each time when the A-D conversion per one pin is completed. When the comparator function is selected, the comparison result is stored into the AN j p in comparator result bit each time the comparison for one pin is completed. ➃ T he operations for all selected analog input pins are performed again. ➄ T he A-D converter repeats its operation until the A-D conversion start bit is cleared to “ 0 ” b y software. Figure 12.10.3 shows the operation in the repeat sweep mode 0. Trigger generated Conversion result A-D register 0 Convert input voltage at pin AN0 Comparison result or Compare input voltage at pin AN0 AN0 pin comparator result bit Conversion result A-D register 1 Convert input voltage at pin AN1 Comparison result or AN1 pin comparator result bit Compare input voltage at pin AN1 Conversion result Convert input voltage at pin ANj or Compare input voltage at pin ANj A-D register j Comparison result ANj pin comparator result bit Fig. 12.10.3 Operation in repeat sweep mode 0 12-34 7905 Group User ’ s Manual Rev.1.0 A -D CONVERTER 12.11 Repeat sweep mode 1 12.11 Repeat sweep mode 1 In the repeat sweep mode 1, the A-D conversions for input voltages from multiple selected analog input pins AN j (j = 0 to 7) are performed repeatedly. In this mode, analog input pins ANj are divided into two groups: frequently-used pins and non-frequently-used pins. Then, the operation for all of the frequently-used pins is performed. Next, the operation for one of the non-frequently-used pins is performed. Figure 12.11.1 shows the operation sequence in the repeat sweep mode 1. As shown in Figure 12.11.1, the non-frequently-used pin changes sequentially. In this mode, no A-D conversion interrupt request occurs. Additionally, the A-D conversion start bit (bit 6 at address 1E 16) remains set to “ 1 ” u ntil it is cleared to “ 0 ” b y software, and the A-D converter repeats its operation while the A-D conversion start bit = “ 1. ” This mode can be used with analog input pins AN j ( j = 0 to 7). 12.11.1 Settings for repeat sweep mode 0 Figures 12.11.2 and 12.10.3 show initial setting examples for related registers in the repeat sweep mode 1. Be sure to select the frequently-used analog input pins by the A-D sweep pin select bits (bits 1 and 0 at address 1F16). All pins that are not selected by the A-D sweep pin select bits become the non-frequentlyused pins. 7905 Group User ’ s Manual Rev.1.0 12-35 A -D CONVERTER 12.11 Repeat sweep mode 1 s When the A-D sweep pin select bits (bits 1 and 0 at address 1F16) = “002” (Frequently used pin: pin AN0) AN 0 AN 1 AN 0 AN 2 AN 0 AN 3 AN 0 AN 4 AN 0 AN 5 AN 0 AN 6 AN 0 AN 7 AN 0 AN 1 AN 0 AN 2 ••••••• s When the A-D sweep pin select bits (bits 1 and 0 at address 1F16) = “012” (Frequently used pins: pins AN0 and AN1) AN 0 AN 1 AN 2 AN 0 AN 1 AN 0 AN 2 AN 1 AN 3 ••••••• AN 0 AN 3 AN 1 AN 4 AN 0 AN 1 AN 5 AN 0 AN 1 AN 6 AN 0 AN 1 AN 7 AN 0 AN 1 s When the A-D sweep pin select bits (bits 1 and 0 at address 1F16) = “102” (Frequently used pins: pins AN0 to AN2) AN 0 AN 1 AN 2 AN 4 AN 3 AN 0 AN 1 AN 2 AN 4 AN 0 AN 1 AN 2 AN 5 AN 0 AN 1 AN 2 AN 6 AN 0 AN 1 AN 2 AN 7 AN 0 AN 1 AN 2 AN 3 AN 0 AN 1 AN 2 ••••••• s When the A-D sweep pin select bits (bits 1 and 0 at address 1F16) = “112” (Frequently used pins: pins AN0 to AN3) AN 0 AN 1 AN 4 AN 2 AN 3 AN 2 AN 3 AN 0 AN 1 AN 5 AN 2 AN 3 AN 0 AN 1 AN 6 AN 2 AN 3 AN 0 AN 1 AN 7 AN 2 AN 3 AN 0 AN 1 AN 4 AN 2 AN 3 AN 0 AN 1 AN 5 ••••••• : Operation sequence : Frequently used pins Fig. 12.11.1 Operation sequence in repeat sweep mode 1 12-36 7905 Group User ’ s Manual Rev.1.0 A -D CONVERTER 12.11 Repeat sweep mode 1 A-D control registers 0, 1, and 2 b7 b0 0 0 11✕✕✕ A-D control register 0 (Address 1E16) Repeat sweep mode 1 A-D conversion start bit 0 : A-D conversion halts. A-D conversion frequency (φAD) select bit 0 See Table 12.2.1. b7 b0 00 1 A-D control register 1 (Address 1F16) A-D sweep pin select bits b1 b0 0 0 : AN0 (1 pin) 0 1 : AN0 and AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) Repeat sweep mode 1 Resolution select bit 0 : 8-bit resolution mode 1 : 10-bit resolution mode A-D conversion frequency (φAD) select bit 1 See Table 12.2.1. VREF connection select bit 0 : Pin VREF connected b7 b0 0 000 0✕✕✕ A-D control register 2 (Address DB16) Analog input pin select bits 1 b3 b2 b1 b0 0 X X X : AN0 to AN7 selected ✕ : It may be either “0” or “1.” Selection of comparator function b7 b0 Comparator function select register 0 (Address DC16) AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 0 : Comparator function is not selected. 1 : Comparator function is selected. Continued on Figure 12.11.3. Fig. 12.11.2 Initial setting example for related registers in repeat sweep mode 1 (1) 7905 Group User ’ s Manual Rev.1.0 12-37 A -D CONVERTER 12.11 Repeat sweep mode 1 Continued from preceding Figure 12.11.2. When comparator function is not selected When comparator function is selected A-D register j (b 15) b7 (b 8) b0 b7 b0 A-D register 0 (Addresses 2116, 2016) A-D register 1 (Addresses 2316, 2216) A-D register 2 (Addresses 2516, 2416) A-D register 3 (Addresses 2716, 2616) A-D register 4 (Addresses 2916, 2816) A-D register 5 (Addresses 2B16, 2A16) A-D register 6 (Addresses 2D16, 2C16) A-D register 7 (Addresses 2F16, 2E16) A value (comparison value) in the range from 0016 through FF16 is set. Port P7 direction register b7 b0 Port P7 direction register (Address 1116) AN 0 AN 1 Clear the bits, corresponding to the AN 2 selected analog input pins, to “0.” AN 3 AN 4 AN 5 AN 6 AN 7 Setting of A-D conversion start bit to “1.” b7 b0 1 A-D control register 0 (Address 1E16) A-D conversion start bit Trigger generated Operation starts. Note: Writing to the following must be performed while the A-D converter halts (in other words, before a trigger is generated); this must be done independent of the operation mode of the A-D converter. • Each bit of the A-D control register 0, except wrinting of “0” to bit 6 • Each bit of the A-D control register 1 • Each bit of the A-D control register 2 • A-D register j (when the comparator function is selected) • Comparator function select register 0 Especially, when the VREF connection select bit is cleared from “1” to “0,” an interval of 1 µs or more must be elapsed before occurrence of a trigger. Fig. 12.11.3 Initial setting example for related registers in repeat sweep mode 1 (2) 12-38 7905 Group User ’ s Manual Rev.1.0 A -D CONVERTER 12.11 Repeat sweep mode 1 12.11.2 Repeat sweep mode 1 operation ➀ The A-D converter starts its operation for the input voltage at pin AN0 when the A-D conversion start bit is set to “ 1. ” ➁ T he A-D conversion for the input voltage at pin AN 0 i s completed after 49 cycles of φAD i n the 8bit resolution mode, or 59 cycles of φ AD i n the 10-bit resolution mode. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register 0. When the comparator function is selected, the comparison for pin AN0 is completed after 14 cycles of φ AD. Then, the result of the comparison is stored into the AN 0 p in comparator result bit. ➂ The operations for all of the frequently-used analog input pins is performed. The conversion result is transferred to the corresponding A-D register j each time when the A-D conversion per one pin is completed. When the comparator function is selected, the comparison result is stored into the ANj pin comparator result bit each time the comparison for one pin is completed. ➃ T he operation for one of the non-frequently-used analog input pins is performed. (See Figure 12.11.1.) ➄ T he operation for all of the frequently-used analog input pins is performed again. ➅ T he operation for one of the non-frequently-used analog input pins is performed. This pin differs from the pin used in ➃ . (See Figure 12.11.1.) ➆ T he A-D converter repeats its operation until the A-D conversion start bit is cleared to “ 0 ” b y software. 7905 Group User ’ s Manual Rev.1.0 12-39 A -D CONVERTER [Precautions for A-D converter] [Precautions for A-D converter] 1. Be sure to clear the V REF c onnection select bit to “ 0. ” 2. Writing to the following must be performed before a trigger is generated (in other words, while the A-D converter halts); this must be done independent of the operation mode of the A-D converter. • E ach bit of the A-D control register 0, except writing of “ 0 ” t o bit 6 • E ach bit of the A-D control register 1 • E ach bit of the A-D control register 2 • A -D register i (when the comparator function is selected) • C omparator function select register 0 • C omparator function select register 1 • C omparator result register 0 • C omparator result register 1 Especially, when any instruction which clears the V REF c onnection select bit from “ 1 ” t o “ 0 ” h as been executed (in other words, the resistor ladder network is connected with pin VREF b y this instruction), an interval of 1 µ s or more must be elapsed before occurrence of a trigger. 3. When using pins AN 0 t o AN 7, regardless of the A-D operation mode, be sure to fix bit 3 of the analog input pin select bits 1 (bits 3 to 0 at address DB 16) to “ 0. ” 4. Pins AN 8 t o AN 11 c an be used only in the one-shot mode or repeat mode. 5. The analog input pin select bits 0 (bits 2 to 0 at address 1E16) and the analog input pin select bits 1 (bits 3 to 0 at address DB16) must be specified again if the user switches the operation mode to the one-shot mode or repeat mode after the operation is performed in the single sweep mode, repeat sweep mode 0, or repeat sweep mode 1. 6. Reading from A-D register i (when the comparator function is selected) must be performed before occurrence of a trigger (in other words, while the A-D converter halts.). The value undefined at reading. 7. When using pin AN7, be sure that the D-A0 output enable bit (bit 0 at address 9616) = “0” (output disabled). When using pin AN8, be sure that the D-A1 output enable bit (bit 1 at address 9616) = “0” (output disabled). Also, be sure not to use pin CTS 2/RTS 2. When using pin AN 9, be sure not to use pin CTS 2/CLK 2. When using pin AN 10, be sure not to use pin RX D 2. When using pin AN 11, be sure not to use pin T XD 2. 8. Setting of bit 3 of the analog input pin select bits 1 (bits 3 to 0 at address DB16 ) to “ 1 ” i nvalidates the analog input pin select bits 0 (bits 2 to 0 at address 1E 16). 9. Refer to section “ Appendix 7. Countermeasures against noise ” w hen using the A-D converter. 12-40 7905 Group User ’ s Manual Rev.1.0 CHAPTER 13 D-A CONVERTER 13.1 Overview 13.2 Block description 13.3 D-A conversion method 13.4 Setting method 13.5 Operation description [Precautions for D-A converter] D-A CONVERTER 13.1 Overview, 13.2 Block description 13.1 Overview The M37905 is provided with two independent D-A converters of the R-2R type with 8-bit resolution. These D-A converters convert the values loaded in D-A register i (i = 0, 1) to analog voltages and output them from pin DA i. 13.2 Block description Figure 13.2.1 shows the block diagram of the D-A converter. The registers related to the D-A converter are described below. Data bus D-A register i (i = 0, 1) (Addresses 9816, 9916) VREF AVSS R-2R ladder network D-Ai output enable bit DAi Fig. 13.2.1 D-A converter block diagram 13-2 7905 Group User’s Manual Rev.1.0 D-A CONVERTER 13.2 Block description 13.2.1 D-A control register Figure 13.2.2 shows the structure of the D-A control register. Pin DA i (i = 0, 1) serves as the analog voltage output pin of the D-A converter. Since pin DAi is equipped with no internal buffer amplifier, it is necessary to connect a buffer amplifier externally to pin DA i, if this pin is needed to be connected with a low-impedance load. Pin DAi i s multiplexed with an analog input pin and I/O pins for serial I/O. When any of the D-A i o utput enable bits is set to “1” (output enabled), the corresponding pin is used only as pin DA i, not as any other multiplexed input/output pin (including a programmable I/O port pin). D-A control register (Address 9616) Bit 0 1 b7 b6 b5 b4 b3 b2 b1 b0 Bit name D-A 0 o utput enable bit D-A 1 o utput enable bit Function 0: Output is disabled. 1: Output is enabled. ( Notes 1, 2) 0: Output is disabled. 1: Output is enabled. ( Notes 1, 2) At reset R/W 0 0 Undefined RW RW — 7 to 2 Nothing is assigned. Notes 1: Pin DAi is multiplexed with an analog input pin and I/O pins for serial I/O. When a D-Ai output enable bit = “1” (in other words, output is enabled.), however, the corresponding pin cannot function as any other multiplexed input/output pin (including a programmable I/O port pin). 2: When not using the D-A converter, be sure to clear this bit to “0.” Fig. 13.2.2 Structure of D-A control register (1) D-Ai o utput enable bits (Bits 0, 1) Setting any of the D-Ai output enable bits to “1” (output enabled) allows the corresponding pin DA i to output D-A converted analog voltage, regardless of the contents of the corresponding bits of the port P7 and port P8 direction registers. 13.2.2 D-A register i (i = 0, 1) Each pin DAi outputs the analog voltage corresponding to the value loaded in D-A register i. Figure 13.2.3 shows the structure of D-A register i. b7 b0 D-A register i (i = 0, 1) (Addresses 98 16, 99 16) Bit 7 to 0 Function Any value in the range from 00 16 t hrough FF 16 c an be set ( Note) , and this value will be D-A converted and will be output. At reset R/W 0 RW Note: When not using the D-A converter, be sure to clear the contents of these bits to “0016.” Fig. 13.2.3 Structure of D-A register i 7905 Group User ’ s Manual Rev.1.0 13-3 D-A CONVERTER 13.3 D-A conversion method 13.3 D-A conversion method The reference voltage V REF i s divided according to the value loaded in D-A register i, and it is output as an analog voltage from pin DA i . Figure 13.3.1 shows the equivalent circuit diagram of the D-A converter. D-Ai output enable bit 0 R 2R R 2R R 2R R 2R R 2R R 2R R 2R 2R 2R LSB DAi 1 MSB D-A register i AVSS VREF Note: In this case, the value of D-A register i is “2A16.” 0 1 Fig. 13.3.1 Equivalent circuit diagram of D-A converter 13-4 7905 Group User ’ s Manual Rev.1.0 D-A CONVERTER 13.4 Setting method, 13.5 Operation description 13.4 Setting method Figure 13.4.1 shows an initial setting example of registers related to the D-A converter. Setting of a value to D-A register i b7 b0 D-A register 0 (Address 9816) D-A register 1 (Address 9916) A value (0016 to FF16) to be D-A converted is set. Setting of the D-Ai output enable bit to “1”. b7 b0 D-A control register (Address 9616) D-A0 output enable bit D-A1 output enable bit Analog voltage output started Fig. 13.4.1 Initial setting example of registers related to D-A converter 13.5 Operation description When any of the D-Ai output enable bits is set to “1,” the value loaded in D-A register i is converted to an analog voltage, and the analog voltage is output from pin DA i. The relationship between analog output voltage V and value n, which has been loaded in D-A register i, can be expressed as follows : V = V REF ✕ n ( n = 0 to 255) 256 VREF : R eference voltage 7905 Group User ’ s Manual Rev.1.0 13-5 D-A CONVERTER [Precautions for D-A converter] [Precautions for D-A converter] 1. Pin DA i i s multiplexed with an analog input pin and I/O pins for serial I/O. When any of the D-Ai o utput enable bits is set to “ 1 ” ( output enabled), the corresponding pin is used as pin DA i, not as any other multiplexed input/output pin (including a programmable I/O port pin). 2. When not using the D-A converter, be sure to do as follows: • C lear the D-A i ( i = 0, 1) output enable bit (bits 0, 1 at address 96 16) to “ 0. ” • C lear the contents of D-A register i (addresses 98 16, 99 16) to “ 00 16. ” 13-6 7905 Group User ’ s Manual Rev.1.0 CHAPTER 14 WATCHDOG TIMER 14.1 Block description 14.2 Operation description [Precautions for watchdog timer] WATCHDOG TIMER 14.1 Block description The watchdog timer functions as follows: q D etects a program runaway. q A t stop mode termination, measures a certain time after oscillation starts. (Refer to section “ 15.3 Stop mode.”) 14.1 Block description Figure 14.1.1 shows the block diagram of the watchdog timer, and registers relevant to the watchdog timer are described below. Watchdog timer frequency select bit f2 Wait mode Divided f(XIN) fX 16 fX 32 fX 64 fX 12 8 Watchdog timer clock source select bits at STP termination 1/ 16 1/ 16 Wf32 1 Wf512 0 Stop mode Watchdog timer interrupt request Watchdog timer ❈ “FFF16” is set. Disables watchdog timer (Note). Writing to watchdog timer register R ESET STP instruction • Watchdog timer register: address 6016 • Watchdog timer frequency select bit: bit 0 at address 6116 • Watchdog timer clock source select bits at STP termination: bits 7, 6 at address 6116 ❈ When the most significant bit of the watchdog timer becomes “0,” this signal will be generated. Note: During the stop mode and until the stop mode is terminated, setting for disabling the watchdog timer is ignored. (Refer to section “14.1.3 Particular function select register 2.”) Fig. 14.1.1 Block diagram of watchdog timer 14-2 7905 Group User’s Manual Rev.1.0 WATCHDOG TIMER 14.1 Block description 14.1.1 Watchdog timer Figure 14.1.2 shows the structure of the watchdog timer register. The watchdog timer is a 12-bit counter where the count source which is selected with the watchdog timer frequency select bit (bit 0 at address 61 16) is counted down. A value of “FFF 16” is automatically set in the watchdog timer if any of the following conditions is satisfied. An arbitrary value cannot be set to the watchdog timer. q q q q W hen dummy data is written to the watchdog timer register. (See Figure 14.1.2.) W hen the most significant bit of watchdog timer becomes “ 0. ” W hen the S TP i nstruction is executed. (Refer to section “ 15.3 Stop mode. ” ) A t reset b7 b0 Watchdog timer register (Address 6016) Bit 7 to 0 Function At reset R/W — Initializes the watchdog timer. Undefined When dummy data has been written to this register, the watchdog timer’s value is initialized to “FFF16” (dummy data: 0016 to FF16). Fig. 14.1.2 Structure of watchdog timer register 14.1.2 Watchdog timer frequency select register Figure 14.1.3 shows the structure of the watchdog timer frequency select register. b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer frequency select register (Address 6116) Bit 0 5 to 1 6 7 Bit name Watchdog timer frequency select bit Nothing is assigned. 0 : Wf512 1 : Wf32 Function At reset 0 Undefined b7 b6 R/W RW — RW RW Watchdog timer clock source 0 0 : fX32 select bits at STP termination 0 1 : fX16 1 0 : fX128 1 1 : fX64 0 0 Fig. 14.1.3 Structure of watchdog timer frequency select register (1) Watchdog timer frequency select bit (bit 0) This bit is used to select a count source of the watchdog timer. (2) Watchdog timer clock source select bits at STP termination (bits 7, 6) These bits are used to select a count source at stop mode termination. For details of the operation at stop mode termination, refer to section “ 15.3 Stop mode. ” 7905 Group User ’ s Manual Rev.1.0 14-3 WATCHDOG TIMER 14.1 Block description 14.1.3 Particular function select register 2 When not using the watchdog timer, this register can be used to disable the watchdog timer. Figure 14.1.4 shows the structure of the particular function select register 2. Particular function select register 2 (Address 6416) Bit 7 to 0 Function b7 b0 At reset Undefined R/W — Disables the watchdog timer. When values of “7916” and “5016” succeedingly in this order, the watchdog timer will stop its operation. Note: After reset, this register can be set only once. Writing to this register requires the following procedure: • Write values of “7916” and “5016” to this register succeedingly in this order. • For the above writing, be sure to use the MOVMB (MOVM when m = 1) instruction or the STAB (STA when m = 1). Note that the following: if an interrupt occurs between writing of “7916” and next writing of “5016,” the watchdog timer does not stop its operation. If any of the following has been performed after reset, writing to this register is disabled from that time: • If this register is read out. • If writing to this register is performed by the procedure other than the above procedure. Fig. 14.1.4 Structure of particular function select register 2 In addition, even when the watchdog timer is disabled by this register, the watchdog timer can be active only at the stop mode termination if the external clock input select bit (bit 1 at address 62 16) = “0.” (Refer to section “ 15.3 Stop mode. ”) 14-4 7905 Group User ’ s Manual Rev.1.0 WATCHDOG TIMER 14.2 Operation description 14.2 Operation description The operations of the watchdog timer are described below. 14.2.1 Basic operation ➀ W atchdog timer starts counting down from “ FFF 16. ” ➁ W hen the watchdog timer ’ s most significant bit becomes “ 0 ” ( counted 2048 times), a watchdog timer interrupt request occurs. (See Table 14.2.1.) ➂ W hen the interrupt request occurs in above ➁ , a value of “ FFF16” i s set to the watchdog timer. A watchdog timer interrupt is a non-maskable interrupt. When a watchdog timer interrupt request is accepted, the processor interrupt priority level (IPL) is set to “ 111 2. ” Table 14.2.1 Occurrence interval of watchdog timer interrupt request f(f sys) = 20 MHz frequency select bit Count source Occurrence interval (Note) 0 Wf512 52.43 ms 1 Wf 32 3.28 ms Note: This applies when the peripheral device’s clock select bits 1, 0 (bits 7, 6 at address BC16) = “002.” Watchdog timer 7905 Group User ’ s Manual Rev.1.0 14-5 WATCHDOG TIMER 14.2 Operation description Be sure to write dummy data to the watchdog timer register (address 6016) before the most significant bit of the watchdog timer becomes “ 0. ” W hen writing to the watchdog timer is not performed owing to a program runaway and the watchdog timer ’ s most significant bit becomes “ 0, ” a w atchdog timer interrupt request occurs. This informs that a program runaway has occurred. In order to reset the microcomputer when a program runaway has been detected, write “1” to the software reset bit (bit 6 at address 5E 16) in the watchdog timer interrupt routine. Figure 14.2.1 shows an example of a program runaway detected by the watchdog timer. Main routine Watchdog timer register (Address 6016) Watchdog timer interrupt request occurrence (In other words, program runaway is detected.) 8-bit dummy data Watchdog timer initialized (Value of watchdog timer : “FFF16”) (Note 1) Watchdog timer interrupt routine Software reset bit (bit 6 at address 5E16) “1” (Note 2) Reset microcomputer RTI Notes 1: Be sure to initialize the watchdog timer before the most significant bit of the watchdog timer becomes “0.” (In other words, be sure to write dummy data to address 6016 before a watchdog timer interrupt request occurs). 2: When a program runaway occurs, values of the data bank register (DT), direct page register (DPRi), etc., may be changed. When “1” is written to the software reset bit by an addressing mode using DT, DPRi, etc., be sure to set values to DT and DPRi, etc. again. Fig. 14.2.1 Example of program runaway detection by watchdog timer 14-6 7905 Group User ’ s Manual Rev.1.0 WATCHDOG TIMER 14.2 Operation description 14.2.2 Stop period The watchdog timer stops its operation in any of the following cases: ➀ D uring Wait mode (Refer to section “ 15.4 Wait mode. ”) ➁ D uring Stop mode (Refer to section “ 15.3 Stop mode. ”) When state ➀ has been terminated, the watchdog timer restarts counting from the state immediately before it stops its operation. For the watchdog timer’s operation at termination of state ➁, refer to section “14.2.3 Operation in stop mode. ” 14.2.3 Operations in stop mode When the S TP i nstruction has been executed, a value of “ FFF 16” i s set to the watchdog timer, and the watchdog timer stops its operation in the stop mode. Immediately after the stop mode termination, the watchdog timer operates as follows. (1) When stop mode is terminated by hardware reset Supply of φ CPU a nd φ BIU s tarts immediately after the stop mode termination, and the microcomputer performs “ operation after reset. ” ( Refer to “ CHAPTER 3. RESET. ” ) The watchdog timer frequency select bit becomes “ 0, ” a nd the watchdog timer starts counting of Wf 512 f rom “ FFF 16. ” (2) When stop mode is terminated by interrupt occurrence (with watchdog timer used) (Note) Immediately after the stop mode termination, the watchdog timer starts counting the count source selected by the watchdog timer clock source select bits at STP termination (bits 6, 7 at address 6116), starting from “ FFF 16. ” I t is independent of the watchdog timer frequency select bit (bit 0 at address 6116). When the most significant bit of the watchdog timer becomes “0,” supply of φ CPU and φBIU starts. (At this time, no watchdog timer interrupt request occurs.) When supply of φ CPU a nd φ BIU s tarts, the routine of the interrupt which the microcomputer used to terminate the stop mode is executed. The watchdog timer restarts counting of the count source (Wf32 or Wf512), which was counted immediately before execution of the STP instruction, starting from “FFF16.” Note: F or the setting of the usage of the watchdog timer, refer to section “ 15.3 Stop mode. ” (3) When stop mode is terminated by interrupt occurrence (with watchdog timer not used) (Note) Supply of φ CPU a nd φ BIU s tarts immediately after the stop mode termination, and the routine of the interrupt which the microcomputer used to terminate the stop mode is executed. The watchdog timer restarts counting of the count source (Wf32 or Wf512), which was counted immediately before execution of the S TP i nstruction, starting from “ FFF16. ” Note: F or the setting of the usage of the watchdog timer, refer to section “ 15.3 Stop mode. ” 7905 Group User ’ s Manual Rev.1.0 14-7 WATCHDOG TIMER [Precautions for watchdog timer] [Precautions for watchdog timer] 1. W hen dummy data has been written to address 60 16 w ith the 16-bit data length, writing to address 6116 is simultaneously performed. Accordingly, when the user does not want to change the contents of the watchdog timer frequency select bit (bit 0 at address 6116) and watchdog timer clock source select bits at STP termination (bits 6, 7 at address 61 16), be sure to write again the values which are currently set in these bits, simultaneously with writing to address 60 16. 2. W hen the S TP i nstruction is executed, the watchdog timer stops its operation. If the S TP i nstruction ’ s code (3116, 3016) has accidentally been executed owing to a program runaway, the watchdog timer stops its operation. Therefore, in the system where the watchdog timer is used to detect a program runaway, we recommend that the STP instruction invalidity select bit (bit 0 at address 6216) = “1.” (STP instruction is invalid.) Refer to section “ 15.3 Stop mode. ” 14-8 7905 Group User ’ s Manual Rev.1.0 CHAPTER 15 STOP AND WAIT MODES 15.1 15.2 15.3 15.4 Overview Block description Stop mode Wait mode S TOP AND WAIT MODES 15.1 Overview 15.1 Overview When there is no need for operation of the central processing unit (CPU), the stop and wait modes are used to stop oscillation or internal clock. As a result, the power consumption can be saved. The microcomputer enters the stop mode when the STP instruction has been executed; the microcomputer enters the wait mode when the W IT i nstruction has been executed. The stop and wait modes are terminated by an interrupt request occurrence or hardware reset. Table 15.1.1 lists the states in the stop and wait modes and operations after these modes are terminated. Table 15.1.1 States in stop and wait modes and operations after these modes are terminated Stop mode Item Oscillation φCPU, φ BIU fsys, clock φ 1, f1 to f4096 When watchdog timer is used at When watchdog timer is not used Inactive. Inactive. Inactive. Wait mode System clock is inactive. System clock is active. Active. Operates (Note 1). Inactive. Active. Inactive. termination (See Figure 15.3.1.) at termination (See Figure 15.3.1.) (Bit 3 at address 6316 = “0”) (Bit 3 at address 6316 = “1”) PLL frequency multiplier Stopped. States Inactive. Wf32, Wf512 Inactive. Timers A, B Can operate only in the event counter mode. Operates. Can operate only in the event counter mode. Can operate only when an external clock is selected. Stopped. Stopped. Internal peripheral Serial I/O Can operate only when an external clock is Operates. selected. Operates. Operates. Stopped. A-D converter Stopped. D-A converter Stopped. Watchdog timer Stopped. Retains the state at the STP instruction execution. Pins Operation after termination Retains the state at the WIT instruction execution. Termination due Supply of φCPU, φBIU starts after a Supply of φCPU, φBIU starts Supply of φ CPU, φ BIU s tarts immediately after to interrupt request certain time has been measured immediately after termi- termination. occurrence by using the watchdog timer. nation (Note 2). Termination due Operation after hardware reset Operation after hardware reset to hardware reset 2: See Table 15.3.2. Notes 1: This applies when the PLL circuit operation enable bit (bit 1 at address BC16) = “1.” 15-2 7905 Group User’s Manual Rev.1.0 Peripheral device’s clocks System clock stop select bit at WIT Wait mode PLL circuit operation enable bit 0 Peripheral device’s clock select bit 1 φ1 0 A-D conversion frequency (φAD) clock source Operating clock for serial I/O, timer B Operating clock for timer A PLL multiplication ratio select bits Peripheral device’s clock select bit 0 f1 f2 f16 f64 f512 1/8 1/4 1/8 1/8 f4096 15.2 Block description 1/2 PLL frequency fPLL multiplier 1 Interrupt request 1 0 S Q System clock select bit 1 STP instruction R fXIN 1/2 Wait mode 0 1 fsys 1/16 1/16 0 Watchdog timer frequency select bit Wf32 1 External clock input select bit f/n Wf512 fX16 fX32 fX64 fX128 VCONT Reset (Clock for BIU) S Q Wait mode STP instruction R CPU wait request Watchdog timer clock source select bits at STP termination Watchdog timer ❈ Interrupt request XIN φ BIU φ CPU (Clock for CPU) XOUT Interrupt request S Q Wait mode fX16 fX32 fX64 fX128 1 Figure 15.2.1 shows the block diagram of the clock generating circuit with the S TP a nd W IT i nstructions. Also, registers relevant to these modes are described below. Fig. 15.2.1 Block diagram of clock generating circuit with STP and WIT instructions 0 7905 Group User’s Manual Rev.1.0 External clock input select bit System clock frequency select bit • Watchdog timer frequency select bit • Watchdog timer clock source select bits at STP termination • External clock input select bit • System clock stop select bit at WIT • PLL circuit operation enable bit • PLL multiplication ratio select bits • System clock select bit • Peripheral device’s clock select bits 0, 1 : bit 0 at address 6116 : bits 6, 7 at address 6116 : bit 1 at address 6216 : bit 3 at address 6316 : bit 1 at address BC16 : bits 2, 3 at address BC16 : bit 5 at address BC16 : bits 6, 7 at address BC16 BIU : Bus interface Unit CPU : Central Processing Unit ❈ : Signal generated when the watchdog timer’s most significant bit becomes “0.” WIT instruction R S TOP AND WAIT MODES 15.2 Block description 15-3 S TOP AND WAIT MODES 15.2 Block description 15.2.1 Particular function select register 0 Figure 15.2.2 shows the structure of the particular function select register 0, and Figure 15.2.3 shows the writing procedure for the particular function select register 0. Particular function select register 0 (Address 6216) Bit 0 1 Bit name Function b7 b6 b5 b4 b3 b2 b1 b0 000000 At reset 0 0 R/W RW (Note) RW (Note) STP instruction invalidity select bit 0 : STP instruction is valid. 1 : STP instruction is invalid. External clcok input select bit 0 : Oscillation circuit is active. (Oscillator is connected.) Watchdog timer is used at stop mode termination. 1 : Oscillation circuit is inactive. (External clock is input.) When the system clock select bit (bit 5 at address BC16) = “0,” watchdog timer is not used at stop mode termination. When the system clock select bit = “1,” watchdog timer is used at stop mode termination. 7 to 2 Fix these bits to “000000.” 0 RW Note: Writing to these bits requires the following procedure: • Write “5516” to this register. (The bit status does not change only by this writing.) • Succeedingly, write “0” or “1” to each bit. Also, use the MOVMB (MOVM when m = 1) instruction or STAB (STA when m = 1) instruction. If an interrupt occurs between writing of “5516” and next writing of “0” or “1,” latter writing may be ignored. When there is a possibility that an interrupt occurs at the above timing, be sure to read this bit’s contents after writing of “0” or “1,” and verify whether “0” or “1” has correctly been written or not. Fig. 15.2.2 Structure of particular function select register 0 (1) STP instruction invalidity select bit (bit 0) Setting this bit to “1” invalidates the STP instruction. When using the stop mode, be sure to clear this bit to “ 0. ” Writing to this bit requires the following procedure: • W rite “ 55 16” t o address 62 16. • S ucceedingly, write “ 0 ” o r “ 1 ” t o this bit. (See Figure 15.2.3.) If an interrupt occurs between writing of “ 55 16” a nd next writing of “ 0 ” o r “ 1, ” l atter writing may be ignored. When there is a possibility that an interrupt occurs at the above timing, be sure to read this bit’s contents after writing of “0” or “1,” and verify whether “0” or “1” has correctly been written or not. 15-4 7905 Group User ’ s Manual Rev.1.0 S TOP AND WAIT MODES 15.2 Block description (2) External clock input select bit (bit 1) When this bit = “ 0, ” t he oscillation driver circuit between pins XIN a nd XOUT i s operationg. A t the stop mode termination owing to an interrupt occurrence, the watchdog timer is used. Setting this bit to “1” stops the oscillation driver circuit between pins XIN and XOUT and keeps the output level at pin X OUT b eing “ H. ” ( Refer to section “ 16.3 Stop of oscillation circuit.”) At the stop mode termination owing to an interrupt occurrence, the watchdog timer is not used if the system clock select bit (bit 5 at address BC 16) = “ 0, ” w here as the watchdog timer is used if the system clock select bit = “ 1. ” To rewrite this bit, write “ 0 ” o r “ 1 ” j ust after writing of “ 5516” t o address 62 16. (See Figure 15.2.3.) Note that if an interrupt occurs between writing of “ 55 16” a nd next writing of “ 0 ” o r “ 1, ” l atter writing may be ignored. When there is a possibility that an interrupt occurs at the above timing, be sure to read this bit ’ s contents after writing of “ 0 ” o r “ 1, ” a nd verify whether “ 0 ” o r “ 1 ” h as correctly been written or not. In addition, even when the watchdog timer is disabled by the particular function select register 2 (address 6416 ), the watchdog timer can be active only at the stop mode termination if this bit = “ 0. ” (Refer to section “ 15.3 Stop mode.” ) Writing of “5516” b7 b0 0 1 01 0 1 0 1 Particular function select register 0 (Address 6216) Note: Bits’ state does not change only by writing of “5516.” Next instruction Writing to bits 0, 1 b7 b0 00 0 0 0 0 Particular function select register 0 (Address 6216) STP instruction invalidity select bit 0 : STP instruction is valid. 1 : STP instruction is invalid. External clock input select bit 0 : Oscillation circuit is active. (Oscillator is connected.) Watchdog timer is used at stop mode termination. 1 : Oscillation circuit is inactive. (External clock is input.) When the system clock select bit (bit 5 at address BC16) = “0,” watchdog timer is not used at stop mode termination. When the system clock select bit = “1,” watchdog timer is used at stop mode termination. Setting completed Fig. 15.2.3 Writing procedure for particular function select register 0 7905 Group User ’ s Manual Rev.1.0 15-5 S TOP AND WAIT MODES 15.2 Block description 15.2.2 Particular function select register 1 Figure 15.2.4 shows the structure of the particular function select register 1. b7 b6 b5 b4 b3 b2 b1 b0 Particular function select register 1 (Address 6316) Bit 0 1 2 3 4 5 6 Bit name STP-instruction-execution status bit WIT-instruction-execution status bit Fix this bit to “0.” System clock stop select bit at WIT (Note 3) Fix this bit to “0.” The value is “0” at reading. Timer B2 clock source select bit 0 : External signal input to the TB2IN pin is counted. (Valid in event counter mode.) 1 : fX32 is counted. (Note 4) The value is “0” at reading. 0 : In the wait mode, system clock fsys is active. 1 : In the wait mode, system clock fsys is inactive. Function 0 : Normal operation. 1 : During execution of STP instruction 0 : Normal operation. 1 : During execution of WIT instruction 0 0 R/W RW (Note 2) RW (Note 2) RW RW RW — RW At reset (Note 1) (Note 1) 0 0 0 0 0 7 0 — Notes 1: At power-on reset, this bit becomes “0.” At hardware reset or software reset, this bit retains the value just before reset. 2: Even when “1” is written, the bit status will not change. 3: Setting this bit to “1” must be performed just before execution of the WIT instruction. Also, after the wait state is terminated, this bit must be cleared to “0” immediately. 4: When using timer B2 in the pulse period/pulse width measurement mode, be sure to clear this bit to “0.” Fig. 15.2.4 Structure of particular function select register 1 (1) STP-instruction-execution status bit (bit 0) When the microcomputer enters the stop mode, this bit becomes “1,” indicating that the STP instruction has been executed. This bit becomes “0” at power-on reset. At hardware reset and software reset, this bit retains the value immediately before reset. Therefore, this bit is used for the following verification: • W hich of the power-on reset and hardware reset has been used to reset the system? • H as the hardware reset been used for the stop mode termination? This bit is cleared to “ 0 ” b y writing “ 0 ” t o this bit. Although, even when “ 1 ” i s written to this bit, this bit does not change. At the stop mode termination, be sure to clear this bit to “ 0 ” b y software. (2) WIT-instruction-execution status bit (bit 1) When the microcomputer enters the wait mode, this bit becomes “1,” indicating that the WIT instruction has been executed. This bit becomes “0” at power-on reset. At hardware reset and software reset, this bit retains the value immediately before reset. Therefore, this bit is used for the following verification: • W hich of the power-on reset and hardware reset has been used to reset the system? • H as the hardware reset been used for the wait mode termination? This bit is cleared to “ 0 ” b y writing “ 0 ” t o this bit. Although, even when “ 1 ” i s written to this bit, this bit does not change. At the wait mode termination, be sure to clear this bit to “ 0 ” b y software. 15-6 7905 Group User ’ s Manual Rev.1.0 S TOP AND WAIT MODES 15.2 Block description 15.2.3 Watchdog timer frequency select register Figure 15.2.5 shows the structure of the watchdog timer frequency select register. b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer frequency select register (Address 6116) Bit 0 5 to 1 6 7 Bit name Watchdog timer frequency select bit Nothing is assigned. Watchdog timer clock source 0 0 : fX32 select bits at STP termination 0 1 : fX16 1 0 : fX128 1 1 : fX64 b7 b6 Function 0 : Wf512 1 : Wf32 At reset 0 Undefined 0 0 R/W RW — RW RW Fig. 15.2.5 Structure of watchdog timer frequency select register (1) Watchdog timer clock source select bits at STP termination (bits 7, 6) These bits are used to select a count source at stop mode termination. For details of the operation at stop mode termination, refer to section “ 15.3 Stop mode. ” 7905 Group User ’ s Manual Rev.1.0 15-7 S TOP AND WAIT MODES 15.3 Stop mode 15.3 Stop mode When the S TP i nstruction has been executed, each of the oscillation and the PLL frequency multiplier ’ s operation becomes inactive. This state is called “ stop mode. ” ( See Table 15.1.1) In the stop mode, even when oscillation becomes inactive, the contents of the internal RAM can be retained if Vcc (the power source voltage) ≥ V RAM ( RAM hold voltage). Furthermore, since the CPU and internal peripheral devices which use any of clocks f1 to f4096, Wf32, Wf512 stop their operations, the power consumption can be saved. The stop mode is terminated owing to an interrupt request occurrence or hardware reset. When terminated owing to an interrupt request occurrence, an instruction can be executed immediately after termination if all of the following conditions are satisfied. (Refer to section “15.3.2 Terminate operation at interrupt request occurrence (when not using watchdog timer). ” ): • An stable clock is input from the external. (The external clock input select bit (bit 1 at address 6216) = “1.”) • T he PLL frequency multiplier is not used. (The system clock select bit (bit 5 at address BC 16) = “ 0. ” ) When terminated owing to an interrupt request occurrence, an instruction will be executed after the oscillation stabilizing time has been measured by using the watchdog timer if any of the following conditions is satisfied. (Refer to section “15.3.1 Terminate operation at interrupt request occurrence (when using watchdog timer).”): • A n oscillator is used. (The external clock input select bit (bit 1 at address 62 16) = “ 0. ” ) • T he PLL frequency multiplier is used. (The system clock select bit (bit 5 at address BC 16) = “ 1. ” ) 15.3.1 Terminate operation at interrupt request occurrence (when using watchdog timer) At the stop mode termination, execution of an instruction is started after a certain time has been measured by using the watchdog timer. (See Figure 15.3.1.) ➀ When an interrupt request occurs, an oscillator starts its operation. Also, when the PLL circuit operation enable bit (bit 1 at address BC16) = “1,” the PLL frequency multiplier starts its operation. Simultaneously with this, each supply of clocks fsys, φ 1, f1 t o f 4096, Wf 32, Wf 512 s tarts. ➁ B y start of oscillation in ➀, the watchdog timer starts its operation. Regardless of the watchdog timer frequency select bit (bit 0 at address 6116), the watchdog timer counts a count source (fX 16 t o fX 128), which is selected by the watchdog timer clock source select bits at STP termination (bits 7, 6 at address 61 16). This counting is started from a value of “ FFF 16. ” ➂ When the most significant bit (MSB) of the watchdog timer becomes “0,” each supply of φCPU, φBIU starts. (At this time, no watchdog timer interrupt request occurs.) Also, the count source of the watchdog timer returns to the count source selected by the watchdog timer frequency select bits (in order words, Wf 32 or Wf512). ➃ T he interrupt request which occurred in ➀ i s accepted. For the watchdog timer, refer to “ CHAPTER 14. WATCHDOG TIMER. ” Table 15.3.1 lists the interrupts which can be used to terminate the stop mode. Table 15.3.1 Interrupts which can be used to terminate stop mode Interrupt INTi interrupt (i = 0 to 7) Timer Ai interrupt (i = 0 to 9) Timer Bi interrupt (i = 0 to 2) UARTi transmit interrupt (i = 0 to 2) UARTi receive interrupt (i = 0 to 2) Notes 1: When multiple interrupts are enabled, the stop mode is terminated owing to the interrupt request which occurs first. 2: For interrupts, refer to “CHAPTER 6. INTERRUPTS” and each peripheral device’s chapter. When an external clock is selected. In event counter mode Usage condition for interrupt request occurrence 15-8 7905 Group User ’ s Manual Rev.1.0 S TOP AND WAIT MODES 15.3 Stop mode Before executing the STP instruction, be sure to enable an interrupt which is to be used for the stop mode termination. Also, make sure that the interrupt priority level of an interrupt, which is to be used for the termination, is higher than the processor interrupt priority level (IPL) of a routine where the STP instruction is executed. After oscillation starts (➀), there is a possibility that each interrupt request occurs until the supply of φ CPU, φ BIU s tarts ( ➂). The interrupt requests which occurred during this period are accepted in order of priority after the watchdog timer’s MSB becomes “0.” (When the level sense of an INTi interrupt is used, however, no interrupt request is retained. Therefore, if pin INT i is at the invalid level when the watchdog timer’s MSB becomes “0,” no interrupt request is accepted.) For an interrupt which has no need to be accepted, be sure to set its interrupt priority level to “ 0 ” ( Interrupt disabled) before executing the S TP i nstruction. 15.3.2 Terminate operation at interrupt request occurrence (when not using watchdog timer) At the stop mode termination, an instruction is executed without use of the watchdog timer. (See Figure 15.3.1.) ➀ When an interrupt request occurs, clock input from pin XIN starts. Simultaneously, supply of clocks f sys, φ 1, f1 t o f 4096, Wf 32, Wf 512 s tarts. ➁ S upply of φ CPU, φ BIU s tarts after the time listed in Table 15.3.2 has elapsed. ➂ T he interrupt request which occurred in ➀ i s accepted. Table 15.3.2 Time after stop mode is terminated until supply of φCPU, φ BIU s tarts Watchdog timer clock source select bits at STP termination (bits 7, 6 at address 6116) 00 01 10 11 Time until supply of φCPU and φBIU starts fXIN ✕ 19 cycles fXIN ✕ 11 cycles fXIN ✕ 67 cycles fXIN ✕ 35 cycles Before executing the S TP i nstruction, be sure to set as follows: s E nable an interrupt which is to be used for the stop mode termination. Also, make sure that the interrupt priority level of an interrupt, which is to be used for the termination, is higher than the processor interrupt priority level (IPL) of a routine where the S TP i nstruction is executed. s T he external clock input select bit (bit 1 at address 62 16) = “ 1 ” ( Note) s T he system clock select bit (bit 5 at address BC 16) = “ 0 ” ( Note) Note: S imultaneously, the oscillation driver circuit between pins X IN a nd X OUT s tops, and the output level at pin X OUT i s kept “ H. ” ( Refer to section “ 16.3 Stop of oscillation circuit. ”) 7905 Group User ’ s Manual Rev.1.0 15-9 S TOP AND WAIT MODES 15.3 Stop mode s When using watchdog timer Stop mode fXIN fPLL (Note) φ1 φBIU Interrupt request to be used for stop mode termination (Interrupt request bit) Value of watchdog timer 7FF16 fXi ✕ 2048 counts FFF16 CPU Internal peripheral devices Operating Operating Stopped Stopped Stopped Operating Operating Operating q STP instru- q Interrupt request to be used for ction is termination occurs. executed. q Oscillation starts. (When an external clock is input from pin XIN, clock input starts.) q PLL frequency multiplier starts its operation. q Watchdog timer starts counting. q Watchdog timer’s MSB = “0” (However, watchdog timer interrupt request does not occur.) q Each supply of φCPU, φBIU starts. q Interrupt request which was used for termination is accepted. Note: This applies when the PLL circuit operation enable bit (bit 1 at address BC16) = “1.” fXi : fX16, fX32, fX64, fX128. These are clocks selected by the watchdog timer clock source select bits at STP termination (bits 7, 6 at address 61 16.) s When not using watchdog timer Stop mode fXIN φ1 φBIU Interrupt request to be used for stop mode termination (Interrupt request bit) Value of watchdog timer 7FF16 (Note) FFF16 CPU Internal peripheral devices Operating Operating Stopped Stopped Stopped Operating Operating Operating q STP instru- q Interrupt q Each supply of φCPU, φBIU starts. ction is request to q Interrupt request which was used executed. be used for for termination is accepted. termination occurs. q Clock input from pin XIN starts. q Watchdog timer starts counting. Note: Time listed in Table 15.3.2. See Figure 19.1.3 for the built-in flash memory version. Fig. 15.3.1 Stop mode terminate sequence owing to interrupt request occurrence 15-10 7905 Group User ’ s Manual Rev.1.0 S TOP AND WAIT MODES 15.3 Stop mode 15.3.3 Terminate operation at hardware reset Although each of the CPU and SFR area is initialized, the contents of the internal RAM immediately before the STP instruction execution are retained. The terminate sequence is the same as the internal processing sequence after reset. For reset, refer to “ CHAPTER 3. RESET. ” Also, the STP-instruction-execution status bit (bit 0 at address 6316) is used for the following verification: • W hich of the power-on reset and hardware reset has been used to reset the system? • H as the hardware reset been used for the stop mode termination? 7905 Group User ’ s Manual Rev.1.0 15-11 S TOP AND WAIT MODES 15.4 Wait mode 15.4 Wait mode When the W IT i nstruction is executed, both of φ CPU a nd φ BIU b ecome inactive. (The oscillation does not become inactive.) This state is called “ wait mode. ” ( See Table 15.1.1.) In the wait mode, the power consumption can be saved with Vcc (the power source voltage) retained. When using no internal peripheral device in the wait mode, the power consumption can be saved furthermore since each of f sys a nd internal peripheral device ’ s operation clock can be inactive. (Refer to section “ 16.2 Stop of system clock in wait mode. ” ) The wait mode is terminated owing to an interrupt request occurrence or hardware reset. The wait mode terminate operation is described below. 15.4.1 Terminate operation at interrupt request occurrence ➀ W hen an interrupt request occurs, each supply of φ CPU a nd φ BIU s tarts. ➁ T he interrupt request which occurred in ➀ i s accepted. Table 15.4.1 lists the interrupts which can be used for the wait mode termination. Table 15.4.1 Interrupts which can be used for wait mode termination Usage conditions for interrupt request occurrences Interrupt System clock in action System clock out of action INTi interrupt (i = 0 to 7) Timer Ai interrupt (i = 0 to 9) Timer Bi interrupt (i = 0 to 2) UARTi transmit interrupt (i = 0 to 2) UARTi receive interrupt (i = 0 to 2) A-D conversion interrupt Do not use. Notes 1: When multiple interrupts are enabled, the wait mode is terminated owing to the interrupt request which occurs first. 2: For interrupts, refer to “CHAPTER 6. INTERRUPTS” and each peripheral device’s chapter. Before executing the WIT instruction, be sure to enable an interrupt which is to be used for the wait mode termination. Also, make sure that the interrupt priority level of an interrupt, which is to be used for termination, is higher than the processor interrupt priority level (IPL) of a routine where the W IT i nstruction is executed. Also, when multiple interrupts in Table 15.4.1 are enabled, the wait mode is terminated owing to the interrupt request which occurs first. 15.4.2 Terminate operation at hardware reset Although each of the CPU and SFR area is initialized, the contents of the internal RAM immediately before the WIT instruction execution are retained. The terminate sequence is the same as the internal processing sequence after reset. For reset, refer to “ CHAPTER 3. RESET. ” Also, the WIT-instruction-execution status bit (bit 1 at address 6316) is used for the following verification: • W hich of the power-on reset and hardware reset has been used to reset the system? • H as the hardware reset been used for the wait mode termination? When an external clock is selected. In event counter mode 15-12 7905 Group User ’ s Manual Rev.1.0 CHAPTER 16 POWER SAVING FUNCTIONS 16.1 Overview 16.2 I nactivity of system clock in wait mode 16.3 Stop of oscillation circuit 16.4 Pin VREF d isconnection P OWER SAVING FUNCTIONS 16.1 Overview This chapter explains the functions to save the power consumption of the microcomputer and the total system including the microcomputer. 16.1 Overview Table 16.1.1 lists the overview of the power saving functions. Each of these functions saves the power consumption of the total system. The registers related to the power saving functions are explained in the following. Table 16.1.1 Overview of power saving functions Item Function Reference Inactivity of system clock in In the wait mode, operating clocks for the internal peripheral CHAPTER 15. STOP devices and fsys can be inactive. wait mode AND WAIT MODES Stop of oscillation circuit When a stable clock externally generated is used, the drive CHAPTER 4. CLOCK circuit for oscillation between pins XIN and XOUT can be stopped. GENERATING CIRCUIT, (The output level at pin XOUT is fixed to “H.”) Pin VREF disconnection Section 15.3 Stop mode The VREF input can be disconnected when the A-D converter CHAPTER 12. A-D CONVERTER is not used 16-2 7905 Group User’s Manual Rev.1.0 P OWER SAVING FUNCTIONS 16.1 Overview 16.1.1 Particular function select register 0 Figure 16.1.1 shows the structure of the particular function select register 0, and Figure 16.1.2 shows the writing procedure for the particular function select register 0. Particular function select register 0 (Address 6216) Bit 0 1 Bit name Function b7 b6 b5 b4 b3 b2 b1 b0 000000 At reset 0 0 R/W RW (Note) RW (Note) STP instruction invalidity select bit 0 : STP instruction is valid. 1 : STP instruction is invalid. External clcok input select bit 0 : Oscillation circuit is active. (Oscillator is connected.) Watchdog timer is used at stop mode termination. 1 : Oscillation circuit is inactive. (External clock is input.) When the system clock select bit (bit 5 at address BC16) = “0,” watchdog timer is not used at stop mode termination. When the system clock select bit = “1,” watchdog timer is used at stop mode termination. 7 to 2 Fix these bits to “000000.” 0 RW Note: Writing to these bits requires the following procedure: • Write “5516” to this register. (The bit status does not change only by this writing.) • Succeedingly, write “0” or “1” to each bit. Also, use the MOVMB (MOVM when m = 1) instruction or STAB (STA when m = 1) instruction. If an interrupt occurs between writing of “5516” and next writing of “0” or “1,” latter writing may be ignored. When there is a possibility that an interrupt occurs at the above timing, be sure to read this bit’s contents after writing of “0” or “1,” and verify whether “0” or “1” has correctly been written or not. Fig. 16.1.1 Structure of particular function select register 0 7905 Group User’s Manual Rev.1.0 16-3 P OWER SAVING FUNCTIONS 16.1 Overview (1) External clock input select bit (bit 1) When this bit = “0,” the oscillation driver circuit between pins X IN a nd X OUT i s operationg. A lso, at the stop mode termination owing to an interrupt request occurrence, the watchdog timer is used. Setting this bit to “1” stops the oscillation driver circuit between pins XIN and XOUT and keeps the output level at pin X OUT b eing “H.” (Refer to section “ 16.3 Stop of oscillation circuit.” ) At the stop mode termination owing to an interrupt request occurrence, the watchdog timer is not used if the system clock select bit (bit 5 at address BC16) = “0,” where as the watchdog timer is used if the system clock select bit = “1.” To rewrite this bit, write “0” or “1” just after writing of “5516” to address 62 16. (See Figure 16.1.2.) Note that if an interrupt occurs between writing of “55 16” and next writing of “0” or “1,” latter writing may be ignored. When there is a possibility that an interrupt occurs at the above timing, be sure to read this bit’s contents after writing of “0” or “1,” and verify whether “0” or “1” has correctly been written or not. In addition, even when the watchdog timer is disabled by the particular function select register 2 (address 64 16), the watchdog timer can be active only at the stop mode termination if this bit = “0.” (Refer to section “ 15.3 Stop mode.” ) Writing of “5516” b7 b0 0 1 01 0 1 0 1 Particular function select register 0 (Address 6216) Note: Bits’ state does not change only by writing of “5516.” Next instruction Writing to bits 0, 1 b7 b0 00 0 0 0 0 Particular function select register 0 (Address 6216) STP instruction invalidity select bit 0 : STP instruction is valid. 1 : STP instruction is invalid. External clock input select bit 0 : Oscillation circuit is active. (Oscillator is connected.) Watchdog timer is used at stop mode termination. 1 : Oscillation circuit is inactive. (External clock is input.) When the system clock select bit (bit 5 at address BC16) = “0,” watchdog timer is not used at stop mode termination. When the system clock select bit = “1,” watchdog timer is used at stop mode termination. Setting completed Fig. 16.1.2 Writing procedure for particular function select register 0 16-4 7905 Group User’s Manual Rev.1.0 P OWER SAVING FUNCTIONS 16.1 Overview 16.1.2 Particular function select register 1 Figure 16.1.3 shows the structure of the particular function select register 1. b7 b6 b5 b4 b3 b2 b1 b0 Particular function select register 1 (Address 6316) Bit 0 1 2 3 4 5 6 Bit name STP-instruction-execution status bit WIT-instruction-execution status bit Fix this bit to “0.” System clock stop select bit at WIT (Note 3) Fix this bit to “0.” The value is “0” at reading. Timer B2 clock source select bit 0 : External signal input to the TB2IN pin is counted. (Valid in event counter mode.) 1 : fX32 is counted. (Note 4) The value is “0” at reading. 0 : In the wait mode, system clock fsys is active. 1 : In the wait mode, system clock fsys is inactive. Function 0 : Normal operation. 1 : During execution of STP instruction 0 : Normal operation. 1 : During execution of WIT instruction 0 0 R/W RW (Note 2) RW (Note 2) RW RW RW — RW At reset (Note 1) (Note 1) 0 0 0 0 0 7 0 — Notes 1: At power-on reset, this bit becomes “0.” At hardware reset or software reset, this bit retains the value just before reset. 2: Even when “1” is written, the bit status will not change. 3: Setting this bit to “1” must be performed just before execution of the WIT instruction. Also, after the wait state is terminated, this bit must be cleared to “0” immediately. 4: When using timer B2 in the pulse period/pulse width measurement mode, be sure to clear this bit to “0.” Fig. 16.1.3 Structure of particular function select register 1 (1) System clock stop select bit at WIT (bit 3) Setting this bit to “ 1 ” m akes the following clocks inactive in the wait mode: the operating clocks for the internal peripheral devices and f sys. (Refer to section “ 16.2 Inactivity of system clock in wait mode.” ) 7905 Group User ’ s Manual Rev.1.0 16-5 P OWER SAVING FUNCTIONS 16.2 Inactivity of system clock in wait mode 16.2 Inactivity of system clock in wait mode In the wait mode, if there is not need to operate the internal peripheral devices, setting the system clock stop select bit at WIT (See Figure 16.1.3.) to “1” makes the following clocks inactive: the operating clocks for the internal peripheral devices and f sys. This saves the power consumption of the microcomputer. Table 16.2.1 lists the states and operations in the wait mode and after this mode is terminated. Table 16.2.1 States and operations in wait mode and after this mode is terminated Item Oscillation φCPU, φBIU fsys, Clock φ 1, f1 to f4096 System clock is active. (bit 3 at address 6316 = 0) System clock is inactive. (bit 3 at address 6316 = 1) Active. Inactive. Active. Inactive. Operates. Operates. Operates. Can operate only in the event counter mode. Can operate only when an external clock is selected. Stopped. Inactive. PLL frequency multiplier Operates (Note). States Internal peripheral devices Wf32, Wf512 Timers A, B Serial I/O A-D converter D-A converter Stopped. Operates. Watchdog timer Stopped. Pins Retains the state at the WIT instruction execution. Supply of φCPU, φBIU starts immediately just after termination. Operation after termination Termination due to interrupt request occurrence Termination due to hardware reset Operation after hardware reset Note: This applies when the PLL circuit operation enable bit (bit 1 at address BC16) = “1.” 16-6 7905 Group User ’ s Manual Rev.1.0 P OWER SAVING FUNCTIONS 16.3 Stop of oscillation circuit, 16.4 Pin V REF d isconnection 16.3 Stop of oscillation circuit When a stable clock externally generated is input to pin X IN, power consumption can be saved by setting the external clock input select bit to “ 1 ” t o stop the drive circuit for oscillation between pins X IN a nd X OUT. (See Figure 16.1.1.) At this time, the output level at pin XOUT is fixed to “H.” Also, if the system clock select bit (bit 5 at address BC 16) = “ 0, ” t he watchdog timer is not used when the stop mode is terminated owing to an interrupt request occurrence; therefore, the microcomputer can start instruction execution just after termination of the stop mode. When the system clock select bit = “ 1, ” i n this case, the watchdog timer is used. 16.4 Pin VREF d isconnection When the A-D converter is not used, power consumption can be saved by setting the VREF connection select bit (See Figure 16.4.1) to “1.” It is because the reference voltage input pin (V REF) is disconnected from the ladder resistors of the A-D converter, and there is no current flow between them. When the VREF connection select bit has been cleared from “1” (VREF disconnected) to “0” (VREF connected), be sure to start the A-D conversion after an interval of 1 µs or more has elapsed. b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 1 (Address 1F16) Bit 0 Bit name A-D sweep pin select bits (Valid in the single sweep mode, b1 b0 0 Function Single sweep mode/Repeat sweep mode 0 At reset 1 R/W RW 0 0 : Pins AN0 and AN1 (2 pins) repeat sweep mode 0, and 0 1 : Pins AN0 to AN3 (4 pins) repeat sweep mode 1.) (Note 1) 1 0 : Pins AN0 to AN5 (6 pins) 1 1 : Pins AN0 to AN7 (8 pins) (Note 2) 1 Repeat sweep mode 1 b1 b0 (Note 3) 1 RW 0 0 : Pin AN0 (1 pin) 0 1 : Pins AN0 and AN1 (2 pins) 1 0 : Pins AN0 to AN2 (3 pins) 1 1 : Pins AN0 to AN3 (4 pins) 2 A-D operation mode select bit 1 0 : Repeat sweep mode 0 (Used in the repeat sweep mode 0 1 : Repeat sweep mode 1 and repeat sweep mode 1.)(Note 4) Resolution select bit 0 : 8-bit resolution mode 1 : 10-bit resolution mode A-D conversion frequency (φAD) select bit 1 See Table 12.2.1. Fix this bit to “0.” VREF connection select bit (Note 5) The value is “0” at reading. 0 : Pin VREF is connected. 1 : Pin VREF is disconnected. 0 RW 3 4 5 6 7 0 0 0 0 0 RW RW RW RW – Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either “0” or “1.”) 2: When using pin AN7, be sure that the D-A0 output enable bit (bit 0 at address 9616) = “0” (output disabled). 3: Be sure to select the frequently-used analog input pins in the repeat sweep mode 1. 4: Fix this bit to “0” in the one-shot mode, repeat mode, and single sweep mode. 5: When this bit is cleared from “1” to “0,” be sure to start the A-D conversion after an interval of 1 µs or more has elapsed. 6: Writing to each bit of the A-D control register 1 must be performed while the A-D converter halts, regardless of the A-D operation mode. Fig. 16.4.1 Structure of A-D control register 1 7905 Group User ’ s Manual Rev.1.0 16-7 P OWER SAVING FUNCTIONS 16.4 Pin V REF d isconnection MEMORANDUM 16-8 7905 Group User ’ s Manual Rev.1.0 CHAPTER 17 DEBUG FUNCTION 17.1 Overview 17.2 Block description 17.3 Address matching detection mode 17.4 Out-of-address-area detection mode [Precautions for debug function] DEBUG FUNCTION 17.1 Overview, 17.2 Block description 17.1 Overview When the CPU fetches an op code (op-code fetch), the debug function generates an address matching detection interrupt request if a selected condition is satisfied as a result of comparison between the address where the op code to be fetched is stored (in other words, the contents of PG and PC) and the specified address. The debug function provides the following 2 modes: (1) Address matching detection mode When the contents of PG and PC match with the specified address, an address matching detection interrupt request occurs. This mode can be used for avoiding or modifying a portion of a program. (2) Out-of-address-area detection mode When the contents of PG and PC go out of the specified area, an address matching detection interrupt request occurs. This mode can be used for the program runaway detection by specifying the area where a program exists. Note that an address matching detection interrupt is a non-maskable software interrupt. For details of this interrupt, refer to “ CHAPTER 6. INTERRUPTS.” In addition, the debug function cannot be evaluated by a debugger. Therefore, do not use a debugger when using the debug function. 17.2 Block description Figure 17.2.1 shows the block diagram of the debug function, and the registers relevant to this function are described in the following. Internal data bus (DB0 to DB15) Debug control register 0 Address compare register 0 Address compare register 1 Debug control register 1 Matching • Compare register Matching • Compare register Address matching detect circuit Address matching detection interrupt CPU bus (Address) Fig. 17.2.1 Block diagram of debug function 17-2 7905 Group User’s Manual Rev.1.0 DEBUG FUNCTION 17.2 Block description 17.2.1 Debug control register 0 Figure 17.2.2 shows the structure of the debug control register 0. b7 b6 b5 b4 b3 b2 b1 b0 Debug control register 0 (Address 6616) Bit 0 1 2 3 4 5 6 7 Detect enable bit Fix this bit to “0.” The value is “1” at reading. 0 : Detection disabled. 1 : Detection enabled. Fix these bits to “00.” (Note 1) Bit name Detect condition select bits b2 b1 b0 0 Function 0 0 0 : Do not select. 0 0 1 : Address matching detection 0 0 1 0 : Address matching detection 1 0 1 1 : Address matching detection 2 1 0 0 : Do not select. 1 0 1 : Out-of-address-area detection 110: Do not select. 111: 00 At reset (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) 1 R/W RW RW RW RW RW RW RW — Notes 1: These bits are valid when the detect enable bit (bit 5) = “1.” Therefore, these bits must be set before or simultaneously with setting of the detect enable bit to “1.” 2: At power-on reset, each bit becomes “0”; at hardware reset or software reset, each bit retains the value immediately before reset. Fig. 17.2.2 Structure of debug control register 0 (1) Detect condition select bits (bits 0 to 2) These bits are used to select an occurrence condition for an address matching detection interrupt request. This condition can be selected from the following: s A ddress matching detection 0 An address matching detection interrupt request occurs when the contents of PG and PC match with the address being set in the address compare register 0 (addresses 68 16 t o 6A 16); (Refer to section “ 17.3 Address matching detection mode.” ) s A ddress matching detection 1 An address matching detection interrupt request occurs when the contents of PG and PC match with the address being set in the address compare register 1 (addresses 6B16 t o 6D 16); (Refer to section “ 17.3 Address matching detection mode.” ) s A ddress matching detection 2 An address matching detection interrupt request occurs when the contents of PG and PC match with the address being set in the address compare register 0 (addresses 6816 to 6A 16) or address compare register 1 (addresses 6B16 to 6D16); (Refer to section “17.3 Address matching detection mode.”) s Out-of-address-area detection An address matching detection interrupt request occurs when the contents of PG and PC are less than the address being set in the address compare register 0 (addresses 68 16 t o 6A 16) or larger than the address compare register 1 (addresses 6B 16 t o 6D 16); (Refer to section “ 17.4 Out-ofaddress-area detection mode.”) 7905 Group User ’ s Manual Rev.1.0 17-3 DEBUG FUNCTION 17.2 Block description (2) Detect enable bit (bit 5) If any selected condition is satisfied when this bit = “ 1, ” a n address matching detection interrupt request occurs. 17.2.2 Debug control register 1 Figure 17.2.3 shows the structure of the debug control register 1. b7 b6 b5 b4 b3 b2 b1 b0 Debug control register 1 (Address 6716) Bit 0 1 2 3 4 5 6 Bit name Fix this bit to “0.” The value is “0” at reading. Address compare register access enable bit (Note 2) 0 : Disabled. 1 : Enabled. Function 1 At reset (Note 1) (Note 1) 0 0 Undefined 0 0 0 R/W RW RO RW RW — RO RO Fix this bit to “1” when using the debug function. Nothing is assigned. While a debugger is not used, the value is “0” at reading. While a debugger is used, the value is “1” at reading. Address-matching-detection 2 decision bit (Valid when the address matching detection 2 is selected.) The value is “0” at reading. 0 : Matches with the contents of the address compare register 0. 1 : Matches with the contents of the address compare register 1. 7 0 — Notes 1: At power-on reset, each bit become “0”; at hardware reset or software reset, each bit retains the value immediately before reset. 2: Be sure to set this bit to “1” immediately before the access to the address compare registers 0 and 1 (addresses 6816 to 6D16). Then, be sure to clear this bit to “0” immediately after this access. Fig. 17.2.3 Structure of debug control register 1 (1) Address compare register access enable bit (bit 2) Setting this bit to “1” enables reading from or writing to the contents of address compare registers 0 and 1 (addresses 68 16 t o 6D 16), while clearing this bit to “ 0 ” d isables this reading or writing. Be sure to set this bit to “ 1 ” i mmediately before reading from or writing to the address compare registers 0 and 1, and then clear it to “ 0 ” i mmediately after this reading or writing. (2) Address-matching-detection 2 decision bit (bit 6) When the address matching detection 2 is selected, this bit is used to decide which of the addresses being set in the address compare registers 0 and 1 matches with the contents of PG and PC. This bit is cleared to “ 0 ” w hen the contents of PG and PC matches with the address being set in address compare register 0 and set to “1” when the contents of PG and PC match with the one being set in the address compare register 1. This bit is invalid when the address matching detection 0 and 1 are selected. 17-4 7905 Group User ’ s Manual Rev.1.0 DEBUG FUNCTION 17.2 Block description 17.2.3 Address compare registers 0 and 1 Each of the address compare registers 0 and 1 consists of 24 bits, and the address to be detected is set here. Figure 17.2.4 shows the structures of the address compare registers 0 and 1. Address compare register 0 (Addresses 6A16 to 6816) Address compare register 1 (Addresses 6D16 to 6B16) Bit 23 to 0 Function (b23) (b16) (b15) (b8) b0 b7 b7 b0 b7 b0 At reset R/W RW The address to be detected (in other words, the start address of instructions) is set here. Undefined Note: When accessing to these registers, be sure to set the address compare register access enable bit (bit 2 at address 6716) to “1” immediately before the access. Then, be sure to clear this bit to “0” immediately after this access. Fig. 17.2.4 Structures of address compare registers 0 and 1 At op-code fetch, the contents of PG and PC are compared with the addresses being set in the address compare register 0 or 1. Therefore, be sure to set the start address of an instruction into the address compare register 0 or 1. If such an address as in the middle of instructions or in the data table is set into the address compare register 0 or 1, no address matching detection interrupt request occurs because this address does not match with the contents of PG and PC. Note that, before the instruction at the address being set in the address compare register 0 or 1 is executed, an address matching detection interrupt request occurs and is accepted. 7905 Group User ’ s Manual Rev.1.0 17-5 DEBUG FUNCTION 17.3 Address matching detection mode 17.3 Address matching detection mode When the contents of PG and PC match with the specified address, an address matching detection interrupt request occurs. 17.3.1 Setting procedure for address matching detection mode Figure 17.3.1 shows an initial setting example for registers relevant to the address matching detection mode. Disables interrupts. The interrupt disable flag (I) is set to “1.” Selection of detect condition b7 b0 b7 b0 0 Debug control register 0 (Address 6616) Detect condition select bits b2 b1 b0 Debug control register 1 (Address 6716) Address compare register access enable bit (Note 1) 0 : Disabled. 0000 0 0 1 : Address matching detection 0 0 1 0 : Address matching detection 1 0 1 1 : Address matching detection 2 Detect enable bit 0 : Detection disabled. Set the detect enable bit to “1.” b7 b0 1 Processing for setting of address compare registers b7 b0 Debug control register 0 (Address 6616) Detect enable bit 1 : Detection enabled. 11 Debug control register 1 (Address 6716) Address compare register access enable bit (Note 1) 1 : Enabled. Clear the interrupt disable flag (I) to “0” (Note 2). Setting of address compare registers b23 b 0 Detection starts. Notes 1: Be sure to set this bit to “1” immediately before reading from or writing to the address compare registers 0, 1. Then, be sure to clear this bit to “0” immediately after this reading or writing. 2: This processing is unnecessary when no maskable interrupt is used. Address compare register 0 (Addresses 6A16 to 6816) Address compare register 1 (Addresses 6D16 to 6B16) The address to be detected is set here. Fig. 17.3.1 Initial setting example for registers relevant to address matching detection mode 17-6 7905 Group User ’ s Manual Rev.1.0 DEBUG FUNCTION 17.3 Address matching detection mode 17.3.2 Operations in address matching detection mode ➀ Setting the detect enable bit to “1” initiate to compare the contents of PG and PC with one of the contents of the following registers. This comparison is performed at each op-code fetch: • W hen the address matching detection 0 is selected, the contents of the address compare register 0 are used for the above comparison. • W hen the address matching detection 1 is selected, the contents of the address compare register 1 are used for the above comparison. • W hen the address matching detection 2 is selected, the contents of the address compare register 0 or 1 are used for the above comparison. ➁ When the address which matches with the above register’s contents is detected, an address matching detection interrupt request occurs, and then, this request will be accepted. ➂ P erform the necessary processing with an address matching detection interrupt routine. ➃ The contents of PG, PC, and PS at acceptance of the address matching detection interrupt request are saved onto the stack area. Therefore, be sure to rewrite the above contents of PG and PC to a certain return address, and return to the address by using the R TI i nstruction. When an address matching detection interrupt request has been accepted, the interrupt disable flag (I) is set to “ 1 ” ; the processor interrupt priority level (IPL) does not change. Figures 17.3.2 and 17.3.3 show the examples of the ROM correct processing using the address matching detection mode. 7905 Group User ’ s Manual Rev.1.0 17-7 DEBUG FUNCTION 17.3 Address matching detection mode s Address matching detection 0 or 1 selected Main routine Address matching detection interrupt routine The interrupt disable flag (I) is cleared to “0” (Note 1) TOP_BUG Defective or Former program Modified or Updated program TOP_RTN The contents of PG and PC saved onto the stack area (address TOP_BUG) are rewritten to address TOP_RTN (Note 2). STAB A, LG : 0h (Note 3) RTI TOP_BUG : The start address of defective or former program. →This address is to be set in the address compare register 0 or 1, in advance. TOP_RTN : The address next to the defective or former program. Notes 1: When an address matching detection interrupt request has been accepted, the interrupt disable flag (I) is set to “1.” If another interrupt requests is required to be accepted under the same conditions as those of the defective or former program, be sure to clear the interrupt disable flag (I) to “0” at the start of an address matching detection interrupt routine. 2: Each status of PG, PC, and PS immediately before acceptance of an address matching detection interrupt request is saved onto the stack area. (The contents of PG, PC, and PS are saved onto the stack area in this order.) Refer to section “6.7 Sequence from acceptance of interrupt request until execution of interrupt routine.” 3: Make sure that this instruction is executed in the absolute long addressing mode. The above is just an example. In an actual programming, be sure to refer to the format of the assembler description to be used. Fig. 17.3.2 Example of ROM correct processing using address matching detection mode (1) 17-8 7905 Group User ’ s Manual Rev.1.0 DEBUG FUNCTION 17.3 Address matching detection mode s Address matching detection 2 selected Main routine Address matching detection interrupt routine The interrupt disable flag (I) is cleared to “0” (Note 1) TOP_BUG1 Defective or Former program ➀ Address-matchingdetection 2 decision bit? 0 Modified or Updated program ➀ 1 TOP_RTN1 Modified or Updated program ➁ TOP_BUG2 The contents of PG and PC saved onto the stack area (address TOP_BUG1) are rewritten to address TOP_RTN1 (Note 2). Defective or Former program ➁ STAB A, LG : 0h (Note 3) The contents of PG and PC saved onto the stack area (address TOP_BUG2) are rewritten to address TOP_RTN2 (Note 2). TOP_RTN2 RTI TOP_BUG1 : The start address of defective or former program ➀. →This address is to be set in the address compare register 0, in advance. TOP_RTN1 : The address next to the defective or former program ➀. TOP_BUG2 : The start address of defective or former program ➁. →This address is to be set in the address compare register 1, in advance. TOP_RTN2 : The address next to the defective or former program ➁. Notes 1: When an address matching detection interrupt request has been accepted, the interrupt disable flag (I) is set to “1.” If another interrupt requests is required to be accepted under the same conditions as those of the defective or former program, be sure to clear the interrupt disable flag (I) to “0” at the start of an address matching detection interrupt routine. 2: Each status of PG, PC, and PS immediately before acceptance of an address matching detection interrupt request is saved onto the stack area. (The contents of PG, PC, and PS are saved onto the stack area in this order.) Refer to section “6.7 Sequence from acceptance of interrupt request until execution of interrupt routine.” 3: Make sure that this instruction is executed in the absolute long addressing mode. The above is just an example. In an actual programming, be sure to refer to the format of the assembler description to be used. Fig. 17.3.3 Example of ROM correct processing using address matching detection mode (2) 7905 Group User ’ s Manual Rev.1.0 17-9 DEBUG FUNCTION 17.4 Out-of-address-area detection mode 17.4 Out-of-address-area detection mode When the contents of PG and PC go out of the range of the specified area, an address matching detection interrupt request occurs. 17.4.1 Setting procedure for out-of-address-area detection mode Figure 17.4.1 shows an initial setting example for registers relevant to the out-of-address-area detection mode. Disables interrupts. The interrupt disable flag (I) is set to “1.” Selection of detect condition b7 b0 b7 b0 0 Selection of out-of-address-area detection Detect enable bit 0 : Detection disabled. Debug control register 1 (Address 6716) Address compare register access enable bit (Note 1) 0 : Disabled. 0 0 0 0 1 0 1 Debug control register 0 (Address 6616) Set the detect enable bit to “1.” Processing for setting of address compare registers b7 b0 b7 b0 1 Debug control register 0 (Address 6616) Detect enable bit 1 : Detection enabled. 11 Debug control register 1 (Address 6716) Address compare register access enable bit (Note 1) 1 : Enabled. Clear the interrupt disable flag (I) to “0” (Note 2). Setting of address compare registers b23 b 0 Address compare register 0 (Addresses 6A16 to 6816) The start address of the programming area is set here. b23 b 0 Detection starts. Notes 1: Be sure to set this bit to “1” immediately before reading from or writing to the address compare registers 0, 1. Then, be sure to clear this bit to “0” immediately after this reading or writing. 2: This processing is unnecessary when no maskable interrupt is used. Address compare register 1 (Addresses 6D16 to 6B16) The last address of the programming area is set here. Fig. 17.4.1 Initial setting example for registers relevant to out-of-address-area detection mode 17-10 7905 Group User ’ s Manual Rev.1.0 DEBUG FUNCTION 17.4 Out-of-address-area detection mode 17.4.2 Operations in out-of-address-area detection mode ➀ S etting the detect enable bit to “ 1 ” i nitiate to compare the contents of PG and PC with the contents of the address compare registers 0 and 1. ➁ W hen an address less than the contents of the address compare registers 0 or larger than the one of the address compare register 1 is detected, an address matching detection interrupt request occurs, and then, this request will be accepted. ➂ P erform the necessary processing with an address matching detection interrupt routine. ➃ The contents of PG, PC, and PS at acceptance of the address matching detection interrupt request are saved onto the stack area. Therefore, be sure to rewrite the above contents of PG and PC to a certain return address, and return there by using the R TI i nstruction. When an address matching detection interrupt request has been accepted, the interrupt disable flag (I) is set to “ 1 ” ; the processor interrupt priority level (IPL) does not change. By setting the start address of the programming area into the address compare register 0 and the last address of the programming area into the address compare register 1, a program runaway (in other words, fetching op codes from the area out of the programming area) can be detected. If any program runaway is detected and reset of the microcomputer is required, be sure to write “1” into the software reset bit (bit 6 at address 5E 16) within an address matching detection interrupt routine. Figure 17.4.2 shows an example of program runaway detection using the out-of-address-area detection mode. 00000016 Access to the area out of the programming area Address matching detection interrupt routine TOP PRG Programming area END PRG Access to the area out of the programming area Software reset bit ← 1 (Note) (bit 6 at address 5E16) The microcomputer is reset RTI FFFFFF16 TOP_PRG : Start address of programming area → This address is to be set into the address compare register 0, in advance. END_PRG : Last address of programming area → This address is to be set into the address compare register 1, in advance. Note: A program runaway may affect the contents of the data bank register (DT), the direct page registers (DPRi) etc. Therefore, the contents of these registers must be rewritten in order to write “1” to the software reset bit with an addressing mode using DT, DPRi, etc. Fig. 17.4.2 Example of program runaway detection using out-of-address-area detection mode 7905 Group User ’ s Manual Rev.1.0 17-11 DEBUG FUNCTION [Precautions for debug function] [Precautions for debug function] 1. The debug function cannot be evaluated by a debugger. Therefore, do not use a debugger when using the debug function. 2. When returning from an address matching detection interrupt routine, be sure to rewrite the saved contents of PG and PC to a certain return address, and then return there by using the RTI instruction. However, this is unnecessary processing when the software reset is performed within an address matching detection interrupt routine for program runaway detection, etc. 3. Be sure to set the start address of an instruction into the address compare register 0 or 1. 17-12 7905 Group User ’ s Manual Rev.1.0 CHAPTER 18 APPLICATIONS 18.1 Application example of A-D converter APPLICATIONS 18.1 Application example of A-D converter A certain application example is described below. This application described here is just an example. Therefore, b efore actual using it, be sure to properly modify it according to the user’s system and sufficiently evaluate it. 18.1 Application example of A-D converter 18.1.1 Application example of A-D converter, using single sweep mode with pins AN 0 t o AN 11 Figures 18.1.1 to 18.1.3 show an application example of the A-D converter, using the single sweep mode with pins AN 0 t o AN 11. For details, refer to the following specifications: ➀ ➁ ➂ ➃ F or pins AN0 t o AN7, the single sweep mode is used. F or pins AN 8 t o AN 11, the one-shot mode is used. 1 0-bit resolution mode N o A-D conversion interrupt 18-2 7905 Group User’s Manual Rev.1.0 APPLICATIONS 18.1 Application example of A-D converter Setting of A-D conversion start bit to “0.” b7 b0 Setting of pins AN0 to AN7 to single sweep mode b7 b0 0 A-D control register 0 (Address 1E16) A-D conversion halts. 00 1 0✕✕✕ A-D control register 0 (Address 1E16) Single sweep mode A-D conversion start bit 0 : A-D conversion halts. Selection of comparator function b7 A-D conversion frequency (φAD) See Table 12.2.1. select bit 0 Comparator function select register 0 0 0 0 0 0 0 0 0 (Address DC16) AN0 AN1 AN2 0 : Comparator function is not selected. AN3 AN4 AN5 AN6 AN7 b0 b7 b0 00 1011 A-D control register 1 (Address 1F16) A-D sweep pin select bits b1 b0 1 1 : AN0 to AN7 (8 pins) Resolution select bit 1 : 10-bit resolution mode A-D conversion frequency (φAD) select bit 1 See Table 12.2.1. VREF connection select bit 0 : Pin VREF is connected. b7 b0 b7 b0 00000000 Comparator function select register 1 (Address DD16) AN8 AN9 0 : Comparator function is not selected. AN10 AN11 00 000✕✕✕ A-D control register 2 (Address DB16) Analog input pin select bits 1 b3 b2 b1 b0 0 ✕ ✕ ✕: Pins AN0 to AN7 are selected. ✕: It may be either “0” or “1.” Port P7 direction register, Port P8 direction register b7 b0 00000000 Port P7 direction register (Address 1116) Interrupt disabled, no interrupt requested b7 b0 0000 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 b7 b0 A-D conversion interrupt control register (Address 7016) Interrupt disabled No interrupt requested Clear the bits, corresponding to the selected analog input pins, to “0.” Setting of A-D conversion start bit to “1.” b7 b0 0000 Port P8 direction register (Address 1416) 1 A-D control register 0 (Address 1E16) A-D conversion starts. AN8 AN9 AN10 AN11 Clear the bits, corresponding to the selected analog input pins, to “0.” Trigger generated, A-D conversion started 0: During A-D conversion. A-D conversion interrupt request bit = “1” ? 1: A-D conversion, using single sweep mode with pins AN0 to AN7, is completed. Continued on Figure 18.1.2. Fig. 18.1.1 Application example of A-D converter, using single sweep mode with pins AN0 to AN11 (1) 7905 Group User’s Manual Rev.1.0 18-3 APPLICATIONS 18.1 Application example of A-D converter Continued from preceding Figure 18.1.1. Setting of pin AN9 to one-shot mode (Note) b7 b0 00001001 A-D control register 2 (Address DB16) Analog input pin select bits 1 b3 b2 b1 b0 1 0 0 1: Pin AN9 is selected. Setting of pin AN8 to one-shot mode b7 b0 0 0 0 0 ✕✕ ✕ A-D control register 0 (Address 1E16) One-shot mode A-D conversion start bit 0 : A-D conversion halts. A-D conversion frequency (φAD) select bit 0 See Table 12.2.1. Interrupt disabled, no interrupt requested b7 b0 0000 A-D conversion interrupt control register (Address 7016) Interrupt disabled No interrupt requested b7 b0 00 10✕✕ A-D control register 1 (Address 1F16) Resolution select bit 1 : 10-bit resolution mode A-D conversion frequency (φAD) select bit 1 See Table 12.2.1. VREF connection select bit 0 : Pin VREF is connected. Setting of A-D conversion start bit to “1.” b7 b0 1 A-D control register 0 (Address 1E16) A-D conversion starts. Trigger generated, A-D conversion started b7 b0 00001000 A-D control register 2 (Address DB16) Analog input pin select bits 1 b3 b2 b1 b0 0: During A-D conversion. 1 0 0 0: Pin AN8 is selected. ✕: It may be either “0” or “1.” A-D conversion interrupt request bit = “1” ? 1: A-D conversion, using one-shot mode with pin AN9, is completed. Interrupt disabled, no interrupt requested b7 b0 0000 A-D conversion interrupt control register (Address 7016) Interrupt disabled No interrupt requested Setting of pin AN10 to one-shot mode (Note) b7 b0 00001010 A-D control register 2 (Address DB16) Analog input pin select bits 1 b3 b2 b1 b0 Setting of A-D conversion start bit to “1.” b7 b0 1 A-D control register 0 (Address 1E16) A-D conversion starts. 1 0 1 0: Pin AN10 is selected. Interrupt disabled, no interrupt requested b7 b0 Trigger generated, A-D conversion started 0000 A-D conversion interrupt control register (Address 7016) Interrupt disabled No interrupt requested 0: During A-D conversion. A-D conversion interrupt request bit = “1” ? 1: A-D conversion, using one-shot mode with pin AN8, is completed. Setting of A-D conversion start bit to “1.” b7 b0 1 A-D control register 0 (Address 1E16) A-D conversion starts. Trigger generated, A-D conversion started 0: During A-D conversion. A-D conversion interrupt request bit = “1” ? 1: A-D conversion, using one-shot mode with pin AN10, is completed. Continued on Figure 18.1.3. Fig. 18.1.2 Application example of A-D converter, using single sweep mode with pins AN0 to AN11 (2) 18-4 7905 Group User ’ s Manual Rev.1.0 APPLICATIONS 18.1 Application example of A-D converter Continued from preceding Figure 18.1.2. Setting of pin AN11 to one-shot mode (Note) b7 b0 00001011 A-D control register 2 (Address DB16) Analog input pin select bits 1 b3 b2 b1 b0 1 0 1 1: Pin AN11 is selected. Interrupt disabled, no interrupt requested b7 b0 0000 A-D conversion interrupt control register (Address 7016) Interrupt disabled No interrupt requested 1 Setting of A-D conversion start bit to “1.” b7 b0 1 A-D control register 0 (Address 1E16) A-D conversion starts. Trigger generated, A-D conversion started 0: During A-D conversion. A-D conversion interrupt request bit = “1” ? 1: A-D conversion, using one-shot mode with pin AN11, is completed. A-D conversion with pins AN0 to AN11 is completed. Fig. 18.1.3 Application example of A-D converter, using single sweep mode with pins AN0 to AN11 (3) 7905 Group User ’ s Manual Rev.1.0 18-5 APPLICATIONS 18.1 Application example of A-D converter MEMORANDUM 18-6 7905 Group User ’ s Manual Rev.1.0 CHAPTER 19 FLASH MEMORY VERSION 19.1 Overview 19.2 Flash memory CPU reprogramming mode [Precautions for flash memory CPU reprogramming mode] 19.3 Flash memory serial I/O mode [Precautions for flash memory serial I/O mode] 19.4 Flash memory parallel I/O mode [Precautions for flash memory parallel I/O mode] F LASH MEMORY VERSION 19.1 Overview 19.1 Overview The flash memory version is provided with the same function as that of the mask ROM version except that the former includes the flash memory. Note that, however, part of the SFR area of the flash memory version differs from that of the mask ROM version. (Refer to section “19.1.1 Memory assignment.” ) Also, the stop mode terminate operation of the flash memory version differs from that of the mask ROM version. (Refer to section “ 19.1.2 Single-chip mode.”) In the flash memory version, its internal flash memory can be handled in the following three reprogramming modes: flash memory CPU reprogramming mode, flash memory serial I/O mode, and flash memory parallel I/O mode. Table 19.1.1 lists the performance overview of the flash memory version. (For the items not listed in Table 19.1.1, see Table 1.1.1.) Table 19.1.1 Performance overview of flash memory version Item Power source voltage Programming/Erase voltage Flash memory reprogramming modes Performance 5 V ± 0.5 V 5 V ± 0.5 V Flash memory CPU reprogramming mode, Flash memory serial I/O mode, Flash memory parallel I/O mode Programming CPU reprogramming mode, Programmed in a unit of word Flash memory serial I/O mode Flash memory Parallel I/O mode Programmed in a unit of byte Erase method Block erase or Total erase Maximum number of reprograms (programming 100 and erasure) For the flash memory version, in addition to the same single-chip mode as that of the mask ROM version, any of the operating modes listed in Table 19.1.2 can further be selected by the voltage levels applied to pins MD1 and MD0. Table 19.1.3 also lists the overview of flash memory reprogramming modes. Note: D o not switch the voltages applied to pins MD0 and MD1 while the microcomputer is active. Table 19.1.2 Operating mode selection according to voltages applied to pins MD0 and MD1 MD1 VSS VSS VCC VCC MD0 VSS VCC VSS VCC Operating modes Single-chip mode – (Note 1) Boot mode (Note 2) Flash memory parallel I/O mode (Note 3) Notes 1: Do not select. 2: Refer to section “19.1.3 Boot mode.” 3: Refer to section “19.4 Flash memory parallel I/O mode.” 19-2 7905 Group User’s Manual Rev.1.0 F LASH MEMORY VERSION 19.1 Overview Table 19.1.3 Overview of flash memory reprogramming modes Flash memory Flash memory CPU Flash memory serial I/O mode Flash memory parallel I/O mode reprogramming mode reprogramming mode Functional overview User ROM area is reprogrammed User ROM area is reprogram- Boot ROM area and User ROM by the CPU executing software med by using a dedicated serial area are reprogrammed by using commands. Reprogrammable User ROM area area Operating mode Single-chip mode, available Boot mode ROM programmer (Unnecessary) available programmer. User ROM area Boot mode Serial programmer (Note) a dedicated parallel programmer. User ROM area, Boot ROM area Flash memory parallel I/O mode Parallel programmer (Note) Note: For details of the serial and parallel programmers, please visit MITSUBISHI TOOL Homepage (http:/ /www.tool-spt.maec.co.jp/index_e.htm). 7905 Group User’s Manual Rev.1.0 19-3 F LASH MEMORY VERSION 19.1 Overview 19.1.1 Memory assignment Figure 19.1.1 shows the memory assignment of the M37905F8. 016 FF16 10016 3FF16 40016 M37905F8 SFR area Unused area Internal RAM area (3 Kbytes) FFF16 100016 Bank 016 Internal flash memory area (User ROM area) (60 Kbytes) FFFF16 Fig. 19.1.1 Memory assignment of M37905F8 19-4 7905 Group User’s Manual Rev.1.0 F LASH MEMORY VERSION 19.1 Overview In addition to the internal flash memory area (in other words, user ROM area) shown in Figure 19.1.1, the flash memory version has the boot ROM area of 8 Kbytes. Figure 19.1.2 shows the memory assignment of the internal flash memory. The user ROM area is divided into several blocks. The user ROM area is reprogrammed in the flash memory CPU reprogramming mode, serial I/O mode, and parallel I/O mode. The boot ROM area is assigned at addresses, overlapping with the user ROM area, however, the boot ROM area exists in the defferent memory; the boot ROM area can be reprogrammed only in the flash memory parallel I/O mode. (Refer to section “19.4 Flash memory parallel I/O mode.”). When being reset with pin MD1 tied to Vcc level and pin MD0 to Vss level, the software in the boot ROM area is executed after reset. (Refer to section “19.1.3 Boot mode.”) When pin MD1 = Vss level, however, the contents of the boot ROM area cannot be read out. User ROM area 100016 E00016 Boot ROM area (In boot mode) (In flash memory parallel I/O mode) 016 8 Kbytes FFFF16 1FFF16 28 Kbytes 7FFF16 800016 16 Kbytes BFFF16 C00016 8 Kbytes DFFF16 E00016 8 Kbytes (Note) FFFF16 M37905F8 Note: Addresses FF9016 to FF9F16 are reserved for serial and parallel programmers. Be sure not to use this area. Fig. 19.1.2 Memory assignment of internal flash memory 7905 Group User ’ s Manual Rev.1.0 19-5 F LASH MEMORY VERSION 19.1 Overview 19.1.2 Single-chip mode When being reset with both of pins MD1 and MD0 tied to Vss level, the microcomputer enters the singlechip mode. In the single-chip mode, the software in the user ROM area is executed after reset. The difference between the flash memory version and the mask ROM version is as follows: q S top mode terminate operation (1) Stop mode terminate operation Figure 19.1.3 shows stop mode terminate sequence owing to an interrupt request occurrence in the flash memory version. (Refer from section “ Stop mode ”.) In the flash memory version, when the watchdog timer is not used for termination of the stop mode, an interrupt request is accepted after a maximum of 10 µs has elapsed since the interrupt request occurred. 19-6 7905 Group User ’ s Manual Rev.1.0 F LASH MEMORY VERSION 19.1 Overview s When using the watchdog timer Stop mode fXIN fPLL (Note) φ1 φBIU Interrupt request to be used for stop mode termination (Interrupt request bit) FFF16 Value of watchdog timer 7FF16 fXi ✕ 2048 counts CPU Operating Internal peripheral device Operating Stopped Stopped Stopped Operating Operate Operate q STP q Interrupt request to be used for q Watchdog timer's MSB = “0” instruction termination occurs. (However, watchdog timer interrupt is executed. q Oscillation stars. request dose not occur.) (When an external clock is input q Each supply of φCPU, φBIU starts. from pin XIN, clock input starts.) q Interrupt request which was used for q PLL frequency multiplier starts its termination is accepted. operation. q Watchdog timer starts counting. Note: This applies when the PLL circuit operation enable bit (bit 1 at address BC16) = “1.” fXi : fX16, fX32, fX64, fX128 There are clocks selected by the watchdog timer clock source bits at STP termination (bits 6, 7 at address 6116) s When not using the watchdog timer Stop mode fXIN φ1 φBIU Interrupt request to be used for stop mode termination (Interrupt request bit) Value of the watchdog timer 10µs (Max.) FFF16 7FF16 CPU Operating Internal peripheral device Operating Stopped Stopped Stopped Operating Operating Operating q STP q Interrupt request q Each supply of φCPU, φBIU starts. instruction to be used for q Interrupt request which was used is executed. termination occurs. for termination is accepted. q Clock input from pin XIN starts. q Watchdog timer starts counting. Fig. 19.1.3 Stop mode terminate sequence owing to interrupt request occurrence 7905 Group User ’ s Manual Rev.1.0 19-7 F LASH MEMORY VERSION 19.1 Overview 19.1.3 Boot mode When being reset with pin MD1 tied to Vcc level and pin MD0 to Vss level, the flash memory version enters the boot mode. In the boot mode, the software in the boot ROM area is executed after reset. In the boot mode, either the boot ROM area or the user ROM area can be selected with the user ROM area select bit (bit 5 at address 9E 16). The boot ROM area is located at addresses E000 16 to FFFF 16 in the boot mode. A reprogramming control firmware used in the flash memory serial I/O mode has been stored in the boot ROM area on shipment. (Refer to section “19.3 Flash memory serial I/O mode.”) Therefore, when being reset in the boot mode, the flash memory version enters the flash memory serial I/O mode, allowing the user ROM area to be reprogrammed with a dedicated serial programmer. Also the boot ROM area can be reprogrammed in the flash memory parallel I/O mode. If an appropriate reprogramming control software using the CPU reprogramming mode has been stored in the boot ROM area, reprogramming suitable for the user ’ s system is enabled. Note that if the boot ROM area has been reprogrammed in the flash memory parallel I/O mode, the flash memory serial I/O mode cannot be used. 19-8 7905 Group User ’ s Manual Rev.1.0 F LASH MEMORY VERSION 19.2 Flash memory CPU reprogramming mode 19.2 Flash memory CPU reprogramming mode In this mode, the user ROM area can be reprogrammed by the central processing unit (CPU) executing software commands. Therefore, this mode allows the user to reprogram the contents of the user ROM area with the microcomputer mounted on the final printed circuit board, without using any ROM programmer. Be sure to store the reprogramming control software into the user ROM area or the boot ROM area in advance. In the flash memory CPU reprogramming mode, however, an opcode cannot be fetched for the internal flash memory. Accordingly, be sure to transfer the reprogramming control software to an area other than the internal flash memory area (e.g. the internal RAM area), and then execute the software in this area. The flash memory CPU reprogramming mode is available in any of the single-chip and boot modes. The software commands listed in Table 19.2.1 can be used in the flash memory CPU reprogramming mode. For details of each command, refer to section “ 19.2.4 Software commands.” Note that commands and data must be read from and written into even-numbered addresses within the user ROM area, 16 bits at a time. At writing of software command codes, the high-order 8 bits (D 8 t o D 15) are ignored. (Except for the write data at the 2nd bus cycle of the programming command code.) Table 19.2.1 Software commands 1st bus cycle Software commands Read Array Read Status Register Clear Status Register Programming Block Erase Erase All Blocks SRD : Status register data (D0 to D7) WA : Write address (A7 to A0 to be incremented by 2 from “0016” to “FE16”) WD : Write data (16 bits) BA ✕ : The highest address of a block (Note that A0 = 0.) : Arbitrary even-numbered address in user ROM area (A0 = 0) Mode Write Write Write Write Write Write Address ✕ ✕ ✕ ✕ ✕ ✕ Data (D0 to D7) 2nd bus cycle Mode — Read — Write Write Write Address — ✕ — WA BA ✕ Data — SRD — WD D0 16 2016 FF16 7016 5016 4016 2016 2016 7905 Group User’s Manual Rev.1.0 19-9 F LASH MEMORY VERSION 19.2 Flash memory CPU reprogramming mode 19.2.1 Flash memory control register Figure 19.2.1 shows the structure of the flash memory control register. b7 b6 b5 b4 b3 b2 b1 b0 Flash memory control register (Address 9E16) Bit 0 Bit name RY/BY status bit Function 0 : BUSY (Automatic programming or erase operation is active.) 1 : READY (Automatic programming or erase operation has been completed.) At reset 1 R/W RO 1 2 3 CPU reprogramming mode select bit 0 : Flash memory CPU reprogramming mode is invalid. 1 : Flash memory CPU reprogramming mode is valid. The value is “0” at reading. Flash memory reset bit (Note 3) Writing “1” into this bit discontinues the access to the internal flash memory. This causes the built-in flash memory circuit being reset. 0 0 0 RW (Notes 1, 2) — RW (Note 4) — RW (Note 2) — 4 5 7, 6 The value is “0” at reading. 0 : Access to boot ROM area User ROM area select bit (Valid in boot mode) (Note 5) 1 : Access to user ROM area The value is “0” at reading. 0 0 0 Notes 1: In order to set this bit to “1,” write “0” followed with “1” successively; while in order to clear this bit “0,” write “0.” 2: Writing to this bit must be performed in an area other than the internal flash memory. 3: T his bit is valid when the CPU reprogramming mode select bit (bit 1) = “1”: on the other hand, when the CPU reprogramming mode select bit = “0,” be sure to fix this bit to “0.” Rewriting of this bit must be performed with the CPU reprogramming mode select bit = “1.” 4: After writing of “1” to this bit, be sure to confirm the RY/BY status bit (bit 0) becomes “1”; and then, write “0” to this bit. 5: When MD1 = Vss level, this bit is invalid. (It may be either “0” or “1.”) Fig. 19.2.1 Structure of flash memory control register (1) RY/BY status bit (bit 0) This bit is used to indicate the operating status of the sequencer. This bit is “0” during the automatic programming or erase operation is active and becomes “1” upon completion of them. This bit also changes during the execution of the programming, block erase, or erase all blocks command, but does not change owing to the execution of another command. (2) CPU reprogramming mode select bit (bit 1) Setting this bit to “1” allows the microcomputer to enter the flash memory CPU reprogramming mode to accept commands. In order to set this bit to “1,” write “1” followed with “0” successively; while to clear this bit to “0,” write “0.” Since the microcomputer enters the flash memory CPU reprogramming mode after setting this bit to “1,” opcodes cannot be fetched for the internal flash memory. Accordingly, be sure to execute the instruction to be used for writing to this bit in an area other than the internal flash memory area (e.g. the internal RAM area). When executing commands of the flash memory CPU reprogramming mode in the boot mode, be sure to set the user ROM area select bit (bit 5) to “1.” 19-10 7905 Group User’s Manual Rev.1.0 F LASH MEMORY VERSION 19.2 Flash memory CPU reprogramming mode (3) Flash memory reset bit (bit 3) Writing “1” to this bit discontinues the access to the user ROM area and causes the built-in flash memory control circuit to be reset. After this reset, the microcomputer enters the read array mode to set the RY/BY status bit (bit 0) to “1”. When this flash memory control circuit is reset with the flash memory reset bit during programming (automatic programming) or erase (automatic erase) operation, that programming or erase operation is discontinued to invalidate the data in the working block. After writing of “1” to this bit, be sure to confirm the RY/BY status bit (bit 0) becomes “1”; and then, write “0” to this bit. (4) User ROM area select bit (bit 5) This bit is used to select either the boot ROM area or the user ROM area in the boot mode. In order to access the boot ROM area (read out), clear this bit to “0.” On the other hand, in order to access the user ROM area (reading out, programming, or erase), set it to “1.” Instructions for writing into this bit must be executed in an area other than the internal flash memory (e.g. the internal RAM area). Note that when MD1 = Vss level, the user ROM area is accessed (being read out) regardless of the contents of this bit. 7905 Group User’s Manual Rev.1.0 19-11 F LASH MEMORY VERSION 19.2 Flash memory CPU reprogramming mode 19.2.2 Status register The programming and erase operations for the internal flash memory are controlled by the sequencer in the internal flash memory. The status register indicates the completion states (normal or abnormal) of the programming and erase operations. For details of abnormal endings (errors), refer to section “19.2.5 Full status check.” Table 19.2.2 lists the bit definition of the status register. The contents of the status register can be read out by the read status register command. (Refer to section “19.2.4 Software commands.” ) Table 19.2.2 Bit definition of status register Symbol (Data bus) Status — — — — Programming Status Erase Status — — — — — — Definition “0” — — — — Error Error — — “1” SR.0 (D0) SR.1 (D1) SR.2 (D2) SR.3 (D3) SR.4 (D4) SR.5 (D5) SR.6 (D6) SR.7 (D7) Terminated normally. Terminated normally. — — Data bus: Indicates the data bus to be read out when the read status register command has been executed. (1) Programming status bit (SR.4) This bit is set to “1” if a programming error has occurred during the automatic programming (the programming) operation and cleared to “0” by executing the clear status register command. This bit is also cleared to “0” at reset. (2) Erase status bit (SR.5) This bit is set to “1” if an erase error has occurred during the automatic erase (the block erase or erase all unlocked blocks) operation and cleared to “0” by executing the clear status register command. This bit is also cleared to “0” at reset. 19-12 7905 Group User’s Manual Rev.1.0 F LASH MEMORY VERSION 19.2 Flash memory CPU reprogramming mode 19.2.3 Setting and Terminate procedure for flash memory CPU reprogramming mode Figure 19.2.2 shows the setting and terminate procedures for the flash memory CPU reprogramming mode. In the flash memory CPU reprogramming mode, opcodes cannot be fetched for the internal flash memory. Therefore, be sure to transfer the reprogramming control software to an area other than the internal flash memory and then execute the software in that area. Moreover, in order to prevent any interrupt occurrence during the flash memory CPU reprogramming mode, before selecting this mode, be sure to set the interrupt disable flag (I) to “1” or set the interrupt priority level to “000 2” (interrupts disabled). Also, we recommend to connect pins P4OUT CUT a nd P6OUTCUT w ith V CC v ia resistors, respectively. Even in the flash memory CPU reprogramming mode, periodically writing to the watchdog timer is required in order to prevent the watchdog timer interrupt occurrence. At the same time, it is necessary to write to the watchdog timer just before executing the programming, block erase, or erase all blocks command in order to prevent the watchdog timer interrupt occurrence during the automatic programming and erase operation. An interrupt, hardware reset, or software reset, generated in the flash memory CPU reprogramming mode, makes program runaway. If a program runaway has occurred, be sure to push the microcomputer into the power-on reset state. When an interrupt or reset is generated during the programming or erase operation, the contents of the corresponding block becomes invalidated. Reprogramming control software Single-chip mode, or Boot mode User ROM area select bit ← “1” (Only in the boot mode) Internal ROM bus cycle select bit ← “0” (bit 7 at address 5F16) CPU reprogramming mode select bit ← “0” CPU reprogramming mode select bit ← “1” Interrupt disable flag (I) = “1” or Interrupt priority level of each interrupt = “0002” Software command is executed. The reprogramming control software for the flash memory CPU reprogramming mode is transferred to an area other than the internal flash memory. Read array command is executed, or Flash memory reset bit ← “1” Flash memory reset bit ← “0” (Notes 1, 2) Jump to the control software transferred in the above procedure (The subsequent.procedures will be executed by the reprogramming control software transferred in the above procedure.) CPU reprogramming mode select bit ← “0” User ROM area select bit ← “0” (Only in the boot mode ) (Note 3) Jump to an arbitrary address in the internal flash memory area. Notes 1: Before termination of the flash memory CPU reprogramming mode, be sure to execute the read array . command or flash memory reset 2: After writing of “1” to the flash memory reset bit, be sure to confirm the RY/BY status bit (bit 0 at address 9E16) becomes “1”; and then, write “0” to this bit. 3: When the flash memory CPU reprogramming mode has been terminated with the user ROM area select bit (bit 5 at address 9E16) = “1,” the access to the user ROM area is selected. Fig. 19.2.2 Setting and Terminate procedures for flash memory CPU reprogramming mode 7905 Group User’s Manual Rev.1.0 19-13 F LASH MEMORY VERSION 19.2 Flash memory CPU reprogramming mode 19.2.4 Software commands Software commands are described below. Software commands and data must be read from and written into even-numbered addresses in the user ROM area, 16 bits at a time. At writing of a command code, the high-order 8 bits (D 8 to D15) are ignored. (1) Read array command Writing command code “FF16” at the 1st bus cycle pushes the microcomputer into the read array mode. When an address to be read is input at the next and the following bus cycles, the contents at the specified address are output to the data bus (D 0 t o D 15), 16 bits at a time. The read array mode is maintained until another software command is written. (2) Read status register command Writing command code “ 70 16” a t the 1st bus cycle outputs the contents of the status register to the data bus (D 0 t o D 7) by a read at the 2nd bus cycle. (See Table 19.2.2.) (3) Clear status register command Writing command code “5016” at the 1st bus cycle clears two bits (SR.4 and SR.5) of the status register to “ 0. ” ( See Table 19.2.2.) (4) Programming This command executes programming, one word at a time. Write command code “ 40 16” a t the 1st bus cycle and then write data at the 2nd bus cycle, 16 bits at a time. After writing of one word has been completed, the automatic programming (programming and verification of data) operation is initiated. During the automatic programming operation, be sure not to access the flash memory or not to execute the next command. The completion of the automatic programming can be recognized by the RY/BY status bit (bit 0 at address 9E 16). After the automatic programming operation has been completed, the result of it can be recognized by reading out the status register. (Refer to section “19.2.5 Full status check.”) Figure 19.2.3 shows the programming operation flowchart. Note that, for the areas having already been programmed, be sure to program after an erase (block erase) operation. If the programming command is executed for the areas having already been programmed, no programming error will occur, but the contents of the areas become undefined. Start Command code “4016” is written. Data is written to an arbitrary write address. RY/BY status bit = “1”? (bit 0 at address 9E16) NO YES Full status check ••• See Figure 19.2.6. Programming operation is completed. Fig. 19.2.3 Programming operation flowchart 19-14 7905 Group User ’ s Manual Rev.1.0 F LASH MEMORY VERSION 19.2 Flash memory CPU reprogramming mode (5) Block erase command Writing of command code “2016” at the 1st bus cycle and “D016” to the highest address (here, A 0 = 0 ) of the block to be erased at the 2nd bus cycle initiate the automatic erase (erase and erase-verify) operation for the specified block. During the automatic erase operation, be sure not to access the flash memory or not to execute the next command. The completion of the automatic erase operation can be recognized by the RY/BY status bit (bit 0 at address 9E 16). After the automatic erase operation is completed, the result of it can be recognized by reading out the status register. (Refer to section “19.2.5 Full status check. ”) Figure 19.2.4 shows the block erase operation flowchart. (6) Erase-all-blocks command Writing of command code “2016” at the 1st bus cycle and “ 20 16” a t the 2nd bus cycle initiate the automatic erase (erase and erase-verify) operation for all the blocks. During the automatic erase operation, be sure not to access the flash memory or not to execute the next command. The completion of the automatic erase operation can be recognized by the RY/BY status bit (bit 0 at address 9E 16). After the automatic erase operation is completed, the result of it can be recognized by reading out the status register. (Refer to section “19.2.5 Full status check. ”) Figure 19.2.5 shows the erase-all-blocks operation flowchart. Start Command code “2016” is written. “D016” is written to the highest address of the block. RY/BY status bit = “1”? (bit 0 at address 9E16) NO YES Full status check ••• See Figure 19.2.6. Block erase operation is completed. Fig. 19.2.4 Block erase operation flowchart Start Command code “20 16” is written. “20 16” is written. RY/BY status bit = “1”? (bit 0 at address 9E16) NO YES Full status check ••• See Figure 19.2.6. Erase-all-blocks operation is completed. Fig. 19.2.5 Erase-all-blocks operation flowchart 7905 Group User ’ s Manual Rev.1.0 19-15 F LASH MEMORY VERSION 19.2 Flash memory CPU reprogramming mode 19.2.5. Full status check If an error has occurred, bits SR.4 and SR.5 of the status register are set to “ 1 ” u pon completion of the programming or erase operation. Therefore, the result of the programming or erase operation can be recognized by checking these status (in other words, full status check). Table 19.2.3 lists the errors and the states of bits SR.4 and SR.5, and Figure 19.2.6 shows the full status check flowchart and the action to be taken if any error has occurred. Table 19.2.3 Errors and States of bits SR.3 to SR.5 Status register Error SR.4 SR.5 1 1 Error occurrence conditions Command sequen- • Commands are not correctly written. ce error • Data other than “D016” and “FF16” is written at the 2nd bus cycle of the block erase command (Note). • Data other than“2016” and “FF 16” is written at the 2nd bus cycle of the erase-all-blocks command (Note). 1 0 0 1 Erase error • A lthough the block erase or erase-all-blocks command is executed, these blocks are not correctly erased. Programming error • Although the programming command is executed, programming is not correctly performed. Notes: When “FF16” is written at the 2nd bus cycle of any of these commands, the microcomputer enters the read array mode. Simultaneously with this, the command code written at the 1st bus cycle is cancelled. Read status register SR.4 = 1 and SR.5 = 1 ? NO SR.5 = 0? YES Command sequence • • • • ➀ Execute the clear status command to clear SR.4 and SR.5 to “0.” error ➁ Execute the correct command again. Note: If the same error occurs, however, the block cannot be used. NO YES SR.4 = 0? NO YES Completed. Erase error •••• ➀ Execute the clear status command to clear SR.5 to “0.” ➁ Execute the block erase or erase-all-unlocked-blocks command again. Note: If the same error occurs, however, the block cannot be used. Programming error • • • • ➀ Execute the clear status command to clear SR.4 to “0.” ➁ Execute the programming command again. Note: If the same error occurs, however, the block cannot be used. Note: Under the condition that any of SR.4 and SR.5 = “1,” none of the programming, block erase, erase-all-blocks commands can be accepted. To execute any of these commands, in advance, execute the clear status register command. Fig. 19.2.6 Full status check flowchart and actions to be taken if any error has ocurred 19-16 7905 Group User ’ s Manual Rev.1.0 F LASH MEMORY VERSION 19.2 Flash memory CPU reprogramming mode 19.2.6 Electrical characteristics (1) M37905F8CFP DC Electrical Characteristics (VCC = 5 V ± 0.5 V, Ta = 0 to 60 °C, f(fsys) = 20 MHz) Limits Parameter Symbol Min. Typ. ICC1 VCC power source current (at read) 10 ICC2 VCC power source current (at write) ICC3 VCC power source current (at programming) ICC4 VCC power source current (at erasing) AC Electrical Characteristics (VCC = 5 V ± 0.5 V, Ta = 0 to 60 °C, f(fsys) = 20 MHz) Limits Parameter Min. Typ. 4 256 bytes programming time 0.6 Block erase time Erase all blocks time 0.6 ✕ n n = Number of blocks to be erased For the limits of parameters other than the above, refer to section “Appendix 9. M37905M4C-XXXFP electrical characteristics.” Max. 30 30 40 40 Unit mA mA mA mA Max. 40 8 8✕n Unit ms s s 7905 Group User ’ s Manual Rev.1.0 19-17 F LASH MEMORY VERSION [Precautions for flash memory CPU reprogramming mode] [Precautions for flash memory CPU reprogramming mode] 1. In the flash memory CPU reprogramming mode, an opcode cannot be fetched for the internal flash memory. Accordingly, be sure to transfer the reprogramming control software to an area other than the internal flash memory area, and then execute the software in this area. (See Figure 19.2.2.) Also, take consideration for instruction description (such as specified addresses, addressing modes) in the reprogramming control software since this software is to be executed in an area other than the internal flash memory area. 2. In order to prevent any interrupt occurrence during the flash memory CPU reprogramming mode, before selecting this mode, be sure to set the interrupt disable flag (I) to “1” or set the interrupt priority level to “0002” (interrupts disabled). Also, we recommend to connect pins P4OUTCUT and P6OUTCUT with VCC via resistors, respectively. Even in the flash memory CPU reprogramming mode, periodically writing to the watchdog timer is required. Also, an interrupt, hardware reset, or software reset, generated in the CPU reprogramming mode, makes program runaway. If a program runaway has occurred, be sure to push the microcomputer into the power-on reset state. 3. Commands and data must be read from and written into even-numbered addresses in the user ROM area, 16 bits at a time. 4. Be sure not to execute the STP instruction in the CPU reprogramming mode. 5. In order to reset the internal flash memory control circuit by using the flash memory reset bit (bit 3 at address 9E16), be sure to confirm the RY/BY status bit (bit 0 at address 9E16) becomes “1” after writing of “1” to this bit; and then, write “0” to the flash memory reset bit. 6. Addresses FF9016 to FF9F16 (the user ROM area) are reserved for serial and parallel programmers. Be sure not to use this area. 19-18 7905 Group User ’ s Manual Rev.1.0 F LASH MEMORY VERSION 19.3 Flash memory serial I/O mode 19.3 Flash memory serial I/O mode In the flash memory serial I/O mode, by using a dedicated serial programmer, the contents of the user ROM area can be reprogrammed with the microcomputer mounted on the final printed circuit board. About the serial programmer concerned, consult its manufacturer, and for more information on using it, refer to the user’s manual of the serial programmer. Note that if the boot ROM area has been reprogrammed in the flash memory parallel I/O mode, the flash memory serial I/O mode cannot be used. (Refer to section “ 19.4 Flash memory parallel I/O mode.” ) Addresses FF9016 to FF9F16 (the user ROM area) are reserved for serial or parallel programmers. Therefore, be sure not to use to this area. 19.3.1. Pin description Table 19.3.1 lists the pin description in the flash memory serial I/O mode, and each of Figures 19.3.1 and 19.3.2 shows the pin configuration in this mode. 7905 Group User’s Manual Rev.1.0 19-19 F LASH MEMORY VERSION 19.3 Flash memory serial I/O mode Table 19.3.1 Pin description in flash memory serial I/O mode Pin VCC VSS MD0 MD1 RESET XIN XOUT VCONT AVCC AVSS VREF P10 to P17 P27 P24 P25 P26 P40 to P47 P51 to P53, P55 to P57 P60 to P67 P70 to P77 P80 to P83 P4OUTCUT P6OUTCUT Input port P6 Input port P7 Input port P8 P4OUTCUT input P6OUTCUT input Input Input Input Input Input The P4OUTCUT pin. (Not used in this mode.) Recommended to be connected with VCC via a resistor. The P6OUTCUT pin. (Not used in this mode.) Recommended to be connected with VCC via a resistor. Notes 1: When there is a possibility that the user reset signal becomes “L” level in the flash memory serial I/O mode, be sure to cut off the current flow between the user reset signal and pin RESET by using a jumper switch, etc. (Refer to section “19.3.2 Examples of handling control pins in flash memory serial I/O mode.”) 2: F or pins not used in the flash memory serial I/O mode, properly connect to somewhere in the user system. For pins not used in the user system, handle them with reference to section “5.3 Examples of handling unused pins.” For pins used in the flash memory serial I/O mode, handle them with reference to section “19.3.2 Examples of handling control pins in flash memory serial I/O mode.” SCLK input SDA I/O BUSY output Input port P4 Input port P5 Input I/O The input pin for a serial clock. The I/O pin for serial data. This pin must be connected with VCC via a resistor (about 1 kΩ). Output The BUSY signal output pin. Input Input port pins. (Not used in this mode.) Input Reference voltage input Input port P1 Input Input Input MD0 MD1 Reset input Clock input Clock output Filter circuit connection Analog supply input Input Input Input Name Power supply input Input/Output Functions Supply VCC level voltage to pin Vcc. Supply VSS level voltage to pin Vss. Connect this pin to V SS. Connect this pin to V SS via a resistor (about 10 kΩ to 100 kΩ). The reset input pin (Note 1). Input Connect a ceramic resonator or quartz-crystal oscillator between Output X IN and X OUT pins. When using an external clock, the clcok source must be input to X IN pin and X OUT pin must be left open. — The VCONT pin. (Not used in this mode.) Connect this pin to VCC. Connect this pin to VSS. The VREF pin. (Not used in this mode.) Input port pins. (Not used in this mode.) P2 0 t o P2 3, Input port P2 19-20 7905 Group User’s Manual Rev.1.0 F LASH MEMORY VERSION 19.3 Flash memory serial I/O mode VCC P83/AN11 /TXD2 P82/AN10/RXD2 P81/AN9/CTS2/CLK2 P80/AN8/CTS2/RTS2/DA1 P77/AN7/DA0 P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 P67/TA3 IN/RTP13 P66/TA3 OUT/RTP12 P65/TA2 IN/U/RTP11 P64/TA2 OUT/V/RTP10 P63/TA1 IN/W/RTP03 P62/TA1 OUT/U/RTP02 P61/TA0 IN/V/RTP01 P60/TA0 OUT/W/RTP00 P57/INT7/TB2IN/IDU (Note 1) P56/INT6/TB1IN/IDV P55/INT5/TB0IN/IDW P6OUTCUT/INT4 (Note 3) MD0 RESET RESET XIN (Note 2) XOUT VCONT Vss P53/INT3/RTPTRG0 P52/INT2/RTPTRG1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Vss AVss VREF AVcc Vcc P10/CTS0/RTS0 P11/CTS0/CLK0 P12/RXD0 P13/TXD0 P14/CTS1/RTS1 P15/CTS1/CLK1 P16/RXD1 P17/TXD1 P20/TA4 OUT P21/TA4 IN P22/TA9 OUT P23/TA9 IN P24(/TB0IN) P25(/TB1IN) P26(/TB2IN) P27 MD1 P40/TA5 OUT/RTP20 P41/TA5 IN/RTP21 P42/TA6 OUT/RTP22 P43/TA6 IN/RTP23 P44/TA7 OUT/RTP30 P45/TA7 IN/RTP31 P46/TA8 OUT/RTP32 P47/TA8 IN/RTP33 P4OUTCUT/INT0 P51/INT1 SCLK SDA BUSY MD1 (Note 1) (Note 3) VSS Notes 1: Allocation of pins TB0IN to TB2IN can be switched by software. 2: Connected to the oscillation circuit. 3: Recommended to be connected with VCC via a resistor. : Connected to a serial programmer. Outline 64P4B Fig. 19.3.1 Pin connection in flash memory serial I/O mode (Outline: 64P4B) 7905 Group User’s Manual Rev.1.0 19-21 F LASH MEMORY VERSION 19.3 Flash memory serial I/O mode 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 (Note 1) (Note 3) P73/AN3 P72/AN2 P71/AN1 P70/AN0 P67/TA3 IN/RTP13 P66/TA3 OUT/RTP12 P65/TA2 IN/U/RTP11 P64/TA2 OUT/V/RTP10 P63/TA1 IN/W/RTP03 P62/TA1 OUT/U/RTP02 P61/TA0 IN/V/RTP01 P60/TA0 OUT/W/RTP00 P57/INT7/TB2IN/IDU P56/INT6/TB1IN/IDV P55/INT5/TB0IN/IDW P6OUTCUT/INT4 P74/AN4 P75/AN5 P76/AN6 P77/AN7/DA0 P80/AN8/CTS2/RTS2/DA1 P81/AN9/CTS2/CLK2 P82/AN10/RxD2 P83/AN11 /TxD2 Vss AVss VREF AVcc Vcc P10/CTS0/RTS0 P11/CTS0/CLK0 P12/RxD0 VSS VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P13/TxD0 P14/CTS1/RTS1 P15/CTS1/CLK1 P16/RxD1 P17/TxD1 P20/TA4 OUT P21/TA4 IN P22/TA9 OUT P23/TA9 IN P24(/TB0IN) P25(/TB1IN) P26(/TB2IN) P27 MD1 P40/TA5 OUT/RTP20 P41/TA5 IN/RTP21 SCLK SDA BUSY MD1 (Note 1) MD0 RESET XIN XOUT VCONT Vss P53/INT3/RTPTRG0 P52/INT2/RTPTRG1 P51/INT1 P4OUTCUT/INT0 (Note 3) (Note 2) RESET P47/TA8 IN/RTP33 P46/TA8 OUT/RTP32 P45/TA7 IN/RTP31 P44/TA7 OUT/RTP30 P43/TA6 IN/RTP23 P42/TA6 OUT/RTP22 Notes 1: Allocation of pins TB0IN to TB2IN can be switched by software. 2: Connected to the oscillation circuit. 3: Recommended to be connected with VCC via a resistor. : Connected to a serial programmer. Outline 64P6N-A Fig. 19.3.2 Pin connection in flash memory serial I/O mode (Outline: 64P6N-A) 19-22 7905 Group User ’ s Manual Rev.1.0 F LASH MEMORY VERSION 19.3 Flash memory serial I/O mode 19.3.2. Example of handling control pins in flash memory serial I/O mode Each of pins P2 4 t o P2 6, MD0, and MD1 serves as an input/output pin for a control signal in the flash memory serial I/O mode. Examples of handling these pins and pin RESET on the board are described below. (1) With control signals not affecting user system circuit When control signals in the flash memory serial I/O mode are not used in the user system circuit, or when these signals do not affect that circuit, the connections shown in Figure 19.3.3 are available. When pins P4OUTCUT and P6OUTCUT, however, are used in the user system circuit, see Figures 19.3.4 and 19.3.5. User system board Not used, or Connected to the user system circuit M37905F SDA(P25) BUSY(P 26) SCLK(P 24) ❈ VCC P4OUT CUT , P6OUT CUT MD0 Connected to serial programmer. User reset signal (Note) MD1 R ESET VSS XIN XOUT Note: When there is a possibility that the user reset signal becomes “L” level in the flash memory serial I/O mode, be sure to cut the current flow between the user reset pin and pin RESET by using a jumper switch, etc. ❈: The flash memory version of the 7905 Group Fig. 19.3.3 Example of handing control pins when control signals do not affect user system circuit 7905 Group User’s Manual Rev.1.0 19-23 F LASH MEMORY VERSION 19.3 Flash memory serial I/O mode (2) With control signals affecting user system circuit In the flash memory serial I/O mode, be sure to cut the current flow toward the user system circuit if control signals for this mode are also used in the user system circuit. Figure 19.3.4 shows an example of handling pins with jumper switches used, and Figure 19.3.5 shows an example of handling pins with analog switches used. User system board Connected to the user system circuit. M37905F ❈ SDA(P2 5 ) BUSY(P2 6 ) SCLK(P2 4 ) VCC MD0 VSS R ESET User reset signal (Note 2) Connected to serial programmer. P 4OUT CUT , P6OUT CUT (Note 1) MD1 XIN XOUT Note 1: Recommended to be connected with VCC via a resistor. 2: When there is a possibility that the user reset signal becomes “L” level in the flash memory serial I/O mode, be sure to cut the current flow between the user reset pin and pin RESET by using a jumper switch, etc. ❈: The flash memory version of the 7905 Group Fig. 19.3.4 Example of handling pins with jumper switches used User system board 74 HC4066 Connected to the user system circuit. M37905F❈ SDA(P2 5 ) BUSY(P2 6 ) SCLK(P2 4 ) VCC MD0 VSS Connected to serial programmer. P 4OUT CUT , P6OUT CUT (Note 1) MD1 R ESET User reset signal (Note 2) XIN XOUT Note 1: Recommended to be connected with VCC via a resistor. 2: When there is a possibility that the user reset signal becomes “L” level in the flash memory serial I/O mode, be sure to cut the current flow between the user reset pin and pin RESET by using a jumper switch, etc. ❈: The flash memory version of the 7905 Group Fig. 19.3.5 Example of handling pins with analog switches used 19-24 7905 Group User ’ s Manual Rev.1.0 F LASH MEMORY VERSION [Precautions for flash memory serial I/O mode] [Precautions for flash memory serial I/O mode] 1. If the boot ROM area has been reprogrammed in the flash memory parallel I/O mode, the flash memory serial I/O mode cannot be used. 2. In the flash memory serial I/O mode, we recommend to connect pins P4OUTCUT and P6OUTCUT with VCC via resistors, respectively. (Refer to section “19.3.2 Examples of handling control pins in flash memory serial I/O mode.”) 3. When there is a possibility that the user reset signal becomes “L” level in the flash memory serial I/O mode, be sure to cut the current flow between the user reset pin and pin RESET by using a jumper switch, etc. (Refer to section “19.3.2 Examples of handling control pins in flash memory serial I/O mode.”) 4. Addresses FF9016 to FF9F16 (the user ROM area) are reserved for serial and parallel programmers. Therefore, be sure not to use this area. 7905 Group User ’ s Manual Rev.1.0 19-25 F LASH MEMORY VERSION 19.4 Flash memory parallel I/O mode 19.4 Flash memory parallel I/O mode In the flash memory parallel I/O mode, the contents of the user ROM area and boot ROM area can be reprogrammed by using a dedicated parallel programmer. (See Figure 19.1.2.) About the parallel programmer concerned, consult its manufacturer, and for more information on using it, refer to the user’s manual of the parallel programmer. In the flash memory parallel I/O mode, the boot ROM area is assigned to addresses 0 16 t o 1FFFF 16 ( word addresses). Note that if the boot ROM area has been reprogrammed in the flash memory parallel I/O mode, the flash memory serial I/O mode cannot be used. (Refer to section “ 19.3 Flash memory serial I/O mode. ” ) Also, addresses FF9016 to FF9F16 (the user ROM area) are reserved for serial and parallel programmers. Therefore, besure not to use this area. 19-26 7905 Group User ’ s Manual Rev.1.0 F LASH MEMORY VERSION [Precautions for flash memory parallel I/O mode] [Precautions for flash memory parallel I/O mode] 1. If the boot ROM area has been reprogrammed in the flash memory parallel I/O mode, the flash memory serial I/O mode cannot be used. (Refer to section “19.3 Flash memory serial I/O mode.”) 2. Addresses FF9016 to FF9F16 (the user ROM area) are reserved for serial and parallel programmers. Be sure not to use this area. 7905 Group User ’ s Manual Rev.1.0 19-27 F LASH MEMORY VERSION [Precautions for flash memory parallel I/O mode] MEMORANDUM 19-28 7905 Group User ’ s Manual Rev.1.0 APPENDIX Appendix 1. Memory assignment in SFR area Appendix 2. Control registers Appendix 3. Package outline Appendix 4. E x a m p l e s o f h a n d l i n g unused pins Appendix 5. Hexadecimal instruction code table Appendix 6. Machine instructions Appendix 7. Countermeasure against noise Appendix 8. 7905 Group Q & A Appendix 9. M 37905M4C-XXXFP electrical characteristics Appendix 10. M 3 7 9 0 5 M 4 C - X X X F P standard characteristics Appendix 11. Memory assignment of 7905 Group APPENDIX Appendix 1. Memory assigment in SFR area Appendix 1. Memory assigment in SFR area s S FR area (Addresses 0 16 t o FF 16) qSFR area (Addresses 016 to FF16) Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : “0” immediately after reset. 1 : “1” immediately after reset. ? : Undefined immediately after reset. 0 1 ? 0 : Always “0” at reading. : Always “1” at reading. : Always undefined at reading. : “0” immediately after reset. Fix this bit to “0.” Address 016 116 216 316 416 516 616 716 816 916 A16 B16 C16 D16 E16 F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 1A16 1B16 1C16 1D16 1E16 1F16 Register name b7 Access characteristics b0 State immediately after reset b7 b0 Port P1 register Port P1 direction register Port P2 register Port P2 direction register Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P8 direction register (Note 1) (Note 1) (Note 2) RW (Note 2) RW RW (Note 2) RW (Note 2) RW RW RW RW RW RW RW RW RW RW (Note 2) (Note 2) (Note 2) (Note 2) ? ? ? ? ? ? RW 0 0 0 RW ? ? ? A-D control register 0 A-D control register 1 RW RW 0 0 0 0 0 0 ? ? ? ? ? 0016 ? ? 0016 ? ? ?? 0016 ?0 ? ? 0016 0016 ?0 ? ?0 ? ? ? ? ? ? ? ? ? 00 00 ? 0 ? 0 ? ? 0 0 0 0 0 0 ? 0 ? 1 ? 1 Notes 1: Do not read from and write to this register. 2: Do not write to this register. 20-2 7 905 Group User’s Manual Rev.1.0 APPENDIX Appendix 1. Memory assigment in SFR area Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : “0” immediately after reset. 1 : “1” immediately after reset. ? : Undefined immediately after reset. 0 1 ? 0 : Always “0” at reading. : Always “1” at reading. : Always undefined at reading. : “0” immediately after reset. Fix this bit to “0.” Address 2016 2116 2216 2316 2416 2516 2616 2716 2816 2916 2A16 2B16 2C16 2D16 2E16 2F16 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C16 3D16 3E16 3F16 Register name b7 Access characteristics b0 State immediately after reset b7 b0 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 UART0 transmit/receive mode register UART0 baud rate register (BRG0) UART0 transmit buffer register UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 baud rate register (BRG1) UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register RW RO RW RO (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) RW WO WO RO RO RO RW WO WO RO RO RO WO RW RW RO RW ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 00 0016 ? ? ? 01 00 ? 00 0016 ? ? ? 01 00 ? 00 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 ? WO RW RW RO RW 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 ? Note 3: The access characteristics at addresses 2016 to 2F16 vary according to the contents of the comparator function select register 0 (address DC16). (Refer to “CHAPTER 12. A-D CONVERTER.”) 7 905 Group User ’ s Manual Rev.1.0 20-3 APPENDIX Appendix 1. Memory assigment in SFR area Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : “0” immediately after reset. 1 : “1” immediately after reset. ? : Undefined immediately after reset. 0 1 ? 0 : Always “0” at reading. : Always “1” at reading. : Always undefined at reading. : “0” immediately after reset. Fix this bit to “0.” Address 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 4A16 4B16 4C16 4D16 4E16 4F16 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C16 5D16 5E16 5F16 Register name b7 Count start register 0 Count start register 1 One-shot start register 0 One-shot start register 1 Up-down register 0 Timer A clock division select register Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 Access characteristics b0 State immediately after reset b7 b0 RW RW RW WO (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) RW RW RW RW RW RW (Note 6) RW (Note 6) RW (Note 6) RW WO RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 ? ? ? 0 0 RW WO WO RW RW RW ? 0 0 0 0 ? ? 0 0 0 0 0016 00 00 00 00 00 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0016 0016 0016 0016 0016 00 00 00 01 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Notes 4: The access characteristics at addresses 4616 to 4F16 vary according to the timer A’s operating mode. (Refer to “CHAPTER 7. TIMER A.”) 5: The access characteristics at addresses 5016 to 5516 vary according to the timer B’s operating mode. (Refer to “CHAPTER 8. TIMER B.”) 6: The access characteristics for bit 5 at addresses 5B16 to 5D16 vary according to the timer B’s operating mode. (Refer to “CHAPTER 8. TIMER B.”) 20-4 7 905 Group User ’ s Manual Rev.1.0 APPENDIX Appendix 1. Memory assigment in SFR area Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : “0” immediately after reset. 1 : “1” immediately after reset. ? : Undefined immediately after reset. 0 1 ? 0 : Always “0” at reading. : Always “1” at reading. : Always undefined at reading. : “0” immediately after reset. Fix this bit to “0.” Address Register name b7 Access characteristics b0 b7 State immediately after reset b0 Watchdog timer register 6016 Watchdog timer frequency select register 6116 6216 Particular function select register 0 (Note 7) RW RW RW RW RW (Note 9) RW RW RW RW (Note 10) 0 0 0 6316 6416 6516 6616 6716 6816 6916 6A16 6B16 6C16 6D16 6E16 6F16 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C16 7D16 7E16 7F16 Particular function select register 1 Particular function select register 2 Debug control register 0 Debug control register 1 Address comparison register 0 Address comparison register 1 INT3 interrupt control register INT4 interrupt control register A-D conversion interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register (Note 12) RW RO RO RW RW RO RW RW (Note 13) RW (Note 13) RW (Note 13) RW (Note 13) RW (Note 13) RW (Note 13) RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 1 0 ? ? ? ? ? ? (Note 8) 0 0 ? 0000000 0 0 0 0 0 (Note 11) ? ? 0 (Note 11) 0 0 (Note 11) 0 0? 0000 ? ? ? ? ? ? 000000 000000 ?000 ? 0000 ? 0000 ? 0000 ? 0000 ? 0000 ? ? 0000 0000 ? 0000 ? 0000 ? 0000 ? 0000 ? 0000 ? 000000 000000 000000 Notes 7 : By writing dummy data to address 6016, a value of “FFF16” is set to the watchdog timer. The dummy data is not retained anywhere. 8 : A value of “FFF16” is set to the watchdog timer. (Refer to “CHAPTER 14. WATCHDOG TIMER.”) 9 : After writing “5516” to address 6216, each bit must be set. 10 : It is possible to read the bit state at reading. By writing “0” to this bit, this bit becomes “0.” But when writing “1” to this bit, this bit will not change. 11 : This bit becomes “0” at power-on reset. This bit retains the state immediately before reset in the case of hardware reset and software reset. 12 : Do not write to this register. 13 : When these registers are accessed, set the address comparison register access enable bit (bit 2 at address 6716) to “1.” (Refer to “CHAPTER 17. DEBUG FUNCTION.”) 7 905 Group User ’ s Manual Rev.1.0 20-5 APPENDIX Appendix 1. Memory assigment in SFR area Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : “0” immediately after reset. 1 : “1” immediately after reset. ? : Undefined immediately after reset. 0 1 ? 0 : Always “0” at reading. : Always “1” at reading. : Always undefined at reading. : “0” immediately after reset. Fix this bit to “0.” Address Register name b7 Access characteristics b0 State immediately after reset b7 b0 8016 8116 8216 8316 8416 8516 8616 8716 8816 8916 8A16 8B16 8C16 8D16 8E16 8F16 9016 9116 9216 9316 9416 9516 External interrupt input read-out register D-A control register 9616 9716 9816 D-A register 0 D-A register 1 9916 9A16 9B16 9C16 9D16 9E16 Flash memory control register (Note 15) 9F16 (Note 14) (Note 14) (Note 14) (Note 14) (Note 14) (Note 14) (Note 14) (Note 14) (Note 14) (Note 14) (Note 14) (Note 14) (Note 14) RO RW RW RW RW ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 ? 0016 0016 ? ? ? ? 00 ? 0 (Note 14) (Note 14) RW RW RW RO 0 0 0 0 0 1 Notes 14 : Do not write to this register. 15 : This register is assigned only to the flash memory version. (Refer to “CHAPTER 19. FLASH MEMORY VERSION.”) Nothing is assigned here in the mask ROM version. 20-6 7 905 Group User ’ s Manual Rev.1.0 APPENDIX Appendix 1. Memory assigment in SFR area Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : “0” immediately after reset. 1 : “1” immediately after reset. ? : Undefined immediately after reset. 0 1 ? 0 : Always “0” at reading. : Always “1” at reading. : Always undefined at reading. : “0” immediately after reset. Fix this bit to “0.” Address Register name b7 Access characteristics b0 State immediately after reset b7 b0 RW Pulse output control register A016 A116 Pulse output data register 0 RW A216 A316 Pulse output data register 1 RW A416 A516 Waveform output mode register RW A616 Dead-time timer WO A716 Three-phase output data register 0 RW A816 Three-phase output data register 1 RW A916 RW RO RO RO AA16 Position-data-retain function control register AB16 Serial I/O pin control register RW RW RW RW RW RW AC16 AD16 Port P2 pin function control register RW RW RW RW AE16 AF16 RW UART2 transmit/receive mode register B016 UART2 baud rate register (BRG2) WO B116 WO B216 UART2 transmit buffer register WO B316 B416 UART2 transmit/receive control register 0 RO RW RW RO B516 UART2 transmit/receive control register 1 RW RO RW B616 RO UART2 receive buffer register B716 RO B816 (Note 16) B916 BA16 (Note 16) BB16 (Note 16) Clock control register 0 BC16 RW RW RW RW (Note 17) RW RW (Note 16) BD16 BE16 (Note 16) BF16 (Note 16) ? 0 0 0 ? 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0016 ? 0016 ? 0016 ? 0016 ? 0016 0016 0 ? 00 ? ?? ? 0016 ? ? ? 01 00 ? 00 ? ? ? ? 10 ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 ? 1 1 1 Notes 16 : Do not write to this register. 17 : After reset, these bits are allowed to be changed only once. 7 905 Group User ’ s Manual Rev.1.0 20-7 APPENDIX Appendix 1. Memory assigment in SFR area Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : “0” immediately after reset. 1 : “1” immediately after reset. ? : Undefined immediately after reset. 0 1 ? 0 : Always “0” at reading. : Always “1” at reading. : Always undefined at reading. : “0” immediately after reset. Fix this bit to “0.” Address Register name b7 Access characteristics b0 State immediately after reset b7 b0 C016 C116 C216 C316 Up-down register 1 C416 C516 C616 Timer A5 register C716 C816 Timer A6 register C916 CA16 Timer A7 register CB16 CC16 Timer A8 register CD16 CE16 Timer A9 register CF16 D016 Timer A01 register D116 D216 Timer A11 register D316 D416 Timer A21 register D516 D616 Timer A5 mode register D716 Timer A6 mode register D816 Timer A7 mode register D916 Timer A8 mode register Timer A9 mode register DA16 DB16 A-D control register 2 DC16 Comparator function select register 0 DD16 Comparator function select register 1 DE16 Comparator result register 0 Comparator result register 1 DF16 ? ? ? ? WO RW (Note 18) (Note 18) (Note 18) (Note 18) (Note 18) (Note 18) (Note 18) (Note 18) (Note 18) (Note 18) WO WO WO WO WO WO RW RW RW RW RW RW RW RW RW RW 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0016 0016 0016 0016 0016 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 18: The access characteristics at addresses C616 to CF16 vary according to the timer A’s operating mode. (Refer to “CHAPTER 7. TIMER A.”) 20-8 7 905 Group User ’ s Manual Rev.1.0 APPENDIX Appendix 1. Memory assigment in SFR area Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : “0” immediately after reset. 1 : “1” immediately after reset. ? : Undefined immediately after reset. 0 1 ? 0 : Always “0” at reading. : Always “1” at reading. : Always undefined at reading. : “0” immediately after reset. Fix this bit to “0.” Address Register name b7 Access characteristics b0 State immediately after reset b7 b0 E016 A-D register 8 E116 E216 A-D register 9 E316 E416 A-D register 10 E516 E616 A-D register 11 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 UART2 transmit interrupt control register F216 UART2 receive interrupt control register F316 F416 Timer A5 interrupt control register F516 Timer A6 interrupt control register F616 F716 Timer A7 interrupt control register F816 Timer A8 interrupt control register F916 Timer A9 interrupt control register FA16 FB16 FC16 INT5 interrupt control register FD16 INT6 interrupt control register FE16 INT7 interrupt control register FF16 (Note 19) (Note 19) (Note 19) (Note 19) (Note 19) (Note 19) (Note 19) (Note 19) (Note 20) (Note 20) (Note 20) (Note 20) (Note 20) (Note 20) (Note 20) (Note 20) RW RW ? 0 0 0 0 0 0 0 0 0 0 0 0 0 ? 0 ? 0 ? 0 ? ? ? ? ? ? ? ? ? ? ? ? ? RW RW RW RW RW ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? 0 0 ? 0 0 ? 0 0 ? (Note 20) (Note 20) (Note 20) RW RW RW Notes 19: The access characteristics at addresses E016 to E716 vary according to the contents of the comparator function select register 1 (address DD16). (Refer to “CHAPTER 12. A-D CONVERTER.”) 20: Do not write to this register. 7 905 Group User ’ s Manual Rev.1.0 20-9 APPENDIX Appendix 2. Control registers Appendix 2. Control registers The control registers allocated in the SFR area are shown on the following pages. Below is the structure diagram for all registers. ✽3 ✽2 XXX register (address XX16) Bit 0 Bit name • • • select bit ✽1 b7 b6 b5 b4 b3 b2 b1 b0 ✽5 Function 0:… 1:… The value is “0” at reading. b2 b1 X0 At reset Undefined R/W WO ✽4 Reference 3-10 1 2 3 4 5 6 7 • • • select bit 00:… 01:… 10:… 11:… 0:… 1:… 0 0 0 0 0 Undefined 0 RW RW RO RW RW – – 3-11 • • • flag Fix this bit to “0.” This bit is invalid in … mode. Nothing is assigned. The value is “0” at reading. 2-6 ✽6 ✽1 Blank 0 1 ✕ ✽2 0 1 Undefined ✽3 RW RO WO : It is possible to read the bit state at reading. The written value becomes valid. : It is possible to read the bit state at reading. The written value becomes invalid. Accordingly, the written value may be “0” or “1.” : The written value becomes valid. It is impossible to read the bit state. The value is undefined at reading. However, when [“0” at reading”] is indicated in the “Function” or “Note” column, the bit is always “0” at reading. (See ✽5 above.) : It is impossible to read the bit state. The value is undefined at reading. However, when [“0” at reading”] is indicated in the “Function” or “Note” column, the bit is always “0” at reading. (See ✽6 above.) The written value becomes invalid. Accordingly, the written value may be “0” or “1.” : “0” immediately after reset. : “1” immediately after reset. : Undefined immediately after reset. : Set to “0” or “1” according to the usage. : Set to “0” at writing. : Set to “1” at writing. : Invalid depending on the mode or state. It may be “0” or “1.” : Nothing is assigned. — ✽4 Reference page for each bit. 20-10 7 905 Group User’s Manual Rev.1.0 APPENDIX Appendix 2. Control registers Port Pi register (i = 1, 2, 4 to 8) (Addresses 316, 616, A16, B16, E16, F16, 1216) Bit 0 1 2 3 4 5 6 7 Port pin Pi0 Port pin Pi1 Port pin Pi2 Port pin Pi3 Port pin Pi4 Port pin Pi5 Port pin Pi6 Port pin Pi7 Bit name Funtion Data is input from or output to a pin by reading from or writing to the corresponding bit. 0 : “L” level 1 : “H” level At reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W RW RW RW RW RW RW RW RW Reference 5-4 b7 b6 b5 b4 b3 b2 b1 b0 Notes 1: Nothing is assigned for bits 0 and 4 of the port P5 register. These bits are undefined at reading. 2: Nothing is assigned for bits 4 to 7 of the port P8 register. These bits are undefined at reading. Port Pi direction register (i = 1, 2, 4 to 8) (Addresses 516, 816, C16, D16, 1016, 1116, 1416) Bit 0 1 2 3 4 5 6 7 Bit name Port Pi0 direction bit Port Pi1 direction bit Port Pi2 direction bit Port Pi3 direction bit Port Pi4 direction bit Port Pi5 direction bit Port Pi6 direction bit Port Pi7 direction bit Function 0 : Input mode (The port functions as an input port.) 1 : Output mode (The port functions as an output port.) b7 b6 b5 b4 b3 b2 b1 b0 At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Reference Port P1 Port P2 Port P4 Port P5 6-17 8-7 9-11 9-22 10-13 5-7 7-9 5-7 7-9 7-9 8-7 11-18 5-3 Port P6 Port P7 Port P8 11-18 12-15 12-15 Notes 1: Nothing is assigned for bits 0 and 4 of the port P5 direction register. These bits are undefined at reading. 2: Nothing is assigned for bits 4 to 7 of the port P8 direction register. These bits are undefined at reading. 3: Any of bits 0 to 7 of the port P4 direction register becomes “0” by input of a falling edge to pin P4OUTCUT/INT0. (Refer to section “5.2.3 Pin P4OUTCUT/INT0.”) 4: Any of bits 0 to 7 of the port P6 direction register becomes “0” by input of a falling edge to pin P6OUTCUT/INT4. (Refer to section “5.2.4 Pin P6OUTCUT/INT4.”) 7 905 Group User ’ s Manual Rev.1.0 20-11 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 0 (Address 1E16) Bit 0 1 2 3 4 5 6 7 Fix this bit to “0.” A-D conversion start bit 0 : A-D conversion halts. 1 : A-D conversion starts. Bit name Analog input pin select bits 0 b2 b1 b0 0 Function At reset Undefined Undefined Undefined (Note 2) 0 0 0 0 0 RW RW RW RW (Note 3) RW R/W RW RW RW Reference 12-8 0 0 0 : AN0 is selected. (Valid in the one-shot and repeat 0 0 1 : AN1 is selected. 0 1 0 : AN2 is selected. modes.) (Note 1) 0 1 1 : AN3 is selected. 1 0 0 : AN4 is selected. 1 0 1 : AN5 is selected. 1 1 0 : AN6 is selected. 1 1 1 : AN7 is selected. b4 b3 A-D operation mode select bits 0 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 or 1 A-D conversion frequency ( φ AD) See Table 12.2.1. select bit 0 Notes 1: When using pins AN0 to AN7, be sure to fix bit 3 of the analog input pin select bits 1 (bits 3 to 0 at address DB16) to “0.” Setting bit 3 of the analog input pin select bits 1 to “1” invalidates the analog input pin select bits 0. Also, the analog input pin select bits 0 are invalid in the single sweep mode, repeat sweep mode 0 and repeat sweet mode 1. (Each may be either “0” or “1.”) 2: When using pin AN7, be sure that the D-A0 output enable bit (bit 0 at address 9616) = “0” (output disabled). 3: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. 4: Writing to each bit (except write of “0” to bit 6) of the A-D control register 0 must be performed while the A-D converter halts, regardless of the A-D operation mode. 20-12 7 905 Group User ’ s Manual Rev.1.0 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 1 (Address 1F16) Bit 0 Bit name A-D sweep pin select bits b1 b0 0 Function Single sweep mode/Repeat sweep mode 0 At reset 1 R/W RW Reference 12-8 12-9 1 (Valid in the single sweep mode, 0 0 : Pins AN0 and AN1 (2 pins) repeat sweep mode 0, and 0 1 : Pins AN0 to AN3 (4 pins) repeat sweep mode 1.) (Note 1) 1 0 : Pins AN0 to AN5 (6 pins) 1 1 : Pins AN0 to AN7 (8 pins) (Note 2) Repeat sweep mode 1 (Note 3) b1 b0 1 RW 0 0 : Pin AN0 (1 pin) 0 1 : Pins AN0 and AN1 (2 pins) 1 0 : Pins AN0 to AN2 (3 pins) 1 1 : Pins AN0 to AN3 (4 pins) 2 A-D operation mode select bit 1 0 : Repeat sweep mode 0 (Used in the repeat sweep mode 0 1 : Repeat sweep mode 1 and repeat sweep mode 1.)(Note 4) Resolution select bit 0 : 8-bit resolution mode 1 : 10-bit resolution mode 0 RW 3 4 5 6 7 0 0 0 RW RW RW RW – 12-9 16-7 A-D conversion frequency (φAD) select bit 1 See Table 12.2.1. Fix this bit to “0.” VREF connection select bit (Note 5) The value is “0” at reading. 0 : Pin VREF is connected. 1 : Pin VREF is disconnected. 0 0 Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either “0” or “1.”) 2: When using pin AN7, be sure that the D-A0 output enable bit (bit 0 at address 9616) = “0” (output disabled). 3: Be sure to select the frequently-used analog input pins in the repeat sweep mode 1. 4: Fix this bit to “0” in the one-shot mode, repeat mode, and single sweep mode. 5: When this bit is cleared from “1” to “0,” be sure to start the A-D conversion after an interval of 1 µs or more has elapsed. 6: Writing to each bit of the A-D control register 1 must be performed while the A-D converter halts, regardless of the A-D operation mode. b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 2 (Address DB16) Bit 0 1 2 3 7 to 4 Fix these bits to “0000.” Bit name Analog input pin select bits 1 (Note 1) b3 b2 b1 b0 0000 Function 0 X X X : Pins AN0 to AN7 are selected. 1 0 0 0 : Pin AN8 is selected. 1 0 0 1 : Pin AN9 is selected. 1 0 1 0 : Pin AN10 is selected. 1 0 1 1 : Pin AN11 is selected. 1 1 0 0 : Do not select. (Note 2) (Note 3) (Note 4) (Note 5) (Note 6) At reset 0 0 0 0 0 R/W RW RW RW RW RW Reference 12-8 1 1 1 1 : Do not select. X : They may be either “0” or “1.” Note 1: When using pins AN0 to AN7, regardless of the A-D operation mode, be sure to fix bit 3 to “0.” Also, pins AN8 to AN11 are used only in the one-shot mode and repeat mode. 2: Use bits 2 to 0 of A-D control register 0 (address 1E16) for selection of pins AN0 to AN7. 3: When using pin AN8, be sure that the D-A1 output enable bit (bit 1 at address 9616) = “0” (output disabled). Also, be sure not to use pin CTS2/RTS2. 4: When using pin AN9, be sure not to use pin CTS2/CLK2. 5: When using pin AN10, be sure not to use pin RXD2. 6: When using pin AN11, be sure not to use pin TXD2. 7: Writing to each bit of A-D control register 2 must be performed while the A-D conversion halts, regardless of the A-D operation mode. 7 905 Group User ’ s Manual Rev.1.0 ••• 20-13 APPENDIX Appendix 2. Control registers s When 8-bit resolution mode is selected A-D register 0 (Addresses 2116, 2016) A-D register 1 (Addresses 2316, 2216) A-D register 2 (Addresses 2516, 2416) A-D register 3 (Addresses 2716, 2616) A-D register 4 (Addresses 2916, 2816) A-D register 5 (Addresses 2B16, 2A16) A-D register 6 (Addresses 2D16, 2C16) A-D register 7 (Addresses 2F16, 2E16) Bit 7 to 0 Reads an A-D conversion result. A-D register 8 (Addresses E116, E016) A-D register 9 (Addresses E316, E216) A-D register 10 (Addresses E516, E416) A-D register 11 (Addresses E716, E616) (b15) b7 (b8) b0 b7 b0 Function At reset Undefined 0 R/W RO – Reference 12-10 15 to 8 The value is “0” at reading. s When 10-bit resolution mode is selected A-D register 0 (Addresses 2116, 2016) A-D register 1 (Addresses 2316, 2216) A-D register 2 (Addresses 2516, 2416) A-D register 3 (Addresses 2716, 2616) A-D register 4 (Addresses 2916, 2816) A-D register 5 (Addresses 2B16, 2A16) A-D register 6 (Addresses 2D16, 2C16) A-D register 7 (Addresses 2F16, 2E16) Bit 9 to 0 Reads an A-D conversion result. A-D register 8 (Addresses E116, E016) A-D register 9 (Addresses E316, E216) A-D register 10 (Addresses E516, E416) A-D register 11 (Addresses E716, E616) (b15) b7 (b8) b0 b7 b0 Function At reset Undefined 0 R/W RO – Reference 12-10 15 to 10 The value is “0” at reading. s When comparator function is selected A-D register 0 (Addresses 2116, 2016) A-D register 1 (Addresses 2316, 2216) A-D register 2 (Addresses 2516, 2416) A-D register 3 (Addresses 2716, 2616) A-D register 4 (Addresses 2916, 2816) A-D register 5 (Addresses 2B16, 2A16) A-D register 6 (Addresses 2D16, 2C16) A-D register 7 (Addresses 2F16, 2E16) Bit 7 to 0 15 to 8 A-D register 8 (Addresses E116, E016) A-D register 9 (Addresses E316, E216) A-D register 10 (Addresses E516, E416) A-D register 11 (Addresses E716, E616) (b15) b7 (b8) b0 b7 b0 Function Any value in the range from “0016” to “FF16” can be set. The set value is compared with the input voltage. The value is undefined at reading. The value is “0” at reading. At reset Undefined 0 R/W WO – Reference 12-10 Note: When the comparator function is selected, writing to and reading from the A-D register i must be performed while the A-D converter halts. 20-14 7 905 Group User ’ s Manual Rev.1.0 APPENDIX Appendix 2. Control registers UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) UART2 transmit/receive mode register (Address B016) Bit 0 Bit name Serial I/O mode select bits b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 Function 0 0 0 : Serial I/O is invalid. (P1 and P8 function as programmable I/O ports.) 0 0 1 : Clock synchronous serial I/O mode 010: Do not select. 011: 1 0 0 : UART mode (Transfer data length = 7 bits) 1 0 1 : UART mode (Transfer data length = 8 bits) 1 1 0 : UART mode (Transfer data length = 9 bits) 1 1 1 : Do not select. 0 : Internal clock 1 : External clock 0 : One stop bit 1 : Two stop bits 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode terminated (Invalid) 1 : Sleep mode selected At reset 0 R/W RW Reference 11-5 1 0 RW 2 Internal/External clock select bit Stop bit length select bit (Valid in UART mode) (Note) Odd/Even parity select bit (Valid in UART mode when parity enable bit = “1.”) (Note) Parity enable bit (Valid in UART mode) (Note) Sleep select bit (Valid in UART mode) (Note) 0 RW 3 4 5 0 0 0 RW RW RW 6 7 0 0 RW RW Note: Bits 4 to 6 are invalid in the clock synchronous serial I/O mode. (Each may be either “0” or “1.”) Additionally, fix bit 7 to “0.” UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) UART2 baud rate register (BRG2) (Address B116) Bit 7 to 0 Function b7 b0 At reset Undefined R/W WO Reference 11-14 Any value in the range from “0016” to “FF16” can be set. Assuming that the set value = n, BRGi divides the count source frequency by (n + 1). Note: Writing to this register must be performed while the transmission/reception halts. Use the MOVM (MOVMB) or STA (STAB, STAD) instruction for writing to this register. UART0 transmit buffer register (Addresses 3316, 3216) UART1 transmit buffer register (Addresses 3B16, 3A16)(b15) b7 UART2 transmit buffer register (Addresses B316, B216) Bit 8 to 0 Transmit data is set. Function (b8) b0 b7 b0 At reset Undefined Undefined R/W WO – Reference 11-11 15 to 9 Nothing is assigned. Note: Use the MOVM (MOVMB) or STA (STAB, STAD) instruction for writing to this register. 7 905 Group User ’ s Manual Rev.1.0 20-15 APPENDIX Appendix 2. Control registers UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) UART2 transmit/receive control register 0 (Address B416) Bit 0 1 2 3 CTS/RTS function select bit (Note 1) Transmit register empty flag Bit name BRG count source select bits b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 Function 0 0 : Clock f2 0 1 : Clock f16 1 0 : Clock f64 1 1 : Clock f512 0 : The CTS function is selected. 1 : The RTS function is selected. 0 : Data is present in the transmit register. (Transmission is in progress.) 1 : No data is present in the transmit register. (Transmission is completed.) 0 : The CTS/RTS function is enabled. 1 : The CTS/RTS function is disabled. At reset 0 0 0 1 R/W RW RW RW RO Reference 11-7 4 5 6 CTS/RTS enable bit 0 0 0 RW RW RW UARTi receive interrupt mode 0 : Reception interrupt 1 : Reception error interrupt select bit CLK polarity select bit 0 : At the falling edge of the transfer clock, transmit data is output; at the rising edge of the transfer (This bit is used in the clock clock, receive data is input. synchronous serial I/O mode.) When not in transferring, pin CLKi’s level is “H.” (Note 2) 1 : At the falling edge of the transfer clock, transmit data is output; at the falling edge of the transfer clock, receive data is input. When not in transferring, pin CLKi’s level is “L.” 0 : LSB (Least Significant Bit) first Transfer format select bit (This bit is used in the clock 1 : MSB (Most Significant Bit) first synchronous serial I/O mode.) (Note 2) 7 0 RW Notes 1: Valid when the CTS/RTS enable bit (bit 4) is “0” and CTSi/RTSi separate select bit (bit 0, 1 or 4 at address AC16) is “0.” 2: Fix these bits to “0” in the UART mode or when serial I/O is disabled. UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) UART2 transmit/receive control register 1 (Address B516) Bit 0 1 2 3 4 5 6 7 Bit name Transmit enable bit Transmit buffer empty flag Receive enable bit Receive complete flag Overrun error flag Framing error flag (Valid in UART mode) Parity error flag (Valid in UART mode) Error sum flag (Valid in UART mode) (Note) (Note) (Note) Function 0 : Transmission disabled 1 : Transmission enabled b7 b6 b5 b4 b3 b2 b1 b0 At reset 0 1 0 0 0 0 0 0 R/W RW RO RW RO RO RO RO RO Reference 11-9 0 : Data is present in the transmit buffer register. 1 : No data is present in the transmit buffer register. 0 : Reception disabled 1 : Reception enabled 0 : No data is present in the receive buffer register. 1 : Data is present in the receive buffer register. 0 : No overrun error 1 : Overrun error detected 0 : No framing error 1 : Framing error detected 0 : No parity error 1 : Parity error detected 0 : No error 1 : Error detected Note: Bits 5 to 7 are invalid in the clock synchronous serial I/O mode. 20-16 7 905 Group User ’ s Manual Rev.1.0 APPENDIX Appendix 2. Control registers UART0 receive buffer register (Addresses 3716, 3616) UART1 receive buffer register (Addresses 3F16, 3E16) (b15) b7 UART2 receive buffer register (Addresses B716, B616) Bit 8 to 0 Receive data is read out from here. Function (b8) b0 b7 b0 At reset Undefined 0 R/W RO – Reference 11-13 15 to 9 The value is “0” at reading. 7 905 Group User ’ s Manual Rev.1.0 20-17 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Count start register 0 (Address 4016) Bit 0 1 2 3 4 5 6 7 Bit name Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit 0 : Stop counting 1 : Start counting Function At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW 8-4 Reference 7-6 b7 b6 b5 b4 b3 b2 b1 b0 Count start register 1 (Address 4116) Bit 0 1 2 3 4 7 to 5 Bit name Timer A5 count start bit Timer A6 count start bit Timer A7 count start bit Timer A8 count start bit Timer A9 count start bit Nothing is assigned. 0 : Stop counting 1 : Start counting Function At reset 0 0 0 0 0 Undefined R/W RW RW RW RW RW – Reference 7-6 20-18 7 905 Group User ’ s Manual Rev.1.0 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 One-shot start register 0 (Address 4216) Bit 0 1 2 3 4 6, 5 7 Bit name Timer A0 one-shot start bit Timer A1 one-shot start bit Timer A2 one-shot start bit Timer A3 one-shot start bit Timer A4 one-shot start bit Nothing is assigned. Fix this bit to “0.” Function 0 At reset 0 0 The value is “0” at reading. 0 0 0 Undefined 0 R/W WO WO WO WO WO – RW Reference 7-33 1 : Start outputting one-shot pulse. (Valid when an internal trigger is selected.) b7 b6 b5 b4 b3 b2 b1 b0 One-shot start register 1 (Address 4316) Bit 0 1 2 3 4 6, 5 7 Bit name Timer A5 one-shot start bit Timer A6 one-shot start bit Timer A7 one-shot start bit Timer A8 one-shot start bit Timer A9 one-shot start bit Nothing is assigned. Fix this bit to “0.” Function 0 At reset 0 0 The value is “0” at reading. 0 0 0 Undefined 0 R/W WO WO WO WO WO – RW Reference 7-33 1 : Start outputting one-shot pulse. (Valid when an internal trigger is selected.) 7 905 Group User ’ s Manual Rev.1.0 20-19 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Up-down register 0 (Address 4416) Bit 0 1 2 3 4 5 6 7 Bit name Timer A0 up-down bit Timer A1 up-down bit Timer A2 up-down bit Timer A3 up-down bit Timer A4 up-down bit Timer A2 two-phase pulse signal 0 : Two-phase pulse signal processing function disabled 1 : Two-phase pulse signal processing function enabled processing select bit Timer A3 two-phase pulse signal When not using the two-phase pulse signal processing processing select bit function, clear the bit to “0.” Timer A4 two-phase pulse signal The value is “0” at reading. processing select bit 0 : Countdown 1 : Countup This function is valid when the contents of the updown register is selected as the up-down switching factor. Function At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW WO (Note) WO (Note) WO (Note) 7-26 Reference 7-24 Note: Use the MOVM (MOVMB) or STA(STAB, STAD) instruction for writing to bits 5 to 7. b7 b6 b5 b4 b3 b2 b1 b0 Up-down register 1 (Address C416) Bit 0 1 2 3 4 5 6 7 Bit name Timer A5 up-down bit Timer A6 up-down bit Timer A7 up-down bit Timer A8 up-down bit Timer A9 up-down bit Timer A7 two-phase pulse signal 0 : Two-phase pulse signal processing function disabled 1 : Two-phase pulse signal processing function enabled processing select bit Timer A8 two-phase pulse signal When not using the two-phase pulse signal processing processing select bit function, clear the bit to “0.” Timer A9 two-phase pulse signal The value is “0” at reading. processing select bit 0 : Countdown 1 : Countup This function is valid when the contents of the updown register is selected as the up-down switching factor. Function At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW WO (Note) WO (Note) WO (Note) 7-26 Reference 7-24 Note: Use the MOVM (MOVMB) or STA(STAB, STAD) instruction for writing to bits 5 to 7. 20-20 7 905 Group User ’ s Manual Rev.1.0 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Timer A clock division select register (Address 4516) Bit 0 1 7 to 2 The value is “0” at reading. Bit name Timer A clock division select bits See Table 7.2.3. Function At reset 0 0 0 R/W RW RW – Reference 7-5 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Timer A5 register (Addresses C716, C616) Timer A6 register (Addresses C916, C816) Timer A7 register (Addresses CB16, CA16) Timer A8 register (Addresses CD16, CC16) Timer A9 register (Addresses CF16, CE16) (b15) b7 (b8) b0 b7 b0 Bit Function At reset Undefined R/W RW Reference 7-4 15 to 0 These bits have different functions according to the operating mode. Note: Reading from or writing to this register must be performed in a unit of 16 bits. Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) Timer Ai mode register (i = 5 to 9) (Addresses D616 to DA16) Bit 0 1 2 3 4 5 6 7 Bit name Operating mode select bits b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 Function 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot pulse mode 1 1 : Pulse width modulation (PWM) mode. At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Reference 7-7 These bits have different functions according to the operating mode. 7 905 Group User ’ s Manual Rev.1.0 20-21 APPENDIX Appendix 2. Control registers s Timer mode Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Timer A5 register (Addresses C716, C616) Timer A6 register (Addresses C916, C816) Timer A7 register (Addresses CB16, CA16) Timer A8 register (Addresses CD16, CC16) Timer A9 register (Addresses CF16, CE16) (b15) b7 (b8) b0 b7 b0 Bit Function At reset R/W RW Reference 7-12 Undefined 15 to 0 Any value in the range from “000016” to “FFFF16” can be set. Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. Note: Reading from or writing to this register must be performed in a unit of 16 bits. Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) Timer Ai mode register (i = 5 to 9) (Addresses D616 to DA16) Bit 0 1 2 Pulse output function select bit Bit name Operating mode select bits b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 0 At reset 0 0 00 R/W RW RW RW Reference 7-12 9-12 9-23 10-15 7-16 Function 0 0 : Timer mode 0 : No pulse output (TAiOUT pin functions as a programmable I/O port pin.) 1 : Pulse output (TAiOUT pin functions as a pulse output pin.) b4 b3 0 3 Gate function select bits 00: 01: 10: 4 11: No gate function (TAiIN pin functions as a programmable I/O port pin.) Gate function (Counter is active only while TAiIN pin’s input signal is at “L” level.) Gate function (Counter is active only while TAiIN pin’s input signal is at “H” level.) 0 RW 7-15 0 RW 5 6 7 Fix this bit to “0” in timer mode. Count source select bits See Table 7.2.3. 0 0 0 RW RW RW 7-5 20-22 7 905 Group User ’ s Manual Rev.1.0 APPENDIX Appendix 2. Control registers s Event counter mode Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Timer A5 register (Addresses C716, C616) Timer A6 register (Addresses C916, C816) Timer A7 register (Addresses CB16, CA16) Timer A8 register (Addresses CD16, CC16) Timer A9 register (Addresses CF16, CE16) (b15) b7 (b8) b0 b7 b0 Bit Function At reset R/W RW Reference 7-20 15 to 0 Any value in the range from “000016” to “FFFF16” can be set. Undefined Assuming that the set value = n, the counter divides the count source frequency by (n + 1) during countdown, or by (FFFF16 – n + 1) during countup. When reading, the register indicates the counter value. Note: Reading from or writing to this register must be performed in a unit of 16 bits. Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) Timer Ai mode register (i = 5 to 9) (Addresses D616 to DA16) Bit 0 1 2 Pulse output function select bit Bit name Operating mode select bits b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 XX0 At reset 0 0 01 R/W RW RW RW 7-26 Reference 7-20 Function 0 1 : Event counter mode 0 : No pulse output (TAi OUT p in functions as a programmable I/O port pin.) 1 : Pulse output (TAiOUT pin functions as a pulse output pin.) 0 : Counts at falling edge of external signal 1 : Counts at rising edge of external signal 0 : Contents of up-down register 1 : Input signal to TAiOUT pin 0 3 4 5 6 7 Count polarity select bit Up-down switching factor select bit 0 0 0 0 0 RW RW RW RW RW 7-20 7-24 Fix this bit to “0” in event counter mode. These bits are invalid in event counter mode. X : It may be either “0” or “1.” 7 905 Group User ’ s Manual Rev.1.0 20-23 APPENDIX Appendix 2. Control registers s One-shot pulse mode Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Timer A5 register (Addresses C716, C616) Timer A6 register (Addresses C916, C816) Timer A7 register (Addresses CB16, CA16) Timer A8 register (Addresses CD16, CC16) Timer A9 register (Addresses CF16, CE16) (b15) b7 (b8) b0 b7 b0 Bit Function At reset R/W WO Reference 7-30 10-13 Undefined 15 to 0 Any value in the range from “000016” to “FFFF16” can be set. Assuming that the set value = n, the “H” level width of the one-shot pulse which is n output from the TAiOUT pin is expressed as follows : fi. fi: Frequency of count source Note: Use the MOVM or STA(STAD) instruction for writing to this register. Writing to this register must be performed in a unit of 16 bits. Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) Timer Ai mode register (i = 5 to 9) (Addresses D616 to DA16) Bit 0 1 2 3 4 5 6 7 Fix this bit to “1” in one-shot pulse mode. Trigger select bits b4 b3 b7 b6 b5 b4 b3 b2 b1 b0 0 110 At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW 7-5 7-33 Reference 7-30 10-13 Bit name Operating mode select bits b1 b0 Function 1 0 : One-shot pulse mode Writing “1” to one-shot start bit (TAiIN pin functions as a programmable I/O port pin.) 1 0 : Falling edge of TAiN pin’s input signal 1 1 : Rising edge of TAiIN pin’s input signal See Table 7.2.3. 00: 01: Fix this bit to “0” in one-shot pulse mode. Count source select bits 20-24 7 905 Group User’s Manual Rev.1.0 APPENDIX Appendix 2. Control registers s Pulse width modulation (PWM) mode Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Timer A5 register (Addresses C716, C616) Timer A6 register (Addresses C916, C816) Timer A7 register (Addresses CB16, CA16) Timer A8 register (Addresses CD16, CC16) Timer A9 register (Addresses CF16, CE16) (b15) b7 (b8) b0 b7 b0 Bit 15 to 0 Function At reset R/W WO Reference 7-39 Undefined Any value in the range from “000016” to “FFFE16” can be set. Assuming that the set value = n, the “H” level width of the PWM pulse which is output n from the TAiOUT pin is expressed as follows : fi (PWM pulse period = 216–1 ) fi fi: Frequency of count source Note: Use the MOVM or STA(STAD) instruction for writing to this register. Writing to this register must be performed in a unit of 16 bits. Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Timer A5 register (Addresses C716, C616) Timer A6 register (Addresses C916, C816) Timer A7 register (Addresses CB16, CA16) Timer A8 register (Addresses CD16, CC16) Timer A9 register (Addresses CF16, CE16) (b15) b7 (b8) b0 b7 b0 Bit 7 to 0 Function At reset R/W WO Reference 7-39 Undefined Any value in the range from “0016” to “FF16” can be set. Assuming that the set value = m, the period of the PWM pulse which is output from the TAiOUT pin is expressed as follows: (m + 1) (28 – 1) fi Undefined 15 to 8 Any value in the range from “0016” to “FF16” can be set. Assuming that the set value = n, the “H” level width of the PWM pulse which is output from the TAiOUT pin is expressed as follows: n(m + 1) fi fi: Frequency of count source Note: Use the MOVM or STA(STAD) instruction for writing to this register. Writing to this register must be performed in a unit of 16 bits. WO 7 905 Group User’s Manual Rev.1.0 20-25 APPENDIX Appendix 2. Control registers s Pulse width modulation (PWM) mode Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) Timer Ai mode register (i = 5 to 9) (Addresses D616 to DA16) b7 b6 b5 b4 b3 b2 b1 b0 111 Bit 0 1 2 3 4 5 6 7 16/8-bit PWM mode select bit Count source select bits Fix this bit to “1” in PWM mode. Trigger select bits b4 b3 Bit name Operating mode select bits b1 b0 Function 1 1 : PWM mode At reset 0 0 0 R/W RW RW RW RW RW RW RW RW Reference 7-40 9-12 9-23 00: 01: Writing “1” to count start bit (TAiIN pin functions as a programmable I/O port pin.) 1 0 : Falling edge of TAiIN pin’s input signal 1 1 : Rising edge of TAiIN pin’s input signal 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator 0 0 0 0 0 7-43 7-44 7-5 See Table 7.2.3. 20-26 7 905 Group User’s Manual Rev.1.0 APPENDIX Appendix 2. Control registers Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) Bit (b15) b7 (b8) b0 b7 b0 Function At reset Undefined R/W RW Reference 8-3 15 to 0 These bits have different functions according to the operating mode. Note: Reading from or writing to this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Bit 0 1 2 3 4 5 6 7 Note: Bit 5 is invalid in the timer and event counter modes; its value is undefined at reading. Bit name Operating mode select bits b1 b0 Function 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/Pulse width measurement mode 1 1 : Do not select. At reset 0 0 0 0 0 Undefined 0 0 R/W RW RW RW RW RW RO (Note) RW RW Reference 8-4 These bits have different functions according to the operating mode. 7 905 Group User’s Manual Rev.1.0 20-27 APPENDIX Appendix 2. Control registers s Timer mode Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) Bit (b15) b7 (b8) b0 b7 b0 Function At reset R/W RW Reference 8-9 15 to 0 Any value in the range from “000016” to “FFFF16” can be set. Undefined Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. Note: Reading from or writing to this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Bit 0 1 2 3 4 5 6 7 X : It may be either “0” or “1.” XXXX00 At reset 0 0 R/W RW RW RW RW RW RO RW RW 8-7 Reference 8-9 Bit name Operating mode select bits b1 b0 Function 0 0 : Timer mode These bits are invalid in timer mode. 0 0 0 This bit is invalid in timer mode; its value is undefined at reading. Count source select bits b7 b6 Undefined 0 0 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 20-28 7 905 Group User’s Manual Rev.1.0 APPENDIX Appendix 2. Control registers s Event counter mode Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) Bit (b15) b7 (b8) b0 b7 b0 Function At reset R/W RW Reference 8-14 15 to 0 Any value in the range from “000016” to “FFFF16” can be set. Undefined Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. Note: Reading from or writing to this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Bit 0 1 2 3 4 5 6 7 X : It may be either “0” or “1.” XXXX At reset 0 0 01 R/W RW RW RW RW RW RO RW RW Reference 8-14 Bit name Operating mode select bits b1 b0 Function 0 1 : Event counter mode b3 b2 Count polarity select bits 0 0 : Count at falling edge of external signal 0 1 : Count at rising edge of external signal 1 0 : Count at both falling and rising edges of external signal 1 1 : Do not select. (Note) 0 0 0 Undefined 0 0 This bit is invalid in event counter mode. This bit is invalid in event counter mode; its value is undefined at reading. These bits are invalid in event counter mode. Note: When the timer B2 clock source select bit (bit 6 at address 6316) = “1,” be sure to fix these bits to “012” (count at the rising edge of the external signal). 7 905 Group User’s Manual Rev.1.0 20-29 APPENDIX Appendix 2. Control registers s Pulse period/Pulse width measurement mode Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) Bit (b15) b7 (b8) b0 b7 b0 Function At reset Undefined R/W RO Reference 8-21 15 to 0 The measurement result of pulse period or pulse width is read out. Note: Reading from this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Bit 0 1 2 Measurement mode select bits b3 b2 10 At reset 0 0 R/W RW RW RW 8-23 Reference 8-21 Bit name Operating mode select bits b1 b0 Function 1 0 : Pulse period/Pulse width measurement mode 3 0 0 : Pulse period measurement (Interval between falling edges of measurement pulse) 0 1 : Pulse period measurement (Interval between rising edges of measurement pulse) 1 0 : Pulse width measurement (Interval from a falling edge to a rising edge, and from a rising edge to a falling edge of measurement pulse) 1 1 : Do not select. 0 : Counter clear type 1 : Free-run type 0 : No overflow 1 : Overflowed b7 b6 0 0 RW 4 5 6 7 Count-type select bit Timer Bi overflow flag (Note) Count source select bits 0 Undefined 0 0 RW RO RW RW 8-24 8-7 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 Note: The timer Bi overflow flag is cleared to “0” when a value is written to the timer Bi mode register with the count start bit = “1.” This flag cannot be set to “1” by software. 20-30 7 905 Group User’s Manual Rev.1.0 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Processor mode register 0 (Address 5E16) Bit 0 1 2 3 4 5 6 7 Software reset bit Fix this bit to “0.” Interrupt priority detection time select bits b5 b4 0 Function XX00 At reset 0 0 0 1 R/W RW RW RW RW RW RW WO RW 3-3 6-11 Reference 2-20 Bit name Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Do not select. 1 0 : Do not select. 1 1 : Do not select. Any of these bits may be either “0” or “1.” 0 0 : 7 cycles of fsys 0 1 : 4 cycles of fsys 1 0 : 2 cycles of fsys 1 1 : Do not select. The microcomputer is reset by writing “1” to this bit. The value is “0” at reading. 0 0 0 0 X : It may be either “0” or “1.” Processor mode register 1 (Address 5F16) Bit 0 1 6 to 2 7 Bit name This bit may be either “0” or “1.” Direct page register switch bit Fix these bits to “00000.” Internal ROM bus cycle select bit 0 : 3φ 1 : 2φ (Note 2) 0 : Only DPR0 is used. 1 : DPR0 through DPR3 are used. Function b7 b6 b5 b4 b3 b2 b1 b0 00000 At reset 1 0 0 0 X R/W RW RW (Note 1) RW RW 2-12 2-6 Reference X : It may be either “0” or “1.” Notes 1: After reset, this bit is allowed to be changed only once. (During the software execution, be sure not to change this bit’s content.) 2: To reprogram the internal flash memory by using the CPU reprogramming mode, clear this bit to “0.” (Refer to section “19.2 Flash memory CPU reprogramming mode.”) 7 905 Group User’s Manual Rev.1.0 20-31 APPENDIX Appendix 2. Control registers b7 b0 Watchdog timer register (Address 6016) Bit 7 to 0 Function At reset R/W — Reference 14-3 Initializes the watchdog timer. Undefined When dummy data has been written to this register, the watchdog timer’s value is initialized to “FFF16” (dummy data: 0016 to FF16). b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer frequency select register (Address 6116) Bit 0 5 to 1 6 7 Bit name Watchdog timer frequency select bit Nothing is assigned. 0 : Wf512 1 : Wf32 Function At reset 0 Undefined 0 0 R/W RW — RW RW 14-3 15-7 Reference 14-3 Watchdog timer clock source b7 b6 0 0 : fX32 select bits at STP termination 0 1 : fX16 1 0 : fX128 1 1 : fX64 20-32 7 905 Group User’s Manual Rev.1.0 APPENDIX Appendix 2. Control registers Particular function select register 0 (Address 6216) Bit 0 1 Bit name Function b7 b6 b5 b4 b3 b2 b1 b0 000000 At reset 0 0 R/W RW (Note) RW (Note) Reference 15-4 4-10 15-5 16-4 STP instruction invalidity select bit 0 : STP instruction is valid. 1 : STP instruction is invalid. External clcok input select bit 0 : Oscillation circuit is active. (Oscillator is connected.) Watchdog timer is used at stop mode termination. 1 : Oscillation circuit is inactive. (External clock is input.) When the system clock select bit (bit 5 at address BC16) = “0,” watchdog timer is not used at stop mode termination. When the system clock select bit = “1,” watchdog timer is used at stop mode termination. 7 to 2 Fix these bits to “000000.” 0 RW Note: Writing to these bits requires the following procedure: • Write “5516” to this register. (The bit status does not change only by this writing.) • Succeedingly, write “0” or “1” to each bit. Also, use the MOVMB (MOVM when m = 1) instruction or STAB (STA when m = 1) instruction. If an interrupt occurs between writing of “5516” and next writing of “0” or “1,” latter writing may be ignored. When there is a possibility that an interrupt occurs at the above timing, be sure to read this bit’s contents after writing of “0” or “1,” and verify whether “0” or “1” has correctly been written or not. b7 b6 b5 b4 b3 b2 b1 b0 Particular function select register 1 (Address 6316) Bit 0 1 2 3 4 5 6 Bit name STP-instruction-execution status bit WIT-instruction-execution status bit Fix this bit to “0.” System clock stop select bit at WIT (Note 3) Fix this bit to “0.” The value is “0” at reading. Timer B2 clock source select bit 0 : External signal input to the TB2IN pin is counted. (Valid in event counter mode.) 1 : fX32 is counted. (Note 4) The value is “0” at reading. 0 : In the wait mode, system clock fsys is active. 1 : In the wait mode, system clock fsys is inactive. Function 0 : Normal operation. 1 : During execution of STP instruction 0 : Normal operation. 1 : During execution of WIT instruction 0 0 R/W RW (Note 2) RW (Note 2) RW RW RW — RW 8-15 16-5 Reference 15-6 At reset (Note 1) (Note 1) 0 0 0 0 0 7 0 — Notes 1: At power-on reset, this bit becomes “0.” At hardware reset or software reset, this bit retains the value just before reset. 2: Even when “1” is written, the bit status will not change. 3: Setting this bit to “1” must be performed just before execution of the WIT instruction. Also, after the wait state is terminated, this bit must be cleared to “0” immediately. 4: When using timer B2 in the pulse period/pulse width measurement mode, be sure to clear this bit to “0.” 7 905 Group User’s Manual Rev.1.0 20-33 APPENDIX Appendix 2. Control registers Particular function select register 2 (Address 6416) Bit 7 to 0 Function Disables the watchdog timer. When values of “7916” and “5016” succeedingly in this order, the watchdog timer will stop its operation. b7 b0 At reset Undefined R/W — Reference 14-4 Note: After reset, this register can be set only once. Writing to this register requires the following procedure: • Write values of “7916” and “5016” to this register succeedingly in this order. • For the above writing, be sure to use the MOVMB (MOVM when m = 1) instruction or the STAB (STA when m = 1). Note that the following: if an interrupt occurs between writing of “7916” and next writing of “5016,” the watchdog timer does not stop its operation. If any of the following has been performed after reset, writing to this register will be disabled from that time: • If this register is read out. • If writing to this register is performed by the procedure other than the above procedure. 20-34 7 905 Group User’s Manual Rev.1.0 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Debug control register 0 (Address 6616) Bit 0 1 2 3 4 5 6 7 Detect enable bit Fix this bit to “0.” The value is “1” at reading. 0 : Detection disabled. 1 : Detection enabled. Fix these bits to “00.” Bit name Detect condition select bits (Note 1) b2 b1 b0 0 Function 0 0 0 : Do not select. 0 0 1 : Address matching detection 0 0 1 0 : Address matching detection 1 0 1 1 : Address matching detection 2 1 0 0 : Do not select. 1 0 1 : Out-of-address-area detection 110: Do not select. 111: 00 At reset (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) 1 R/W RW RW RW RW RW RW RW — Reference 17-3 Notes 1: These bits are valid when the detect enable bit (bit 5) = “1.” Therefore, these bits must be set before or simultaneously with setting of the detect enable bit to “1.” 2: At power-on reset, each bit becomes “0”; at hardware reset or software reset, each bit retains the value immediately before reset. b7 b6 b5 b4 b3 b2 b1 b0 Debug control register 1 (Address 6716) Bit 0 1 2 3 4 5 6 Bit name Fix this bit to “0.” The value is “0” at reading. Address compare register access enable bit (Note 2) 0 : Disabled. 1 : Enabled. Function 1 At reset (Note 1) (Note 1) 0 0 Undefined 0 0 0 R/W RW RO RW RW — RO RO Reference 17-4 Fix this bit to “1” when using the debug function. Nothing is assigned. While a debugger is not used, the value is “0” at reading. While a debugger is used, the value is “1” at reading. Address-matching-detection 2 decision bit (Valid when the address matching detection 2 is selected.) The value is “0” at reading. 0 : Matches with the contents of the address compare register 0. 1 : Matches with the contents of the address compare register 1. 7 0 — Notes 1: At power-on reset, each bit becomes “0”; at hardware reset or software reset, each bit retains the value immediately before reset. 2: Be sure to set this bit to “1” immediately before the access to the address compare registers 0 and 1 (addresses 6816 to 6D16). Then, be sure to clear this bit to “0” immediately after this access. 7 905 Group User’s Manual Rev.1.0 20-35 APPENDIX Appendix 2. Control registers (b23) (b16) (b15) (b8) b7 b0 b7 b0 b7 Address compare register 0 (Addresses 6A16 to 6816) Address compare register 1 (Addresses 6D16 to 6B16) Bit 23 to 0 Function b0 At reset R/W RW Reference 17-5 The address to be detected (in other words, the start address of instructions) is set here. Undefined Note: When accessing these registers, be sure to set the address compare register access enable bit (bit 2 at address 6716) to “1” immediately before this access. Then, be sure to clear this bit to “0” immediately after this access. 20-36 7 905 Group User’s Manual Rev.1.0 APPENDIX Appendix 2. Control registers INT0, INT1, INT2 interrupt control registers (Addresses 7D16, 7E16, 7F16) INT3, INT4 interrupt control registers (Addresses 6E16, 6F16) INT5, INT6, INT7 interrupt control registers (Addresses FD16, FE16, FF16) Bit 0 1 2 3 4 Interrupt request bit (Note 1) Polarity select bit Bit name Interrupt priority level select bits b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 Function 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested 0 : The interrupt request bit is set to “1” at “H” level when level sense is selected; this bit is set to “1” at falling edge when edge sense is selected. 1 : The interrupt request bit is set to “1” at “L” level when level sense is selected; this bit is set to “1” at rising edge when edge sense is selected. 0 : Edge sense 1 : Level sense At reset 0 0 0 0 0 R/W RW RW RW RW (Note 2) RW Reference 6-7 6-17 5 7, 6 Level sense/Edge sense select bit Nothing is assigned. 0 Undefined RW — Notes 1: The interrupt request bits of INT0 to INT7 interrupts are invalid when the level sense is selected. 2: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2 interrupt control registers (Addresses 7016 to 7C16) UART2 transmit, UART2 receive interrupt control registers (Addresses F116, F216) Timers A5 to A9 interrupt control registers (Addresses F516 to F916) b7 b6 b5 b4 b3 b2 b1 b0 Bit 0 1 2 3 7 to 4 Bit name Interrupt priority level select bits b2 b1 b0 Function 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested At reset 0 0 0 R/W RW RW RW Reference 6-7 Timer Ai 7-8 Timer Bi 8-5 UART0 UART1 UART2 11-16 A-D 12-14 Interrupt request bit Nothing is assigned. RW 0 (Note 1) (Note 2) Undefined — Notes 1: The A-D conversion interrupt request bit is undefined after reset. 2: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. 7 905 Group User’s Manual Rev.1.0 20-37 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 External interrupt input read register (Address 9516) Bit 0 1 2 3 4 5 6 7 Bit name INT0 read out bit INT1 read out bit INT2 read out bit INT3 read out bit INT4 read out bit INT5 read out bit INT6 read out bit INT7 read out bit Function The input level at the corresponding pin is read out. 0 : “L” level 1 : “H” level At reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W RO RO RO RO RO RO RO RO Reference 6-17 20-38 7 905 Group User’s Manual Rev.1.0 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 D-A control register (Address 9616) Bit 0 1 Bit name D-A0 o utput enable bit D-A1 o utput enable bit Function 0: Output is disabled. 1: Output is enabled. ( Notes 1, 2) 0: Output is disabled. 1: Output is enabled. ( Notes 1, 2) At reset 0 0 Undefined R/W RW RW — Reference 13-3 7 to 2 Nothing is assigned. Notes 1: Pin DAi is multiplexed with an analog input pin or serial input/output pin. When a D-Ai output enable bit = “1” (in other words, output is enabled.), however, the corresponding pin cannot function as any other multiplexed input/output pin (including a programmable I/O port pin). 2: When not using the D-A converter, be sure to clear this bit to “0.” b7 b0 D-A register i (i = 0 and 1) (Addresses 98 16 a nd 99 16) Bit 7 to 0 Function Any value in the range from 00 16 t hrough FF16 c an be set ( Note) , and this value will be D-A converted and will be output. At reset 0 R/W RW Reference 13-3 Note: When not using the D-A converter, be sure to clear the contents of these bits to “0016.” b7 b6 b5 b4 b3 b2 b1 b0 Flash memory control register (Address 9E16) Bit 0 Bit name RY/BY status bit Function 0 : BUSY (Automatic programming or erase operation is active.) 1 : READY (Automatic programming or erase operation has been completed.) At reset 1 R/W RO Reference 19-10 19-11 1 2 3 CPU reprogramming mode select bit 0 : Flash memory CPU reprogramming mode is invalid. 1 : Flash memory CPU reprogramming mode is valid. The value is “0” at reading. Flash memory reset bit (Note 3) Writing “1” into this bit discontinues the access to the internal flash memory. This causes the built-in flash memory circuit being reset. 0 0 0 RW (Notes 1, 2) — RW (Note 4) — RW (Note 2) — 4 5 7, 6 The value is “0” at reading. 0 : Access to boot ROM area User ROM area select bit (Valid in boot mode) (Note 5) 1 : Access to user ROM area The value is “0” at reading. 0 0 0 Notes 1: In order to set this bit to “1,” write “0” followed with “1” successively; while in order to clear this bit “0,” write “0.” 2: Writing to this bit must be performed in an area other than the internal flash memory. 3: T his bit is valid when the CPU reprogramming mode select bit (bit 1) = “1”: on the other hand, when the CPU reprogramming mode select bit = “0,” be sure to fix this bit to “0.” Rewriting of this bit must be performed with the CPU reprogramming mode select bit = “1.” 4: After writing of “1” to this bit, be sure to confirm the RY/BY status bit (bit 0) becomes “1”; and then, write “0” to this bit. 5: When MD1 = Vss level, this bit is invalid. (It may be either “0” or “1.”) 7 905 Group User’s Manual Rev.1.0 20-39 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Pulse output control register (Address A016) Bit 0 1 2 3 4 5 6 Pulse output mode select bit Pulse width modulation timer select bits Waveform output control bit 0 0 : Pulse mode 0 1 : Pulse mode 1 See Table 9.3.2. When pulse mode 0 is selected, 0: RTP30 to RTP33: pulse outputs are disabled. 1: RTP30 to RTP33: pulse outputs are enabled. When pulse mode 1 is selected, 0: RTP32, RTP33: pulse outputs are disabled. 1: RTP32, RTP33: pulse outputs are enabled. When pulse mode 0 is selected, 0 : RTP20 to RTP23: pulse outputs are disabled. 1 : RTP20 to RTP23: pulse outputs are enabled. When pulse mode 1 is selected, 0 : RTP20 to RTP23, RTP30, RTP31: pulse outputs are disabled. 1 : RTP20 to RTP23, RTP30, RTP31: pulse outputs are enabled. Bit name Waveform output select bits (Note) See Table 9.3.1. Function At reset 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW Reference 9-17 9-18 7 Waveform output control bit 1 0 RW Note: When not using pulse output port 1, be sure to fix these bits to “0002.” 20-40 7 905 Group User’s Manual Rev.1.0 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Pulse output data register 0 (Address A216) Bit 0 1 2 3 4 5 7, 6 Bit name RTP20 pulse output data bit RTP21 pulse output data bit RTP22 pulse output data bit RTP23 pulse output data bit RTP30 pulse output data bit (Valid in pulse mode 1) (Note) RTP31 pulse output data bit (Valid in pulse mode 1) (Note) Pulse output trigger select bits b7 b6 Function 0 : “L” level output 1 : “H” level output At reset 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW Reference 9-20 0 0 : Underflow of timer A5 0 1 : Falling edge of input signal to pin RTPTRG1 1 0 : Rising edge of input signal to pin RTPTRG1 1 1 : Both falling and rising edges of input signal to pin RTPTRG1 RW Note: This bit is invalid in pulse mode 0. b7 b6 b5 b4 b3 b2 b1 b0 Pulse output data register 1 (Address A416) Bit 0 1 2 3 4 5 6 7 Bit name Pulse width modulation enable bit 0 Pulse width modulation enable bit 1 Pulse width modulation enable bit 2 Pulse output polarity select bit RTP30 pulse output data bit (Valid in pulse mode 0) (Note) RTP31 pulse output data bit (Valid in pulse mode 0) (Note) RTP32 pulse output data bit RTP33 pulse output data bit Function 0 : No pulse width modulation by timer A6 1 : Pulse width modulation by timer A6 0 : No pulse width modulation by timer A7 1 : Pulse width modulation by timer A7 0 : No pulse width modulation by timer A9 1 : Pulse width modulation by timer A9 0 : Positive 1 : Negative 0 : “L” level output 1 : “H” level output At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Reference 9-20 Note: This bit is invalid in pulse mode 1. 7 905 Group User’s Manual Rev.1.0 20-41 APPENDIX Appendix 2. Control registers Waveform output mode register (Address A616) s Three-phase waveform mode b7 b6 b5 b4 b3 b2 b1 b0 Waveform output mode register (Address A616) Bit 0 1 2 3 4 5 6 Three-phase output polarity set buffer 0 : “H” output (Valid in three-phase mode 1) (Note 2) 1 : “L” output Three-phase mode select bit 0 : Three-phase mode 0 1 : Three-phase mode 1 Bit name Waveform output select bits (Note 1) b2 b1 b0 X Function 100 At reset 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW Reference 10-6 1 0 0 : Three-phase waveform mode Invalid in the three-phase waveform mode. Dead-time timer trigger select bit (Note 3) 0: Both falling and rising edges of one-shot pulse for timers A0 to A2 1: Only the falling edge of one-shot pulse for timers A0 to A2 0 : Waveform output disabled 1 : Waveform output enabled 7 Waveform output control bit 0 RW X: It may be either “0” or “1.” Notes 1: When not using pulse output port 0 and three-phase waveform mode, be sure to fix these bits to “0002.” 2: This bit is invalid in three-phase mode 0. 3: When the saw-tooth-wave modulation output is performed, be sure to fix this bit to “0.” 4: Writing to any of bits 0 to 6 must be performed while counting for timers A0 to A3 halts. s Pulse output mode (Pulse output port 0) b7 b6 b5 b4 b3 b2 b1 b0 Waveform output mode register (Address A616) Bit 0 1 2 3 4 5 6 Pulse output mode select bit Pulse width modulation timer select bits Waveform output control bit 0 0 : Pulse mode 0 1 : Pulse mode 1 See Table 9.2.2. When pulse mode 0 is selected, 0: RTP10 to RTP13: pulse outputs are disabled. 1: RTP10 to RTP13: pulse outputs are enabled. When pulse mode 1 is selected, 0: RTP12, RTP13: pulse outputs are disabled. 1: RTP12, RTP13: pulse outputs are enabled. When pulse mode 0 is selected, 0 : RTP00 to RTP03: pulse outputs are disabled. 1 : RTP00 to RTP03: pulse outputs are enabled. When pulse mode 1 is selected, 0 : RTP00 to RTP03, RTP10, RTP11: pulse outputs are disabled. 1 : RTP00 to RTP03, RTP10, RTP11: pulse outputs are enabled. Bit name Waveform output select bits (Note) See Table 9.2.1. Function At reset 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW Reference 9-6 9-7 7 Waveform output control bit 1 0 RW Note: When not using pulse output port 0 and three-phase waveform mode, be sure to fix these bits to “0002.” 20-42 7 905 Group User’s Manual Rev.1.0 APPENDIX Appendix 2. Control registers b7 b0 Dead-time timer (Address A716) Bit 7 to 0 Function A value in the range from “0016” to “FF16” can be set. At reset Undefined R/W WO Reference 10-7 Note: Use the MOVMB (MOVM when m = 1) or STAB (STA when m = 1) instruction for writing to this register. Additionally, make sure writing to this register does not overlap with a trigger-occurrence timing of the dead-time timer. 7 905 Group User’s Manual Rev.1.0 20-43 APPENDIX Appendix 2. Control registers Three-phase output data register 0 (Address A816) s Three-phase waveform mode b7 b6 b5 b4 b3 b2 b1 b0 Three-phase output data register 0 (Address A816) Bit 0 1 2 3 Bit name W-phase output fix bit V-phase output fix bit U-phase output fix bit Function 0 : Released from output fixation 1 : Output fixed 0 : Released from output fixation 1 : Output fixed 0 : Released from output fixation 1 : Output fixed XX At reset 0 0 0 0 R/W RW RW RW RW Reference 10-9 W-phase output polarity set buffer 0 : “H” output (Valid in three-phase mode 0.) 1 : “L” output (Note) Invalid in the three-phase waveform mode. Clock-source-of-dead-time-timer b7 b6 : f2 00 0 1 : f2/2 select bits 1 0 : f2/4 1 1 : Do not select. 5, 4 6 7 0 0 0 RW RW RW X: It may be either “0” or “1.” Note: This bit is invalid in three-phase mode 1. s Pulse output port mode (Pluse output port 0) b7 b6 b5 b4 b3 b2 b1 b0 Three-phase output data register 0 (Address A816) Bit 0 1 2 3 4 5 7, 6 Bit name RTP00 pulse output data bit RTP01 pulse output data bit RTP02 pulse output data bit RTP03 pulse output data bit RTP10 pulse output data bit (Valid in pulse mode 1.) (Note) RTP11 pulse output data bit (Valid in pulse mode 1.) (Note) Pulse output trigger select bits b7 b6 Function 0 : “L” level output 1 : “H” level output At reset 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW Reference 9-9 0 0 : Underflow of timer A0 0 1 : Falling edge of input signal to pin RTPTRG0 1 0 : Rising edge of input signal to pin RTPTRG0 1 1 : Both falling and rising edges of input signal to pin RTPTRG0 0 Note: This bit is invalid in pulse mode 0. 20-44 7 905 Group User’s Manual Rev.1.0 APPENDIX Appendix 2. Control registers Three-phase output data register 1 (Address A916) s Three-phase waveform mode b7 b6 b5 b4 b3 b2 b1 b0 Three-phase output data register 1 (Address A916) Bit 0 1 2 3 4 Bit name W-phase fixed output’s polarity set bit (Note 1) V-phase fixed output’s polarity set bit (Note 2) U-phase fixed output’s polarity set bit (Note 3) 0 : “H” output fixed 1 : “L” output fixed 0 : “H” output fixed 1 : “L” output fixed 0 : “H” output fixed 1 : “L” output fixed Function XX X At reset 0 0 0 0 0 R/W RW RW RW RW RW Reference 10-11 Invalid in the three-phase waveform mode. V-phase output polarity set buffer 0 : “H” output 1 : “L” output (in three-phase mode 0) Interrupt request interval set bit (in three-phase mode 1) 0 : Every second time 1 : Every forth time 5 U-phase output polarity set buffer 0 : “H” output 1 : “L” output (in three-phase mode 0) Interrupt validity output select bit 0 : An interrupt request occurs at each even-numbered underflow of timer A3 (in three-phase mode 1) 1 : An interrupt request occurs at each odd-numbered underflow of timer A3 0 RW 7, 6 Invalid in the three-phase waveform mode. 0 RW X: It may be either “0” or “1.” Notes 1: Valid when the W-phase output fix bit (bit 0 at address A816) = “1.” Be sure not to change the value during output of a fixed value. 2: Valid when the V-phase output fix bit (bit 1 at address A816) = “1.” Be sure not to change the value during output of a fixed value. 3: Valid when the U-phase output fix bit (bit 2 at address A816) = “1.” Be sure not to change the value during output of a fixed value. s Pulse output port mode (Pulse output port 0) b7 b6 b5 b4 b3 b2 b1 b0 Three-phase output data register 1 (Address A916) Bit 0 1 2 3 4 5 6 7 Bit name Pulse width modulation enable bit 0 Pulse width modulation enable bit 1 Pulse width modulation enable bit 2 Pulse output polarity select bit RTP10 pulse output data bit (Valid in pulse mode 0) (Note) RTP11 pulse output data bit (Valid in pulse mode 0) (Note) RTP12 pulse output data bit RTP13 pulse output data bit Function 0 : No pulse width modulation by timer A1 1 : Pulse width modulation by timer A1 0 : No pulse width modulation by timer A2 1 : Pulse width modulation by timer A2 0 : No pulse width modulation by timer A4 1 : Pulse width modulation by timer A4 0 : Positive 1 : Negative 0 : “L” level output 1 : “H” level output At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Reference 9-9 Note: This bit is invalid in pulse mode 1. 7 905 Group User’s Manual Rev.1.0 20-45 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Position-data-retain function control register (Address AA16) Bit 0 Bit name W-phase position data retain bit V-phase position data retain bit U-phase position data retain bit Retain-trigger polarity select bit Nothing is assigned. Function Input level at pin IDW is read out. 0 : “L” level 1 : “H” level Input level at pin IDV is read out. 0 : “L” level 1 : “H” level Input level at pin IDU is read out. 0 : “L” level 1 : “H” level 0 : Falling edge of positive phase 1 : Rising edge of positive phase At reset 0 R/W RO Reference 10-12 1 2 3 7 to 4 0 RO 0 0 Undefined RO RW — Note: This register is valid only in the three-phase mode. b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O pin control register (Address AC16) Bit 0 1 2 3 4 Bit name CTS0/RTS0 separate select bit (Note) CTS1/RTS1 separate select bit (Note) TxD0/P13 switch bit TxD1/P17 switch bit CTS2/RTS2 separate select bit (Note) TxD2/P83 switch bit The value is “00” at reading. Function 0 : CTS0/RTS0 are used together. 1 : CTS0/RTS0 are separated. 0 : CTS1/RTS1 are used together. 1 : CTS1/RTS1 are separated. 0 : Functions as TxD0. 1 : Functions as P13. 0 : Functions as TxD1. 1 : Functions as P17. 0 : CTS2/RTS2 are used together. 1 : CTS2/RTS2 are separated. 0 : Functions as TxD2. 1 : Functions as P83. At reset 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW — Reference 11-17 11-18 5 7, 6 Note: Valid when the CTS/RTS enable bit (bit 4 at addresses 3416, 3C16, and B416) is “0.” 20-46 7 905 Group User’s Manual Rev.1.0 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Port P2 pin function control register (Address AE16) Bit 0 1 2 6 to 3 7 Bit name Pin TB0IN select bit Pin TB1IN select bit Pin TB2IN select bit Nothing is assigned. Fix this bit to “0.” Function 0 : Allocate pin TB0IN to P55. 1 : Allocate pin TB0IN to P24. 0 : Allocate pin TB1IN to P56. 1 : Allocate pin TB1IN to P25. 0 : Allocate pin TB2IN to P57. 1 : Allocate pin TB2IN to P26. 0 At reset 0 0 0 Undefined 0 R/W RW RW RW — RW Reference 8-6 7 905 Group User’s Manual Rev.1.0 20-47 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Clock control register 0 (Address BC16) Bit 0 1 Bit name Function 1 At reset 1 1 1 R/W RW RW Reference 4-6 4-7 Fix this bit to “1.” PLL circuit operation enable bit 0 : PLL frequency multiplier is inactive, and pin VCONT is invalid. (Floating) (Note 1) 1 : PLL frequency multiplier is active, and pin VCONT is valid. PLL multiplication ratio select bits (Note 2) b3 b2 2 3 4 5 6 7 0 0 : Do not select. 01:✕2 10:✕3 11:✕4 1 0 1 RW RW RW RW RW RW Fix this bit to “1.” System clock select bit 0 : fXIN (Note 3) 1 : fPLL 0 0 0 Peripheral device’s clock select bit 0 See Table 4.2.2. Peripheral device’s clock select bit 1 Notes 1: Clear this bit to “0” if the PLL frequency multiplier needs not to be active. In the stop and flash memory parallel I/O modes, the PLL frequency multiplier is inactive and pin VCONT is invalid regardless of the contents of this bit. 2: Rewriting of these bits must be performed simultaneously with clearance of the system clock select bit (bit 5) to “0.” Then, set bit 5 to “1” 2 ms after the rewriting of these bits. (After reset, these bits are allowed to be changed only once.) 3: Clearance of the PLL circuit operation enable bit (bit 1) to “0” clears the system clock select bit to “0.” Also, while the PLL circuit operation enable bit = “0,” nothing can be written to the system clock select bit. (Fixed to be “0.”) Before setting of the system clock select bit to “1” after reset, it is necessary to insert an interval of 2 ms after the stabilization of f(XIN). 20-48 7 905 Group User’s Manual Rev.1.0 APPENDIX Appendix 2. Control registers Timer A01 register (Addresses D116, D016) Timer A11 register (Addresses D316, D216) Timer A21 register (Addresses D516, D416) Bit (b15) b7 (b8) b0 b7 b0 Function At reset R/W WO Reference 10-13 Undefined 15 to 0 Any value in the range from 000016 to FFFF16 can be set. Assuming that the set value = n, the “H” level width of the one-shot pulse is expressed as follows: n/fi. fi: Frequency of a count source Notes 1: Use the MOVM or STA (STAD) instruction for writing to this register. Additionally, make sure writing to this register must be performed in a unit of 16 bits. 2: This register is valid only in three-phase mode 1 of the three-phase waveform mode. 7 905 Group User’s Manual Rev.1.0 20-49 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Comparator function select register 0 (Address DC16) Bit 0 1 2 3 4 5 6 7 Bit name AN0 pin comparator function select bit AN1 pin comparator function select bit AN2 pin comparator function select bit AN3 pin comparator function select bit AN4 pin comparator function select bit AN5 pin comparator function select bit AN6 pin comparator function select bit AN7 pin comparator function select bit Function 0 : The comparator function is not selected. 1 : The comparator function is selected. At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Reference 12-12 Note: Writing to comparator function select register 0 must be performed while the A-D converter halts. b7 b6 b5 b4 b3 b2 b1 b0 Comparator function select register 1 (Address DD16) Bit 0 1 2 3 7 to 4 Bit name AN8 pin comparator function select bit AN9 pin comparator function select bit AN10 pin comparator function select bit AN11 pin comparator function select bit Fix these bits to “0000.” Function 0000 At reset 0 0 0 0 0 R/W RW RW RW RW RW Reference 12-12 0 : The comparator function is not selected. 1 : The comparator function is selected. Note: Writing to comparator function select register 1 must be performed while the A-D converter halts. 20-50 7 905 Group User’s Manual Rev.1.0 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Comparator result register 0 (Address DE16) Bit 0 1 2 3 4 5 6 7 Bit name AN0 pin comparator result bit AN1 pin comparator result bit AN2 pin comparator result bit AN3 pin comparator result bit AN4 pin comparator result bit AN5 pin comparator result bit AN6 pin comparator result bit AN7 pin comparator result bit Function 0 : The set value > The input level at pin ANi 1 : The set value < The input level at pin ANi At reset 0 0 0 0 0 0 0 0 R/W RW RW RW RW RW RW RW RW Reference 12-12 Note: Writing to comparator result register 0 must be performed while the A-D converter halts. b7 b6 b5 b4 b3 b2 b1 b0 Comparator result register 1 (Address DF16) Bit 0 1 2 3 7 to 4 Bit name AN8 pin comparator result bit AN9 pin comparator result bit AN10 pin comparator result bit AN11 pin comparator result bit Fix these bits to “0000.” Function 0000 At reset 0 0 0 0 0 R/W RW RW RW RW RW Reference 12-12 0 : The set value > The input level at pin ANi 1 : The set value < The input level at pin ANi Note: Writing to comparator result register 1 must be performed while the A-D converter halts. 7 905 Group User’s Manual Rev.1.0 20-51 APPENDIX Appendix 3. Package outline Appendix 3. Package outline 64P4B EIAJ Package Code SDIP64-P-750-1.78 JEDEC Code – Weight(g) 7.9 Lead Material Alloy 42 Plastic 64pin 750mil SDIP 64 33 1 32 Symbol D A2 e SEATING PLANE b1 b b2 A A1 A2 b b1 b2 c D E e e1 L Dimension in Millimeters Min Nom Max – – 5.08 0.38 – – – 3.8 – 0.4 0.5 0.6 0.9 1.0 1.3 0.65 0.75 1.05 0.2 0.25 0.32 56.2 56.4 56.6 16.85 17.0 17.15 – 1.778 – – 19.05 – 2.8 – – 0° – 15° L A 64P6N-A EIAJ Package Code QFP64-P-1414-0.80 HD D 64 49 JEDEC Code – Weight(g) 1.11 Lead Material Alloy 42 e A1 Plastic 64pin 14✕14mm body QFP MD e1 E c 1 48 b2 I2 Recommended Mount Pad Symbol HE E 16 33 17 32 A L1 F M A A1 A2 b c D E e HD HE L L1 x y b2 I2 MD ME A1 e y b x L Detail F Dimension in Millimeters Min Nom Max – – 3.05 0.1 0.2 0 – – 2.8 0.3 0.35 0.45 0.13 0.15 0.2 13.8 14.0 14.2 13.8 14.0 14.2 0.8 – – 16.5 16.8 17.1 16.5 16.8 17.1 0.4 0.6 0.8 1.4 – – – – 0.2 0.1 – – 0° 10° – 0.5 – – – – 1.3 14.6 – – – – 14.6 A2 20-52 7905 Group User’s Manual Rev.1.0 c ME APPENDIX Appendix 4. Examples of handling unused pins Appendix 4. Examples of handling unused pins When unusing an I/O pin, some handling is necessary for this pin. Examples of handling unused pins are described below. The following are just examples. In actual use, the user shall modify them according to the user’s application and properly evaluate their performance. Table 1 Example of handling unused pins Pin name P1, P2, P5 to P8 Handling example Set these pins to the input mode and connect each pin to Vcc or Vss via a resistor; or set these pins to the output mode and leave them open ( Note 1). P4OUTCUT/INT 0, P6OUTCUT/INT 4 XOUT ( Note 2) , VCONT ( Note 3) AVCC AVSS, VREF Connect this pin to Vcc via a resistor. Select a falling edge for pins INT 0 a nd INT 4. Leave these pins open. Connect this pin to Vcc. Connect these pins to Vss. Notes 1: When leaving these pins open after they have been set to the output mode, note the following: these port pins are placed in the input mode from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these port pins are placed in the input mode. Software reliability can be enhanced by setting the contents of the above ports’ direction registers periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins). 2: This applies when a clock externally generated is input to pin X IN. 3: Be sure that the PLL circuit operation enable bit (bit 1 at address BC16) = “0.” When setting port pins to input mode When setting port pins to output mode P1, P2, P5 to P8 P1, P2, P5 to P8 XOUT VCONT Left open XOUT VCONT Left open VCC Left open VCC P4OUT CUT /INT 0 P6OUT CUT /INT 4 Fig. 1 Example of handling unused pins M37905 M37905 AV CC AV SS VR E F VCC AV CC AV SS VR EF VCC VSS VSS P4OUT CUT /INT 0 P6OUT CUT /INT 4 7905 Group User’s Manual Rev.1.0 20-53 APPENDIX Appendix 5. Hexadecimal instruction code table Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE 0 D3–D0 Hexadecimal D7–D4 notation 0000 0 BRK IMP BPL REL BRA REL BMI REL BGTU REL BVC REL BLEU REL BVS REL BGT REL BCC REL BLE REL BCS REL BGE REL BNE REL BLT REL BEQ REL 0001 1 Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 0010 2 LDX DIR LDY DIR CPX DIR CPY DIR BBSB DIR,b,REL BBCB DIR,b,REL CBEQB DIR/IMM,REL 0011 3 ASL A ROL A ANDB A,IMM EORB A,IMM LSR A ROR A ORAB A,IMM 0100 4 SEC IMP CLC IMP NEG A EXTZ A CLRB A CLR A ASR A NOP IMP 0101 5 SEI IMP CLI IMP SEM IMP EXTS A CLM IMP XAB IMP CLV IMP 0110 6 0111 7 LDX ABS 1000 8 LDAB A,(DIR),Y LDA A,(DIR),Y LDAB A,IMM CMPB A,IMM MOVMB DIR/DIR MOVM DIR/DIR MOVMB ABS/DIR MOVM ABS/DIR LDAD E,(DIR),Y CLP IMM PSH STK LDD n /PHD n /PHLD n STK/IMM 1001 9 LDAB A,L(DIR),Y LDA A,L(DIR),Y ADDB A,IMM SUBB A,IMM 1010 A LDAB A,DIR LDA A,DIR ADD A,DIR SUB A,DIR CMP A,DIR ORA A,DIR 1011 B LDAB A,DIR,X LDA A,DIR,X ADD A,DIR,X SUB A,DIR,X CMP A,DIR,X ORA A,DIR,X AND A,DIR,X E OR A,DIR,X LDAD E,DIR,X ADDD E,DIR,X SUBD E,DIR,X CMPD E,DIR,X STAB A,DIR,X STA A,DIR,X STAD E,DIR,X 1100 C LDAB A,ABL LDA A,ABL LDAD E,IMM CMPD E,IMM MOVMB DIR/ABS MOVM DIR/ABS MOVMB ABS/ABS MOVM ABS/ABS LDAD E,ABL JMP ABS JMPL ABL JMP (ABS,X) STAB A,ABL STA A,ABL STAD E,ABL BSR REL 1101 D LDAB A,ABL,X LDA A,ABL,X ADDD E,IMM SUBD E,IMM MOVMB DIR/ABS,X MOVM DIR/ABS,X 1110 E LDAB A,ABS LDA A,ABS ADD A,ABS SUB A,ABS CMP A,ABS ORA A,ABS AND A,ABS E OR A,ABS 1111 F LDAB A,ABS,X LDA A,ABS,X ADD A,ABS,X SUB A,ABS,X CMP A,ABS,X ORA A,ABS,X AND A,ABS,X EOR A,ABS,X LDAD E,ABS,X ADDD E,ABS,X SUBD E,ABS,X CMPD E,ABS,X STAB A,ABS,X STA A,ABS,X STAD E,ABS,X 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F LDA A,IMM ADD A,IMM SUB A,IMM CMP A,IMM ORA A,IMM AND A,IMM E OR A,IMM LDY ABS LDXB IMM LDYB IMM BBSB ABS,b,REL BBCB ABS,b,REL PUL STK PLD n /RTLD n /RTSD n STK MOVMB ABS/DIR,X MOVM ABS/DIR,X LDAD E,L(DIR),Y SEP IMM MOVMB DIR/IMM MOVMB ABS/IMM STAB A,L(DIR),Y STA A,L(DIR),Y STAD E,L(DIR),Y AND A,DIR E OR A,DIR LDAD E,DIR ADDD E,DIR SUBD E,DIR CMPD E,DIR STAB A,DIR STA A,DIR STAD E,DIR CBNEB DIR/IMM,REL INC DIR DEC DIR CBEQB A/IMM,REL CBNEB PHD STK PLD STK INC A DEC A INX IMP INY IMP DEX IMP DEY IMP RTS IMP RTL IMP TXA IMP TYA IMP TAX IMP TAY IMP CLRX IMP CLRY IMP PHA STK PLA STK PHP STK PLP STK PHX STK PLX STK PHY STK PLY STK MOVM DIR/IMM MOVM ABS/IMM CBEQ A/IMM,REL CBNE A/IMM,REL LDX IMM LDY IMM CPX IMM CPY IMM INC ABS DEC ABS BRAL REL LDAD E,ABL,X JSR ABS JSRL ABL JSR (ABS,X) STAB A,ABL,X STA A,ABL,X STAD E,ABL,X LDAD E,ABS ADDD E,ABS SUBD E,ABS CMPD E,ABS STAB A,ABS STA A,ABS STAD E,ABS Table 12 A/IMM,REL Table 13 Table 14 ABS A RTI IMP CLRMB DIR CLRM DIR STX DIR STY DIR CLRMB ABS CLRM ABS STX ABS STY ABS STAB A,(DIR),Y STA A,(DIR),Y STAD E,(DIR),Y Note: Tables 1 through 14 specifies the contents of the INSTRUCTION CODE TABLE 1 through 14. About the second word’s codes, refer to the INSTRUCTION CODE TABLE 1 through 14. 20-54 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE 1 (The first word’s code of each instruction is 0116) D3–D0 Hexadecimal D7–D4 notation 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F ADDX IMM ADDY IMM SUBX IMM SUBY IMM BSS A,b,REL BSC A,b,REL DXBNE IMM,REL DYBNE IMM,REL INSTRUCTION CODE TABLE 2 (The first word’s code of each instruction is 1116) D3–D0 Hexadecimal D7–D4 notation 0000 0 LDAB A,(DIR) LDA A,(DIR) ADD A,(DIR) SUB A,(DIR) CMP A,(DIR) ORA A,(DIR) AND A,(DIR) E OR A,(DIR) LDAD E,(DIR) ADDD E,(DIR) SUBD E,(DIR) CMPD E,(DIR) STAB A,(DIR) STA A,(DIR) STAD E,(DIR) 0001 1 LDAB A,(DIR,X) LDA A,(DIR,X) ADD A,(DIR,X) SUB A,(DIR,X) CMP A,(DIR,X) ORA A,(DIR,X) AND A,(DIR,X) E OR A,(DIR,X) LDAD E,(DIR,X) ADDD E,(DIR,X) SUBD E,(DIR,X) CMPD E,(DIR,X) STAB A,(DIR,X) STA A,(DIR,X) STAD E,(DIR,X) 0010 2 LDAB A,L(DIR) LDA A,L(DIR) ADD A,L(DIR) SUB A,L(DIR) CMP A,L(DIR) ORA A,L(DIR) AND A,L(DIR) E OR A,L(DIR) LDAD E,L(DIR) ADDD E,L(DIR) SUBD E,L(DIR) CMPD E,L(DIR) STAB A,L(DIR) STA A,L(DIR) STAD E,L(DIR) 0011 3 LDAB A,SR LDA A,SR ADD A,SR SUB A,SR CMP A,SR ORA A,SR AND A,SR E OR A,SR LDAD E,SR ADDD E,SR SUBD E,SR CMPD E,SR STAB A,SR STA A,SR STAD E,SR 0100 4 LDAB A,(SR),Y LDA A,(SR),Y ADD A,(SR),Y SUB A,(SR),Y CMP A,(SR),Y ORA A,(SR),Y AND A,(SR),Y E OR A,(SR),Y LDAD E,(SR),Y ADDD E,(SR),Y SUBD E,(SR),Y CMPD E,(SR),Y STAB A,(SR),Y STA A,(SR),Y STAD E,(SR),Y 0101 5 0110 6 LDAB A,ABS,Y LDA A,ABS,Y ADD A,ABS,Y SUB A,ABS,Y CMP A,ABS,Y ORA A,ABS,Y AND A,ABS,Y E OR A,ABS,Y LDAD E,ABS,Y ADDD E,ABS,Y SUBD E,ABS,Y CMPD E,ABS,Y STAB A,ABS,Y STA A,ABS,Y STAD E,ABS,Y 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F ADD ADD A,(DIR),Y A,L(DIR),Y SUB SUB A,(DIR),Y A,L(DIR),Y CMP CMP A,(DIR),Y A,L(DIR),Y ORA ORA A,(DIR),Y A,L(DIR),Y AND AND A,(DIR),Y A,L(DIR),Y E OR EOR A,(DIR),Y A,L(DIR),Y ADD A,ABL SUB A,ABL CMP A,ABL ORA A,ABL AND A,ABL E OR A,ABL ADD A,ABL,X SUB A,ABL,X CMP A,ABL,X ORA A,ABL,X AND A,ABL,X E OR A,ABL,X ADDD ADDD E,(DIR),Y E,L(DIR),Y SUBD SUBD E,(DIR),Y E,L(DIR),Y CMPD CMPD E,(DIR),Y E,L(DIR),Y ADDD E,ABL SUBD E,ABL CMPD E,ABL ADDD E,ABL,X SUBD E,ABL,X CMPD E,ABL,X 7905 Group User ’ s Manual Rev.1.0 20-55 APPENDIX Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE 3 (The first word’s code of each instruction is 2116) D3–D0 Hexadecimal D7–D4 notation 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A ASL DIR ROL DIR LSR DIR ROR DIR ASR DIR 1011 B ASL DIR,X ROL DIR,X LSR DIR,X ROR DIR,X ASR DIR,X 1100 C 1101 D 1110 E ASL ABS ROL ABS LSR ABS ROR ABS ASR ABS 1111 F ASL ABS,X ROL ABS,X LSR ABS,X ROR ABS,X ASR ABS,X 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F ADC A,(DIR) ADCD E,(DIR) SBC A,(DIR) SBCD E,(DIR) MPY (DIR) MPYS (DIR) DIV (DIR) DIVS (DIR) ADC A,(DIR,X) ADCD E,(DIR,X) SBC A,(DIR,X) SBCD E,(DIR,X) MPY (DIR,X) MPYS (DIR,X) DIV (DIR,X) DIVS (DIR,X) ADC A,L(DIR) ADCD E,L(DIR) SBC A,L(DIR) SBCD E,L(DIR) MPY L(DIR) MPYS L(DIR) DIV L(DIR) DIVS L(DIR) ADC A,SR ADCD E,SR SBC A,SR SBCD E,SR MPY SR MPYS SR DIV SR DIVS SR ADC A,(SR),Y ADCD E,(SR),Y SBC A,(SR),Y SBCD E,(SR),Y MPY (SR),Y MPYS (SR),Y DIV (SR),Y DIVS (SR),Y ADC A,ABS,Y ADCD E,ABS,Y SBC A,ABS,Y SBCD E,ABS,Y MPY ABS,Y MPYS ABS,Y DIV ABS,Y DIVS ABS,Y ADC ADC A,(DIR),Y A,L(DIR),Y ADCD ADCD E,(DIR),Y E,L(DIR),Y SBC SBC A,(DIR),Y A,L(DIR),Y SBCD SBCD E,(DIR),Y E,L(DIR),Y MPY (DIR),Y MPYS (DIR),Y DIV (DIR),Y DIVS (DIR),Y MPY L(DIR),Y MPYS L(DIR),Y DIV L(DIR),Y DIVS L(DIR),Y ADC A,DIR ADCD E,DIR SBC A,DIR SBCD E,DIR MPY DIR MPYS DIR DIV DIR DIVS DIR ADC A,DIR,X ADCD E,DIR,X SBC A,DIR,X SBCD E,DIR,X MPY DIR,X MPYS DIR,X DIV DIR,X DIVS DIR,X ADC A,ABL ADCD E,ABL SBC A,ABL SBCD E,ABL MPY ABL MPYS ABL DIV ABL DIVS ABL ADC A,ABL,X ADCD E,ABL,X SBC A,ABL,X SBCD E,ABL,X MPY ABL,X MPYS ABL,X DIV ABL,X DIVS ABL,X ADC A,ABS ADCD E,ABS SBC A,ABS SBCD E,ABS MPY ABS MPYS ABS DIV ABS DIVS ABS ADC A,ABS,X ADCD E,ABS,X SBC A,ABS,X SBCD E,ABS,X MPY ABS,X MPYS ABS,X DIV ABS,X DIVS ABS,X INSTRUCTION CODE TABLE 4 (The first word’s code of each instruction is 3116) D3–D0 Hexadecimal D7–D4 notation 0000 0 0001 1 0010 2 TAD,0 IMP 0011 3 0100 4 0101 5 0110 6 0111 7 RLA A 1000 8 1001 9 1010 A ADDS IMM ADCB A,IMM MVP BLK 1011 B SUBS IMM SBCB A,IMM MVN BLK 1100 C 1101 D 1110 E 1111 F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F STP IMP PHT STK PLT STK PHG STK TSD IMP NEGD E ABSD E EXTZD E EXTSD E WIT IMP TAD,1 IMP TAD,2 IMP TAD,3 IMP TDA,0 IMP TDA,1 IMP TDA,2 IMP TDA,3 IMP TAS IMP TSA IMP SBC A,IMM TDS IMP ADC A,IMM MOVM DIR,X/IMM MOVM ABS,X/IMM ADCD E,IMM SBCD E,IMM MOVMB MOVMB DIR,X/IMM ABS,X/IMM LDT IMM RMPA Multiplied accumulation PEI STK PEA STK JMP (ABS) PER STK JMPL L(ABS) TXY IMP TYX IMP TXS IMP TSX IMP MPY IMM MPYS IMM DIV IMM DIVS IMM 20-56 7905 Group User ’ s Manual Rev.1.0 APPENDIX Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE 5 (The first word’s code of each instruction is 4116) D3–D0 Hexadecimal D7–D4 notation 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 LDX DIR,Y 0110 6 LDX ABS,Y 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F LDY DIR,X CPX ABS CPY ABS BBS DIR,b,REL BBC DIR,b,REL CBEQ DIR/IMM,REL LDY ABS,X BBS ABS,b,REL BBC ABS,b,REL CBNE DIR/IMM,REL INC DIR,X DEC DIR,X INC ABS,X DEC ABS,X STX DIR,Y STY DIR,X INSTRUCTION CODE TABLE 6 (The first word’s code of each instruction is 5116) D3–D0 Hexadecimal D7–D4 notation 0000 0 0001 1 0010 2 ADDMB DIR/IMM SUBMB DIR/IMM CMPMB DIR/IMM ORAMB DIR/IMM 0011 3 ADDM DIR/IMM SUBM DIR/IMM CMPM DIR/IMM ORAM DIR/IMM 0100 4 0101 5 0110 6 ADDMB ABS/IMM SUBMB ABS/IMM CMPMB ABS/IMM ORAMB ABS/IMM 0111 7 ADDM ABS/IMM SUBM ABS/IMM CMPM ABS/IMM ORAM ABS/IMM 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F ANDMB DIR/IMM EORMB DIR/IMM ANDM DIR/IMM EORM DIR/IMM ADDMD DIR/IMM SUBMD DIR/IMM CMPMD DIR/IMM ORAMD DIR/IMM ANDMB ABS/IMM EORMB ABS/IMM ANDM ABS/IMM EORM ABS/IMM ADDMD ABS/IMM SUBMD ABS/IMM CMPMD ABS/IMM ORAMD ABS/IMM ANDMD DIR/IMM EORMD DIR/IMM ANDMD ABS/IMM EORMD ABS/IMM 7905 Group User ’ s Manual Rev.1.0 20-57 APPENDIX Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE 7 (The first word’s code of each instruction is 6116) D3–D0 Hexadecimal D7–D4 notation 0000 0 MOVRB DIR/IMM MOVR DIR/IMM MOVRB ABS/IMM MOVR ABS/IMM MOVRB DIR/DIR MOVR DIR/DIR MOVRB ABS/DIR MOVR ABS/DIR MOVRB DIR/ABS MOVR DIR/ABS MOVRB ABS/ABS MOVR ABS/ABS 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F INSTRUCTION CODE TABLE 8 (The first word’s code of each instruction is 7116) D3–D0 Hexadecimal D7–D4 notation 0000 0 MOVRB DIR/ABS,X MOVR DIR/ABS,X 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F MOVRB ABS/DIR,X MOVR ABS/DIR,X BSS DIR,b,REL BSC DIR,b,REL BSS ABS,b,REL BSC ABS,b,REL 20-58 7905 Group User ’ s Manual Rev.1.0 APPENDIX Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE 9 (The first word’s code of each instruction is 8116) D3–D0 Hexadecimal D7–D4 notation 0000 0 0001 1 0010 2 0011 3 ASL B ROL B ANDB B,IMM EORB B,IMM LSR B ROR B ORAB B,IMM 0100 4 0101 5 0110 6 0111 7 1000 8 LDAB B,(DIR),Y 1001 9 LDAB B,L(DIR),Y LDA B,L(DIR),Y ADDB B,IMM SUBB B,IMM 1010 A LDAB B,DIR LDA B,DIR ADD B,DIR SUB B,DIR CMP B,DIR ORA B,DIR AND B,DIR E OR B,DIR 1011 B LDAB B,DIR,X LDA B,DIR,X ADD B,DIR,X SUB B,DIR,X CMP B,DIR,X ORA B,DIR,X AND B,DIR,X EOR B,DIR,X 1100 C LDAB B,ABL LDA B,ABL 1101 D LDAB B,ABL,X LDA B,ABL,X 1110 E LDAB B,ABS LDA B,ABS ADD B,ABS SUB B,ABS CMP B,ABS ORA B,ABS AND B,ABS E OR B,ABS 1111 F LDAB B,ABS,X LDA B,ABS,X ADD B,ABS,X SUB B,ABS,X CMP B,ABS,X ORA B,ABS,X AND B,ABS,X E OR B,ABS,X 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F ABS B CBEQB B/IMM,REL CBNEB B/IMM,REL LDA B,IMM NEG B EXTZ B CLRB B CLR B ASR B EXTS B ADD B,IMM SUB B,IMM CMP B,IMM ORA B,IMM AND B,IMM EOR B,IMM PHB STK PLB STK LDA B,(DIR),Y LDAB B,IMM CMPB B,IMM INC B DEC B TXB IMP TYB IMP TBX IMP TBY IMP CBEQ B/IMM,REL CBNE B/IMM,REL STAB B,(DIR),Y STA B,(DIR),Y STAB B,L(DIR),Y STA B,L(DIR),Y STAB B,DIR STA B,DIR STAB B,DIR,X STA B,DIR,X STAB B,ABL STA B,ABL STAB B,ABL,X STA B,ABL,X STAB B,ABS STA B,ABS STAB B,ABS,X STA B,ABS,X INSTRUCTION CODE TABLE 10 (The first word’s code of each instruction is 9116) D3–D0 Hexadecimal D7–D4 notation 0000 0 LDAB B,(DIR) LDA B,(DIR) ADD B,(DIR) SUB B,(DIR) CMP B,(DIR) ORA B,(DIR) AND B,(DIR) E OR B,(DIR) 0001 1 LDAB B,(DIR,X) LDA B,(DIR,X) ADD B,(DIR,X) SUB B,(DIR,X) CMP B,(DIR,X) ORA B,(DIR,X) AND B,(DIR,X) E OR B,(DIR,X) 0010 2 LDAB B,L(DIR) LDA B,L(DIR) ADD B,L(DIR) SUB B,L(DIR) CMP B,L(DIR) ORA B,L(DIR) AND B,L(DIR) E OR B,L(DIR) 0011 3 LDAB B,SR LDA B,SR ADD B,SR SUB B,SR CMP B,SR ORA B,SR AND B,SR E OR B,SR 0100 4 LDAB B,(SR),Y LDA B,(SR),Y ADD B,(SR),Y SUB B,(SR),Y CMP B,(SR),Y ORA B,(SR),Y AND B,(SR),Y EOR B,(SR),Y 0101 5 0110 6 LDAB B,ABS,Y LDA B,ABS,Y ADD B,ABS,Y SUB B,ABS,Y CMP B,ABS,Y ORA B,ABS,Y AND B,ABS,Y EOR B,ABS,Y 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F ADD ADD B,(DIR),Y B,L(DIR),Y SUB SUB B,(DIR),Y B,L(DIR),Y CMP CMP B,(DIR),Y B,L(DIR),Y ORA ORA B,(DIR),Y B,L(DIR),Y AND AND B,(DIR),Y B,L(DIR),Y EOR E OR B,(DIR),Y B,L(DIR),Y ADD B,ABL SUB B,ABL CMP B,ABL ORA B,ABL AND B,ABL E OR B,ABL ADD B,ABL,X SUB B,ABL,X CMP B,ABL,X ORA B,ABL,X AND B,ABL,X EOR B,ABL,X STAB B,(DIR) STA B,(DIR) STAB B,(DIR,X) STA B,(DIR,X) STAB B,L(DIR) STA B,L(DIR) STAB B,SR STA B,SR STAB B,(SR),Y STA B,(SR),Y STAB B,ABS,Y STA B,ABS,Y 7905 Group User ’ s Manual Rev.1.0 20-59 APPENDIX Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE 11 (The first word’s code of each instruction is A116) D3–D0 Hexadecimal D7–D4 notation 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F SBC B,(DIR) SBC B,(DIR,X) SBC B,L(DIR) SBC B,SR SBC B,(SR),Y SBC B,ABS,Y SBC B,(DIR),Y SBC B,L(DIR),Y SBC B,DIR SBC B,DIR,X SBC B,ABL SBC B,ABL,X SBC B,ABS SBC B,ABS,X ADC B,(DIR) ADC B,(DIR,X) ADC B,L(DIR) ADC B,SR ADC B,(SR),Y ADC B,ABS,Y ADC ADC B,(DIR),Y B,L(DIR),Y ADC B,DIR ADC B,DIR,X ADC B,ABL ADC B,ABL,X ADC B,ABS ADC B,ABS,X INSTRUCTION CODE TABLE 12 (The first word’s code of each instruction is B116) D3–D0 Hexadecimal D7–D4 notation 0000 0 0001 1 0010 2 TBD,0 IMP TBD,1 IMP TBD,2 IMP TBD,3 IMP TDB,0 IMP TDB,1 IMP TDB,2 IMP TDB,3 IMP TBS IMP TSB IMP 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F ADCB B,IMM SBCB B,IMM ADC B,IMM SBC B,IMM 20-60 7905 Group User ’ s Manual Rev.1.0 APPENDIX Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE 13 (The first word’s code of each instruction is C116) D3–D0 Hexadecimal D7–D4 notation 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F LSR,#n A ROR,#n A ASL,#n A ROL,#n A ASR,#n A DEBNE DIR/IMM,REL INSTRUCTION CODE TABLE 14 (The first word’s code of each instruction is D116) D3–D0 Hexadecimal D7–D4 notation 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F LSRD,#n E RORD,#n E ASLD,#n E ROLD,#n E ASRD,#n E DEBNE ABS/IMM,REL 7905 Group User ’ s Manual Rev.1.0 20-61 APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Note: F or an instruction of which “Operation length (Bit)” = 16/8 is executed in the bit length described below. • 16-bit length when m = 0 or x = 0. • 8-bit length when m = 1 or x = 1. For an instruction of which “Operation length (Bit)” = 8 or 32 is executed in 8-bit or 32-bit length regardless of the contents of flags m and x. 20-62 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Symbol IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK Multiplied accumulation op n # C Z I D x m V N IPL + – ✕ ÷ Description Implied addressing mode Immediate addressing mode Accumulator addressing mode Direct addressing mode Direct indexed X addressing mode Direct indexed Y addressing mode Direct indirect addressing mode Direct indexed X indirect addressing mode Direct indirect indexed Y addressing mode Direct indirect long addressing mode Direct indirect long indexed Y addressing mode Absolute addressing mode Absolute indexed X addressing mode Absolute indexed Y addressing mode Absolute long addressing mode Absolute long indexed X addressing mode Absolute indirect addressing mode Absolute indirect long addressing mode Absolute indexed X indirect addressing mode Stack addressing mode Relative addressing mode Direct bit relative addressing mode Absolute bit relative addressing mode Stack pointer relative addressing mode Stack pointer relative indirect indexed Y addressing mode Block transfer addressing mode Multiplied accumulation addressing mode Instruction code (Op code) Number of cycles Number of bytes Carry flag Zero flag Interrupt disable flag Decimal operation mode flag Index register length selection flag Data length selection flag Overflow flag Negative flag Processor interrupt priority level Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Absolute value Negation Movement to the arrow direction Movement to the arrow direction Exchange Accumulator Accumulator’s high-order 8 bits Accumulator’s low-order 8 bits Accumulator A Accumulator A’s high-order 8 bits Accumulator A’s low-order 8 bits Accumulator B Accumulator B’s high-order 8 bits Accumulator B’s low-order 8 bits Symbol E EH EL X XH XL Y YH YL S REL PC PCH PCL PG DT DPR0 DPR0H DPR0L DPRn DPRnH DPRnL PS PSH PSL PSL(bit n) M M(S) M(bit n) Mn IMM IMMn IMMH IMML ADH ADM ADL EAR EARH EARL imm immn dd i i1, i2 source dest Description Accumulator E Accumulator E’s high-order 16 bits (Accumulator B) Accumulator E’s low-order 16 bits (Accumulator A) Index register X Index register X’s high-order 8 bits Index register X’s low-order 8 bits Index register Y Index register Y’s high-order 8 bits Index register Y’s low-order 8 bits Stack pointer Relative address Program counter Program counter’s high-order 8 bits Program counter’s low-order 8 bits Program bank register Data back register Direct page register 0 Direct page register 0’s high-order 8 bits Direct page register 0’s low-order 8 bits Direct page register n Direct page register n’s high-order 8 bits Direct page register n’s low-order 8 bits Processor status register Processor status register’s high-order 8 bits Processor status register’s low-order 8 bits nth bit in processor status register Contents of memory Contents of memory at address indicated by stack pointer nth bit of memory n-bit memory’s address or contents Immediate value (8 bits or 16 bits) n-bit immediate value 16-bit immediate value’s high-order 8 bits 16-bit immediate value’s low-order 8 bits Value of 24-bit address’s high-order 8 bits (A23–A16) Value of 24-bit address’s middle-order 8 bits (A15–A8) Value of 24-bit address’s low-order 8 bits (A7–A0) Effective address (16 bits) Effective address’s high-order 8 bits Effective address’s low-order 8 bits 8-bit immediate value n-bit immediate value Displacement for DPR (8 bits or 16 bits) Number of transfer bytes, rotation or repeated operations Number of registers pushed or pulled Operand to specify transfer source Operand to specify transfer destination ∨ ∨ ∀ ||  → ← ⇔ Acc AccH AccL A AH AL B BH BL 7905 Group User’s Manual Rev.1.0 20-63 APPENDIX Appendix 6. Machine instructions 7900 Series Machine Instructions Addressing Modes Symbol Function Acc← | Acc | IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y length (Bit) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 16/8 E1 3 1 81 4 2 E1 ABSD E← | E | 32 31 5 2 90 Operation ABS (Note 1) ADC Acc←Acc + M + C (Notes 1 and 2) AccL←AccL + IMM8 + C 16/8 31 3 3 87 B1 3 3 87 21 5 3 21 6 3 8A 8B A1 7 3 A1 8 3 8A 8B 21 7 3 21 8 3 21 8 3 21 9 3 21 10 3 80 81 88 82 89 A1 9 3 A1 10 3 A1 10 3 A1 11 3 A1 12 3 89 80 81 88 82 ADCB (Note 1) 8 31 3 3 1A B1 3 3 1A ADCD E←E + M32 + C 32 31 4 6 1C 21 7 3 21 8 3 9A 9B 21 9 3 21 10 3 21 10 3 21 11 3 21 12 3 99 90 91 98 92 ADD Acc←Acc + M (Notes 1 and 2) AccL←AccL + IMM8 16/8 26 1 2 81 2 3 26 2A 3 2 2B 4 2 81 4 3 81 5 3 2B 2A 11 6 3 11 7 3 11 7 3 11 8 3 11 9 3 29 20 21 28 22 91 6 3 91 7 3 91 7 3 91 8 3 91 9 3 20 21 28 22 29 ADDB (Note 1) 8 29 1 2 81 2 3 29 ADDD E←E + M32 32 2D 3 5 9A 6 2 9B 7 2 11 9 3 11 10 3 11 10 3 11 11 3 11 12 3 90 91 98 92 99 ADDM (Note 3) M←M + IMM 16/8 51 7 4 03 ADDMB M8←M8 + IMM8 8 51 7 4 02 ADDMD M32←M32 + IMM32 32 51 10 7 83 ADDS S←S + IMM8 16 31 2 3 0A ADDX X←X + IMM (IMM = 0 to 31) 16/8 01 2 2 ADDY (Note 4) Y←Y + IMM (IMM = 0 to 31) 16/8 01 2 2 20 + imm 20-64 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C • • • 0V • • •• Z0 • • • 0V • • •• Z0 21 5 4 21 6 4 21 6 4 21 6 5 21 7 5 86 8E 8F 8C 8D A1 7 4 A1 8 4 A1 8 4 A1 8 5 A1 9 5 8E 8F 86 8C 8D 21 6 3 21 9 3 84 83 A1 8 3 A1 11 3 83 84 • • • NV • • • • ZC • • • NV • • •• Z C 21 7 4 21 8 4 21 8 4 21 8 5 21 9 5 9F 96 9C 9E 9D 21 8 3 21 11 3 93 94 • • • NV • • • • ZC 2E 3 3 2F 4 3 11 5 4 11 5 5 11 6 5 26 2C 2D 81 4 4 81 5 4 91 5 4 91 5 5 91 6 5 26 2E 2F 2C 2D 11 5 3 11 8 3 93 24 91 5 3 91 8 3 23 24 • • • NV • • • • ZC • • • NV • • •• ZC 9E 6 3 9F 7 3 11 8 4 11 8 5 11 9 5 96 9C 9D 11 8 3 11 11 3 93 94 • • • NV • • •• ZC 51 7 5 07 • • • NV • • • • ZC 51 7 5 06 • • • NV • • •• ZC 51 10 8 87 • • • NV • • •• ZC • • • NV • • • • ZC • • • NV • • •• ZC • • • NV • • • • ZC 7905 Group User’s Manual Rev.1.0 20-65 APPENDIX Appendix 6. Machine instructions Addressing Modes Symbol Function IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y length (Bit) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 16/8 66 1 2 81 2 3 66 8 23 1 2 81 2 3 23 ANDM (Note 3) M←M IMM 6A 3 2 6B 4 2 81 4 3 81 5 3 6A 6B 11 6 3 11 7 3 11 7 3 11 8 3 11 9 3 60 61 68 62 69 91 6 3 91 7 3 91 7 3 91 8 3 91 9 3 62 69 60 61 68 Operation AND Acc←Acc M (Notes 1 and 2) AccL←AccL IMM8 ANDB (Note 1) ANDMB M8←M8 IMM8 ANDMD M32←M32 IMM32 ASL (Note 1) Arithmetic shift to the left by 1 bit m=0 Acc or M16 C ← b15 … b0 ← 0 m=1 AccL or M8 C ← b 7 … b0 ← 0 ASL #n (Note 4) Arithmetic shift to the left by n bits (n = 0 to 15) m=0 A C ← b15 … b0 ← 0 m=1 AL C ← b 7 … b0 ← 0 ASLD #n (Note 4) Arithmetic shift to the left by n bits (n = 0 to 31) E C ← b31 … b0 ← 0 Arithmetic shift to the right by 1 bit m=0 Acc or M16 → b15 … b0 → C m=1 AccL or M8 → b7 … b0 → C ASR (Note 1) ASR #n (Note 4) Arithmetic shift to the right by n bits (n = 0 to 15) m=0 A → b15 … b0 → C AL → b7 … b0 → C m=1 20-66 ∨ ∨ ∨ ∨ ∨ 16/8 51 7 4 63 8 51 7 4 62 32 51 10 7 E3 16/8 03 1 1 21 7 3 21 8 3 0B 0A 81 2 2 03 16/8 C1 6 2 40 + + imm imm 32 D1 8 2 40 + + imm imm 64 1 1 21 7 3 21 8 3 4A 4B 16/8 81 2 2 64 16/8 C1 6 2 80 + + imm imm 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C 6E 3 3 6F 4 3 11 5 4 11 5 5 11 6 5 66 6C 6D 81 4 4 81 5 4 91 5 4 91 5 5 91 6 5 6E 6F 66 6C 6D 11 5 3 11 8 3 63 64 91 5 3 91 8 3 63 64 • • •N• • • •• Z• • • •N• • • •• Z• 51 7 5 67 • • •N• • • •• Z • 51 7 5 66 • • •N• • • •• Z • 51 10 8 E7 • • •N• • • •• Z• 21 7 4 21 8 4 0E 0F • • •N• • • •• ZC • • •N• • • •• ZC • • •N• • • •• ZC 21 7 4 21 8 4 4E 4F • • •N• • • •• ZC • • • N• • • •• ZC 7905 Group User’s Manual Rev.1.0 20-67 APPENDIX Appendix 6. Machine instructions Addressing Modes Symbol Function IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y length (Bit) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 32 D1 8 2 80 + + imm imm Operation ASRD #n (Note 4) Arithmetic shift to the right by n bits (n = 0 to 31) E → b31 … b0 ← C if M(bit n) = 0 then PC←PC + cnt + REL (–128 to +127) (cnt: Number of bytes of instruction) if M8(bit n) = 0 then PC←PC + cnt + REL (–128 to +127) (cnt: Number of bytes of instruction) if M(bit n) = 1 then PC←PC + cnt + REL (–128 to +127) (cnt: Number of bytes of instruction) if M8(bit n) = 1 then PC←PC+cnt+REL (–128 to +127) (cnt: Number of bytes of instruction) if C = 0 then PC←PC + 2 + REL (–128 to +127) BBC (Note 3) 16/8 BBCB 8 BBS (Note 3) 16/8 BBSB 8 BCC – BCS if C = 1 then PC←PC + 2 + REL (–128 to +127) – BEQ if Z = 1 then PC←PC + 2 + REL (–128 to +127) if N∀V = 0 then PC←PC + 2 + REL (–128 to +127) if Z = 0 and N∀V = 0 then PC←PC + 2 + REL (–128 to +127) – BGE – BGT – BGTU if C = 1 and Z = 0 then PC←PC + 2 + REL (–128 to +127) if Z = 1 or N∀V = 1 then PC←PC + 2 + REL (–128 to +127) – BLE – BLEU if C = 0 or Z = 1 then PC←PC + 2 + REL(–128 to +127) if N∀V = 1 then PC←PC + 2 + REL (–128 to +127) – BLT – 20-68 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C • • •N• • • •• ZC 41 9 5 41 9 6 5A 5E • • • • • • • •• • • 52 8 4 57 8 5 • • • • • • • •• • • 41 9 5 41 9 6 4A 4E • • • • • • • •• • • 42 8 4 47 8 5 • • • • • • • •• • • 90 6 2 • • • • • • • •• • • B0 6 2 • • • • • • • •• • • F0 6 2 • • • • • • • •• • • C0 6 2 • • • • • • • •• • • 80 6 2 • • • • • • • •• • • 40 6 2 • • • • • • • •• • • A0 6 2 • • • • • • • •• • • 60 6 2 • • • • • • • •• • • E0 6 2 • • • • • • • •• • • 7905 Group User’s Manual Rev.1.0 20-69 APPENDIX Appendix 6. Machine instructions Addressing Modes Symbol Function IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y length (Bit) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # – Operation BMI if N = 1 then PC←PC + 2 + REL (–128 to +127) BNE if Z = 0 then PC←PC + 2 + REL (–128 to +127) – BPL if N = 0 then PC←PC + 2 + REL (–128 to +127) PC←PC + cn t + REL (BRA:–128 to +127, BRAL: –32768 to +32767) (cnt: Number of bytes of instruction) PG←PG + 1 (When carry occurs) PG←PG – 1 (When borrow occurs) PC←PC + 2 M(S)←PG S←S – 1 M(S)←PCH S←S – 1 M(S)←PCL S←S – 1 M(S)←PSH S←S – 1 M(S)←PSL S←S – 1 I←1 PCL←ADL PCH←ADM PG←0016 or FF16 if A(bit n) or M(bit n) = 0 (n = 0 to 15), then PC←PC + cnt + REL (–128 to +127) (cnt: Number of bytes of instruction) (S)←PC + 2 PC←PC + 2 + REL (–1024 to +1023) – BRA/BRAL (Note 5) – BRK (Note 6) – 00 15 2 74 BSC (Note 7) 16/8 01 7 3 71 11 4 A0 A0 + + n n BSR – BSS (Note 7) if A(bit n) or M(bit n) = 1 (n = 0 to 15), then PC←PC + cnt + REL (–128 to +127) (cnt: Number of bytes of instruction) if V = 0 then PC←PC + 2 + REL (–128 to +127) 16/8 01 7 3 71 11 4 80 80 + + n n BVC – BVS if V = 1 then PC←PC + 2 + REL (–128 to +127) – 20-70 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C 30 6 2 • • • • • • • •• • • D0 6 2 • • • • • • • •• • • 10 6 2 • • • • • • • •• • • 20 5 2 • • • • • • • •• • • A7 5 3 • • • • • • • •1 • • 71 10 5 E + n F8 7 2 | FF • • • • • • • •• • • • • • • • • • •• • • 71 10 5 C0 + n 50 6 2 • • • • • • • •• • • • • • • • • • •• • • 70 6 2 • • • • • • • •• • • 7905 Group User’s Manual Rev.1.0 20-71 APPENDIX Appendix 6. Machine instructions Addressing Modes Symbol Function IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y length (Bit) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 16/8 A6 6 3 41 9 5 6A 81 7 4 A6 8 A2 6 3 62 8 4 81 7 4 A2 16/8 B6 6 3 41 9 5 7A 81 7 4 B6 8 B2 6 3 72 8 4 81 7 4 B2 – 14 1 1 Operation if Acc = IMM or M = IMM CBEQ (Notes 1 and then PC←PC + cnt + REL(–128 to +127) 3) (cnt: Number of bytes of instruction) CBEQB (Note 1) if AccL = IMM8 or M8 = IMM8 then PC←PC + cnt + REL (–128 to +127) (cnt: Number of bytes of instruction) CBNE if Acc ≠ IMM or M ≠ IMM (Notes 1 and then PC←PC + cnt + REL (–128 to 3) +127) (cnt: Number of bytes of instruction) CBNEB (Note 1) if AccL ≠ IMM8 or M8 ≠ IMM8 then PC←PC+cnt+REL(–128 to +127) (cnt: Number of bytes of instruction) C←0 CLC CLI I←0 – 15 3 1 CLM m←0 – 45 3 1 CLP PSL(bit n)←0 (n = 0 to 7. Multiple bits can be specified.) – 98 4 2 CLR (Note 1) Acc←0 16/8 54 1 1 81 2 2 54 CLRB (Note 1) AccL←0016 8 44 1 1 81 2 2 44 CLRM M←0 16/8 D2 5 2 CLRMB M8←0016 8 C2 5 2 CLRX X← 0 16/8 E4 1 1 CLRY Y← 0 16/8 F4 1 1 20-72 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C • • • NV • • •• Z C • • • NV • • •• Z C • • • NV • • •• Z C • • • NV • • •• Z C • • • • • • • •• • 0 • • • • • • • •0 • • • • • • • 0• •• • • • • • Specified flag becomes “0.” • • •0• • • •• 1 • • • •0• • • •• 1 • D7 5 3 • • • • • • • •• • • C7 5 3 • • • • • • • •• • • • • •0• • • •• 1 • • • •0• • • •• 1 • 7905 Group User’s Manual Rev.1.0 20-73 APPENDIX Appendix 6. Machine instructions Addressing Modes Symbol V← 0 Function IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y length (Bit) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # – 65 1 1 Operation CLV CMP Acc – M (Notes 1 and 2) 16/8 46 1 2 81 2 3 46 4A 3 2 4B 4 2 81 4 3 81 5 3 4A 4B 11 6 3 11 7 3 11 7 3 11 8 3 11 9 3 40 49 41 48 42 91 6 3 91 7 3 91 7 3 91 8 3 91 9 3 49 48 40 41 42 CMPB (Note 1) AccL – IMM8 8 38 1 2 81 2 3 38 CMPD E – M32 32 3C 3 5 BA 6 2 BB 7 2 11 9 3 11 10 3 11 10 3 11 11 3 11 12 3 B0 B1 B8 B2 B9 CMPM (Note 3) M – IMM 16/8 51 5 4 23 CMPMB M8 – IMM8 8 51 5 4 22 CMPMD M32 – IMM32 32 51 7 7 A3 CPX (Note 8) X–M 16/8 E6 1 2 22 3 2 CPY (Note 8) Y–M 16/8 F6 1 2 32 3 2 DEBNE (Note 4) M←M – IMM(IMM = 0 to 31) if M ≠ 0, then PC←PC + cnt + REL (–128 to +127) (cnt: Number of bytes of instruction) Acc←Acc – 1 or M ←M – 1 X←X – 1 16/8 C1 12 4 A0 + imm B3 1 1 92 6 2 41 8 3 9B 81 2 2 B3 DEC (Note 1) 16/8 DEX 16/8 E3 1 1 DEY Y←Y – 1 16/8 F3 1 1 DIV (Notes 2, 9, and 10) A (quotient) ← (B, A) ÷ M B (remainder) 16/8 31 15 3 E7 21 16 3 21 17 3 EA EB 21 18 3 21 19 3 21 19 3 21 20 3 21 21 3 E0 E1 E8 E2 E9 20-74 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C • • • •0 • • •• • • 4E 3 3 4F 4 3 11 5 4 11 5 5 11 6 5 46 4D 4C 81 4 4 81 5 4 91 5 4 91 5 5 91 6 5 4E 4F 46 4C 4D 11 5 3 11 8 3 43 44 91 5 3 91 8 3 43 44 • • • NV • • •• Z C • • • NV • • •• Z C BE 6 3 BF 7 3 11 8 4 11 8 5 11 9 5 B6 BC BD 11 8 3 11 11 3 B3 B4 • • • NV • • • • Z C 51 5 5 27 • • • NV • • • • Z C 51 5 5 26 • • • NV • • • • Z C 51 7 8 A7 • • • NV • • •• Z C 41 4 4 2E • • • NV • • • • Z C 41 4 4 3E • • • NV • • •• Z C D1 11 5 E0 + imm 97 6 3 41 8 4 9F • • • • • • • •• • • • • •N• • • •• Z • • • •N• • • •• Z • • • •N• • • •• Z • 21 16 4 21 17 4 21 17 4 21 17 5 21 18 5 EE EF E6 EC ED 21 17 3 21 20 3 E3 E4 • • • NV • • • I Z C 7905 Group User’s Manual Rev.1.0 20-75 APPENDIX Appendix 6. Machine instructions Addressing Modes Symbol Function A (quotient) ←(B, A) ÷ M B (remainder) (Signed) IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y length (Bit) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 16/8 31 22 3 F7 21 23 3 21 24 3 FA FB 21 25 3 21 26 3 21 26 3 21 27 3 21 28 3 F0 F1 F8 F2 F9 Operation DIVS (Notes 2, 9, and 10) DXBNE (Note 4) X←X – IMM (IMM = 0 to 31) if X ≠ 0, then PC←PC + cnt + REL (–128 to +127) (cnt: Number of bytes of instruction) Y←Y – IMM (IMM = 0 to 31) if Y≠0, then PC←PC + cnt + REL (–128 to +127) (cnt: Number of bytes of instruction) 16/8 01 7 3 C0 + imm 01 7 3 E0 + imm 76 1 2 81 2 3 76 7A 3 2 7B 4 2 81 4 3 81 5 3 7A 7B 11 6 3 11 7 3 11 7 3 11 8 3 11 9 3 70 71 78 79 72 91 6 3 91 7 3 91 7 3 91 8 3 91 9 3 72 70 71 78 79 DYBNE (Note 4) 16/8 EOR Acc←Acc∀M (Notes 1 and 2) AccL←AccL∀IMMB 16/8 EORB (Note 1) 8 33 1 2 81 2 3 33 EORM (Note 3) M←M∀IMM 16/8 51 7 4 73 EORMB M8←M8∀IMM8 8 51 7 4 72 EORMD M32←M32∀IMM32 32 51 10 7 F3 EXTS (Note 1) Acc ←AccL (Extension sign) (Bit 7 of AccL = 0) b15 b7 b0 00000000 0 AccH AccL (Bit 7 of AccL = 1) b15 b7 b0 11111111 1 AccH AccL E←EL(= A) (Extension sign) (Bit 15 of A = 0) b15 b0 b15 b0 000016 0 EH(B) EL(A) (Bit 15 of A = 1) b15 b0 b15 b0 FFFF16 1 EL(A) EH(B) 16 35 1 1 81 2 2 35 EXTSD 32 31 5 2 B0 EXTZ (Note 1) Acc ← AccL (Extension zero) b15 b8 b7 b0 00000000 AccH AccL E←EL(= A) (Extension zero) b15 b0 b15 b0 000016 EL(A) EH(B) 16 34 1 1 81 2 2 34 EXTZD 32 31 3 2 A0 20-76 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C 21 23 4 21 24 4 21 24 4 21 24 5 21 25 5 FE FF F6 FC FD 21 24 3 21 27 3 F3 F4 • • • NV • • • I Z C • • • • • • • •• • • • • • • • • • •• • • 7E 3 3 7F 4 3 11 5 4 11 5 5 11 6 5 76 7C 7D 81 4 4 81 5 4 91 5 4 91 5 5 91 6 5 7E 7F 76 7C 7D 11 5 3 11 8 3 73 74 91 5 3 91 8 3 73 74 • • •N• • • •• Z • • • •N• • • •• Z • 51 7 5 77 • • •N• • • •• Z • 51 7 5 76 • • •N• • • •• Z • 51 10 8 F7 • • •N• • • •• Z • • • •N• • • •• Z • • • •N• • • •• Z • • • •0• • • •• Z • • • •0• • • •• Z • 7905 Group User’s Manual Rev.1.0 20-77 APPENDIX Appendix 6. Machine instructions Addressing Modes Symbol Function Acc←Acc + 1 or M ←M + 1 X←X + 1 IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y length (Bit) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # A3 1 1 82 6 2 41 8 3 16/8 8B 81 2 2 A3 16/8 C3 1 1 Operation INC (Note 1) INX INY Y←Y + 1 16/8 D3 1 1 JMP/JMPL When ABS specified PCL←ADL PCH←ADM When ABL specified PCL←ADL PCH←ADM PG←ADH When (ABS) specified PCL←(ADM, ADL) PCH←(ADM, ADL + 1) When L(ABS) specified PCL←(ADM, ADL) PCH←(ADM, ADL + 1) PG←(ADM, ADL + 2) When (ABS,X) specified PCL←(ADM, ADL + X) PCH←(ADM, ADL + X + 1) – JSR/JSRL When ABS specified PC←PC + 3 M(S)←PCH S←S–1 M(S)←PCL S←S–1 PCL←ADL PCH←ADM When ABL specified PC←PC + 4 M(S)←PG S←S – 1 M(S)←PCH S←S – 1 M(S)←PCL S←S – 1 PCL←ADL PCH←ADM PG←ADH When (ABS,X) specified PC←PC + 3 M(S)←PCH S←S – 1 M(S)←PCL S←S – 1 PCL←(ADM, ADL + X) PCH←(ADM, ADL + X + 1) – LDA Acc←M (Notes 1 and 2) LDAB (Note 1) Acc←M8 (Extension zero) 16/8 16 1 2 81 2 3 16 28 1 2 81 2 3 28 1A 3 2 1B 4 2 81 4 3 81 5 3 1A 1B 0A 3 2 0B 4 2 81 4 3 81 5 3 0A 0B 16 11 6 3 11 7 3 18 6 2 11 8 3 19 8 2 11 12 10 91 6 3 91 7 3 81 7 3 91 8 3 81 9 3 19 10 11 18 12 11 6 3 11 7 3 08 6 2 11 8 3 09 8 2 00 01 02 91 6 3 91 7 3 81 7 3 91 8 3 81 9 3 00 01 08 09 02 20-78 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C 87 6 3 41 8 4 8F • • •N• • • •• Z • • • •N• • • •• Z • • • •N• • • •• Z• 9C 4 3 AC 5 4 31 7 4 31 9 4 BC 7 3 5C 5D • • • • • • • •• • • 9D 6 3 AD 7 4 BD 8 3 • • • • • • • •• • • 1E 3 3 1F 4 3 11 5 4 1C 4 4 1D 5 4 16 81 4 4 81 5 4 91 5 4 81 5 5 81 6 5 1E 1F 16 1C 1D 0E 3 3 0F 4 3 11 5 4 0C 4 4 0D 5 4 06 81 4 4 81 5 4 91 5 4 81 5 5 81 6 5 0E 0F 06 0C 0D 11 5 3 11 8 3 13 14 91 5 3 91 8 3 13 14 11 5 3 11 8 3 04 03 91 5 3 91 8 3 03 04 • • •N• • • •• Z • • • •0• • • •• Z • 7905 Group User’s Manual Rev.1.0 20-79 APPENDIX Appendix 6. Machine instructions Addressing Modes Symbol E←M32 Function IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y length (Bit) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 32 2C 3 5 8A 6 2 8B 7 2 11 9 3 11 10 3 88 9 2 11 11 3 89 11 2 80 81 82 Operation LDAD LDD n (Notes 11 and 12) DPRn←IMM16 (n = 0 to 3. Multiple DPRs can be specified.) 16 B8 13 4 ?0 B8 11 2 ?0 + + 2i 2i LDT DT←IMM8 8 31 4 3 4A LDX (Note 8) X← M 16/8 C6 1 2 02 3 2 41 5 3 05 LDXB X←IMM8 (Extension zero) 16 27 1 2 LDY (Note 8) Y←M 16/8 D6 1 2 12 3 2 41 5 3 1B LDYB Y←IMM8 (Extension zero) 16 37 1 2 LSR (Note 1) Logical shift to the right by 1 bit m=0 Acc or M16 0→ b15 … b0 →C m=1 AccL or M8 0→ b7 … b0 →C 16/8 43 1 1 21 7 3 21 8 3 2A 2B 81 2 2 43 LSR #n (Note 4) Logical shift to the right by n bits (n = 0 to 15) m=0 A 0→ b15 … b0 →C m=1 AL 0→ b7 … b0 →C 16/8 C1 6 2 + imm LSRD #n (Note 4) Logical shift to the right by n bits (n = 0 to 31) E 0→ b31 … b0 →C 32 D1 8 2 + imm 20-80 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C 8E 6 3 8F 7 3 11 8 4 8C 7 4 8D 8 4 86 11 8 3 11 11 3 83 84 • • •N• • • •• Z • •• ••• •• •••• •• ••• •• •••• 07 3 3 41 5 4 06 • • •N• • • •• Z • • • •0• • • •• Z • 17 3 3 41 5 4 1F • • •N• • • •• Z • • • •0• • • •• Z • 21 7 4 21 8 4 2E 2F • • • 0• • • •• ZC • • • 0 • • • •• ZC • • •0• • • •• ZC 7905 Group User’s Manual Rev.1.0 20-81 APPENDIX Appendix 6. Machine instructions Destination Symbol Function Operation length (Bit) 16/8 IMM DIR IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 86 5 3 31 7 4 47 58 6 3 MOVM (Note 2) m=0 M16(dest)←M16(source) m=1 M8(dest)←M8(source) Source DIR, X ABS ABS, X 5C 6 4 5D 7 4 A9 5 3 31 7 4 3A 48 6 3 MOVMB M8(dest)←M8(source) 8 IMM DIR Source DIR, X ABS ABS, X 4C 6 4 4D 7 4 61 3 2 10 + + + 5n 2n n 61 3 2 50 + + + 6n 2n n MOVR m=0 (Notes 7 and M16(dest1) ←M16(source1) 13) M16(dest n)←M16(source n) m=1 M8(dest1) ←M8(source1) 16/8 IMM Source M8(dest n)←M8(source n) (n = 0 to 15) MOVRB (Note 7) M8(dest1) ←M8(source1) M8(dest n)←M8(source n) (n = to 15) Source … … DIR … … … DIR, X ABS ABS, X 8 IMM 61 3 2 90 + + + 6n 3n n 71 3 2 10 + + + 6n 3n n 61 3 2 00 + + + 5n 2n n 61 3 2 40 + + + 6n 2n n … DIR DIR, X ABS 61 3 2 80 + + + 6n 3n n 71 3 2 00 + + + 6n 3n n ABS, X 20-82 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Destination Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C 96 4 4 31 6 5 57 78 5 4 79 6 4 7C 5 5 • • • • • • • •• • • B9 4 4 31 6 5 3B 68 5 4 69 6 4 6C 5 5 • • • • • • • •• • • 61 3 2 30 + + + 4n 3n n 61 3 2 70 + + + 5n 3n n 71 3 2 70 + + + 6n 3n n 61 3 2 B0 + + + 5n 4n n • • • • • • • •• • • 61 3 2 20 + + + 4n 3n n 61 3 2 60 + + + 5n 3n n 71 3 2 60 + + + 6n 3n n 61 3 2 A0 + + + 5n 4n n • • • • • • • •• •• 7905 Group User’s Manual Rev.1.0 20-83 APPENDIX Appendix 6. Machine instructions Addressing Modes Symbol Function IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y length (Bit) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 16/8 31 8 3 C7 21 9 3 21 10 3 CB CA 21 11 3 21 12 3 21 12 3 21 13 3 21 14 3 C0 C1 C8 C2 C9 Operation (B, A)←A ✕ M MPY (Notes 2 and 14) MPYS (B, A)←A ✕ M (Signed) (Notes 2 and 14) M(Y + k)←M(X + k) k = 0 to i – 1 i: Number of transfer bytes specified by accumulator A M(Y–k)←M(X–k) k = 0 to i–1 i: Number of transfer bytes specified by accumulator A Acc← –Acc 16/8 31 8 3 D7 21 9 3 21 10 3 DB DA 21 11 3 21 12 3 21 12 3 21 13 3 21 14 3 D0 D1 D8 D2 D9 MVN (Note 15) 16/8 ( MVP (Note 16) ) 16/8 ( NEG (Note 1) ) 16/8 24 1 1 81 2 2 24 NEGD E← –E 32 31 4 2 80 NOP PC←PC + 1 When catty occurs in PC PG←PG + 1 – 74 1 1 ORA Acc←Acc∨M (Notes 1 and 2) AccL←AccL∨IMM8 16/8 56 1 2 81 2 3 56 5A 3 2 5B 4 2 81 4 3 81 5 3 5A 5B 11 6 3 11 7 3 11 7 3 11 8 3 11 9 3 50 51 59 58 52 91 6 3 91 7 3 91 7 3 91 8 3 91 9 3 50 51 59 58 52 ORAB (Note 1) 8 63 1 2 81 2 3 63 ORAM (Note 3) M←M∨IMM 16/8 51 7 4 33 ORAMB M8←M8∨IMM8 8 51 7 4 32 ORAMD M32←M32∨IMM32 32 51 10 7 B3 PEA M(S)←IMMH S←S – 1 M(S)←IMML S←S – 1 M(S)←M((DPRn) + dd + 1) S←S + 1 M(S)←M((DPRn)+dd) S←S – 1 (n = 0 to 3) 16 PEI 16 20-84 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C 21 9 4 21 10 4 21 10 4 21 10 5 21 11 5 CC CE CF C6 CD 21 10 3 21 13 3 C3 C4 • • •N• • • •• Z0 21 9 4 21 10 4 21 10 4 21 10 5 21 11 5 DE D6 DD DF DC 21 10 3 21 13 3 D3 D4 • • •N• • • •• Z0 31 5 4 2B + 5i •• ••• •• •••• 31 9 4 2A + 5i •• ••• •• •••• • • • NV • • • • ZC • • • NV • • • • ZC • • • • • • • •• • • 5E 3 3 5F 4 3 11 5 4 11 5 5 11 6 5 56 5C 5D 81 4 4 81 5 4 91 5 4 91 5 5 91 6 5 5E 5F 56 5C 5D 11 5 3 11 8 3 54 53 91 5 3 91 8 3 54 53 • • •N• • • •• Z• • • •N• • • •• Z• 51 7 5 37 • • •N• • • •• Z• 51 7 5 36 • • •N• • • •• Z• 51 10 8 B7 • • •N• • • •• Z• 31 5 4 4C • • • • • • • •• • • 31 7 3 4B • • • • • • • •• • • 7905 Group User’s Manual Rev.1.0 20-85 APPENDIX Appendix 6. Machine instructions Addressing Modes Symbol Function EAR←PC + IMM16 M(S)←EARH S← S – 1 M(S)←EARL S← S – 1 m=0 M(S)←AH S← S – 1 M(S)←AL S← S – 1 m=1 M(S)←AL S← S – 1 PHB m=0 M(S)←BH S← S – 1 M(S)←BL S← S – 1 m=1 M(S)←BL S← S – 1 PHD M(S)←DPR0H S← S – 1 M(S)←DPR0L S← S – 1 M(S)←DPRnH S← S – 1 M(S)←DPRnL S← S – 1 16 16/8 IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y length (Bit) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 16 Operation PER PHA 16/8 PHD n (Note 11) 16 (n = 0 to 3) When multiple DPRs are specified, the above operations are repeated. M(S)←PG S← S – 1 PHG 8 PHLD n (Note 11) M(S)←DPRnH S← S – 1 M(S)←DPRnL S← S – 1 DPRn←IMM16 16 (n = 0 to 3) When multiple DPRs are specified, the above operations are repeated. PHP M(S)←PSH S←S – 1 M(S)←PSL S←S – 1 M(S)←DT S←S – 1 16 PHT 8 20-86 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C 31 6 4 4D •• ••• •• •••• 85 4 1 •• ••• •• •••• 81 5 2 85 •• ••• •• •••• 83 4 1 •• ••• •• •••• B8 12 2 01 0F •• ••• •• •••• B8 11 2 01 + | i 0F 31 4 2 60 •• ••• •• •••• B8 14 4 01 | 0F B8 11 2 01 + + | 3i 2i 0F A5 4 1 •• ••• •• •••• •• ••• •• •••• 31 4 2 40 •• ••• •• •••• 7905 Group User’s Manual Rev.1.0 20-87 APPENDIX Appendix 6. Machine instructions Addressing Modes Symbol Function IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y length (Bit) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 16/8 Operation PHX x=0 M(S)←XH S← S – 1 M(S)←XL S← S – 1 x=1 M(S)←XL S← S – 1 PHY x=0 M(S)←YH S← S – 1 M(S)←YL S← S – 1 x=1 M(S)←YL S← S – 1 16/8 PLA m=0 S← S + 1 AL←M(S) S← S + 1 AH←M(S) m=1 S← S + 1 AL←M(S) 16/8 PLB m=0 S← S + 1 BL←M(S) S← S + 1 BH←M(S) m=1 S← S + 1 BL←M(S) S←S + 1 DPR0L←M(S) S←S + 1 DPR0H←M(S) 16/8 PLD 16 PLD n S←S + 1 (Notes 11 and DPRnL←M(S) 12) S←S + 1 DPRnH←M(S) 16 (n = 0 to 3) When multiple DPRs are specified, the above operations are repeated. PLP (Note 22) S← S + 1 PSL←M(S) S← S + 1 PSH←M(S) S← S + 1 DT←M(S) 16 PLT 8 20-88 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C C5 4 1 •• ••• •• •••• E5 4 1 •• ••• •• •••• 95 4 1 • • •N• • • ••Z• 81 5 2 95 • • •N• • • ••Z• 93 5 1 •• ••• •• •••• 77 11 2 ?0 •• ••• •• •••• 77 8 2 ?0 + 3i B5 5 1 Value restored from stack 31 6 2 50 • • •N• • • ••Z• 7905 Group User’s Manual Rev.1.0 20-89 APPENDIX Appendix 6. Machine instructions Addressing Modes Symbol Function IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y length (Bit) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 16/8 Operation PLX x=0 S← S + 1 XL←M(S) S← S + 1 XH←M(S) x=1 S← S + 1 XL←M(S) PLY x=0 S←S + 1 YL←M(S) S←S + 1 YH←M(S) x=1 S←S + 1 YL←M(S) M(S to S – i + 1)←A, B, X… S←S – i i: Number of bytes corresponding to register pushed on stack A, B, X…←M(S + 1 to S + i) S←S + i i: Number of bytes corresponding to register restored from stack 16/8 PSH (Note 17) 16/8 PUL (Notes 18 and 22) 16/8 RLA (Note 3) Rotate to the left by n bits m=0 (n = 0 to 65535) 16/8 31 5 3 07 + n A ← b15 … b0 ← m=1 (n = 0 to 255) AL ← b 7 … b0 ← RMPA (Note 19) m=0 Repeat (B, A)←(B, A) + M(DT:X)✕ M(DT:Y) (Signed) X←X + 2 Y←Y + 2 i←i – 1 Until i = 0 m=1 Repeat (BL, AL)←(BL, AL)+M(DT,X) M(DT,Y) (Signed) X←X + 1 Y←Y + 1 i←i – 1 Until i = 0 i: Numder of repetitions (0 to 255) 16/8 20-90 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C D5 4 1 • • •N• • • ••Z • F5 4 1 • • •N• • • ••Z • A8 11 2 + 2i1 + i2 •• ••• •• •••• 67 13 2 + 3 i1 When the contents of PS is restored, this becomes the value. In the other cases, nothing changes. •• ••• •• •••• 31 5 3 • • • N V • • • • Z C 5A + 14 imm 7905 Group User’s Manual Rev.1.0 20-91 APPENDIX Appendix 6. Machine instructions Addressing Modes Symbol Function IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y length (Bit) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 16/8 13 1 1 21 7 3 21 8 3 1A 1B Operation ROL (Note 1) Rotate to the left by 1 bit m=0 Acc or M16 ← b15 … b0 ← C ← m=1 AccL or M8 ← b7 … b0 ← C ← 81 2 2 13 ROL #n (Note 4) Rotate to the left by n bits (n = 0 to 15) m=0 A ← b15 … b0 ← C ← m=1 AL ← b 7 … b0 ← C ← 16/8 C1 6 2 60 + + imm imm ROLD #n (Note 4) Rotate to the left by n bits (n = 0 to 31) E ← b31 … b0 ← C ← 32 D1 8 2 60 + + imm imm ROR (Note 1) Rotate to the right by 1 bit m=0 Acc or M16 → C → b15 … b0 → m=1 AccL or M8 → C → b 7 … b0 → 16/8 53 1 1 21 7 3 21 8 3 3B 3A 81 2 2 53 ROR #n (Note 4) Rotate to the right by n bits (n = 0 to 15) m=0 A → C → b15 … b0 → m=1 AL → C → b 7 … b0 → 16/8 C1 6 2 20 + + imm imm RORD #n (Note 4) Rotate to the right by n bits (n = 0 to 31) E → b31 … b0 → C → 32 D1 8 2 20 + + imm imm 20-92 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C 21 7 4 21 8 4 1E 1F • • •N• • • •• ZC • • •N• • • • • ZC • • •N• • • • • ZC 21 7 4 21 8 4 3E 3F • • •N• • • • • ZC • • •N• • • •• ZC • • •N• • • • • ZC 7905 Group User’s Manual Rev.1.0 20-93 APPENDIX Appendix 6. Machine instructions Addressing Modes Symbol S←S + 1 PSL←M(S) S←S + 1 PSH←M(S) S←S + 1 PCL←M(S) S←S + 1 PCH←M(S) S←S + 1 PG←M(S) S← S + 1 PCL←M(S) S← S + 1 PCH←M(S) S← S + 1 PG←M(S) Function IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y length (Bit) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # – F1 12 1 Operation RTI RTL – 94 10 1 RTLD n S← S + 1 (Notes 11 and DPRnL←M(S) 12) S← S + 1 DPRnH←M(S) S← S + 1 PCL←M(S) S← S + 1 PCH←M(S) S← S + 1 PG←M(S). (n = 0 to 3. Multiple DPRs can be specified.) RTS S←S + 1 PCL←M(S) S←S + 1 PCH←M(S) 16 – 84 7 1 S← S + 1 RTSD n (Notes 11 and DPRnL←M(S) S← S + 1 12) DPRnH←M(S) S← S + 1 PCL←M(S) S← S + 1 PCH←M(S), (n = 0 to 3. Multiple DPRs can be specified.) SBC Acc←Acc – M – C (Notes 1 and 2) AccL←AccL – IMM8 – C 16 16/8 31 3 3 A7 B1 3 3 A7 21 5 3 21 6 3 AA AB A1 7 3 A1 8 3 AA AB 21 7 3 21 8 3 21 8 3 21 9 3 21 10 3 A9 A0 A1 A8 A2 A1 9 3 A1 10 3 A1 10 3 A1 11 3 A1 12 3 A2 A9 A0 A1 A8 SBCB (Note 1) 8 31 3 3 1B B1 3 3 1B SBCD E←E – M32 – C 32 31 4 6 1D 21 7 3 21 8 3 BA BB 21 9 3 21 10 3 21 10 3 21 11 3 21 12 3 B0 B1 B2 B9 B8 SEC C←1 – 04 1 1 SEI I←1 – 05 4 1 20-94 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C Value restored from stack •• ••• •• •• •• 77 15 2 ?C •• ••• •• •••• 77 12 2 ?C + 3i •• ••• •• •••• 77 14 2 ?8 •• ••• •• •••• 77 11 2 ?8 + 3i 21 5 4 21 6 4 21 6 4 21 6 5 21 7 5 AE AF A6 AC AD A1 7 4 A1 8 4 A1 8 4 A1 8 5 A1 9 5 AE AF AD AC A6 21 6 3 21 9 3 A3 A4 A1 8 3 A1 11 3 A3 A4 • • • NV • • • • ZC • • • NV • • • • Z C 21 7 4 21 8 4 21 8 4 21 8 5 21 9 5 BE BF B6 BC BD 21 8 3 21 11 3 B3 B4 • • • NV • • • • Z C •• • •• •• •• •1 • • • • • • • •1•• 7905 Group User’s Manual Rev.1.0 20-95 APPENDIX Appendix 6. Machine instructions Addressing Modes Symbol m←1 Function IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y length (Bit) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # – 25 3 1 Operation SEM SEP PSL(bit n)←1 (n = 0, 1, 3 to 7. Multiple bits can be specified.) M←Acc – 99 3 2 STA (Note 1) 16/8 DA 4 2 DB 5 2 81 5 3 81 6 3 DA DB 11 7 3 11 8 3 D8 7 2 11 9 3 D9 9 2 D0 D1 D2 91 7 3 91 8 3 81 8 3 91 9 3 81 10 3 D0 D1 D8 D2 D9 11 7 3 11 8 3 C8 7 2 11 9 3 C9 9 2 C0 C1 C2 91 7 3 91 8 3 81 8 3 91 9 3 81 10 3 C0 C9 C1 C8 C2 11 9 3 11 10 3 E8 9 2 11 11 3 E9 11 2 E0 E1 E2 STAB (Note 1) M8←AccL 8 CA 4 2 CB 5 2 81 5 3 81 6 3 CA CB STAD M32←E 32 EA 6 2 EB 7 2 STP Oscillation stopped – 31 – 2 30 STX M←X 16/8 E2 4 2 41 6 3 F5 STY M←Y 16/8 F2 4 2 41 6 3 FB SUB Acc←Acc – M (Notes 1 and 2) AccL←AccL – IMM8 16/8 36 1 2 81 2 3 36 3A 3 2 3B 4 2 81 4 3 81 5 3 3A 3B 11 6 3 11 7 3 11 7 3 11 8 3 11 9 3 30 31 39 38 32 91 6 3 91 7 3 91 7 3 91 8 3 91 9 3 30 39 31 38 32 SUBB (Note 1) 8 39 1 2 81 2 3 39 SUBD E←E – M32 32 3D 3 5 AA 6 2 AB 7 2 11 9 3 11 10 3 11 10 3 11 11 3 11 12 3 A0 A1 A8 A2 A9 SUBM (Note 3) M←M – IMM 16/8 51 7 4 13 SUBMB M8←M8 – IMM8 8 51 7 4 12 SUBMD M32←M32 – IMM32 32 51 10 7 93 20-96 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C •• ••• 1• •••• • • • Specified flag becomes “1” (Note 21). DE 4 3 DF 5 3 11 6 4 DC 5 4 DD 6 4 D6 81 5 4 81 6 4 91 6 4 81 6 5 81 7 5 DE DF D6 DC DD CE 4 3 CF 5 3 11 6 4 CC 5 4 CD 6 4 C6 81 5 4 81 6 4 91 6 4 81 6 5 81 7 5 CE CF C6 CC CD EE 6 3 EF 7 3 11 8 4 EC 7 4 ED 8 4 E6 11 6 3 11 9 3 D3 D4 91 6 3 91 9 3 D3 D4 11 6 3 11 9 3 C3 C4 91 6 3 91 9 3 C3 C4 11 8 3 11 11 3 E3 E4 •• ••• •• •••• •• ••• •• •••• •• ••• •• •••• •• ••• •• •••• E7 4 3 •• ••• •• •••• F7 4 3 •• ••• •• •••• 3E 3 3 3F 4 3 11 5 4 11 5 5 11 6 5 36 3C 3D 81 4 4 81 5 4 91 5 4 91 5 5 91 6 5 3E 36 3C 3D 3F 11 5 3 11 8 3 33 34 91 5 3 91 8 3 33 34 • • • NV • • • • ZC • • • NV • • • • ZC AE 6 3 AF 7 3 11 8 4 11 8 5 11 9 5 A6 AC AD 11 8 3 11 11 3 A3 A4 • • • NV • • • • ZC 51 7 5 17 • • • NV • • • • Z C 51 7 5 16 • • • NV • • • • ZC 51 10 8 97 • • • NV • • • • ZC 7905 Group User’s Manual Rev.1.0 20-97 APPENDIX Appendix 6. Machine instructions Addressing Modes Symbol Function S←S – IMM8 IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y length (Bit) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 16 31 2 3 0B Operation SUBS SUBX (Note 4) X←X – IMM (IMM = 0 to 31) 16/8 01 2 2 40 + imm 01 2 2 60 + imm 31 3 2 n2 SUBY (Note 4) Y←Y – IMM (IMM = 0 to 31) 16/8 TAD n (Note 20) DPRn←A (n = 0 to 3) 16 TAS S←A 16 31 2 2 82 TAX X←A 16/8 C4 1 1 TAY Y←A 16/8 D4 1 1 TBD n (Note 20) DPRn←B (n = 0 to 3) 16 B1 3 2 n2 TBS S←B 16 B1 2 2 82 TBX X←B 16/8 81 2 2 C4 TBY Y←B 16/8 81 2 2 D4 TDA n (Note 20) A←DPRn (n = 0 to 3) 16/8 31 2 2 40 + n2 B1 2 2 40 + n2 31 2 2 73 TDB n (Note 20) B←DPRn (n = 0 to 3) 16/8 TDS S←DPR0 16 20-98 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C • • • NV • • • • ZC • • • NV • • • • ZC • • • NV • • • • ZC •• ••• •• •• •• •• ••• •• •••• • • •N• • • ••Z• • • •N• • • ••Z• •• ••• •• •••• •• ••• •• •••• • • •N• • • ••Z• • • •N• • • ••Z• • • •N• • • ••Z• • • •N• • • ••Z• •• ••• •• •••• 7905 Group User’s Manual Rev.1.0 20-99 APPENDIX Appendix 6. Machine instructions Addressing Modes Symbol A←S Function IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y length (Bit) op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 16/8 31 2 2 92 Operation TSA TSB B← S 16/8 B1 2 2 92 TSD DPR0←S 16 31 4 2 70 TSX X← S 16/8 31 2 2 F2 TXA A←X 16/8 A4 1 1 TXB B←X 16/8 81 2 2 A4 TXS S←X 16/8 31 2 2 E2 TXY Y←X 16/8 31 2 2 C2 TYA A←Y 16/8 B4 1 1 TYB B←Y 16/8 81 2 2 B4 TYX X←Y 16/8 31 2 2 D2 WIT CPU clock stopped – 31 – 2 10 XAB AB 20-100 → ← 16/8 55 2 1 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C • • •N• • • ••Z• • • •N• • • ••Z• •• ••• •• •••• • • •N• • • ••Z• • • •N• • • ••Z• • • •N• • • ••Z• •• ••• •• •••• • • •N• • • ••Z• • • •N• • • ••Z • • • •N• • • ••Z • • • •N• • • ••Z • •• ••• •• •••• • • •N• • • ••Z • 7905 Group User’s Manual Rev.1.0 20-101 APPENDIX Appendix 6. Machine instructions Notes for machine instructions table The table lists the minimum number of instruction cycles for each instruction. The number of cycle is changed by the following condition. • The value of the low-order bytes of DPR (DPRn L) The number of cycle of the addressing mode related with DPRn (n = 0 to 3) is applied when DPRn = 0. When DPRn ≠ 0 , add 1 to the number of cycles. • The number of bytes of instruction which fetched into the instruction queue buffer • The address at read and write of memory (either even or odd) • When the external area accessed in BYTE = Vcc level (at external data bus width 8 bits) • The number of wait Note 1. The op code at the upper row is used for accumulator A, and the op code at the lower row is used for accumulator B. Note 2. When handing 16-bit data with flag m = 0 in the immediate addressing mode, add 1 to the numder of bytes. Note 3. When handing 16-bit data with flag m = 0, add 1 to the numder of bytes. Note 4. Imm is the immediate value specified with an operand (imm = 0–31). Note 5. The op code at the upper row is used for branching in the range of –128 to +127, and the op code at the lower row is used for branching in the range of –32768 to +32767. Note 6. The BRK instruction is a instruction for debugger; it cannot be used. Note 7. Any value from 0 through 15 is placed in an “n.” Note 8. When handling 16-bit data with flag x = 0 in the immediate addressing mode, add 1 to the numder of bytes. Note 9. The number of cycles is the case of the 16-bit ÷ 8-bit operation. In the case of the 32-bit ÷ 16-bit operation, add 8 to the number of cycles. Note 10. When a zero division interrupt occurs, the number of cycles is 16 cycles. It is regardless of the data length. Note 11. When placing a value in any of DPRs, the op code at the upper row is applied. When placing values to multiple DPRs, the op code at the lower row is applied. The letter “i” represents the number of DPRn specified: 1 to 4. Note 12. A “?” indicates to the value of 4 bits which the bit corressing to the specified DPRn becomes “1.” Note 13. When the source is in the immediate addressing mode and flag m = 0, add n (n = 0 to 15) to the number of bytes. Note 14. The number of cycles of the case of the 8-bit ✕ 8 -bit operation. In the case of the 16-bit ✕ 16-bit operation, add 4 to the number of cycles. 20-102 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 6. Machine instructions Note 15. The number of cycles is the case where the number of bytes to be transferred (i) is even. When the number of bytes to be transferred (i) is odd, the number is calculated as; 5 ✕ i + 10 Note 16. The number of cycles is the case where the number of bytes to be transferred (i) is even. When the number of bytes to be transferred (i) is odd, the number is calculated as; 5 ✕ i + 14 Note that it is 10 cycles in the case of 1-byte thanster. Note 17. i 1 i s the number of registers to be stored among A, B, X, Y, DPR0, and PS. i 2 i s the number of registers to be stored between DT and PG. Note 18. Letter “i 1” indicates the number of registers to be restored. Note 19. The number of cycles is applied when flag m = “1.” When flag m=“0,” the number is calculated as; 18 ✕ i mm + 5 Note 20. Any value from 0 through 3 is placed in an “n” in op code.” 7905 Group User’s Manual Rev.1.0 20-103 APPENDIX Appendix 7. Countermeasure against noise Appendix 7. Countermeasure against noise General countermeasure examples against noise are described below. Although the effect of these countermeasure depends on each system. The user shall modify them according to the actual application and test them. 1. Short wiring length The wiring on a printed circuit board may function as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less possibility of noise insertion into the microcomputer. (1) Wiring for R ESET p in ______ Make the length of wiring connected to the RESET pin as short as possible. ______ In particular, connect a capacitor between the RESET pin and the Vss pin with the shortest possible wiring (within 20 mm). ______ ______ Reason: If noise is input to the RESET pin, the microcomputer restarts operation before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise M37905 M37905 Reset circuit Vss RESET Reset circuit Vss RESET Vss Vss Not acceptable Acceptable Fig. 2 Wiring for R ESET p in (2) Wiring for clock input/output pins q M ake the length of wiring connected to the clock input/output pins as short as possible. q M ake the length of wiring between the grounding lead of the capacitor, which is connected to the oscillator, and the Vss pin of the microcomputer, as short as possible (within 20 mm). q S eparate the Vss pattern for oscillation from all other Vss patterns. (See Figure 10.) Reason: The microcomputer’s operation synchronizes with a clock generated by the oscillation circuit. If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a malfunction or a program runaway. Also, if the noise causes a potential difference between the Vss level of the microcomputer and the Vss level of an oscillator, the correct clock will not be input in the microcomputer. ______ Noise M37905 M37905 XIN XOUT Vss XIN XOUT Vss Not acceptable Acceptable Fig. 3 Wiring for clock input/output pins 20-104 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 7. Countermeasure against noise (3) Wiring for MD0 and MD1 pins Connect MD0 and MD1 pins to the Vss pin (or Vcc pin) with the shortest possible wiring. Reason: The processor mode of the microcomputer is influenced by a potential at the MD0 and MD1 pins when the MD0 and MD1 pins and the Vss pin (or Vcc pin) are connected. If the noise causes a potential difference between the MD0 and MD1 pins and the Vss pin (or Vcc pin), the processor mode may become unstable. This may cause a microcomputer malfunction or a program runaway. M37905 MD1 MD0 Vss Noise M37905 MD1 MD0 Vss Not Acceptable Acceptable Fig. 4 Wiring for MD0 and MD1 pins 2. Connection of bypass capacitor between Vss and Vcc lines Connect an approximate 0.1 µ F bypass capacitor as follows: q C onnect a bypass capacitor between the Vss and Vcc pins, at equal lengths. q T he wiring connecting the bypass capacitor between the Vss and Vcc pins should be as short as possible. q Use thicker wiring for the Vss and Vcc lines than that for the other signal lines. Bypass capacitor Wiring pattern Wiring pattern Vss Vcc M37905 Fig. 5 Bypass capacitor between Vss and Vcc lines 7905 Group User ’ s Manual Rev.1.0 20-105 APPENDIX Appendix 7. Countermeasure against noise 3. Wiring for analog input pins, analog power source pins, etc. (1) Processing for analog input pins q Connect a resistor to the analog signal line, which is connected to an analog input pin, in series. Additionally, connect the resistor to the microcomputer as close as possible. q Connect a capacitor between the analog input pin and the AVss pin, as close to the AVss pin as possible. Reason: A s ignal which is input to the analog input pin is usually an output signal from a sensor. The sensor, which detects changes in status, is installed far from the microcomputer ’ s printed circuit board. Therefore, this long wiring between them becomes an antenna which picks up noise and feeds it into the microcomputer ’ s analog input pin. If a capacitor between an analog input pin and the AVss pin is grounded far away from the AVss pin, noise on the GND line may enter the microcomputer through the capacitor. Noise (Note 2) Acceptable M37905 ANi RI Thermistor Not acceptable Acceptable CI AVss Reference values RI : Approximate 100 Ω to 1000 Ω CI : Approximate 100 pF to 1000 pF Notes 1: Design an external circuit for the ANi pin so that charge/discharge is available within 1 cycle of φAD. 2: This resistor and thermistor are used to divide resistance. Fig. 6 Countermeasure example against noise for analog input pin using thermistor 20-106 7905 Group User ’ s Manual Rev.1.0 APPENDIX Appendix 7. Countermeasure against noise (2) Processing for analog power source pins, etc. q U se independent power sources for the Vcc, AVcc and V REF p ins. q I nsert capacitors between the AVcc and AVss pins, and between the V REF a nd AVss pins. Reasons: P revents the A-D converter and D-A converter from noise on the Vcc line. M37905 AVcc VREF C1 AVss ANi (sensor, etc.) C2 Note : Connect capacitors using the thickest, shortest wiring possible. Reference values C1 ≥ 0.47 µF C2 ≥ 0.47 µF Fig. 7 Processing for analog power source pins, etc. 7905 Group User ’ s Manual Rev.1.0 20-107 APPENDIX Appendix 7. Countermeasure against noise 4. Oscillator protection The oscillator, which generates the basic clock for the microcomputer operations, must be protected from the affect of other signals. (1) Distance oscillator from signal lines with large current flows Install the microcomputer, especially the oscillator, as far as possible from signal lines which handle currents larger than the microcomputer current value tolerance. Reason: The microcomputer is used in systems which contain signal lines for controlling motors, LEDs, thermal heads, etc. Noise occurs due to mutual inductance when a large current flows through the signal lines. M37905 Mutual inductance M XIN XOUT Vss Large current Fig. 8 Wiring for signal lines where large current flows (2) Distance oscillator from signal lines with frequent potential level changes q I nstall an oscillator and its wiring pattern away from signal lines where potential levels change frequently. q D o not cross these signal lines over the clock-related or noise-sensitive signal lines. Reason: Signal lines with frequently changing potential levels may affect other signal lines at a rising or falling edge. In particular, if the lines cross over a clock-related signal line, clock waveforms may be deformed, which causes a microcomputer malfunction or a program runaway. M37905 Do not cross. ❈ XIN XOUT VSS ❈ I/O pin for signal with frequently changing potential levels Fig. 9 Wiring for signal lines where potential levels frequently change (3) Oscillator protection using Vss pattern Print a Vss pattern on the bottom (soldering side) of a double-sided printed circuit board, under the oscillator mount position. Connect the Vss pattern to the Vss pin of the microcomputer with the shortest possible wiring, separating it from other Vss patterns. An example of Vss pattern on the underside of an oscillator. M37905 Mounted pattern example of oscillator unit. XIN XOUT Vss Separate Vss lines for oscillation and supply. Fig. 10 Vss pattern underneath mounted oscillator 20-108 7905 Group User ’ s Manual Rev.1.0 APPENDIX Appendix 7. Countermeasure against noise 5. Setup for I/O ports Setup I/O ports by hardware and software as follows: q C onnect a resistor of 100 Ω o r more to an I/O port in series. q R ead the data of an input port several times to confirm that input levels are equal. q S ince the output data may reverse because of noise, rewrite data to the output port ’ s Pi register periodically. q R ewrite data to port Pi direction registers periodically. Data bus Direction register Noise Port latch Port Fig. 11 Setup for I/O ports 6. Reinforcement of the power source line q F or the Vss and Vcc lines, use thicker wiring than that of other signal lines. q When using a multilayer printed circuit board, the Vss and Vcc patterns must each be one of the middle layers. q T he following is necessary for double-sided printed circuit boards: •On one side, the microcomputer is installed at the center, and the Vss line is looped or meshed around it. The vacant area is filled with the Vss line. • On the opposite side, the Vcc line is wired the same as the Vss line. 7905 Group User ’ s Manual Rev.1.0 20-109 APPENDIX Appendix 8. 7905 Group Q & A Appendix 8. 7905 Group Q & A Information which may be helpful in fully utilizing the 7905 Group is provided in Q & A format. In Q & A, as a rule, one question and its answer are summarized within one page. The upper box on each page is a question, and a box below the question is its answer. (If a question or an answer extends to two or more pages, there is a page number at the lower right corner.) At the upper right corner of each page, the main function related to the contents of description in that page is listed. 20-110 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 8. 7905 Group Q & A Interrupts Q If an interrupt request (b) occurs while an interrupt routine (a) is executed, is it true that the main routine is not executed at all after the execution of the interrupt routine (a) is completed until the execution of the INTACK sequence for the next interrupt (b) starts? Sequence of execution RTI instruction Interrupt routine (a) ? Main routine INTACK sequence for interrupt (b) Conditions: q F lag I is cleared to “0” by executing the R TI i nstruction. q T he interrupt priority level of interrupt (b) is higher than IPL of the main routine. q T he interrupt priority detection time = 2 cycles of f sys. A An interrupt request is sampled by a sampling pulse generated synchronously with the CPU’s op-code fetch cycle. (1) If the next interrupt request (b) occurs before sampling pulse ➀ f or the R TI i nstruction is generated, the microcomputer executes the INTACK sequence for (b) without executing the main routine. (No instruction of the main routine is executed.) It is because that sampling is completed while executing the R TI i nstruction. Interrupt request (b) ➀ Sampling pulse RTI instruction Interrupt routine (a) INTACK sequence for interrupt (b) (2) If the next interrupt request (b) occurs immediately after sampling pulse ➀ i s generated, the microcomputer executes one instruction of the main routine before executing the INTACK sequence for (b). It is because that the interrupt request is sampled by the next sampling pulse ➁ . Interrupt request (b) ➀ Sampling pulse ➁ RTI instruction One instruction executed Interrupt routine (a) Main routine INTACK sequence for interrupt (b) 7905 Group User’s Manual Rev.1.0 20-111 APPENDIX Appendix 8. 7905 Group Q & A Interrupts Q Suppose that there is a routine which should not accept a certain interrupt request. (This routine can accept any of the other interrupt request.) Although the interrupt priority level select bits for a certain interrupt are set to “000 2” (in other words, although this interrupt is set to be disabled), this interrupt request is actually accepted immediately after the change of the priority level. Why did this occur, and what should I do about it? : Interrupt request is MOVMB X XXIC, #00H ; Writes “ 000 2” t o the interrupt priority level select bits. accepted in this → ; Clears the interrupt request bit to “ 0. ” interval LDA A ,DATA ; Instruction at the beginning of the routine which should not accept a certain interrupt request. : ; A As for the change of the interrupt priority level, if the following are met, the microcomputer may pretend to accept an interrupt request immediately after this interrupt is set to be disabled: •The next instruction (in the above example, it is the LDA instruction) is already stored into a instruction queue buffer of the BIU. •Requirements for accepting the interrupt request which should not be accepted are satisfied immediately before the next instruction in the instruction queue buffer is executed. When writing to a memory or an I/O, the CPU passes an address and data to the BIU. Then, the CPU executes the next instruction in the instruction queue buffer while the BIU is writing data into the actual address. Detection of the interrupt priority level is performed at the beginning of each instruction. In the above case, the CPU e xecutes the next instruction before the BIU completes the change of the interrupt priority level. Therefore, in the detection of the interrupt priority level performed synchronously with the execution of the next instruction, a ctually, the interrupt priority level before the change is used to detection, and its interrupt request is accepted. Interrupt request generated Sequence of execution Interrupt priority detection time CPU operation BIU operation Previous instruction executed MOVMB instruction executed LDA instruction executed Interrupt request accepted (Instruction prefetched) Writing to interrupt priority level select bits. Change of interrupt priority level completed (1/2) 20-112 7905 Group User ’ s Manual Rev.1.0 APPENDIX Appendix 8. 7905 Group Q & A Interrupts A To prevent this problem, make sure that the routine which should not accept a certain interrupt request will be executed after the change of the interrupt priority level (IPL) has been completed. (This is to be made by software.) The following is a sample program. [Sample program] After writing “0002” to the interrupt priority level select bits, the instruction queue buffer is filled with several N OP i nstructions to make the next instruction not to be executed before this writing is completed. : MOVMB X XXIC, #00H NOP : NOP LDA A ,DATA : ; Writes “ 0002” t o the interrupt priority level select bits. ; Inserts ten N OP i nstructions. ; ; Instruction at the beginning of the routine that should not accept a certain interrupt request (2/2) 7905 Group User ’ s Manual Rev.1.0 20-113 APPENDIX Appendix 8. 7905 Group Q & A Interrupts Q After execution of the S EI i nstruction, a branch is made in an interrupt routin. Why did this occur? • • • • SEI LDAB A, #00H • • • • CLI Interrupt routine • • • • RTI A When an interrupt request is generated before the S EI i nstruction is executed, this interrupt request may be accepted immediately before the execution of the S EI i nstruction. (This acceptance occurs depending on the timing when that interrupt request occurs.) In this case, a branch to the interrupt routine is made immediately after execution of the S EI i nstruction. Accordingly, the interrupt routine which is executed immediately after the SEI instruction is due to an interrupt request generated before execution of the SEI instruction. Note that, in the routine ( a ) which should not accept the interrupt request, the following occur. (This routine follows the SEI instruction.): • N o interrupt request is accepted. • N o branch to the interrupt routine is made. • ← Interrupt request • • generated • SEI LDAB A, #00H • • • • a CLI Interrupt routine • • • • RTI Note: “Interrupt” described here means “maskable interrupt” which can be disabled by the SEI instruction. (Refer to section “ 6.2 Interruput source.”) 20-114 7905 Group User ’ s Manual Rev.1.0 APPENDIX Appendix 8. 7905 Group Q & A Interrupts Q (1) Which timing of clock φ1 i s the external interrupts (input signals to the INT i p in) detected? (2) When external interrupt input (INT i) pins are not enough, what should I do? A (1) In both of the edge sense and level sense, an external interrupt request occurs w hen the input signal to the I NT i p in changes its level. This is independent of clock φ 1. In the edge sense, also, the interrupt request bit is set to “ 1 ” a t this time. (2) There are two methods: one uses external interrupt ’ s level sense, and the other uses the timer ’ s event counter mode. ➀ Method using external interrupt’s level sense As for hardware, input a logical sum of multiple interrupt signals (e.g., ‘a’, ‘b’, and ‘c’) to the INTi p in, and input each signal to each corresponding port pin. As for software, check the port pin’s input levels in the INTi interrupt routine in order to detect which signal ( ‘ a ’ , ‘ b ’ , or ‘ c ’ ) was input. M37905 Port pin Port pin Port pin a b c INTi ➁ Method using timer’s event counter mode As for hardware, input an interrupt signal to the TAi IN p in or TBi IN p in. As for software, set the timer’s operating mode to the event counter mode. Then, set a value of “ 0000 16” i nto the timer register and select the valid edge. A timer ’ s interrupt request occurs when an interrupt signal (selected valid edge) is input. 7905 Group User ’ s Manual Rev.1.0 20-115 APPENDIX Appendix 8. 7905 Group Q & A Watchdog timer Q In detection of a program runaway with usage of the watchdog timer, if the same value as that at the reset vector address is set to the watchdog timer interrupt’s vector address, not performing software reset, how does it occur? When a branch is made to the branch destination address for reset within the watchdog timer interrupt routine, how does it occur? A The CPU registers and the SFR are not initialized in the above-mentioned way. Accordingly, the user must initialize all of them by software. Note that the processor interrupt priority level (IPL) retains “7” and is not initialized. Consequently, all interrupt requests cannot be accepted. When rewriting the IPL by software, be sure to save the 16-bit immediate value to the stack area, and then restore that 16-bit immediate value to all bits of the processor status register (PS). When a program runaway occurs, we recommend to perform software reset in order to initialize the microcomputer. 20-116 7905 Group User ’ s Manual Rev.1.0 APPENDIX Appendix 9. M37905M4C-XXXFP electrical characteristics Appendix 9. M37905M4C-XXXFP electrical characteristics The electrical characteristics of the M37905M4C-XXXFP are described below. For the electrical characteristics, be sure to refer to the latest datasheet. ABSOLUTE MAXIMUM RATINGS Symbol VCC AVCC VI Parameter Power source voltage Analog power source voltage Input voltage P10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67, P70–P77, P80–P83, P4OUTCUT, P6OUTCUT, VCONT, VREF, XIN, RESET, MD0, MD1 Ratings –0.3 to 6.5 –0.3 to 6.5 –0.3 to VCC+0.3 Unit V V V VO Pd Topr Tstg Output voltage P10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67, P70–P77, P80–P83, XOUT Power dissipation Operating ambient temperature Storage temerature –0.3 to VCC+0.3 300 –20 to 85 –40 to 150 V mW °C °C 7 905 Group User’s Manual Rev.1.0 20-117 APPENDIX Appendix 9. M37905M4C-XXXFP electrical characteristics RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol VCC AVCC VSS AVSS VIH Power source voltage Analog power source voltage Power source voltage Analog power source voltage High-level input voltage P10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67, P70–P77, P80–P83, P4OUTCUT, P6OUTCUT, XIN, RESET, MD0, MD1 Low-level input voltage P10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67, P70–P77, P80–P83, P4OUTCUT, P6OUTCUT, XIN, RESET, MD0, MD1 High-level peak output current P10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67, P70–P77, P80–P83 0.8 Vcc Parameter Min. 4.5 Typ. 5.0 VCC 0 0 Vcc Max. 5.5 Unit V V V V V VIL 0 0.2 VCC V IOH(peak) IOH(avg) IOL(peak) IOL(peak) IOL(avg) IOL(avg) f(XIN) f(fsys) –10 –5 10 20 5 15 20 20 mA mA mA mA mA mA MHz MHz High-level average output current P10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67, P70–P77, P80–P83 Low-level peak output current P10–P17, P20–P27, P51–P53, P55–P57, P70–P77, P80–P83 Low-level peak output current P40–P47, P60–P67 Low-level average output current P10–P17, P20–P27, P51–P53, P55–P57, P70–P77, P80–P83 Low-level average output current P40–P47, P60–P67 External clock input frequency (Note 1) System clock frequency Notes 1: When using the PLL frequency multiplier, be sure that f(fsys) = 20 MHz or less. 2: The average output current is the average value of an interval of 100 ms. 3: The sum of IOL(peak) must be 110 mA or less, the sum of IOH(peak) must be 80 mA or less. 20-118 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 9. M37905M4C-XXXFP electrical characteristics DC ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, f(fsys) = 20 MHz, unless otherwise noted) Symbol VOH Parameter High-level output voltage P10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67, P70–P77, P80–P83 Low-level output voltage P10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67, P70–P77, P80–P83 Hysteresis TA0IN–TA9IN, TA0OUT–TA9OUT, TB0IN–TB2IN, INT0–INT7, CTS0, CTS1, CTS2, CLK0, CLK1, CLK2, RxD0, RxD1, RxD2, RTPTRG0, RTPTRG1, P4OUTCUT, P6OUTCUT RESET XIN VI = 5.0 V Test conditions IOH = –10 mA Min. 3 Limits Typ. Max. Unit V VOL IOL = 10 mA 2 V VT+ —VT– 0.4 1 V VT+ —VT– VT+ —VT– IIH Hysteresis Hysteresis 0.5 0.1 1.5 0.3 5 V V µA High-level input current P10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67, P70–P77, P80–P83, P4OUTCUT, P6OUTCUT, XIN, RESET, MD0, MD1 Low-level input current P10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67, P70–P77, P80–P83, P4OUTCUT, P6OUTCUT, XIN, RESET, MD0, MD1 RAM hold voltage Power source current Output-only pins are open, and the other pins are connected to Vss or Vcc. An external square-waveform clock is input. (Pin X OUT is open.) The PLL frequency multiplier is inactive. IIL VI = 0 V –5 µA VRAM ICC When clock is inactive. f(fsys) = 20 MHz. CPU is active. Ta = 25 °C when clock is inactive. Ta = 85 °C when clock is inactive. 2 25 50 1 20 V mA µA 7 905 Group User’s Manual Rev.1.0 20-119 APPENDIX Appendix 9. M37905M4C-XXXFP electrical characteristics A-D CONVERTER CHARACTERISTICS (VCC = AVCC = 5 V ± 0.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol ————— Parameter Resolution VREF = VCC Test conditions A-D converter Comparator 10-bit resolution mode 8-bit resolution mode Comparater 5 10-bit resolution mode 8-bit resolution mode Comparater 5.9 2.45 (Note) 0.7 (Note) 2.7 0 VCC VREF V V Limits Min. Typ. Max. 10 Unit Bits ————— RLADDER tCONV VREF VIA Absolute accuracy Ladder resistance Conversion time Reference voltage Analog input voltage VREF = VCC VREF = VCC f(fsys) ≤ 20 MHz 1 VREF V 256 ±3 LSB ±2 LSB ± 40 mV kΩ µs Note: This is applied when A-D conversion freguency (φAD) = f1 (φ). D-A CONVERTER CHARACTERISTICS (VCC = 5 V, VSS = AVSS = 0 V, VREF = 5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol —— —— tsu RO IVREF Resolution Absolute accuracy Set time Output resistance Reference power source input current 2 (Note) 3.5 Parameter Test conditions Limits Min. Typ. Max. 8 ± 1.0 3 4.5 3.2 Unit Bits % µs kΩ mA Note: The test conditions are as follows: • One D-A converter is used. • The D-A register value of the unused D-A converter is “0016.” • The reference power source input current for the ladder resistance of the A-D converter is excluded. RESET INPUT Reset input timing requirements (VCC = 5 V ± 0.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tw(RESETL) Parameter RESET input low-level pulse width Min. 10 Limits Typ. Max. Unit µs RESET input tw(RESETL) 20-120 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 9. M37905M4C-XXXFP electrical characteristics PERIPHERAL DEVICE INPUT/OUTPUT TIMING (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 20 MHz, unless otherwise noted) For limits depending on f(fsys), their calculation formulas are shown below. Also, the values at f(fsys) = 20 MHz are shown in ( ). ∗ Timer A input (Count input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Limits Min. 80 40 40 Max. Unit ns ns ns Timer A input (Gating input in timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz Limits Min. 16 × 109 (800) f(fsys) 8 × 109 f(fsys) 8× f(fsys) 109 (400) (400) Max. Unit ns ns ns Note : The TAiIN input cycle time requires 4 or more cycles of a count source. The TAiIN input high-level pulse width and the TAiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 20 MHz. Timer A input (External trigger input in one-shot pulse mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter f(fsys) ≤ 20 MHz Limits Min. 8 × 109 f(fsys) 80 80 (400) Max. Unit ns ns ns Timer A input (External trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Limits Min. 80 80 Max. Unit ns ns Timer A input (Up-down input and Count input in event counter mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time Parameter Limits Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns 7 905 Group User’s Manual Rev.1.0 20-121 APPENDIX Appendix 9. M37905M4C-XXXFP electrical characteristics Timer A input (Two-phase pulse input in event counter mode) (j = 2 to 4, 7 to 9) Symbol tc(TA) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) TAjIN input cycle time TAjIN input setup time TAjOUT input setup time Parameter Limits Min. 800 200 200 Max. Unit ns ns ns • Gating input in timer mode • Count input in event counter mode • External trigger input in one-shot pulse mode • External trigger input in pulse width modulation mode tc(TA) tw(TAH) TAiIN input tw(TAL) • Up-down and Count input in event counter mode tc(UP) tw(UPH) TAiOUT input (Up-down input) tw(UPL) TAiOUT input (Up-down input) TAiIN input (When count by falling) th(TIN-UP) tsu(UP-TIN) TAiIN input (When count by rising) • Two-phase pulse input in event counter mode tc(TA) TAjIN input tsu(TAjIN-TAjOUT) TAjOUT input tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) tsu(TAjOUT-TAjIN) Test conditions • VCC = 5 V ± 0.5 V, Ta = –20 to 85 °C • Input timing voltage : VIL = 1.0 V, VIH = 4.0 V 20-122 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 9. M37905M4C-XXXFP electrical characteristics Timer B input (Count input in event counter mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time (one edge count) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edge count) TBiIN input high-level pulse width (both edge count) TBiIN input low-level pulse width (both edge count) Parameter Limits Min. 80 40 40 160 80 80 Max. Unit ns ns ns ns ns ns Timer B input (Pulse period measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width Parameter f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz Limits Min. 16 × 109 f(fsys) 8 × 109 f(fsys) 8 × 109 f(fsys) (800) (400) (400) Max. Unit ns ns ns Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 20 MHz. Timer B input (Pulse width measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width Parameter f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz Limits Min. 16 × 109 (800) f(fsys) 8 × 109 f(fsys) 8 × 109 f(fsys) (400) (400) Max. Unit ns ns ns Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 20 MHz. Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input high-level pulse width CLKi input low-level pulse width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time 0 20 90 Parameter Limits Min. 200 100 100 80 Max. Unit ns ns ns ns ns ns ns 7 905 Group User’s Manual Rev.1.0 20-123 APPENDIX Appendix 9. M37905M4C-XXXFP electrical characteristics External interrupt (INTi) input Symbol tw(INH) tw(INL) INTi input high-level pulse width INTi input low-level pulse width Parameter Limits Min. 250 250 Max. Unit ns ns tc(TB) tw(TBH) TBiIN input tw(TBL) tc(CK) tw(CKH) CLKi input tw(CKL) th(C-Q) TxDi output td(C-Q) RxDi input tsu(D-C) th(C-D) tw(INL) INTi input tw(INH) Test conditions • Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C • Input timing voltage : VIL = 1.0 V, VIH = 4.0 V • Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF 20-124 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 9. M37905M4C-XXXFP electrical characteristics External clock input Timing Requirements (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 20 MHz, unless otherwise noted) Symbol tc tw(half) tw(H) tw(L) tr tf External clock input cycle time External clock input pulse width with half input-voltage External clock input high-level pulse width External clock input low-level pulse width External clock input rise time External clock input fall time Parameter Limits Min. 50 0.45 tc 0.5 tc – 8 0.5 tc – 8 8 8 Max. 0.55 tc Unit ns ns ns ns ns ns External clock input tw(L) f(XIN) tw(H) tr tf tc tw(half) Test conditions • Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C • Input timing voltage : VIL = 1.0 V, VIH = 4.0 V (tw(H), tw(L), tr, tf) • Input timing voltage : 2.5 V (tc, tw(half)) 7 905 Group User’s Manual Rev.1.0 20-125 APPENDIX Appendix 10. M37905M4C-XXXFP standard characteristics Appendix 10. M37905M4C-XXXFP standard characteristics Standard characteristics described below are just examples of the M37905M4C-XXXFP’s characteristics and are not guaranteed. For each parameter’s limits, refer to sections “Appendix 9. M37905M4C-XXXFP electrical characteristics.” 1. Programmable I/O port (CMOS output) standard characteristics: P1, P2, P5, P7, P8 (1) P-channel IOH–V OH c haracteristics Power source voltage: Vcc = 5 V 30.0 Ta=25°C IOH [mA] Ta=85°C 15.0 0 1.0 2.0 VOH [V] 3.0 4.0 5.0 (2) N-channel I OL–V OL c haracteristics Power source voltage: Vcc = 5 V Ta=25°C 30.0 IOL [mA] Ta=85°C 15.0 0 1.0 2.0 VOL [V] 3.0 4.0 5.0 20-126 7905 Group User’s Manual Rev.1.0 APPENDIX Appendix 10. M37905M4C-XXXFP standard characteristics 2. Programmable I/O port (CMOS output) standard characteristics: P4, P6 (1) P-channel IOH–V OH c haracteristics Power source voltage: Vcc = 5 V 30.0 Ta=25°C IOH [mA] Ta=85°C 15.0 0 1.0 2.0 VOH [V] 3.0 4.0 5.0 (2) N-channel I OL–V OL c haracteristics Power source voltage: Vcc = 5 V 30.0 IOL [mA] Ta=25°C Ta=85°C 15.0 0 1.0 2.0 VOL [V] 3.0 4.0 5.0 7905 Group User ’ s Manual Rev.1.0 20-127 APPENDIX Appendix 10. M37905M4C-XXXFP standard characteristics 4. Icc–f(X IN) standard characteristics 35.0 30.0 Active 25.0 20.0 15.0 10.0 5.0 At Wait mode At reset (PLL frequency multiplier is active.) Measurement condition • Vcc = 5.0 V • Ta = 25 ° C • f(X IN) : square waveform input •Single-chip mode • PLL frequency multiplier is inactive. • External clock input select bit = “ 1 ” Icc [mA] 0.0 0 5 10 15 f(XIN) [MHz] 20 25 30 20-128 7905 Group User ’ s Manual Rev.1.0 APPENDIX Appendix 10. M37905M4C-XXXFP standard characteristics 4. A-D converter standard characteristics The lower lines of the graph indicate the absolute precision errors. These are expressed as the deviation from the ideal value when the output code changes. For example, the change in M37905M4C-XXXFP ’ s output code from 159 to 160 should occur at 797.5 mV, but the measured value is +2.75 mV. Accordingly, the measured point of change is 797.5 + 2.75 = 800.25 mV. The upper lines of the graph indicate the input voltage width for which the output code is constant. For example, the measured input voltage width for which the output code is 56 is 6.0 mV, so that the differential non-linear error is 6.0 – 5 = 1 .0 mV (0.20 LSB). 7905 Group User ’ s Manual Rev.1.0 20-129 APPENDIX Appendix 10. M37905M4C-XXXFP standard characteristics (Measurement conditions Vcc = 5.0 V, VREF = 5.12 V, f(fsys) = 20 MHz, Ta = 25 °C, φAD = f(fsys) divided by 2) 20-130 7905 Group User ’ s Manual Rev.1.0 APPENDIX Appendix 11. Memory assignment of 7905 Group Appendix 11. Memory assignment of 7905 Group 1. M37905F8, M37905M8 M37905F8 016 SFR area FF16 10016 Unused area 3FF16 40016 Internal RAM area (3 Kbytes) FFF16 100016 FFF16 100016 M37905M8 016 FF16 10016 3FF16 40016 SFR area Unused area Internal RAM area (3 Kbytes) Bank 016 Bank 016 Internal flash memory area (User ROM area) (60 Kbytes) Internal ROM area (60 Kbytes) FFFF16 FFFF16 Fig. 12 Memory assigments of M37905F8, M37905M8 2. M37905M6 M37905M6 016 FF16 10016 3FF16 40016 SFR area Unused area Internal RAM area FFF16 100016 3FFF16 400016 (3 Kbytes) (Note) Unused area Bank 016 Internal ROM area (48 Kbytes) FFFF16 Note: Do not assign a program to the last 8 bytes of the internal RAM area. Fig. 13 Memory assigment of M37905M6 7905 Group User’s Manual Rev.1.0 20-131 APPENDIX Appendix 11. Memory assignment of 7905 Group 3. M37905M4 016 FF16 10016 M37905M4 SFR area Unused area BFF16 C0016 Internal RAM area FFF16 100016 (1 Kbyte) (Note) Bank 016 Unused area 7FFF16 800016 Internal ROM area (32 Kbytes) FFFF16 Note: Do not assign a program to the last 8 bytes of the internal RAM area. Fig. 14 Memory assigment of M37905M4 20-132 7905 Group User ’ s Manual Rev.1.0 MITSUBISHI SEMICONDUCTORS USER’S MANUAL 7905 Group Rev.1.0 Nov.28, 2001 Editioned by Committee of editing of Mitsubishi Semiconductor USER’S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©2001 MITSUBISHI ELECTRIC CORPORATION User’s Manual 7905 Group © 2001 MITSUBISHI ELECTRIC CORPORATION. New publication, effective Nov. 2001. Specifications subject to change without notice.