82P2282PF8

Dual T1/E1/J1 Long Haul / Short Haul Transceiver IDT82P2282 Version 10 August 20, 2009 6024 Silver Creek Valley Road, San Jose, CA 95138 Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775 Printed in U.S.A. © 2008 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc. LIFE SUPPORT POLICY Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT. 1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Table of Contents FEATURES ............................................................................................................................................................................ 12 APPLICATIONS..................................................................................................................................................................... 12 BLOCK DIAGRAM ................................................................................................................................................................ 13 1 PIN ASSIGNMENT ........................................................................................................................................................... 14 2 PIN DESCRIPTION .......................................................................................................................................................... 15 3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 22 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 T1 / E1 / J1 MODE SELECTION ................................................................................................................................................................... 24 RECEIVER IMPEDANCE MATCHING .......................................................................................................................................................... 25 3.2.1 Line Monitor .................................................................................................................................................................................... 25 ADAPTIVE EQUALIZER ............................................................................................................................................................................... 28 DATA SLICER ............................................................................................................................................................................................... 28 CLOCK AND DATA RECOVERY ................................................................................................................................................................. 28 RECEIVE JITTER ATTENUATOR ................................................................................................................................................................ 29 DECODER ..................................................................................................................................................................................................... 30 3.7.1 Line Code Rule ............................................................................................................................................................................... 30 3.7.1.1 T1 / J1 Mode .................................................................................................................................................................... 30 3.7.1.2 E1 Mode ........................................................................................................................................................................... 30 3.7.2 Decode Error Detection ................................................................................................................................................................. 30 3.7.2.1 T1 / J1 Mode .................................................................................................................................................................... 30 3.7.2.2 E1 Mode ........................................................................................................................................................................... 30 3.7.3 LOS Detection ................................................................................................................................................................................ 31 FRAME PROCESSOR .................................................................................................................................................................................. 34 3.8.1 T1/J1 Mode ...................................................................................................................................................................................... 34 3.8.1.1 Synchronization Searching ............................................................................................................................................... 34 3.8.1.1.1 Super Frame (SF) Format ............................................................................................................................. 34 3.8.1.1.2 Extended Super Frame (ESF) Format ........................................................................................................... 35 3.8.1.1.3 T1 Digital Multiplexer (DM) Format (T1 only) ................................................................................................ 36 3.8.1.1.4 Switch Line Carrier - 96 (SLC-96) Format (T1 only) ...................................................................................... 37 3.8.1.2 Error Event And Out Of Synchronization Detection .......................................................................................................... 38 3.8.1.2.1 Super Frame (SF) Format ............................................................................................................................. 38 3.8.1.2.2 Extended Super Frame (ESF) Format ........................................................................................................... 38 3.8.1.2.3 T1 Digital Multiplexer (DM) Format (T1 only) ................................................................................................ 38 3.8.1.2.4 Switch Line Carrier - 96 (SLC-96) Format (T1 only) ...................................................................................... 38 3.8.1.3 Overhead Extraction (T1 Mode SLC-96 Format Only) ..................................................................................................... 39 3.8.1.4 Interrupt Summary ............................................................................................................................................................ 39 3.8.2 E1 Mode .......................................................................................................................................................................................... 41 3.8.2.1 Synchronization Searching ............................................................................................................................................... 43 3.8.2.1.1 Basic Frame .................................................................................................................................................. 43 3.8.2.1.2 CRC Multi-Frame ........................................................................................................................................... 44 3.8.2.1.3 CAS Signaling Multi-Frame ........................................................................................................................... 45 3.8.2.2 Error Event And Out Of Synchronization Detection .......................................................................................................... 45 3.8.2.2.1 Out Of Basic Frame Synchronization ............................................................................................................ 46 3.8.2.2.2 Out Of CRC Multi-Frame Synchronization .................................................................................................... 46 3.8.2.2.3 Out Of CAS Signaling Multi-Frame Synchronization ..................................................................................... 46 3.8.2.3 Overhead Extraction ......................................................................................................................................................... 46 3.8.2.3.1 International Bit Extraction ............................................................................................................................. 46 3.8.2.3.2 Remote Alarm Indication Bit Extraction ......................................................................................................... 46 Table of Contents 3 August 20, 2009 IDT82P2282 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER 3.8.2.3.3 National Bit Extraction ................................................................................................................................... 46 3.8.2.3.4 National Bit Codeword Extraction .................................................................................................................. 46 3.8.2.3.5 Extra Bit Extraction ........................................................................................................................................ 46 3.8.2.3.6 Remote Signaling Multi-Frame Alarm Indication Bit Extraction ..................................................................... 46 3.8.2.3.7 Sa6 Code Detection Per ETS 300 233 .......................................................................................................... 46 3.8.2.4 V5.2 Link .......................................................................................................................................................................... 47 3.8.2.5 Interrupt Summary ............................................................................................................................................................ 47 PERFORMANCE MONITOR ......................................................................................................................................................................... 49 3.9.1 T1/J1 Mode ...................................................................................................................................................................................... 49 3.9.2 E1 Mode .......................................................................................................................................................................................... 51 ALARM DETECTOR ..................................................................................................................................................................................... 53 3.10.1 T1/J1 Mode ...................................................................................................................................................................................... 53 3.10.2 E1 Mode .......................................................................................................................................................................................... 55 HDLC RECEIVER .......................................................................................................................................................................................... 56 3.11.1 HDLC Channel Configuration ........................................................................................................................................................ 56 3.11.2 HDLC Mode ..................................................................................................................................................................................... 56 BIT-ORIENTED MESSAGE RECEIVER ....................................................................................................................................................... 59 INBAND LOOPBACK CODE DETECTOR (T1/J1 ONLY) ............................................................................................................................ 59 ELASTIC STORE BUFFER ........................................................................................................................................................................... 60 RECEIVE CAS/RBS BUFFER ...................................................................................................................................................................... 60 3.15.1 T1/J1 Mode ...................................................................................................................................................................................... 60 3.15.2 E1 Mode .......................................................................................................................................................................................... 61 RECEIVE PAYLOAD CONTROL .................................................................................................................................................................. 63 RECEIVE SYSTEM INTERFACE .................................................................................................................................................................. 65 3.17.1 T1/J1 Mode ...................................................................................................................................................................................... 65 3.17.1.1 Receive Clock Master Mode ............................................................................................................................................ 65 3.17.1.1.1 Receive Clock Master Full T1/J1 Mode ......................................................................................................... 65 3.17.1.1.2 Receive Clock Master Fractional T1/J1 Mode ............................................................................................... 66 3.17.1.2 Receive Clock Slave Mode .............................................................................................................................................. 66 3.17.1.3 Receive Multiplexed Mode ............................................................................................................................................... 67 3.17.1.4 Offset ................................................................................................................................................................................ 67 3.17.1.5 Output On RSDn/MRSD & RSIGn/MRSIG ....................................................................................................................... 70 3.17.2 E1 Mode .......................................................................................................................................................................................... 70 3.17.2.1 Receive Clock Master Mode ............................................................................................................................................ 70 3.17.2.1.1 Receive Clock Master Full E1 Mode ............................................................................................................. 70 3.17.2.1.2 Receive Clock Master Fractional E1 Mode ................................................................................................... 70 3.17.2.2 Receive Clock Slave Mode .............................................................................................................................................. 70 3.17.2.3 Receive Multiplexed Mode ............................................................................................................................................... 71 3.17.2.4 Offset ................................................................................................................................................................................ 71 3.17.2.5 Output On RSDn/MRSD & RSIGn/MRSIG ....................................................................................................................... 71 TRANSMIT SYSTEM INTERFACE ............................................................................................................................................................... 73 3.18.1 T1/J1 Mode ...................................................................................................................................................................................... 73 3.18.1.1 Transmit Clock Master Mode ............................................................................................................................................ 73 3.18.1.1.1 Transmit Clock Master Full T1/J1 Mode ........................................................................................................ 73 3.18.1.1.2 Transmit Clock Master Fractional T1/J1 Mode .............................................................................................. 73 3.18.1.2 Transmit Clock Slave Mode ............................................................................................................................................. 74 3.18.1.3 Transmit Multiplexed Mode .............................................................................................................................................. 75 3.18.1.4 Offset ................................................................................................................................................................................ 76 3.18.2 E1 Mode .......................................................................................................................................................................................... 79 3.18.2.1 Transmit Clock Master Mode ............................................................................................................................................ 79 3.18.2.1.1 Transmit Clock Master Full E1 Mode ............................................................................................................ 79 3.18.2.1.2 Transmit Clock Master Fractional E1 Mode .................................................................................................. 79 3.18.2.2 Transmit Clock Slave Mode ............................................................................................................................................. 79 3.18.2.3 Transmit Multiplexed Mode .............................................................................................................................................. 80 Table of Contents 4 August 20, 2009 IDT82P2282 DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER 3.18.2.4 Offset ................................................................................................................................................................................ 80 3.19 TRANSMIT PAYLOAD CONTROL ............................................................................................................................................................... 81 3.20 FRAME GENERATOR .................................................................................................................................................................................. 82 3.20.1 Generation ...................................................................................................................................................................................... 82 3.20.1.1 T1 / J1 Mode .................................................................................................................................................................... 82 3.20.1.1.1 Super Frame (SF) Format ............................................................................................................................. 82 3.20.1.1.2 Extended Super Frame (ESF) Format ........................................................................................................... 82 3.20.1.1.3 T1 Digital Multiplexer (DM) Format (T1 only) ................................................................................................ 82 3.20.1.1.4 Switch Line Carrier - 96 (SLC-96) Format (T1 only) ...................................................................................... 82 3.20.1.1.5 Interrupt Summary ......................................................................................................................................... 83 3.20.1.2 E1 Mode ........................................................................................................................................................................... 84 3.20.1.2.1 Interrupt Summary ......................................................................................................................................... 85 3.20.2 HDLC Transmitter .......................................................................................................................................................................... 87 3.20.2.1 HDLC Channel Configuration ........................................................................................................................................... 87 3.20.2.2 HDLC Mode ...................................................................................................................................................................... 87 3.20.2.2.1 HDLC Mode ................................................................................................................................................... 87 3.20.2.3 Interrupt Summary ............................................................................................................................................................ 87 3.20.2.4 Reset ................................................................................................................................................................................ 87 3.20.3 Automatic Performance Report Message (T1/J1 Only) .............................................................................................................. 89 3.20.4 Bit-Oriented Message Transmitter (T1/J1 Only) .......................................................................................................................... 90 3.20.5 Inband Loopback Code Generator (T1/J1 Only) .......................................................................................................................... 90 3.20.6 All ‘Zero’s & All ‘One’s ................................................................................................................................................................... 90 3.20.7 Change Of Frame Alignment ......................................................................................................................................................... 90 3.21 TRANSMIT BUFFER ..................................................................................................................................................................................... 91 3.22 ENCODER ..................................................................................................................................................................................................... 91 3.22.1 Line Code Rule ............................................................................................................................................................................... 91 3.22.1.1 T1/J1 Mode ...................................................................................................................................................................... 91 3.22.1.2 E1 Mode ........................................................................................................................................................................... 91 3.22.2 BPV Error Insertion ........................................................................................................................................................................ 91 3.22.3 All ‘One’s Insertion ........................................................................................................................................................................ 91 3.23 TRANSMIT JITTER ATTENUATOR ............................................................................................................................................................. 92 3.24 WAVEFORM SHAPER / LINE BUILD OUT .................................................................................................................................................. 93 3.24.1 Preset Waveform Template ........................................................................................................................................................... 93 3.24.1.1 T1/J1 Mode ...................................................................................................................................................................... 93 3.24.1.2 E1 Mode ........................................................................................................................................................................... 93 3.24.2 Line Build Out (LBO) (T1 Only) ..................................................................................................................................................... 94 3.24.3 User-Programmable Arbitrary Waveform .................................................................................................................................... 94 3.25 LINE DRIVER .............................................................................................................................................................................................. 101 3.26 TRANSMITTER IMPEDANCE MATCHING ................................................................................................................................................ 102 3.27 TESTING AND DIAGNOSTIC FACILITIES ................................................................................................................................................ 103 3.27.1 PRBS Generator / Detector ......................................................................................................................................................... 103 3.27.1.1 Pattern Generator ........................................................................................................................................................... 103 3.27.1.2 Pattern Detector ............................................................................................................................................................. 103 3.27.2 Loopback ...................................................................................................................................................................................... 104 3.27.2.1 System Loopback ........................................................................................................................................................... 104 3.27.2.1.1 System Remote Loopback .......................................................................................................................... 104 3.27.2.1.2 System Local Loopback .............................................................................................................................. 104 3.27.2.2 Payload Loopback .......................................................................................................................................................... 104 3.27.2.3 Local Digital Loopback 1 ................................................................................................................................................ 104 3.27.2.4 Remote Loopback .......................................................................................................................................................... 104 3.27.2.5 Local Digital Loopback 2 ................................................................................................................................................ 104 3.27.2.6 Analog Loopback ............................................................................................................................................................ 104 3.27.3 G.772 Non-Intrusive Monitoring .................................................................................................................................................. 104 3.28 INTERRUPT SUMMARY ............................................................................................................................................................................. 107 Table of Contents 5 August 20, 2009 IDT82P2282 DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER 4 OPERATION ................................................................................................................................................................... 108 4.1 4.2 4.3 4.4 4.5 POWER-ON SEQUENCE ............................................................................................................................................................................ 108 RESET ......................................................................................................................................................................................................... 108 RECEIVE / TRANSMIT PATH POWER DOWN .......................................................................................................................................... 108 MICROPROCESSOR INTERFACE ............................................................................................................................................................ 109 4.4.1 SPI Mode ....................................................................................................................................................................................... 109 4.4.2 Parallel Microprocessor Interface .............................................................................................................................................. 110 INDIRECT REGISTER ACCESS SCHEME ................................................................................................................................................ 111 4.5.1 Indirect Register Read Access ................................................................................................................................................... 111 4.5.2 Indirect Register Write Access ................................................................................................................................................... 111 5 PROGRAMMING INFORMATION .................................................................................................................................. 112 5.1 5.2 REGISTER MAP .......................................................................................................................................................................................... 112 5.1.1 T1/J1 Mode .................................................................................................................................................................................... 112 5.1.1.1 Direct Register ................................................................................................................................................................ 112 5.1.1.2 Indirect Register ............................................................................................................................................................. 117 5.1.2 E1 Mode ........................................................................................................................................................................................ 118 5.1.2.1 Direct Register ................................................................................................................................................................ 118 5.1.2.2 Indirect Register ............................................................................................................................................................. 123 REGISTER DESCRIPTION ......................................................................................................................................................................... 125 5.2.1 T1/J1 Mode .................................................................................................................................................................................... 126 5.2.1.1 Direct Register ................................................................................................................................................................ 126 5.2.1.2 Indirect Register ............................................................................................................................................................. 227 5.2.2 E1 Mode ........................................................................................................................................................................................ 240 5.2.2.1 Direct Register ................................................................................................................................................................ 240 5.2.2.2 Indirect Register ............................................................................................................................................................. 342 6 IEEE STD 1149.1 JTAG TEST ACCESS PORT ............................................................................................................ 357 6.1 6.2 6.3 JTAG INSTRUCTIONS AND INSTRUCTION REGISTER (IR) ................................................................................................................... 358 JTAG DATA REGISTER ............................................................................................................................................................................. 359 6.2.1 Device Identification Register (IDR) ........................................................................................................................................... 359 6.2.2 Bypass Register (BYP) ................................................................................................................................................................ 359 6.2.3 Boundary Scan Register (BSR) ................................................................................................................................................... 359 TEST ACCESS PORT CONTROLLER ....................................................................................................................................................... 361 7 PHYSICAL AND ELECTRICAL SPECIFICATIONS ...................................................................................................... 364 7.1 7.2 7.3 7.4 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 364 RECOMMENDED OPERATING CONDITIONS .......................................................................................................................................... 364 D.C. CHARACTERISTICS .......................................................................................................................................................................... 365 DIGITAL I/O TIMING CHARACTERISTICS ................................................................................................................................................ 366 7.4.1 In Non-Multiplexed Mode ............................................................................................................................................................. 366 7.4.2 In Multiplexed Mode ..................................................................................................................................................................... 367 7.5 CLOCK FREQUENCY REQUIREMENT ..................................................................................................................................................... 367 7.6 T1/J1 LINE RECEIVER ELECTRICAL CHARACTERISTICS .................................................................................................................... 368 7.7 E1 LINE RECEIVER ELECTRICAL CHARACTERISTICS ......................................................................................................................... 369 7.8 T1/J1 LINE TRANSMITTER ELECTRICAL CHARACTERISTICS ............................................................................................................. 370 7.9 E1 LINE TRANSMITTER ELECTRICAL CHARACTERISTICS ................................................................................................................. 371 7.10 JITTER TOLERANCE ................................................................................................................................................................................. 372 7.10.1 T1/J1 Mode .................................................................................................................................................................................... 372 7.10.2 E1 Mode ........................................................................................................................................................................................ 373 7.11 JITTER TRANSFER .................................................................................................................................................................................... 374 7.11.1 T1/J1 Mode .................................................................................................................................................................................... 374 7.11.2 E1 Mode ........................................................................................................................................................................................ 375 7.12 MICROPROCESSOR TIMING SPECIFICATION ........................................................................................................................................ 376 7.12.1 Motorola Non-Multiplexed Mode ................................................................................................................................................. 376 7.12.1.1 Read Cycle Specification ............................................................................................................................................... 376 Table of Contents 6 August 20, 2009 IDT82P2282 DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER 7.12.1.2 Write Cycle Specification ................................................................................................................................................ 7.12.2 Intel Non-Multiplexed Mode ......................................................................................................................................................... 7.12.2.1 Read Cycle Specification ............................................................................................................................................... 7.12.2.2 Write Cycle Specification ................................................................................................................................................ 7.12.3 SPI Mode ....................................................................................................................................................................................... 377 378 378 379 380 ORDERING INFORMATION .......................................................................................................................................... 381 DOCUMENT HISTORY .................................................................................................................................................. 381 Table of Contents 7 August 20, 2009 List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Table 30: Table 31: Table 32: Table 33: Table 34: Table 35: Table 36: Table 37: Table 38: Table 39: Table 40: Table 41: Table 42: Table 43: Table 44: Table 45: Table 46: Table 47: Table 48: Operating Mode Selection ........................................................................................................................................................................... Related Bit / Register In Chapter 3.1 ........................................................................................................................................................... Impedance Matching Value For The Receiver ............................................................................................................................................. Related Bit / Register In Chapter 3.2 ........................................................................................................................................................... Related Bit / Register In Chapter 3.3 & Chapter 3.4 .................................................................................................................................... Criteria Of Speed Adjustment Start .............................................................................................................................................................. Related Bit / Register In Chapter 3.6 ........................................................................................................................................................... Excessive Zero Error Definition ................................................................................................................................................................... LOS Condition In T1/J1 Mode ...................................................................................................................................................................... LOS Condition In E1 Mode .......................................................................................................................................................................... Related Bit / Register In Chapter 3.7 ........................................................................................................................................................... The Structure of SF ..................................................................................................................................................................................... The Structure of ESF ................................................................................................................................................................................... The Structure of T1 DM ............................................................................................................................................................................... The Structure of SLC-96 .............................................................................................................................................................................. Interrupt Source In T1/J1 Frame Processor ................................................................................................................................................ Related Bit / Register In Chapter 3.8.1 ........................................................................................................................................................ The Structure Of TS0 In CRC Multi-Frame .................................................................................................................................................. FAS/NFAS Bit/Pattern Error Criteria ............................................................................................................................................................ Interrupt Source In E1 Frame Processor ..................................................................................................................................................... Related Bit / Register In Chapter 3.8.2 ........................................................................................................................................................ Monitored Events In T1/J1 Mode ................................................................................................................................................................. Related Bit / Register In Chapter 3.9.1 ........................................................................................................................................................ Monitored Events In E1 Mode ..................................................................................................................................................................... Related Bit / Register In Chapter 3.9.2 ........................................................................................................................................................ RED Alarm, Yellow Alarm & Blue Alarm Criteria ......................................................................................................................................... Related Bit / Register In Chapter 3.10.1 ...................................................................................................................................................... Related Bit / Register In Chapter 3.10.2 ...................................................................................................................................................... Related Bit / Register In Chapter 3.11.1 ...................................................................................................................................................... Interrupt Summarize In HDLC Mode ........................................................................................................................................................... Related Bit / Register In Chapter 3.11.2 ...................................................................................................................................................... Related Bit / Register In Chapter 3.12 ......................................................................................................................................................... Related Bit / Register In Chapter 3.13 ......................................................................................................................................................... Related Bit / Register In Chapter 3.14 ......................................................................................................................................................... Related Bit / Register In Chapter 3.15 ......................................................................................................................................................... A-Law Digital Milliwatt Pattern ..................................................................................................................................................................... µ-Law Digital Milliwatt Pattern ..................................................................................................................................................................... Related Bit / Register In Chapter 3.16 ......................................................................................................................................................... Operating Modes Selection In T1/J1 Receive Path ..................................................................................................................................... Operating Modes Selection In E1 Receive Path .......................................................................................................................................... Related Bit / Register In Chapter 3.17 ......................................................................................................................................................... Operating Modes Selection In T1/J1 Transmit Path .................................................................................................................................... Operating Modes Selection In E1 Transmit Path ......................................................................................................................................... Related Bit / Register In Chapter 3.18 ......................................................................................................................................................... Related Bit / Register In Chapter 3.19 ......................................................................................................................................................... Related Bit / Register In Chapter 3.20.1.1 ................................................................................................................................................... E1 Frame Generation .................................................................................................................................................................................. Control Over E Bits ...................................................................................................................................................................................... List of Tables 8 24 24 25 27 28 29 29 30 32 32 33 34 35 36 37 39 40 44 45 47 48 49 50 51 52 53 54 55 56 57 58 59 59 60 62 63 63 64 65 70 72 73 79 80 81 83 84 84 August 20, 2009 IDT82P2282 Table 49: Table 50: Table 51: Table 52: Table 53: Table 54: Table 55: Table 56: Table 57: Table 58: Table 59: Table 60: Table 61: Table 62: Table 63: Table 64: Table 65: Table 66: Table 67: Table 68: Table 69: Table 70: Table 71: Table 72: Table 73: Table 74: Table 75: Table 76: Table 77: Table 78: Table 79: Table 80: Table 81: Table 82: Table 83: Table 84: Table 85: DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER Interrupt Summary In E1 Mode .................................................................................................................................................................... 85 Related Bit / Register In Chapter 3.20.1.2 ................................................................................................................................................... 86 Related Bit / Register In Chapter 3.20.2.1 ................................................................................................................................................... 87 Related Bit / Register In Chapter 3.20.2.2 ~ Chapter 3.20.2.4 .................................................................................................................... 88 APRM Message Format .............................................................................................................................................................................. 89 APRM Interpretation .................................................................................................................................................................................... 89 Related Bit / Register In Chapter 3.20.3 ...................................................................................................................................................... 90 Related Bit / Register In Chapter 3.20.4 & Chapter 3.20.5 .......................................................................................................................... 90 Related Bit / Register In Chapter 3.20.6, Chapter 3.20.7 & Chapter 3.21 ................................................................................................... 91 Related Bit / Register In Chapter 3.22 ......................................................................................................................................................... 91 Related Bit / Register In Chapter 3.23 ......................................................................................................................................................... 92 PULS[3:0] Setting In T1/J1 Mode ................................................................................................................................................................ 93 LBO PULS[3:0] Setting In T1 Mode ............................................................................................................................................................. 94 Transmit Waveform Value For E1 75 Ohm .................................................................................................................................................. 95 Transmit Waveform Value For E1 120 Ohm ................................................................................................................................................ 95 Transmit Waveform Value For T1 0~133 ft ................................................................................................................................................. 96 Transmit Waveform Value For T1 133~266 ft ............................................................................................................................................. 96 Transmit Waveform Value For T1 266~399 ft ............................................................................................................................................. 97 Transmit Waveform Value For T1 399~533 ft ............................................................................................................................................. 97 Transmit Waveform Value For T1 533~655 ft ............................................................................................................................................. 98 Transmit Waveform Value For J1 0~655ft ................................................................................................................................................... 98 Transmit Waveform Value For DS1 0 dB LBO ............................................................................................................................................ 99 Transmit Waveform Value For DS1 -7.5 dB LBO ........................................................................................................................................ 99 Transmit Waveform Value For DS1 -15.0 dB LBO .................................................................................................................................... 100 Transmit Waveform Value For DS1 -22.5 dB LBO .................................................................................................................................... 100 Related Bit / Register In Chapter 3.24 ....................................................................................................................................................... 100 Impedance Matching Value For The Transmitter ...................................................................................................................................... 102 Related Bit / Register In Chapter 3.25 & Chapter 3.26 .............................................................................................................................. 102 Related Bit / Register In Chapter 3.27.1 .................................................................................................................................................... 103 Related Bit / Register In Chapter 3.27.2 & Chapter 3.27.3 ........................................................................................................................ 106 Related Bit / Register In Chapter 3.28 ....................................................................................................................................................... 107 Parallel Microprocessor Interface .............................................................................................................................................................. 110 Related Bit / Register In Chapter 4 ............................................................................................................................................................ 111 IR Code ...................................................................................................................................................................................................... 358 IDR ............................................................................................................................................................................................................. 359 Boundary Scan (BS) Sequence ................................................................................................................................................................. 359 TAP Controller State Description ............................................................................................................................................................... 361 List of Tables 9 August 20, 2009 List of Figures Figure 1. 100-Pin TQFP (Top View) ............................................................................................................................................................................ 14 Figure 2. Receive / Transmit Line Circuit .................................................................................................................................................................... 25 Figure 3. Receive Path Monitoring (Twisted Pair) ....................................................................................................................................................... 26 Figure 4. Transmit Path Monitoring (Twisted Pair) ...................................................................................................................................................... 26 Figure 5. Receive Path Monitoring (COAX) ................................................................................................................................................................ 27 Figure 6. Transmit Path Monitoring(COAX) ................................................................................................................................................................ 27 Figure 7. Jitter Attenuator ............................................................................................................................................................................................ 29 Figure 8. AMI Bipolar Violation Error ........................................................................................................................................................................... 31 Figure 9. B8ZS Excessive Zero Error ......................................................................................................................................................................... 31 Figure 10. HDB3 Code Violation & Excessive Zero Error ............................................................................................................................................ 31 Figure 11. E1 Frame Searching Process ..................................................................................................................................................................... 42 Figure 12. Basic Frame Searching Process ................................................................................................................................................................ 43 Figure 13. TS16 Structure Of CAS Signaling Multi-Frame .......................................................................................................................................... 45 Figure 14. Standard HDLC Packet .............................................................................................................................................................................. 56 Figure 15. Overhead Indication In The FIFO ............................................................................................................................................................... 57 Figure 16. Signaling Output In T1/J1 Mode ................................................................................................................................................................. 61 Figure 17. Signaling Output In E1 Mode ...................................................................................................................................................................... 61 Figure 18. T1/J1 To E1 Format Mapping - G.802 Mode .............................................................................................................................................. 66 Figure 19. T1/J1 To E1 Format Mapping - One Filler Every Fourth Channel Mode .................................................................................................... 66 Figure 20. T1/J1 To E1 Format Mapping - Continuous Channels Mode ..................................................................................................................... 67 Figure 21. No Offset When FE = 1 & DE = 1 In Receive Path .................................................................................................................................... 68 Figure 22. No Offset When FE = 0 & DE = 0 In Receive Path .................................................................................................................................... 68 Figure 23. No Offset When FE = 0 & DE = 1 In Receive Path .................................................................................................................................... 69 Figure 24. No Offset When FE = 1 & DE = 0 In Receive Path .................................................................................................................................... 69 Figure 25. E1 To T1/J1 Format Mapping - G.802 Mode .............................................................................................................................................. 74 Figure 26. E1 To T1/J1 Format Mapping - One Filler Every Fourth Channel Mode .................................................................................................... 74 Figure 27. E1 To T1/J1 Format Mapping - Continuous Channels Mode ..................................................................................................................... 75 Figure 28. No Offset When FE = 1 & DE = 1 In Transmit Path ................................................................................................................................... 76 Figure 29. No Offset When FE = 0 & DE = 0 In Transmit Path ................................................................................................................................... 76 Figure 30. No Offset When FE = 0 & DE = 1 In Transmit Path ................................................................................................................................... 77 Figure 31. No Offset When FE = 1 & DE = 0 In Transmit Path ................................................................................................................................... 77 Figure 32. DSX-1 Waveform Template ........................................................................................................................................................................ 93 Figure 33. T1/J1 Pulse Template Measurement Circuit .............................................................................................................................................. 93 Figure 34. E1 Waveform Template .............................................................................................................................................................................. 93 Figure 35. E1 Pulse Template Measurement Circuit ................................................................................................................................................... 93 Figure 36. G.772 Non-Intrusive Monitor .................................................................................................................................................................... 105 Figure 37. Hardware Reset When Powered-Up ........................................................................................................................................................ 108 Figure 38. Hardware Reset In Normal Operation ...................................................................................................................................................... 108 Figure 39. Read Operation In SPI Mode ................................................................................................................................................................... 109 Figure 40. Write Operation In SPI Mode .................................................................................................................................................................... 109 Figure 41. JTAG Architecture .................................................................................................................................................................................... 357 Figure 42. JTAG State Diagram ................................................................................................................................................................................ 363 Figure 43. I/O Timing in Non-Multiplexed Mode ........................................................................................................................................................ 366 Figure 44. I/O Timing in Multiplexed Mode ................................................................................................................................................................ 367 Figure 45. T1/J1 Jitter Tolerance Performance Requirement .................................................................................................................................... 372 Figure 46. E1 Jitter Tolerance Performance Requirement ........................................................................................................................................ 373 Figure 47. T1/J1 Jitter Transfer Performance Requirement (AT&T62411 / GR-253-CORE / TR-TSY-000009) ....................................................... 374 Figure 48. E1 Jitter Transfer Performance Requirement (G.736) .............................................................................................................................. 375 List of Figures 10 August 20, 2009 IDT82P2282 Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER Motorola Non-Multiplexed Mode Read Cycle ........................................................................................................................................... Motorola Non-Multiplexed Mode Write Cycle ........................................................................................................................................... Intel Non-Multiplexed Mode Read Cycle .................................................................................................................................................. Intel Non-Multiplexed Mode Write Cycle .................................................................................................................................................. SPI Timing Diagram ................................................................................................................................................................................. List of Figures 11 376 377 378 379 380 August 20, 2009 Dual T1/E1/J1 Long Haul / IDT82P2282 Short Haul Transceiver FEATURES • LINE INTERFACE • • • • • • • • • • • • • • • Each link can be configured as T1, E1 or J1 Supports T1/E1/J1 long haul/short haul line interface HPS for 1+1 protection without external relays Receive sensitivity exceeds -36 dB @ 772 Hz and -43 dB @ 1024 Hz Selectable internal line termination impedance: 100 Ω (for T1), 75 Ω / 120 Ω (for E1) and 110 Ω (for J1) Supports AMI/B8ZS (for T1/J1) and AMI/HDB3 (for E1) line encoding/decoding Provides T1/E1/J1 short haul pulse templates, long haul LBO (per ANSI T1.403 and FCC68: 0 dB, -7.5 dB, -15 dB, -22 dB) and userprogrammable arbitrary pulse template Supports G.772 non-intrusive monitoring Supports T1.102 line monitor Transmit line short-circuit detection and protection Separate Transmit and Receive Jitter Attenuators (2 per link) Indicates the interval between the write pointer and the read pointer of the FIFO in JA Loss of signal indication with programmable thresholds according to ITUT-T G.775, ETS 300 233 (E1) and ANSI T1.403 (T1/J1) Supports Analog Loopback, Digital Loopback and Remote Loopback Each receiver and transmitter can be individually powered down • • • CONTROL INTERFACE • • • • • • • • • • • • Supports Serial Peripheral Interface (SPI) microprocessor and parallel Intel/Motorola non-multiplexed microprocessor interface Global hardware and software reset One general purpose I/O pin Per link power down GENERAL • • • • • • Flexible reference clock (N x 1.544 MHz or N x 2.048 MHz) (0