82V3280APFG

WAN PLL IDT82V3280 NRND - Not Recommend for New Designs FOR REPLACEMENT DEVICE USE IDT82V3280A Version 7 April 15, 2015 6024 Silver Creek Valley Road, San Jose, CA 95138 Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775 Printed in U.S.A. © 2009 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc. LIFE SUPPORT POLICY Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT. 1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Table of Contents NRND - Not Recommend for New Designs FEATURES .............................................................................................................................................................................. 9 HIGHLIGHTS.................................................................................................................................................................................................... 9 MAIN FEATURES ............................................................................................................................................................................................ 9 OTHER FEATURES ......................................................................................................................................................................................... 9 APPLICATIONS....................................................................................................................................................................... 9 DESCRIPTION....................................................................................................................................................................... 10 FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 11 1 PIN ASSIGNMENT ........................................................................................................................................................... 12 2 PIN DESCRIPTION .......................................................................................................................................................... 13 3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 19 3.1 3.2 3.3 RESET ........................................................................................................................................................................................................... 19 MASTER CLOCK .......................................................................................................................................................................................... 19 INPUT CLOCKS & FRAME SYNC SIGNAL ................................................................................................................................................. 20 3.3.1 Input Clocks .................................................................................................................................................................................... 20 3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 20 3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 21 3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 23 3.5.1 LOS Monitoring .............................................................................................................................................................................. 23 3.5.2 Activity Monitoring ......................................................................................................................................................................... 23 3.5.3 Frequency Monitoring ................................................................................................................................................................... 24 3.6 T0 / T4 DPLL INPUT CLOCK SELECTION .................................................................................................................................................. 25 3.6.1 External Fast Selection (T0 only) .................................................................................................................................................. 25 3.6.2 Forced Selection ............................................................................................................................................................................ 26 3.6.3 Automatic Selection ....................................................................................................................................................................... 26 3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 27 3.7.1 T0 / T4 DPLL Locking Detection ................................................................................................................................................... 27 3.7.1.1 Fast Loss .......................................................................................................................................................................... 27 3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 27 3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 27 3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 27 3.7.2 Locking Status ............................................................................................................................................................................... 27 3.7.3 Phase Lock Alarm (T0 only) .......................................................................................................................................................... 28 3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 29 3.8.1 Input Clock Validity ........................................................................................................................................................................ 29 3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 29 3.8.2.1 Revertive Switch ............................................................................................................................................................... 29 3.8.2.2 Non-Revertive Switch (T0 only) ........................................................................................................................................ 30 3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 30 3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 31 3.9.1 T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 31 3.9.2 T4 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 33 3.10 T0 / T4 DPLL OPERATING MODE ............................................................................................................................................................... 34 3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 34 3.10.1.1 Free-Run Mode ................................................................................................................................................................ 34 3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 34 3.10.1.3 Locked Mode .................................................................................................................................................................... 34 Table of Contents 3 April 15, 2015 IDT82V3280 WAN PLL 3.14 3.15 3.16 3.17 3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 34 3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 34 3.10.1.5 Holdover Mode ................................................................................................................................................................. 34 3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 35 3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 35 3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 35 3.10.1.5.4 Manual ........................................................................................................................................................... 35 3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 35 3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 35 3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 35 3.10.2.1 Free-Run Mode ................................................................................................................................................................ 35 3.10.2.2 Locked Mode .................................................................................................................................................................... 35 3.10.2.3 Holdover Mode ................................................................................................................................................................. 35 T0 / T4 DPLL OUTPUT ................................................................................................................................................................................. 37 3.11.1 PFD Output Limit ............................................................................................................................................................................ 37 3.11.2 Frequency Offset Limit .................................................................................................................................................................. 37 3.11.3 PBO (T0 only) ................................................................................................................................................................................. 37 3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 37 3.11.5 Four Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 37 3.11.5.1 T0 Path ............................................................................................................................................................................. 37 3.11.5.2 T4 Path ............................................................................................................................................................................. 38 T0 / T4 APLL ................................................................................................................................................................................................. 39 OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 39 3.13.1 Output Clocks ................................................................................................................................................................................. 39 3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 42 MASTER / SLAVE CONFIGURATION ......................................................................................................................................................... 44 INTERRUPT SUMMARY ............................................................................................................................................................................... 45 T0 AND T4 SUMMARY ................................................................................................................................................................................. 45 POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 46 4.1 MASTER / SLAVE APPLICATION ............................................................................................................................................................... 47 5.1 5.2 5.3 5.4 5.5 EPROM MODE .............................................................................................................................................................................................. 49 MULTIPLEXED MODE .................................................................................................................................................................................. 50 INTEL MODE ................................................................................................................................................................................................. 52 MOTOROLA MODE ...................................................................................................................................................................................... 54 SERIAL MODE .............................................................................................................................................................................................. 56 7.1 7.2 REGISTER MAP ............................................................................................................................................................................................ 59 REGISTER DESCRIPTION ........................................................................................................................................................................... 65 7.2.1 Global Control Registers ............................................................................................................................................................... 65 7.2.2 Interrupt Registers ......................................................................................................................................................................... 74 7.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 79 7.2.4 Input Clock Quality Monitoring Configuration & Status Registers ......................................................................................... 102 7.2.5 T0 / T4 DPLL Input Clock Selection Registers ........................................................................................................................... 116 7.2.6 T0 / T4 DPLL State Machine Control Registers ......................................................................................................................... 120 7.2.7 T0 / T4 DPLL & APLL Configuration Registers .......................................................................................................................... 122 7.2.8 Output Configuration Registers .................................................................................................................................................. 136 7.2.9 PBO & Phase Offset Control Registers ...................................................................................................................................... 146 7.2.10 Synchronization Configuration Registers ................................................................................................................................. 148 3.11 3.12 3.13 4 TYPICAL APPLICATION ................................................................................................................................................. 47 5 MICROPROCESSOR INTERFACE .................................................................................................................................. 48 6 JTAG ................................................................................................................................................................................ 58 7 PROGRAMMING INFORMATION .................................................................................................................................... 59 8 THERMAL MANAGEMENT ........................................................................................................................................... 149 8.1 JUNCTION TEMPERATURE ...................................................................................................................................................................... 149 Table of Contents 4 April 15, 2015 IDT82V3280 WAN PLL 8.2 8.3 8.4 EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 149 HEATSINK EVALUATION .......................................................................................................................................................................... 149 TQFP EPAD THERMAL RELEASE PATH ................................................................................................................................................. 150 9.1 9.2 9.3 ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 151 RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 151 I/O SPECIFICATIONS ................................................................................................................................................................................. 152 9.3.1 AMI Input / Output Port ................................................................................................................................................................ 152 9.3.1.1 Structure ......................................................................................................................................................................... 152 9.3.1.2 I/O Level ......................................................................................................................................................................... 152 9.3.1.3 Over-Voltage Protection ................................................................................................................................................. 154 9.3.2 CMOS Input / Output Port ............................................................................................................................................................ 154 9.3.3 PECL / LVDS Input / Output Port ................................................................................................................................................ 155 9.3.3.1 PECL Input / Output Port ................................................................................................................................................ 155 9.3.3.2 LVDS Input / Output Port ................................................................................................................................................ 157 9.3.3.3 Single-Ended Input for Differential Input ........................................................................................................................ 158 JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 159 OUTPUT WANDER GENERATION ............................................................................................................................................................ 162 INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 163 OUTPUT CLOCK TIMING ........................................................................................................................................................................... 164 9 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 151 9.4 9.5 9.6 9.7 PACKAGE DIMENSIONS.................................................................................................................................................... 169 ORDERING INFORMATION................................................................................................................................................ 172 Table of Contents 5 April 15, 2015 List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Table 30: Table 31: Table 32: Table 33: Table 34: Table 35: Table 36: Table 37: Table 38: Table 39: Table 40: Table 41: Table 42: Table 43: Table 44: Table 45: Table 46: Table 47: Table 48: Pin Description ............................................................................................................................................................................................. 13 Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 19 Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 20 Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 22 Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 24 Input Clock Selection for T0 Path ................................................................................................................................................................ 25 Input Clock Selection for T4 Path ................................................................................................................................................................ 25 External Fast Selection ................................................................................................................................................................................ 25 Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 26 Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 27 Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 27 Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 28 Conditions of Qualified Input Clocks Available for T0 & T4 Selection ......................................................................................................... 29 Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 30 T0 DPLL Operating Mode Control ............................................................................................................................................................... 31 T4 DPLL Operating Mode Control ............................................................................................................................................................... 33 Related Bit / Register in Chapter 3.9 ........................................................................................................................................................... 33 Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 34 Frequency Offset Control in Holdover Mode ............................................................................................................................................... 35 Holdover Frequency Offset Read ................................................................................................................................................................ 35 Related Bit / Register in Chapter 3.10 ......................................................................................................................................................... 36 Related Bit / Register in Chapter 3.11 ......................................................................................................................................................... 38 Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 39 Outputs on OUT1 ~ OUT7 if Derived from T0/T4 DPLL Outputs ................................................................................................................ 40 Outputs on OUT1 ~ OUT7 if Derived from T0/T4 APLL .............................................................................................................................. 41 Outputs on OUT8 & OUT9 ........................................................................................................................................................................... 41 Synchronization Control ............................................................................................................................................................................... 42 Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 43 Device Master / Slave Control ..................................................................................................................................................................... 44 Related Bit / Register in Chapter 3.15 ......................................................................................................................................................... 45 Microprocessor Interface ............................................................................................................................................................................. 48 Access Timing Characteristics in EPROM Mode ......................................................................................................................................... 49 Read Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 50 Write Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 51 Read Timing Characteristics in Intel Mode .................................................................................................................................................. 52 Write Timing Characteristics in Intel Mode .................................................................................................................................................. 53 Read Timing Characteristics in Motorola Mode ........................................................................................................................................... 54 Write Timing Characteristics in Motorola Mode ........................................................................................................................................... 55 Read Timing Characteristics in Serial Mode ................................................................................................................................................ 56 Write Timing Characteristics in Serial Mode ................................................................................................................................................ 57 JTAG Timing Characteristics ....................................................................................................................................................................... 58 Register List and Map .................................................................................................................................................................................. 59 Power Consumption and Maximum Junction Temperature ....................................................................................................................... 149 Thermal Data ............................................................................................................................................................................................. 149 Absolute Maximum Rating ......................................................................................................................................................................... 151 Recommended Operation Conditions ........................................................................................................................................................ 151 AMI Input / Output Port Electrical Characteristics ...................................................................................................................................... 153 CMOS Input Port Electrical Characteristics ............................................................................................................................................... 154 List of Tables 6 April 15, 2015 IDT82V3280 Table 49: Table 50: Table 51: Table 52: Table 53: Table 54: Table 55: Table 56: Table 57: Table 58: Table 59: Table 60: Table 61: Table 62: Table 63: WAN PLL CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics ................................................................................................ CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ........................................................................................... CMOS Output Port Electrical Characteristics ............................................................................................................................................ PECL Input / Output Port Electrical Characteristics ................................................................................................................................... LVDS Input / Output Port Electrical Characteristics ................................................................................................................................... Output Clock Jitter Generation .................................................................................................................................................................. Output Clock Phase Noise ......................................................................................................................................................................... Input Jitter Tolerance (155.52 MHz) .......................................................................................................................................................... Input Jitter Tolerance (1.544 MHz) ............................................................................................................................................................ Input Jitter Tolerance (2.048 MHz) ............................................................................................................................................................ Input Jitter Tolerance (8 kHz) .................................................................................................................................................................... T0 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... T4 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... Input/Output Clock Timing 3 ...................................................................................................................................................................... Output Clock Timing .................................................................................................................................................................................. List of Tables 7 154 154 154 156 157 159 160 160 160 160 160 161 161 163 164 April 15, 2015 List of Figures Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11 Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 12 Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 21 Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 23 Figure 5. External Fast Selection ................................................................................................................................................................................ 25 Figure 6. Qualified Input Clocks for Automatic Selection ............................................................................................................................................ 26 Figure 7. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 32 Figure 8. T4 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 33 Figure 9. On Target Frame Sync Input Signal Timing ................................................................................................................................................. 42 Figure 10. 0.5 UI Early Frame Sync Input Signal Timing ............................................................................................................................................. 42 Figure 11. 0.5 UI Late Frame Sync Input Signal Timing .............................................................................................................................................. 43 Figure 12. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 43 Figure 13. Physical Connection Between Two Devices .............................................................................................................................................. 44 Figure 14. IDT82V3280 Power Decoupling Scheme ................................................................................................................................................... 46 Figure 15. Typical Application ...................................................................................................................................................................................... 47 Figure 16. EPROM Access Timing Diagram ............................................................................................................................................................... 49 Figure 17. Multiplexed Read Timing Diagram ............................................................................................................................................................. 50 Figure 18. Multiplexed Write Timing Diagram .............................................................................................................................................................. 51 Figure 19. Intel Read Timing Diagram ......................................................................................................................................................................... 52 Figure 20. Intel Write Timing Diagram ......................................................................................................................................................................... 53 Figure 21. Motorola Read Timing Diagram .................................................................................................................................................................. 54 Figure 22. Motorola Write Timing Diagram .................................................................................................................................................................. 55 Figure 23. Serial Read Timing Diagram (CLKE Asserted Low) ................................................................................................................................... 56 Figure 24. Serial Read Timing Diagram (CLKE Asserted High) .................................................................................................................................. 56 Figure 25. Serial Write Timing Diagram ....................................................................................................................................................................... 57 Figure 26. JTAG Interface Timing Diagram ................................................................................................................................................................. 58 Figure 27. Assembly for Expose Pad thermal Release Path (Side View) ................................................................................................................. 150 Figure 28. 64 kHz + 8 kHz Signal Structure .............................................................................................................................................................. 152 Figure 29. 64 kHz + 8 kHz + 0.4 kHz Signal Structure .............................................................................................................................................. 152 Figure 30. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Signal Input Level ................................................................................................................ 152 Figure 31. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Signal Output Level ............................................................................................................. 152 Figure 32. AMI Input / Output Port Line Termination (Recommended) ..................................................................................................................... 153 Figure 33. Recommended PECL Input Port Line Termination .................................................................................................................................. 155 Figure 34. Recommended PECL Output Port Line Termination ................................................................................................................................ 155 Figure 35. Recommended LVDS Input Port Line Termination .................................................................................................................................. 157 Figure 36. Recommended LVDS Output Port Line Termination ................................................................................................................................ 157 Figure 37. Example of Single-Ended Signal to Drive Differential Input ..................................................................................................................... 158 Figure 38. Output Wander Generation ...................................................................................................................................................................... 162 Figure 39. Input / Output Clock Timing ...................................................................................................................................................................... 163 Figure 40. 100-Pin EQG Package Dimensions (a) (in Millimeters) ............................................................................................................................ 169 Figure 41. 100-Pin EQG Package Dimensions (b) (in Millimeters) ............................................................................................................................ 170 Figure 42. EQG100 Recommended Land Pattern with Exposed Pad (in Millimeters) .............................................................................................. 171 List of Figures 8 April 15, 2015 WAN PLL IDT82V3280 NRND - Not Recommend for New Designs FEATURES • HIGHLIGHTS • • The first single PLL chip: • Features 0.5 mHz to 560 Hz bandwidth • Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/ Option I) jitter generation requirements • Provides node clocks for Cellular and WLL base-station (GSM and 3G networks) • Provides clocks for DSL access concentrators (DSLAM), especially for Japan TCM-ISDN network timing based ADSL equipments • FOR REPLACEMENT DEVICE USE IDT82V3280A • • • • • • • MAIN FEATURES • • • • • • • • • • • Provides an integrated single-chip solution for Synchronous Equipment Timing Source, including Stratum 2, 3E, 3, SMC, 4E and 4 clocks Employs DPLL and APLL to feature excellent jitter performance and minimize the number of the external components Integrates T0 DPLL and T4 DPLL; T4 DPLL locks independently or locks to T0 DPLL Supports Forced or Automatic operating mode switch controlled by an internal state machine; the primary operating modes are FreeRun, Locked and Holdover Supports programmable DPLL bandwidth (0.5 mHz to 560 Hz in 19 steps) and damping factor (1.2 to 20 in 5 steps) Supports 1.1X10-5 ppm absolute holdover accuracy and 4.4X10-8 ppm instantaneous holdover accuracy Supports PBO to minimize phase transients on T0 DPLL output to be no more than 0.61 ns Supports phase absorption when phase-time changes on T0 selected input clock are greater than a programmable limit over an interval of less than 0.1 seconds Supports programmable input-to-output phase offset adjustment Limits the phase and frequency offset of the outputs Supports manual and automatic selected input clock switch • Supports automatic hitless selected input clock switch on clock failure Supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing Provides a 2 kHz, 4 kHz or 8 kHz frame sync input signal, and a 2 kHz and an 8 kHz frame sync output signals Provides 14 input clocks whose frequency cover from 2 kHz to 622.08 MHz Provides 9 output clocks whose frequency cover from 1 Hz to 622.08 MHz Provides output clocks for BITS, GPS, 3G, GSM, etc. Supports AMI, PECL/LVDS and CMOS input/output technologies Supports master clock calibration Supports Master/Slave application (two chips used together) to enable system protection against single chip failure Meets Telcordia GR-1244-CORE, GR-253-CORE, GR-1377CORE, ITU-T G.812, ITU-T G.813 and ITU-T G.783 criteria OTHER FEATURES • • • • Multiple microprocessor interface modes: EPROM, Multiplexed, Intel, Motorola and Serial IEEE 1149.1 JTAG Boundary Scan Single 3.3 V operation with 5 V tolerant CMOS I/Os 100-pin TQFP package, Green package options available APPLICATIONS • • • • • • • • • • BITS / SSU SMC / SEC (SONET / SDH) DWDM cross-connect and transmission equipments Central Office Timing Source and Distribution Core and access IP switches / routers Gigabit and Terabit IP switches / routers IP and ATM core switches and access equipments Cellular and WLL base-station node clocks Broadband and multi-service access equipments Any other telecom equipments that need synchronous equipment system timing IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 9  2009 Integrated Device Technology, Inc. April 15, 2015 DSC-6772/7 IDT82V3280 WAN PLL DESCRIPTION quency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations. The IDT82V3280 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 2, 3E, 3, SMC, 4E and 4 clocks in SONET / SDH equipments, DWDM and Wireless base station, such as GSM, 3G, DSL concentrator, Router and Access Network applications. If the DPLL outputs are processed by T0/T4 APLL, the outputs of the device will be in a better jitter/wander performance. The device provides programmable DPLL bandwidths: 0.5 mHz to 560 Hz in 19 steps and damping factors: 1.2 to 20 in 5 steps. Different settings cover all SONET / SDH clock synchronization requirements. The device supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing. A high stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ±741 ppm. Based on ITU-T G.783 and Telcordia GR-253-CORE, the device consists of T0 and T4 paths. The T0 path is a high quality and highly configurable path to provide system clock for node timing synchronization within a SONET / SDH network. The T4 path is simpler and less configurable for equipment synchronization. The T4 path locks independently from the T0 path or locks to the T0 path. All the read/write registers are accessed through a microprocessor interface. The device supports five microprocessor interface modes: EPROM, Multiplexed, Intel, Motorola and Serial. In general, the device can be used in Master/Slave application. In this application, two devices should be used together to enable system protection against single chip failure. See Chapter 4 Typical Application for details. An input clock is automatically or manually selected for T0 and T4 each for DPLL locking. Both the T0 and T4 paths support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the fre- Description 10 April 15, 2015 Functional Block Diagram 11 Priority Input Pre-Divider EX_SYNC1 Priority Input Pre-Divider Selection Priority Priority Priority Input Pre-Divider Input Pre-Divider Priority Input Pre-Divider Priority Input Pre-Divider Priority Priority Input Pre-Divider Input Pre-Divider Priority Input Pre-Divider Input Pre-Divider Priority Input Pre-Divider Priority Priority Input Pre-Divider Input Pre-Divider Priority Input Pre-Divider IN14 IN9 IN10 IN11 IN12 IN13 IN7 IN8 IN3 IN4 IN5 IN6 IN1 IN2 Input T0 Input Selector Monitors T4 Input Selector Divider T0 PFD & LPF MUX T4 DPLL OSCI APLL PBO Phase Offset T0 8 kHz Divider T4 PFD & LPF Microprocessor Interface T0 DPLL 12E1/24T1/E3/T3 16E1/16T1 GSM/OBSAI/16E1/16T1 77.76 MHz 8 k Divider T0 77.76 MHz 12E1/24T1/E3/T3 16E1/16T1 GSM/GPS/16E1/16T1 77.76 MHz JTAG T0 APLL MUX T4 APLL MUX T0 APLL T4 APLL Output From T4 16E1/16T1 From T0 16E1/16T1 From T4 77.76 MHz From T0 77.76 MHz 10 10 10 10 10 10 10 OUT9 MUX OUT8 MUX OUT7 MUX OUT6 MUX OUT5 MUX OUT4 MUX OUT3 MUX OUT2 MUX OUT1 MUX OUT9 FRSYNC_8K MFRSYNC_2K Auto Divider Auto Divider OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 Auto Divider Auto Divider Divider Divider Divider Divider Divider Divider Divider IDT82V3280 WAN PLL FUNCTIONAL BLOCK DIAGRAM Figure 1. Functional Block Diagram April 15, 2015 IDT82V3280 PIN ASSIGNMENT 76 79 78 77 80 88 87 86 85 84 83 82 81 92 91 90 89 94 93 1 2 75 74 3 4 5 73 72 71 6 7 8 9 10 11 70 69 68 67 66 65 IDT82V3280 12 13 14 15 64 63 62 61 60 59 58 57 56 55 16 17 18 19 20 21 47 48 49 41 42 43 44 45 46 37 38 39 40 33 34 35 36 30 31 32 VDD_AMI OUT8_NEG OUT8_POS GND_AMI FRSYNC_8K MFRSYNC_2K GND_DIFF1 VDD_DIFF1 OUT6_POS OUT6_NEG OUT7_POS OUT7_NEG GND_DIFF2 VDD_DIFF2 IN5_POS IN5_NEG IN6_POS IN6_NEG NC EX_SYNC1 IN3 IN4 IN7 DGND4 VDDD4 28 29 25 RDY RST ALE/SCLK RD WR CS A0/SDI A1/CLKE A2 A3 A4 A5 A6 DGND5 VDDD5 MPU_MODE0 MPU_MODE1 MPU_MODE2 IN14 IN13 IN12 IN11 IN10 IN9 IN8 50 54 53 52 51 22 23 24 26 27 AGND TRST IC1 IC2 AGND1 VDDA1 TMS INT_REQ TCK OSCI DGND1 VDDD1 VDDD3 DGND3 DGND2 VDDD2 IC3 FF_SRCSW VDDA2 AGND2 TDO IC4 TDI IN1 IN2 97 96 95 100 99 98 SONET/SDH MS/SL IC7 IC6 IC5 OUT9 OUT5 OUT4 AGND3 VDDA3 OUT3 OUT2 OUT1 DGND7 VDDD7 VDDD6 DGND6 AD0/SDO AD1 AD2 AD3 AD4 AD5 AD6 AD7 1 WAN PLL Figure 2. Pin Assignment (Top View) Pin Assignment 12 April 15, 2015 IDT82V3280 2 WAN PLL PIN DESCRIPTION Table 1: Pin Description Name Pin No. I/O Description 1 Type Global Control Signal OSCI 10 I CMOS FF_SRCSW 18 I pull-down CMOS MS/SL 99 I pull-up OSCI: Crystal Oscillator Master Clock A nominal 12.8000 MHz clock provided by a crystal oscillator is input on this pin. It is the master clock for the device. FF_SRCSW: External Fast Selection Enable During reset, this pin determines the default value of the EXT_SW bit (b4, 0BH) 2. The EXT_SW bit determines whether the External Fast Selection is enabled. High: The default value of the EXT_SW bit (b4, 0BH) is ‘1’ (External Fast selection is enabled); Low: The default value of the EXT_SW bit (b4, 0BH) is ‘0’ (External Fast selection is disabled). After reset, this pin selects an input clock pair for the T0 DPLL if the External Fast selection is enabled: High: Pair IN3 / IN5 is selected. Low: Pair IN4 / IN6 is selected. After reset, the input on this pin takes no effect if the External Fast selection is disabled. CMOS MS/SL: Master / Slave Selection This pin, together with the MS_SL_CTRL bit (b0, 13H), controls whether the device is configured as the Master or as the Slave. Refer to Chapter 3.14 Master / Slave Configuration for details. The signal level on this pin is reflected by the MASTER_SLAVE bit (b1, 09H). SONET/SDH 100 I pull-down CMOS SONET/SDH: SONET / SDH Frequency Selection During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H): High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET); Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH). After reset, the value on this pin takes no effect. RST 74 I pull-up CMOS RST: Reset A low pulse of at least 50 µs on this pin resets the device. After this pin is high, the device will still be held in reset state for 500 ms (typical). Frame Synchronization Input Signal EX_SYNC1 45 I pull-down CMOS EX_SYNC1: External Sync Input 1 A 2 kHz, 4 kHz or 8 kHz signal is input on this pin. Input Clock IN1 24 I AMI IN2 25 I AMI IN3 46 I pull-down CMOS IN4 47 I pull-down CMOS Pin Description IN1: Input Clock 1 A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is input on this pin. IN2: Input Clock 2 A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is input on this pin. IN3: Input Clock 3 A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin. IN4: Input Clock 4 A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin. 13 April 15, 2015 IDT82V3280 WAN PLL Table 1: Pin Description (Continued) Name Pin No. IN5_POS 40 IN5_NEG 41 IN6_POS 42 IN6_NEG 43 IN7 48 IN8 51 IN9 52 IN10 53 IN11 54 IN12 55 IN13 56 IN14 57 I/O Description 1 Type IN5_POS / IN5_NEG: Positive / Negative Input Clock 5 A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz I PECL/LVDS clock is differentially input on this pair of pins. Whether the clock signal is PECL or LVDS is automatically detected. Single-ended input for differential input is also supported. Refer to Chapter 9.3.3.3 SingleEnded Input for Differential Input. IN6_POS / IN6_NEG: Positive / Negative Input Clock 6 A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz I PECL/LVDS clock is differentially input on this pair of pins. Whether the clock signal is PECL or LVDS is automatically detected. Single-ended input for differential input is also supported. Refer to Chapter 9.3.3.3 SingleEnded Input for Differential Input. IN7: Input Clock 7 I CMOS A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, pull-down 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin. IN8: Input Clock 8 I CMOS A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, pull-down 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin. IN9: Input Clock 9 I CMOS A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, pull-down 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin. IN10: Input Clock 10 I CMOS A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, pull-down 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin. IN11: Input Clock 11 A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, I CMOS 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin. pull-down In Slave operation, the frequency of the T0 selected input clock IN11 is recommended to be 6.48 MHz. IN12: Input Clock 12 I CMOS A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, pull-down 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin. IN13: Input Clock 13 I CMOS A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, pull-down 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin. IN14: Input Clock 14 I CMOS A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, pull-down 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin. Output Frame Synchronization Signal FRSYNC_8K 30 O CMOS MFRSYNC_2K 31 O CMOS FRSYNC_8K: 8 kHz Frame Sync Output An 8 kHz signal is output on this pin. MFRSYNC_2K: 2 kHz Multiframe Sync Output A 2 kHz signal is output on this pin. Output Clock OUT1 Pin Description 88 O CMOS OUT1: Output Clock 1 A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7, 5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is output on this pin. 14 April 15, 2015 IDT82V3280 WAN PLL Table 1: Pin Description (Continued) Name Pin No. I/O OUT2 89 O OUT3 90 O OUT4 93 O OUT5 94 O OUT6_POS 34 OUT6_NEG 35 OUT7_POS 36 OUT7_NEG 37 OUT8_POS 28 OUT8_NEG 27 OUT9 95 O O O O Description 1 Type OUT2: Output Clock 2 A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7, CMOS 5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is output on this pin. OUT3: Output Clock 3 A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7, CMOS 5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is output on this pin. OUT4: Output Clock 4 A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7, CMOS 5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is output on this pin. OUT5: Output Clock 5 A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7, CMOS 5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is output on this pin. OUT6_POS / OUT6_NEG: Positive / Negative Output Clock 6 A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7, PECL/LVDS 5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz clock is differentially output on this pair of pins. OUT7_POS / OUT7_NEG: Positive / Negative Output Clock 7 A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7, PECL/LVDS 5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz clock is differentially output on this pair of pins. OUT8_POS / OUT8_NEG: Positive / Negative Output Clock 8 A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is differentially output on this AMI pair of pins. CMOS OUT9: Output Clock 9 A 1.544 MHz (SONET) / 2.048 MHz (SDH) BITS/SSU clock is output on this pin. Microprocessor Interface CS 70 I pull-up CMOS INT_REQ 8 O CMOS MPU_MODE0 60 MPU_MODE1 59 I pull-down CMOS MPU_MODE2 58 Pin Description CS: Chip Selection A transition from high to low must occur on this pin for each read or write operation and this pin should remain low until the operation is over. INT_REQ: Interrupt Request This pin is used as an interrupt request. The output characteristics are determined by the HZ_EN bit (b1, 0CH) and the INT_POL bit (b0, 0CH). MPU_MODE[2:0]: Microprocessor Interface Mode Selection The device supports five microprocessor interface modes: EPROM, Multiplexed, Intel, Motorola and Serial. During reset, these pins determine the default value of the MPU_SEL_CNFG[2:0] bits (b2~0, 7FH) as follows: 001 (EPROM mode); 010 (Multiplexed mode); 011 (Intel mode); 100 (Motorola mode); 101 (Serial mode); 110 - 111 (Reserved). After reset, these pins are general purpose inputs. The microprocessor interface mode is selected by the MPU_SEL_CNFG[2:0] bits (b2~0, 7FH). The value of these pins is always reflected by the MPU_PIN_STS[2:0] bits (b2~0, 02H). 15 April 15, 2015 IDT82V3280 WAN PLL Table 1: Pin Description (Continued) Name Pin No. A0 / SDI 69 A1 / CLKE 68 A2 67 A3 66 A4 65 A5 64 A6 63 AD0 / SDO 83 AD1 82 AD2 81 AD3 80 AD4 79 AD5 78 AD6 77 AD7 76 I/O Description 1 Type A[6:0]: Address Bus In ERPOM, Intel and Motorola modes, these pins are the address bus of the microprocessor interface. I pull-down SDI: Serial Data Input In Serial mode, this pin is used as the serial data input. Address and data on this pin are serially clocked into the device on the rising edge of SCLK. CMOS CLKE: SCLK Active Edge Selection In Serial mode, this pin selects the active edge of SCLK to update the SDO: High - The falling edge; Low - The rising edge. In Multiplexed mode, A0/SDI, A1/CLKE and A[6:2] pins should be connected to ground. In Serial mode, A[6:2] pins should be connected to ground. AD[7:0]: Address / Data Bus In EPROM, Intel and Motorola modes, these pins are the bi-directional data bus of the microprocessor interface. In Multiplexed mode, these pins are the bi-directional address/data bus of the microprocessor interface. I/O pull-down CMOS SDO: Serial Data Output In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked out of the device on the active edge of SCLK. In Serial mode, AD[7:1] pins should be connected to ground. WR 71 I pull-up RD 72 I pull-up CMOS ALE / SCLK 73 I pull-down CMOS CMOS WR: Write Operation In Multiplexed and Intel modes, this pin is asserted low to initiate a write operation. In Motorola mode, this pin is asserted low to initiate a write operation or s asserted high to initiate a read operation. In EPROM and Serial modes, this pin should be connected to ground. RD: Read Operation In Multiplexed and Intel modes, this pin is asserted low to initiate a read operation. In EPROM, Motorola and Serial modes, this pin should be connected to ground. ALE: Address Latch Enable In Multiplexed mode, the address on AD[7:0] pins is sampled into the device on the falling edge of ALE. SCLK: Shift Clock In Serial mode, a shift clock is input on this pin. Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated on the active edge of SCLK. The active edge is determined by the CLKE. In EPROM, Intel and Motorola modes, this pin should be connected to ground. Pin Description 16 April 15, 2015 IDT82V3280 WAN PLL Table 1: Pin Description (Continued) Name RDY Pin No. 75 I/O O Type Description 1 CMOS RDY: Ready/Data Acknowledge In Multiplexed and Intel modes, a high level on this pin indicates that a read/write cycle is completed. A low level on this pin indicates that wait state must be inserted. In Motorola mode, a low level on this pin indicates that valid information on the data bus is ready for a read operation or acknowledges the acceptance of the written data during a write operation. In EPROM and Serial modes, this pin should be connected to ground. JTAG (per IEEE 1149.1) TRST 2 I pull-down CMOS TMS 7 I pull-up CMOS TCK 9 I pull-down CMOS TDI 23 I pull-up CMOS TDO 21 O CMOS TRST: JTAG Test Reset (Active Low) A low signal on this pin resets the JTAG test port. This pin should be connected to ground when JTAG is not used. TMS: JTAG Test Mode Select The signal on this pin controls the JTAG test performance and is sampled on the rising edge of TCK. TCK: JTAG Test Clock The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge of TCK and TDO is updated on the falling edge of TCK. If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely retain their state. TDI: JTAG Test Data Input The test data is input on this pin. It is clocked into the device on the rising edge of TCK. TDO: JTAG Test Data Output The test data is output on this pin. It is clocked out of the device on the falling edge of TCK. TDO pin outputs a high impedance signal except during the process of data scanning. This pin can indicate the interrupt of T0 selected input clock fail, as determined by the LOS_FLAG_ON_TDO bit (b6, 0BH). Refer to Chapter 3.8.1 Input Clock Validity for details. Power & Ground VDDD1 12 VDDD2 16 VDDD3 13 VDDD4 50 VDDD5 61 VDDD6 85 VDDD7 VDDA1 86 6 VDDA2 19 Power - VDDA3 VDD_AMI VDD_DIFF1 VDD_DIFF2 91 26 33 39 Power Power Power - Pin Description VDDDn: 3.3 V Digital Power Supply Each VDDDn should be paralleled with ground through a 0.1 µF capacitor. Power - VDDAn: 3.3 V Analog Power Supply Each VDDAn should be paralleled with ground through a 0.1 µF capacitor. VDD_AMI: 3.3 V Power Supply for AMI I/O VDD_DIFF1: 3.3 V Power Supply for OUT6 VDD_DIFF2: 3.3 V Power Supply for OUT7 17 April 15, 2015 IDT82V3280 WAN PLL Table 1: Pin Description (Continued) Name Pin No. I/O DGND1 11 DGND2 15 DGND3 14 DGND4 49 DGND5 62 DGND6 84 DGND7 AGND1 87 5 AGND2 20 Ground - AGND3 GND_DIFF1 GND_DIFF2 GND_AMI AGND 92 32 38 29 1 Ground Ground Ground Ground - Description 1 Type DGNDn: Digital Ground Ground - AGNDn: Analog Ground GND_DIFF: Ground for OUT6 GND_DIFF: Ground for OUT7 GND_AMI: Ground for AMI I/O AGND: Analog Ground Others IC1 3 IC2 4 IC3 17 IC4 22 IC5 96 IC6 97 IC7 NC 98 44 IC: Internal Connected Internal Use. These pins should be left open for normal operation. - - - - NC: Not Connected Note: 1. All the unused input pins should be connected to ground; the output of all the unused output pins are don’t-care. 2. The contents in the brackets indicate the position of the register bit/bits. 3. N x 8 kHz: 1 < N < 19440. 4. N x E1: N = 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64. 5. N x T1: N = 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96. 6. N x 13.0 MHz: N = 1, 2, 4. 7. N x 3.84 MHz: N = 1, 2, 4, 8, 16, 10, 20, 40. Pin Description 18 April 15, 2015 IDT82V3280 WAN PLL 3 FUNCTIONAL DESCRIPTION 3.2 3.1 RESET A nominal 12.8000 MHz clock, provided by a crystal oscillator, is input on the OSCI pin. This clock is provided for the device as a master clock. The master clock is used as a reference clock for all the internal circuits. A better active edge of the master clock is selected by the OSC_EDGE bit to improve jitter and wander performance. The reset operation resets all registers and state machines to their default value or status. After power on, the device must be reset for normal operation. MASTER CLOCK In fact, an offset from the nominal frequency may input on the OSCI pin. This offset can be compensated by setting the NOMINAL_FREQ_VALUE[23:0] bits. The calibration range is within ±741 ppm. For a complete reset, the RST pin must be asserted low for at least 50 µs. After the RST pin is pulled high, the device will still be in reset state for 500 ms (typical). If the RST pin is held low continuously, the device remains in reset state. The performance of the master clock should meet GR-1244-CORE, GR-253-CORE, ITU-T G.812 and G.813 criteria. Table 2: Related Bit / Register in Chapter 3.2 Bit Register Address (Hex) NOMINAL_FREQ_VALUE[23:0] OSC_EDGE NOMINAL_FREQ[23:16]_CNFG, NOMINAL_FREQ[15:8]_CNFG, NOMINAL_FREQ[7:0]_CNFG DIFFERENTIAL_IN_OUT_OSCI_CNFG 06, 05, 04 0A Functional Description 19 April 15, 2015 IDT82V3280 3.3 WAN PLL INPUT CLOCKS & FRAME SYNC SIGNAL For SDH and SONET networks, the default frequency is different. SONET / SDH frequency selection is controlled by the IN_SONET_SDH bit. During reset, the default value of the IN_SONET_SDH bit is determined by the SONET/SDH pin: high for SONET and low for SDH. After reset, the input signal on the SONET/SDH pin takes no effect. Altogether 14 clocks and 1 frame sync signal are input to the device. 3.3.1 INPUT CLOCKS The device provides 14 input clock ports. IDT82V3280 supports single-ended input for differential input. Refer to Chapter 9.3.3.3 Single-Ended Input for Differential Input. According to the input port technology, the input ports support the following technologies: • AMI • PECL/LVDS • CMOS 3.3.2 A 2 kHz, 4 kHz or 8 kHz frame sync signal is input on the EX_SYNC1 pin. It is a CMOS input. The input frequency should match the setting in the SYNC_FREQ[1:0] bits. According to the input clock source, the following clock sources are supported: • T1: Recovered clock from STM-N or OC-n • T2: PDH network synchronization timing • T3: External synchronization reference timing The frame sync input signal is used for frame sync output signal synchronization. Refer to Chapter 3.13.2 Frame SYNC Output Signals for details. Table 3: Related Bit / Register in Chapter 3.3 IN1 and IN2 support the AMI input signal only and the clock source is from T3. The input clock is a 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock. The 400HZ_SEL bit should be set to match the input frequency. Any input violation that does not meet the standard composite clock structure will induce an AMI violation. The AMI violation is indicated by the AMI1_VIOL 1 / AMI2_VIOL 1 bit. If the AMI1_VIOL 2 / AMI2_VIOL 2 bit is ‘1’, the occurrence of an AMI violation will trigger an interrupt. Bit Register Address (Hex) 400HZ_SEL IN1_CNFG IN2_CNFG 14 15 INTERRUPT3_STS 0F INTERRUPTS3_ENABLE_CNFG 12 INPUT_MODE_CNFG 09 AMI1_VIOL 1 AMI2_VIOL 1 AMI1_VIOL 2 AMI2_VIOL 2 IN_SONET_SDH SYNC_FREQ[1:0] IN3, IN4 and IN7 ~ IN14 support CMOS input signal only and the clock sources can be from T1, T2 or T3. IN5 and IN6 support PECL/LVDS input signal and automatically detect whether the signal is PECL or LVDS. The clock sources can be from T1, T2 or T3. Functional Description FRAME SYNC INPUT SIGNALS 20 April 15, 2015 IDT82V3280 3.4 WAN PLL When the DivN Divider is used for INn (3  n  14), the division factor setting should observe the following order: 1. Select an input clock by the PRE_DIV_CH_VALUE[3:0] bits; 2. Write the lower eight bits of the division factor to the PRE_DIVN_VALUE[7:0] bits; 3. Write the higher eight bits of the division factor to the PRE_DIVN_VALUE[14:8] bits. INPUT CLOCK PRE-DIVIDER Each input clock is assigned an internal Pre-Divider. The Pre-Divider is used to divide the clock frequency down to the DPLL’s required input frequency, which is no more than 38.88 MHz. For IN1 and IN2, the DPLL required frequency is fixed to 8 kHz (i.e., the corresponding IN_FREQ[3:0] bits are ‘0000’). The 8 kHz clock is extracted from the composite clock and the Pre-Divider is bypassed automatically. For IN3 ~ IN14, the DPLL required frequency is set by the corresponding IN_FREQ[3:0] bits. Once the division factor is set for the input clock selected by the PRE_DIV_CH_VALUE[3:0] bits, it is valid until a different division factor is set for the same input clock. The division factor is calculated as follows: Each Pre-Divider consists of a DivN Divider and a Lock 8k Divider. IN3 and IN4 also include an HF (High Frequency) Divider. Figure 3 shows a block diagram of the pre-dividers for an input clock. Division Factor = (the frequency of the clock input to the DivN Divider ÷ the frequency of the DPLL required clock set by the IN_FREQ[3:0] bits) - 1 When the Lock 8k Divider is used, the input clock is divided down to 8 kHz internally; the PRE_DIVN_VALUE [14:0] bits are not required. Lock 8k Divider can be used for 1.544 MHz, 2.048 MHz, 6.48 MHz, 19.44 MHz, 25.92 MHz or 38.88 MHz input clock frequency and the corresponding IN_FREQ[3:0] bits should be set to match the input frequency. For 2 kHz, 4 kHz or 8 kHz input clock frequency only, the PreDivider is bypassed and the corresponding IN_FREQ[3:0] bits should be set to match the input frequency. The input clock can be inverted, as determine by the IN_2K_4K_8K_INV bit. The DivN Divider can only divide the input clock whose frequency is lower than () 155.52 MHz. The Pre-Divider configuration and the division factor setting depend on the input clock on one of the IN3 ~ IN14 pins and the DPLL required clock. Here is an example: The input clock on the IN6 pin is 622.08 MHz; the DPLL required clock is 6.48 MHz by programming the IN_FREQ[3:0] bits of register IN6 to ‘0010’. Do the following step by step to divide the input clock: 1. Use the HF Divider to divide the clock down to 155.52 MHz: 622.08 ÷ 155.52 = 4, so set the IN6_DIV[1:0] bits to ‘01’; 2. Use the DivN Divider to divide the clock down to 6.48 MHz: Set the PRE_DIV_CH_VALUE[3:0] bits to ‘0110’; Set the DIRECT_DIV bit in Register IN6_CNFG to ‘1’ and the LOCK_8K bit in Register IN6_CNFG to ‘0’; 155.52 ÷ 6.48 = 24; 24 - 1 = 23, so set the PRE_DIVN_VALUE[14:0] bits to ‘10111’. The HF Divider, which is only available for IN5 and IN6, should be used when the input clock is higher than () 155.52 MHz. The input clock can be divided by 4, 5 or can bypass the HF Divider, as determined by the IN5_DIV[1:0]/IN6_DIV[1:0] bits correspondingly. Either the DivN Divider or the Lock 8k Divider can be used or both can be bypassed, as determined by the DIRECT_DIV bit and the LOCK_8K bit. Pre-Divider IN5_DIV[1:0] bits / IN6_DIV[1:0] bits Input Clock INn (14>n>3) HF Divider (for IN5 & IN6 only) DIRECT_DIV bit DivN Divider LOCK_8K bit Lock 8k Divider DPLL required clock Figure 3. Pre-Divider for An Input Clock Functional Description 21 April 15, 2015 IDT82V3280 WAN PLL Table 4: Related Bit / Register in Chapter 3.4 Bit IN5_DIV[1:0] IN6_DIV[1:0] IN_FREQ[3:0] IN_2K_4K_8K_INV DIRECT_DIV LOCK_8K PRE_DIV_CH_VALUE[3:0] PRE_DIVN_VALUE[14:0] Functional Description Register Address (Hex) IN5_IN6_HF_DIV_CNFG 18 IN1_CNFG ~ IN14_CNFG FR_MFR_SYNC_CNFG 14 ~ 17, 19 ~ 22 74 IN3_CNFG ~ IN14_CNFG 16, 17, 19 ~ 22 PRE_DIV_CH_CNFG PRE_DIVN[14:8]_CNFG, PRE_DIVN[7:0]_CNFG 23 25, 24 22 April 15, 2015 IDT82V3280 3.5 WAN PLL INPUT CLOCK QUALITY MONITORING Each input clock is assigned an internal leaky bucket accumulator. The input clock is monitored for each period of 128 ms and the internal leaky bucket accumulator increases by 1 when an event is detected; it decreases by 1 if no event is detected within the period set by the decay rate. The event is that an input clock drifts outside (>) ±500 ppm with respect to the master clock within a 128 ms period. The qualities of all the input clocks are always monitored in the following aspects: • LOS (loss of signal) (only for IN1 and IN2) • Activity • Frequency There are four configurations (0 - 3) for a leaky bucket accumulator. The leaky bucket configuration for an input clock is selected by the corresponding BUCKET_SEL[1:0] bits. Each leaky bucket configuration consists of four elements: upper threshold, lower threshold, bucket size and decay rate. LOS monitoring is only conducted on IN1 and IN2. Activity and frequency monitoring are conducted on all the input clocks. The qualified clocks are available for T0/T4 DPLL selection. The T0 and T4 selected input clocks have to be monitored further. Refer to Chapter 3.7 Selected Input Clock Monitoring for details. 3.5.1 The bucket size is the capability of the accumulator. If the number of the accumulated events reach the bucket size, the accumulator will stop increasing even if further events are detected. The upper threshold is a point above which a no-activity alarm is raised. The lower threshold is a point below which the no-activity alarm is cleared. The decay rate is a certain period during which the accumulator decreases by 1 if no event is detected. LOS MONITORING IN1 and IN2 support the AMI input signal. LOS monitoring is conducted on IN1 and IN2. A LOS event occurs when the amplitude of the input clock falls below +0.6 Vp-p for 1 ms; the LOS event is cleared when the amplitude rises higher than +1 Vp-p. LOS status is indicated by the AMI1_LOS 1 / AMI2_LOS 1 bit. If the AMI1_LOS 2 / AMI2_LOS 2 bit is ‘1’, the occurrence of LOS will trigger an interrupt. The leaky bucket configuration is programmed by one of four groups of register bits: the BUCKET_SIZE_n_DATA[7:0] bits, the UPPER_ THRESHOLD_n_DATA[7:0] bits, the LOWER_THRESHOLD_n_ DATA[7:0] bits and the DECAY_RATE_n_DATA[1:0] bits respectively; ‘n’ is 0 ~ 3. The input clock in LOS status is disqualified for clock selection for T0/ T4 DPLL. 3.5.2 The no-activity alarm status of the input clock is indicated by the INn_NO_ACTIVITY_ALARM bit (14  n  1). ACTIVITY MONITORING Activity is monitored by using an internal leaky bucket accumulator, as shown in Figure 4. The input clock with a no-activity alarm is disqualified for clock selection for T0/T4 DPLL. clock signal with events clock signal with no event Input Clock Decay Rate Bucket Size Upper Threshold Leaky Bucket Accumulator Lower Threshold 0 No-activity Alarm Indication Figure 4. Input Clock Activity Monitoring Functional Description 23 April 15, 2015 IDT82V3280 3.5.3 WAN PLL FREQUENCY MONITORING The input clock with a frequency hard alarm is disqualified for clock selection for T0/T4 DPLL. Frequency is monitored by comparing the input clock with a reference clock. The reference clock can be derived from the master clock or the output of T0 DPLL, as determined by the FREQ_MON_CLK bit. In addition, if the input clock is 2 kHz, 4 kHz or 8 kHz, its clock edges with respect to the reference clock are monitored. If any edge drifts outside ±5%, the input clock is disqualified for clock selection for T0/T4 DPLL. The input clock is qualified if any edge drifts inside ±5%. This function is supported only when the IN_NOISE_WINDOW bit is ‘1’. A frequency hard alarm threshold is set for frequency monitoring. If the FREQ_MON_HARD_EN bit is ‘1’, a frequency hard alarm is raised when the frequency of the input clock with respect to the reference clock is above the threshold; the alarm is cleared when the frequency is below the threshold. The frequency of each input clock with respect to the reference clock can be read by doing the following step by step: 1. Select an input clock by setting the IN_FREQ_READ_CH[3:0] bits; 2. Read the value in the IN_FREQ_VALUE[7:0] bits and calculate as follows: The frequency hard alarm threshold can be calculated as follows: Frequency Hard Alarm Threshold (ppm) = (ALL_FREQ_HARD_ THRESHOLD[3:0] + 1) X FREQ_MON_FACTOR[3:0] If the FREQ_MON_HARD_EN bit is ‘1’, the frequency hard alarm status of the input clock is indicated by the INn_FREQ_HARD_ALARM bit (14  n  1). When the FREQ_MON_HARD_EN bit is ‘0’, no frequency hard alarm is raised even if the input clock is above the frequency hard alarm threshold. Input Clock Frequency (ppm) = IN_FREQ_VALUE[7:0] X FREQ_MON_FACTOR[3:0] Note that the value set by the FREQ_MON_FACTOR[3:0] bits depends on the application. Table 5: Related Bit / Register in Chapter 3.5 Bit Register Address (Hex) INTERRUPTS3_STS 0F INTERRUPTS3_ENABLE_CNFG 12 BUCKET_SIZE_0_CNFG ~ BUCKET_SIZE_3_CNFG UPPER_THRESHOLD_0_CNFG ~ UPPER_THRESHOLD_3_CNFG LOWER_THRESHOLD_0_CNFG ~ LOWER_THRESHOLD_3_CNFG DECAY_RATE_0_CNFG ~ DECAY_RATE_3_CNFG IN1_CNFG ~ IN14_CNFG 33, 37, 3B, 3F 31, 35, 39, 3D 32, 36, 3A, 3E 34, 38, 3C, 40 14 ~ 17, 19 ~ 22 IN1_IN2_STS ~ IN13_IN14_STS 43 ~ 49 MON_SW_PBO_CNFG 0B ALL_FREQ_MON_THRESHOLD_CNFG FREQ_MON_FACTOR_CNFG PHASE_MON_PBO_CNFG IN_FREQ_READ_CH_CNFG IN_FREQ_READ_STS 2F 2E 78 41 42 AMI1_LOS 1 AMI2_LOS 1 AMI1_LOS 2 AMI2_LOS 2 BUCKET_SIZE_n_DATA[7:0] (3  n  0) UPPER_THRESHOLD_n_DATA[7:0] (3  n  0) LOWER_THRESHOLD_n_DATA[7:0] (3  n  0) DECAY_RATE_n_DATA[1:0] (3  n  0) BUCKET_SEL[1:0] INn_NO_ACTIVITY_ALARM (14  n  1) INn_FREQ_HARD_ALARM (14  n  1) FREQ_MON_CLK FREQ_MON_HARD_EN ALL_FREQ_HARD_THRESHOLD[3:0] FREQ_MON_FACTOR[3:0] IN_NOISE_WINDOW IN_FREQ_READ_CH[3:0] IN_FREQ_VALUE[7:0] Functional Description 24 April 15, 2015 IDT82V3280 3.6 WAN PLL T0 / T4 DPLL INPUT CLOCK SELECTION Automatic selection is done based on the results of input clocks quality monitoring and the related registers configuration. An input clock is selected for T0 DPLL and for T4 DPLL respectively. The selected input clock is attempted to be locked in T0/T4 DPLL. For T0 path, the EXT_SW bit and the T0_INPUT_SEL[3:0] bits determine the input clock selection, as shown in Table 6: 3.6.1 The External Fast selection is supported by T0 path only. In External Fast selection, only IN3/IN5 and IN4/IN6 pairs are available for selection. Refer to Figure 5. The results of input clocks quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring) do not affect input clock selection. Table 6: Input Clock Selection for T0 Path Control Bits EXT_SW T0_INPUT_SEL[3:0] 1 don’t-care other than 0000 0000 0 EXTERNAL FAST SELECTION (T0 ONLY) Input Clock Selection External Fast selection Forced selection Automatic selection The T0 input clock selection is determined by the FF_SRCSW pin after reset (this pin determines the default value of the EXT_SW bit during reset, refer to Chapter 2 Pin Description), the IN3_SEL_PRIORITY[3:0] bits and the IN4_SEL_PRIORITY[3:0] bits, as shown in Figure 5 and Table 8: For T4 path, the T4 DPLL may lock to a T0 DPLL output or lock independently from T0 path, as determined by the T4_LOCK_T0 bit. When the T4 DPLL locks to the T0 DPLL output, the T4 selected input clock is a 77.76 MHz or 8 kHz signal from the T0 DPLL 77.76 MHz path (refer to Chapter 3.11.5.1 T0 Path), as determined by the T0_FOR_T4 bit. When the T4 path locks independently from the T0 path, the T4 DPLL input clock selection is determined by the T4_INPUT_SEL[3:0] bits. Refer to Table 7: IN3_SEL_PRIORITY[3:0] bits FF_SRCSW pin IN3 IN5 attempted to be locked in T0 DPLL Table 7: Input Clock Selection for T4 Path Control Bits - T4_INPUT_SEL[3:0] Input Clock Selection IN4 other than 0000 0000 Forced selection Automatic selection IN6 External Fast selection is done between IN3/IN5 and IN4/IN6 pairs. IN4_SEL_PRIORITY[3:0] bits Forced selection is done by setting the related registers. Figure 5. External Fast Selection Table 8: External Fast Selection Control Pin & Bits FF_SRCSW (after reset) IN3_SEL_PRIORITY[3:0] IN4_SEL_PRIORITY[3:0] high 0000 other than 0000 don’t-care low don’t-care 0000 other than 0000 Functional Description 25 the Selected Input Clock IN5 IN3 IN6 IN4 April 15, 2015 IDT82V3280 3.6.2 WAN PLL FORCED SELECTION depends on the results of input clock quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring). Locking allowance is configured by the corresponding INn_VALID bit(14  n  1). Refer to Figure 6. In all the qualified input clocks, the one with the highest priority is selected. The priority is set by the corresponding INn_SEL_PRIORITY[3:0] bits (14  n  1). If more than one qualified input clock INn is available and has the same priority, the input clock with the smallest ‘n’ is selected. In Forced selection, the selected input clock is set by the T0_INPUT_SEL[3:0] / T4_INPUT_SEL[3:0] bits. The results of input clocks quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring) do not affect the input clock selection. 3.6.3 AUTOMATIC SELECTION In Automatic selection, the input clock selection is determined by its validity, priority and locking allowance configuration. The validity Validity Priority No Locking Allowance No No INn_SEL_PRIORITY[3:0] '0000', (14 > n > 1) Input Clock Quality Monitoring (LOS, Activity, Frequency) INn = '1', (14 > n > 1) INn_VALID = '0', (14 > n > 1) Yes Yes Yes All qualified input clocks are available for Automatic selection Figure 6. Qualified Input Clocks for Automatic Selection Table 9: Related Bit / Register in Chapter 3.6 Bit Register Address (Hex) EXT_SW T0_INPUT_SEL[3:0] T4_LOCK_T0 T0_FOR_T4 T4_INPUT_SEL[3:0] MON_SW_PBO_CNFG T0_INPUT_SEL_CNFG 0B 50 T4_INPUT_SEL_CNFG 51 INn_SEL_PRIORITY[3:0] (14  n  1) INn_VALID (14  n  1) INn (14  n  1) T4_T0_SEL IN1_IN2_SEL_PRIORITY_CNFG ~ IN13_IN14_SEL_PRIORITY_CNFG REMOTE_INPUT_VALID1_CNFG, REMOTE_INPUT_VALID2_CNFG INPUT_VALID1_STS, INPUT_VALID2_STS T4_T0_REG_SEL_CNFG 26 ~ 2C * 4C, 4D 4A, 4B 07 Note: * The setting in the 26 ~ 2C registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit. Functional Description 26 April 15, 2015 IDT82V3280 3.7 WAN PLL SELECTED INPUT CLOCK MONITORING 3.7.1.3 The T0/T4 DPLL compares the selected input clock with the feedback signal. If the phase-compared result exceeds the fine phase limit programmed by the PH_LOS_FINE_LIMT[2:0] bits, a fine phase loss is triggered. It is cleared once the phase-compared result is within the fine phase limit. The quality of the selected input clock is always monitored (refer to Chapter 3.5 Input Clock Quality Monitoring) and the DPLL locking status is always monitored. 3.7.1 T0 / T4 DPLL LOCKING DETECTION The following events is always monitored: • Fast Loss; • Coarse Phase Loss; • Fine Phase Loss; • Hard Limit Exceeding. 3.7.1.1 The occurrence of the fine phase loss will result in T0/T4 DPLL unlocked if the FINE_PH_LOS_LIMT_EN bit is ‘1’. 3.7.1.4 A fast loss is triggered when the selected input clock misses 2 consecutive clock cycles. It is cleared once an active clock edge is detected. For T0 path, the occurrence of the fast loss will result in T0 DPLL unlocked if the FAST_LOS_SW bit is ‘1’. For T4 path, the occurrence of the fast loss will result in T4 DPLL unlocked regardless of the FAST_LOS_SW bit. Coarse Phase Loss The DPLL soft limit is set by the DPLL_FREQ_SOFT_LIMT[6:0] bits and can be calculated as follows: The T0/T4 DPLL compares the selected input clock with the feedback signal. If the phase-compared result exceeds the coarse phase limit, a coarse phase loss is triggered. It is cleared once the phase-compared result is within the coarse phase limit. DPLL Soft Limit (ppm) = DPLL_FREQ_SOFT_LIMT[6:0] X 0.724 The DPLL hard limit is set by the DPLL_FREQ_HARD_LIMT[15:0] bits and can be calculated as follows: When the selected input clock is of 2 kHz, 4 kHz or 8 kHz, the coarse phase limit depends on the MULTI_PH_8K_4K_2K_EN bit, the WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to Table 10. When the selected input clock is of other frequencies but 2 kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to Table 11. DPLL Hard Limit (ppm) = DPLL_FREQ_HARD_LIMT[15:0] X 0.0014 3.7.2 0 Coarse Phase Limit don’t-care ±1 UI 0 ±1 UI 1 set by the PH_LOS_COARSE_LIMT[3:0] bits 1 If the FAST_LOS_SW bit, the COARSE_PH_LOS_LIMT_EN bit, the FINE_PH_LOS_LIMT_EN bit or the FREQ_LIMT_PH_LOS bit is ‘0’, the DPLL locking status will not be affected even if the corresponding event is triggered. If all these bits are ‘0’, the DPLL will be in locked state in 2 seconds. Table 11: Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) WIDE_EN Coarse Phase Limit 0 1 ±1 UI set by the PH_LOS_COARSE_LIMT[3:0] bits The DPLL locking status is indicated by the T0_DPLL_LOCK / T4_DPLL_LOCK bit. The T4_STS 1 bit will be set when the locking status of the T4 DPLL changes (from ‘lock’ to ‘unlock’ or from ‘unlock’ to ‘lock’). If the T4_STS 2 bit is ‘1’, an interrupt will be generated. The occurrence of the coarse phase loss will result in T0/T4 DPLL unlocked if the COARSE_PH_LOS_LIMT_EN bit is ‘1’. Functional Description LOCKING STATUS The DPLL locking status depends on the locking monitoring results. The DPLL is in locked state if none of the following events is triggered during 2 seconds; otherwise, the DPLL is unlocked. • Fast Loss (the FAST_LOS_SW bit is ‘1’); • Coarse Phase Loss (the COARSE_PH_LOS_LIMT_EN bit is ‘1’); • Fine Phase Loss (the FINE_PH_LOS_LIMT_EN bit is ‘1’); • DPLL Hard Alarm (the FREQ_LIMT_PH_LOS bit is ‘1’). Table 10: Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) MULTI_PH_8K_4K WIDE_EN _2K_EN Hard Limit Exceeding Two limits are available for this monitoring. They are DPLL soft limit and DPLL hard limit. When the frequency of the DPLL output with respect to the master clock exceeds the DPLL soft / hard limit, a DPLL soft / hard alarm will be raised; the alarm is cleared once the frequency is within the corresponding limit. The occurrence of the DPLL soft alarm does not affect the T0/T4 DPLL locking status. The DPLL soft alarm is indicated by the corresponding T0_DPLL_SOFT_FREQ_ALARM / T4_DPLL_SOFT_FREQ_ALARM bit. The occurrence of the DPLL hard alarm will result in T0/T4 DPLL unlocked if the FREQ_LIMT_PH_LOS bit is ‘1’. Fast Loss 3.7.1.2 Fine Phase Loss 27 April 15, 2015 IDT82V3280 3.7.3 WAN PLL PHASE LOCK ALARM (T0 ONLY) • Be cleared when a ‘1’ is written to the corresponding INn_PH_LOCK_ALARM bit; • Be cleared after the period (= TIME_OUT_VALUE[5:0] X MULTI_FACTOR[1:0] in second) which starts from when the alarm is raised. A phase lock alarm will be raised when the selected input clock can not be locked in T0 DPLL within a certain period. This period can be calculated as follows: Period (sec.) = TIME_OUT_VALUE[5:0] X MULTI_FACTOR[1:0] The selected input clock with a phase lock alarm is disqualified for T0 DPLL locking. The phase lock alarm is indicated by the corresponding INn_PH_LOCK_ALARM bit (14  n  1). Note that no phase lock alarm is raised if the T4 selected input clock can not be locked. The phase lock alarm can be cleared by the following two ways, as selected by the PH_ALARM_TIMEOUT bit: Table 12: Related Bit / Register in Chapter 3.7 Bit Register Address (Hex) PHASE_LOSS_FINE_LIMIT_CNFG 5B * PHASE_LOSS_COARSE_LIMIT_CNFG 5A * OPERATING_STS 52 DPLL_FREQ_SOFT_LIMIT_CNFG 65 DPLL_FREQ_HARD_LIMT[15:0] DPLL_FREQ_HARD_LIMIT[15:8]_CNFG, DPLL_FREQ_HARD_LIMIT[7:0]_CNFG 67, 66 T4_STS 1 INTERRUPTS3_STS 0F INTERRUPTS3_ENABLE_CNFG 12 PHASE_ALARM_TIME_OUT_CNFG 08 IN1_IN2_STS ~ IN13_IN14_STS INPUT_MODE_CNFG T4_T0_REG_SEL_CNFG 43 ~ 49 09 07 FAST_LOS_SW PH_LOS_FINE_LIMT[2:0] FINE_PH_LOS_LIMT_EN MULTI_PH_8K_4K_2K_EN WIDE_EN PH_LOS_COARSE_LIMT[3:0] COARSE_PH_LOS_LIMT_EN T0_DPLL_SOFT_FREQ_ALARM T4_DPLL_SOFT_FREQ_ALARM T0_DPLL_LOCK T4_DPLL_LOCK DPLL_FREQ_SOFT_LIMT[6:0] FREQ_LIMT_PH_LOS 2 T4_STS TIME_OUT_VALUE[5:0] MULTI_FACTOR[1:0] INn_PH_LOCK_ALARM (14  n  1) PH_ALARM_TIMEOUT T4_T0_SEL Note: * The setting in the 5A and 5B registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit. Functional Description 28 April 15, 2015 IDT82V3280 3.8 WAN PLL SELECTED INPUT CLOCK SWITCH For T0 path, Revertive and Non-Revertive switches are supported, as selected by the REVERTIVE_MODE bit. If the input clock is selected by External Fast selection or by Forced selection, it can be switched by setting the related registers (refer to Chapter 3.6.1 External Fast Selection (T0 only) & Chapter 3.6.2 Forced Selection) any time. In this case, whether the input clock is qualified for DPLL locking does not affect the clock switch. If the T4 selected input clock is a T0 DPLL output, it can only be switched by setting the T0_FOR_T4 bit. For T4 path, only Revertive switch is supported. The difference between Revertive and Non-Revertive switches is that whether the selected input clock is switched when another qualified input clock with a higher priority than the current selected input clock is available for selection. In Non-Revertive switch, input clock switch is minimized. When the input clock is selected by Automatic selection, the input clock switch depends on its validity, priority and locking allowance configuration. If the current selected input clock is disqualified, a new qualified input clock may be switched to. 3.8.1 Conditions of the qualified input clocks available for T0 selection are different from that for T4 selection, as shown in Table 13: Table 13: Conditions of Qualified Input Clocks Available for T0 & T4 Selection INPUT CLOCK VALIDITY Conditions of Qualified Input Clocks Available for T0 & T4 Selection For all the input clocks, the validity depends on the results of input clock quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring). When all of the following conditions are satisfied, the input clock is valid; otherwise, it is invalid. • No LOS (the AMI1_LOS / AMI2_LOS bit is ‘0’); • No no-activity alarm (the INn_NO_ACTIVITY_ALARM bit is ‘0’); • No frequency hard alarm (the INn_FREQ_HARD_ALARM bit is ‘0’); • If the IN_NOISE_WINDOW bit is ‘1’, all the edges of the input clock of 2 kHz, 4 kHz or 8 kHz drift inside ±5%; if the IN_NOISE_WINDOW bit is ‘0’, this condition is ignored. • Valid, i.e., the INn 1 bit is ‘1’; • Priority enabled, i.e., the corresponding INn_SEL_PRIORITY[3:0] bits T0 are not ‘0000’; • Locking to the input clock is allowed, i.e., the corresponding INn_VALID bit is ‘0’. • Valid (all the validity conditions listed in Chapter 3.8.1 Input Clock Validity are satisfied); • Priority enabled, i.e., the corresponding INn_SEL_PRIORITY[3:0] bits T4 are not ‘0000’; • Locking to the input clock is allowed, i.e., the corresponding INn_VALID bit is ‘0’. The validity qualification of the T0 selected input clock is different from that of the T4 selected input clock. The validity qualification of the T4 selected input clock is the same as the above. The T0 selected input clock is valid when all of the above and the following conditions are satisfied; otherwise, it is invalid. • No phase lock alarm, i.e., the INn_PH_LOCK_ALARM bit is ‘0’; • If the ULTR_FAST_SW bit is ‘1’, the T0 selected input clock misses less than (T ns Note: * Timing with RDY. If RDY is not used, tpw1 is 3.5T + 10. Microprocessor Interface 50 April 15, 2015 IDT82V3280 WAN PLL tpw3 tT ALE th1 tsu1 CS RD th2 tpw1 tsu2 WR th4 tsu3 AD[7:0] data address td2 RDY tpw2 th3 td5 High-Z High-Z td6 Figure 18. Multiplexed Write Timing Diagram Table 34: Write Timing Characteristics in Multiplexed Mode Symbol Parameter Min Typ Max Unit T One cycle time of the master clock 12.86 ns tin Delay of input pad 5 ns tout Delay of output pad 5 ns tsu1 Valid address to ALE falling edge setup time 2 ns tsu2 Valid CS to valid WR setup time 0 ns tsu3 Valid data to WR rising edge setup time 3 td2 Valid CS to valid RDY delay time 13 ns td5 WR rising edge to RDY low delay time 13 ns td6 CS rising edge to RDY release delay time 13 ns tpw1 Valid WR pulse width low 1.5T + 10 ns tpw2 Valid RDY pulse width low 1.5T + 10 ns tpw3 Valid ALE pulse width high 2 ns th1 Valid address after ALE falling edge hold time 3 ns th2 Valid CS after WR rising edge hold time 0 ns th3 Valid WR after RDY rising edge hold time 0 ns th4 ns Valid data after WR rising edge hold time 9 ns tT Time between ALE falling edge and WR falling edge 0 ns tTI Time between consecutive Write-Read or Write-Write accesses (WR rising edge to ALE rising edge) >7T ns Microprocessor Interface 51 April 15, 2015 IDT82V3280 5.3 WAN PLL INTEL MODE CS WR tpw1 tsu2 th2 RD th1 tsu1 A[6:0] address td4 td1 High-Z td2 RDY High-Z data AD[7:0] tpw2 th3 td5 High-Z High-Z td6 Figure 19. Intel Read Timing Diagram Table 35: Read Timing Characteristics in Intel Mode Symbol Parameter Min Typ Max T One cycle time of the master clock 12.86 ns tin Delay of input pad 5 ns tout Delay of output pad 5 ns tsu1 Valid address to valid CS setup time 0 ns tsu2 Valid CS to valid RD setup time 0 ns td1 Valid RD to valid data delay time 3.5T + 10 Unit ns td2 Valid CS to valid RDY delay time 13 ns td4 RD rising edge to AD[7:0] high impedance delay time 10 ns td5 RD rising edge to RDY low delay time 13 ns td6 CS rising edge to RDY release delay time 13 ns tpw1 Valid RD pulse width low 4.5T + 10 * ns tpw2 Valid RDY pulse width low 4.5T + 10 ns th1 Valid address after RD rising edge hold time 0 ns th2 Valid CS after RD rising edge hold time 0 ns th3 Valid RD after RDY rising edge hold time 0 ns tTI Time between consecutive Read-Read or Read-Write accesses (RD rising edge to RD falling edge, or RD rising edge to WR falling edge) >T ns Note: * Timing with RDY. If RDY is not used, tpw1 is 3.5T + 10. Microprocessor Interface 52 April 15, 2015 IDT82V3280 WAN PLL CS tsu2 tpw1 th2 WR RD tsu1 th1 A[6:0] address tsu3 AD[7:0] data td2 RDY th4 tpw2 th3 td5 High-Z High-Z td6 Figure 20. Intel Write Timing Diagram Table 36: Write Timing Characteristics in Intel Mode Symbol Parameter Min Typ Max Unit T One cycle time of the master clock 12.86 ns tin Delay of input pad 5 ns tout Delay of output pad 5 ns tsu1 Valid address to valid CS setup time 0 ns tsu2 Valid CS to valid WR setup time 0 ns tsu3 Valid data before WR rising edge setup time 3 ns td2 Valid CS to valid RDY delay time 13 ns td5 WR rising edge to RDY low delay time 13 ns td6 CS rising edge to RDY release delay time 13 ns tpw1 Valid WR pulse width low 1.5T + 10 ns tpw2 Valid RDY pulse width low 1.5T + 10 ns th1 Valid address after WR rising edge hold time 0 ns th2 Valid CS after WR rising edge hold time 0 ns th3 Valid WR after RDY rising edge hold time 0 ns th4 Valid data after WR rising edge hold time 9 ns tTI Time between consecutive Write-Read or Write-Write accesses (WR rising edge to WR falling edge, or WR rising edge to RD falling edge) >7T ns Microprocessor Interface 53 April 15, 2015 IDT82V3280 5.4 WAN PLL MOTOROLA MODE tpw1 CS th2 tsu2 WR th1 tsu1 address A[6:0] td3 td1 AD[7:0] High-Z data td2 RDY tpw2 th3 High-Z tr1 td4 High-Z High-Z Figure 21. Motorola Read Timing Diagram Table 37: Read Timing Characteristics in Motorola Mode Symbol Parameter Min Typ T One cycle time of the master clock 12.86 tin Delay of input pad 5 Max Unit ns tout Delay of output pad tsu1 Valid address to valid CS setup time 0 ns tsu2 Valid WR to valid CS setup time 0 ns td1 Valid CS to valid data delay time td2 Valid CS to valid RDY delay time 13 ns td3 CS rising edge to AD[7:0] high impedance delay time 10 ns td4 CS rising edge to RDY release delay time 13 ns tpw1 Valid CS pulse width low 4.5T + 10 * ns tpw2 Valid RDY pulse width high 4.5T + 10 ns 5 ns 3.5T + 10 ns th1 Valid address after CS rising edge hold time 0 ns th2 Valid WR after CS rising edge hold time 0 ns th3 Valid CS after RDY falling edge hold time 0 tr1 RDY release time tTI Time between consecutive Read-Read or Read-Write accesses (CS rising edge to CS falling edge) ns 3 >T ns ns Note: * Timing with RDY. If RDY is not used, tpw1 is 3.5T +10. Microprocessor Interface 54 April 15, 2015 IDT82V3280 WAN PLL tpw1 CS th2 tsu2 WR tsu1 th1 A[6:0] address th4 tsu3 AD[7:0] data td2 RDY th3 tpw2 tr1 td4 High-Z High-Z Figure 22. Motorola Write Timing Diagram Table 38: Write Timing Characteristics in Motorola Mode Symbol Parameter T Min Typ Max Unit One cycle time of the master clock 12.86 ns tin Delay of input pad 5 ns tout Delay of output pad 5 ns tsu1 Valid address to valid CS setup time 0 ns tsu2 Valid WR to valid CS setup time 0 ns tsu3 Valid data before CS rising edge setup time 3 ns td2 Valid CS to valid RDY delay time 13 ns td4 CS rising edge to RDY release delay time 13 ns tpw1 Valid CS pulse width low 1.5T + 10 ns tpw2 Valid RDY pulse width high 1.5T + 10 ns th1 Valid address after valid CS rising edge hold time 0 ns th2 Valid WR after valid CS rising edge hold time 0 ns th3 Valid CS after RDY falling edge hold time 0 ns th4 Valid data after valid CS rising edge hold time 9 tr1 RDY release time tTI Time between consecutive Write-Write or Write-Read accesses (CS rising edge to CS falling edge) Microprocessor Interface ns 3 55 > 7T ns ns April 15, 2015 IDT82V3280 5.5 WAN PLL SERIAL MODE ing edge of SCLK. When CLKE is asserted high, data on SDO will be clocked out on the falling edge of SCLK. In a read operation, the active edge of SCLK is selected by CLKE. When CLKE is asserted low, data on SDO will be clocked out on the ris- In a write operation, data on SDI will be clocked in on the rising edge of SCLK. CS SCLK tsu1 th1 tpw1 R/W SDI th2 tpw2 tsu2 A0 A1 A2 A3 A4 A5 A6 td1 High-Z SDO td2 D0 D1 D2 D3 D4 D5 D6 D7 Figure 23. Serial Read Timing Diagram (CLKE Asserted Low) CS th2 SCLK SDI R/W A0 A1 A2 A3 A4 A5 A6 td1 High-Z td2 D0 SDO D1 D2 D3 D4 D5 D6 D7 Figure 24. Serial Read Timing Diagram (CLKE Asserted High) Table 39: Read Timing Characteristics in Serial Mode Symbol Parameter Min Typ Max Unit T One cycle time of the master clock 12.86 ns tin Delay of input pad 5 ns tout Delay of output pad 5 ns tsu1 Valid SDI to valid SCLK setup time 4 tsu2 Valid CS to valid SCLK setup time 14 td1 Valid SCLK to valid data delay time 10 ns td2 CS rising edge to SDO high impedance delay time 10 ns tpw1 SCLK pulse width low 3.5T + 5 ns tpw2 SCLK pulse width high 3.5T + 5 ns th1 Valid SDI after valid SCLK hold time 6 ns th2 Valid CS after valid SCLK hold time (CLKE = 0/1) 5 ns tTI Time between consecutive Read-Read or Read-Write accesses (CS rising edge to CS falling edge) 10 ns Microprocessor Interface 56 ns ns April 15, 2015 IDT82V3280 WAN PLL CS tsu2 SCLK th1 tpw1 tsu1 SDI th2 tpw2 R/W A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 High-Z SDO Figure 25. Serial Write Timing Diagram Table 40: Write Timing Characteristics in Serial Mode Symbol Parameter Min Typ Max Unit T One cycle time of the master clock 12.86 ns tin Delay of input pad 5 ns tout Delay of output pad 5 ns tsu1 Valid SDI to valid SCLK setup time 4 ns tsu2 Valid CS to valid SCLK setup time 14 ns tpw1 SCLK pulse width low 3.5T ns tpw2 SCLK pulse width high 3.5T ns th1 Valid SDI after valid SCLK hold time 6 ns th2 Valid CS after valid SCLK hold time 5 ns tTI Time between consecutive Write-Write or Write-Read accesses (CS rising edge to CS falling edge) 10 ns Microprocessor Interface 57 April 15, 2015 IDT82V3280 6 WAN PLL JTAG This device is compliant with the IEEE 1149.1 Boundary Scan standard except the following: • The output boundary scan cells do not capture data from the core and the device does not support EXTEST instruction; • The TRST pin is set low by default and JTAG is disabled in order to be consistent with other manufacturers. The JTAG interface timing diagram is shown in Figure 26. tTCK TCK tS tH TMS TDI tD TDO Figure 26. JTAG Interface Timing Diagram Table 41: JTAG Timing Characteristics Symbol JTAG Parameter Min tTCK Typ Max TCK period 100 ns tS TMS / TDI to TCK setup time 25 ns tH TCK to TMS / TDI Hold Time 25 ns tD TCK to TDO delay time 50 58 Unit ns April 15, 2015 IDT82V3280 7 WAN PLL PROGRAMMING INFORMATION After reset, all the registers are set to their default values. The registers are read or written via the microprocessor interface. The access of the Multi-word Registers is different from that of the Single-word Registers. Take the registers (04H, 05H and 06H) for an example, the write operation for the Multi-word Registers follows a fixed sequence. The register (04H) is configured first and the register (06H) is configured last. The three registers are configured continuously and should not be interrupted by any operation. The crystal calibration configuration will take effect after all the three registers are configured. During read operation, the register (04H) is read first and the register (06H) is read last. The crystal calibration reading should be continuous and not be interrupted by any operation. Before any write operation, the value in register PROTECTION_CNFG is recommended to be confirmed to make sure whether the write operation is enabled. The device provides 3 register protection modes: • Protected mode: no other registers can be written except register PROTECTION_CNFG itself; • Fully Unprotected mode: all the writable registers can be written; • Single Unprotected mode: one more register can be written besides register PROTECTION_CNFG. After write operation (not including writing a ‘1’ to clear a bit to ‘0’), the device automatically switches to Protected mode. Certain bit locations within the device register map are designated as Reserved. To ensure proper and predictable operation, bits designated as Reserved should not be written by the users. In addition, their value should be masked out from any testing or error detection methods that are implemented. Writing ‘0’ to the registers will take no effect if the registers are cleared by writing ‘1’. 7.1 T0 and T4 paths share some registers, whose addresses are 26H ~ 2CH, 4EH, 4FH, 5AH, 5BH, 62H ~ 64H, 68H and 69H. The names of shared registers are marked with a *. Before register read/write operation, register T4_T0_REG_SEL_CNFG is recommended to be confirmed to make sure whether the register operation is available for T0 or T4 path. REGISTER MAP Table 42 is the map of all the registers, sorted in an ascending order of their addresses. Table 42: Register List and Map Address (Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference Page Global Control Registers 00 01 02 04 05 06 07 08 09 ID[7:0] - Device ID 1 ID[15:8] - Device ID 2 MPU_PIN_STS - MPU_MODE[2:0] Pins Status NOMINAL_FREQ[7:0]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 1 NOMINAL_FREQ[15:8]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 2 NOMINAL_FREQ[23:16]_CNFG Crystal Oscillator Frequency Offset Calibration Configuration 3 T4_T0_REG_SEL_CNFG - T0 / T4 Registers Selection Configuration PHASE_ALARM_TIME_OUT_CNFG Phase Lock Alarm Time-Out Configuration INPUT_MODE_CNFG - Input Mode Configuration Programming Information ID[7:0] ID[15:8] - - - - - - P 66 P 66 - MPU_PIN_STS[2:0] P 66 NOMINAL_FREQ_VALUE[7:0] P 67 NOMINAL_FREQ_VALUE[15:8] P 67 NOMINAL_FREQ_VALUE[23:16] P 67 - MULTI_FACTOR[1:0] T4_T0_SEL - - - - P 68 TIME_OUT_VALUE[5:0] AUTO_EXPH_ALAR EXT_SYNT_SYNM_TIMEC_EN C_EN OUT 59 SYNC_FREQ[1:0] MASIN_SONTER_SLAV ET_SDH E P 68 REVERTIVE_MODE P 69 April 15, 2015 IDT82V3280 WAN PLL Table 42: Register List and Map (Continued) Address (Hex) 0A 0B 13 7E 7F 0C 0D 0E 0F 10 11 12 14 15 16 17 18 19 1A 1B 1C Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DIFFERENOSC_EDG OUT7_PE- OUT6_PETIAL_IN_OUT_OSCI_CNFG - DifferE CL_LVDS CL_LVDS ential Input / Output Port & Master Clock Configuration MON_SW_PBO_CNFG - Frequency FRELOS_FREULTR_PBO_Monitor, Input Clock Selection & PBO Q_MON_- FLAG_TO_ EXT_SW PBO_EN Q_MON_H FAST_SW FREZ Control CLK TDO ARD_EN MS_SL_CMS_SL_CTRL_CNFG - Master Slave Control TRL PROTECTION_CNFG - Register ProPROTECTION_DATA[7:0] tection Mode Configuration MPU_SEL_CNFG - Microprocessor MPU_SEL_CNFG[2:0] Interface Mode Configuration Interrupt Registers INTERRUPT_CNFG - Interrupt ConHZ_EN INT_POL figuration INTERRUPTS1_STS - Interrupt Status IN[8:1] 1 T0_OPERT0_INTERRUPTS2_STS - Interrupt Status ATING_- MAIN_REF IN[14:9] 2 MODE _FAILED INTERRUPTS3_STS - Interrupt Status EX_SYNINPUT_TO AMI2_VIO AMI1_VIO T4_STS AMI2_LOS AMI1_LOS 3 C_ALARM _T4 L L INTERRUPTS1_ENABLE_CNFG IN[8:1] Interrupt Control 1 T0_OPERT0_INTERRUPTS2_ENABLE_CNFG ATING_- MAIN_REF IN[14:9] Interrupt Control 2 MODE _FAILED INTERRUPTS3_ENABLE_CNFG - EX_SYNAMI1_VIO INPUT_TO AMI2_VIO T4_STS AMI2_LOS AMI1_LOS Interrupt Control 3 C_ALARM L L _T4 Input Clock Frequency & Priority Configuration Registers 400HZ_IN1_CNFG - Input Clock 1 ConfiguraBUCKET_SEL[1:0] IN_FREQ[3:0] tion SEL IN2_CNFG - Input Clock 2 Configura400HZ_BUCKET_SEL[1:0] IN_FREQ[3:0] tion SEL IN3_CNFG - Input Clock 3 Configura- DIRECT_D LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] tion IV IN4_CNFG - Input Clock 4 Configura- DIRECT_D LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] tion IV IN5_IN6_HF_DIV_CNFG - Input Clock 5 & 6 High Frequency Divider ConfiguIN6_DIV[1:0] IN5_DIV[1:0] ration IN5_CNFG - Input Clock 5 Configura- DIRECT_D LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] tion IV IN6_CNFG - Input Clock 6 Configura- DIRECT_D LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] tion IV IN7_CNFG - Input Clock 7 Configura- DIRECT_D LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] tion IV IN8_CNFG - Input Clock 8 Configura- DIRECT_D LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] tion IV Programming Information 60 Reference Page P 70 P 71 P 72 P 72 P 73 P 74 P 74 P 75 P 76 P 77 P 77 P 78 P 79 P 79 P 80 P 81 P 82 P 83 P 84 P 85 P 86 April 15, 2015 IDT82V3280 WAN PLL Table 42: Register List and Map (Continued) Address (Hex) 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2E 2F 31 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IN9_CNFG - Input Clock 9 Configura- DIRECT_D LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] tion IV IN10_CNFG - Input Clock 10 Configu- DIRECT_D LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] ration IV IN11_CNFG - Input Clock 11 Configu- DIRECT_D LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] ration IV IN12_CNFG - Input Clock 12 Configu- DIRECT_D LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] ration IV IN13_CNFG - Input Clock 13 Configu- DIRECT_D LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] ration IV IN14_CNFG - Input Clock 14 Configu- DIRECT_D LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] ration IV PRE_DIV_CH_CNFG - DivN Divider PRE_DIV_CH_VALUE[3:0] Channel Selection PRE_DIVN[7:0]_CNFG - DivN Divider PRE_DIVN_VALUE[7:0] Division Factor Configuration 1 PRE_DIVN[14:8]_CNFG DivN PRE_DIVN_VALUE[14:8] Divider Division Factor Configuration 2 IN1_IN2_SEL_PRIORITY_CNFG Input Clock 1 & 2 Priority Configuration IN2_SEL_PRIORITY[3:0] IN1_SEL_PRIORITY[3:0] * IN3_IN4_SEL_PRIORITY_CNFG Input Clock 3 & 4 Priority Configuration IN4_SEL_PRIORITY[3:0] IN3_SEL_PRIORITY[3:0] * IN5_IN6_SEL_PRIORITY_CNFG Input Clock 5 & 6 Priority Configuration IN6_SEL_PRIORITY[3:0] IN5_SEL_PRIORITY[3:0] * IN7_IN8_SEL_PRIORITY_CNFG Input Clock 7 & 8 Priority Configuration IN8_SEL_PRIORITY[3:0] IN7_SEL_PRIORITY[3:0] * IN9_IN10_SEL_PRIORITY_CNFG Input Clock 9 & 10 Priority ConfiguraIN10_SEL_PRIORITY[3:0] IN9_SEL_PRIORITY[3:0] tion * IN11_IN12_SEL_PRIORITY_CNFG Input Clock 11 & 12 Priority ConfiguraIN12_SEL_PRIORITY[3:0] IN11_SEL_PRIORITY[3:0] tion * IN13_IN14_SEL_PRIORITY_CNFG Input Clock 13 & 14 Priority ConfiguraIN14_SEL_PRIORITY[3:0] IN13_SEL_PRIORITY[3:0] tion * Input Clock Quality Monitoring Configuration & Status Registers FREQ_MON_FACTOR_CNFG - FacFREQ_MON_FACTOR[3:0] tor of Frequency Monitor Configuration ALL_FREQ_MON_THRESHOLD_CNFG - Frequency Monitor ALL_FREQ_HARD_THRESHOLD[3:0] Threshold for All Input Clocks Configuration UPPER_THRESHOLD_0_CNFG Upper Threshold for Leaky Bucket UPPER_THRESHOLD_0_DATA[7:0] Configuration 0 Programming Information 61 Reference Page P 87 P 88 P 89 P 90 P 91 P 92 P 93 P 93 P 94 P 95 P 96 P 97 P 98 P 99 P 100 P 101 P 102 P 102 P 103 April 15, 2015 IDT82V3280 WAN PLL Table 42: Register List and Map (Continued) Address (Hex) 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 Register Name LOWER_THRESHOLD_0_CNFG Lower Threshold for Leaky Bucket Configuration 0 BUCKET_SIZE_0_CNFG - Bucket Size for Leaky Bucket Configuration 0 DECAY_RATE_0_CNFG - Decay Rate for Leaky Bucket Configuration 0 UPPER_THRESHOLD_1_CNFG Upper Threshold for Leaky Bucket Configuration 1 LOWER_THRESHOLD_1_CNFG Lower Threshold for Leaky Bucket Configuration 1 BUCKET_SIZE_1_CNFG - Bucket Size for Leaky Bucket Configuration 1 DECAY_RATE_1_CNFG - Decay Rate for Leaky Bucket Configuration 1 UPPER_THRESHOLD_2_CNFG Upper Threshold for Leaky Bucket Configuration 2 LOWER_THRESHOLD_2_CNFG Lower Threshold for Leaky Bucket Configuration 2 BUCKET_SIZE_2_CNFG - Bucket Size for Leaky Bucket Configuration 2 DECAY_RATE_2_CNFG - Decay Rate for Leaky Bucket Configuration 2 UPPER_THRESHOLD_3_CNFG Upper Threshold for Leaky Bucket Configuration 3 LOWER_THRESHOLD_3_CNFG Lower Threshold for Leaky Bucket Configuration 3 BUCKET_SIZE_3_CNFG - Bucket Size for Leaky Bucket Configuration 3 DECAY_RATE_3_CNFG - Decay Rate for Leaky Bucket Configuration 3 IN_FREQ_READ_CH_CNFG - Input Clock Frequency Read Channel Selection IN_FREQ_READ_STS - Input Clock Frequency Read Value Bit 7 - - - - - - Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P 103 BUCKET_SIZE_0_DATA[7:0] P 103 - - - - DECAY_RATE_0_DATA[1:0] P 104 LOWER_THRESHOLD_1_DATA[7:0] P 104 BUCKET_SIZE_1_DATA[7:0] P 105 - - - - DECAY_RATE_1_DATA[1:0] P 105 LOWER_THRESHOLD_2_DATA[7:0] P 106 BUCKET_SIZE_2_DATA[7:0] P 106 - - - - DECAY_RATE_2_DATA[1:0] P 107 LOWER_THRESHOLD_3_DATA[7:0] P 107 BUCKET_SIZE_3_DATA[7:0] P 107 - - - - - - DECAY_RATE_3_DATA[1:0] IN_FREQ_READ_CH[3:0] - IN2_NO_A IN2_FRECTIVIQ_HARD_ TY_ALAR ALARM M IN4_NO_A IN4_FRECTIVIQ_HARD_ TY_ALAR ALARM M 62 IN2_PH_L OCK_ALA RM - IN4_PH_L OCK_ALA RM - P 108 P 108 IN_FREQ_VALUE[7:0] IN3_IN4_STS - Input Clock 3 & 4 Status P 106 UPPER_THRESHOLD_3_DATA[7:0] - 44 P 105 UPPER_THRESHOLD_2_DATA[7:0] - - P 104 UPPER_THRESHOLD_1_DATA[7:0] - 43 Reference Page LOWER_THRESHOLD_0_DATA[7:0] - IN1_IN2_STS - Input Clock 1 & 2 Status Programming Information Bit 6 P 109 IN1_NO_A IN1_FRECTIVIQ_HARD_ TY_ALAR ALARM M IN3_NO_A IN3_FRECTIVIQ_HARD_ TY_ALAR ALARM M IN1_PH_L OCK_ALA RM P 109 IN3_PH_L OCK_ALA RM P 110 April 15, 2015 IDT82V3280 WAN PLL Table 42: Register List and Map (Continued) Address (Hex) Register Name 45 IN5_IN6_STS - Input Clock 5 & 6 Status - 46 IN7_IN8_STS - Input Clock 7 & 8 Status - 47 IN9_IN10_STS - Input Clock 9 & 10 Status - 48 IN11_IN12_STS - Input Clock 11 & 12 Status - 49 IN13_IN14_STS - Input Clock 13 & 14 Status - 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 IN6_NO_A IN6_PH_L IN6_FRECTIVIOCK_ALA Q_HARD_ TY_ALAR RM ALARM M IN8_NO_A IN8_PH_L IN8_FRECTIVIOCK_ALA Q_HARD_ TY_ALAR RM ALARM M IN10_NO_ IN10_FREIN10_PH_ ACTIVIQ_HARD_ LOCK_AL TY_ALAR ALARM ARM M IN12_NO_ IN12_PH_ IN12_FREACTIVILOCK_AL Q_HARD_ TY_ALAR ARM ALARM M IN14_NO_ IN14_PHA IN14_FREACTIVISE_LOCK Q_HARD_ TY_ALAR _ALARM ALARM M T0 / T4 DPLL Input Clock Selection Registers - - - - - Bit 2 Bit 1 IN5_NO_A IN5_FRECTIVIQ_HARD_ TY_ALAR ALARM M IN7_NO_A IN7_FRECTIVIQ_HARD_ TY_ALAR ALARM M IN9_NO_A IN9_FRECTIVIQ_HARD_ TY_ALAR ALARM M IN11_NO_ IN11_FREACTIVIQ_HARD_ TY_ALAR ALARM M IN13_NO_ IN13_FREACTIVIQ_HARD_ TY_ALAR ALARM M Bit 0 Reference Page IN5_PH_L OCK_ALA RM P 111 IN7_PH_L OCK_ALA RM P 112 IN9_PH_L OCK_ALA RM P 113 IN11_PH_L OCK_ALA RM P 114 IN13_PHA SE_LOCK _ALARM P 115 INPUT_VALID1_STS - Input Clocks IN[8:1] Validity 1 INPUT_VALID2_STS - Input Clocks IN[14:9] Validity 2 REMOTE_INPUT_VALID1_CNFG IN8_VALID IN7_VALID IN6_VALID IN5_VALID IN4_VALID IN3_VALID IN2_VALID IN1_VALID Input Clocks Validity Configuration 1 REMOTE_INPUT_VALID2_CNFG IN14_VALI IN13_VALI IN12_VALI IN11_VALI IN10_VALI IN9_VALID Input Clocks Validity Configuration 2 D D D D D PRIORITY_TABLE1_STS - Priority HIGHEST_PRIORITY_VALIDATED[3:0] CURRENTLY_SELECTED_INPUT[3:0] Status 1 * PRIORITY_TABLE2_STS - Priority SECOND_HIGHEST_PRIORITY_VALITHIRD_HIGHEST_PRIORITY_VALIDATED[3:0] Status 2 * DATED[3:0] T0_INPUT_SEL_CNFG - T0 Selected T0_INPUT_SEL[3:0] Input Clock Configuration T4_INPUT_SEL_CNFG - T4 Selected T4_LOCK_ T0_T4_TEST_ T4_INPUT_SEL[3:0] Input Clock Configuration T0 FOR_T4 T0_PH T0 / T4 DPLL State Machine Control Registers T0_DPLL_- T4_DPLL_EX_SYNOPERATING_STS - DPLL Operating T4_DSOFT_SOFT_T0_DC_ALARM T0_DPLL_OPERATING_MODE[2:0] Status PLL_LOCK FREQ_AL FREQ_AL PLL_LOCK _MON ARM RAM T0_OPERATING_MODE_CNFG - T0 T0_OPERATING_MODE[2:0] DPLL Operating Mode Configuration T4_OPERATING_MODE_CNFG - T4 T4_OPERATING_MODE[2:0] DPLL Operating Mode Configuration T0 / T4 DPLL & APLL Configuration Registers T0_DPLL_APLL_PATH_CNFG - T0 T0_GSM_OBSAT0_12E1_24T1_E3_T3 T0_APLL_PATH[3:0] DPLL & APLL Path Configuration I_16E1_16T1_SEL[1:0] _SEL[1:0] Programming Information 63 P 116 P 116 P 116 P 117 P 117 P 118 P 118 P 119 P 120 P 121 P 121 P 122 April 15, 2015 IDT82V3280 WAN PLL Table 42: Register List and Map (Continued) Address (Hex) 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 Register Name Bit 7 Bit 6 Bit 5 T0_DPLL_START_BW_DAMPING_CNFG - T0 DPLL Start Band- T0_DPLL_START_DAMPING[2:0] width & Damping Factor Configuration T0_DPLL_ACQ_BW_DAMPING_CNFG - T0 DPLL Acquisition T0_DPLL_ACQ_DAMPING[2:0] Bandwidth & Damping Factor Configuration T0_DPLL_LOCKED_BW_DAMPING_CNFG - T0 DPLL Locked Band- T0_DPLL_LOCKED_DAMPING[2:0] width & Damping Factor Configuration T0_BW_OVERSHOOT_CNFG - T0 AUTO_BDPLL Bandwidth Overshoot ConfiguW_SEL ration Bit 4 - Bit 3 Bit 2 Bit 1 Bit 0 T0_DPLL_START_BW[4:0] P 123 T0_DPLL_ACQ_BW[4:0] P 124 T0_DPLL_LOCKED_BW[4:0] P 125 T0_LIMT - - - P 126 MULPHASE_LOSS_COARSE_LIMCOARSE_ MULTI_PH_8K PH_LOS_COARSE_LIMT[3:0] IT_CNFG - Phase Loss Coarse Detec- PH_LOS_L WIDE_EN TI_PH_AP _4K_2K_E tor Limit Configuration * IMT_EN P N PHASE_LOSS_FINE_LIMIT_CNFG - FINE_PH_ FAST_LOS Phase Loss Fine Detector Limit Con- LOS_LIMT PH_LOS_FINE_LIMT[2:0] _SW figuration * _EN T0_HOLDOVER_MODE_CNFG - T0 MAN_HOL AUTO_AV READ_AV TEMP_HOLDOVER_FAST_AVG DPLL Holdover Mode Configuration DOVER G G MODE[1:0] T0_HOLDOVER_FREQ[7:0]_CNFG T0 DPLL Holdover Frequency ConfigT0_HOLDOVER_FREQ[7:0] uration 1 T0_HOLDOVER_FREQ[15:8]_CNFG - T0 DPLL Holdover Frequency ConT0_HOLDOVER_FREQ[15:8] figuration 2 T0_HOLDOVER_FREQ[23:16]_CNFG - T0 DPLL HoldT0_HOLDOVER_FREQ[23:16] over Frequency Configuration 3 T4_GSM_GT4_DPLL_APLL_PATH_CNFG - T4 T4_12E1_24T1_E3_T3 T4_APLL_PATH[3:0] PS_16E1_16T1_DPLL & APLL Path Configuration _SEL[1:0] SEL[1:0] T4_DPLL_LOCKED_BW_DAMPT4_DING_CNFG - T4 DPLL Locked Band- T4_DPLL_LOCKED_DAMPING[2:0] PLL_LOCKED_BW[1:0] width & Damping Factor Configuration CURRENT_DPLL_FREQ[7:0]_STS CURRENT_DPLL_FREQ[7:0] DPLL Current Frequency Status 1 * CURRENT_DPLL_FREQ[15:8]_STS CURRENT_DPLL_FREQ[15:8] DPLL Current Frequency Status 2 * CURRENT_DPLL_FREQ[23:16]_STS CURRENT_DPLL_FREQ[23:16] - DPLL Current Frequency Status 3 * FREDPLL_FREQ_SOFT_LIMIT_CNFG Q_LIMT_P DPLL_FREQ_SOFT_LIMT[6:0] DPLL Soft Limit Configuration H_LOS DPLL_FREQ_HARD_LIMIT[7:0]_CNFG - DPLL DPLL_FREQ_HARD_LIMT[7:0] Hard Limit Configuration 1 Programming Information 64 Reference Page P 127 P 128 P 129 P 129 P 130 P 130 P 131 P 132 P 132 P 132 P 133 P 133 P 133 April 15, 2015 IDT82V3280 WAN PLL Table 42: Register List and Map (Continued) Address (Hex) 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 78 7A 7B 7C 7D Register Name DPLL_FREQ_HARD_LIMIT[15:8]_CNFG - DPLL Hard Limit Configuration 2 CURRENT_DPLL_PHASE[7:0]_STS DPLL Current Phase Status 1 * CURRENT_DPLL_PHASE[15:8]_STS - DPLL Current Phase Status 2 * T0_T4_APLL_BW_CNFG - T0 / T4 APLL Bandwidth Configuration Bit 7 - Bit 6 - Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DPLL_FREQ_HARD_LIMT[15:8] P 134 CURRENT_PH_DATA[7:0] P 134 CURRENT_PH_DATA[15:8] P 134 T0_APLL_BW[1:0] - - T4_APLL_BW[1:0] Output Configuration Registers OUT1_FREQ_CNFG - Output Clock 1 OUT1_PATH_SEL[3:0] OUT1_DIVIDER[3:0] Frequency Configuration OUT2_FREQ_CNFG - Output Clock 2 OUT2_PATH_SEL[3:0] OUT2_DIVIDER[3:0] Frequency Configuration OUT3_FREQ_CNFG - Output Clock 3 OUT3_PATH_SEL[3:0] OUT3_DIVIDER[3:0] Frequency Configuration OUT4_FREQ_CNFG - Output Clock 4 OUT4_PATH_SEL[3:0] OUT4_DIVIDER[3:0] Frequency Configuration OUT5_FREQ_CNFG - Output Clock 5 OUT5_PATH_SEL[3:0] OUT5_DIVIDER[3:0] Frequency Configuration OUT6_FREQ_CNFG - Output Clock 6 OUT6_PATH_SEL[3:0] OUT6_DIVIDER[3:0] Frequency Configuration OUT7_FREQ_CNFG - Output Clock 7 OUT7_PATH_SEL[3:0] OUT7_DIVIDER[3:0] Frequency Configuration OUT8_FREQ_CNFG - Output Clock 8 OUTT4_IN- AMI_OUT_ 400HZ_Frequency Configuration & Output 8_PATH_- OUT8_EN OUT9_INV OUT7_INV OUT6_INV PUT_FAIL DUTY SEL Clock 6, 7 & 9 Invert Configuration SEL OUT9_FREQ_CNFG - Output Clock 9 OUTT4_INFrequency Configuration & Output 9_PATH_- OUT9_EN OUT5_INV OUT4_INV OUT3_INV OUT2_INV OUT1_INV PUT_FAIL Clock 1 ~ 5 Invert Configuration SEL FR_MFR_SYNC_CNFG - Frame Sync 2K_8K_PU IN_2K_4K_ & Multiframe Sync Output Configura8K_EN 2K_EN L_POSI8K_INV 8K_PUL 2K_INV 2K_PUL 8K_INV tion TION PBO & Phase Offset Control Registers PHASE_MON_PBO_CNFG - Phase IN_NOISE PH_MON_ PH_MON_ Transient Monitor & PBO ConfiguraPH_TR_MON_LIMT[3:0] _WINDOW EN PBO_EN tion PHASE_OFFSET[7:0]_CNFG - Phase PH_OFFSET[7:0] Offset Configuration 1 PHASE_OFFSET[9:8]_CNFG - Phase PH_OFFPH_OFFSET[9:8] Offset Configuration 2 SET_EN Synchronization Configuration Registers SYNC_MONITOR_CNFG - Sync MonSYNC_MON_LIMT[2:0] itor Configuration SYNC_PHASE_CNFG - Sync Phase SYNC_PH1[1:0] Configuration Programming Information 65 Reference Page P 135 P 136 P 137 P 138 P 139 P 140 P 141 P 142 P 143 P 144 P 145 P 146 P 146 P 147 P 148 P 148 April 15, 2015 IDT82V3280 WAN PLL 7.2 REGISTER DESCRIPTION 7.2.1 GLOBAL CONTROL REGISTERS ID[7:0] - Device ID 1 Address: 00H Type: Read Default Value: 10001000 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Bit Name 7-0 ID[7:0] Description Refer to the description of the ID[15:8] bits (b7~0, 01H). ID[15:8] - Device ID 2 Address: 01H Type: Read Default Value: 00010001 7 6 5 4 3 2 1 0 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 Bit Name Description 7-0 ID[15:8] The value in the ID[15:0] bits are pre-set, representing the identification number for the IDT82V3280. MPU_PIN_STS - MPU_MODE[2:0] Pins Status Address: 02H Type: Read Default Value: XXXXXXXX 7 6 5 4 3 2 1 0 - - - - - MPU_PIN_STS2 MPU_PIN_STS1 MPU_PIN_STS0 Bit Name 7-3 - 2-0 Description Reserved. These bits indicate the value of the MPU_MODE[2:0] pins. MPU_PIN_STS[2:0] The default value of these bits is determined by the MPU_MODE[2:0] pins during reset. Programming Information 66 April 15, 2015 IDT82V3280 WAN PLL NOMINAL_FREQ[7:0]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 1 Address: 04H Type: Read / Write Default Value: 00000000 7 6 5 4 3 2 1 0 NOMINAL_FREQ_VALUE7 NOMINAL_FREQ_VALUE6 NOMINAL_FREQ_VALUE5 NOMINAL_FREQ_VALUE4 NOMINAL_FREQ_VALUE3 NOMINAL_FREQ_VALUE2 NOMINAL_FREQ_VALUE1 NOMINAL_FREQ_VALUE0 Bit Name 7-0 Description NOMINAL_FREQ_VALUE[7:0] Refer to the description of the NOMINAL_FREQ_VALUE[23:16] bits (b7~0, 06H). NOMINAL_FREQ[15:8]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 2 Address: 05H Type: Read / Write Default Value: 00000000 7 6 5 4 3 2 1 0 NOMINAL_FREQ_VALUE15 NOMINAL_FREQ_VALUE14 NOMINAL_FREQ_VALUE13 NOMINAL_FREQ_VALUE12 NOMINAL_FREQ_VALUE11 NOMINAL_FREQ_VALUE10 NOMINAL_FREQ_VALUE9 NOMINAL_FREQ_VALUE8 Bit Name 7-0 Description NOMINAL_FREQ_VALUE[15:8] Refer to the description of the NOMINAL_FREQ_VALUE[23:16] bits (b7~0, 06H). NOMINAL_FREQ[23:16]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 3 Address: 06H Type: Read / Write Default Value: 00000000 7 6 5 4 3 2 1 0 NOMINAL_FREQ_VALUE23 NOMINAL_FREQ_VALUE22 NOMINAL_FREQ_VALUE21 NOMINAL_FREQ_VALUE20 NOMINAL_FREQ_VALUE19 NOMINAL_FREQ_VALUE18 NOMINAL_FREQ_VALUE17 NOMINAL_FREQ_VALUE16 Bit 7-0 Name Description The NOMINAL_FREQ_VALUE[23:0] bits represent a 2’s complement signed integer. If the value is multiplied by 0.0000884, the calibration value for the master clock in ppm will be gotten. For example, the frequency offset on OSCI is +3 ppm. Though -3 ppm should be compensated, the calibration value is NOMINAL_FREQ_VALUE[23:16] calculated as +3 ppm: 3 ÷ 0.0000884 = 33937 (Dec.) = 8490 (Hex); So ‘008490’ should be written into these bits. The calibration range is within ±741 ppm. Programming Information 67 April 15, 2015 IDT82V3280 WAN PLL T4_T0_REG_SEL_CNFG - T0 / T4 Registers Selection Configuration Address: 07H Type: Read / Write Default Value: XXX0XXXX 7 6 5 4 3 2 1 0 - - - T4_T0_SEL - - - - Bit Name Description 7-5 - 4 T4_T0_SEL 3-0 - Reserved. A part of the registers are shared by T0 and T4 paths. These registers are addressed 26H ~ 2CH, 4EH, 4FH, 5AH, 5BH, 62H ~ 64H, 68H and 69H. This bit determines whether the register configuration is available for T0 or T4 path. 0: T0 path (default). 1: T4 path. Reserved. PHASE_ALARM_TIME_OUT_CNFG - Phase Lock Alarm Time-Out Configuration Address: 08H Type: Read / Write Default Value: 00110010 7 6 5 4 3 2 1 0 MULTI_FACTOR1 MULTI_FACTOR0 TIME_OUT_VA LUE5 TIME_OUT_VA LUE4 TIME_OUT_VA LUE3 TIME_OUT_VA LUE2 TIME_OUT_VA LUE1 TIME_OUT_VAL UE0 Bit 7-6 5-0 Name Description These bits determine a factor which has a relationship with a period in seconds. A phase lock alarm will be raised if the T0 selected input clock is not locked in T0 DPLL within this period. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, the phase lock alarm will be cleared after this period (starting from when the alarm is raised). Refer to the description of the TIME_OUT_VALUE[5:0] bits (b5~0, 08H). MULTI_FACTOR[1:0] 00: 2 (default) 01: 4 10: 8 11: 16 These bits represent an unsigned integer. If the value in these bits is multiplied by the value in the MULTI_FACTOR[1:0] bits (b7~6, 08H), a period in seconds will be gotten. TIME_OUT_VALUE[5:0] A phase lock alarm will be raised if the T0 selected input clock is not locked in T0 DPLL within this period. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, the phase lock alarm will be cleared after this period (starting from when the alarm is raised). Programming Information 68 April 15, 2015 IDT82V3280 WAN PLL INPUT_MODE_CNFG - Input Mode Configuration Address: 09H Type: Read / Write Default Value: 10100XX0 7 6 5 4 3 2 1 0 AUTO_EXT_SYNC_EN EXT_SYNC_EN PH_ALARM_TIMEOUT SYNC_FREQ1 SYNC_FREQ0 IN_SONET_SDH MASTER_SLAVE REVERTIVE_MODE Bit 7 6 5 4-3 2 1 0 Name Description AUTO_EXT_SYNC_EN Refer to the description of the EXT_SYNC_EN bit (b6, 09H). This bit, together with the AUTO_EXT_SYNC_EN bit (b7, 09H), determines whether EX_SYNC1 is enabled to synchronize the frame sync output signals. EXT_SYNC_EN AUTO_EXT_SYNC_EN EXT_SYNC_EN Synchronization don’t-care 0 1 0 1 1 Disabled (default) Enabled Enabled if the T0 selected input clock is IN11; otherwise, disabled. This bit determines how to clear the phase lock alarm. 0: The phase lock alarm will be cleared when a ‘1’ is written to the corresponding INn_PH_LOCK_ALARM bit (b4/0, PH_ALARM_TIMEOUT 43H~49H). 1: The phase lock alarm will be cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. (default) These bits set the frequency of the frame sync signal input on the EX_SYNC1 pin. 00: 8 kHz (default) SYNC_FREQ[1:0] 01: 8 kHz. 10: 4 kHz. 11: 2 kHz. This bit selects the SDH or SONET network type. 0: SDH. The DPLL required clock is 2.048 MHz when the IN_FREQ[3:0] bits (b3~0, 14H~17H & 19H~22H) are ‘0001’; the T0/T4 DPLL output from the 16E1/16T1 path is 16E1; and OUT9 outputs a 2.048 MHz signal if enabled. IN_SONET_SDH 1: SONET. The DPLL required clock is 1.544 MHz when the IN_FREQ[3:0] bits (b3~0, 14H~17H & 19H~22H) are ‘0001’; the T0/T4 DPLL output from the 16E1/16T1 path is 16T1; and OUT9 outputs a 1.544 MHz signal if enabled. The default value of this bit is determined by the SONET/SDH pin during reset. This bit is read only. It indicates the value of the MS/SL pin. MASTER_SLAVE Its default value is determined by the MS/SL pin during reset. This bit selects Revertive or Non-Revertive switch for T0 path. REVERTIVE_MODE 0: Non-Revertive switch. (default) 1: Revertive switch. Programming Information 69 April 15, 2015 IDT82V3280 WAN PLL DIFFERENTIAL_IN_OUT_OSCI_CNFG - Differential Input / Output Port & Master Clock Configuration Address: 0AH Type: Read / Write Default Value: XXXXX001 7 6 5 4 3 2 1 0 - - - - - OSC_EDGE OUT7_PECL_LVDS OUT6_PECL_LVDS Bit Name 7-3 - 2 1 0 Description Reserved. This bit selects a better active edge of the master clock. OSC_EDGE 0: The rising edge. (default) 1: The falling edge. This bit selects a port technology for OUT7. OUT7_PECL_LVDS 0: LVDS. (default) 1: PECL. This bit selects a port technology for OUT6. OUT6_PECL_LVDS 0: LVDS. 1: PECL. (default) Programming Information 70 April 15, 2015 IDT82V3280 WAN PLL MON_SW_PBO_CNFG - Frequency Monitor, Input Clock Selection & PBO Control Address: 0BH Type: Read / Write Default Value: 100X01X1 7 6 5 4 3 2 1 0 FREQ_MON_CLK LOS_FLAG_TO_TDO ULTR_FAST_SW EXT_SW PBO_FREZ PBO_EN - FREQ_MON_HARD _EN Bit 7 6 5 4 3 2 1 0 Name Description The bit selects a reference clock for input clock frequency monitoring. 0: The output of T0 DPLL. 1: The master clock. (default) The bit determines whether the interrupt of T0 selected input clock fail - is reported by the TDO pin. 0: Not reported. TDO pin is used as JTAG test data output which complies with IEEE 1149.1. (default) LOS_FLAG_TO_TDO 1: Reported. TDO pin mimics the state of the T0_MAIN_REF_FAILED bit (b6, 0EH) and does not strictly comply with IEEE 1149.1. This bit determines whether the T0 selected input clock is valid when missing 2 consecutive clock cycles or more. ULTR_FAST_SW 0: Valid. (default) 1: Invalid. This bit determines the T0 input clock selection. 0: Forced selection or Automatic selection, as controlled by the T0_INPUT_SEL[3:0] bits (b3~0, 50H). EXT_SW 1: External Fast selection. The default value of this bit is determined by the FF_SRCSW pin during reset. This bit is valid only when the PBO is enabled by the PBO_EN bit (b2, 0BH). It determines whether PBO is frozen at the current phase offset when a PBO event is triggered. PBO_FREZ 0: Not frozen. (default) 1: Frozen. Further PBO events are ignored and the current phase offset is maintained. This bit determines whether PBO is enabled when the T0 selected input clock switch or the T0 DPLL exiting from Holdover mode or Free-Run mode occurs. PBO_EN 0: Disabled. 1: Enabled. (default) Reserved. This bit determines whether the frequency hard alarm is enabled when the frequency of the input clock with respect to the reference clock is above the frequency hard alarm threshold. The reference clock can be the output of T0 DPLL or the masFREQ_MON_HARD_EN ter clock, as determined by the FREQ_MON_CLK bit (b7, 0BH). 0: Disabled. 1: Enabled. (default) FREQ_MON_CLK Programming Information 71 April 15, 2015 IDT82V3280 WAN PLL MS_SL_CTRL_CNFG - Master Slave Control Address: 13H Type: Read / Write Default Value: XXXXXXX0 7 6 5 4 3 2 1 0 - - - - - - - MS_SL_CTRL Bit Name 7-1 - Description Reserved. These bits, together with the MS/SL pin, control whether the device is configured as the Master or as the Slave. Master/Slave Control MS/SL pin 0 MS_SL_CTRL Result MS_SL_CTRL Bit 0 1 0 1 High Low Master Slave Slave Master The default value of this bit is ‘0’. PROTECTION_CNFG - Register Protection Mode Configuration Address: 7EH Type: Read / Write Default Value: 10000101 7 6 5 4 3 2 1 0 PROTECTION_DATA7 PROTECTION_DATA6 PROTECTION_DATA5 PROTECTION_DATA4 PROTECTION_DATA3 PROTECTION_DATA2 PROTECTION_DATA1 PROTECTION_DATA0 Bit 7-0 Name Description These bits select a register write protection mode. 00000000 - 10000100, 10000111 - 11111111: Protected mode. No other registers can be written except this register. PROTECTION_DATA[7:0] 10000101: Fully Unprotected mode. All the writable registers can be written. (default) 10000110: Single Unprotected mode. One more register can be written besides this register. After write operation (not including writing a ‘1’ to clear the bit to ‘0’), the device automatically switches to Protected mode. Programming Information 72 April 15, 2015 IDT82V3280 WAN PLL MPU_SEL_CNFG - Microprocessor Interface Mode Configuration Address: 7FH Type: Read / Write Default Value: XXXXXXXX 7 6 5 4 3 2 1 0 - - - - - MPU_SEL_CNFG2 MPU_SEL_CNFG1 MPU_SEL_CNFG0 Bit Name 7-3 - 2-0 Description Reserved. These bits select a microprocessor interface mode: 000: Reserved. 001: ERPOM mode. 010: Multiplexed mode. MPU_SEL_CNFG[2:0] 011: Intel mode. 100: Motorola mode. 101: Serial mode. 110, 111: Reserved. The default value of these bits are determined by the MPU_MODE[2:0] pins during reset. Programming Information 73 April 15, 2015 IDT82V3280 7.2.2 WAN PLL INTERRUPT REGISTERS INTERRUPT_CNFG - Interrupt Configuration Address: 0CH Type: Read / Write Default Value: XXXXXX10 7 6 5 4 3 2 1 0 - - - - - - HZ_EN INT_POL Bit Name Description 7-2 - 1 HZ_EN 0 INT_POL Reserved. This bit determines the output characteristics of the INT_REQ pin. 0: The output on the INT_REQ pin is high/low when the interrupt is active; the output is the opposite when the interrupt is inactive. 1: The output on the INT_REQ pin is high/low when the interrupt is active; the output is in high impedance state when the interrupt is inactive. (default) This bit determines the active level on the INT_REQ pin for an active interrupt indication. 0: Active low. (default) 1: Active high. INTERRUPTS1_STS - Interrupt Status 1 Address: 0DH Type: Read / Write Default Value: 11111111 7 6 5 4 3 2 1 0 IN8 IN7 IN6 IN5 IN4 IN3 IN2 IN1 Bit 7-0 Name Description INn This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for the corresponding INn; i.e., whether there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the corresponding INn bit (b7~0, 4AH). Here n is any one of 8 to 1. 0: Has not changed. 1: Has changed. (default) This bit is cleared by writing a ‘1’. Programming Information 74 April 15, 2015 IDT82V3280 WAN PLL INTERRUPTS2_STS - Interrupt Status 2 Address: 0EH Type: Read / Write Default Value: 00111111 7 6 5 4 3 2 1 0 T0_OPERATING_MODE T0_MAIN_REF_FAILED IN14 IN13 IN12 IN11 IN10 IN9 Bit 7 6 5-0 Name Description This bit indicates the operating mode switch for T0 DPLL; i.e., whether the value in the T0_DPLL_OPERATING_MODE[2:0] bits (b2~0, 52H) changes. T0_OPERATING_MODE 0: Has not switched. (default) 1: Has switched. This bit is cleared by writing a ‘1’. This bit indicates whether the T0 selected input clock has failed. The T0 selected input clock fails when its validity changes from ‘valid’ to ‘invalid’; i.e., when there is a transition from ‘1’ to ‘0’ on the corresponding INn bit (4AH, 4BH). T0_MAIN_REF_FAILED 0: Has not failed. (default) 1: Has failed. This bit is cleared by writing a ‘1’. This bit indicates the validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’) for the corresponding INn for T0 path, i.e., whether there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the corresponding INn bit (b5~0, 4BH). Here n is any one of 14 to 9. INn 0: Has not changed. 1: Has changed. (default) This bit is cleared by writing a ‘1’. Programming Information 75 April 15, 2015 IDT82V3280 WAN PLL INTERRUPTS3_STS - Interrupt Status 3 Address: 0FH Type: Read / Write Default Value: 11X10000 7 6 5 4 3 2 1 0 EX_SYNC_ALARM T4_STS - INPUT_TO_T4 AMI2_VIOL AMI2_LOS AMI1_VIOL AMI1_LOS Bit 7 6 5 4 3 2 1 0 Name Description This bit indicates whether an external sync alarm is raised; i.e., whether there is a transition from ‘0’ to ‘1’ on the EX_SYNC_ALARM_MON bit (b7, 52H). EX_SYNC_ALARM 0: Has not occurred. 1: Has occurred. (default) This bit is cleared by writing a ‘1’. This bit indicates the T4 DPLL locking status changes (from ‘locked’ to ‘unlocked’ or from ‘unlocked’ to ‘locked’); i.e., whether there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the T4_DPLL_LOCK bit (b6, 52H). T4_STS 0: Has not changed. 1: Has changed. (default) This bit is cleared by writing a ‘1’. Reserved. This bit indicates whether all the input clocks for T4 path changes to be unqualified; i.e., whether the HIGHEST_PRIORITY_VALIDATED[3:0] bits (b7~4, 4EH) are set to ‘0000’ when these bits are available for T4 path. INPUT_TO_T4 0: Has not changed. 1: Has changed. (default) This bit is cleared by writing a ‘1’. This bit indicates whether IN2 has an AMI violation. 0: Has no AMI violation. (default) AMI2_VIOL 1: Has an AMI violation. This bit is cleared by writing a ‘1’. This bit indicates whether IN2 has a LOS error. 0: Has no LOS error. (default) AMI2_LOS 1: Has a LOS error. This bit is cleared by writing a ‘1’. This bit indicates whether IN1 has an AMI violation. 0: Has no AMI violation. (default) AMI1_VIOL 1: Has an AMI violation. This bit is cleared by writing a ‘1’. This bit indicates whether IN1 has a LOS error. 0: Has no LOS error. (default) AMI1_LOS 1: Has a LOS error. This bit is cleared by writing a ‘1’. Programming Information 76 April 15, 2015 IDT82V3280 WAN PLL INTERRUPTS1_ENABLE_CNFG - Interrupt Control 1 Address: 10H Type: Read / Write Default Value: 00000000 7 6 5 4 3 2 1 0 IN8 IN7 IN6 IN5 IN4 IN3 IN2 IN1 Bit 7-0 Name Description INn This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding INn bit (b7~0, 0DH) is ‘1’. Here n is any one of 8 to 1. 0: Disabled. (default) 1: Enabled. INTERRUPTS2_ENABLE_CNFG - Interrupt Control 2 Address: 11H Type: Read / Write Default Value: 00000000 7 6 5 4 3 2 1 0 T0_OPERATING_MODE T0_MAIN_REF_FAILED IN14 IN13 IN12 IN11 IN10 IN9 Bit 7 6 5-0 Name Description This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 DPLL operating mode switches, i.e., when the T0_OPERATING_MODE bit (b7, 0EH) is ‘1’. T0_OPERATING_MODE 0: Disabled. (default) 1: Enabled. This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 selected input clock has failed; i.e., when the T0_MAIN_REF_FAILED bit (b6, 0EH) is ‘1’. T0_MAIN_REF_FAILED 0: Disabled. (default) 1: Enabled. This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding INn bit (b5~0, 0EH) is ‘1’. Here n INn is any one of 14 to 9. 0: Disabled. (default) 1: Enabled. Programming Information 77 April 15, 2015 IDT82V3280 WAN PLL INTERRUPTS3_ENABLE_CNFG - Interrupt Control 3 Address: 12H Type: Read / Write Default Value: 00X00000 7 6 5 4 3 2 1 0 EX_SYNC_ALARM T4_STS - INPUT_TO_T4 AMI2_VIOL AMI2_LOS AMI1_VIOL AMI1_LOS Bit 7 6 5 4 3 2 1 0 Name Description This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when an external sync alarm has occurred, i.e., when the EX_SYNC_ALARM bit (b7, 0FH) is ‘1’. EX_SYNC_ALARM 0: Disabled. (default) 1: Enabled. This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T4 DPLL locking status changes (from ‘locked’ to ‘unlocked’ or from ‘unlocked’ to ‘locked’), i.e., when the T4_STS bit (b6, 0FH) is ‘1’. T4_STS 0: Disabled. (default) 1: Enabled. Reserved. This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when all the input clocks for T4 path change to be unqualified, i.e., when the INPUT_TO_T4 bit (b4, 0FH) is ‘1’. INPUT_TO_T4 0: Disabled. (default) 1: Enabled. This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when IN2 has AMI violation, i.e., when the AMI2_VIOL bit (b3, 0FH) is ‘1’. AMI2_VIOL 0: Disabled. (default) 1: Enabled. This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when IN2 has LOS error, i.e., when the AMI2_LOS bit (b2, 0FH) is ‘1’. AMI2_LOS 0: Disabled. (default) 1: Enabled. This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when IN1 has AMI violation, i.e., when the AMI1_VIOL bit (b1, 0FH) is ‘1’. AMI1_VIOL 0: Disabled. (default) 1: Enabled. This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when IN1 has LOS error, i.e., when the AMI1_LOS bit (b0, 0FH) is ‘1’. AMI1_LOS 0: Disabled. (default) 1: Enabled. Programming Information 78 April 15, 2015 IDT82V3280 7.2.3 WAN PLL INPUT CLOCK FREQUENCY & PRIORITY CONFIGURATION REGISTERS IN1_CNFG - Input Clock 1 Configuration Address: 14H Type: Read / Write Default Value: X0000000 7 6 5 4 3 2 1 0 - 400HZ_SEL BUCKET_SEL1 BUCKET_SEL0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0 Bit Name 7 - Description Reserved. This bit should be set to match the clock input on IN1: 400HZ_SEL 0: 64 kHz + 8 kHz. (default) 1: 64 kHz + 8 kHz + 0.4 kHz. These bits select one of the four groups of leaky bucket configuration registers for IN1: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. These bits set the DPLL required frequency for IN1: IN_FREQ[3:0] 0000: 8 kHz. (default) 0001 ~ 1111: Reserved. 6 5-4 3-0 IN2_CNFG - Input Clock 2 Configuration Address: 15H Type: Read / Write Default Value: X0000000 7 6 5 4 3 2 1 0 - 400HZ_SEL BUCKET_SEL1 BUCKET_SEL0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0 Bit Name 7 - 6 5-4 3-0 Description Reserved. This bit should be set to match the clock input on IN2: 400HZ_SEL 0: 64 kHz + 8 kHz. (default) 1: 64 kHz + 8 kHz + 0.4 kHz. These bits select one of the four groups of leaky bucket configuration registers for IN2: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. These bits set the DPLL required frequency for IN2: IN_FREQ[3:0] 0000: 8 kHz. (default) 0001 ~ 1111: Reserved. Programming Information 79 April 15, 2015 IDT82V3280 WAN PLL IN3_CNFG - Input Clock 3 Configuration Address: 16H Type: Read / Write Default Value: 00000000 7 6 5 4 3 2 1 0 DIRECT_DIV LOCK_8K BUCKET_SEL1 BUCKET_SEL0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0 Bit Name Description 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 16H). This bit, together with the DIRECT_DIV bit (b7, 16H), determines whether the DivN Divider or the Lock 8k Divider is used for IN3: 6 5-4 3-0 LOCK_8K DIRECT_DIV bit LOCK_8K bit Used Divider 0 0 1 1 0 1 0 1 Both bypassed (default) Lock 8k Divider DivN Divider Reserved These bits select one of the four groups of leaky bucket configuration registers for IN3: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. These bits set the DPLL required frequency for IN3: 0000: 8 kHz. (default) 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’). 0010: 6.48 MHz. 0011: 19.44 MHz. 0100: 25.92 MHz. IN_FREQ[3:0] 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. For IN3, the required frequency should not be set higher than that of the input clock. Programming Information 80 April 15, 2015 IDT82V3280 WAN PLL IN4_CNFG - Input Clock 4 Configuration Address: 17H Type: Read / Write Default Value: 00000000 7 6 5 4 3 2 1 0 DIRECT_DIV LOCK_8K BUCKET_SEL1 BUCKET_SEL0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0 Bit Name Description 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 17H). This bit, together with the DIRECT_DIV bit (b7, 17H), determines whether the DivN Divider or the Lock 8k Divider is used for IN4: 6 5-4 3-0 LOCK_8K DIRECT_DIV bit LOCK_8K bit Used Divider 0 0 1 1 0 1 0 1 Both bypassed (default) Lock 8k Divider DivN Divider Reserved These bits select one of the four groups of leaky bucket configuration registers for IN4: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. These bits set the DPLL required frequency for IN4: 0000: 8 kHz. (default) 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’). 0010: 6.48 MHz. 0011: 19.44 MHz. 0100: 25.92 MHz. IN_FREQ[3:0] 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. For the IN4, the required frequency should not be set higher than that of the input clock. Programming Information 81 April 15, 2015 IDT82V3280 WAN PLL IN5_IN6_HF_DIV_CNFG - Input Clock 5 & 6 High Frequency Divider Configuration Address: 18H Type: Read / Write Default Value: 00XXXX00 7 6 5 4 3 2 1 0 IN6_DIV1 IN6_DIV0 - - - - IN5_DIV1 IN5_DIV0 Bit Name 7-6 IN6_DIV[1:0] 5-2 - 1-0 IN5_DIV[1:0] Programming Information Description These bits determine whether the HF Divider is used and what the division factor is for IN6 frequency division: 00: Bypassed. (default) 01: Divided by 4. 10: Divided by 5. 11: Reserved. Reserved. These bits determine whether the HF Divider is used and what the division factor is for IN5 frequency division: 00: Bypassed. (default) 01: Divided by 4. 10: Divided by 5. 11: Reserved. 82 April 15, 2015 IDT82V3280 WAN PLL IN5_CNFG - Input Clock 5 Configuration Address: 19H Type: Read / Write Default Value: 00000011 7 6 5 4 3 2 1 0 DIRECT_DIV LOCK_8K BUCKET_SEL1 BUCKET_SEL0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0 Bit Name Description 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 19H). This bit, together with the DIRECT_DIV bit (b7, 19H), determines whether the DivN Divider or the Lock 8k Divider is used for IN5: 6 5-4 3-0 LOCK_8K DIRECT_DIV bit LOCK_8K bit Used Divider 0 0 1 1 0 1 0 1 Both bypassed (default) Lock 8k Divider DivN Divider Reserved These bits select one of the four groups of leaky bucket configuration registers for IN5: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. These bits set the DPLL required frequency for IN5: 0000: 8 kHz. 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’). 0010: 6.48 MHz. 0011: 19.44 MHz. (default) 0100: 25.92 MHz. IN_FREQ[3:0] 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. The required frequency should not be set higher than that of the input clock. Programming Information 83 April 15, 2015 IDT82V3280 WAN PLL IN6_CNFG - Input Clock 6 Configuration Address: 1AH Type: Read / Write Default Value: 00000011 7 6 5 4 3 2 1 0 DIRECT_DIV LOCK_8K BUCKET_SEL1 BUCKET_SEL0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0 Bit Name Description 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 1AH). This bit, together with the DIRECT_DIV bit (b7, 1AH), determines whether the DivN Divider or the Lock 8k Divider is used for IN6: 6 5-4 3-0 LOCK_8K DIRECT_DIV bit LOCK_8K bit Used Divider 0 0 1 1 0 1 0 1 Both bypassed (default) Lock 8k Divider DivN Divider Reserved These bits select one of the four groups of leaky bucket configuration registers for IN6: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. These bits set the DPLL required frequency for IN6: 0000: 8 kHz. 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’). 0010: 6.48 MHz. 0011: 19.44 MHz. (default) 0100: 25.92 MHz. IN_FREQ[3:0] 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. For IN6, the required frequency should not be set higher than that of the input clock. Programming Information 84 April 15, 2015 IDT82V3280 WAN PLL IN7_CNFG - Input Clock 7 Configuration Address: 1BH Type: Read / Write Default Value: 00000011 7 6 5 4 3 2 1 0 DIRECT_DIV LOCK_8K BUCKET_SEL1 BUCKET_SEL0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0 Bit Name Description 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 1BH). This bit, together with the DIRECT_DIV bit (b7, 1BH), determines whether the DivN Divider or the Lock 8k Divider is used for IN7: 6 5-4 3-0 LOCK_8K DIRECT_DIV bit LOCK_8K bit Used Divider 0 0 1 1 0 1 0 1 Both bypassed (default) Lock 8k Divider DivN Divider Reserved These bits select one of the four groups of leaky bucket configuration registers for IN7: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. These bits set the DPLL required frequency for IN7: 0000: 8 kHz. 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’). 0010: 6.48 MHz. 0011: 19.44 MHz. (default) 0100: 25.92 MHz. IN_FREQ[3:0] 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. For IN7, the required frequency should not be set higher than that of the input clock. Programming Information 85 April 15, 2015 IDT82V3280 WAN PLL IN8_CNFG - Input Clock 8 Configuration Address: 1CH Type: Read / Write Default Value: 00000011 7 6 5 4 3 2 1 0 DIRECT_DIV LOCK_8K BUCKET_SEL1 BUCKET_SEL0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0 Bit Name Description 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 1CH). This bit, together with the DIRECT_DIV bit (b7, 1CH), determines whether the DivN Divider or the Lock 8k Divider is used for IN8: 6 LOCK_8K 5-4 3-0 DIRECT_DIV bit LOCK_8K bit Used Divider 0 0 1 1 0 1 0 1 Both bypassed (default) Lock 8k Divider DivN Divider Reserved These bits select one of the four groups of leaky bucket configuration registers for IN8: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. These bits set the DPLL required frequency for IN8: 0000: 8 kHz. 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’). 0010: 6.48 MHz. 0011: 19.44 MHz. (default) 0100: 25.92 MHz. IN_FREQ[3:0] 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. For IN8, the required frequency should not be set higher than that of the input clock. Programming Information 86 April 15, 2015 IDT82V3280 WAN PLL IN9_CNFG - Input Clock 9 Configuration Address: 1DH Type: Read / Write Default Value: 00000011 7 6 5 4 3 2 1 0 DIRECT_DIV LOCK_8K BUCKET_SEL1 BUCKET_SEL0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0 Bit Name Description 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 1DH). This bit, together with the DIRECT_DIV bit (b7, 1DH), determines whether the DivN Divider or the Lock 8k Divider is used for IN9: 6 5-4 3-0 LOCK_8K DIRECT_DIV bit LOCK_8K bit Used Divider 0 0 1 1 0 1 0 1 Both bypassed (default) Lock 8k Divider DivN Divider Reserved These bits select one of the four groups of leaky bucket configuration registers for IN9: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. These bits set the DPLL required frequency for IN9: 0000: 8 kHz. 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’). 0010: 6.48 MHz. 0011: 19.44 MHz. (default) 0100: 25.92 MHz. IN_FREQ[3:0] 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. For IN9, the required frequency should not be set higher than that of the input clock. Programming Information 87 April 15, 2015 IDT82V3280 WAN PLL IN10_CNFG - Input Clock 10 Configuration Address: 1EH Type: Read / Write Default Value: 00000011 7 6 5 4 3 2 1 0 DIRECT_DIV LOCK_8K BUCKET_SEL1 BUCKET_SEL0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0 Bit Name Description 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 1EH). This bit, together with the DIRECT_DIV bit (b7, 1EH), determines whether the DivN Divider or the Lock 8k Divider is used for IN10: 6 5-4 3-0 LOCK_8K DIRECT_DIV bit LOCK_8K bit Used Divider 0 0 1 1 0 1 0 1 Both bypassed (default) Lock 8k Divider DivN Divider Reserved These bits select one of the four groups of leaky bucket configuration registers for IN10: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. These bits set the DPLL required frequency for IN10: 0000: 8 kHz. 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’). 0010: 6.48 MHz. 0011: 19.44 MHz. (default) 0100: 25.92 MHz. IN_FREQ[3:0] 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. For IN10, the required frequency should not be set higher than that of the input clock. Programming Information 88 April 15, 2015 IDT82V3280 WAN PLL IN11_CNFG - Input Clock 11 Configuration Address: 1FH Type: Read / Write Default Value: 0000XXXX 7 6 5 4 3 2 1 0 DIRECT_DIV LOCK_8K BUCKET_SEL1 BUCKET_SEL0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0 Bit Name Description 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 1FH). This bit, together with the DIRECT_DIV bit (b7, 1FH), determines whether the DivN Divider or the Lock 8k Divider is used for IN11: 6 5-4 3-0 LOCK_8K DIRECT_DIV bit LOCK_8K bit Used Divider 0 0 1 1 0 1 0 1 Both bypassed (default) Lock 8k Divider DivN Divider Reserved These bits select one of the four groups of leaky bucket configuration registers for IN11: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. These bits set the DPLL required frequency for IN11: 0000: 8 kHz. 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’). 0010: 6.48 MHz. 0011: 19.44 MHz. 0100: 25.92 MHz. 0101: 38.88 MHz. IN_FREQ[3:0] 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. For IN11, the required frequency should not be set higher than that of the input clock. The default value of these bits depends on the device application as follows: In Master / Slave application, when the device is configured as the Master, the default value is ‘0001’; when the device is configured as the Slave, the default value is ‘0010’. Programming Information 89 April 15, 2015 IDT82V3280 WAN PLL IN12_CNFG - Input Clock 12 Configuration Address: 20H Type: Read / Write Default Value: 00000001 7 6 5 4 3 2 1 0 DIRECT_DIV LOCK_8K BUCKET_SEL1 BUCKET_SEL0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0 Bit Name Description 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 20H). This bit, together with the DIRECT_DIV bit (b7, 20H), determines whether the DivN Divider or the Lock 8k Divider is used for IN12: 6 5-4 3-0 LOCK_8K DIRECT_DIV bit LOCK_8K bit Used Divider 0 0 1 1 0 1 0 1 Both bypassed (default) Lock 8k Divider DivN Divider Reserved These bits select one of the four groups of leaky bucket configuration registers for IN12: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. These bits set the DPLL required frequency for IN12: 0000: 8 kHz. 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’). (default) 0010: 6.48 MHz. 0011: 19.44 MHz. IN_FREQ[3:0] 0100: 25.92 MHz. 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. For IN12, the required frequency should not be set higher than that of the input clock. Programming Information 90 April 15, 2015 IDT82V3280 WAN PLL IN13_CNFG - Input Clock 13 Configuration Address: 21H Type: Read / Write Default Value: 00000001 7 6 5 4 3 2 1 0 DIRECT_DIV LOCK_8K BUCKET_SEL1 BUCKET_SEL0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0 Bit Name Description 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 21H). This bit, together with the DIRECT_DIV bit (b7, 21H), determines whether the DivN Divider or the Lock 8k Divider is used for IN13: 6 5-4 3-0 LOCK_8K DIRECT_DIV bit LOCK_8K bit Used Divider 0 0 1 1 0 1 0 1 Both bypassed (default) Lock 8k Divider DivN Divider Reserved These bits select one of the four groups of leaky bucket configuration registers for IN13: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. These bits set the DPLL required frequency for IN13: 0000: 8 kHz. 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’). (default) 0010: 6.48 MHz. 0011: 19.44 MHz. IN_FREQ[3:0] 0100: 25.92 MHz. 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. For IN13, the required frequency should not be set higher than that of the input clock. Programming Information 91 April 15, 2015 IDT82V3280 WAN PLL IN14_CNFG - Input Clock 14 Configuration Address: 22H Type: Read / Write Default Value: 00000001 7 6 5 4 3 2 1 0 DIRECT_DIV LOCK_8K BUCKET_SEL1 BUCKET_SEL0 IN_FREQ3 IN_FREQ2 IN_FREQ1 IN_FREQ0 Bit Name Description 7 DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 22H). This bit, together with the DIRECT_DIV bit (b7, 22H), determines whether the DivN Divider or the Lock 8k Divider is used for IN14: 6 5-4 3-0 LOCK_8K DIRECT_DIV bit LOCK_8K bit Used Divider 0 0 1 1 0 1 0 1 Both bypassed (default) Lock 8k Divider DivN Divider Reserved These bits select one of the four groups of leaky bucket configuration registers for IN14: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. These bits set the DPLL required frequency for IN14: 0000: 8 kHz. 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’). (default) 0010: 6.48 MHz. 0011: 19.44 MHz. IN_FREQ[3:0] 0100: 25.92 MHz. 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. For IN14, the required frequency should not be set higher than that of the input clock. Programming Information 92 April 15, 2015 IDT82V3280 WAN PLL PRE_DIV_CH_CNFG - DivN Divider Channel Selection Address: 23H Type: Read / Write Default Value: XXXX0000 7 6 5 4 3 2 1 0 - - - - PRE_DIV_CH_VALUE3 PRE_DIV_CH_VALUE2 PRE_DIV_CH_VALUE1 PRE_DIV_CH_VALUE0 Bit Name 7-4 - Description Reserved. This register is an indirect address register for Register 24H and 25H. These bits select an input clock. The value set in the PRE_DIVN_VALUE[14:0] bits (25H, 24H) is available for the selected input clock. 0000: Reserved. (default) 0001, 0010: Reserved. PRE_DIV_CH_VALUE[3:0] 0011: IN3. 0100: IN4. ...... 1101: IN13. 1110: IN14. 1111: Reserved. 3-0 PRE_DIVN[7:0]_CNFG - DivN Divider Division Factor Configuration 1 Address: 24H Type: Read / Write Default Value: 00000000 7 6 5 4 3 2 1 0 PRE_DIVN_VA LUE7 PRE_DIVN_VA LUE6 PRE_DIVN_VA LUE5 PRE_DIVN_VA LUE4 PRE_DIVN_VA LUE3 PRE_DIVN_VA LUE2 PRE_DIVN_VA LUE1 PRE_DIVN_VA LUE0 Bit 7-0 Name Description PRE_DIVN_VALUE[7:0] Refer to the description of the PRE_DIVN_VALUE[14:8] bits (b6~0, 25H). Programming Information 93 April 15, 2015 IDT82V3280 WAN PLL PRE_DIVN[14:8]_CNFG - DivN Divider Division Factor Configuration 2 Address: 25H Type: Read / Write Default Value: X0000000 7 6 5 4 3 2 1 0 - PRE_DIVN_VAL UE14 PRE_DIVN_VAL UE13 PRE_DIVN_VAL UE12 PRE_DIVN_VAL UE11 PRE_DIVN_VAL UE10 PRE_DIVN_VAL UE9 PRE_DIVN_VAL UE8 Bit Name Description 7 - 6-0 PRE_DIVN_VALUE[14:8] Reserved. If the value in the PRE_DIVN_VALUE[14:0] bits is plus 1, the division factor for an input clock will be gotten. The input clock is selected by the PRE_DIV_CH_VALUE[3:0] bits (b3~0, 23H). A value from ‘0’ to ‘4BEF’ (Hex) can be written into, corresponding to a division factor from 1 to 19440. The others are reserved. So the DivN Divider only supports an input clock whose frequency is lower than () 155.52 MHz. The division factor setting should observe the following order: 1. Write the lower eight bits of the division factor to the PRE_DIVN_VALUE[7:0] bits; 2. Write the higher eight bits of the division factor to the PRE_DIVN_VALUE[14:8] bits. Programming Information 94 April 15, 2015 IDT82V3280 WAN PLL IN1_IN2_SEL_PRIORITY_CNFG - Input Clock 1 & 2 Priority Configuration * Address: 26H Type: Read / Write Default Value: T0 - 00110010 / T4 - 00000000 7 6 5 4 3 2 1 0 IN2_SEL_PRIORITY3 IN2_SEL_PRIORITY2 IN2_SEL_PRIORITY1 IN2_SEL_PRIORITY0 IN1_SEL_PRIORITY3 IN1_SEL_PRIORITY2 IN1_SEL_PRIORITY1 IN1_SEL_PRIORITY0 Bit 7-4 3-0 Name Description These bits set the priority of the corresponding INn. Here n is 2: 0000: Disable INn for automatic selection. (T4 default) 0001: Priority 1. 0010: Priority 2. 0011: Priority 3. (T0 default) 0100: Priority 4. 0101: Priority 5. 0110: Priority 6. INn_SEL_PRIORITY[3:0] 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. These bits set the priority of the corresponding INn. Here n is 1: 0000: Disable INn for automatic selection. (T4 default) 0001: Priority 1. 0010: Priority 2. (T0 default) 0011: Priority 3. 0100: Priority 4. 0101: Priority 5. 0110: Priority 6. INn_SEL_PRIORITY[3:0] 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. Programming Information 95 April 15, 2015 IDT82V3280 WAN PLL IN3_IN4_SEL_PRIORITY_CNFG - Input Clock 3 & 4 Priority Configuration * Address: 27H Type: Read / Write Default Value: T0 - 01010100 / T4 - 00000000 7 6 5 4 3 2 1 0 IN4_SEL_PRIORITY3 IN4_SEL_PRIORITY2 IN4_SEL_PRIORITY1 IN4_SEL_PRIORITY0 IN3_SEL_PRIORITY3 IN3_SEL_PRIORITY2 IN3_SEL_PRIORITY1 IN3_SEL_PRIORITY0 Bit Name 7-4 INn_SEL_PRIORITY[3:0] 3-0 INn_SEL_PRIORITY[3:0] Programming Information Description These bits set the priority of the corresponding INn. Here n is 4. 0000: Disable INn for automatic selection. (T4 default) 0001: Priority 1. 0010: Priority 2. 0011: Priority 3. 0100: Priority 4. 0101: Priority 5. (T0 default) 0110: Priority 6. 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. These bits set the priority of the corresponding INn. Here n is 3. 0000: Disable INn for automatic selection. (T4 default) 0001: Priority 1. 0010: Priority 2. 0011: Priority 3. 0100: Priority 4. (T0 default) 0101: Priority 5. 0110: Priority 6. 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. 96 April 15, 2015 IDT82V3280 WAN PLL IN5_IN6_SEL_PRIORITY_CNFG - Input Clock 5 & 6 Priority Configuration * Address: 28H Type: Read / Write Default Value: T0/T4 - 01110110 7 6 5 4 3 2 1 0 IN6_SEL_PRIORITY3 IN6_SEL_PRIORITY2 IN6_SEL_PRIORITY1 IN6_SEL_PRIORITY0 IN5_SEL_PRIORITY3 IN5_SEL_PRIORITY2 IN5_SEL_PRIORITY1 IN5_SEL_PRIORITY0 Bit Name 7-4 INn_SEL_PRIORITY[3:0] 3-0 INn_SEL_PRIORITY[3:0] Programming Information Description These bits set the priority of the corresponding INn. Here n is 6. 0000: Disable INn for automatic selection. 0001: Priority 1. 0010: Priority 2. 0011: Priority 3. 0100: Priority 4. 0101: Priority 5. 0110: Priority 6. 0111: Priority 7. (default) 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. These bits set the priority of the corresponding INn. Here n is 5. 0000: Disable INn for automatic selection. 0001: Priority 1. 0010: Priority 2. 0011: Priority 3. 0100: Priority 4. 0101: Priority 5. 0110: Priority 6. (default) 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. 97 April 15, 2015 IDT82V3280 WAN PLL IN7_IN8_SEL_PRIORITY_CNFG - Input Clock 7 & 8 Priority Configuration * Address: 29H Type: Read / Write Default Value: 10011000 7 6 5 4 3 2 1 0 IN8_SEL_PRIORITY3 IN8_SEL_PRIORITY2 IN8_SEL_PRIORITY1 IN8_SEL_PRIORITY0 IN7_SEL_PRIORITY3 IN7_SEL_PRIORITY2 IN7_SEL_PRIORITY1 IN7_SEL_PRIORITY0 Bit 7-4 3-0 Name Description These bits set the priority of the corresponding INn. Here n is 8. 0000: Disable INn for automatic selection. 0001: Priority 1. 0010: Priority 2. 0011: Priority 3. 0100: Priority 4. 0101: Priority 5. 0110: Priority 6. INn_SEL_PRIORITY[3:0] 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. (default) 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. These bits set the priority of the corresponding INn. Here n is 7. 0000: Disable INn for automatic selection. 0001: Priority 1. 0010: Priority 2. 0011: Priority 3. 0100: Priority 4. 0101: Priority 5. 0110: Priority 6. INn_SEL_PRIORITY[3:0] 0111: Priority 7. 1000: Priority 8. (default) 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. Programming Information 98 April 15, 2015 IDT82V3280 WAN PLL IN9_IN10_SEL_PRIORITY_CNFG - Input Clock 9 & 10 Priority Configuration * Address: 2AH Type: Read / Write Default Value: 10111010 7 6 5 4 3 2 1 0 IN10_SEL_PRIORITY3 IN10_SEL_PRIORITY2 IN10_SEL_PRIORITY1 IN10_SEL_PRIORITY0 IN9_SEL_PRIORITY3 IN9_SEL_PRIORITY2 IN9_SEL_PRIORITY1 IN9_SEL_PRIORITY0 Bit Name 7-4 INn_SEL_PRIORITY[3:0] 3-0 INn_SEL_PRIORITY[3:0] Programming Information Description These bits set the priority of the corresponding INn. Here n is 10. 0000: Disable INn for automatic selection. 0001: Priority 1. 0010: Priority 2. 0011: Priority 3. 0100: Priority 4. 0101: Priority 5. 0110: Priority 6. 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. (default) 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. These bits set the priority of the corresponding INn. Here n is 9. 0000: Disable INn for automatic selection. 0001: Priority 1. 0010: Priority 2. 0011: Priority 3. 0100: Priority 4. 0101: Priority 5. 0110: Priority 6. 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. (default) 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. 99 April 15, 2015 IDT82V3280 WAN PLL IN11_IN12_SEL_PRIORITY_CNFG - Input Clock 11 & 12 Priority Configuration * Address: 2BH Type: Read / Write Default Value: 11011100 (T0 Master)/11010001 (T0 Slave) 00000000 (T4) 7 6 5 4 3 2 1 0 IN12_SEL_PRIORITY3 IN12_SEL_PRIORITY2 IN12_SEL_PRIORITY1 IN12_SEL_PRIORITY0 IN11_SEL_PRIORITY3 IN11_SEL_PRIORITY2 IN11_SEL_PRIORITY1 IN11_SEL_PRIORITY0 Bit 7-4 3-0 Name Description These bits set the priority of the corresponding INn. Here n is 12: 0000: Disable INn for automatic selection. (T4 default) 0001: Priority 1. 0010: Priority 2. 0011: Priority 3. 0100: Priority 4. 0101: Priority 5. 0110: Priority 6. INn_SEL_PRIORITY[3:0] 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. (T0 Master/Slave default) 1110: Priority 14. 1111: Priority 15. These bits set the priority of the corresponding INn. Here n is 11: 0000: Disable INn for automatic selection. (T4 default) 0001: Priority 1. (T0 Slave default) 0010: Priority 2. 0011: Priority 3. 0100: Priority 4. 0101: Priority 5. 0110: Priority 6. INn_SEL_PRIORITY[3:0] 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. (T0 Master default) 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. Programming Information 100 April 15, 2015 IDT82V3280 WAN PLL IN13_IN14_SEL_PRIORITY_CNFG - Input Clock 13 & 14 Priority Configuration * Address: 2CH Type: Read / Write Default Value: 11111110 (T0) 00000000 (T4) 7 6 5 4 3 2 1 0 IN14_SEL_PRIORITY3 IN14_SEL_PRIORITY2 IN14_SEL_PRIORITY1 IN14_SEL_PRIORITY0 IN13_SEL_PRIORITY3 IN13_SEL_PRIORITY2 IN13_SEL_PRIORITY1 IN13_SEL_PRIORITY0 Bit Name 7-4 INn_SEL_PRIORITY[3:0] 3-0 INn_SEL_PRIORITY[3:0] Programming Information Description These bits set the priority of the corresponding INn. Here n is 14: 0000: Disable INn for automatic selection. (T4 default) 0001: Priority 1. 0010: Priority 2. 0011: Priority 3. 0100: Priority 4. 0101: Priority 5. 0110: Priority 6. 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. (T0 default) These bits set the priority of the corresponding INn. Here n is 13: 0000: Disable INn for automatic selection. (T4 default) 0001: Priority 1. 0010: Priority 2. 0011: Priority 3. 0100: Priority 4. 0101: Priority 5. 0110: Priority 6. 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. (T0 default) 1111: Priority 15. 101 April 15, 2015 IDT82V3280 7.2.4 WAN PLL INPUT CLOCK QUALITY MONITORING CONFIGURATION & STATUS REGISTERS FREQ_MON_FACTOR_CNFG - Factor of Frequency Monitor Configuration Address: 2EH Type: Read / Write Default Value: XXXX1011 7 6 5 4 3 2 1 0 - - - - FREQ_MON_FACTOR3 FREQ_MON_FACTOR2 FREQ_MON_FACTOR1 FREQ_MON_FACTOR0 Bit Name 7-4 - 3-0 Description Reserved. These bits determine a factor. The factor has a relationship with the frequency hard alarm threshold in ppm (refer to the description of the ALL_FREQ_HARD_THRESHOLD[3:0] bits (b3~0, 2FH)) and with the frequency of the input clock with respect to the master clock in ppm (refer to the description of the IN_FREQ_VALUE[7:0] bits (b7~0, 42H)). The factor represents the accuracy of the frequency monitor and should be set according to the requirements of different applications. 0000: 0.0032. 0001: 0.0064. 0010: 0.0127. 0011: 0.0257. FREQ_MON_FACTOR[3:0] 0100: 0.0514. 0101: 0.103. 0110: 0.206. 0111: 0.412. 1000: 0.823. 1001: 1.646. 1010: 3.292. 1011: 3.81. (default) 1100 - 1111: 4.6. ALL_FREQ_MON_THRESHOLD_CNFG - Frequency Monitor Threshold for All Input Clocks Configuration Address: 2FH Type: Read / Write Default Value: XXXX0011 7 6 5 4 3 2 1 0 - - - - ALL_FREQ_HARD_THRESHOLD3 ALL_FREQ_HARD_THRESHOLD2 ALL_FREQ_HARD_THRESHOLD1 ALL_FREQ_HARD_THRESHOLD0 Bit Name 7-4 - 3-0 Description Reserved. These bits represent an unsigned integer. The frequency hard alarm threshold in ppm can be calculated as follows: ALL_FREQ_HARD_THRESHOLD[3:0] Frequency Hard Alarm Threshold (ppm) = (ALL_FREQ_HARD_THRESHOLD[3:0] + 1) X FREQ_MON_FACTOR[3:0] (b3~0, 2EH) This threshold is symmetrical about zero. Programming Information 102 April 15, 2015 IDT82V3280 WAN PLL UPPER_THRESHOLD_0_CNFG - Upper Threshold for Leaky Bucket Configuration 0 Address: 31H Type: Read / Write Default Value: 00000110 7 6 5 4 3 2 1 0 UPPER_THRESHOLD_0_DATA7 UPPER_THRESHOLD_0_DATA6 UPPER_THRESHOLD_0_DATA5 UPPER_THRESHOLD_0_DATA4 UPPER_THRESHOLD_0_DATA3 UPPER_THRESHOLD_0_DATA2 UPPER_THRESHOLD_0_DATA1 UPPER_THRESHOLD_0_DATA0 Bit Name Description 7-0 UPPER_THRESHOLD_0_DATA[7:0] These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumulated events is above this threshold, a no-activity alarm is raised. LOWER_THRESHOLD_0_CNFG - Lower Threshold for Leaky Bucket Configuration 0 Address: 32H Type: Read / Write Default Value: 00000100 7 6 5 4 3 2 1 0 LOWER_THRESHOLD_0_DATA7 LOWER_THRESHOLD_0_DATA6 LOWER_THRESHOLD_0_DATA5 LOWER_THRESHOLD_0_DATA4 LOWER_THRESHOLD_0_DATA3 LOWER_THRESHOLD_0_DATA2 LOWER_THRESHOLD_0_DATA1 LOWER_THRESHOLD_0_DATA0 Bit Name Description 7-0 LOWER_THRESHOLD_0_DATA[7:0] These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumulated events is below this threshold, the no-activity alarm is cleared. BUCKET_SIZE_0_CNFG - Bucket Size for Leaky Bucket Configuration 0 Address: 33H Type: Read / Write Default Value: 00001000 7 6 5 4 3 2 1 0 BUCKET_SIZE_0_DATA7 BUCKET_SIZE_0_DATA6 BUCKET_SIZE_0_DATA5 BUCKET_SIZE_0_DATA4 BUCKET_SIZE_0_DATA3 BUCKET_SIZE_0_DATA2 BUCKET_SIZE_0_DATA1 BUCKET_SIZE_0_DATA0 Bit Name Description 7-0 BUCKET_SIZE_0_DATA[7:0] These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach the bucket size, the accumulator will stop increasing even if further events are detected. Programming Information 103 April 15, 2015 IDT82V3280 WAN PLL DECAY_RATE_0_CNFG - Decay Rate for Leaky Bucket Configuration 0 Address: 34H Type: Read / Write Default Value: XXXXXX01 7 6 5 4 3 2 1 0 - - - - - - DECAY_RATE_ 0_DATA1 DECAY_RATE_ 0_DATA0 Bit Name 7-2 - Description Reserved. These bits set a decay rate for the internal leaky bucket accumulator: 00: The accumulator decreases by 1 in every 128 ms with no event detected. DECAY_RATE_0_DATA[1:0] 01: The accumulator decreases by 1 in every 256 ms with no event detected. (default) 10: The accumulator decreases by 1 in every 512 ms with no event detected. 11: The accumulator decreases by 1 in every 1024 ms with no event detected. 1-0 UPPER_THRESHOLD_1_CNFG - Upper Threshold for Leaky Bucket Configuration 1 Address: 35H Type: Read / Write Default Value: 00000110 7 6 5 4 3 2 1 0 UPPER_THRESHOLD_1_DATA7 UPPER_THRESHOLD_1_DATA6 UPPER_THRESHOLD_1_DATA5 UPPER_THRESHOLD_1_DATA4 UPPER_THRESHOLD_1_DATA3 UPPER_THRESHOLD_1_DATA2 UPPER_THRESHOLD_1_DATA1 UPPER_THRESHOLD_1_DATA0 Bit Name Description 7-0 UPPER_THRESHOLD_1_DATA[7:0] These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumulated events is above this threshold, a no-activity alarm is raised. LOWER_THRESHOLD_1_CNFG - Lower Threshold for Leaky Bucket Configuration 1 Address: 36H Type: Read / Write Default Value: 00000100 7 6 5 4 3 2 1 0 LOWER_THRESHOLD_1_DATA7 LOWER_THRESHOLD_1_DATA6 LOWER_THRESHOLD_1_DATA5 LOWER_THRESHOLD_1_DATA4 LOWER_THRESHOLD_1_DATA3 LOWER_THRESHOLD_1_DATA2 LOWER_THRESHOLD_1_DATA1 LOWER_THRESHOLD_1_DATA0 Bit 7-0 Name Description These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumulated LOWER_THRESHOLD_1_DATA[7:0] events is below this threshold, the no-activity alarm is cleared. Programming Information 104 April 15, 2015 IDT82V3280 WAN PLL BUCKET_SIZE_1_CNFG - Bucket Size for Leaky Bucket Configuration 1 Address: 37H Type: Read / Write Default Value: 00001000 7 6 5 4 3 2 1 0 BUCKET_SIZE_1_DATA7 BUCKET_SIZE_1_DATA6 BUCKET_SIZE_1_DATA5 BUCKET_SIZE_1_DATA4 BUCKET_SIZE_1_DATA3 BUCKET_SIZE_1_DATA2 BUCKET_SIZE_1_DATA1 BUCKET_SIZE_1_DATA0 Bit Name Description 7-0 BUCKET_SIZE_1_DATA[7:0] These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach the bucket size, the accumulator will stop increasing even if further events are detected. DECAY_RATE_1_CNFG - Decay Rate for Leaky Bucket Configuration 1 Address: 38H Type: Read / Write Default Value: XXXXXX01 7 6 5 4 3 2 1 0 - - - - - - DECAY_RATE_ 1_DATA1 DECAY_RATE_ 1_DATA0 Bit Name 7-2 - Description Reserved. These bits set a decay rate for the internal leaky bucket accumulator: 00: The accumulator decreases by 1 in every 128 ms with no event detected. DECAY_RATE_1_DATA[1:0] 01: The accumulator decreases by 1 in every 256 ms with no event detected. (default) 10: The accumulator decreases by 1 in every 512 ms with no event detected. 11: The accumulator decreases by 1 in every 1024 ms with no event detected. 1-0 UPPER_THRESHOLD_2_CNFG - Upper Threshold for Leaky Bucket Configuration 2 Address: 39H Type: Read / Write Default Value: 00000110 7 6 5 4 3 2 1 0 UPPER_THRESHOLD_2_DATA7 UPPER_THRESHOLD_2_DATA6 UPPER_THRESHOLD_2_DATA5 UPPER_THRESHOLD_2_DATA4 UPPER_THRESHOLD_2_DATA3 UPPER_THRESHOLD_2_DATA2 UPPER_THRESHOLD_2_DATA1 UPPER_THRESHOLD_2_DATA0 Bit 7-0 Name Description These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumuUPPER_THRESHOLD_2_DATA[7:0] lated events is above this threshold, a no-activity alarm is raised. Programming Information 105 April 15, 2015 IDT82V3280 WAN PLL LOWER_THRESHOLD_2_CNFG - Lower Threshold for Leaky Bucket Configuration 2 Address: 3AH Type: Read / Write Default Value: 00000100 7 6 5 4 3 2 1 0 LOWER_THRESHOLD_2_DATA7 LOWER_THRESHOLD_2_DATA6 LOWER_THRESHOLD_2_DATA5 LOWER_THRESHOLD_2_DATA4 LOWER_THRESHOLD_2_DATA3 LOWER_THRESHOLD_2_DATA2 LOWER_THRESHOLD_2_DATA1 LOWER_THRESHOLD_2_DATA0 Bit Name Description 7-0 LOWER_THRESHOLD_2_DATA[7:0] These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumulated events is below this threshold, the no-activity alarm is cleared. BUCKET_SIZE_2_CNFG - Bucket Size for Leaky Bucket Configuration 2 Address: 3BH Type: Read / Write Default Value: 00001000 7 6 5 4 3 2 1 0 BUCKET_SIZE_2_DATA7 BUCKET_SIZE_2_DATA6 BUCKET_SIZE_2_DATA5 BUCKET_SIZE_2_DATA4 BUCKET_SIZE_2_DATA3 BUCKET_SIZE_2_DATA2 BUCKET_SIZE_2_DATA1 BUCKET_SIZE_2_DATA0 Bit Name Description 7-0 BUCKET_SIZE_2_DATA[7:0] These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach the bucket size, the accumulator will stop increasing even if further events are detected. DECAY_RATE_2_CNFG - Decay Rate for Leaky Bucket Configuration 2 Address: 3CH Type: Read / Write Default Value: XXXXXX01 7 6 5 4 3 2 1 0 - - - - - - DECAY_RATE_ 2_DATA1 DECAY_RATE_ 2_DATA0 Bit Name 7-2 - 1-0 Description Reserved. These bits set a decay rate for the internal leaky bucket accumulator: 00: The accumulator decreases by 1 in every 128 ms with no event detected. DECAY_RATE_2_DATA[1:0] 01: The accumulator decreases by 1 in every 256 ms with no event detected. (default) 10: The accumulator decreases by 1 in every 512 ms with no event detected. 11: The accumulator decreases by 1 in every 1024 ms with no event detected. Programming Information 106 April 15, 2015 IDT82V3280 WAN PLL UPPER_THRESHOLD_3_CNFG - Upper Threshold for Leaky Bucket Configuration 3 Address: 3DH Type: Read / Write Default Value: 00000110 7 6 5 4 3 2 1 0 UPPER_THRESHOLD_3_DATA7 UPPER_THRESHOLD_3_DATA6 UPPER_THRESHOLD_3_DATA5 UPPER_THRESHOLD_3_DATA4 UPPER_THRESHOLD_3_DATA3 UPPER_THRESHOLD_3_DATA2 UPPER_THRESHOLD_3_DATA1 UPPER_THRESHOLD_3_DATA0 Bit Name Description 7-0 UPPER_THRESHOLD_3_DATA[7:0] These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumulated events is above this threshold, a no-activity alarm is raised. LOWER_THRESHOLD_3_CNFG - Lower Threshold for Leaky Bucket Configuration 3 Address: 3EH Type: Read / Write Default Value: 00000100 7 6 5 4 3 2 1 0 LOWER_THRESHOLD_3_DATA7 LOWER_THRESHOLD_3_DATA6 LOWER_THRESHOLD_3_DATA5 LOWER_THRESHOLD_3_DATA4 LOWER_THRESHOLD_3_DATA3 LOWER_THRESHOLD_3_DATA2 LOWER_THRESHOLD_3_DATA1 LOWER_THRESHOLD_3_DATA0 Bit Name Description 7-0 LOWER_THRESHOLD_3_DATA[7:0] These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumulated events is below this threshold, the no-activity alarm is cleared. BUCKET_SIZE_3_CNFG - Bucket Size for Leaky Bucket Configuration 3 Address: 3FH Type: Read / Write Default Value: 00001000 7 6 5 4 3 2 1 0 BUCKET_SIZE_3_DATA7 BUCKET_SIZE_3_DATA6 BUCKET_SIZE_3_DATA5 BUCKET_SIZE_3_DATA4 BUCKET_SIZE_3_DATA3 BUCKET_SIZE_3_DATA2 BUCKET_SIZE_3_DATA1 BUCKET_SIZE_3_DATA0 Bit Name Description 7-0 BUCKET_SIZE_3_DATA[7:0] These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach the bucket size, the accumulator will stop increasing even if further events are detected. Programming Information 107 April 15, 2015 IDT82V3280 WAN PLL DECAY_RATE_3_CNFG - Decay Rate for Leaky Bucket Configuration 3 Address: 40H Type: Read / Write Default Value: XXXXXX01 7 6 5 4 3 2 1 0 - - - - - - DECAY_RATE_ 3_DATA1 DECAY_RATE_ 3_DATA0 Bit Name 7-2 - Description Reserved. These bits set a decay rate for the internal leaky bucket accumulator: 00: The accumulator decreases by 1 in every 128 ms with no event detected. DECAY_RATE_3_DATA[1:0] 01: The accumulator decreases by 1 in every 256 ms with no event detected. (default) 10: The accumulator decreases by 1 in every 512 ms with no event detected. 11: The accumulator decreases by 1 in every 1024 ms with no event detected. 1-0 IN_FREQ_READ_CH_CNFG - Input Clock Frequency Read Channel Selection Address: 41H Type: Read / Write Default Value: XXXX0000 7 6 5 4 3 2 1 0 - - - - IN_FREQ_READ_CH3 IN_FREQ_READ_CH2 IN_FREQ_READ_CH1 IN_FREQ_READ_CH0 Bit Name 7-4 - 3-0 Description Reserved. These bits select an input clock, the frequency of which with respect to the reference clock can be read. 0000: Reserved. (default) 0001: IN1. 0010: IN2. IN_FREQ_READ_CH[3:0] ...... 1101: IN13. 1110: IN14. 1111: Reserved. Programming Information 108 April 15, 2015 IDT82V3280 WAN PLL IN_FREQ_READ_STS - Input Clock Frequency Read Value Address: 42H Type: Read Default Value: 00000000 7 6 5 4 3 2 1 0 IN_FREQ_VALUE7 IN_FREQ_VALUE6 IN_FREQ_VALUE5 IN_FREQ_VALUE4 IN_FREQ_VALUE3 IN_FREQ_VALUE2 IN_FREQ_VALUE1 IN_FREQ_VALUE0 Bit Name Description These bits represent a 2’s complement signed integer. If the value is multiplied by the value in the FREQ_MON_FACTOR[3:0] bits (b3~0, 2EH), the frequency of an input clock with respect to the reference clock in ppm will be gotten. The IN_FREQ_VALUE[7:0] input clock is selected by the IN_FREQ_READ_CH[3:0] bits (b3~0, 41H). The value in these bits is updated every 16 seconds, starting when an input clock is selected. 7-0 IN1_IN2_STS - Input Clock 1 & 2 Status Address: 43H Type: Read Default Value: X110X110 7 6 5 4 3 2 1 0 - IN2_FREQ_HARD_ALA RM IN2_NO_ACTIVITY_ALARM IN2_PH_LOCK _ALARM - IN1_FREQ_HARD_ALA RM IN1_NO_ACTIVITY_ALARM IN1_PH_LOCK _ALARM Bit Name Description 7 - 6 IN2_FREQ_HARD_ALARM 5 IN2_NO_ACTIVITY_ALARM 4 IN2_PH_LOCK_ALARM 3 - 2 IN1_FREQ_HARD_ALARM 1 IN1_NO_ACTIVITY_ALARM 0 IN1_PH_LOCK_ALARM Reserved. This bit indicates whether IN2 is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default) This bit indicates whether IN2 is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default) This bit indicates whether IN2 is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. Reserved. This bit indicates whether IN1 is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default) This bit indicates whether IN1 is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default) This bit indicates whether IN1 is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. Programming Information 109 April 15, 2015 IDT82V3280 WAN PLL IN3_IN4_STS - Input Clock 3 & 4 Status Address: 44H Type: Read Default Value: X110X110 7 6 5 4 3 2 1 0 - IN4_FREQ_HARD_ALAR M IN4_NO_ACTIVITY_ALARM IN4_PH_LOCK_ ALARM - IN3_FREQ_HARD_ALAR M IN3_NO_ACTIVITY_ALARM IN3_PH_LOCK_ ALARM Bit Name Description 7 - 6 IN4_FREQ_HARD_ALARM 5 IN4_NO_ACTIVITY_ALARM 4 IN4_PH_LOCK_ALARM 3 - 2 IN3_FREQ_HARD_ALARM 1 IN3_NO_ACTIVITY_ALARM 0 IN3_PH_LOCK_ALARM Reserved. This bit indicates whether IN4 is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default) This bit indicates whether IN4 is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default) This bit indicates whether IN4 is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. Reserved. This bit indicates whether IN3 is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default) This bit indicates whether IN3 is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default) This bit indicates whether IN3 is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. Programming Information 110 April 15, 2015 IDT82V3280 WAN PLL IN5_IN6_STS - Input Clock 5 & 6 Status Address: 45H Type: Read Default Value: X110X110 7 6 5 4 3 2 1 0 - IN6_FREQ_HARD_ALAR M IN6_NO_ACTIVITY_ALARM IN6_PH_LOCK_ ALARM - IN5_FREQ_HARD_ALAR M IN5_NO_ACTIVITY_ALARM IN5_PH_LOCK_ ALARM Bit Name Description 7 - 6 IN6_FREQ_HARD_ALARM 5 IN6_NO_ACTIVITY_ALARM 4 IN6_PH_LOCK_ALARM 3 - 2 IN5_FREQ_HARD_ALARM 1 IN5_NO_ACTIVITY_ALARM 0 IN5_PH_LOCK_ALARM Reserved. This bit indicates whether IN6 is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default) This bit indicates whether IN6 is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default) This bit indicates whether IN6 is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. Reserved. This bit indicates whether IN5 is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default) This bit indicates whether IN5 is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default) This bit indicates whether IN5 is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. Programming Information 111 April 15, 2015 IDT82V3280 WAN PLL IN7_IN8_STS - Input Clock 7 & 8 Status Address: 46H Type: Read Default Value: X110X110 7 6 5 4 3 2 1 0 - IN8_FREQ_HARD_ALA RM IN8_NO_ACTIVITY_ALARM IN8_PH_LOCK _ALARM - IN7_FREQ_HARD_ALA RM IN7_NO_ACTIVITY_ALARM IN7_PH_LOCK _ALARM Bit Name Description 7 - 6 IN8_FREQ_HARD_ALARM 5 IN8_NO_ACTIVITY_ALARM 4 IN8_PH_LOCK_ALARM 3 - 2 IN7_FREQ_HARD_ALARM 1 IN7_NO_ACTIVITY_ALARM 0 IN7_PH_LOCK_ALARM Reserved. This bit indicates whether IN8 is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default) This bit indicates whether IN8 is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default) This bit indicates whether IN8 is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. Reserved. This bit indicates whether IN7 is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default) This bit indicates whether IN7 is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default) This bit indicates whether IN7 is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. Programming Information 112 April 15, 2015 IDT82V3280 WAN PLL IN9_IN10_STS - Input Clock 9 & 10 Status Address: 47H Type: Read Default Value: X110X110 7 6 5 4 3 2 1 0 - IN10_FREQ_HARD_ALAR M IN10_NO_ACTIVITY_ALARM IN10_PH_LOCK _ALARM - IN9_FREQ_HARD_ALAR M IN9_NO_ACTIVITY_ALARM IN9_PH_LOCK_ ALARM Bit Name Description 7 - 6 IN10_FREQ_HARD_ALARM 5 IN10_NO_ACTIVITY_ALARM 4 IN10_PH_LOCK_ALARM 3 - 2 IN9_FREQ_HARD_ALARM 1 IN9_NO_ACTIVITY_ALARM 0 IN9_PH_LOCK_ALARM Reserved. This bit indicates whether IN10 is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default) This bit indicates whether IN10 is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default) This bit indicates whether IN10 is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. Reserved. This bit indicates whether IN9 is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default) This bit indicates whether IN9 is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default) This bit indicates whether IN9 is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. Programming Information 113 April 15, 2015 IDT82V3280 WAN PLL IN11_IN12_STS - Input Clock 11 & 12 Status Address: 48H Type: Read Default Value: X110X110 7 6 5 4 3 2 1 0 - IN12_FREQ_HARD_ALA RM IN12_NO_ACTIVITY_ALARM IN12_PH_LOC K_ALARM - IN11_FREQ_HARD_ALA RM IN11_NO_ACTIVITY_ALARM IN11_PH_LOCK _ALARM Bit Name Description 7 - 6 IN12_FREQ_HARD_ALARM 5 IN12_NO_ACTIVITY_ALARM 4 IN12_PH_LOCK_ALARM 3 - 2 IN11_FREQ_HARD_ALARM 1 IN11_NO_ACTIVITY_ALARM 0 IN11_PH_LOCK_ALARM Reserved. This bit indicates whether IN12 is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default) This bit indicates whether IN12 is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default) This bit indicates whether IN12 is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. Reserved. This bit indicates whether IN11 is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default) This bit indicates whether IN11 is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default) This bit indicates whether IN11 is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. Programming Information 114 April 15, 2015 IDT82V3280 WAN PLL IN13_IN14_STS - Input Clock 13 & 14 Status Address: 49H Type: Read Default Value: X110X110 7 6 5 4 3 2 1 0 - IN14_FREQ_HARD_ALA RM IN14_NO_ACTIVITY_ALARM IN14_PH_LOC K_ALARM - IN13_FREQ_HARD_ALA RM IN13_NO_ACTIVITY_ALARM IN13_PH_LOC K_ALARM Bit Name Description 7 - 6 IN14_FREQ_HARD_ALARM 5 IN14_NO_ACTIVITY_ALARM 4 IN14_PH_LOCK_ALARM 3 - 2 IN13_FREQ_HARD_ALARM 1 IN13_NO_ACTIVITY_ALARM 0 IN13_PH_LOCK_ALARM Reserved. This bit indicates whether IN14 is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default) This bit indicates whether IN14 is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default) This bit indicates whether IN14 is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. Reserved. This bit indicates whether IN13 is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default) This bit indicates whether IN13 is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default) This bit indicates whether IN13 is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. Programming Information 115 April 15, 2015 IDT82V3280 7.2.5 WAN PLL T0 / T4 DPLL INPUT CLOCK SELECTION REGISTERS INPUT_VALID1_STS - Input Clocks Validity 1 Address: 4AH Type: Read Default Value: 00000000 7 6 5 4 3 2 1 0 IN8 IN7 IN6 IN5 IN4 IN3 IN2 IN1 Bit Name 7-0 INn Description This bit indicates the validity of the corresponding INn. Here n is any one of 8 to 1. 0: Invalid. (default) 1: Valid. INPUT_VALID2_STS - Input Clocks Validity 2 Address: 4BH Type: Read Default Value: XX000000 7 6 5 4 3 2 1 0 - - IN14 IN13 IN12 IN11 IN10 IN9 Bit Name 7-6 - 5-0 INn Description Reserved. This bit indicates the validity of the corresponding INn. Here n is any one of 14 to 9. 0: Invalid. (default) 1: Valid. REMOTE_INPUT_VALID1_CNFG - Input Clocks Validity Configuration 1 Address: 4CH Type: Read / Write Default Value: 11111111 7 6 5 4 3 2 1 0 IN8_VALID IN7_VALID IN6_VALID IN5_VALID IN4_VALID IN3_VALID IN2_VALID IN1_VALID Bit Name 7-0 INn_VALID Programming Information Description This bit controls whether the corresponding INn is allowed to be locked for automatic selection. Here n is any one of 8 to 1. 0: Enabled. 1: Disabled. (default) 116 April 15, 2015 IDT82V3280 WAN PLL REMOTE_INPUT_VALID2_CNFG - Input Clocks Validity Configuration 2 Address: 4DH Type: Read / Write Default Value: XX111111 7 6 5 4 3 2 1 0 - - IN14_VALID IN13_VALID IN12_VALID IN11_VALID IN10_VALID IN9_VALID Bit Name 7-6 - Description 5-0 INn_VALID Reserved. This bit controls whether the corresponding INn is allowed to be locked for automatic selection. Here n is any one of 14 to 9. 0: Enabled. 1: Disabled. (default) PRIORITY_TABLE1_STS - Priority Status 1 * Address: 4EH Type: Read Default Value: 00000000 7 6 5 4 3 2 1 0 HIGHEST_PRIORITY_VALIDATED3 HIGHEST_PRIORITY_VALIDATED2 HIGHEST_PRIORITY_VALIDATED1 HIGHEST_PRIORITY_VALIDATED0 CURRENTLY_SELECTED_INPUT3 CURRENTLY_SELECTED_INPUT2 CURRENTLY_SELECTED_INPUT1 CURRENTLY_SELECTED_INPUT0 Bit 7-4 3-0 Name Description These bits indicate a qualified input clock with the highest priority. 0000: No input clock is qualified. (default) 0001: IN1. 0010: IN2. ...... HIGHEST_PRIORITY_VALIDATED[3:0] 1101: IN13. 1110: IN14. 1111: Reserved. Note that the input clock is indicated by these bits only when the corresponding INn (b7-0, 4CH) or INn (b5-0, 4DH) bit is ‘0’. These bits indicate the T0/T4 selected input clock. 0000: No input clock is selected; or the T4 selected input clock is the T0 DPLL output. (default) 0001: IN1 is selected. 0010: IN2 is selected. ...... CURRENTLY_SELECTED_INPUT[3:0] 1101: IN13 is selected. 1110: IN14 is selected. 1111: Reserved. Note that the input clock is indicated by these bits only when the corresponding INn (b7-0, 4CH) or INn (b5-0, 4DH) bit is ‘0’. Programming Information 117 April 15, 2015 IDT82V3280 WAN PLL PRIORITY_TABLE2_STS - Priority Status 2 * Address: 4FH Type: Read Default Value: 00000000 7 6 5 4 3 2 1 0 THIRD_HIGHEST_PRIORITY_VALIDATED 3 THIRD_HIGHEST_PRIORITY_VALIDATED 2 THIRD_HIGHEST_PRIORITY_VALIDATED 1 THIRD_HIGHEST_PRIORITY_VALIDATED 0 SECOND_HIGHEST_PRIORITY _VALIDATED3 SECOND_HIGHEST_PRIORITY _VALIDATED2 SECOND_HIGHEST_PRIORITY _VALIDATED1 SECOND_HIGHEST_PRIORITY _VALIDATED0 Bit Name Description These bits indicate a qualified input clock with the third highest priority. 0000: No input clock is qualified. (default) 0001: IN1. 0010: IN2. ...... THIRD_HIGHEST_PRIORITY_VALIDATED[3:0] 1101: IN13. 1110: IN14. 1111: Reserved. Note that the input clock is indicated by these bits only when the corresponding INn (b7-0, 4CH) or INn (b5-0, 4DH) bit is ‘0’. These bits indicate a qualified input clock with the second highest priority. 0000: No input clock is qualified. (default) 0001: IN1. 0010: IN2. ...... SECOND_HIGHEST_PRIORITY_VALIDATED[3:0] 1101: IN13. 1110: IN14. 1111: Reserved. Note that the input clock is indicated by these bits only when the corresponding INn (b7-0, 4CH) or INn (b5-0, 4DH) bit is ‘0’. 7-4 3-0 T0_INPUT_SEL_CNFG - T0 Selected Input Clock Configuration Address: 50H Type: Read / Write Default Value: XXXX0000 7 6 5 4 3 2 1 0 - - - - T0_INPUT_SEL3 T0_INPUT_SEL2 T0_INPUT_SEL1 T0_INPUT_SEL0 Bit Name 7-4 - 3-0 Description Reserved. This bit determines T0 input clock selection. It is valid only when the EXT_SW bit (b4, 0BH) is ‘0’. 0000: Automatic selection. (default) 0001: Forced selection - IN1 is selected. 0010: Forced selection - IN2 is selected. T0_INPUT_SEL[3:0] ...... 1101: Forced selection - IN13 is selected. 1110: Forced selection - IN14 is selected. 1111: Reserved. Programming Information 118 April 15, 2015 IDT82V3280 WAN PLL T4_INPUT_SEL_CNFG - T4 Selected Input Clock Configuration Address: 51H Type: Read / Write Default Value: X0000000 7 6 5 4 3 2 1 0 - T4_LOCK_T0 T0_FOR_T4 T4_TEST_T0_PH T4_INPUT_SEL3 T4_INPUT_SEL2 T4_INPUT_SEL1 T4_INPUT_SEL0 Bit Name 7 - 6 5 4 3-0 Description Reserved. This bit determines whether the T4 DPLL locks to a T0 DPLL output or locks independently from the T0 DPLL. T4_LOCK_T0 0: Independently from the T0 path. (default) 1: Locks to a 77.76 MHz or 8 kHz signal from the T0 DPLL 77.76 MHz path. This bit is valid only when the T4_LOCK_T0 bit (b6, 51H) is ‘1’. It determines whether a 77.76 MHz or 8 kHz signal from the T0 DPLL 77.76 MHz path is selected by the T4 DPLL. T0_FOR_T4 0: 77.76 MHz. (default) 1: 8 kHz. This bit determines whether T4 selected input clock is compared with the feedback signal of the T4 DPLL for T4 DPLL locking or is compared with the T0 selected input clock to get the phase difference between T0 and T4 selected input clocks. T4_TEST_T0_PH 0: The T4 DPLL output. (default) 1: The T0 selected input clock. These bits are valid only when the T4_LOCK_T0 bit (b6, 51H) is ‘0’. They determines the T4 DPLL input clock selection. 0000: Automatic selection. (default) 0001: Forced selection - IN1 is selected. 0010: Forced selection - IN2 is selected. T4_INPUT_SEL[3:0] ...... 1101: Forced selection - IN13 is selected. 1110: Forced selection - IN14 is selected. 1111: Reserved. Programming Information 119 April 15, 2015 IDT82V3280 7.2.6 WAN PLL T0 / T4 DPLL STATE MACHINE CONTROL REGISTERS OPERATING_STS - DPLL Operating Status Address: 52H Type: Read Default Value: 10000001 7 6 5 4 3 2 1 0 EX_SYNC_ALARM_MO N T4_DPLL_LOCK T0_DPLL_SOFT_FREQ_ALARM T4_DPLL_SOFT_FREQ_ALARM T0_DPLL_LOCK T0_DPLL_OPERATING_MODE2 T0_DPLL_OPERATING_MODE1 T0_DPLL_OPERATING_MODE0 Bit 7 6 5 4 3 2-0 Name Description This bit indicates whether the frame sync input signal is in external sync alarm status. 0: No external sync alarm. 1: In external sync alarm status. (default) This bit indicates the T4 DPLL locking status. T4_DPLL_LOCK 0: Unlocked. (default) 1: Locked. This bit indicates whether the T0 DPLL is in soft alarm status. T0_DPLL_SOFT_FREQ_ALARM 0: No T0 DPLL soft alarm. (default) 1: In T0 DPLL soft alarm status. This bit indicates whether the T4 DPLL is in soft alarm status. T4_DPLL_SOFT_FREQ_ALARM 0: No T4 DPLL soft alarm. (default) 1: In T4 DPLL soft alarm status. This bit indicates the T0 DPLL locking status. T0_DPLL_LOCK 0: Unlocked. (default) 1: Locked. These bits indicate the current operating mode of T0 DPLL. 000: Reserved. 001: Free-Run. (default) 010: Holdover. T0_DPLL_OPERATING_MODE[2:0] 011: Reserved. 100: Locked. 101: Pre-Locked2. 110: Pre-Locked. 111: Lost-Phase. EX_SYNC_ALARM_MON Programming Information 120 April 15, 2015 IDT82V3280 WAN PLL T0_OPERATING_MODE_CNFG - T0 DPLL Operating Mode Configuration Address: 53H Type: Read / Write Default Value: XXXXX000 7 6 5 4 3 2 1 0 - - - - - T0_OPERATING_MODE2 T0_OPERATING_MODE1 T0_OPERATING_MODE0 Bit Name 7-3 - 2-0 Description Reserved. These bits control the T0 DPLL operating mode. 000: Automatic. (default) 001: Forced - Free-Run. 010: Forced - Holdover. T0_OPERATING_MODE[2:0] 011: Reserved. 100: Forced - Locked. 101: Forced - Pre-Locked2. 110: Forced - Pre-Locked. 111: Forced - Lost-Phase. T4_OPERATING_MODE_CNFG - T4 DPLL Operating Mode Configuration Address: 54H Type: Read / Write Default Value: XXXXX000 7 6 5 4 3 2 1 0 - - - - - T4_OPERATING_MODE2 T4_OPERATING_MODE1 T4_OPERATING_MODE0 Bit Name 7-3 - 2-0 Description Reserved. These bits control the T4 DPLL operating mode. 000: Automatic. (default) 001: Forced - Free-Run. T4_OPERATING_MODE[2:0] 010: Forced - Holdover. 011: Reserved. 100: Forced - Locked. 101, 110, 111: Reserved. Programming Information 121 April 15, 2015 IDT82V3280 7.2.7 WAN PLL T0 / T4 DPLL & APLL CONFIGURATION REGISTERS T0_DPLL_APLL_PATH_CNFG - T0 DPLL & APLL Path Configuration Address: 55H Type: Read / Write Default Value: 00000X0X 7 6 5 4 3 2 1 0 T0_APLL_PATH3 T0_APLL_PATH2 T0_APLL_PATH1 T0_APLL_PATH0 T0_GSM_OBSAI_16E1_16T1_SEL1 T0_GSM_OBSAI_16E1_16T1_SEL0 T0_12E1_24T1_ E3_T3_SEL1 T0_12E1_24T1_ E3_T3_SEL0 Bit 7-4 3-2 1-0 Name Description These bits select an input to the T0 APLL. 0000: The output of T0 DPLL 77.76 MHz path. (default) 0001: The output of T0 DPLL 12E1/24T1/E3/T3 path. 0010: The output of T0 DPLL 16E1/16T1 path. 0011: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path. T0_APLL_PATH[3:0] 0100: The output of T4 DPLL 77.76 MHz path. 0101: The output of T4 DPLL 12E1/24T1/E3/T3 path. 0110: The output of T4 DPLL 16E1/16T1 path. 0111: The output of T4 DPLL GSM/GPS/16E1/16T1 path. 1XXX: Reserved. These bits select an output clock from the T0 DPLL GSM/OBSAI/16E1/16T1 path. 00: 16E1. 01: 16T1. T0_GSM_OBSAI_16E1_16T1_SEL[1:0] 10: GSM. 11: OBSAI. The default value of the T0_GSM_OBSAI_16E1_16T1_SEL0 bit is determined by the SONET/SDH pin during reset. These bits select an output clock from the T0 DPLL 12E1/24T1/E3/T3 path. 00: 12E1. 01: 24T1. T0_12E1_24T1_E3_T3_SEL[1:0] 10: E3. 11: T3. The default value of the T0_12E1_24T1_E3_T3_SEL0 bit is determined by the SONET/SDH pin during reset. Programming Information 122 April 15, 2015 IDT82V3280 WAN PLL T0_DPLL_START_BW_DAMPING_CNFG - T0 DPLL Start Bandwidth & Damping Factor Configuration Address: 56H Type: Read / Write Default Value: 01101111 7 6 5 4 3 2 1 0 T0_DPLL_START_D AMPING2 T0_DPLL_START_D AMPING1 T0_DPLL_START_D AMPING0 T0_DPLL_START_B W4 T0_DPLL_START_B W3 T0_DPLL_START_B W2 T0_DPLL_START_B W1 T0_DPLL_START_B W0 Bit 7-5 4-0 Name Description These bits set the starting damping factor for T0 DPLL. 000: Reserved. 001: 1.2. 010: 2.5. T0_DPLL_START_DAMPING[2:0] 011: 5. (default) 100: 10. 101: 20. 110, 111: Reserved. These bits set the starting bandwidth for T0 DPLL. 00000: 0.5 mHz. 00001: 1 mHz. 00010: 2 mHz. 00011: 4 mHz. 00100: 8 mHz. 00101: 15 mHz. 00110: 30 mHz. 00111: 60 mHz. 01000: 0.1 Hz. 01001: 0.3 Hz. T0_DPLL_START_BW[4:0] 01010: 0.6 Hz. 01011: 1.2 Hz. 01100: 2.5 Hz. 01101: 4 Hz. 01110: 8 Hz. 01111: 18 Hz. (default) 10000: 35 Hz. 10001: 70 Hz. 10010: 560 Hz. 10011 ~ 11111: Reserved. Programming Information 123 April 15, 2015 IDT82V3280 WAN PLL T0_DPLL_ACQ_BW_DAMPING_CNFG - T0 DPLL Acquisition Bandwidth & Damping Factor Configuration Address: 57H Type: Read / Write Default Value: 01101111 7 6 5 4 3 2 1 0 T0_DPLL_ACQ_DAMPING2 T0_DPLL_ACQ_DAMPING1 T0_DPLL_ACQ_DAMPING0 T0_DPLL_ACQ_BW4 T0_DPLL_ACQ_BW3 T0_DPLL_ACQ_BW2 T0_DPLL_ACQ_BW1 T0_DPLL_ACQ_BW0 Bit 7-5 4-0 Name Description These bits set the acquisition damping factor for T0 DPLL. 000: Reserved. 001: 1.2. 010: 2.5. T0_DPLL_ACQ_DAMPING[2:0] 011: 5. (default) 100: 10. 101: 20. 110, 111: Reserved. These bits set the acquisition bandwidth for T0 DPLL. 00000: 0.5 mHz. 00001: 1 mHz. 00010: 2 mHz. 00011: 4 mHz. 00100: 8 mHz. 00101: 15 mHz. 00110: 30 mHz. 00111: 60 mHz. 01000: 0.1 Hz. 01001: 0.3 Hz. T0_DPLL_ACQ_BW[4:0] 01010: 0.6 Hz. 01011: 1.2 Hz. 01100: 2.5 Hz. 01101: 4 Hz. 01110: 8 Hz. 01111: 18 Hz. (default) 10000: 35 Hz. 10001: 70 Hz. 10010: 560 Hz. 10011 ~ 11111: Reserved. Programming Information 124 April 15, 2015 IDT82V3280 WAN PLL T0_DPLL_LOCKED_BW_DAMPING_CNFG - T0 DPLL Locked Bandwidth & Damping Factor Configuration Address: 58H Type: Read / Write Default Value: 01101011 7 6 5 4 3 2 1 0 T0_DPLL_LOCKED_ DAMPING2 T0_DPLL_LOCKED_ DAMPING1 T0_DPLL_LOCKED_ DAMPING0 T0_DPLL_LOCKED_ BW4 T0_DPLL_LOCKED_ BW3 T0_DPLL_LOCKED_ BW2 T0_DPLL_LOCKED_ BW1 T0_DPLL_LOCKED_ BW0 Bit 7-5 4-0 Name Description These bits set the locked damping factor for T0 DPLL. 000: Reserved. 001: 1.2. 010: 2.5. T0_DPLL_LOCKED_DAMPING[2:0] 011: 5. (default) 100: 10. 101: 20. 110, 111: Reserved. These bits set the locked bandwidth for T0 DPLL. 00000: 0.5 mHz. 00001: 1 mHz. 00010: 2 mHz. 00011: 4 mHz. 00100: 8 mHz. 00101: 15 mHz. 00110: 30 mHz. 00111: 60 mHz. 01000: 0.1 Hz. 01001: 0.3 Hz. T0_DPLL_LOCKED_BW[4:0] 01010: 0.6 Hz. 01011: 1.2 Hz. (default) 01100: 2.5 Hz. 01101: 4 Hz. 01110: 8 Hz. 01111: 18 Hz. 10000: 35 Hz. 10001: 70 Hz. 10010: 560 Hz. 10011 ~ 11111: Reserved. Programming Information 125 April 15, 2015 IDT82V3280 WAN PLL T0_BW_OVERSHOOT_CNFG - T0 DPLL Bandwidth Overshoot Configuration Address: 59H Type: Read / Write Default Value: 1XXX1XXX 7 6 5 4 3 2 1 0 AUTO_BW_SEL - - - T0_LIMT - - - Bit 7 6-4 3 2-0 Name Description This bit determines whether starting or acquisition bandwidth / damping factor is used for T0 DPLL. 0: The starting and acquisition bandwidths / damping factors are not used. Only the locked bandwidth / damping factor is used AUTO_BW_SEL regardless of the T0 DPLL locking stage. 1: The starting, acquisition or locked bandwidth / damping factor is used automatically depending on different T0 DPLL locking stages. (default) Reserved. This bit determines whether the integral path value is frozen when the T0 DPLL hard limit is reached. T0_LIMT 0: Not frozen. 1: Frozen. It will minimize the subsequent overshoot when T0 DPLL is pulling in. (default) Reserved. Programming Information 126 April 15, 2015 IDT82V3280 WAN PLL PHASE_LOSS_COARSE_LIMIT_CNFG - Phase Loss Coarse Detector Limit Configuration * Address: 5AH Type: Read / Write Default Value: 10000101 7 6 5 4 3 2 1 0 COARSE_PH_L OS_LIMT_EN WIDE_EN MULTI_PH_APP MULTI_PH_8K_4K_ 2K_EN PH_LOS_COARSE_LIMT 3 PH_LOS_COARSE_LIMT 2 PH_LOS_COARSE_LIMT 1 PH_LOS_COARSE_LIMT 0 Bit 7 6 5 Name Description This bit controls whether the occurrence of the coarse phase loss will result in the T0/T4 DPLL unlocked. COARSE_PH_LOS_LIMT_EN 0: Disabled. 1: Enabled. (default) WIDE_EN Refer to the description of the MULTI_PH_8K_4K_2K_EN bit (b4, 5AH). This bit determines whether the PFD output of T0/T4 DPLL is limited to ±1 UI or is limited to the coarse phase limit. 0: Limited to ±1 UI. (default) 1: Limited to the coarse phase limit. When the selected input clock is of 2 kHz, 4 kHz or 8 kHz, the coarse phase limit depends MULTI_PH_APP on the MULTI_PH_8K_4K_2K_EN bit, the WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits; when the selected input clock is of other frequencies but 2 kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to the description of the MULTI_PH_8K_4K_2K_EN bit (b4, 5AH) for details. This bit, together with the WIDE_EN bit (b6, 5AH) and the PH_LOS_COARSE_LIMT[3:0] bits (b3~0, 5AH), determines the coarse phase limit when the selected input clock is of 2 kHz, 4 kHz or 8 kHz. When the selected input clock is of other frequencies but 2 kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits. Selected Input Clock MULTI_PH_8K_4K_2K_EN WIDE_EN 4 0 MULTI_PH_8K_4K_2K_EN 2 kHz, 4 kHz or 8 kHz other than 2 kHz, 4 kHz and 8 kHz 1 don’t-care 0 1 0 don’t-care 1 Coarse Phase Limit ±1 UI ±1 UI set by the PH_LOS_COARSE_LIMT[3:0] bits (b3~0, 5AH). ±1 UI set by the PH_LOS_COARSE_LIMT[3:0] bits (b3~0, 5AH). These bit set the coarse phase limit. The limit is used only in some cases. Refer to the description of the MULTI_PH_8K_4K_2K_EN bit (b4, 5AH). 0000: ±1 UI. 0001: ±3 UI. 0010: ±7 UI. 0011: ±15 UI. 3 - 0 PH_LOS_COARSE_LIMT[3:0] 0100: ±31 UI. 0101: ±63 UI. (default) 0110: ±127 UI. 0111: ±255 UI. 1000: ±511 UI. 1001: ±1023 UI (T0); Reserved (T4). 1010-1111: Reserved. Programming Information 127 April 15, 2015 IDT82V3280 WAN PLL PHASE_LOSS_FINE_LIMIT_CNFG - Phase Loss Fine Detector Limit Configuration * Address: 5BH Type: Read / Write Default Value: 10XXX010 7 6 5 4 3 2 1 0 FINE_PH_LOS_ LIMT_EN FAST_LOS_SW - - - PH_LOS_FINE _LIMT2 PH_LOS_FINE _LIMT1 PH_LOS_FINE _LIMT0 Bit 7 6 5-3 2-0 Name Description This bit controls whether the occurrence of the fine phase loss will result in the T0/T4 DPLL unlocked. FINE_PH_LOS_LIMT_EN 0: Disabled. 1: Enabled. (default) The value in this bit can be switched only when it is available for T0 path; this bit is always ‘1’ when it is available for T4 path. This bit controls whether the occurrence of the fast loss will result in the T0/T4 DPLL unlocked. FAST_LOS_SW 0: Does not result in the T0 DPLL unlocked. T0 DPLL will enter Temp-Holdover mode automatically. (default) 1: Results in the T0/T4 DPLL unlocked. For T0 path, T0 DPLL will enter Lost-Phase mode if the T0 DPLL operating mode is switched automatically. Reserved. These bits set a fine phase limit. 000: 0. 001: ± (45 ° ~ 90 °). 010: ± (90 ° ~ 180 °). (default) PH_LOS_FINE_LIMT[2:0] 011: ± (180 ° ~ 360 °). 100: ± (20 ns ~ 25 ns). 101: ± (60 ns ~ 65 ns). 110: ± (120 ns ~ 125 ns). 111: ± (950 ns ~ 955 ns). Programming Information 128 April 15, 2015 IDT82V3280 WAN PLL T0_HOLDOVER_MODE_CNFG - T0 DPLL Holdover Mode Configuration Address: 5CH Type: Read / Write Default Value: 010001XX 7 6 5 4 3 2 1 0 MAN_HOLDOVER AUTO_AVG FAST_AVG READ_AVG TEMP_HOLDOVER_MODE1 TEMP_HOLDOVER_MODE0 - - Bit Name Description 7 6 MAN_HOLDOVER AUTO_AVG Refer to the description of the FAST_AVG bit (b5, 5CH). Refer to the description of the FAST_AVG bit (b5, 5CH). This bit, together with the AUTO_AVG bit (b6, 5CH) and the MAN_HOLDOVER bit (b7, 5CH), determines a frequency offset acquiring method in T0 DPLL Holdover Mode. MAN_HOLDOVER 5 AUTO_AVG FAST_AVG Frequency Offset Acquiring Method 0 don’t-care 0 1 Automatic Instantaneous Automatic Slow Averaged (default) Automatic Fast Averaged Manual FAST_AVG 0 1 1 don’t-care This bit controls the holdover frequency offset reading, which is read from the T0_HOLDOVER_FREQ[23:0] bits (5FH ~ 5DH). 0: The value read from the T0_HOLDOVER_FREQ[23:0] bits (5FH ~ 5DH) is equal to the one written to them. READ_AVG (default) 1: The value read from the T0_HOLDOVER_FREQ[23:0] bits (5FH ~ 5DH) is not equal to the one written to them. The value is acquired by Automatic Slow Averaged method if the FAST_AVG bit (b5, 5CH) is ‘0’; or is acquired by Automatic Fast Averaged method if the FAST_AVG bit (b5, 5CH) is ‘1’. These bits determine the frequency offset acquiring method in T0 DPLL Temp-Holdover Mode. 00: The method is the same as that used in T0 DPLL Holdover mode. TEMP_HOLDOVER_MODE[1:0] 01: Automatic Instantaneous. (default) 10: Automatic Fast Averaged. 11: Automatic Slow Averaged. Reserved. 4 3-2 1-0 T0_HOLDOVER_FREQ[7:0]_CNFG - T0 DPLL Holdover Frequency Configuration 1 Address: 5DH Type: Read / Write Default Value: 00000000 7 6 5 4 3 2 1 0 T0_HOLDOVER_FREQ7 T0_HOLDOVER_FREQ6 T0_HOLDOVER_FREQ5 T0_HOLDOVER_FREQ4 T0_HOLDOVER_FREQ3 T0_HOLDOVER_FREQ2 T0_HOLDOVER_FREQ1 T0_HOLDOVER_FREQ0 Bit 7-0 Name Description T0_HOLDOVER_FREQ[7:0] Refer to the description of the T0_HOLDOVER_FREQ[23:16] bits (b7~0, 5FH). Programming Information 129 April 15, 2015 IDT82V3280 WAN PLL T0_HOLDOVER_FREQ[15:8]_CNFG - T0 DPLL Holdover Frequency Configuration 2 Address: 5EH Type: Read / Write Default Value: 00000000 7 6 5 4 3 2 1 0 T0_HOLDOVER_FREQ15 T0_HOLDOVER_FREQ14 T0_HOLDOVER_FREQ13 T0_HOLDOVER_FREQ12 T0_HOLDOVER_FREQ11 T0_HOLDOVER_FREQ10 T0_HOLDOVER_FREQ9 T0_HOLDOVER_FREQ8 Bit Name 7-0 Description T0_HOLDOVER_FREQ[15:8] Refer to the description of the T0_HOLDOVER_FREQ[23:16] bits (b7~0, 5FH). T0_HOLDOVER_FREQ[23:16]_CNFG - T0 DPLL Holdover Frequency Configuration 3 Address: 5FH Type: Read / Write Default Value: 00000000 7 6 5 4 3 2 1 0 T0_HOLDOVER_FREQ23 T0_HOLDOVER_FREQ22 T0_HOLDOVER_FREQ21 T0_HOLDOVER_FREQ20 T0_HOLDOVER_FREQ19 T0_HOLDOVER_FREQ18 T0_HOLDOVER_FREQ17 T0_HOLDOVER_FREQ16 Bit 7-0 Name Description The T0_HOLDOVER_FREQ[23:0] bits represent a 2’s complement signed integer. In T0 DPLL Holdover mode, the value written to these bits multiplied by 0.000011 is the frequency offset set manuT0_HOLDOVER_FREQ[23:16] ally; the value read from these bits multiplied by 0.000011 is the frequency offset automatically slow or fast averaged or manually set, as determined by the READ_AVG bit (b4, 5CH) and the FAST_AVG bit (b5, 5CH). Programming Information 130 April 15, 2015 IDT82V3280 WAN PLL T4_DPLL_APLL_PATH_CNFG - T4 DPLL & APLL Path Configuration Address: 60H Type: Read / Write Default Value: 01000X0X 7 6 5 4 3 2 1 0 T4_APLL_PATH3 T4_APLL_PATH2 T4_APLL_PATH1 T4_APLL_PATH0 T4_GSM_GPS_16E1_16T1_SEL1 T4_GSM_GPS_16E1_16T1_SEL0 T4_12E1_24T1_ E3_T3_SEL1 T4_12E1_24T1_ E3_T3_SEL0 Bit 7-4 3-2 1-0 Name Description These bits select an input to the T4 APLL. 0000: The output of T0 DPLL 77.76 MHz path. 0001: The output of T0 DPLL 12E1/24T1/E3/T3 path. 0010: The output of T0 DPLL 16E1/16T1 path. 0011: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path. T4_APLL_PATH[3:0] 0100: The output of T4 DPLL 77.76 MHz path. (default) 0101: The output of T4 DPLL 12E1/24T1/E3/T3 path. 0110: The output of T4 DPLL 16E1/16T1 path. 0111: The output of T4 DPLL GSM/GPS/16E1/16T1 path. 1XXX: Reserved. These bits select an output clock from the T4 DPLL GSM/GPS/16E1/16T1 path. 00: 16E1. 01: 16T1. T4_GSM_GPS_16E1_16T1_SEL[1:0] 10: GSM. 11: GPS. The default value of the T0_GSM_GPS_16E1_16T1_SEL0 bit is determined by the SONET/SDH pin during reset. These bits select an output clock from the T4 DPLL 12E1/24T1/E3/T3 path. 00: 12E1. 01: 24T1. T4_12E1_24T1_E3_T3_SEL[1:0] 10: E3. 11: T3. The default value of the T4_12E1_24T1_E3_T3_SEL0 bit is determined by the SONET/SDH pin during reset. Programming Information 131 April 15, 2015 IDT82V3280 WAN PLL T4_DPLL_LOCKED_BW_DAMPING_CNFG - T4 DPLL Locked Bandwidth & Damping Factor Configuration Address: 61H Type: Read / Write Default Value: 011XXX00 7 6 5 4 3 2 1 0 T4_DPLL_LOCKED_ DAMPING2 T4_DPLL_LOCKED_ DAMPING1 T4_DPLL_LOCKED_ DAMPING0 - - - T4_DPLL_LOCKED_ BW1 T4_DPLL_LOCKED_ BW0 Bit Name 7-5 4-2 1-0 Description These bits set the locked damping factor for T4 DPLL. 000: Reserved. 001: 1.2. 010: 2.5. T4_DPLL_LOCKED_DAMPING[2:0] 011: 5. (default) 100: 10. 101: 20. 110, 111: Reserved. Reserved. These bits set the locked bandwidth for T4 DPLL. 00: 18 Hz. (default) T4_DPLL_LOCKED_BW[1:0] 01: 35 Hz. 10: 70 Hz. 11: 560 Hz. CURRENT_DPLL_FREQ[7:0]_STS - DPLL Current Frequency Status 1 * Address: 62H Type: Read Default Value: 00000000 7 6 5 4 3 2 1 0 CURRENT_DPLL_FREQ7 CURRENT_DPLL_FREQ6 CURRENT_DPLL_FREQ5 CURRENT_DPLL_FREQ4 CURRENT_DPLL_FREQ3 CURRENT_DPLL_FREQ2 CURRENT_DPLL_FREQ1 CURRENT_DPLL_FREQ0 Bit Name 7-0 Description CURRENT_DPLL_FREQ[7:0] Refer to the description of the CURRENT_DPLL_FREQ[23:16] bits (b7~0, 64H). CURRENT_DPLL_FREQ[15:8]_STS - DPLL Current Frequency Status 2 * Address: 63H Type: Read Default Value: 00000000 7 6 5 4 3 2 1 0 CURRENT_DPLL_FREQ15 CURRENT_DPLL_FREQ14 CURRENT_DPLL_FREQ13 CURRENT_DPLL_FREQ12 CURRENT_DPLL_FREQ11 CURRENT_DPLL_FREQ10 CURRENT_DPLL_FREQ9 CURRENT_DPLL_FREQ8 Bit 7-0 Name Description CURRENT_DPLL_FREQ[15:8] Refer to the description of the CURRENT_DPLL_FREQ[23:16] bits (b7~0, 64H). Programming Information 132 April 15, 2015 IDT82V3280 WAN PLL CURRENT_DPLL_FREQ[23:16]_STS - DPLL Current Frequency Status 3 * Address: 64H Type: Read Default Value: 00000000 7 6 5 4 3 2 1 0 CURRENT_DPLL_FREQ23 CURRENT_DPLL_FREQ22 CURRENT_DPLL_FREQ21 CURRENT_DPLL_FREQ20 CURRENT_DPLL_FREQ19 CURRENT_DPLL_FREQ18 CURRENT_DPLL_FREQ17 CURRENT_DPLL_FREQ16 Bit Name Description The CURRENT_DPLL_FREQ[23:0] bits represent a 2’s complement signed integer. If the value in these bits is mulCURRENT_DPLL_FREQ[23:16] tiplied by 0.000011, the current frequency offset of the T0/T4 DPLL output in ppm with respect to the master clock will be gotten. 7-0 DPLL_FREQ_SOFT_LIMIT_CNFG - DPLL Soft Limit Configuration Address: 65H Type: Read / Write Default Value: 10001100 7 6 5 4 3 2 1 0 FREQ_LIMT_PH_LO S DPLL_FREQ_SOFT_LIMT6 DPLL_FREQ_SOFT_LIMT5 DPLL_FREQ_SOFT_LIMT4 DPLL_FREQ_SOFT_LIMT3 DPLL_FREQ_SOFT_LIMT2 DPLL_FREQ_SOFT_LIMT1 DPLL_FREQ_SOFT_LIMT0 Bit Name Description This bit determines whether the T0/T4 DPLL in hard alarm status will result in it unlocked. 0: Disabled. 1: Enabled. (default) These bits represent an unsigned integer. If the value is multiplied by 0.724, the DPLL soft limit for T0 and T4 paths in DPLL_FREQ_SOFT_LIMT[6:0] ppm will be gotten. The DPLL soft limit is symmetrical about zero. 7 FREQ_LIMT_PH_LOS 6-0 DPLL_FREQ_HARD_LIMIT[7:0]_CNFG - DPLL Hard Limit Configuration 1 Address: 66H Type: Read / Write Default Value: 10101011 7 6 5 4 3 2 1 0 DPLL_FREQ_HARD_LIMT 7 DPLL_FREQ_HARD_LIMT 6 DPLL_FREQ_HARD_LIMT 5 DPLL_FREQ_HARD_LIMT 4 DPLL_FREQ_HARD_LIMT 3 DPLL_FREQ_HARD_LIMT 2 DPLL_FREQ_HARD_LIMT 1 DPLL_FREQ_HARD_LIMT 0 Bit 7-0 Name Description DPLL_FREQ_HARD_LIMT[7:0] Refer to the description of the DPLL_FREQ_HARD_LIMT[15:8] bits (b7~0, 67H). Programming Information 133 April 15, 2015 IDT82V3280 WAN PLL DPLL_FREQ_HARD_LIMIT[15:8]_CNFG - DPLL Hard Limit Configuration 2 Address: 67H Type: Read / Write Default Value: 00011001 7 6 5 4 3 2 1 0 DPLL_FREQ_HARD_LIMT 15 DPLL_FREQ_HARD_LIMT 14 DPLL_FREQ_HARD_LIMT 13 DPLL_FREQ_HARD_LIMT 12 DPLL_FREQ_HARD_LIMT 11 DPLL_FREQ_HARD_LIMT 10 DPLL_FREQ_HARD_LIMT 9 DPLL_FREQ_HARD_LIMT 8 Bit Name 7-0 Description The DPLL_FREQ_HARD_LIMT[15:0] bits represent an unsigned integer. If the value is multiplied by 0.0014, the DPLL_FREQ_HARD_LIMT[15:8] DPLL hard limit for T0 and T4 paths in ppm will be gotten. The DPLL hard limit is symmetrical about zero. CURRENT_DPLL_PHASE[7:0]_STS - DPLL Current Phase Status 1 * Address: 68H Type: Read Default Value: 00000000 7 6 5 4 3 2 1 0 CURRENT_PH_DATA7 CURRENT_PH_DATA6 CURRENT_PH_DATA5 CURRENT_PH_DATA4 CURRENT_PH_DATA3 CURRENT_PH_DATA2 CURRENT_PH_DATA1 CURRENT_PH_DATA0 Bit Name 7-0 Description CURRENT_PH_DATA[7:0] Refer to the description of the CURRENT_PH_DATA[15:8] bits (b7~0, 69H). CURRENT_DPLL_PHASE[15:8]_STS - DPLL Current Phase Status 2 * Address: 69H Type: Read Default Value: 00000000 7 6 5 4 3 2 1 0 CURRENT_PH_DATA15 CURRENT_PH_DATA14 CURRENT_PH_DATA13 CURRENT_PH_DATA12 CURRENT_PH_DATA11 CURRENT_PH_DATA10 CURRENT_PH_DATA9 CURRENT_PH_DATA8 Bit 7-0 Name Description The CURRENT_PH_DATA[15:0] bits represent a 2’s complement signed integer. If the value is multiplied by 0.61, the CURRENT_PH_DATA[15:8] averaged phase error of the T0/T4 DPLL feedback with respect to the selected input clock in ns will be gotten. Programming Information 134 April 15, 2015 IDT82V3280 WAN PLL T0_T4_APLL_BW_CNFG - T0 / T4 APLL Bandwidth Configuration Address: 6AH Type: Read / Write Default Value: XX01XX01 7 6 5 4 3 2 1 0 - - T0_APLL_BW1 T0_APLL_BW0 - - T4_APLL_BW1 T4_APLL_BW0 Bit Name 7-6 - 5-4 3-2 1-0 Description Reserved. These bits set the bandwidth for T0 APLL. 00: 100 kHz. T0_APLL_BW[1:0] 01: 500 kHz. (default) 10: 1 MHz. 11: 2 MHz. Reserved. These bits set the bandwidth for T4 APLL. 00: 100 kHz. T4_APLL_BW[1:0] 01: 500 kHz. (default) 10: 1 MHz. 11: 2 MHz. Programming Information 135 April 15, 2015 IDT82V3280 7.2.8 WAN PLL OUTPUT CONFIGURATION REGISTERS OUT1_FREQ_CNFG - Output Clock 1 Frequency Configuration Address: 6BH Type: Read / Write Default Value: 00001011 7 6 5 4 3 2 1 0 OUT1_PATH_SEL3 OUT1_PATH_SEL2 OUT1_PATH_SEL1 OUT1_PATH_SEL0 OUT1_DIVIDER3 OUT1_DIVIDER2 OUT1_DIVIDER1 OUT1_DIVIDER0 Bit 7-4 3-0 Name Description These bits select an input to OUT1. 0000 ~ 0011: The output of T0 APLL. (default: 0000) 0100: The output of T0 DPLL 77.76 MHz path. 0101: The output of T0 DPLL 12E1/24T1/E3/T3 path. 0110: The output of T0 DPLL 16E1/16T1 path. OUT1_PATH_SEL[3:0] 0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path. 1000 ~ 1011: The output of T4 APLL. 1100: The output of T4 DPLL 77.76 MHz path. 1101: The output of T4 DPLL 12E1/24T1/E3/T3 path. 1110: The output of T4 DPLL 16E1/16T1 path. 1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path. These bits select a division factor of the divider for OUT1. The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output OUT1_DIVIDER[3:0] (selected by the OUT1_PATH_SEL[3:0] bits (b7~4, 6BH)). If the signal is derived from one of the T0/T4 DPLL outputs, please refer to Table 24 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to Table 25 for the division factor selection. Programming Information 136 April 15, 2015 IDT82V3280 WAN PLL OUT2_FREQ_CNFG - Output Clock 2 Frequency Configuration Address: 6CH Type: Read / Write Default Value: 00000110 7 6 5 4 3 2 1 0 OUT2_PATH_SEL3 OUT2_PATH_SEL2 OUT2_PATH_SEL1 OUT2_PATH_SEL0 OUT2_DIVIDER3 OUT2_DIVIDER2 OUT2_DIVIDER1 OUT2_DIVIDER0 Bit Name 7-4 OUT2_PATH_SEL[3:0] 3-0 OUT2_DIVIDER[3:0] Programming Information Description These bits select an input to OUT2. 0000 ~ 0011: The output of T0 APLL. (default: 0000) 0100: The output of T0 DPLL 77.76 MHz path. 0101: The output of T0 DPLL 12E1/24T1/E3/T3 path. 0110: The output of T0 DPLL 16E1/16T1 path. 0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path. 1000 ~ 1011: The output of T4 APLL. 1100: The output of T4 DPLL 77.76 MHz path. 1101: The output of T4 DPLL 12E1/24T1/E3/T3 path. 1110: The output of T4 DPLL 16E1/16T1 path. 1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path. These bits select a division factor of the divider for OUT2. The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output (selected by the OUT2_PATH_SEL[3:0] bits (b7~4, 6CH)). If the signal is derived from one of the T0/T4 DPLL outputs, please refer to Table 24 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to Table 25 for the division factor selection. 137 April 15, 2015 IDT82V3280 WAN PLL OUT3_FREQ_CNFG - Output Clock 3 Frequency Configuration Address: 6DH Type: Read / Write Default Value: 00001000 7 6 5 4 3 2 1 0 OUT3_PATH_SEL3 OUT3_PATH_SEL2 OUT3_PATH_SEL1 OUT3_PATH_SEL0 OUT3_DIVIDER3 OUT3_DIVIDER2 OUT3_DIVIDER1 OUT3_DIVIDER0 Bit 7-4 3-0 Name Description These bits select an input to OUT3. 0000 ~ 0011: The output of T0 APLL. (default: 0000) 0100: The output of T0 DPLL 77.76 MHz path. 0101: The output of T0 DPLL 12E1/24T1/E3/T3 path. 0110: The output of T0 DPLL 16E1/16T1 path. OUT3_PATH_SEL[3:0] 0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path. 1000 ~ 1011: The output of T4 APLL. 1100: The output of T4 DPLL 77.76 MHz path. 1101: The output of T4 DPLL 12E1/24T1/E3/T3 path. 1110: The output of T4 DPLL 16E1/16T1 path. 1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path. These bits select a division factor of the divider for OUT3. The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output OUT3_DIVIDER[3:0] (selected by the OUT3_PATH_SEL[3:0] bits (b7~4, 6DH)). If the signal is derived from one of the T0/T4 DPLL outputs, please refer to Table 24 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to Table 25 for the division factor selection. Programming Information 138 April 15, 2015 IDT82V3280 WAN PLL OUT4_FREQ_CNFG - Output Clock 4 Frequency Configuration Address: 6EH Type: Read / Write Default Value: 00000110 7 6 5 4 3 2 1 0 OUT4_PATH_SEL3 OUT4_PATH_SEL2 OUT4_PATH_SEL1 OUT4_PATH_SEL0 OUT4_DIVIDER3 OUT4_DIVIDER2 OUT4_DIVIDER1 OUT4_DIVIDER0 Bit 7-4 3-0 Name Description These bits select an input to OUT4. 0000 ~ 0011: The output of T0 APLL. (default: 0000) 0100: The output of T0 DPLL 77.76 MHz path. 0101: The output of T0 DPLL 12E1/24T1/E3/T3 path. 0110: The output of T0 DPLL 16E1/16T1 path. OUT4_PATH_SEL[3:0] 0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path. 1000 ~ 1011: The output of T4 APLL. 1100: The output of T4 DPLL 77.76 MHz path. 1101: The output of T4 DPLL 12E1/24T1/E3/T3 path. 1110: The output of T4 DPLL 16E1/16T1 path. 1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path. These bits select a division factor of the divider for OUT4. The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output OUT4_DIVIDER[3:0] (selected by the OUT4_PATH_SEL[3:0] bits (b7~4, 6EH)). If the signal is derived from one of the T0/T4 DPLL outputs, please refer to Table 24 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to Table 25 for the division factor selection. Programming Information 139 April 15, 2015 IDT82V3280 WAN PLL OUT5_FREQ_CNFG - Output Clock 5 Frequency Configuration Address: 6FH Type: Read / Write Default Value: 00000100 7 6 5 4 3 2 1 0 OUT5_PATH_SEL3 OUT5_PATH_SEL2 OUT5_PATH_SEL1 OUT5_PATH_SEL0 OUT5_DIVIDER3 OUT5_DIVIDER2 OUT5_DIVIDER1 OUT5_DIVIDER0 Bit 7-4 3-0 Name Description These bits select an input to OUT5. 0000 ~ 0011: The output of T0 APLL. (default: 0000) 0100: The output of T0 DPLL 77.76 MHz path. 0101: The output of T0 DPLL 12E1/24T1/E3/T3 path. 0110: The output of T0 DPLL 16E1/16T1 path. OUT5_PATH_SEL[3:0] 0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path. 1000 ~ 1011: The output of T4 APLL. 1100: The output of T4 DPLL 77.76 MHz path. 1101: The output of T4 DPLL 12E1/24T1/E3/T3 path. 1110: The output of T4 DPLL 16E1/16T1 path. 1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path. These bits select a division factor of the divider for OUT5. The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output OUT5_DIVIDER[3:0] (selected by the OUT5_PATH_SEL[3:0] bits (b7~4, 6FH)). If the signal is derived from one of the T0/T4 DPLL outputs, please refer to Table 24 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to Table 25 for the division factor selection. Programming Information 140 April 15, 2015 IDT82V3280 WAN PLL OUT6_FREQ_CNFG - Output Clock 6 Frequency Configuration Address:70H Type: Read / Write Default Value: 00000110 7 6 5 4 3 2 1 0 OUT6_PATH_SEL3 OUT6_PATH_SEL2 OUT6_PATH_SEL1 OUT6_PATH_SEL0 OUT6_DIVIDER3 OUT6_DIVIDER2 OUT6_DIVIDER1 OUT6_DIVIDER0 Bit 7-4 3-0 Name Description These bits select an input to OUT6. 0000 ~ 0011: The output of T0 APLL. (default: 0000) 0100: The output of T0 DPLL 77.76 MHz path. 0101: The output of T0 DPLL 12E1/24T1/E3/T3 path. 0110: The output of T0 DPLL 16E1/16T1 path. OUT6_PATH_SEL[3:0] 0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path. 1000 ~ 1011: The output of T4 APLL. 1100: The output of T4 DPLL 77.76 MHz path. 1101: The output of T4 DPLL 12E1/24T1/E3/T3 path. 1110: The output of T4 DPLL 16E1/16T1 path. 1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path. These bits select a division factor of the divider for OUT6. The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output OUT6_DIVIDER[3:0] (selected by the OUT6_PATH_SEL[3:0] bits (b7~4, 70H)). If the signal is derived from one of the T0/T4 DPLL outputs, please refer to Table 24 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to Table 25 for the division factor selection. Programming Information 141 April 15, 2015 IDT82V3280 WAN PLL OUT7_FREQ_CNFG - Output Clock 7 Frequency Configuration Address:71H Type: Read / Write Default Value: 00001000 7 6 5 4 3 2 1 0 OUT7_PATH_SEL3 OUT7_PATH_SEL2 OUT7_PATH_SEL1 OUT7_PATH_SEL0 OUT7_DIVIDER3 OUT7_DIVIDER2 OUT7_DIVIDER1 OUT7_DIVIDER0 Bit 7-4 3-0 Name Description These bits select an input to OUT7. 0000 ~ 0011: The output of T0 APLL. (default: 0000) 0100: The output of T0 DPLL 77.76 MHz path. 0101: The output of T0 DPLL 12E1/24T1/E3/T3 path. 0110: The output of T0 DPLL 16E1/16T1 path. OUT7_PATH_SEL[3:0] 0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path. 1000 ~ 1011: The output of T4 APLL. 1100: The output of T4 DPLL 77.76 MHz path. 1101: The output of T4 DPLL 12E1/24T1/E3/T3 path. 1110: The output of T4 DPLL 16E1/16T1 path. 1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path. These bits select a division factor of the divider for OUT7. The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output OUT7_DIVIDER[3:0] (selected by the OUT7_PATH_SEL[3:0] bits (b7~4, 71H)). If the signal is derived from one of the T0/T4 DPLL outputs, please refer to Table 24 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to Table 25 for the division factor selection. Programming Information 142 April 15, 2015 IDT82V3280 WAN PLL OUT8_FREQ_CNFG - Output Clock 8 Frequency Configuration & Output Clock 6, 7 & 9 Invert Configuration Address:72H Type: Read / Write Default Value: 01000000 7 6 5 4 3 2 1 0 OUT8_PATH_SEL OUT8_EN T4_INPUT_FAIL AMI_OUT_DUT Y 400HZ_SEL OUT9_INV OUT7_INV OUT6_INV Bit 7 6 Name Description These bits select an input to OUT8. OUT8_PATH_SEL 0: The output of T4 DPLL 77.76 MHz path. (default) 1: The output of T0 DPLL 77.76 MHz path. OUT8_EN Refer to the description of the T4_INPUT_FAIL bit (b5, 72H). This bit, together with the OUT8_EN bit (b6, 72H), determines whether a clock is enabled to be output on OUT8. OUT8_EN T4_INPUT_FAIL 5 T4_INPUT_FAIL 0 1 4 3 2 1 0 don’t-care 0 1 Output on OUT8 Output is disabled (output low). Output is enabled. (default) Output is enabled when the T4 selected input clock does not fail. Output is disabled (output low) when the T4 selected input clock fails. This bit determines the duty cycle of the output on OUT8. AMI_OUT_DUTY 0: 50:50. (default) 1: 5:8. This bit determines the frequency of the output on OUT8. 400HZ_SEL 0: 64 kHz + 8 kHz. (default) 1: 64 kHz + 8 kHz + 0.4 kHz. This bit determines whether the output on OUT9 is inverted. OUT9_INV 0: Not inverted. (default) 1: Inverted. This bit determines whether the output on OUT7 is inverted. OUT7_INV 0: Not inverted. (default) 1: Inverted. This bit determines whether the output on OUT6 is inverted. OUT6_INV 0: Not inverted. (default) 1: Inverted. Programming Information 143 April 15, 2015 IDT82V3280 WAN PLL OUT9_FREQ_CNFG - Output Clock 9 Frequency Configuration & Output Clock 1 ~ 5 Invert Configuration Address:73H Type: Read / Write Default Value: 01000000 7 6 5 4 3 2 1 0 OUT9_PATH_SEL OUT9_EN T4_INPUT_FAIL OUT5_INV OUT4_INV OUT3_INV OUT2_INV OUT1_INV Bit 7 6 5 Name Description These bits select an input to OUT9. OUT9_PATH_SEL 0: The output of T4 DPLL 16E1/16T1 path. (default) 1: The output of T0 DPLL 16E1/16T1 path. OUT9_EN Refer to the description of the T4_INPUT_FAIL bit (b5, 73H). This bit, together with the OUT9_EN bit (b6, 73H), determines whether clock is enabled to output on OUT9. OUT9_EN T4_INPUT_FAIL Output on OUT9 0 don’t-care 0 Output is disabled (output low). Output is enabled. (default) Output is enabled when the T4 selected input clock does not fail. Output is disabled (output low) when the T4 selected input clock fails. (Whether the T4 selected input clock is switched or not, as long as the T4 selected input clock does not change to be invalid, the T4 selected input clock does not fail). T4_INPUT_FAIL 1 4 OUT5_INV 3 OUT4_INV 2 OUT3_INV 1 OUT2_INV 0 OUT1_INV Programming Information 1 This bit determines whether the output on OUT5 is inverted. 0: Not inverted. (default) 1: Inverted. This bit determines whether the output on OUT4 is inverted. 0: Not inverted. (default) 1: Inverted. This bit determines whether the output on OUT3 is inverted. 0: Not inverted. (default) 1: Inverted. This bit determines whether the output on OUT2 is inverted. 0: Not inverted. (default) 1: Inverted. This bit determines whether the output on OUT1 is inverted. 0: Not inverted. (default) 1: Inverted. 144 April 15, 2015 IDT82V3280 WAN PLL FR_MFR_SYNC_CNFG - Frame Sync & Multiframe Sync Output Configuration Address:74H Type: Read / Write Default Value: 01100000 7 6 5 4 3 2 1 0 IN_2K_4K_8K_INV 8K_EN 2K_EN 2K_8K_PUL_P OSITION 8K_INV 8K_PUL 2K_INV 2K_PUL Bit 7 6 5 4 3 2 1 0 Name Description This bit determines whether the input clock is inverted before locked by the T0/T4 DPLL when the input clock is 2 kHz, 4 kHz or 8 kHz. IN_2K_4K_8K_INV 0: Not inverted. (default) 1: Inverted. This bit determines whether an 8 kHz signal is enabled to be output on FRSYNC_8K. 8K_EN 0: Disabled. FRSYNC_8K outputs low. 1: Enabled. (default) This bit determines whether a 2 kHz signal is enabled to be output on MFRSYNC_2K. 2K_EN 0: Disabled. MFRSYNC_2K outputs low. 1: Enabled. (default) This bit is valid only when FRSYNC_8K and/or MFRSYNC_2K output pulse; i.e., when one of the 8K_PUL bit (b2, 74H) and the 2K_PUL bit (b0, 74H) is ‘1’ or when the 8K_PUL bit (b2, 74H) and the 2K_PUL bit (b0, 74H) are both ‘1’. It deter2K_8K_PUL_POSITION mines the pulse position referring to the standard 50:50 duty cycle. 0: Pulsed on the falling edge of the standard 50:50 duty cycle position. (default) 1: Pulsed on the rising edge of the standard 50:50 duty cycle position. This bit determines whether the output on FRSYNC_8K is inverted. 8K_INV 0: Not inverted. (default) 1: Inverted. This bit determines whether the output on FRSYNC_8K is 50:50 duty cycle or pulsed. 8K_PUL 0: 50:50 duty cycle. (default) 1: Pulsed. The pulse width is defined by the period of the output on OUT3. This bit determines whether the output on MFRSYNC_2K is inverted. 2K_INV 0: Not inverted. (default) 1: Inverted. This bit determines whether the output on MFRSYNC_2K is 50:50 duty cycle or pulsed. 2K_PUL 0: 50:50 duty cycle. (default) 1: Pulsed. The pulse width is defined by the period of the output on OUT3. Programming Information 145 April 15, 2015 IDT82V3280 7.2.9 WAN PLL PBO & PHASE OFFSET CONTROL REGISTERS PHASE_MON_PBO_CNFG - Phase Transient Monitor & PBO Configuration Address:78H Type: Read / Write Default Value: 0X000110 7 6 5 4 3 2 1 0 IN_NOISE_WIN DOW - PH_MON_EN PH_MON_PBO_EN PH_TR_MON_L IMT3 PH_TR_MON_L IMT2 PH_TR_MON_L IMT1 PH_TR_MON_L IMT0 Bit Name Description This bit determines whether the input clock whose edge respect to the reference clock is outside ±5% is enabled to be selected for T0/T4 DPLL. IN_NOISE_WINDOW 0: Disabled. (default) 1: Enabled. Reserved. This bit is valid only when the PH_MON_PBO_EN bit (b4, 78H) is ‘1’. It determines whether the Phase Transient Monitor is enabled to monitor the phase-time changes on the T0 selected input clock. PH_MON_EN 0: Disabled. (default) 1: Enabled. This bit determines whether a PBO event is triggered when the phase-time changes on the T0 selected input clock are greater than a programmable limit over an interval of less than 0.1 seconds with the PH_MON_EN bit being ‘1’. The limit PH_MON_PBO_EN is programmed by the PH_TR_MON_LIMT[3:0] bits (b3~0, 78H). 0: Disabled. (default) 1: Enabled. These bits represent an unsigned integer. The Phase Transient Monitor limit in ns can be calculated as follows: PH_TR_MON_LIMT[3:0] Limit (ns) = (PH_TR_MON_LIMT[3:0] + 7) X 156. 7 6 5 4 3-0 PHASE_OFFSET[7:0]_CNFG - Phase Offset Configuration 1 Address:7AH Type: Read / Write Default Value: 00000000 7 6 5 4 3 2 1 0 PH_OFFSET7 PH_OFFSET6 PH_OFFSET5 PH_OFFSET4 PH_OFFSET3 PH_OFFSET2 PH_OFFSET1 PH_OFFSET0 Bit 7-0 Name Description PH_OFFSET[7:0] Refer to the description of the PH_OFFSET[9:8] bits (b1~0, 7BH). Programming Information 146 April 15, 2015 IDT82V3280 WAN PLL PHASE_OFFSET[9:8]_CNFG - Phase Offset Configuration 2 Address:7BH Type: Read / Write Default Value: 0XXXXX00 7 6 5 4 3 2 1 0 PH_OFFSET_EN - - - - - PH_OFFSET9 PH_OFFSET8 Bit 7 6-2 1-0 Name Description This bit determines whether the input-to-output phase offset is enabled. If the device is configured as the Master, the input-to-output phase offset: PH_OFFSET_EN 0: Disabled. (default) 1: Enabled. If the device is configured as the Slave, the input-to-output phase offset is always enabled. Reserved. These bits represent a 2’s complement signed integer. If the value is multiplied by 0.61, the input-to-output phase offset in ns PH_OFFSET[9:8] to adjust will be gotten. Programming Information 147 April 15, 2015 IDT82V3280 7.2.10 WAN PLL SYNCHRONIZATION CONFIGURATION REGISTERS SYNC_MONITOR_CNFG - Sync Monitor Configuration Address:7CH Type: Read / Write Default Value: X0101011 7 6 5 4 3 2 1 0 - SYNC_MON_LIMT2 SYNC_MON_LIMT1 SYNC_MON_LIMT0 - - - - Bit Name 7 - Description Reserved. These bits set the limit for the external sync alarm. 000: ±1 UI. 001: ±2 UI. 010: ±3 UI. (default) SYNC_MON_LIMT[2:0] 011: ±4 UI. 100: ±5 UI. 101: ±6 UI. 110: ±7 UI. 111: ±8 UI. These bits must be set to ‘1011’. 6-4 3-0 SYNC_PHASE_CNFG - Sync Phase Configuration Address:7DH Type: Read / Write Default Value: XXXXXX00 7 6 5 4 3 2 1 0 - - - - - - SYNC_PH11 SYNC_PH10 Bit Name Description 7-2 - 1-0 SYNC_PH1[1:0] Reserved. These bits set the sampling of EX_SYNC1 when EX_SYNC1 is enabled to synchronize the frame sync output signal. Nominally, the falling edge of EX_SYNC1 is aligned with the rising edge of the T0 selected input clock. 00: On target. (default) 01: 0.5 UI early. 10: 1 UI late. 11: 0.5 UI late. Programming Information 148 April 15, 2015 IDT82V3280 8 WAN PLL THERMAL MANAGEMENT The junction temperature Tj can be calculated as follows: Tj = TA + P X JA = 85°C + 1.9W X 18.9°C/W = 120.9°C The device operates over the industry temperature range -40°C ~ +85°C. To ensure the functionality and reliability of the device, the maximum junction temperature Tjmax should not exceed 125°C. In some applications, the device will consume more power and a thermal solution should be provided to ensure the junction temperature Tj does not exceed the Tjmax. 8.1 The junction temperature of 120.9°C is below the maximum junction temperature of 125°C so no extra heat enhancement is required. In some operation environments, the calculated junction temperature might exceed the maximum junction temperature of 125°C and an external thermal solution such as a heatsink is required. 8.3 JUNCTION TEMPERATURE A heatsink is expanding the surface area of the device to which it is attached. JA is now a combination of device case and heat-sink thermal resistance, as the heat flowing from the die junction to ambient goes through the package and the heatsink. JA can be calculated as follows: Junction temperature Tj is the temperature of package typically at the geographical center of the chip where the device's electrical circuits are. It can be calculated as follows: Equation 1: Tj = TA + P X JA Equation 2: JA = JC + CH+ HA Where: JA = Junction-to-Ambient Thermal Resistance of the Package Where: JC = Junction-to-Case Thermal Resistance CH = Case-to-Heatsink Thermal Resistance HA = Heatsink-to-Ambient Thermal Resistance Tj = Junction Temperature TA = Ambient Temperature P = Device Power Consumption CH+ HA determines which heatsink and heatsink attachment can In order to calculate junction temperature, an appropriate JA must be used. The JA is shown in Table 44: be selected to ensure the junction temperature does not exceed the maximum junction temperature. According to Equation 1 and 2, Power consumption is the core power excluding the power dissipated in the loads. Table 43 provides power consumption in special environments. CH+ HA can be calculated as follows: Equation 3: CH+ HA = (Tj - TA) / P - JC Assume: Table 43: Power Consumption and Maximum Junction Temperature Package Power Consumption (W) Operating Voltage (V) 1.9 1.9 3.6 3.6 TQFP/PNG100 TQFP/EQG100 8.2 HEATSINK EVALUATION Tj = 125°C (Tjmax) Maximum TA (°C) Junction Temperature (°C) 85 85 TA = 85°C P = 1.9W JC = 16.1°C/W (TQFP/EQG100) 125 125 CH+ HA can be calculated as follows: CH+ HA = (125°C - 85°C ) / 1.9W - 16.1°C/W = 5.0°C/W EXAMPLE OF JUNCTION TEMPERATURE CALCULATION That is, if a heatsink and heatsink attachment whose CH+ HA is below or equal to 5.0°C/W is used in such operation environment, the junction temperature will not exceed the maximum junction temperature. Assume: TA = 85°C JA = 18.9°C/W (TQFP/EQG100 Soldered & when airfow rate is 0 m/ s) P = 1.9W Table 44: Thermal Data Package Pin Count Thermal Pad TQFP/PNG100 100 No TQFP/EQG100 100 Yes/Exposed TQFP/EQG100 100 Yes/Soldered* *note: Simulated with 3 x 3 array of thermal vias. Thermal Management JC (°C/W) JB (°C/W) 11.0 16.1 16.1 34.2 34.2 1.3 149 JA (°C/W) Air Flow in m/s 0 1 2 3 4 5 39.3 35.8 18.9 36.2 31.1 14.6 34.3 29.5 13.5 33.5 28.6 12.9 32.9 27.9 12.6 32.6 27.4 12.4 April 15, 2015 IDT82V3280 8.4 WAN PLL TQFP EPAD THERMAL RELEASE PATH by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 27. The solderable area on the PCB, as defined SOLDER PIN PIN PAD EXPOSED HEAT SLUG GROUND PLANE SOLDER LAND PATTERN THERMAL VIA SOLDER PIN PIN PAD (GROUND PAD) Figure 27. Assembly for Expose Pad thermal Release Path (Side View) While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as ‘heat pipes’. The number of vias (i.e. ‘heat pipes’) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias con- Thermal Management nected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1 oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Leadfame Base Package, Amkor Technology. 150 April 15, 2015 IDT82V3280 WAN PLL 9 ELECTRICAL SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATING Table 45: Absolute Maximum Rating Symbol Parameter Min Max Unit VDD Supply Voltage VDD -0.5 3.6 V VIN Input Voltage (non-supply pins) 5.5 V VOUT Output Voltage (non-supply pins) 5.5 V TA Ambient Operating Temperature Range -40 +85 °C TSTOR Storage Temperature -50 +150 °C 9.2 RECOMMENDED OPERATION CONDITIONS Table 46: Recommended Operation Conditions Symbol Parameter Min Typ Max Unit VDD Power Supply (DC voltage) VDD 3.0 3.3 3.6 V TA Ambient Temperature Range -40 +85 °C IDD Supply Current 455 528 mA PTOT Total Power Dissipation 1.5 1.9 W Electrical Specifications 151 Test Condition Exclude the loading current and power April 15, 2015 IDT82V3280 WAN PLL 9.3 I/O SPECIFICATIONS 9.3.1 AMI INPUT / OUTPUT PORT 9.3.1.1 Structure Violation Violation Violation 8 kHz (125 s) 8 kHz (125 s) 8 kHz (125 s) Figure 28. 64 kHz + 8 kHz Signal Structure Violation Violation Violation 8 kHz (125 s) 8 kHz (125 s) Violation 8 kHz (125 s) 8 kHz (125 s) 0.4 kHz (2.5 ms) Figure 29. 64 kHz + 8 kHz + 0.4 kHz Signal Structure 9.3.1.2 I/O Level 15.6 s 15.6 s 7.8 s 7.8 s + VDD + 1.0 VIH 2 Vp-p 0 VIM 470 nF 1V - 1.0 VIL IN1 0V OUT8_POS 1V Signal structure of 64 kHz / 8 kHz central clock interface after suitable transformer 15.6 s 470 pF IN2 7.8 s 470 nF OUT8_NEG Figure 30. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Signal Input Level + VDD 0V Figure 31. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Signal Output Level Electrical Specifications 152 April 15, 2015 IDT82V3280 WAN PLL AMI input Turns ratio 3:1 IN1 OUT8_POS AMI output 470 nF Rload 470 pF AMI input 2 nF GND IN2 OUT8_NEG 470 nF For a transformer with a turns ratio of 1:1, a 3:1 ratio potential divider Rload must be used to achieve the required 1 V pk-pk voltage level for the positive and negative pulses. Figure 32. AMI Input / Output Port Line Termination (Recommended) Table 47: AMI Input / Output Port Electrical Characteristics Parameter Description Min Typ Max Unit tPW Input Pulse Width 1.56 7.8 14.04 S tR/F S Input Pulse Rise/Fall Time 5 VIH Input Voltage High 2.13 VDD + 0.3 V VIM Input Voltage Middle 1.5 1.8 V VIL Input Voltage Low 0 1.4 V 20 mA IOUT Output Current Drive VOH Output Voltage High, Output Current = 20 mA VOL Output Voltage Low, Output Current = 20 mA 1.65 VDD - 0.16 V 0.16 V RTEST Nominal Test Load Impedance VMARK ‘Mark’ Amplitude after Transformer 0.9 1.0 1.1 V VSPACE “Space” Amplitude after Transformer -0.1 0 0.1 V Electrical Specifications  110 153 April 15, 2015 IDT82V3280 9.3.1.3 WAN PLL Over-Voltage Protection The device may require over-voltage protection on AMI input ports according to ITU Recommendation K.41. 9.3.2 CMOS INPUT / OUTPUT PORT From Table 48 to Table 51, VDD is 3.3 V. Table 48: CMOS Input Port Electrical Characteristics Parameter Description Min Typ Max Unit VIH Input Voltage High 0.7VDD VIL Input Voltage Low 0.2VDD V IIN Input Current 10 A VIN Input Voltage 5.5 V Max Unit Test Condition V -0.5 Table 49: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics Parameter Description Min VIH Input Voltage High 0.7VDD VIL Input Voltage Low PU Pull-Up Resistor IIN Input Current VIN Input Voltage Typ Test Condition V 10 -0.5 0.2VDD V 80 K 250 A 5.5 V Table 50: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics Parameter Description Min VIH Input Voltage High 0.7VDD VIL Input Voltage Low PD Pull-Down Resistor IIN Input Current VIN Input Voltage Typ Max -0.5 Test Condition V 0.2VDD 10 5 100 Unit 80 40 300 350 700 40 5.5 V other CMOS input port with internal pull-down resistor TRST and TCK pin A[6:0], AD[7:0] pins other CMOS input port with internal pull-down resistor TRST and TCK pin A[6:0], AD[7:0] pins K A V Table 51: CMOS Output Port Electrical Characteristics Application Pin Parameter Description VOH Output Voltage High VOL Output Voltage Low tR Rise time Output Clock Min Typ Max Unit Test Condition 2.4 VDD V IOH = 8 mA 0 0.4 V IOL = 8 mA 4 ns 15 pF 3 tF Fall time 4 ns 15 pF VOH Output Voltage High 2.5 VDD V IOH = 4 mA VOL Output Voltage Low 0 0.4 V IOL= 4 mA tR Rise Time 10 ns 50 pF tF Fall Time 10 ns 50 pF Other Output Electrical Specifications 3 154 April 15, 2015 IDT82V3280 WAN PLL 9.3.3 PECL / LVDS INPUT / OUTPUT PORT 9.3.3.1 PECL Input / Output Port 130  82  VDD (+ 3.3 V) GND 50  (transmission line) 2 kHz OUT6_POS to 667 MHz OUT6_NEG 50  (transmission line) VDD (+ 3.3 V) GND 130  82  VDD (+ 3.3 V) 50  (transmission line) 130  IN5_POS 82  2 kHz to 667 MHz GND 130  82  VDD (+ 3.3 V) GND 50  (transmission line) 2 kHz OUT7_POS to 667 MHz OUT7_NEG 50  (transmission line) VDD (+ 3.3 V) GND 130  82  VDD (+ 3.3 V) 50  (transmission line) 130  IN5_NEG 82  GND VDD (+ 3.3 V) 50  (transmission line) Figure 34. Recommended PECL Output Port Line Termination 130  IN6_POS 82  2 kHz to 667 MHz GND VDD (+ 3.3 V) 50  (transmission line) 130  IN6_NEG 82  GND Figure 33. Recommended PECL Input Port Line Termination Electrical Specifications 155 April 15, 2015 IDT82V3280 WAN PLL Table 52: PECL Input / Output Port Electrical Characteristics Parameter Description Min Max Unit VDD - 2.5 VDD - 0.5 V VDD - 2.4 VDD - 0.4 V Input Differential Voltage 0.1 1.4 V Input Low Voltage, Single-ended Input 2 VDD - 2.4 VDD - 1.5 V VDD - 1.3 VDD - 0.5 V IIH Input High Voltage, Single-ended Input 2 Input High Current, Input Differential Voltage VID = 1.4 V -10 10 A IIL Input Low Current, Input Differential Voltage VID = 1.4 V -10 10 A VOL Output Voltage Low 3 VDD - 2.1 VDD - 1.62 V VOH Output Voltage High 3 VDD - 1.25 VDD - 0.88 V VOD Output Differential Voltage3 580 900 mV VIL Input Low Voltage, Differential Inputs 1 VIH Input High Voltage, Differential Inputs 1 VID VIL_S VIH_S Typ tRISE Output Rise time (20% to 80%) 200 300 pS tFALL Output Fall time (20% to 80%) 200 300 pS tSKEW Output Differential Skew 50 pS Test Condition Note: 1. Assuming a differential input voltage of at least 100 mV. 2. Unused differential input terminated to VDD-1.4 V. 3. With 50  load on each pin to VDD-2 V, i.e. 82 to GND and 130 to VDD. Electrical Specifications 156 April 15, 2015 IDT82V3280 9.3.3.2 WAN PLL LVDS Input / Output Port 50  (transmission line) 2 kHz to 667 MHz OUT6_POS 100  IN5_POS 100  50  (transmission line) 50  (transmission line) OUT6_NEG IN5_NEG OUT7_POS 50  (transmission line) IN6_POS 2 kHz to 100  667 MHz IN6_NEG 50  (transmission line) 50  (transmission line) 50  (transmission line) 100  OUT7_NEG 50  (transmission line) 2 kHz to 667 MHz 2 kHz to 667 MHz Figure 36. Recommended LVDS Output Port Line Termination Figure 35. Recommended LVDS Input Port Line Termination Table 53: LVDS Input / Output Port Electrical Characteristics Parameter Description VCM Min Typ Max Unit VDIFF Input Common-mode Voltage Range 0 1200 2400 mV Input Peak Differential Voltage 100 900 mV -100 100 mV Test Condition VIDTH Input Differential Threshold RTERM External Differential Termination Impedance 95 105  VOH Output Voltage High 1350 1475 mV VOL Output Voltage Low 925 1100 mV RLOAD = 100  ± 1% 100 RLOAD = 100  ± 1% VOD Differential Output Voltage 250 400 mV RLOAD = 100  ± 1% VOS Output Offset Voltage 1125 1275 mV RLOAD = 100  ± 1% 80 RO Differential Output Impedance 120  VCM = 1.0 V or 1.4 V RO RO Mismatch between A and B 20 % VCM = 1.0 V or 1.4 V VOD Change in VOD between Logic 0 and Logic 1 25 mV RLOAD = 100  ± 1% 25 mV RLOAD = 100  ± 1% 100 VOS Change in VOS between Logic 0 and Logic 1 ISA, ISB Output Current 24 mA Driver shorted to GND ISAB Output Current 12 mA Driver shorted together tRISE Output Rise time (20% to 80%) 300 pS RLOAD = 100  ± 1% 300 pS RLOAD = 100  ± 1% 50 pS RLOAD = 100  ± 1% tFALL Output Fall time (20% to 80%) tSKEW Output Differential Skew Electrical Specifications 200 200 157 April 15, 2015 IDT82V3280 9.3.3.3 WAN PLL Single-Ended Input for Differential Input This is a recommended and tested interface circuit to drive differential input with a single-ended signal. VCC = 3.3 V VCC = 3.3 V R4 100 (Option) Ro ~ 7  R1 1K Zo = 50  Rs + Vth 43 R5 100 (Option) Driver_LVCMOS C1 0.1 uF R2 1K Receiver Ro + Rs = Zo Figure 37. Example of Single-Ended Signal to Drive Differential Input Vth = VCC*[R2/(R1+R2)] For the example in Figure 37, R1 = R2, so Vth = VCC/2 =1.65 V The suggested single-ended signal input: VIHmax = VCC VILmin = 0 V Vswing = 0.6 V ~ VCC DC offset (Swing Center) = Vth/2 +/- Vswing*10% Electrical Specifications 158 April 15, 2015 IDT82V3280 9.4 WAN PLL JITTER & WANDER PERFORMANCE Table 54: Output Clock Jitter Generation Test Definition 1 Peak to Peak Typ RMS Typ N x 2.048MHz without APLL N x 2.048MHz with T0/T4 APLL N x 1.544 MHz without APLL N x 1.544 MHz with T0/T4 APLL 44.736 MHz with T0/T4 APLL 44.736 MHz without APLL 34.368 MHz with T0/T4 APLL 34.368 MHz without APLL