840002AGI-01LF

FemtoClock®, Crystal-to-LVCMOS/LVTTL Frequency Synthesizer 840002I-01 DATA SHEET General Description Features The 840002I-01 is a two output LVCMOS/LVTTL Synthesizer optimized to generate Ethernet reference clock frequencies. Using a 25MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the two frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz, and 62.5MHz. The 840002I-01 uses IDT’s 3RD generation low phase noise VCO technology and can achieve 1ps or lower typical random rms phase jitter, easily meeting Ethernet jitter requirements. The 840002I-01 is packaged in a small 16-pin TSSOP package. • Two LVCMOS/LVTTL outputs@ 3.3V, 17 typical output impedance • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended TEST_CLK • Supports the following output frequencies: 156.25MHz, 125MHz and 62.5MHz • • • • Output frequency range: 56MHz to 175MHz VCO range: 560MHz to 700MHz Output skew: 12ps (maximum) RMS phase jitter at 156.25MHz, (1.875MHz to 20MHz): 0.47ps (typical) Phase Noise: Offset Noise Power 100Hz ................ -97.4 dBc/Hz 1kHz .................. -120.2 dBc/Hz 10kHz ................ -127.6 dBc/Hz 100kHz .............. -126.1 dBc/Hz Frequency Select Function Table Inputs N Divider Value Output Frequency (25MHz Ref.) F_SEL1 F_SEL0 M Divider Value 0 0 25 4 156.25 0 1 25 5 125 1 0 25 10 62.5 1 1 25 5 125 • Power Supply Modes: Core / Output 3.3V / 3.3V 3.3V / 2.5V 2.5V / 2.5V • • -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment Block Diagram OE F_SEL1:0 F_SEL0 nXTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA VDD Pullup 2 Pullup:Pullup nPLL_SEL Pulldown nXTAL_SEL Pulldown XTAL_IN OSC F_SEL1:0 0 1 XTAL_OUT TEST_CLK Pulldown 1 Phase Detector VCO 0 00 01 10 11 N 4 5 10 5 Q0 Q1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 F_SEL1 GND GND Q0 Q1 VDDO XTAL_IN XTAL_OUT 840002I-01 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View M = 25 (fixed) MR Pulldown 840002I-01 Rev B 8/5/15 1 ©2015 Integrated Device Technology, Inc. 840002I-01 DATA SHEET Table 1. Pin Descriptions Number Name 1 F_SEL0 Type Input Description Pullup 2 nXTAL_SEL Input Pulldown 3 TEST_CLK Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. Selects between crystal or TEST_CLK inputs as the PLL reference source. When HIGH, selects TEST_CLK. When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. Single-ended test clock input. LVCMOS/LVTTL interface levels. 4 OE Input Pullup Output enable. When logic HIGH, the outputs are active. When LOW, the outputs are in high-impedance state. LVCMOS/LVTTL interface levels. 5 MR Input Pulldown Active High Master Reset. When logic HIGH, the internal dividers are reset causing the active outputs to go low. When Logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 6 nPLL_SEL Input Pulldown PLL Bypass. When LOW, the output is driven from the VCO output. When HIGH, the PLL is bypassed and the output frequency = reference clock frequency/N output divider. LVCMOS/LVTTL interface levels. 7 VDDA Power Analog supply pin. 8 VDD Power Core supply pin. 9, 10 XTAL_OUT XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 11 VDDO Power Output supply pin. 12, 13 Q1, Q0 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. 14, 15 GND Power Power supply ground. 16 F_SEL1 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF CPD Power Dissipation Capacitance 8 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k ROUT Output Impedance FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER Test Conditions Minimum Typical Maximum Units VDDO = 3.3V ± 5% 14 17 21  VDDO = 2.5V ± 5% 16 21 25  2 Rev B 8/5/15 840002I-01 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 89C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 3A. Power Supply DC Characteristics, VDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 100 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 5 mA Table 3B. Power Supply DC Characteristics, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C to 85°C Symbol Parameter VDD Minimum Typical Maximum Units Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 95 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 5 mA Rev B 8/5/15 Test Conditions 3 FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840002I-01 DATA SHEET Table 3C. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = VDDO = 3.3V±5% or 2.5V±5%; or VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum VDD = 3.3V Typical Maximum Units 2 VDD + 0.3 V VDD = 2.5V 1.7 VDD + 0.3 V VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V OE, F_SEL0, F_SEL1 VDD = VIN = 3.465V or 2.625V 5 µA MR, TEST_CLK, nXTAL_SEL, nPLL_SEL VDD = VIN =3.465V or 2.625V 150 µA OE, F_SEL0, F_SEL1 VDD = 3.465V or 2.625V, VIN = 0V -150 µA MR, TEST_CLK, nXTAL_SEL, nPLL_SEL VDD = 3.465V or 2.625V, VIN = 0V -5 µA VDDO = 3.3V±5% 2.6 V VDDO = 2.5V±5% 1.8 V VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VDDO = 3.3V±5% or 2.5V±5% 0.5 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section, Output Load Test Circuit diagrams. Table 4. Crystal Characteristics Parameter Test Conditions Mode of Oscillation Minimum Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50  Shunt Capacitance (CO) 7 pF NOTE: Characterized using an 18pF parallel resonant crystal. FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 4 Rev B 8/5/15 840002I-01 DATA SHEET AC Electrical Characteristics Table 5A. AC Characteristics, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C to 85°C Symbol fOUT tsk(o) tjit(Ø) Parameter Output Frequency Test Conditions Minimum F_SEL[1:0] = 00 Typical Maximum Units 140 175 MHz F_SEL[1:0] = 01 or 11 112 140 MHz F_SEL[1:0] = 10 56 70 MHz 12 ps Output Skew; NOTE 1, 2 RMS Phase Jitter, Random; NOTE 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle 156.25MHz, (1.875MHz - 20MHz) 0.47 ps 125MHz, (1.875MHz - 20MHz) 0.57 ps 62.5MHz, (1.875MHz - 20MHz) 0.51 ps 20% to 80% 200 700 ps 46 54 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Refer to Phase Noise Plots. Table 5B. AC Characteristics, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C to 85°C Symbol fOUT tsk(o) tjit(Ø) Parameter Output Frequency Test Conditions Minimum F_SEL[1:0] = 00 Typical Maximum Units 140 175 MHz F_SEL[1:0] = 01 or 11 112 140 MHz F_SEL[1:0] = 10 56 70 MHz 12 ps Output Skew; NOTE 1, 2 RMS Phase Jitter, Random; NOTE 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle 156.25MHz, (1.875MHz - 20MHz) 0.47 ps 125MHz, (1.875MHz - 20MHz) 0.55 ps 62.5MHz, (1.875MHz - 20MHz) 0.49 ps 20% to 80% 200 700 ps 46 54 % Maximum Units For NOTES, see Table 5A above. Table 5C. AC Characteristics, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency tsk(o) Output Skew; NOTE 1, 2 tjit(Ø) RMS Phase Jitter, Random; NOTE 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical F_SEL[1:0] = 00 140 175 MHz F_SEL[1:0] = 01 or 11 112 140 MHz F_SEL[1:0] = 10 56 70 MHz 12 ps 156.25MHz, (1.875MHz - 20MHz) 0.49 ps 125MHz, (1.875MHz - 20MHz) 0.56 ps 62.5MHz, (1.875MHz - 20MHz) 20% to 80% fOUT = 125MHz 0.52 ps 200 700 ps 46 54 % 47 53 % For NOTES, see Table 5A above. Rev B 8/5/15 5 FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840002I-01 DATA SHEET ➝ Typical Phase Noise at 62.5MHz (3.3V) 1Gb Ethernet Filter Raw Phase Noise Data ➝ ➝ Noise Power dBc Hz 62.5MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.51ps (typical) Phase Noise Result by adding a 1Gb Ethernet filter to raw data Offset Frequency (Hz) FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 6 Rev B 8/5/15 840002I-01 DATA SHEET ➝ Typical Phase Noise at 156.25MHz (3.3V) 10Gb Ethernet Filter Raw Phase Noise Data ➝ ➝ Noise Power dBc Hz 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.47ps (typical) Phase Noise Result by adding a 10Gb Ethernet filter to raw data Offset Frequency (Hz) Rev B 8/5/15 7 FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840002I-01 DATA SHEET Parameter Measurement Information 1.65V±5% 2.05V±5% 1.25V±5% SCOPE VDD, VDDA, VDDO SCOPE VDD, VDDA Qx VDDO LVCMOS Qx GND GND VDDO 2 -1.65V±5% -1.25V±5% 3.3V Core/2.5V Output Load AC Test Circuit 3.3V Core/3.3V Output Load AC Test Circuit 1.25V±5% Noise Power Phase Noise Plot SCOPE VDD, VDDA, VDDO Qx Phase Noise Mask GND f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot -1.25V±5% RMS Phase Jitter 2.5V Core/2.5V Output Load AC Test Circuit V V DDO DDO Qx 2 Q[0:1] 2 t PW t V PERIOD DDO Qy 2 tsk(o) odc = t PW x 100% t PERIOD Output Skew Output Duty Cycle/Pulse Width/Period Q[0:1] 80% 80% tR tF 20% 20% Output Rise/Fall Time FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 8 Rev B 8/5/15 840002I-01 DATA SHEET Applications Information Recommendations for Unused Input and Output Pins Inputs: Outputs: Crystal Inputs LVCMOS Outputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. All unused LVCMOS outputs can be left floating. We recommend that there is no trace attached. TEST_CLK Input For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the TEST_CLK to ground. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Rev B 8/5/15 9 FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840002I-01 DATA SHEET Overdriving the XTAL Interface matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 1A. The XTAL_OUT pin can be left floating. The maximum amplitude of the input signal should not exceed 2V and the input edge rate can be as slow as 10ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 10 Rev B 8/5/15 840002I-01 DATA SHEET Layout Guideline 0.1uF capacitor in each power pin filter should be placed on the device side of the PCB and the other components can be placed on the opposite side. Figure 2 shows a schematic example of the 840002I-01 application schematic. In this example, the device is operated at VDD = VDDA = VDDO = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The load capacitance C1 = 22pF and C2 = 22pF are recommended for frequency accuracy. Depending on the parasitic of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used. This will required adjusting C1 and C2. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. As with any high speed analog circuitry, the power supply pins are vulnerable to noise. To achieve optimum jitter performance, power supply isolation is required. The 840002I-01 provides separate power supplies to isolate from coupling into the internal PLL. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the Figure 2. 840002I-01 Application Schematic Example Rev B 8/5/15 11 FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840002I-01 DATA SHEET Reliability Information Table 6. JA vs. Air Flow Table for a 16 Lead TSSOP JA by Velocity Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 118.2°C/W 106.8°C/W Multi-Layer PCB, JEDEC Standard Test Boards 89.0°C/W 81.8°C/W 78.1°C/W Transistor Count The transistor count for 840002I-01 is: 3356 Package Outline and Package Dimensions Package Outline - G Suffix for 16 Lead TSSOP Table 7. Package Dimensions for 16 Lead TSSOP All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.20 A1 0.5 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75  0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 12 Rev B 8/5/15 840002I-01 DATA SHEET Ordering Information Table 8. Ordering Information Part/Order Number 840002AGI-01LF 840002AGI-01LFT Marking 002AI01L 002AI01L Package “Lead-Free”, 16 Lead LQFP “Lead-Free”, 16 Lead LQFP Shipping Packaging Tube Tape & Reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. Rev B 8/5/15 13 FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 840002I-01 DATA SHEET Revision History Sheet Rev A A Table Page T8 12 T8 12 14 T5A - T5C 4-5 8 9 10 A T5B 5 T5C 5 8 8 9 10 B Description of Change Date Ordering Information Table - corrected standard marking and added Lead-Free part number, marking and note. 10/18/07 Updated datasheet's header/footer with IDT from ICS. Removed ICS prefix from Part/Order Number column. Added Contact Page. 11/18/10 AC Characteristics Tables - added thermal note. Power Supply Filtering Techniques - corrected figure 1. Added Overdriving the Crystal Interface section. Added Recommendations for Unused Input & Output Pins section. 12/6/10 3.3V/2.5V AC Characteristics Table -corrected FOUT from 56MHz min - 68MHz max to 56MHz min - 70MHz max. 2.5V AC Characteristics Table - added 2nd odc spec and added thermal note. Corrected FOUT from 56MHz min - 68MHz max to 56MHz min - 70MHz max. Deleted Power Supply Filtering Techniques section, added to schematic layout. Deleted Crystal Input Interface section. Added Overdriving the XTAL Interface section. Updated Layout Guideline and diagram. Converted datasheet format. 2/3/11 B 5A, 5B, 5C 5 AC Table; fOUT = F_SEL[1:0] = 01 or 11, F_SEL[1:0] = 10 B 8 13 Deleted Quantity from Tape and Reel T8 13 Ordering Information - removed leaded devices. Updated data sheet format. B FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 14 9/28/12 8/5/15 Rev B 8/5/15 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. 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