840051AGLF

ICS840051 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR NRND – Not Recommend for New Designs - 8/30/2013 For replacement device use ICS840N051BGI NRND GENERAL DESCRIPTION FEATURES The 840051 is a Gigabit Ethernet Clock Generator and a member of the family of high performance devices from IDT. T h e 8 4 0 0 5 1 c a n s y n t h e s i ze 1 0 G i g a b i t E t h e r n e t , SONET, or Ser ial ATA reference clock frequencies with the appropriate choice of crystal and output divider. The 840051 has excellent phase jitter performance and is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • 1 LVCMOS/LVTTL output, 15Ω output impedance • Crystal oscillator interface designed for 18pF parallel resonant crystals • Output frequency range: 70MHz - 170MHz • VCO range: 560MHz - 680MHz • RMS phase jitter at 155.52MHz (1.875MHz - 20MHz): 0.48ps (typical) • RMS phase noise at 155.52MHz Offset Noise Power 100Hz ................-99.7 dBc/Hz 1KHz .................-120 dBc/Hz 10KHz .................-128 dBc/Hz 100KHz .................-127 dBc/Hz • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Lead-Free fully RoHS compliant • Industrial temperature information available upon request • Not Recommended For New Designs FREQUENCY TABLE • For New Designs use ICS840N051BGI Inputs Crystal Frequency (MHz) FREQ_SEL Output Frequency (MHz) 20.141601 0 161.132812 20.141601 1 80.566406 19.53125 0 156.25 19.53125 1 78.125 19.44 0 155.52 19.44 1 77.76 18.75 0 150 18.75 1 75 BLOCK DIAGRAM PIN ASSIGNMENT OE Pullup VDDA OE XTAL_OUT XTAL_IN FREQ_SEL Pulldown XTAL_IN OSC XTAL_OUT Phase Detector 0 ÷4 (default) 1 ÷8 VCO 560MHz-680MHz 1 2 3 4 8 7 6 5 VDD Q0 GND FREQ_SEL Q0 840051 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View ÷32 (fixed) 840051 REV. A 9/1/15 1 ICS840051 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR NRND – Not Recommend for New Designs - 8/30/2013 NRND TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 VDDA Power 2 OE Input 3, 4 XTAL_OUT, XTAL_IN Input 5 FREQ_SEL Input 6 GND Power Power supply ground. 7 Q0 Output Single-ended clock output. LVCMOS/LVTTL interface levels. 15Ω output impedance. 8 VDD Power Core supply pin. Analog supply pin. Pullup Output enable pin. When HIGH, Q0 output is enabled. When LOW, forces Q0 to HiZ state. LVCMOS/LVTTL interface levels. See Table 3A. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3B. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical 4 VDD, VDDA = 3.465V Maximum Units pF CPD Power Dissipation Capacitance 7 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ ROUT Output Impedance 15 Ω TABLE 3A. CONTROL FUNCTION TABLE Control Input Output OE Q0 0 Hi-Z 1 Active TABLE 3B. FREQ_SEL FUNCTION TABLE Control Input FRE_SEL N Divider 0 ÷4 (default) 1 ÷8 840051 REV. A 9/1/15 2 ICS840051 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR NRND – Not Recommend for New Designs - 8/30/2013 NRND ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 60 mA IDDA Analog Supply Current 10 mA Maximum Units 2 VDD + 0.3 V -0.3 0.8 V 5 µA 150 µA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current Test Conditions OE FREQ_SEL Minimum Typical VDD = VIN = 3.465V VDD = VIN = 3.465V OE VDD = 3.465V, VIN = 0V -150 µA FREQ_SEL VDD = 3.465V, VIN = 0V -5 µA 2.6 V IIL Input Low Current VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 0.5 V Maximum Units 21.25 MHz NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section, “3.3V Output Load Test Circuit”. TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental Frequency 17.5 Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF 840051 REV. A 9/1/15 3 ICS840051 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR NRND – Not Recommend for New Designs - 8/30/2013 NRND TABLE 6. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter ( Random); NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 70 155.52MHz, Integration Range: 1.875MHz - 20MHz 77.76MHz, Integration Range: 1.875MHz - 20MHz 20% to 80% Maximum Units 170 MHz 0.48 ps 0.45 ps 200 500 ps 48 52 % NOTE 1: Please refer to the Phase Noise Plots. 840051 REV. A 9/1/15 4 ICS840051 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR NRND – Not Recommend for New Designs - 8/30/2013 NRND TYPICAL PHASE NOISE AT 155.52MHZ 0 -10 ➤ -20 -30 10GigE Filter -40 155.52MHz NOISE POWER dBc Hz -50 RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.48ps (typical) -60 -70 -80 -90 -100 Raw Phase Noise Data -110 ➤ -120 -130 -140 -150 -160 ➤ -170 Phase Noise Result by adding 10GigE Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 77.76MHZ 0 -10 ➤ -20 -30 10GigE Filter -40 77.76MHz NOISE POWER dBc Hz -50 RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.45ps (typical) -60 -70 -80 -90 -100 Raw Phase Noise Data -110 ➤ -120 -130 -140 -150 -160 ➤ -170 -180 -190 100 1k 10k Phase Noise Result by adding 10GigE Filter to raw data 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 840051 REV. A 9/1/15 5 ICS840051 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR NRND – Not Recommend for New Designs - 8/30/2013 PARAMETER MEASUREMENT INFORMATION 3.3V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME 840051 NRND REV. A 9/1/15 6 ICS840051 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR NRND – Not Recommend for New Designs - 8/30/2013 NRND APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 840051 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The 840051 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. Figure 2. CRYSTAL INPUt INTERFACE 840051 REV. A 9/1/15 7 ICS840051 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR NRND – Not Recommend for New Designs - 8/30/2013 NRND RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT The transistor count for 840051 is: 1927 840051 REV. A 9/1/15 8 ICS840051 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR NRND – Not Recommend for New Designs - 8/30/2013 NRND PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 8 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 840051 REV. A 9/1/15 9 ICS840051 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR NRND – Not Recommend for New Designs - 8/30/2013 NRND TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 840051AGLF 051AL 840051AGLFT 051AL 8 Lead “Lead-Free” TSSOP tube 0°C to 70°C 8 Lead “Lead-Free” TSSOP tape & reel 0°C to 70°C 840051 REV. A 9/1/15 10 ICS840051 FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR NRND – Not Recommend for New Designs - 8/30/2013 REVISION HISTORY SHEET Rev Table Page A T9 10 Description of Change Ordering Information Table - Removed leaded devices. 840051 NRND Date 9/1/15 REV. A 9/1/15 11 Corporate Headquarters 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. 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