260MHz, Crystal-to-LVCMOS/LVTTL
Frequency Synthesizer
84021
DATA SHEET
General Description
Features
The 84021 is a general purpose, Crystal-to-LVCMOS/LVTTL High
Frequency Synthesizer. The 84021 has a selectable TEST_CLK or
crystal input. The VCO operates at a frequency range of 620MHz to
780MHz. The VCO frequency is programmed in steps equal to the
value of the input reference or crystal frequency. The VCO and
output frequency can be programmed using the serial or parallel
interface to the configuration logic.
•
•
Two LVCMOS/LVTTL outputs
•
•
•
•
Output frequency range: 103.3MHz to 260MHz
•
•
RMS period jitter: 14.7ps (typical), (N ÷ 4, VDDO = 3.3V±5%)
Selectable crystal oscillator interface or LVCMOS/LVTTL
TEST_CLK
Crystal input frequency range: 14MHz to 40MHz
VCO range: 620MHz to 780MHz
Parallel or serial interface for programming counter and output
dividers
RMS phase jitter at 155.52MHz, using a 38.88MHz crystal (12kHz
to 20MHz): 2.61ps (typical)
Offset
Noise Power
100Hz.................-87.9 dBc/Hz
1kHz ...................-115.8 dBc/Hz
10kHz .................-124.2 dBc/Hz
100kHz ...............-127.7 dBc/Hz
•
•
•
•
Full 3.3V or mixed 3.3V core/2.5V or 1.8V output supply voltage
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
Available in lead-free (RoHS 6) package
VCO
÷M
0
1
N
÷3
÷4
÷5
÷6
Configuration Interface Logic
Q0
Q1
TEST
nP_LOAD
XTAL_IN
M0
3
22
XTAL_SEL
M8
4
21
VDDA
N0
5
20
S_LOAD
N1
6
19
S_DATA
nc
7
18
S_CLOCK
GND
8
17
MR
9
10 11 12 13 14 15 16
GND
MR Pulldown
M7
Q1
Phase Detector
TEST_CLK
Q0
PLL
23
VDDO
XTAL_OUT
XTAL_OUT
2
OE0
1
24
M6
OE1
OSC
1
VDD
0
XTAL_IN
M5
TEST
TEST_CLK Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
M1
32 31 30 29 28 27 26 25
XTAL_SEL Pullup
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M2
M4
OE1 Pullup
VCO_SEL Pullup
M3
OE0 Pullup
VCO_SEL
Pin Assignment
Block Diagram
84021
32 Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
M[0:8] M5 Pullup; M[0:4, 6:8] Pulldown
N[0:1] Pulldown
84021 Rev E 9/23/15
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©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Functional Description
NOTE: The functional description that follows describes operation
using a 25MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 5, NOTE 1.
VCO frequency, the crystal frequency and the M divider is defined as
follows: fVCO = fxtal x M
The M value and the required values of M0 through M8 are shown in
Table 3B, Programmable VCO Frequency Function Table. Valid M
values for which the PLL will achieve lock for a 25MHz reference are
defined as 25 M 31. The frequency out is defined as follows:
The 84021 features a fully integrated PLL and therefore requires no
external components for setting the loop bandwidth. A fundamental
crystal is used as the input to the on-chip oscillator. The output of the
oscillator is fed into the phase detector. A 25MHz crystal provides a
25MHz phase detector reference frequency. The VCO of the PLL
operates over a range of 620MHz to 780MHz. The output of the M
divider is also applied to the phase detector.
FOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed directly to
the M divider and N output divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits and test
bits T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high
or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the LVCMOS output
buffers. The divider provides a 50% output duty cycle.
The programmable features of the 84021 support two input modes to
program the M divider and N output divider. The two input operational
modes are parallel and serial. Figure 1 shows the timing diagram for
each mode. In parallel mode, the nP_LOAD input is initially LOW.
The data on inputs M0 through M8 and N0 and N1 is passed directly
to the M divider and N output divider. On the LOW-to-HIGH transition
of the nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a serial
event occurs. As a result, the M and N bits can be hardwired to set
the M divider and N output divider to a specific default state that will
automatically occur during power-up. The TEST output is LOW when
operating in the parallel input mode. The relationship between the
T1
T0
TEST Output
0
0
LOW
0
1
S_DATA, Shift Register Input
1
0
Output of M Divider
1
1
CMOS FOUT
SERIAL LOADING
S_CLOCK
T1
S_DATA
t
S_LOAD
S
t
T0 *NULL N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
H
t
nP_LOAD
S
PARALLEL LOADING
M[0:8], N[0:1]
M, N
nP_LOAD
t
S
t
H
S_LOAD
Time
*NOTE: The NULL timing slot must be observed.
Figure 1. Parallel & Serial Load Operations
84021 Rev E 9/23/15
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©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
Name
1
M5
Input
Type
Pullup
Description
2, 3, 4,
28, 29,
30, 31, 32
M6, M7, M8,
M0, M1,
M2, M3, M4
Input
Pulldown
5, 6
N0, N1
Input
Pulldown
7
nc
Unused
8, 16
GND
Power
Power supply pins.
9
TEST
Output
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
10
VDD
Power
Core supply pin.
11, 12
OE1, OE0
Input
13
VDDO
Power
Output supply pin.
14, 15
Q1, Q0
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD
input. LVCMOS/LVTTL interface levels.
Determines N output divider value as defined in Table 3C, Function
Table. LVCMOS/LVTTL interface levels.
No connect.
Pullup
Output enable. When logic HIGH, the outputs are enabled (default).
When logic LOW, the outputs are in an Hi-Z state. See Table 3E, OE
Function Table. LVCMOS/LVTTL interface levels.
17
MR
Input
Pulldown
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the outputs to go low. When Logic LOW, the internal
dividers and the outputs are enabled. Assertion of MR does not affect
loaded M, N, and T values. LVCMOS/LVTTL interface levels.
18
S_CLOCK
Input
Pulldown
Clocks in serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
19
S_DATA
Input
Pulldown
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS/LVTTL interface levels.
20
S_LOAD
Input
Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
21
VDDA
Power
22
XTAL_SEL
Input
Pullup
23
TEST_CLK
Input
Pulldown
24,
25
XTAL_OUT
XTAL_IN
Input
26
nP_LOAD
Input
Pulldown
27
VCO_SEL
Input
Pullup
Analog supply pin.
Selects between crystal or test inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS/LVTTL interface levels.
Single-ended test clock input. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the
output.
Parallel load input. Determines when data present at M[8:0] is loaded into
M divider, and when data present at N[1:0] sets the N output divider
value. LVCMOS/LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
84021 Rev E 9/23/15
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©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
CIN
Input Capacitance
CPD
Power Dissipation Capacitance
(per output)
Minimum
Typical
Maximum
Units
4
pF
VDDO = 3.465V
15
pF
VDDO = 2.625V
15
pF
VDDO = 1.89V
20
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
VDDO = 3.3V ± 5%
7
VDDO = 2.5V ± 5%
7
VDDO = 1.8V ± 5%
10
ROUT
Output Impedance
Function Tables
Table 3A. Parallel and Serial Mode Function Table
Inputs
MR
nP_LOAD
M
N
S_LOAD
S_CLOCK
S_DATA
Conditions
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
L
L
Data
Data
X
X
X
Data on M and N inputs passed directly to the M divider and
N output divider. TEST output forced LOW.
L
Data
Data
L
X
X
Data is latched into input registers and remains loaded until
next LOW transition or until a serial event occurs.
L
H
X
X
L
Data
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
L
H
X
X
L
Data
Contents of the shift register are passed to the M divider and
N output divider.
L
H
X
X
L
Data
M divider and N output divider values are latched.
L
H
X
X
L
X
X
Parallel or serial input do not affect shift registers.
L
H
X
X
H
Data
S_DATA passed directly to M divider as it is clocked.
NOTE: L = LOW
H = HIGH
X = Don’t care
= Rising edge transition
= Falling edge transition
84021 Rev E 9/23/15
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©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 3B. Programmable VCO Frequency Function Table(NOTE 1)
256
128
64
32
16
8
4
2
1
M Divide
M8
M7
M6
M5
M4
M3
M2
M1
M0
625
25
0
0
0
0
1
1
0
0
1
•
•
•
•
•
•
•
•
•
•
•
700
28
0
0
0
0
1
1
1
0
0
•
•
•
•
•
•
•
•
•
•
•
775
31
0
0
0
0
1
1
1
1
1
VCO Frequency
(MHz)
NOTE 1: These M divide values and the resulting frequencies correspond to TEST_CLK or crystal frequency of 25MHz.
Table 3C. Programmable Output Divider Function Table (PLL Enabled)
Inputs
Output Frequency (MHz)
N1
N0
N Divider Value
Minimum
Maximum
0
0
3
206.7
260
0
1
4
155
195
1
0
5
124
156
1
1
6
103.3
130
Table 3D. Commonly Used Configuration Function Table
Inputs
Output Frequency (MHz)
Crystal (MHz)
M Divider Value
N Divider Value
Minimum
19.44
32
4
155.52
19.53125
32
4
156.25
25
25
4
156.25
25
25
5
125
25.50
25
3
212.50
25.50
25
4
159.375
25.50
25
6
106.25
38.88
16
4
155.52
Table 3E. Output Enable & Clock Enable Function Table
Control Inputs
Output
OE0
OE1
Q0
Q1
0
0
Hi-Z
Hi-Z
0
1
Hi-Z
Enabled
1
0
Enabled
Hi-Z
1
1
Enabled
Enabled
84021 Rev E 9/23/15
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©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
XTAL_IN
Other Inputs
0V to VDD
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, JA
47.9C/W (0 lfpm)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5%, VDDO = 3.3V±5%, 2.5V±5% or 1.8V±5%, TA = 0°C to 70°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Analog Supply Voltage
VDDO
Test Conditions
Output Supply Voltage
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VDD – 0.36
3.3
VDD
V
3.135
3.3
3.465
V
2.375
2.5
2.625
V
1.71
1.8
1.89
V
IDD
Power Supply Current
110
mA
IDDA
Analog Supply Current
24
mA
IDDO
Output Supply Current
5
mA
84021 Rev E 9/23/15
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©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V±5%, VDDO = 3.3V±5%, 2.5V±5% or 1.8V±5%, TA = 0°C to 70°C
Symbol
Parameter
VIH
Input High Voltage
VIL
IIH
IIL
VOH
VOL
Input
Low Voltage
Input
High Current
Input
Low Current
Test Conditions
Minimum
Typical
Maximum
Units
2
VDD + 0.3
V
OE[0:1], N[0:1], M[0:8],
XTAL_SEL, VCO_SEL,
S_DATA, S_CLOCK,
S_LOAD, nP_LOAD, MR
-0.3
0.8
V
TEST_CLOCK
-0.3
1.3
V
MR, S_CLOCK,
TEST_CLK, S_DATA,
S_LOAD, nP_LOAD,
M[0:4], M[6:8], N0, N1
VDD = VIN = 3.465V
150
µA
M5, OE0, OE1,
XTAL_SEL, VCO_SEL
VDD = VIN = 3.465V
5
µA
MR, S_CLOCK,
TEST_CLK, S_DATA,
S_LOAD, nP_LOAD,
M[0:4], M[6:8], N0, N1
VDD = 3.465V, VIN = 0V
-5
µA
M5, OE0, OE1,
XTAL_SEL, VCO_SEL
VDD = 3.465V, VIN = 0V
-150
µA
VDDO = 3.3V±5%
2.6
V
VDDO = 2.5V±5%
1.8
V
VDDO = 1.8V±5%
VDDO - 0.3
V
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VDDO = 3.3V±5% or 2.5V±5%
0.5
V
VDDO = 1.8V±5%
0.4
V
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section, Output Load Test Circuit diagrams.
Table 5. Input Frequency Characteristics, VDD = 3.3V±5%, VDDO = 3.3V±5%, 2.5V±5% or 1.8V±5%, TA = 0°C to 70°C
Symbol
fIN
Parameter
Input Frequency
Test Conditions
Minimum
Typical
Maximum
Units
TEST_CLK; NOTE 1
14
40
MHz
XTAL; NOTE 1
14
40
MHz
50
MHz
S_CLOCK
NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within the 620MHz to 780MHz
range. Using the minimum input frequency of 14MHz, valid values of M are 45 M 55. Using the maximum input frequency of 40MHz, valid
values of M are 16 M 19.
Table 6. Crystal Characteristics
Parameter
Test Conditions
Minimum
Maximum
Units
40
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance (CO)
7
pF
Mode of Oscillation
Fundamental
Frequency
84021 Rev E 9/23/15
Typical
14
7
©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
AC Electrical Characteristics
Table 7A. AC Characteristics, VDD = VDDO = 3.3V±5%, TA = 0°C to 70°C
Symbol
Parameter
fOUT
Output Frequency
tjit(per)
Test Conditions
Period Jitter, RMS; NOTE 1, 2
tsk(o)
Output Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
tS
tH
Setup Time
Hold Time
Typical
Maximum
Units
260
MHz
N=3
13.5
26.4
ps
N=4
14.7
34.2
ps
N=5
16.7
42.4
ps
103.3
N=6
24.7
40.8
ps
M=40, N=4, 16.667MHz XTAL,
fOUT=166.67MHz
4.5
6.9
ps
M=40, N=5, 16.667MHz XTAL,
fOUT=133.33MHz
4.6
7.8
ps
100
ps
800
ps
20% to 80%
tLOCK
100
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
odc
Minimum
Output Duty Cycle
5
ns
N3
44
56
%
M=40, N=4, 16.667MHz XTAL,
fOUT=166.67MHz
45
55
%
M=40, N=5, 16.667MHz XTAL,
fOUT=133.33MHz
47
53
%
1
ms
PLL Lock Time
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
84021 Rev E 9/23/15
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©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 7B. AC Characteristics, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C to 70°C
Symbol
Parameter
fOUT
Output Frequency
tjit(per)
Test Conditions
Period Jitter, RMS; NOTE 1, 2
tsk(o)
Output Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
tS
tH
Setup Time
Hold Time
Typical
Maximum
Units
260
MHz
N=3
11.4
18.8
ps
N=4
13.3
28.3
ps
N=5
16.0
39.8
ps
103.3
N=6
19.2
32.4
ps
M=40, N=4, 16.667MHz XTAL,
fOUT=166.67MHz
4.3
6.2
ps
M=40, N=5, 16.667MHz XTAL,
fOUT=133.33MHz
4.5
7.7
ps
90
ps
800
ps
20% to 80%
tLOCK
100
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
odc
Minimum
Output Duty Cycle
5
ns
N3
44
56
%
M=40, N=4, 16.667MHz XTAL,
fOUT=166.67MHz
45
55
%
M=40, N=5, 16.667MHz XTAL,
fOUT=133.33MHz
47
53
%
1
ms
PLL Lock Time
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
84021 Rev E 9/23/15
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©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 7C. AC Characteristics, VDD = 3.3V±5%, VDDO = 1.8V±5%, TA = 0°C to 70°C
Symbol
Parameter
fOUT
Output Frequency
tjit(per)
Test Conditions
Period Jitter, RMS; NOTE 1, 2
tsk(o)
Output Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
tS
tH
Setup Time
Hold Time
Typical
Maximum
Units
260
MHz
N=3
9.4
13.2
ps
N=4
10.8
19.6
ps
N=5
12.7
32.5
ps
103.3
N=6
13.4
25.4
ps
M=40, N=4, 16.667MHz XTAL,
fOUT=166.67MHz
5.4
8.3
ps
M=40, N=5, 16.667MHz XTAL,
fOUT=133.33MHz
5.1
8.8
ps
90
ps
800
ps
20% to 80%
tLOCK
100
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
odc
Minimum
Output Duty Cycle
5
ns
N3
40
60
%
M=40, N=4, 16.667MHz XTAL,
fOUT=166.67MHz
44
56
%
M=40, N=5, 16.667MHz XTAL,
fOUT=133.33MHz
48
52
%
1
ms
PLL Lock Time
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
84021 Rev E 9/23/15
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©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Parameter Measurement Information
1.65V±5%
2.05V±5%
1.65V±5%
1.25V±5%
SCOPE
15Ω
VDD,
2.05V±5%
VDDO
VDD
VDDA
Qx
SCOPE
15Ω
VDDO
Qx
VDDA
GND
GND
-1.65V±5%
-1.25V±5%
3.3V Core/2.5V Output Load AC Test Circuit
3.3V Core/3.3V Output Load AC Test Circuit
2.4V±5%
0.9V±5%
VOH
2.4V±5%
VREF
VDD
SCOPE
15Ω
VDDO
VDDA
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Qx
GND
Histogram
Reference Point
Mean Period
(Trigger Edge)
(First edge after trigger)
-0.9V±5%
Period Jitter
3.3V Core/1.8V Output Load AC Test Circuit
V
DDO
Qx
80%
Q[0:1]
V
tF
2
tsk(o)
Output Rise/Fall Time
Output Skew
84021 Rev E 9/23/15
20%
20%
tR
DDO
Qy
80%
2
11
©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Parameter Measurement Information, continued
V
DDO
2
Q[0:1]
t PW
t
odc =
PERIOD
t PW
x 100%
t PERIOD
Output Duty Cycle/Pulse Width/Period
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
Crystal Inputs
TEST Output
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
XTAL_IN to ground.
The unused TEST output can be left floating. There should be no
trace attached.
LVCMOS Outputs
All unused LVCMOS outputs can be left floating. We recommend that
there is no trace attached.
TEST_CLK Input
For applications not requiring the use of the test clock, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the TEST_CLK to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
84021 Rev E 9/23/15
12
©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 2A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
VCC
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100. This can also be
accomplished by removing R1 and making R2 50. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
XTAL_OUT
R1
100
Rs
Ro
C1
Zo = 50 ohms
XTAL_IN
R2
100
Zo = Ro + Rs
.1uf
LVCMOS Driver
Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_IN
.1uf
Zo = 50 ohms
LVPECL Driver
R1
50
R2
50
R3
50
Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface
84021 Rev E 9/23/15
13
©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Layout Guideline
Figure 3 shows a schematic example of the 84021. In this example,
a series termination is shown. Additional LVCMOS termination
approaches are shown in the LVCMOS Termination Application Note.
In this example, an 18pF parallel resonant crystal is used. The C1 =
22pF and C2 = 22pF are approximate values for frequency accuracy.
The C1 and C2 may be slightly adjusted for optimizing frequency
accuracy.
device side of the PCB and the other components can be placed on
the opposite side.
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
supply isolation is required. The 84021 provides separate power
supplies to isolate from coupling into the internal PLL.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
C1
Logic Input Pin Examples
U1
To Logic
Input
pins
1
2
3
4
5
6
7
8
RD2
1K
M5
M6
M7
M8
N0
N1
nc
GND
VDD
X_OUT
T_CLK
nXTAL_SEL
VDDA
S_LOAD
S_DATA
S_CLOCK
MR
24
23
22
21
20
19
18
17
R7
15 - 24
VDDA
C11
0.01u
C16
10u
ICS84021
3.3V
9
10
11
12
13
14
15
16
TEST
VDD
OE1
OE0
VDDO
Q1
Q0
GND
RD1
Not Install
22p
18pF
RU2
Not Install
To Logic
Input
pins
C2
32
31
30
29
28
27
26
25
RU1
1K
22p
Set Logic
Input to '0'
VDD
M4
M3
M2
M1
M0
VCO_SEL
nP_LOAD
X_IN
Set Logic
Input to '1'
VDD
X1
BLM18BB221SN1
1
VDD
2
Ferrite Bead
C17
0.1uF
C18
C14
0.1u
R1
Zo = 50 Ohm
10uF
43
3.3V, 2.5V or 1.8V
BLM18BB221SN2
1
Ferrite Bead
C19
0.1uF
VDDO
2
R2
Zo = 50 Ohm
C20
10uF
C15
0.1u
43
Figure 3. 84021 Application Schematic Example
84021 Rev E 9/23/15
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©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Reliability Information
Table 8. JA vs. Air Flow Table for a 32 Lead LQFP
JA by Velocity
Linear Feet per Minut
0
1
2.5
Single-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
Transistor Count
The transistor count for 84021 is: 4325
84021 Rev E 9/23/15
15
©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Package Outline and Package Dimensions
Package Outline - Y Suffix for 32 Lead LQFP
Table 9. Package Dimensions for 32 Lead LQFP
JEDEC Variation: BBC - HD
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
1.60
A1
0.05
0.10
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
0.20
D&E
9.00 Basic
D1 & E1
7.00 Basic
D2 & E2
5.60 Ref.
e
0.80 Basic
L
0.45
0.60
0.75
0°
7°
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
84021 Rev E 9/23/15
16
©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Ordering Information
Table 10. Ordering Information
Part/Order Number
84021BYLF
84021BYLFT
Marking
ICS84021BYLF
ICS84021BYLF
Package
“Lead-Free” 32 Lead LQFP
“Lead-Free” 32 Lead LQFP
Shipping Packaging
Tray
1000 Tape & Reel
Temperature
0C to 70C
0C to 70C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product
for use in life support devices or critical medical instruments.
84021 Rev E 9/23/15
17
©2015 Integrated Device Technology, Inc
84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Revision History Sheet
Rev
Table
Page
T2
B
C
T6
T10
T4A
T6
T7A - T7C
D
Description of Change
Date
4
12
Pin Characteristics Table - added ROUT rows.
Added Schematic Layout.
Changed XTAL naming convention to XTAL_IN/XTAL_OUT throughout the data sheet.
1/5/04
1
2
7
15
Features Section - added Lead-Free bullet.
Updated Parallel & Serial Load Operations Diagram.
Crystal Characteristics Table - added Drive Level.
Ordering Information Table - added Lead-Free package.
6/9/05
1
Features section - updated RMS period jitter spec in bullet; added RMS phase jitter bullet.
Block Diagram - added pullups/pulldowns to input pins and added “N” in output divider box.
Absolute Maximum Ratings - updated Inputs, VI.
Power Supply DC Characteristics - updated VDDA, IDD, IDDA and IDDO specs.
Crystal Characteristics - deleted Drive Level row.
Updated Period Jitter, Output Rise/Fall Time and Output Duty Cycle specs. Added thermal
note.
Parameter Measurement Information - corrected Output Load AC Test Circuit diagrams to
coincide with 15 VDDA.
Added Recommendations for Unused Input & Output Pins.
Deleted Power Supply Filtering Techniques section, added to schematic layout.
Added Overdriving the XTAL Interface section.
Updated Layout Guideline and diagram.
Ordering Information Table - updated Part/Order Numbers and Marking to revision “B”.
Converted datasheet format.
1/5/11
8/18/11
13
AC Characteristics Table - corrected Period Jitter N = 4 spec, from 32.2ps max. to 34.2ps
max.
Deleted Crystal Input Interface section, added to the schematic.
17
Ordering Information - removed leaded device.
9/23/15
6
6
7
8 - 10
11
T10
12
13
13
14
17
T7A
8
E
E
T10
84021 Rev E 9/23/15
18
©2015 Integrated Device Technology, Inc
Corporate Headquarters
Sales
Tech Support
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com
email: clocks@idt.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or
other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as
those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any
circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected
names, logos and designs, are the property of IDT or their respective third party owners.
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