Clock Generator for Cavium Processors
8413S06
DATA SHEET
General Description
Features
The 8413S06 is a PLL-based clock generator specifically designed
for Cavium Networks Octeon II processors. This high performance
device is optimized to generate the processor core reference clock,
sRIO, XAUI, SGMII SerDes reference clocks and the clocks for both
the Gigabit Ethernet MAC and PHY. The clock generator offers ultra
low-jitter, low-skew clock outputs, and edge rates that easily meet
the input requirements for the CN63XX and CN68XX series of
processors. The output frequencies are generated from a 25MHz
external input source or an external 25MHz parallel resonant crystal.
The industrial temperature range of the 8413S06 supports
telecommunication, networking, and storage requirements.
•
Six selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz
clocks for sRIO, XAUI, SGMII and HCSL interface levels
•
•
One 125MHz RGMII clock (QG), LVCMOS/LVTTL interface levels
•
Two 25MHz QREF clocks, LVCMOS/LVTTL interface levels,
15 output impedance
•
Selectable external crystal or differential (single-ended) input
source
•
Crystal oscillator interface designed for 25MHz, parallel
resonant crystal
•
Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,
LVHSTL, HCSL input levels
•
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
Applications
•
Full 3.3V or mixed 3.3V core/2.5V output supply modes, (RGMII
output and QREF outputs)
•
•
•
•
•
•
•
•
•
•
•
•
Full 3.3V output supply mode, (HCSL and core clock outputs)
Systems using Cavium Processors
CPE Gateway Design
Home Media Servers
One 50MHz processor core clock (QF), LVCMOS/LVTTL
interface levels
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
802.11n AP or Gateway
GND
IREF
VDD
nMR
VDDO_F
QF
VDDO_G
QG
OE_G
Web Servers and Exchange Servers
OE_REF
Wired and Wireless Network Security
QREF0
Wireless Soho and SME VPN Solutions
QREF1
Pin Assignment
48 47 46 45 44 43 42 41 40 39 38 37
36
1
OE_C
FSEL_A0
2
35
nQC1
FSEL_A1
3
34
QC1
FSEL_B0
4
33
nQC0
FSEL_B1
5
32
QC0
FSEL_C0
6
8413S06
31
VDDO_C
30
VDDO_B
FSEL_C1
7
VDDA
8
29
nQB1
XTAL_IN
9
28
QB1
XTAL_OUT
10
27
nQB0
REF_SEL
11
26
QB0
OE_B
VDD
GND
nQA1
QA1
nQA0
QA0
VDDO_A
OE_A
nCLK
CLK
25
12
13 14 15 16 17 18 19 20 21 22 23 24
VDD
GND
PLL_SEL
Soho SME Gateway
VDDO_QREF
Soho Secure Gateway
48-pin, 7mm x 7mm VFQFN Package
REVISION C 03/06/15
1
©2015 INTEGRATED DEVICE TECHNOLOGY, INC.
8413S06 DATA SHEET
Block Diagram
FSELA [0:1]
Pulldown
2
FSELB [0:1]
Pulldown
2
FSELC [0:1]
Pulldown
2
PLL_SEL
Pullup
REF_SEL
Pullup
CLK
nCLK
Clock
Output
Control
Logic
00 = 100MHz
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
00 = 100MHz
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
Pulldown
2
2
Pullup
0
XTAL_IN
OSC
1
XTAL_OUT
1
PLL
IREF
00 = 100MHz
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
2
2
Pullup
QB0, QB1
nQB0, nQB1
OE_B
2
2
Pullup
nQA0, nQA1
OE_A
0
PU/PD
QA0, QA1
QC0, QC1
nQC0, nQC1
OE_C
50MHz
QF
125MHz
QG
Pullup
OE_G
QREF0
QREF1
Pullup
nMR
Pullup
OE_REF
NOTE: PU/PD denotes Pullup/Pulldown resistors
CLOCK GENERATOR FOR CAVIUM PROCESSORS
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REVISION C 03/06/15
8413S06 DATA SHEET
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
1, 12, 23
GND
Power
2,
3
FSEL_A0.
FSEL_A1
Input
Pulldown
Selects the QAx, nQAx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
4,
5
FSEL_B0,
FSEL_B1
Input
Pulldown
Selects the QBx, nQBx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
6,
7
FSEL_C0,
FSEL_C1
Input
Pulldown
Selects the QCx, nQCx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
8
VDDA
Power
Analog supply pin.
9,
10
XTAL_IN,
XTAL_OUT
Input
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input.
11
REF_SEL
Input
13, 24, 38
VDD
Power
14
PLL_SEL
Input
Pullup
15
CLK
Input
Pulldown
Non-inverting differential clock input.
16
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. Internal resistor bias to VDD/2.
17
OE_A
Input
Pullup
Active HIGH output enable for Bank A outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
18
VDDO_A
Power
Bank A (HCSL) output supply pin. 3.3 V supply.
19, 20
QA0, nQA0
Output
Differential output pair. HCSL interface levels.
21, 22
QA1, nQA1
Output
Differential output pair. HCSL interface levels.
25
OE_B
Input
26, 27
QB0, nQB0
Output
Differential output pair. HCSL interface levels.
28, 29
QB1, nQB1
Output
Differential output pair. HCSL interface levels.
30
VDDO_B
Power
Bank B (HCSL) output supply pin. 3.3V supply.
31
VDDO_C
Power
Bank C (HCSL) output and HCSL reference circuit supply pin. Must be
connected to 3.3V to use any of the HCSL outputs.
32, 33
QC0, nQC0
Output
Differential output pair. HCSL interface levels.
34, 35
QC1, nQC1
Output
Differential output pair. HCSL interface levels.
36
OE_C
Input
37
IREF
Input
39
nMR
Input
40
VDDO_F
Power
QF output supply pin. 3.3V supply.
41
QF
Output
Single-ended output. 3.3V LVCMOS/LVTTL interface levels.
REVISION C 03/06/15
Type
Description
Power supply ground.
Pullup
Input source control pin. See Table 3C. LVCMOS/LVTTL interface levels.
Core supply pins.
Pullup
Pullup
PLL bypass control pin. See Table 3B. LVCMOS/LVTTL interface levels.
Active HIGH output enable for Bank B outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
Active HIGH output enable for Bank C outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
External fixed precision resistor (475) from this pin to ground provides a
reference current used for differential current-mode QAx:QCx, nQAx:QCx
outputs.
Pullup
Active LOW Master Reset. When logic LOW, all outputs are reset causing
the true outputs Qx to go low and the inverted outputs nQx to go high. When
logic HIGH, all outputs are enabled. LVCMOS/LVTTL interface levels.
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CLOCK GENERATOR FOR CAVIUM PROCESSORS
8413S06 DATA SHEET
Number
Name
Type
Description
42
VDDO_G
Power
QG output supply pin. 3.3V or 2.5V supply.
43
QG
Output
Single-ended output. 3.3V or 2.5V LVCMOS/LVTTL interface levels.
44
OE_G
Input
Pullup
Active HIGH output enable for Bank G output. See Table 3E.
LVCMOS/LVTTL interface levels.
45
OE_REF
Input
Pullup
Active HIGH output enable for QREF[0:1] outputs. See Table 3F.
LVCMOS/LVTTL interface levels.
46,
47
QREF0,
QREF1
Output
Single-ended output QREFx outputs. 3.3V or 2.5V LVCMOS/LVTTL
interface levels.
48
VDDO_QREF
Power
QREF output supply pin. 3.3V or 2.5V supply.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input
Capacitance
RPULLUP
Test Conditions
Minimum
Typical
Maximum
Units
CLK, nCLK
2
pF
Control Pins
4
pF
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
ROUT
Output
Impedance
VDDO_F = VDDO_G = VDDO_QREF =
3.3V
15
VDDO_QREF, VDDO_G = 2.5V
21
QF, QG,
QREF[0:1]
QG, QREF[0:1]
CLOCK GENERATOR FOR CAVIUM PROCESSORS
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REVISION C 03/06/15
8413S06 DATA SHEET
Function Tables
Table 3A. FSEL_X Control Input Function Table
Table 3D. OE_[A:C] Control Input Function Table
Input
Output Frequency
Input
Outputs
FSEL_X[0:1]
QAx:QCx, nQAx:nQCx
OE_[A:C]
QAx:QCx, nQAx:QCx
00 (default)
100MHz
0
High-Impedance
01
125MHz
1 (default)
Enabled
10
156.25MHz
11
312.50MHz
Table 3E. OE_G Control Input Function Table
NOTE: FSEL_X denotes FSEL_A, _B, _C.
NOTE: Any two outputs operated at the same frequency will be
synchronous.
Table 3B. PLL_SEL Control Input Function Table
Input
Outputs
OE_G
QG
0
High-Impedance
1 (default)
Enabled
Input
PLL_SEL
Operation
0
PLL Bypass
Input
Output
1 (default)
PLL Mode
OE_REF
QREF[0:1]
0
High-Impedance
1 (default)
Enabled
Table 3F. OE_REF Control Input Function Table
Table 3C. REF_SEL Control Input Function Table
Input
REF_SEL
Clock Source
0
CLK, nCLK
1 (default)
XTAL_IN, XTAL_OUT
REVISION C 03/06/15
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CLOCK GENERATOR FOR CAVIUM PROCESSORS
8413S06 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
XTAL_IN
Other Inputs
0V to VDD
-0.5V to VDD + 0.5V
Outputs, VO (LVCMOS, HCSL)
-0.5V to VDDO_X + 0.5V
Package Thermal Impedance, JA
30.5°C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO_X = 3.3V ± 5% or
VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VDD – 0.16
3.3
VDD
V
VDDO_X
Output Supply Voltage
3.135
3.3
3.465
V
VDDO_G,
VDDO_QREF
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
86
mA
IDDA
Analog Supply Current
16
mA
IDDO_A +
IDDO_B + IDDO_C
HCSL 3.3V Output Supply
Current
No Load, CLK selected
17
mA
IDDO_F + IDDO_G+
IDDO_QREF
LVCMOS 3.3V Output Supply
Current
No Load, CLK selected
30
mA
IDDO_G+
IDDO_QREF
LVCMOS 2.5V Output Supply
Current
No Load, CLK selected
15
mA
,
NOTE: VDDO_X denotes VDDO_(A:C), VDDO_F, VDDO_G, VDDO_QREF.
CLOCK GENERATOR FOR CAVIUM PROCESSORS
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REVISION C 03/06/15
8413S06 DATA SHEET
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
VOH
VOL
Input
High
Current
Input
Low
Current
Test Conditions
Minimum
Typical
Maximum
Units
2.2
VDD + 0.3
V
-0.3
0.8
V
FSEL_A[0:1],
FSEL_B[0:1], FSEL_C[0:1]
VDD = VIN = 3.465V
150
µA
REF_SEL, PLL_SEL,
OE_REF, OE_A, OE_B,
OE_C, OE_G, nMR
VDD = VIN = 3.465V
10
uA
FSEL_A[0:1],
FSEL_B[0:1], FSEL_C[0:1]
VDD = 3.465V, VIN = 0V
-10
µA
REF_SEL, PLL_SEL,
OE_REF, OE_A, OE_B,
OE_C, OE_G, nMR
VDD = 3.465V, VIN = 0V
-150
uA
IOH = -12mA,
VDDO_F, VDDO_G, VDDO_QREF
= 3.465V
2.6
V
IOH = -12mA,
VDDO_G, VDDO_QREF =
2.625V
1.8
V
Output High Voltage
IOL = 12mA,
VDDO_F, VDDO_G, VDDO_QREF
= 3.465V or
VDDO_G, VDDO_QREF =
2.625V
Output Low Voltage
0.6
V
Maximum
Units
150
µA
NOTE: VDDO_X denotes VDDO_F, VDDO_G, VDDO_QREF.
Table 4C. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage; NOTE 1
0.15
1.3
V
VCMR
Common Mode Input Voltage;
NOTE 1, 2
0.5
VDD – 0.85
V
Maximum
Units
CLK, nCLK
Minimum
Typical
VDD = VIN = 3.465V
CLK
VDD = 3.465V, VIN = 0V
-10
µA
nCLK
VDD = 3.465V, VIN = 0V
-150
µA
NOTE 1: VIL should not be less than -0.3V.
NOTE 2. Common mode voltage is defined as VIH.
Table 5. Crystal Characteristics
Parameter
Test Conditions
Mode of Oscillation
Minimum
Typical
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
NOTE: Characterized using an 18pF parallel resonant crystal.
REVISION C 03/06/15
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CLOCK GENERATOR FOR CAVIUM PROCESSORS
8413S06 DATA SHEET
Table 6. Input Frequency Characteristics, VDD = 3.3V ± 5%, VDDO_[A:D] = VDDO_QF = VDDO_QG = 3.3V ± 5%; or
VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
FIN
Input
Frequency
Test Conditions
Minimum
Typical
Maximum
Units
CLK, nCLK
25
MHz
XTAL_IN, XTAL_OUT
25
MHz
AC Electrical Characteristics
Table 7A. AC Characteristics, VDD = VDDO_[A:C] = VDDO_F = 3.3V ± 5%; or
VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
RJ
DJ
tjit(Ø)
Parameter
Output Configurations
Outputs
Random Jitter;
NOTE 1
QAx, nQAx = 100MHz,
QBx, nQBx = 125MHz,
QCx, nQCx = 156.25MHz,
QF = 50MHz,
QG = 125MHz,
QREF0 = QREF1 = Enabled
QG
4
6
ps
QAx, nQAx = 100MHz,
QBx, nQBx = 125MHz,
QCx, nQCx = 156.25MHz,
QF = 50MHz,
QG = 125MHz,
QREF0 = QREF1 = Enabled
QAx, nQAx
26
55
ps
QBx, nQBx
43
90
ps
QCx, nQCx
48
80
ps
Deterministic Jitter;
NOTE 1
RMS Phase Jitter,
(Random)
Integration Range:
(12kHz to 20MHz)
QAx, nQAx = 100MHz,
QBx, nQBx = 125MHz,
QCx, nQCx = 156.25MHz,
QF = 50MHz,
QG = 125MHz,
QREF0 = QREF1 = Enabled
Minimum
Typical
Maximum
Units
QAx, nQAx
3
4
ps
QBx, nQBx
3
4
ps
QCx, nQCx
3
5
ps
QF
3
4
ps
QF
58
134
ps
QG
147
246
ps
QAx, nQAx
0.66
1.00
ps
QBx, nQBx
0.65
0.98
ps
QCx, nQCx
0.64
0.97
ps
QF
0.87
1.30
ps
QG
0.77
1.19
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Refer to Applications Section for peak-to-peak jitter calculations.
NOTE 1: Measured using a Wavecrest SIA-3000.
CLOCK GENERATOR FOR CAVIUM PROCESSORS
8
REVISION C 03/06/15
8413S06 DATA SHEET
Table 7B. AC Characteristics, VDD = VDDO_[A:C] = VDDO_F = 3.3V ± 5%; or
VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
RJ
DJ
tjit(Ø)
Parameter
Output Configurations
Random Jitter;
NOTE 1
QAx, nQAx; QBx, nQBx = 100MHz,
QCx, nQCx = 156.25MHz,
QF = 50MHz,
QG = 125MHz,
QREF0 = QREF1 = Enabled
Deterministic Jitter;
NOTE 1
RMS Phase Jitter,
(Random)
Integration Range:
(12kHz to 20MHz)
Outputs
Minimum
Typical
Maximum
Units
QAx, nQAx
3
4
ps
QBx, nQBx
3
4
ps
QCx, nQCx
3
5
ps
QF
3
4
ps
QG
3
4
ps
QAx, nQAx = 100MHz,
QBx, nQBx = 100MHz,
QCx, nQCx = 156.25MHz,
QF = 50MHz,
QG = 125MHz,
QREF0 = QREF1 = Enabled
QAx, nQAx
33
65
ps
QBx, nQBx
27
60
ps
QCx, nQCx
62
100
ps
QF
88
182
ps
QG
175
310
ps
QAx, nQAx = 100MHz,
QBx, nQBx = 100MHz,
QCx, nQCx = 156.25MHz,
QF = 50MHz,
QG = 125MHz,
QREF0 = QREF1 = Enabled
QAx, nQAx
0.65
0.95
ps
QBx, nQBx
0.64
0.96
ps
QCx, nQCx
0.63
0.97
ps
QF
0.86
1.31
ps
QG
0.78
1.22
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Refer to Applications Section for peak-to-peak jitter calculations.
NOTE 1: Measured using a Wavecrest SIA-3000.
REVISION C 03/06/15
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CLOCK GENERATOR FOR CAVIUM PROCESSORS
8413S06 DATA SHEET
Table 7C. AC Characteristics, VDD = VDDO_[A:C] = VDDO_F = 3.3V ± 5%; or VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 2.5V ± 5%,
TA = -40°C to 85°C
Symbol
Parameter
VRB
Ring-Back Voltage Margin;
NOTE 1, 2
Q[Ax:Cx],
nQ[Ax:Cx]
-100
tSTABLE
Time before VRB is
allowed; NOTE 1, 2
Q[Ax:Cx],
nQ[Ax:Cx]
500
VMAX
Absolute Max Output
Voltage; NOTE 3, 4
Q[Ax:Cx],
nQ[Ax:Cx]
VMIN
Absolute Min Output
Voltage; NOTE 3, 5
Q[Ax:Cx],
nQ[Ax:Cx]
-300
VCROSS
Absolute Crossing Voltage; Q[Ax:Cx],
NOTE 3, 6, 7
nQ[Ax:Cx]
250
Total Variation of VCROSS
VCROSS over All Edges;
NOTE 3, 6, 8
Test Conditions
Minimum
Typical
Maximum
Units
100
mV
ps
1150
mV
mV
Q[Ax:Cx],
nQ[Ax:Cx]
550
mV
140
mV
tSLEW+
Rising Edge Rate;
NOTE 1, 9
Q[Ax:Cx],
nQ[Ax:Cx]
0.6
5.5
V/ns
tSLEW-
Falling Edge Rate;
NOTE 1, 9
Q[Ax:Cx],
nQ[Ax:Cx]
0.6
5.5
V/ns
odc
Output Duty Cycle
Q[Ax:Cx],
nQ[Ax:Cx]
48
52
%
tjit(Ø)
RMS Phase Jitter,
(Random)
QREF[0:1]
0.98
ps
tR /tF
odc
Output Rise/Fall Time
Output Duty Cycle
25MHz, Integration Range:
(10kHz to 5MHz)
0.69
QF
20% to 80%
400
1400
ps
QG
20% to 80%
400
1400
ps
QREF[0:1]
20% to 80%
300
1400
ps
QF
measured at VDDO_F/2
48
52
%
QG
measured at VDDO_G/2
45
55
%
measured at VDDO_QREF/2
45
55
%
QREF[0:1]
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measurement taken from differential waveform.
NOTE 2: tSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB ±100mV range. See Parameter Measurement Information Section.
NOTE 3: Measurement taken from single-ended waveform.
NOTE 4: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 5: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 6: Measured at the crossing point where the instantaneous voltage value of the rising edge of Q[Ax:Cx] equals the falling edge of
nQ[Ax:Cx].
NOTE 7: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement.
NOTE 8: Defined as the total variation of all crossing voltages of rising Q[Ax:Cx] and falling nQ[Ax:Cx]. This is the maximum allowed variance
in Vcross for any particular system.
NOTE 9: Measured from -150mV to +150mV on the differential waveform (derived from Q[Ax:Cx] minus nQ[Ax:Cx]). The signal must be
monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero
crossing.
CLOCK GENERATOR FOR CAVIUM PROCESSORS
10
REVISION C 03/06/15
8413S06 DATA SHEET
Typical Phase Noise at 156.25MHz
Noise Power
dBc
Hz
RMS Phase Jitter at 156.25MHz,
Integration range (12kHz - 20MHz) = 0.64ps (typical)
Offset Frequency (Hz)
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CLOCK GENERATOR FOR CAVIUM PROCESSORS
8413S06 DATA SHEET
Parameter Measurement Information
2.05V±5%
1.65V±5%
1.25V±5%
1.65V±5%
2.05V±5%
VDD,
VDDO_[F:G],
VDDO_QREFx
SCOPE
VDD
VDDA
VDDO_G,
VDDO_QREFx
VDDA
Qx
GND
SCOPE
2
Qx
GND
-1.65V±5%
-1.25V±5%
3.3V Core/2.5V LVCMOS Output Load Test Circuit
3.3V Core/3.3V LVCMOS Output Load Test Circuit
3.3V±5%
3.3V±5%
3.3V±5%
3.3V±5%
VDD,
VDD,
VDDO_[A:C]
VDDO_[A:C]
VDDA
VDDA
This load condition is used for IDD and tjit(Ø) measurements.
This load condition is used for VMAX, VMIN, VRB, tSTABLE, VCROSS,
VCROSS and Rise/Fall Edge Rate measurements.
3.3V Core/3.3V HCSL Output Load Test Circuit
3.3V Core/3.3V HCSL Output Load Test Circuit
VDD
nCLK
V
PP
Cross Points
V
CMR
CLK
GND
Differential Input Level
CLOCK GENERATOR FOR CAVIUM PROCESSORS
RMS Phase Jitter
12
REVISION C 03/06/15
8413S06 DATA SHEET
Parameter Measurement Information, continued
QF, QG,
QREF[0:1]
80%
80%
tR
tF
20%
20%
QF, QG,
QREF[0:1]
LVCMOS Output Duty Cycle/Pulse Width
LVCMOS Output Rise/Fall Time
Differential Measurement Points for Rise/Fall Time Edge
Rate
Single-ended Measurement Points for Absolute Cross
Point/Swing
Single-ended Measurement Points for Delta Cross Point
Differential Measurement Points for Ringback
REVISION C 03/06/15
13
CLOCK GENERATOR FOR CAVIUM PROCESSORS
8413S06 DATA SHEET
Parameter Measurement Information, continued
Differential Measurement Points for Duty Cycle/Period
CLOCK GENERATOR FOR CAVIUM PROCESSORS
14
REVISION C 03/06/15
8413S06 DATA SHEET
Peak-to-Peak Jitter Calculations
A standard deviation of a statistical population or data set is the
square root of its variance. A standard deviation is used to calculate
the probability of an anomaly or to predict a failure. Many times, the
term "root mean square" (RMS) is used synonymously for standard
deviation. This is accurate when referring to the square root of the
mean squared deviation of a signal from a given baseline and when
the data set contains a Gaussian distribution with no deterministic
components. A low standard deviation indicates that the data set is
close to the mean with little variation. A large standard deviation
indicates that the data set is spread out and has a large variation
from the mean.
Jitter (Peak to Peak) = RMS Multiplier x RMS (typical)
If the data set contains deterministic components, then the Random
Jitter (RJ) and Deterministic Jitter (DJ) must be separated and analyzed separately. RJ, also know as Gaussian Jitter, is not bounded
and the peak-to-peak will continue to get larger as the sample size
increases. Alternatively, peak-to-peak value of DJ is bounded an can
easily be observed and predicted. Therefore, the peak-to-peak jitter
for the random component must be added to the deterministic component. this is call Total Jitter (TJ).
Total Jitter (Peak to Peak) = [RMS Multiplier x Random Jitter
(RJ)] + Deterministic Jitter (DJ)
A standard deviation is required when calculating peak-to-peak jitter.
Since true peak-to-peak jitter is random and unbounded, it is important to always associate a bit error ratio (BER) when specifying a
peak-to-peak jitter limit. Without it, the specification does not have a
boundary and will continue get larger with sample size. Given that a
BER is application specific, many frequency timing devices specify
jitter as an RMS. This allows the peak-to-peak jitter to be calculated
for the specific application and BER requirement. Because a standard deviation is the variation from the mean of the data set, it is
important to always calculate the peak-to-peak jitter using the typical
RMS value.
This calculation is not specific to one type of jitter classification. It
can be used to calculate BER on various types of RMS jitter. It is
important that the user understands their jitter requirement to ensure
they are calculating the correct BER for their jitter requirement.
The table shows the BER with its appropriate RMS Multiplier. There
are two columns for the RMS multiplier, one should be used if your
signal is data and the other should be used if the signal is a repetitive clock signal. The difference between the two is the data transition density (DTD). The DTD is the number of rising or falling
transitions divided by the total number of bits. For a clock signal,
they are equal, hence the DTD is 1. For Data, on average, most
common encoding standards have a.5 DTD.
Once the BER is chosen, there are two circumstances to consider.
Is the data set purely Gaussian or does it contains any deterministic
component? If it is Gaussian, then the peak to peak jitter can be calculated by simply multiplying the RMS multiplier with the typical
RMS specification. For example, if a 10-12 BER is required for a
clock signal, multiply 14.260 times the typical jitter specification.
REVISION C 03/06/15
15
BER
RMS Multiplier Data,
“DTD = 0.5”
RMS Multiplier Clock,
“DTD = 1.0”
10-3
6.180
6.582
10-4
7.438
7.782
10-5
8.530
8.834
10-6
9.507
9.784
10-7
10.399
10.654
10-8
11.224
11.462
10-9
11.996
12.218
10-10
12.723
12.934
10-11
13.412
13.614
10-12
14.069
14.260
10-13
14.698
14.882
10-14
15.301
15.478
10-15
15.883
16.028
CLOCK GENERATOR FOR CAVIUM PROCESSORS
8413S06 DATA SHEET
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1 = VDD/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1 in the center of the input voltage swing.
For example, if the input clock swing is 3.3V and VDD = 3.3V, R1 and
R2 value should be adjusted to set V1 at 1.25V. The values below are
for when both the single ended swing and VDD are at the same
voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
CLOCK GENERATOR FOR CAVIUM PROCESSORS
16
REVISION C 03/06/15
8413S06 DATA SHEET
3.3V Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both signals must meet the VPP and VCMR input
requirements. Figures 2A to 2E show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
vendor of the driver component to confirm the driver termination
requirements. For example, in Figure 2A, the input termination
applies for IDT open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
LVHSTL
IDT
LVHSTL Driver
R1
50Ω
R2
50Ω
Differential
Input
Figure 2A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
3.3V
*R3
CLK
nCLK
HCSL
Figure 2C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Differential
Input
*R4
Figure 2D. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 2E. CLK/nCLK Input Driven by a 3.3V LVDS Driver
REVISION C 03/06/15
17
CLOCK GENERATOR FOR CAVIUM PROCESSORS
8413S06 DATA SHEET
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by one
side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 3A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
VCC
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 3B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
XTAL_OUT
R1
100
Ro
Rs
C1
Zo = 50 ohms
XTAL_IN
R2
100
Zo = Ro + Rs
.1uf
LVCMOS Driver
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_IN
.1uf
Zo = 50 ohms
LVPECL Driver
R1
50
R2
50
R3
50
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
CLOCK GENERATOR FOR CAVIUM PROCESSORS
18
REVISION C 03/06/15
8413S06 DATA SHEET
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVCMOS Outputs
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
All unused LVCMOS outputs can be left floating. There should be no
trace attached.
Differential Outputs
Crystal Inputs
All unused differential output pairs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or terminated.
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
XTAL_IN to ground.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
REVISION C 03/06/15
19
CLOCK GENERATOR FOR CAVIUM PROCESSORS
8413S06 DATA SHEET
Recommended Termination
Figure 4A is the recommended source termination for applications
where the driver and receiver will be on a separate PCBs. This
termination is the standard for PCI Express™and HCSL output types.
0.5" Max
Rs
All traces should be 50Ω impedance single-ended or 100Ω
differential.
0-0.2"
22 to 33 +/-5%
0.5 - 3.5"
1-14"
L1
L2
L4
L1
L2
L4
L5
L5
PCI Expres s
PCI Expres s
Connector
Driver
0-0.2"
L3
L3
PCI Expres s
Add-in Card
49.9 +/- 5%
Rt
Figure 4A. Recommended Source Termination (where the driver and receiver will be on separate PCBs)
Figure 4B is the recommended termination for applications where a
point-to-point connection can be used. A point-to-point connection
contains both the driver and the receiver on the same PCB. With a
matched termination at the receiver, transmission-line reflections will
0.5" Max
Rs
0 to 33
L1
be minimized. In addition, a series resistor (Rs) at the driver offers
flexibility and can help dampen unwanted reflections. The optional
resistor can range from 0Ω to 33Ω. All traces should be 50Ω
impedance single-ended or 100Ω differential.
0-18"
0-0.2"
L2
L3
L2
L3
0 to 33
L1
PCI Expres s
Driver
49.9 +/- 5%
Rt
Figure 4B. Recommended Termination (where a point-to-point connection can be used)
CLOCK GENERATOR FOR CAVIUM PROCESSORS
20
REVISION C 03/06/15
8413S06 DATA SHEET
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 5. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
REVISION C 03/06/15
21
CLOCK GENERATOR FOR CAVIUM PROCESSORS
8413S06 DATA SHEET
Application Schematic
Figure 6 (next page) shows an example of 8413S06 application
schematic. In this example, the device is operated at VDD = VDDA =
VDDO_A = VDDO_B = VDDO_C = VDDO_F = VDDO_G = 3.3V and
VDDO_QREF = 3.3V. The schematic example focuses on functional
connections and is not configuration specific. Refer to the pin
description and functional tables in the datasheet to ensure that the
logic control inputs are properly set.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 8413S06 provides separate
power supplies to isolate any high switching noise from coupling into
the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uf capacitor in each power pin filter should be placed on the device
side. The other components can be on the opposite side of the PCB.
An 18pF parallel resonant 25MHz crystal is used. For this device, the
crystal load capacitors are required for proper operation. The load
capacitance, C1 = 22pF and C2 = 10pF, are recommended for
frequency accuracy. Depending on the variation of the parasitic stray
capacity of the printed circuit board traces between the crystal and
the XTAL_IN and XTAL_OUT pins, the values of C1 and C2 might
require a slight adjustment to optimize the frequency accuracy.
Crystals with other load capacitance specifications can be used, but
this will require adjusting C1 and C2.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
The ePAD provides a low thermal impedance connection between
the internal device and the PCB. It also provides an electrical
connection to the die and must be connected to ground.
CLOCK GENERATOR FOR CAVIUM PROCESSORS
22
REVISION C 03/06/15
8413S06 DATA SHEET
3. 3V
FB 1
VD D
2
1
B L M1 8BB 22 1SN 1
C 19
0. 1u F
C6
0 . 1u F
C4
1 0 uF
R5
C3
0 . 1 uF
10
OE _A
OE _B
OE _C
OE _D
O E _ R EF
17
25
36
44
45
R E F_S EL
P LL _S E L
11
14
F SE L_ A0
F SE L_ A1
F SE L_ B0
F SE L_ B1
F SE L_ C 0
F SE L_ C 1
2
3
4
5
6
7
8
C7
0. 1 u F
VDDA
38
V DD
24
VD D
U 21
V DD
C 20
0 . 1 uF
13
VDDA
C5
10 uF
Pl ace eac h 0.1u F bypas s cap
di rectly adjace nt to i ts
co rrespon ding V DD, VDD A or
VD DO_x pi n.
VDDO
OE _A
V D D O_ QR E F
OE _B
OE _C
OE _G
VD D O_ A
O E _ R EF
48
18
C 16
0. 1u F
30
39
nMR
31
40
C 13
0 . 1 uF
VD D O_ F
V D D O_ G
C 10
0. 1u F
42
QA0
n QA0
15
C LK
16
QA1
n QA1
R3
18
QB1
n QB1
XTAL_ I N
9
XTA L_ IN
QC 0
n QC 0
10
X1
2 5MH z
XTA L_ OU T
XTAL_ OU T
Q A0
nQA 0
21
22
Q A1
nQA 1
26
27
Q B0
nQB 0
28
29
Q B1
nQB 1
32
33
Q C0
nQC 0
34
35
Q C1
nQC 1
C9
10 uF
R 10
+
33
QC 1
n QC 1
QR E F0
-
R4
50
H C SL _R e c e iv er
For PCI Express Add-In Card
43
R6
47 5
C8
0 . 1 uF
33
R 11
50
R8
33
HCSL Termination
R7
33
Z o = 50
+
Optional
QG
IRE F
1
BL M 18 BB 22 1 SN 1
R 13
41
37
2
Zo = 5 0
QF
C2
20 pF
VD D O
Zo = 5 0
QB0
n QB0
2.5 V PE C L D riv er
F
p
8
1
19
20
nC L K
R 2 50
3.3V
F B2
C 21
0. 1 u F
nMR
R 1 50
C1
22 p F
C 14
0 . 1 uF
V D D O_ C
F SE L_ A0
F SE L_ A1
F SE L_ B0
F SE L_ B1
F SE L_ C 0
F SE L_ C 1
Z o = 50 Ohm
Z o = 50 Ohm
C 15
0. 1u F
VD D O_ B
R E F_S EL
P LL _SE L
Z o = 50
-
46
H C SL _R e c e iv er
R 12
50
47
QR E F1
R9
50
I C S 84 13 S0 6
49
1
12
23
GN D
GN D
G ND
eP AD
For PCI Express Point-to-Point Connection
R 14
QF
Zo = 5 0
Logic Control Input Examples
VD D
Set Logic
Input to '1'
VD D
Set Logic
Input to '0'
33
QG
LV C MOS R e c e iv er
QR EF 0
RU1
1K
RU2
N ot I ns t a ll
To Logic
Input
pins
RD1
N ot I n s t all
To Logic
Input
pins
R 15
QR EF 1
Zo = 5 0
33
RD2
1K
L VC MO S R e c e iv er
Figure 6. 8413S06 Schematic Example
REVISION C 03/06/15
23
CLOCK GENERATOR FOR CAVIUM PROCESSORS
8413S06 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 8413S06. Equations and example calculations are also
provided.
1.
Power Dissipation.
The total power dissipation for the8413S06 is the sum of the core power plus the analog power plus the power dissipated due to the load.
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.
•
Power (core)MAX = VDD_MAX * (IDD + IDDA)= 3.465V * (86mA + 16mA) = 353.43mW
•
Power (HCSL)MAX = (3.465V – 17mA * 50) 17mA = 44.5mW per output
•
Total Power (HCSL)MAX = 44.5mW * 6 = 267mW
LVCMOS Driver Power Dissipation
•
Output Impedance ROUT Power Dissipation due to Loading 50 to VDD/2
Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 15)] = 26.7mA
•
Power Dissipation on the ROUT per LVCMOS output
Power (LVCMOS) = ROUT * (IOUT)2 = 15 * (26.7mA)2 = 10.7mW per output
•
Total Power Dissipation on the ROUT
Total Power (ROUT) = 10.7mW * 4 = 42.8mW
Total Power Dissipation
•
Total Power
= Power (core) + Total Power (HCSL) + Total Power (ROUT)
= 353.43mW + 267mW + 42.8mW
= 663.23mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 30.5°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.663W * 30.5°C/W = 105.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 8. Thermal Resistance JA for 48 Lead VFQFN, Forced Convection
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
CLOCK GENERATOR FOR CAVIUM PROCESSORS
0
1
2.5
30.5°C/W
26.7°C/W
23.9°C/W
24
REVISION C 03/06/15
8413S06 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 7.
VDD
IOUT = 17mA
VOUT
RREF =
475 ± 1%
RL
50
IC
Figure 7. HCSL Driver Circuit and Termination
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,
use the following equations which assume a 50 load to ground.
The highest power dissipation occurs when VDD_MAX.
Power = (VDD_MAX – VOUT) * IOUT
since VOUT = IOUT * RL
Power
= (VDD_MAX – IOUT * RL) * IOUT
= (3.465V – 17mA * 50) * 17mA
Total Power Dissipation per output pair = 44.5mW
REVISION C 03/06/15
25
CLOCK GENERATOR FOR CAVIUM PROCESSORS
8413S06 DATA SHEET
Reliability Information
Table 9. JA vs. Air Flow Table for a 48 Lead VFQFN
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
30.5°C/W
26.7°C/W
23.9°C/W
Transistor Count
The transistor count for 8413S06 is: 10,307
CLOCK GENERATOR FOR CAVIUM PROCESSORS
26
REVISION C 03/06/15
8413S06 DATA SHEET
Package Outline and Package Dimensions
Package Outline - K Suffix for 48 Lead VFQFN
Bottom View w/Type A ID
2
1
CHAMFER
4
N N-1
Bottom View w/Type C ID
2
1
RADIUS
4
N N-1
There are 2 methods of indicating pin 1 corner
at the back of the VFQFN package:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
Table 10. PackageDimensions for 48 Lead VFQFN
Symbol
N
A
A1
A3
b
D&E
D1 & E1
D2 & E2
e
R
ZD & ZE
L
All Dimensions in Millimeters
Minimum
Nominal
Maximum
48
0.8
0.9
0
0.02
0.05
0.2 Ref.
0.18
0.25
0.30
7.00 Basic
5.50 Basic
5.50
5.65
5.80
0.50 Basic
0.20~0.25
0.75 Basic
0.35
0.40
0.45
Reference Document: IDT Drawing #PSC-4203
REVISION C 03/06/15
27
CLOCK GENERATOR FOR CAVIUM PROCESSORS
8413S06 DATA SHEET
Ordering Information
Table 11. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
8413S06BKILF
ICS8413S06BIL
48 Lead VFQFN, Lead-Free
Tray
-40C to 85C
8413S06BKILFT
ICS8413S06BIL
48 Lead VFQFN, Lead-Free
Tape & Reel
-40C to 85C
NOTE: Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
CLOCK GENERATOR FOR CAVIUM PROCESSORS
28
REVISION C 03/06/15
8413S06 DATA SHEET
Revision History Sheet
Rev
B
Table
Page
T1
1
2
3
New pin assignment format - no changes to pins.
Corrected block diagram.
Pin Description Table - corrected pin 39 (nMR) description.
Updated header/footer throughout the datasheet.
2/03/15
2
Corrected QG output in block diagram from differential output to single-ended output.
3/06/15
C
REVISION C 03/06/15
Description of Change
Date
29
CLOCK GENERATOR FOR CAVIUM PROCESSORS
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