8430S10BYI-02LF

8430S10I-02 Clock Generator for Cavium Processors Data Sheet General Description Features The 8430S10I-02 is a PLL-based clock generator specifically designed for Cavium Networks SoC processors. This high performance device is optimized to generate the processor core reference clock, the DDR reference clocks, the PCI/PCI-X bus clocks, and the clocks for both the Gigabit Ethernet MAC and PHY. The clock generator offers ultra low-jitter, low-skew clock outputs, and edge rates that easily meet the input requirements for the CN30XX/CN31XX/CN38XX/CN58XX processors. The output frequencies are generated from a 25MHz external input source or an external 25MHz parallel resonant crystal. The extended temperature range of the 8430S10I-02 supports telecommunication, networking, and storage requirements. • One selectable differential output pair for DDR 533/400/667, LVPECL, LVDS interface levels • • Nine LVCMOS/ LVTTL outputs, 20 typical output impedance • Crystal oscillator interface designed for 25MHz, parallel resonant crystal • Differential input pair (CLK, nCLK) accepts LVPECL, LVDS, SSTL input levels • Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/ LVTTL) input levels • Power output supply modes LVDS and LVPECL – full 3.3V LVCMOS – full 3.3V or mixed 3.3V core/2.5V output • • -40°C to 85°C ambient operating temperature Applications Available in lead-free (RoHS 6) package Systems using Cavium Processors CPE Gateway Design Home Media Servers Pin Assignment VDDO_REF nOE_E Wireless Soho and SME VPN Solutions Wired and Wireless Network Security Web Servers and Exchange Servers nOE_D GND nPLL_ SEL XTAL_IN XTAL_ OUT nXTAL_ SEL CLK nCLK nOE_C VDD nOE_B GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ICS8430S10I-02 48Pin TQFP, EPad 5 32 7mm xx 7m x 1mm 7mm 7mm x1mm 6 31 package bodybody 7 package 30 & Package 8 29 YTop Package View 9 28 Top View 10 27 26 11 12 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 ©2016 Integrated Device Technology, Inc. 1 VDDO_CD QC QD0 QD1 CORE_SEL GND GND nOE_REF VDDO_B QB0 QB1 VDDO_B SPI_SEL0 PCI_SEL1 PCI_SEL0 DDR_SEL 1 DDR_SEL0 nQA QA VDD VDDA VDD GND QREF0 QREF1 Soho SME Gateway VDDO_E Soho Secure Gateway QREF2 GND VDDO_REF nLVDS_SEL GND QE 802.11n AP or Gateway nOE_A SPI_SEL1 • • • • • • • • • Selectable external crystal or differential (single-ended) input source October 4, 2016 8430S10I-02 Data Sheet Block Diagram nLVDS_SEL ©2016 Integrated Device Technology, Inc. 2 October 4, 2016 8430S10I-02 Data Sheet Table 1. Pin Descriptions Number Name 1, 13, 23 VDD Power Type Description 2 nOE_D Input 3, 12, 30, 31, 39, 42, 46 GND Power 4 nPLL_SEL Input 5, 6 XTAL_IN, XTAL_OUT Input 7 nXTAL_SEL Input Pulldown Selects XTAL inputs when LOW. Selects differential clock (CLK, nCLK) input when HIGH. LVCMOS/LVTTL interface levels. 8 CLK Input Pulldown Non-inverting differential clock input. 9 nCLK Input Pullup/ Pulldown Inverting differential clock input. Internal resistor bias to VDD/2. 10 nOE_C Input Pulldown Active LOW output enable for Bank C output. When logic HIGH, the output is in high impedance (HI-Z). When logic LOW, QC output is enabled. LVCMOS/LVTTL interface levels. 11 nOE_B Input Pulldown Active LOW output enable for Bank B outputs. When logic HIGH, the outputs are in high impedance (HI-Z). When logic LOW, the outputs are enabled. LVCMOS/LVTTL interface levels. 14 nOE_A Input Pulldown Active LOW output enable for Bank A outputs. LVCMOS/LVTTL interface levels. 15, 16 SPI_SEL1, SPI_SEL0 Input Pulldown Selects the SPI PLL clock reference frequency. See Table 3D. 17, 18 PCI_SEL1, PCI_SEL0 Input Pulldown Selects the PCI, PCI-X reference clock output frequency. See Table 3C. LVCMOS/LVTTL interface levels. 19, 20 DDR_SEL1, DDR_SEL0 Input Pulldown Selects the DDR reference clock output frequency. See Table 3B. LVCMOS/LVTTL interface levels. 21, 22 nQA, QA Output Differential output pair. Selectable between LVPECL and LVDS interface levels. 24 VDDA Power Analog supply pin. 25, 28 VDDO_B Power Bank B output supply pins. 3.3 V or 2.5V supply. 26, 27 QB1, QB0 Output Single-ended Bank B outputs. LVCMOS/LVTTL interface levels. 29 nOE_REF Input Pulldown Active LOW output enable. When logic HIGH, the QREF[2:0] outputs are in high impedance (HI-Z). When logic LOW, the QREF[2:0] outputs are enabled. LVCMOS/ LVTTL interface levels. 32 CORE_SEL Input Pulldown Selects the processor core clock output frequency. The output frequency is 50MHz when LOW, and 33.333MHz when HIGH. See Table 3A. LVCMOS/LVTTL interface levels. 33, 34 QD1, QD0 Output Single-end Bank D outputs. LVCMOS/LVTTL interface levels. 35 QC Output Single-end Bank C output. LVCMOS/LVTTL interface levels. 36 VDDO_CD Power Bank C and Bank D output supply pin. 3.3 V or 2.5V supply. Core supply pins. Pulldown Active LOW output enable for Bank D outputs. When logic HIGH, the outputs are in high impedance (HI-Z). When logic LOW, the outputs are enabled. LVCMOS/LVTTL interface levels. Power supply ground. Pulldown PLL bypass. When LOW, PLL is enable. When HIGH, PLL is bypassed. LVCMOS/LVTTL interface levels. Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. Pin descriptions continue on the next page. ©2016 Integrated Device Technology, Inc. 3 October 4, 2016 8430S10I-02 Data Sheet Number Name Type 37 VDDO_E Power 38 QE Output Description Bank E output supply pin. 3.3 V or 2.5V supply. Single-end Bank E output. LVCMOS/LVTTL interface levels. Pulldown Selects between LVDS and LVPECL interface levels on differential output pair QA and nQA. When LOW, LVDS interface levels are selected. When HIGH, LVPECL is selected. See Table 3E. 40 nLVDS_SEL Input 41, 48 VDDO_REF Power Bank QREF output supply pins. 3.3 V or 2.5V supply. 43, 44, 45 QREF2, QREF1, QREF0 Output Single-ended reference clock outputs. LVCMOS/LVTTL interface levels. 47 nOE_E Input Pulldown Active LOW output enable for Bank E outputs. When logic HIGH, the outputs are in high impedance (HI-Z). When logic LOW, the outputs are enabled. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions CIN Input Capacitance CPD Power Dissipation Capacitance (per output) RPULLUP Input Pullup Resistor Output Impedance Typical Maximum Units 2 pF VDD, VDDO_X = 3.465V 10 pF VDD = 3.465V, VDDO_X = 2.625V 5 pF 51 k 51 k RPULLDOWN Input Pulldown Resistor ROUT Minimum QB[0:1], QC, QD[0:1], QE QREF[0:2] VDDO_X = 3.465V 20  QB[0:1], QC, QD[0:1], QE QREF[0:2] VDDO_X = 2.625V 25  NOTE: VDDO_X denotes VDDO_B, VDDO_CD, VDDO_E and VDDO_REF. ©2016 Integrated Device Technology, Inc. 4 October 4, 2016 8430S10I-02 Data Sheet Function Tables Table 3A. Control Input Function Table Input Output Frequency CORE_SEL QB[0:1] 0 50MHz (default) 1 33.333MHz Table 3B. Control Input Function Table Inputs Output Frequency DDR_SEL1 DDR_SEL0 QA, nQA 0 0 133.333MHz (default) 0 1 100.000MHz 1 0 83.333MHz 1 1 125.000MHz Table 3C. Control Input Function Table Inputs Output Frequency PCI_SEL1 PCI_SEL0 QC 0 0 133.333MHz (default) 0 1 100.000MHz 1 0 66.6667MHz 1 1 33.333MHz Table 3D. Control Input Function Table Inputs Output Frequency SPI_SEL1 SPI_SEL0 QD[0:1] 0 0 100.000MHz (default) 0 1 125.000MHz 1 0 80.000MHz Table 3E. Control Input Function Table Input Output Levels nLVDS_SEL QA, nQA 0 LVDS (default) 1 LVPECL ©2016 Integrated Device Technology, Inc. 5 October 4, 2016 8430S10I-02 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO (LVCMOS) -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 33.1°C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. LVCMOS Power Supply DC Characteristics, VDD = VDDO_X = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Core Supply Voltage VDDA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VDD – 0.25 3.3 VDD V VDDO_X Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 180 mA IDDA Analog Supply Current 25 mA IDDO_X Output Supply Current 60 mA No Load, CLK selected NOTE: VDDO_X denotes VDDO_B, VDDO_CD and VDDO_REF. Table 4B. LVCMOS Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Core Supply Voltage VDDA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VDD – 0.25 3.3 VDD V VDDO_X Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 102 mA IDDA Analog Supply Current 25 mA IDDO_X Output Supply Current 42 mA No Load, CLK selected NOTE: VDDO_X denotes VDDO_B, VDDO_CD and VDDO_REF. ©2016 Integrated Device Technology, Inc. 6 October 4, 2016 8430S10I-02 Data Sheet Table 4C. LVPECL Power Supply DC Characteristics, VDD = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions VDD Core Supply Voltage VDDA Analog Supply Voltage IEE Power Supply Current IDDA Analog Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V VDD – 0.25 3.3 VDD V 180 mA 25 mA nLVDS_SEL = 1 Table 4D. LVDS Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions VDD Core Supply Voltage VDDA Analog Supply Voltage IDD Power Supply Current IDDA Analog Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V VDD – 0.25 3.3 VDD V 192 mA 25 mA nLVDS_SEL = 0 Table 4E. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL VOH VOL Test Conditions Minimum Typical Maximum Units 2.2 VDD + 0.3 V -0.3 0.8 V 150 µA Input High Current DDR_SEL[0:1], nPLL_SEL, nLVDS_SEL, PCI_SEL[0:1], nOE_REF, SPI_SEL[0:1], nOE_[A:E], nXTAL_SEL, CORE_SEL VDD = VIN = 3.465V Input Low Current DDR_SEL[0:1], nPLL_SEL, nLVDS_SEL, PCI_SEL[0:1], nOE_REF, SPI_SEL[0:1], nOE_[A:E], nXTAL_SEL, CORE_SEL VDD = 3.465V, VIN = 0V -10 µA VDDO_X = 3.465V, IOH = -12mA 2.6 V VDDO_X = 2.625V, IOH = -12mA 1.8 V Output High Voltage Output Low Voltage VDDO_X = 3.465V, IOL = 12mA 0.65 V VDDO_X = 2.625V, IOL = 12mA 0.55 V NOTE: VDDO_X denotes VDDO_B, VDDO_CD, VDDO_E and VDDO_REF. ©2016 Integrated Device Technology, Inc. 7 October 4, 2016 8430S10I-02 Data Sheet Table 4F. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 1.2 VDD V CLK, nCLK Minimum Typical VDD = VIN = 3.465V Maximum Units 150 µA CLK VDD = 3.465V, VIN = 0V -10 µA nCLK VDD = 3.465V, VIN = 0V -150 µA NOTE 1: VIL should not be less than -0.3V. NOTE 2. Common mode voltage is defined as VIH. Table 4G. LVPECL DC Characteristics, VDD = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VDD – 1.4 VDD – 0.9 V VDD – 2.0 VDD – 1.7 V 0.55 1.0 V NOTE 1: Outputs terminated with 50 to VDD – 2V. Table 4H. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 300 500 600 mV 50 mV 1.24 V 50 mV 1.04 1.14 Table 5. Crystal Characteristics Parameter Test Conditions Mode of Oscillation Minimum Typical Maximum Units Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50  Shunt Capacitance 7 pF NOTE: Characterized using an 18pF parallel resonant crystal. ©2016 Integrated Device Technology, Inc. 8 October 4, 2016 8430S10I-02 Data Sheet AC Electrical Characteristics Table 6. AC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions QA, nQA Output Frequency DDR_SEL[1:0] = 00 Typical Maximum 133.333 Units MHz QA, nQA DDR_SEL[1:0] = 01 100 MHz QA, nQA DDR_SEL[1:0] = 10 83.333 MHz QA, nQA DDR_SEL[1:0] = 11 125 MHz CORE_SEL = 0 50 MHz QBx fOUT Minimum QBx CORE_SEL = 1 33.333 MHz QC PCI_SEL[1:0] = 00 133.333 MHz QC PCI_SEL[1:0] = 01 100 MHz QC PCI_SEL[1:0] = 10 66.667 MHz QC PCI_SEL[1:0] = 11 33.333 MHz QDx SPI_SEL[1:0] = 00 100 MHz QDx SPI_SEL[1:0] = 01 125 MHz QDx SPI_SEL[1:0] = 10 80 MHz QE 125 MHz QREFx 25 MHz tsk(b) Bank Skew; NOTE 2, 4 QREFx 30 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 QREFx 200 ps 60 ps 115 ps QA, nQA measured at crosspoint tjit(cc) Cycle-to-Cycle Jitter QBx, QC, QDx 120 ps tjit(per) RMS Period Jitter QA, nQA measured at crosspoint 40 ps tjit(hper) RMS Half-period Jitter QA, nQA measured at crosspoint 50 ps tjit(Ø) RMS Phase Jitter, (Random); NOTE 1 QREFx 25MHz (10kHz to 5MHz) QE QE 125MHz (1.875MHz to 20MHz) QA, nQA tR / tF Output Rise/Fall Time odc Output Duty Cycle tLOCK Lock Time 0.58 ps 0.72 ps 100 300 ps 400 1200 ps QA, nQA 48 52 % QBx, QC, QDx, QE, QREFx 40 60 % 100 ms QBx, QC, QDx, QE, QREFx 20% to 80% NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at maximum fOUT unless noted otherwise. NOTE: VDDO_X denotes VDDO_B, VDDO_CD, VDDO_E and VDDO_REF. NOTE 1: Refer to the phase noise plot. NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO_REF/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. ©2016 Integrated Device Technology, Inc. 9 October 4, 2016 8430S10I-02 Data Sheet ➝ Typical Phase Noise at 125MHz (QE output) Filter Raw Phase Noise Data ➝ ➝ Noise Power dBc Hz 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.72ps (typical) Phase Noise Result by adding a filter to raw data Offset Frequency (Hz) ©2016 Integrated Device Technology, Inc. 10 October 4, 2016 8430S10I-02 Data Sheet ➝ Typical Phase Noise at 25MHz (QREF output) Filter Noise Power dBc Hz 25MHz RMS Phase Jitter (Random) 10kHz to 5MHz = 0.58ps (typical) ➝ ➝ Raw Phase Noise Data Phase Noise Result by adding a filter to raw data Offset Frequency (Hz) ©2016 Integrated Device Technology, Inc. 11 October 4, 2016 8430S10I-02 Data Sheet Parameter Measurement Information 2.05V±5% 1.65V±5% 1.25V±5% 1.65V±5% 2.05V±5% SCOPE VDD, SCOPE VDD VDDO_X VDDA VDDO_X Qx Qx VDDA GND GND - -1.65V±5% 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit -1.25V±5% 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit 2V 2V VDD 3.3V ±5% VDD VDDA VDDA -1.3V±0.165V 3.3V Core/3.3V LVPECL Output Load AC Test Circuit 3.3V Core/3.3V LVDS Output Load AC Test Circuit VDD Par t 1 V DDOX Qx nCLK V PP Cross Points 2 V CMR Par t 2 CLK Qy V DDOX 2 tsk(pp) GND Differential Input Level ©2016 Integrated Device Technology, Inc. LVCMOS Part-to-Part Skew 12 October 4, 2016 8430S10I-02 Data Sheet Parameter Measurement Information, continued QBx, QC, QDx, QE, QREFx QA V DDOX tcycle n+1 V DDOX 2 DDOX 2 ➤ tcycle n ➤ 2 ➤ tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles Differential Cycle-to-Cycle Jitter LVCMOS Cycle-to-Cycle Jitter VOH nQA VREF QA ➤ VOL t half period n t half period n+1 ➤ ➤ t jit(hper) = t half period n — 1 2*fo Histogram Reference Point ➤ 1 fo ➤ 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements ➤ tcycle n V ➤ nQA Mean Period (Trigger Edge) (First edge after trigger) Period Jitter Half Period Jitter Noise Power Phase Noise Plot QREFx VDDOX 2 Phase Noise Mask VDDOX 2 QREFx f1 Offset Frequency tsk(b) f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS Phase Jitter ©2016 Integrated Device Technology, Inc. LVCMOS Bank Skew (where X denotes QREF0 1, or 2) 13 October 4, 2016 8430S10I-02 Data Sheet Parameter Measurement Information, continued nQA nQA 80% 80% VOD QA 20% 20% QA tF tR LVDS Output Rise/Fall Time LVPECL Output Rise/Fall Time nQA 80% 80% QA QBx, QC, QDx, QE, QREFx 20% 20% tR tF LVCMOS Output Rise/Fall Time Differential Output Duty Cycle/Pulse Width/Period VDD QBx, QC, QDx, QE, QREFx Supply Voltage 60% of VDD GND Output-to-Input Phase Lock Output Lock Time LVCMOS Output Duty Cycle/Pulse Width/Period ©2016 Integrated Device Technology, Inc. Not to Scale Lock Time 14 October 4, 2016 8430S10I-02 Data Sheet Parameter Measurement Information, continued Differential Output Voltage Setup Offset Voltage Setup ©2016 Integrated Device Technology, Inc. 15 October 4, 2016 8430S10I-02 Data Sheet Applications Information Wiring the Differential Input to Accept Single-Ended Levels the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VCC/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ©2016 Integrated Device Technology, Inc. 16 October 4, 2016 8430S10I-02 Data Sheet Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, SSTL, and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2D show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. If the driver is from another vendor, use their termination recommendation. Figure 2A. CLK/nCLK Input Driven by a 3.3V LVDS Driver Figure 2B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 2.5V 3.3V 2.5V R3 120Ω R4 120Ω Zo = 60Ω CLK Zo = 60Ω nCLK SSTL R1 120Ω Figure 2C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver ©2016 Integrated Device Technology, Inc. R2 120Ω Differential Input Figure 2D. CLK/nCLK Input Driven by a 2.5V SSTL Driver 17 October 4, 2016 8430S10I-02 Data Sheet Overdriving the XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3A. The XTAL_OUT pin can be left floating. The maximum amplitude of the input signal should not exceed 2V and the input edge rate can be as slow as 10ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, VCC matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. XTAL_OUT R1 100 Ro Rs C1 Zo = 50 ohms XTAL_IN R2 100 Zo = Ro + Rs .1uf LVCMOS Driver Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface XTAL_OUT C2 Zo = 50 ohms XTAL_IN .1uf Zo = 50 ohms LVPECL Driver R1 50 R2 50 R3 50 Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface ©2016 Integrated Device Technology, Inc. 18 October 4, 2016 8430S10I-02 Data Sheet Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential output pair is low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 R3 125 3.3V R4 125 3.3V 3.3V Zo = 50 + _ Input Zo = 50 R1 84 Figure 4A. 3.3V LVPECL Output Termination R2 84 Figure 4B. 3.3V LVPECL Output Termination LVDS Driver Termination A general LVDS interface is shown in Figure 5. Standard termination for LVDS type output structure requires both a 100 parallel resistor at the receiver and a 100 differential transmission line environment. In order to avoid any transmission line reflection issues, the 100 resistor must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 5 can be used with either type of output structure. If using a non-standard termination, it is recommended to contact IDT and confirm if the output is a current source or a voltage source type structure. In addition, since these outputs are LVDS compatible, the amplitude and common mode input range of the input receivers should be verified for compatibility with the output. + LVDS Driver LVDS Receiver 100Ω – 100Ω Differential Transmission Line Figure 5. Typical LVDS Driver Termination ©2016 Integrated Device Technology, Inc. 19 October 4, 2016 8430S10I-02 Data Sheet EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 6. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific SOLDER PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER PIN LAND PATTERN (GROUND PAD) PIN PAD Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) Recommendations for Unused Input and Output Pins Inputs: Outputs: CLK/nCLK Inputs LVPECL Outputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Crystal Inputs LVDS Outputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached. LVCMOS Control Pins All unused LVCMOS output can be left floating. There should be no trace attached. LVCMOS Outputs All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. ©2016 Integrated Device Technology, Inc. 20 October 4, 2016 8430S10I-02 Data Sheet Schematic Example close to the power pins as possible. If space is limited, the 0.1uF capacitor in each power pin filter should be placed on the device side of the PCB and the other components can be placed on the opposite side. Figure 7 shows an example of 8430S10I-02 application schematic. In this example, the device is operated at VDD = VDDO_B = VDDO_CD = VDDO_E = VDDO_REF = 3.3V. An 18pF parallel resonant 25MHz crystal is used. The load capacitance C1 = 18pF and C2 = 18pF are recommended for frequency accuracy. Depending on the parasitics of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used. This will require adjusting C1 and C2. For this device, the crystal load capacitors are required for proper operation. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. As with any high speed analog circuitry, the power supply pins are vulnerable to noise. To achieve optimum jitter performance, power supply isolation is required. The 8430S10I-02 provides separate power supplies to isolate from coupling into the internal PLL. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as R1 QREF0 Logic Control Input Examples To Logic Input pins VDDO To Logic Input pins R2 QE RD2 1K X1 1 2 3 4 5 6 7 8 9 10 11 12 F p 8 1 25MHz nOE_D 18pF nPLL_SEL XTAL_IN XTAL_OUT nXTAL_SEL VDD nOE_C nOE_B R4 125 VDD nOE_D GND nPLL_SEL XTAL_IN XTAL_OUT nXTAL_SEL CLK nCLK nOE_C nOE_B GND CLK Zo = 50 VDDO_CD QC QD0 QD1 CORE_SEL GND GND nOE_REF VDDO_B QB0 QB1 VDDO_B VD D nOE_A SPI_SEL1 SPI_SEL0 PC I_SEL1 PC I_SEL0 D D R _SEL1 D D R _SEL0 nQA QA VD D VD D A R3 125 13 14 15 16 17 18 19 20 21 22 23 24 nCLK Zo = 50 R7 84 Receiv er 36 35 34 33 32 31 30 29 28 27 26 25 VDD= VDDO_B = 3.3V VDDO_CD = VDDO_E= VDDO_REF = 3.3V CORE_SEL nOE_REF 3.3V R5 133 PAD VDD C2 Zo = 50 33 VD D O_R EF nOE_E GN D QR EF 0 QR EF 1 QR EF 2 GN D VD D O_R EF LVD S_SEL GN D QE VD D O_E U1 R6 133 Zo = 50 Ohm QA0 + 49 RD1 Not Install C1 18pF LVD S_SEL VDDO_REF RU2 Not Install nOE_E RU1 1K Receiv er Set Logic Input to '0' VDD 48 47 46 45 44 43 42 41 40 39 38 37 Set Logic Input to '1' VDD Zo = 50 33 nQA0 R8 84 Zo = 50 Ohm - LVPECL Driv er nOE_A SPI_SEL1 SPI_SEL0 PCI_SEL1 PCI_SEL0 DDR_SEL1 DDR_SEL0 3.3V VDD R9 10 VDDA C3 0.01u R10 82.5 C4 10u R11 82.5 LVPECL Termination BLM18BB221SN1 1 2 VDDO_REF (U1:41) Ferrite Bead C6 C5 0.1uF VDDO_REF (U1:48) C7 C8 10uF 0.1uF 0.1uF QA0 nQA0 3.3V Zo = 50 Ohm BLM18BB221SN2 1 2 QA0 VDD Ferrite Bead C10 C9 0.1uF 3.3V (U1:1) (U1:13) (U1:23) VDD C11 C12 + C13 Zo = 50 Ohm nQA0 10uF 0.1uF 0.1uF 0.1uF 2 VDDO Ferrite Bead C15 C14 0.1uF - LVDS Termination BLM18BB221SN3 1 R12 100 (U1:25) C16 10uF 0.1uF (U1:28) C17 0.1uF (U1:36) (U1:37) C18 0.1uF VDDO C19 0.1uF Figure 7. 8430S10I-02 Layout Example ©2016 Integrated Device Technology, Inc. 21 October 4, 2016 8430S10I-02 Data Sheet Power Considerations (LVCMOS/LVDS Outputs) This section provides information on power dissipation and junction temperature for the 8430S10I-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 8430S10I-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core and LVDS Output Power Dissipation • Power (core, LVDS) = VDD_MAX * (IDD + IDDA) = 3.465V * (192mA + 25mA) = 751.9mW LVCMOS Output Power Dissipation • Output Impedance ROUT Power Dissipation due to Loading 50 to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 20)] = 24.80mA • Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 20 * (24.80mA)2 = 12.3mW per output • Total Power Dissipation on the ROUT Total Power (ROUT) = 12.3mW * 9 = 110.7mW • Dynamic Power Dissipation at 133MHz Power (133MHz) = CPD * Frequency * (VDDO)2 = 10pF * 133MHz * (3.465V)2 = 16mW per output Total Power (133MHz) = 16mW * 6 = 96mW • Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * Frequency * (VDDO)2 = 10pF * 25MHz * (3.465)2 = 3mW per output Total Power (25MHz) = 3mW * 3 = 9mW Total Power Dissipation • Total Power = Power (core, LVDS) + Total Power (ROUT) + Total Power (133MHz) + Total Power (25MHz) = 751.9mW + 110.7mW + 96mW + 9mW = 967.6mW ©2016 Integrated Device Technology, Inc. 22 October 4, 2016 8430S10I-02 Data Sheet 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 33.1°C/W per Table 7A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.968W * 33.1°C/W = 117°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7A. Thermal Resistance JA for 48 Lead TQFP, EPAD Forced Convection JA Vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ©2016 Integrated Device Technology, Inc. 0 1 2.5 33.1°C/W 27.2°C/W 25.7°C/W 23 October 4, 2016 8430S10I-02 Data Sheet Power Considerations (LVCMOS/LVPECL Outputs) This section provides information on power dissipation and junction temperature for the 8430S10I-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 8430S10I-02 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core and LVPECL Output Power Dissipation • Power (core)_MAX = VDD_MAX * IEE_MAX = 3.465V * 180mA = 623.7mW • Power (output)_MAX = 30mW/Loaded Output Pair LVCMOS Output Power Dissipation • Output Impedance ROUT Power Dissipation due to Loading 50 to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 20)] = 24.80mA • Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 20 * (24.80mA)2 = 12.3mW per output • Total Power Dissipation on the ROUT Total Power (ROUT) = 12.3mW * 9 = 110.7mW • Dynamic Power Dissipation at 133MHz Power (133MHz) = CPD * Frequency * (VDDO)2 = 10pF * 133MHz * (3.465V)2 = 16mW per output Total Power (133MHz) = 16mW * 6 = 96mW • Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * Frequency * (VDDO)2 = 10pF * 25MHz * (3.465)2 = 3mW per output Total Power (25MHz) = 3mW * 3 = 9mW Total Power Dissipation • Total Power = Power (core) + Power (LVPECL output) + Total Power (ROUT) + Total Power (133MHz) + Total Power (25MHz) = 623.7mW + 30mW + 110.7mW + 96mW + 9mW = 869.4mW ©2016 Integrated Device Technology, Inc. 24 October 4, 2016 8430S10I-02 Data Sheet 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 33.1°C/W per Table 7B below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.869W * 33.1°C/W = 113.8°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7B. Thermal Resistance JA for 48 Lead TQFP, EPAD Forced Convection JA Vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ©2016 Integrated Device Technology, Inc. 0 1 2.5 33.1°C/W 27.2°C/W 25.7°C/W 25 October 4, 2016 8430S10I-02 Data Sheet 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pairs. The LVPECL output driver circuit and termination are shown in Figure 8. VDDO Q1 VOUT RL VDDO - 2V Figure 8. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VDDO – 2V. • For logic high, VOUT = VOH_MAX = VDDO_MAX – 0.9V (VDDO_MAX – VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VDDO_MAX – 1.7V (VDDO_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VDDO_MAX – 2V))/RL] * (VDDO_MAX – VOH_MAX) = [(2V – (VDDO_MAX – VOH_MAX))/RL] * (VDDO_MAX – VOH_MAX) = [(2V – 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VDDO_MAX – 2V))/RL] * (VDDO_MAX – VOL_MAX) = [(2V – (VDDO_MAX – VOL_MAX))/RL] * (VDDO_MAX – VOL_MAX) = [(2V – 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ©2016 Integrated Device Technology, Inc. 26 October 4, 2016 8430S10I-02 Data Sheet Reliability Information Table 8. JA vs. Air Flow Table for a 48 Lead TQFP, EPAD JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 33.1°C/W 27.2°C/W 25.7°C/W Transistor Count The transistor count for 8430S10I-02 is: 10,871 ©2016 Integrated Device Technology, Inc. 27 October 4, 2016 8430S10I-02 Data Sheet Package Outline and Package Dimensions Package Outline - Y Suffix for 48 Lead TQFP, EPAD -HD VERSION EXPOSED PAD DOWN 0.20 TAB -TAB, EXPOSED PART OF CONNECTION BAR OR TIE BAR Table 9. Package Dimensions 48L TQFP, EPAD Symbol N A A1 A2 b c D&E D1 & E1 D2 & E2 D3 & E3 e L  ccc JEDEC Variation: ABC - HD All Dimensions in Millimeters Minimum Nominal Maximum 48 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.09 0.20 9.00 Basic 7.00 Basic 5.50 Ref. 3.5 0.5 Basic 0.45 0.60 0.75 0° 7° 0.08 Reference Document: JEDEC Publication 95, MS-026 ©2016 Integrated Device Technology, Inc. 28 October 4, 2016 8430S10I-02 Data Sheet Ordering Information Table 10. Ordering Information Part/Order Number 8430S10BYI-02LF 8430S10BYI-02LFT Marking ICS0S10BI02L ICS0S10BI02L ©2016 Integrated Device Technology, Inc. Package “Lead-Free” 48 TQFP, EPAD “Lead-Free” 48 TQFP, EPAD 29 Shipping Packaging Tray Tape & Reel Temperature -40C to 85C -40C to 85C October 4, 2016 8430S10I-02 Data Sheet Revision History Sheet Rev B Table Page T6 9 15 AC Characteristics Table - added Lock Time parameter. Added Lock Time measurement drawing. 11/2/09 1 2 8 Features section - corrected Differential Input bullet (deleted HCSL and LVHSTL levels). Block Diagram - corrected naming convention for SPI4_SEL1:0 to SPI_SEL1:0. Differential DC Characteristics Table - corrected VCMR levels from 0.5V min / VDD - 0.85V max to 1.2V min / VDD max. Deleted Power Supply Filtering Technique application note (see Schematic Example). Updated Wiring the Differential Input to Accept Single-ended Levels application note. Corrected Differential Clock Input Interface application note (deleted HCSL and LVHSTL levels). Deleted Crystal Input Interface application note (see Schematic Example). Updated Overdriving the XTAL Interface application note. Updated LVDS Driver Termination application note. Updated Schematic Example application note and diagram. Corrected D3/E3 dimensions. Updated Package Outline. 1/17/11 Ordering Information - Removed quantity in tape and reel. Deleted LF note below table. Removed ICS from part number where needed. Updated header and footer. 10/4/16 T4F 16 C 17 18 C T9 19 21 28 T10 29 Description of Change ©2016 Integrated Device Technology, Inc. Date 30 October 4, 2016 8430S10I-02 Data Sheet Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com www.IDT.com/go/sales www.IDT.com/go/supp ort DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. 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