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843256BGILFT

843256BGILFT

  • 厂商:

    RENESAS(瑞萨)

  • 封装:

    TSSOP-24

  • 描述:

    IC SYNTHESIZER W/BUFF 24-TSSOP

  • 数据手册
  • 价格&库存
843256BGILFT 数据手册
FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer With/Integrated Fanout Buffer 843256 DATASHEET GENERAL DESCRIPTION FEATURES The 843256 is a Crystal-to-3.3V LVPECL Clock Synthesizer/Fanout Buffer designed for Fibre Channel and Gigabit Ethernet applications. The output frequency can be set using the frequency select pins and a 25MHz crystal for Ethernet frequencies, or a 19.44MHz crystal for SONET. The low phase noise characteristics of the 843256 make it an ideal clock for these demanding applications. • Six 3.3V differential LVPECL output pairs • Output frequency range: 62.5MHz to 625MHz • Crystal input frequency range: 15.625MHz to 25.5MHz • RMS phase jitter at 156.25MHz, using a 25MHz crystal (1.875MHz to 20MHz): 0.41ps (typical) @ 3.3V • Operating supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V • 0°C to 70°C ambient operating temperature • Available in lead-free (RoHS 6) package SELECT FUNCTION TABLE Inputs Function FB_SEL N_SEL1 N_SEL0 M Divide N Divide M/N 0 0 0 25 1 25 0 0 1 25 2 12.5 0 1 0 25 4 6.25 0 1 1 25 5 5 1 0 0 32 1 32 1 0 1 32 2 16 1 1 0 32 4 8 1 1 1 32 8 4 Q0 BLOCK DIAGRAM PIN ASSIGNMENT nQ0 PLL_BYPASS Pullup Q1 1 XTAL_IN OSC PLL 0 N Output Divider XTAL_OUT N_SEL1 N_SEL0 Q2 nQ2 Q3 M Feedback Divider FB_SEL nQ1 nQ3 Pulldown Q4 Pullup nQ4 Pullup 24-Lead TSSOP, E-Pad 4.40mm x 7.8mm x 0.92mm body package G Package Top View Q5 nQ5 843256 REVISION B DECEMBER 18, 2014 1 ©2014 Integrated Device Technology, Inc. 843256 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 2 VCCO Power Output supply pins. 3, 4 nQ2, Q2 Output Differential output pair. LVPECL interface levels. 5, 6 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 7, 8 nQ0, Q0 Output Differential output pair. LVPECL interface levels. Selects between the PLL and crystal inputs as the input to the dividers. When LOW, selects PLL. When HIGH, selects XTAL_IN, XTAL_OUT. LVCMOS / LVTTL interface levels. 9 PLL_BYPASS Input Pullup 10 VCCA Power Analog supply pin. 11 VCC Power Core supply pin. Input 12 FB_SEL 13, 14 15, 18 XTAL_IN, XTAL_ OUT N_SEL0 N_SEL1 Pulldown 16, 17 VEE 19, 20 nQ5, Q5 Output Differential output pair. LVPECL interface levels. 21, 22 nQ4, Q4 Output Differential output pair. LVPECL interface levels. 23, 24 nQ3, Q3 Output Differential output pair. LVPECL interface levels. Input Input Feedback frequency select pin. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Pullup Output frequency select pin. LVCMOS/LVTTL interface levels. Negative supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ RPULLUP Input Pullup Resistor 51 kΩ FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer With/Integrated Fanout Buffer Test Conditions 2 Minimum Typical Maximum Units REVISION B 12/18/14 843256 DATA SHEET TABLE 3. CRYSTAL FUNCTION TABLE Inputs XTAL (MHz) FB_SEL Function N_SEL1 N_SEL0 M VCO (MHz) N Output (MHz) 20 0 0 0 25 500 1 500 20 0 0 1 25 500 2 250 20 0 1 0 25 500 4 125 20 0 1 1 25 500 5 100 21.25 0 1 1 25 531.25 5 106.25 24 0 0 0 25 600 1 600 24 0 0 1 25 600 2 300 24 0 1 0 25 600 4 150 24 0 1 1 25 600 5 120 25 0 0 0 25 625 1 625 25 0 0 1 25 625 2 312.5 25 0 1 0 25 625 4 156.25 25 0 1 1 25 625 5 125 25.5 0 1 0 25 637.5 4 159.375 15.625 1 1 1 32 500 8 62.5 18.5625 1 1 1 32 594 8 74.25 18.75 1 0 0 32 600 1 600 18.75 1 0 1 32 600 2 300 18.75 1 1 0 32 600 4 150 18.75 1 1 1 32 600 8 75 19.44 1 0 0 32 622.08 1 622.08 19.44 1 0 1 32 622.08 2 311.04 19.44 1 1 0 32 622.08 4 155.52 19.44 1 1 1 32 622.08 8 77.76 19.53125 1 0 0 32 625 1 625 19.53125 1 0 1 32 625 2 312.5 19.53125 1 1 0 32 625 4 156.25 19.53125 1 1 1 32 625 8 78.125 20 1 1 1 32 640 8 80 REVISION B 12/18/14 3 FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer With/Integrated Fanout Buffer 843256 DATA SHEET ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 37°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA VCCO Analog Supply Voltage V– 0.12 3.3 3.465 V Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 190 mA ICCA Analog Supply Current 12 mA cc TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VCC Core Supply Voltage VCCA VCCO IEE ICCA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage V– 0.12 3.3 3.465 V Output Supply Voltage 2.375 2.5 2.625 V Power Supply Current 190 mA Analog Supply Current 12 mA cc TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VIH Input High Voltage Test Conditions 2 VCC + 0.3 V VIL Input Low Voltage -0.3 0.8 V FB_SEL VCC = VIN = 3.465V 150 µA IIH Input High Current PLL_BYPASS, N_SEL0, N_SEL1 VCC = VIN = 3.465V 5 µA FB_SEL VCC = 3.465V, VIN = 0V -5 µA IIL Input Low Current PLL_BYPASS, N_SEL0, N_SEL1 VCC = 3.465V, VIN = 0V -150 µA FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer With/Integrated Fanout Buffer 4 Minimum Typical REVISION B 12/18/14 843256 DATA SHEET TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Minimum Typical Maximum Units V - 1.4 V - 0.9 V V - 2.0 V - 1.7 V 0.6 1.0 V CCO CCO CCO CCO NOTE 1: Outputs terminated with 50 to VCCO - 2V. Ω TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 15.625 25.5 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Maximum Units 625 MHz NOTE: Characterized using an 18pF parallel resonant crystal. TABLE 6A. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter FOUT Output Frequency tjit(Ø) RMS Phase Jitter (Random) tsk(o) Output Skew; NOTE 1, 2 tR / tF Output Rise/Fall Time odc Output Duty Cycle tLOCK PLL Lock Time Test Conditions Minimum Typical 62.5 156.25MHz, Integration Range: 1.875MHz - 20MHz 156.25MHz, Integration Range: 12kHz - 20MHz 0.41 ps 0.85 ps 40 ps 20% to 80% 200 650 ps F ≤ 312.5MHz 47 53 % F > 312.5MHz 45 OUT OUT 55 % 20 ms Maximum Units 625 MHz See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. TABLE 6B. AC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter FOUT Output Frequency tjit(Ø) RMS Phase Jitter (Random) tsk(o) Output Skew; NOTE 1, 2 tR / tF Output Rise/Fall Time odc Output Duty Cycle tLOCK PLL Lock Time Test Conditions Minimum Typical 62.5 156.25MHz, Integration Range: 1.875MHz - 20MHz 156.25MHz, Integration Range: 12kHz - 20MHz 20% to 80% 0.41 ps 0.85 ps 45 ps 200 650 ps 46 54 % 20 ms For NOTES, please see Table 6A above. REVISION B 12/18/14 5 FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer With/Integrated Fanout Buffer 843256 DATA SHEET ➤ TYPICAL PHASE NOISE AT 156.25MHZ @ 3.3V Ethernet Filter 156.25MHz Raw Phase Noise Data ➤ ➤ NOISE POWER dBc Hz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.41ps (typical) Phase Noise Result by adding Ethernet Filter to raw data OFFSET FREQUENCY (HZ) FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer With/Integrated Fanout Buffer 6 REVISION B 12/18/14 843256 DATA SHEET PARAMETER MEASUREMENT INFORMATION 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD RMS PHASE JITTER OUTPUT RISE/FALL TIME REVISION B 12/18/14 7 FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer With/Integrated Fanout Buffer 843256 DATA SHEET APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 843256 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01μF 10Ω VCCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: INPUTS: LVCMOS CONTROL PINS LVPECL OUTPUTS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CRYSTAL INPUT INTERFACE The 843256 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 18p X1 18pF Parallel Crystal XTAL_OUT C2 22p FIGURE 2. CRYSTAL INPUt INTERFACE FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer With/Integrated Fanout Buffer 8 REVISION B 12/18/14 843256 DATA SHEET LVCMOS TO XTAL INTERFACE impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3 The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD VDD R1 Ro Rs .1uf Zo = 50 Zo = Ro + Rs XTAL_IN R2 XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission FIGURE 4A. LVPECL OUTPUT TERMINATION REVISION B 12/18/14 FIGURE 4B. LVPECL OUTPUT TERMINATION 9 FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer With/Integrated Fanout Buffer 843256 DATA SHEET TERMINATION FOR 2.5V LVPECL OUTPUT Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminat-ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground 2.5V VCCO=2.5V Zo = 50 Ohm R1 250 level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C. 2.5V 2.5V VCCO=2.5V R3 250 Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - 2,5V LVPECL Driv er R2 62.5 2,5V LVPECL Driv er R4 62.5 R1 50 R2 50 R3 18 FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer With/Integrated Fanout Buffer 10 REVISION B 12/18/14 843256 DATA SHEET POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 843256. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 843256 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. · · Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 190mA = 658.35mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 6 * 30mW = 180mW Total Power_MAX (3.465V, with all outputs switching) = 658;.35mW + 180mW = 838.35mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.838W * 37°C/W = 101°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7B. THERMAL RESISTANCE θJA FOR 24-PIN TSSOP, E-PAD FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards REVISION B 12/18/14 0 1 2.5 37°C/W 31°C/W 30°C/W 11 FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer With/Integrated Fanout Buffer 843256 DATA SHEET 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCCO- 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX - VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer With/Integrated Fanout Buffer 12 REVISION B 12/18/14 843256 DATA SHEET RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP, E-PAD θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 37°C/W 31°C/W 30°C/W TRANSISTOR COUNT The transistor count for 843256 is: 3863 REVISION B 12/18/14 13 FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer With/Integrated Fanout Buffer 843256 DATA SHEET PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP, E-PAD TABLE 9. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Nominal Maximum 24 A -- A1 0.05 A2 0.85 b 0.19 b1 0.19 c 0.09 c1 0.09 0.127 0.16 D 7.70 7.80 7.90 E E1 0.15 0.90 0.95 0.30 0.22 0.25 0.20 6.40 BASIC 4.30 e L 1.10 4.40 4.50 0.65 BASIC 0.50 0.60 0.70 P 5.0 P1 α 3.2 0° 8° aaa 0.076 bbb 0.10 Reference Document: JEDEC Publication 95, MO-153 FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer With/Integrated Fanout Buffer 14 REVISION B 12/18/14 843256 DATA SHEET TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843256BGLF ICS843256BGLF 24 Lead “Lead-Free” TSSOP, E-Pad tube 0°C to 70°C ICS843256BGLFT ICS843256BGLF 24 Lead “Lead-Free” TSSOP, E-Pad tape & reel 0°C to 70°C NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. REVISION B 12/18/14 15 FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer With/Integrated Fanout Buffer Corporate Headquarters 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2014. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.
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