86004BGILF

86004I 15.625MHZ to 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer DATA SHEET GENERAL DESCRIPTION FEATURES The 86004I is a high performance 1:4 LVCMOS/LVTTL Clock Buffer. The 86004I has a fully integrated PLL and can be configured as zero delay buffer and has an input and output frequency range of 15.625MHz to 62.5MHz. The VCO operates at a frequency range of 250MHz to 500MHz. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output divider. • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Single LVCMOS/LVTTL clock input • CLK accepts the following input levels: LVCMOS or LVTTL • Output frequency range: 15.625MHz to 62.5MHz • Input frequency range: 15.625MHz to 62.5MHz • VCO range: 250MHz to 500MHz • External feedback for “zero delay” clock regeneration with configurable frequencies • Fully integrated PLL • Cycle-to-cycle jitter: 75ps (maximum) • Output skew: 65ps (maximum) • Full 3.3V or 2.5V, or 3.3V core/2.5V output operating supply • -40°C to 85° ambient operating temperature • Available in lead-free RoHS compliant package BLOCK DIAGRAM PIN ASSIGNMENT 86004I 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View 86004I REVISION A 7/10/15 1 ©2015 Integrated Device Technology, Inc. 86004I DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 3, 13, 15 Q1, Q0, Q3, Q2 Output 2, 7, 14 GND Power Power supply ground. Frequency range select input. See Table 3A and 3B. LVCMOS/LVTTL interface levels. Clock outputs. 7 typical output impedance. LVCMOS/LVTTL interface levels. Ω 4 F_SEL Input Pulldown 5 VDD Power Core supply pin. 6 CLK Input Pulldown LVCMOS/LVTTL clock input. 8 VDDA Power Analog supply pin. 9 PLL_SEL Input 10 FB_IN Input 11 MR Input 12, 16 VDDO Power Selects between the PLL and reference clock as input to the dividers. When LOW, selects the reference clock (PLL Bypass). When HIGH, selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels. Feedback input to phase detector for regenerating clocks with “zero delay”. Pulldown Connect to one of the outputs. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset Pulldown causing the outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pullup Output supply pins. NOTE: and refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Pullup Pulldown TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor CPD Power Dissipation Capacitance (per output) ROUT Output Impedance Maximum 0 31.25 62.5 1 15.625 31.25 15.625MHZ to 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer Units kΩ 23 pF VDD, VDDA, VDDO = 2.625V 17 pF 12 Ω 5 7 TABLE 3B. CONTROL INPUT FUNCTION TABLE, PLL_SEL = 0 Input/Output Frequency Range (MHz) Minimum Maximum 51 3.3V ± 5% F_SEL Typical VDD, VDDA, VDDO = 3.465V TABLE 3A. CONTROL INPUT FUNCTION TABLE, PLL_SEL = 1 Input Minimum Input F_SEL 2 Output 0 Ref ÷8 1 Ref ÷16 REVISION A 7/10/15 86004I DATA SHEET ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 89°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 VDD V 3.135 3.3 VDDO Output Supply Voltage 3.465 V IDD Power Supply Current 98 mA IDDA Analog Supply Current 22 mA IDDO Output Supply Current 8 mA Maximum Units TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VDD VDDA Test Conditions Minimum Typical Core Supply Voltage 3.135 3.3 Analog Supply Voltage 3.135 3.3 VDDO Output Supply Voltage 2.375 2.5 IDD 3.465 V V V DD 2.625 V Power Supply Current 98 mA IDDA Analog Supply Current 22 mA IDDO Output Supply Current 8 mA TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage 2.375 2.5 VDDO Output Supply Voltage 2.375 2.5 IDD V V DD 2.625 V Power Supply Current 88 mA IDDA Analog Supply Current 18 mA IDDO Output Supply Current 6 mA REVISION A 7/10/15 3 15.625MHZ to 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer 86004I DATA SHEET TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL VOH Input High Current Input Low Current Test Conditions Minimum Typical Maximum Units VDD = 3.3V 2 VDD + 0.3 V VDD = 2.5V 1.7 VDD + 0.3 V VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V CLK, MR, FB_IN, F_SEL VDD = VIN = 3.465V 150 µA PLL_SEL VDD = VIN = 3.465V 5 µA CLK, MR, FB_IN, F_SEL VDD = 3.465V, VIN = 0V -5 µA PLL_SEL VDD = 3.465V, VIN = 0V -150 µA VDDO = 3.465V 2.6 V VDDO = 2.625V 1.8 Output High Voltage; NOTE 1 V VOL Output Low Voltage; NOTE 1 VDDO = 3.465V or 2.625V NOTE 1: Outputs terminated with 50W to VDDO/2. See Parameter Measurement Information Section, Output Load Test Circuit diagrams. 0.5 V Maximum Units TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tpLH Propagation Delay, Low-to-High; NOTE 1 t(Ø) Static Phase Offset; NOTE 2, 4 tsk(o) tjit(cc) Output Skew; NOTE 3, 4 Cycle-to-Cycle Jitter; NOTE 4 tL PLL Lock Time tR / tF Output Rise/Fall Time Test Conditions Minimum Typical F_SEL = 0 31.25 62.5 MHz F_SEL = 1 15.625 31.25 MHz 4.1 6.1 ns -500 500 ps 65 75 ps ps 1 mS 1 ns PLL_SEL = 0V, Bypass Mode PLL_SEL = 3.3V PLL_SEL = 0V 0.4 odc Output Duty Cycle 49 51 % All parameters measured at fMAX unless noted otherwise. NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from VDD/2 of the input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 15.625MHZ to 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer 4 REVISION A 7/10/15 86004I DATA SHEET TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tpLH Propagation Delay, Low-to-High; NOTE 1 t(Ø) Static Phase Offset; NOTE 2, 4 tsk(o) tjit(cc) Output Skew; NOTE 3, 4 Cycle-to-Cycle Jitter; NOTE 4 tL PLL Lock Time tR / tF Output Rise/Fall Time Test Conditions Minimum F_SEL = 0 F_SEL = 1 PLL_SEL = 0V, Bypass Mode PLL_SEL = 2.5V Typical Maximum Units 31.25 62.5 MHz 15.625 31.25 MHz 4.25 6.25 ns -500 500 ps 65 75 ps ps 1 mS 1 ns PLL_SEL = 0V 0.4 odc Output Duty Cycle 48 52 % All parameters measured at fMAX unless noted otherwise. NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from VDD/2 of the input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tpLH Propagation Delay, Low-to-High; NOTE 1 t(Ø) Static Phase Offset; NOTE 2, 4 tsk(o) tjit(cc) Output Skew; NOTE 3, 4 Cycle-to-Cycle Jitter; NOTE 4 tL PLL Lock Time tR / tF Output Rise/Fall Time Test Conditions Minimum Typical Maximum Units F_SEL = 0 31.25 62.5 MHz F_SEL = 1 PLL_SEL = 0V, Bypass Mode PLL_SEL = 2.5V 15.625 31.25 MHz 4.5 6.5 ns -500 500 ps 65 75 ps ps 1 mS 1 ns PLL_SEL = 0V 0.4 odc Output Duty Cycle 48 52 % All parameters measured at fMAX unless noted otherwise. NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from VDD/2 of the input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. REVISION A 7/10/15 5 15.625MHZ to 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer 86004I DATA SHEET PARAMETER MEASUREMENT INFORMATION 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 2.5VCORE/ 2.5V OUTPUT LOAD AC TEST CIRCUIT CYCLE-TO-CYCLE JITTER t(Ø) mean = Static Phase Offset (where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges) STATIC PHASE OFFSET OUTPUT SKEW 15.625MHZ to 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer 6 REVISION A 7/10/15 86004I DATA SHEET PARAMETER MEASUREMENT INFORMATION, CONTINUED OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD PROPAGATION DELAY REVISION A 7/10/15 7 15.625MHZ to 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer 86004I DATA SHEET APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 86004I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD 10Ω .01μF VDDA 10 μF .01μF FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. LVCMOS OUTPUTS All unused LVCMOS output can be left floating. We recommend that there is no trace attached. SCHEMATIC EXAMPLE Figure 2 shows a schematic example of using an 86004I. It is recommended to have one decouple capacitor per power pin. Each decoupling capacitor should be located as close as possible to the power pin. The low pass filter R7, C11 and C16 for clean analog supply should also be located as close to the VDDA pin as possible. R1 43 VDD Zo = 50 Serial Termination R3 1K VDD U1 VDD 1 2 3 4 5 6 7 8 Ro ~ 7 Ohm R8 LVCMOS 43 Zo = 50 VDD Q1 GND Q0 F_SEL VDD CLK GND VDDA VDDO Q2 GND Q3 VDDO MR FB_IN PLL_SEL 43 Zo = 50 R11 43 ICS86004 ICS86004I R7 10 C16 10u R2 16 15 14 13 12 11 10 9 C11 0.01u VDD=3.3V Zo = 50 VDD R6 1K (U1-5) VDD (U1-12) C1 0.1uF C2 0.1uF VDD (U1-16) C3 0.1uF Parallel Termination R4 100 Zo = 50 R5 100 FIGURE 2. 86004I SCHEMATIC EXAMPLE 15.625MHZ to 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer 8 REVISION A 7/10/15 86004I DATA SHEET RELIABILITY INFORMATION TABLE 5. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 137.1°C/W 89.0°C/W 118.2°C/W 81.8°C/W 500 106.8°C/W 78.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for 86004I is: 2496 REVISION A 7/10/15 9 15.625MHZ to 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer 86004I DATA SHEET PACKAGE OUTLINE - G SUFFIX 16 LEAD TSSOP TABLE 6. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N Maximum 16 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 15.625MHZ to 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer 10 REVISION A 7/10/15 86004I DATA SHEET TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 86004BGILF 86004BIL 16 Lead “Lead-Free” TSSOP Tube -40°C to 85°C 86004BGILFT 86004BIL 16 Lead “Lead-Free” TSSOP Tape & Reel -40°C to 85°C NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. REVISION A 7/10/15 11 15.625MHZ to 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer 86004I DATA SHEET REVISION HISTORY SHEET Rev A A Table Page 5A - 5C T7 4-5 11 T7 11 15.625MHZ to 62.5MHZ, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer Description of Change AC Tables - added thermal note and corrected NOTE 1. Ordering Information Table - added LF marking and deleted “ICS” prefix from Part/Order Number column. Updated Header/Footer. Ordering Information - removed leaded devices. Updated data sheet format. 12 Date 2/24/10 7/10/15 REVISION A 7/10/15 Corporate Headquarters 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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