870919BRI-01LF

LVCMOS Clock Generator 870919I-01 DATA SHEET General Description Features The 870919I-01 is an LVCMOS clock generator that uses an internal phase lock loop (PLL) for frequency multiplication and to lock the low-skew outputs to the selected reference clock. The device offers eight outputs. The PLL loop filter is completely internal and does not require external components. Several output configurations of the PLL feedback and a divide-by-2 (controlled by FREQ_SEL) allow applications to optimize frequency generation over a wide range of input reference frequencies. The PLL can also be disabled by the PLL_EN control signal to allow for low frequency or DC testing. The LOCK output asserts to indicate when phase-lock has been achieved. The 870919I-01 device is a member of the family of high performance clock solutions from IDT. • • • • • • • • • • • • • • • • • Two selectable single-ended input reference clocks • For functional replacement part use 8T49N285 Eight single-ended clock outputs Internal PLL does not require external loop filter components 5V tolerant inputs Maximum output frequency: 160MHz, (2XQ output) Maximum output frequency: 80MHz, (Q0:Q4 and nQ5 outputs) LVCMOS interface levels for all inputs and outputs PLL disable feature for low-frequency testing PLL lock output Selectable synchronization of output to input edge Output drive capability: ±24mA Output skew: 300ps (maximum), Q0:Q4 Output skew: 500ps (maximum), all outputs Full 3.3V supply voltage Available in lead-free packages -40°C to 85°C ambient operating temperature Fully pin and function compatible with the IDT QS5LV919 (including 55, 70, 100, 133 and 160MHz options) Block Diagram LOCK 0 SYNC0 SYNC1 0 1 1 fREF PLL fVCO 20MHz - 160MHz 1 ÷2 0 ÷1 2XQ ÷2 Q0 Q1 REF_SEL Q2 FEEDBACK Q3 nPE Q4 PLL_EN nQ5 FREQ_SEL ÷4 Q/2 OE/nRST 870919I-01 REVISION C 11/6/15 1 ©2015 Integrated Device Technology, Inc. 870919I-01 DATA SHEET Q4 VDD 2XQ Q/2 GND Q3 VDD Q2 GND LOCK PLL_EN GND Q1 VDD Q4 2XQ GND 28 27 26 VDD VDD nQ5 1 25 Q/2 REF_SEL 6 24 GND SYNC0 7 23 Q3 AVDD 8 22 VDD nPE 9 21 Q2 AGND 10 20 GND SYNC1 11 19 LOCK PLL_EN GND Q1 VDD 12 13 14 15 16 17 18 870919I-01 28-Lead QSOP, 150Mil 3.9mm x 9.9mm x 1.5mm package body R Package Top View REVISION C 11/6/15 2 Q0 28 27 26 25 24 23 22 21 20 19 18 17 16 15 3 5 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 4 FEEDBACK FREQ_SEL GND nQ5 VDD OE/nRST FEEDBACK REF_SEL SYNC0 AVDD nPE AGND SYNC1 FREQ_SEL GND Q0 OE/nRST Pin Assignments 870919I-01 28-Lead PLCC 11.5mm x 11.5mm x 4.4mm package body V Package Top View 2 LVCMOS CLOCK GENERATOR 870919I-01 DATA SHEET Table 1. Pin Descriptions Number Name Type Description 1, 13, 17, 20, 24 GND Power Power supply ground. 2 nQ5 Output Single-ended clock output (phase is inverted with respect to other outputs). LVCMOS/LVTTL interface levels 3, 15, 22, 27 VDD Power Positive power supply pins. 4 OE/nRST Input Output enable and asynchronous reset. Resets all outputs. Logic LOW, the outputs are in a high impedance state. Logic HIGH enables all outputs. Internally a Power On reset circuit will ensure that the nQ5 output is inverted relative to Q[4:0]. If OE/nRST is pulsed low, it must be held low for a minimum of 10 ns for a complete reset operation. This reset may be applied asynchronously to the input reference. 5 FEEDBACK Input PLL feedback input which is connected to one of the clock outputs to close the PLL feedback loop. LVCMOS/LVTTL interface levels. 6 REF_SEL Input Input reference clock select. Logic LOW selects the SYNC0. Logic HIGH selects the SYNC1 input as the PLL reference input. LVCMOS/LVTTL interface levels. 7, 11 SYNC0, SYNC1 Input Single-ended reference clock inputs. LVCMOS/LVTTL interface levels. 8 AVDD Power Positive power supply for the PLL. Output phase synchronization. In PLL mode (PLL_EN = HIGH) and when logic LOW, the rising edges of the outputs (2XQ, Q0:Q4, Q/2) are synchronized to the rising edge of the selected reference clock (SYNCn). In PLL mode (PLL_EN = HIGH) and when logic HIGH, the falling edges of the outputs (2XQ, Q0:Q4, Q/2) are synchronized to the falling edge of the selected reference clock (SYNCn). LVCMOS/LVTTL interface levels. 9 nPE Input Pulldown 10 AGND Power Power supply ground for the PLL. Internally connected to GND. 12 FREQ_SEL Input Frequency select. Logic LOW level inserts a divide-by-2 into the PLL output and feedback path. Logic HIGH inserts a divide-by-1 into the PLL output and feedback path. LVCMOS/LVTTL interface levels. 14, 16, 21, 23, 28 Q0, Q1, Q2, Q3, Q4 Output 18 PLL_EN Input PLL enable. Enable and disables the PLL. Logic HIGH enables the PLL. Logic LOW disables the PLL and the input reference signal is routed to the output dividers (PLL bypass). LVCMOS/LVTTL interface levels. 19 LOCK Output PLL lock indication output. Logic HIGH indicates PLL lock. Logic LOW indicates PLL is not locked. LVCMOS/LVTTL interface levels. 25 Q/2 Output Single-ended clock output. LVCMOS/LVTTL interface levels. 26 2XQ Output Single-ended clock output. LVCMOS/LVTTL interface levels. Single-ended clock outputs. LVCMOS/LVTTL interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. LVCMOS CLOCK GENERATOR 3 REVISION C 11/6/15 870919I-01 DATA SHEET Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance (total) RPULLDOWN Input Pulldown Resistor ROUT Test Conditions VDD = AVDD = 3.6V nPE Output Impedance Minimum Typical Maximum Units 4 pF 330 pF 56 k 11  Device Configuration The 870919I-01 requires a connection of one of the clock outputs to the FEEDBACK input to close the PLL feedback path. The selection of the output (output divider) for PLL feedback will impact the device configuration and input to output frequency ratio and frequency ranges. See Table 3G for details. Function Tables Table 3A. OE/nRST Mode Configuration Table Input OE/nRST Operation 0 Device is reset and the outputs Q0:Q4, nQ5, 2XQ, Q/2 are in high-impedance state. This control is asynchronous. 1 Outputs are enabled. Table 3B. REF_SEL Mode Configuration Table Input REF_SEL Operation 0 SYNC0 is the selected PLL reference clock. 1 SYNC1 is the selected PLL reference clock. Table 3C. nPE Mode Configuration Table Input nPE Operation 0 The rising edge of the 2XQ, Q0:Q4 and Q/2 outputs and the falling edge of the nQ5 output are synchronized. 1 The falling edge of the 2XQ, Q0:Q4 and Q/2 outputs and the rising edge of the nQ5 output are synchronized. REVISION C 11/6/15 4 LVCMOS CLOCK GENERATOR 870919I-01 DATA SHEET Table 3D. FREQ_SEL Mode Configuration Table Input FREQ_SEL Operation 0 The VCO output is frequency-divided by 2. This setting allows for a lower input frequency range. See also table 3G for available frequency ranges. 1 The VCO output is frequency-divided by 1. This setting allows for a higher input frequency range. See also table 3G for available frequency ranges. Table 3E. PLL_EN Mode Configuration Table Input PLL_EN Operation 0 The PLL is bypassed. The selected input reference clock is routed to the output dividers for low-frequency board test purpose. The PLL-related AC specifications do not apply in PLL bypass mode. 1 The PLL is enabled and locks to the selected input reference signal. Table 3F. LOCK Mode Configuration Table Output LOCK Operation 0 PLL is not locked to the selected input reference clock. 1 PLL is locked to the selected input reference clock. Table 3G. Frequency Configuration Table Outputs Used for PLL Feedback Input Frequency Range (MHz) Output Frequency Range (MHz) and Output-to-Input Frequency Multiplication Factor FREQ_SEL SYNC[0:1] Q[0:4], nQ5NOTE1 2XQ Q/2 0 5 - 40 5 - 40 (1x) 10 - 80 (2x) 2.5 - 20 (0.5x) 1 10 - 80 10 - 80 (1x) 20 - 160 (2x) 5 - 40 (0.5x) 0 10 - 80 5 - 40 (0.5x) 10 - 80 (1x) 2.5 - 20 (0.25x) 10 - 50 (0.5x) 20 - 100 (1x) 5 - 25 (0.25x) Q0, Q1, Q2, Q3, Q4 or nQ5 2XQ 1 20 - 100 NOTE2 0 2.5 - 20 5 - 40 (2x) 10 - 80 (4x) 2.5 - 20 (1x) 1 5 - 40 10 - 80 (2x) 20 - 160 (4x) 5 - 40 (1x) Q/2 NOTE 1: The nQ5 output is inverted (180° phase shift) with respect to Q0:Q4. NOTE 2: The input reference frequency is limited to 100MHz maximum. LVCMOS CLOCK GENERATOR 5 REVISION C 11/6/15 870919I-01 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD(ABS MAX) 4.6V Inputs, VI -0.5V to VDD(ABS MAX) + 0.5V Outputs, VO -0.5V to VDD(ABS MAX) + 0.5V Package Thermal Impedance, JA 28 Lead QSOP 28 Lead PLCC 66.0°C/W (0 lfpm) 46.4°C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = AVDD = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter Test Conditions VDD, AVDD Positive Supply Voltage IDDQ Quiescent Power Supply Current Minimum Typical Maximum Units 3.0 3.3 3.6 V 5 mA VDD = AVDD = max., OE/nRST = 0, SYNCx = 0, all outputs open Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = AVDD = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current Test Conditions Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V FREQ_SEL, FEEDBACK, SYNCn, OE/nRST, REF_SEL, PLL_EN VDD = VIN = 3.3V 5 µA nPE VDD = VIN = 3.3V 150 µA IIL Input Low Current FREQ_SEL, FEEDBACK, nPE, SYNCn, OE/nRST, REF_SEL, PLL_EN VOH Output High Voltage Q0:Q4, nQ5, 2XQ, Q/2, LOCK IOH = -24mA VOL Output Low Voltage Q0:Q4, nQ5, 2XQ, Q/2, LOCK IOL = 24mA 0.5 V IOZ Output Leakage Current Q0:Q4, nQ5, 2XQ, Q/2 OE/nRST = 0, VOUT = 0V or VDD, VDD = 3.6V ±5 µA REVISION C 11/6/15 VDD = 3.3V, VIN = 0V -5 µA 2.6 V 6 LVCMOS CLOCK GENERATOR 870919I-01 DATA SHEET Table 5. AC Electrical Characteristics, VDD = AVDD = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter fREF SYNC[0:1] Input Reference Frequency Test Conditions Minimum Feedback of Q[0:4] or nQ5, FREQ_SEL = 0 Typical Maximum Units 5 40 MHz Feedback of Q[0:4] or nQ5, FREQ_SEL = 1 10 80 MHz Feedback of 2XQ, FREQ_SEL = 0 10 80 MHz Feedback of 2XQ or FREQ_SEL = 1 20 100 MHz Feedback of Q/2, FREQ_SEL = 0 2.5 20 MHz Feedback of Q/2 or FREQ_SEL = 1 5 40 MHz 2XQ 160 MHz Q[0:4], nQ5 80 MHz 40 MHz 75 % fOUT Output Frequency idc Input Duty Cycle SYNC0, SYNC1 tR / tF Input Rise/ Fall Time SYNC0, SYNC1 3 ns Output Skew; NOTE 1, 2 Rising edges of Q[0:4] (incl. Q/2 if nPE = 0) 300 ps Output Skew; NOTE 1, 2 Falling edges of Q[0:4] (incl. Q/2 if nPE = 1) 300 ps Rising edge of Q[0:4] 2XQ, Q/2 and Falling edge of nQ5 500 ps Q/2 tsk(o) Output Skew; NOTE 1, 2, 3 2XQ tPW Pulse Width 25 >40MHz tPERIOD/2 - 0.62 tPERIOD/2 + 0.62 ns Q[0:4], nQ5 80MHz tPERIOD/2 - 0.45 tPERIOD/2 + 0.45 ns Q/2 40MHz tPERIOD/2 - 0.6 tPERIOD/2 + 0.6 ns 150 ps Q[0:4], nQ5 20MHz, FREQ_SEL = 0 Q[0:4], nQ5 20MHz, FREQ_SEL = 1 320 ps Q[0:4], nQ5 80MHz and nPE = 0 0 300 ps Q[0:4], nQ5 80MHz and nPE = 1 -80 300 ps Low-to-High 14 ns OE/nRST High-to-Low 14 ns Q[0:4], nQ5, 2XQ, Q/2 0.8V – 2.0V 2 ns 10 ms tjit(cc) Cycle-to-Cycle Jitter t Static Phase Offset, (SYNC[0:1] to FEEDBACK delay); NOTE 2, 4 tPZH, tPZL Output Enable Time; NOTE 5 OE/nRST tPHZ, tPLZ Output Disable Time; NOTE 5 tR / tF Output Rise/ Fall Time tLOCK PLL Lock Time 0.2 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Measured between coincident rising output edges of Q0:Q4, 2XQ, Q/2 and the falling edge of nQ5. NOTE 4: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. LVCMOS CLOCK GENERATOR 7 REVISION C 11/6/15 870919I-01 DATA SHEET Parameter Measurement Information tsk(o) 1.65V±0.15V 2xQ SCOPE VDD, AVDD Qx Qx Qy tsk(o) GND Q/2 -1.65V±0.15V tsk(o) 3.3V Output Load AC Test Circuit Output Skew VDD 2 SYNC[0:1] Q[0:4], nQ5 VDD ➤ ➤ tcycle n+1 ➤ 2 ➤ t(Ø) ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles ➤ tcycle n FEEDBACK t(Ø) mean = Static Phase Offset Where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges Static Phase Offset for nPE = 0 Cycle-to-Cycle Jitter Static Phase Offset SYNC[0:1] VDD 2 FEEDBACK Q[0:4], nQ5, 2XQ, Q/2 VDD Pulse Width 2 t PERIOD ➤ ➤ t(Ø) Static Phase Offset for nPE = 1 Static Phase Offset REVISION C 11/6/15 Output Pulse Width 8 LVCMOS CLOCK GENERATOR 870919I-01 DATA SHEET Parameter Measurement Information VDD OE (High-level enabling) 2V Q0:Q4, nQ5, Q/2, 2XQ VDD/2 VDD/2 0V 2V 0.8V 0.8V tR tEN tF Output Qx (See Note) tDIS VDD/2 VOH VDD/2 VOL Output Rise/Fall Time Output Enable/Disable Application Information Recommendations for Unused Output Pins Outputs: LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. REVISION C 11/6/15 9 LVCMOS CLOCK GENERATOR 870919I-01 DATA SHEET Schematic Layout Figure 1 shows an example of 870919I-01 application schematic. In this example, the device is operated at VDD=AVDD=3.3V. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 870919I-01 provides separate power supplies to isolate any high switching noise from coupling into the internal PLL. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10 kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1µFcapacitor in each power pin filter should be placed on the device side. The other components can be on the opposite side of the PCB. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. R1 AVDD VDD FEEDBACK 1-2 C1 10uF C2 0.1uF U1 R2 VDD AGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 nQ5 R6 VDD QE/nRST C3 0.1uF 0 REF_SEL SYNC0 nPE SYNC1 FREQ_SEL VDD Q0 Q1 Ro ~ 7 O hm R3 GND nQ5 VDD OE/nRST FEEDBACK REF_SEL SYNC0 AVDD nPE AGND SYNC1 FREQ_SEL GND Q0 Q4 VDD 2XQ Q/ 2 GND Q3 VDD Q2 GND LOCK PLL_EN GND Q1 VDD 28 27 26 25 24 23 22 21 20 19 18 17 16 15 35 VDD 2XQ Q/2 C4 0.1uF VDD Q3 Q2 C5 0.1uF LOCK PLL_EN Q1 Zo = 50 Ohm VDD C6 0.1uF 43 Driver_LVCMOS 3.3V muRata, BLM18BB221SN1 1 2 FB1 Logic Control Input Examples Set Logic Input to '1' VDD RU1 1K C8 C7 0.1uF Q0 To Log ic Inpu t pins To Lo gic Inp ut pin s R4 Zo = 50 10uF 39 Receiver Set Logic Input to '0' VDD RU2 Not Install RD1 Not I nst all VDD V DD=3.3V Unused output can be left floating. There should no trace attached to unused output. Device characterized with all outputs terminated. 2XQ R5 Zo = 50 39 RD2 1K Receiver Figure 1. 870919I-01 Application Schematic REVISION C 11/6/15 10 LVCMOS CLOCK GENERATOR 870919I-01 DATA SHEET Power Considerations This section provides information on power dissipation and junction temperature for the 870919I-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 870919I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results. • Power (core)MAX = VDD_MAX * IDD_MAX= 3.6V *5mA = 18mW • Output Impedance ROUT Power Dissipation due to Loading 50 to VDD/2 Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.6V / [2 * (50 + 11)] = 29.5mA • Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 11 * (29.5mA)2 = 9.57mW per output • Total Power (ROUT) = ROUT (per output) * number of outputs = 9.57mW * 8 outputs = 76.56mW Dynamic Power Dissipation for Q = 80MHz Power (80MHz) = CPD * Frequency * (VDD)2 = 330pF * 80MHz * (3.6V)2 = 342mW Total Power = Power (core)MAX + Total Power (ROUT) + Power (80MHz) = 18mW + 76.56mW + 342mW = 436.56mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 66°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.437W * 66°C/W = 113.8°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for a 28 Lead QSOP, Forced Convection JA by Velocity Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards LVCMOS CLOCK GENERATOR 0 200 500 66.0°C/W 58.3°C/W 55.2°C/W 11 REVISION C 11/6/15 870919I-01 DATA SHEET Package Outline - R Suffix for 28 Lead QSOP, 150MIL Table 7B. Package Dimensions for 28 Lead QSOP All Dimensions in Millimeters Symbol Minimum Maximum N 28 A 1.35 1.75 A1 0.10 0.25 A2 1.50 b 0.20 0.30 c 0.18 0.25 D 9.80 10.00 E 5.80 6.20 E1 3.80 4.00 e 0.635 Basic L 0.40 1.27  0° 8° ZD 0.84 Ref Reference Document: JEDEC Publication 95, MO-137 Reliability Information Table 8A. JA vs. Air Flow Table for a 28 Lead QSOP, 150MIL JA vs. Air Flow Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 66.0°C/W 58.3°C/W 55.2°C/W 0 200 500 46.4°C/W 38.6°C/W 36.2°C/W Table 8B. JA vs. Air Flow Table for a 28 Lead PLCC JA vs. Air Flow Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for 870919I-01: 1654 REVISION C 11/6/15 12 LVCMOS CLOCK GENERATOR 870919I-01 DATA SHEET Ordering Information Table 9. Ordering Information Part/Order Number 870919BRI-01LF 870919BRI-01LFT Marking 870919BRI-01L 870919BRI-01L Package “Lead-Free” 28 Lead QSOP “Lead-Free” 28 Lead QSOP Shipping Packaging Tube 2500 Tape & Reel Temperature -40C to 85C -40C to 85C NOTE: "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. LVCMOS CLOCK GENERATOR 13 REVISION C 11/6/15 870919I-01 DATA SHEET Revision History Sheet Rev Table Page Description of Change Date A 2 B 3, 6 Updated Pin 4, OE/nRST Description; changed VDD to VDD (ABS MAX). C 10 Added Application Schematic T9 14 Removed leaded orderable parts from the Ordering Information table 11/15/12 Crossed out PLCC package. Removed PLCC package drawing. Ordering Information - removed PLCC part number. 11/6/15 9 2 12 14 C C REVISION C 11/6/15 QSOP Pin Assignment - added dimensions. 7/7/09 11/15/11 1/6/12 14 LVCMOS CLOCK GENERATOR Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright ©2015 Integrated Device Technology, Inc.. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.