874001AGI-02LF

PCI Express™ Jitter Attenuator ICS874001I-02 DATA SHEET General Description Features The ICS874001I-02 is a high performance Jitter Attenuator designed for use in PCI Express™ systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874001I-02 has two different PLL bandwidth modes: 2MHz and 3MHz. The 2MHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. The 3MHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth mode. The 874001I-02 can be set for different modes using the F_SELx pins, as shown in Table 3C. • • • One differential LVDS output pair • • • • • • Input frequency range: 98MHz to 128MHz • • • Full 3.3V or 2.5V operating supply The ICS874001I-02 uses IDT’s 3RD Generation FemtoClock® PLL technology to achieve the lowest possible phase noise. The device is packaged in a small 20-pin TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. One differential clock input CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL Output frequency range: 98MHz to 640MHz VCO range: 490MHz - 640MHz Cycle-to-cycle jitter: 15ps (maximum), 3.3V RMS period jitter: 3ps (maximum), 3.3V Two bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package PLL Bandwidth Control Table BW_SEL 0 = PLL Bandwidth: 2MHz (default) Pin Assignment 1 = PLL Bandwidth: 3MHz PLL_SEL nc nc nc MR BW_SEL F_SEL1 PLL_SEL Control Table PLL_SEL 0 = Bypass 1 = VCO (default) VDDA F_SEL0 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nc VDDO Q nQ nc nc GND nCLK CLK OE ICS874001I-02 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View ICS874001AGI-02 REVISION A AUGUST 30, 2010 1 ©2010 Integrated Device Technology, Inc. ICS74001I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Block Diagram PLL_SEL Pullup BW_SEL Pulldown 0 = 2MHz 1 = 3MHz 0 CLK Pulldown nCLK Pullup Phase Detector VCO 490 - 640MHz 1 Output Divider 0 0 ÷5 0 1 ÷4 1 0 ÷2 (default) 1 1 ÷1 Q nQ Internal Feedback ÷5 F_SEL[1:0] Pullup/Pulldown 2 MR Pulldown OE Pullup ICS874001AGI-02 REVISION A AUGUST 30, 2010 2 ©2010 Integrated Device Technology, Inc. ICS74001I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Table 1. Pin Descriptions Number Name Type 1 PLL_SEL Input 2, 3, 4, 15, 16, 20 nc Unused Description Pullup PLL select pin. When LOW, bypasses the VCO. When HIGH selects VCO. LVCMOS/LVTTL interface levels. No connect. 5 MR Input Pulldown Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true output Q to go LOW and the inverted output nQ to go HIGH. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 6 BW_SEL Input Pulldown PLL Bandwidth select pin. LVCMOS/LVTTL interface levels. See Table 3B. 7 F_SEL1 Input Pullup Frequency select pin. See Table 3C. LVCMOS/LVTTL interface levels. 8 VDDA Power 9 F_SEL0 Input Analog supply pin. 10 VDD Power 11 OE Input Pullup 12 CLK Input Pulldown 13 nCLK Input Pullup 14 GND Power Power supply ground. 17, 18 nQ, Q Output Differential output pair. LVDS interface levels. 19 VDDO Power Output supply pin. Pulldown Frequency select pin. See Table 3C. LVCMOS/LVTTL interface levels. Core supply pin. Output enable. When HIGH, outputs are enabled. When LOW, forces outputs to High-Impedance state. LVCMOS/LVTTL interface levels. See Table 3A. Non-inverting differential clock input. Inverting differential clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ICS874001AGI-02 REVISION A AUGUST 30, 2010 Test Conditions 3 Minimum Typical Maximum Units ©2010 Integrated Device Technology, Inc. ICS74001I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Function Tables Table 3A. Output Enable Function Table Inputs Outputs OE Q, nQ 0 High-Impedance 1 Enabled Table 3B. PLL Bandwidth Control Table Inputs BW_SEL PLL Bandwidth 0 2MHz (default) 1 3MHz Table 3C. F_SELx Function Table Inputs Input Frequency (MHz) F_SEL1 F_SEL0 Divider Output Frequency (MHz) 100 0 0 ÷5 100 100 0 1 ÷4 125 100 1 0 ÷2 250 (default) 100 1 1 ÷1 500 ICS874001AGI-02 REVISION A AUGUST 30, 2010 4 ©2010 Integrated Device Technology, Inc. ICS74001I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 86.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Core Supply Voltage VDDA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VDD – 0.12 3.3 VDD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 72 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 24 mA Table 4B. Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Core Supply Voltage VDDA Minimum Typical Maximum Units 2.375 2.5 2.625 V Analog Supply Voltage VDD – 0.12 2.5 VDD V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 70 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 22 mA ICS874001AGI-02 REVISION A AUGUST 30, 2010 Test Conditions 5 ©2010 Integrated Device Technology, Inc. ICS74001I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Test Conditions Minimum VDD = 3.465V Typical Maximum Units 2 VDD + 0.3 V VDD = 2.625V 1.7 VDD + 0.3 V VDD = 3.465V -0.3 0.8 V VDD = 2.625V -0.3 0.7 V F_SEL0, MR, BW_SEL VDD = VIN = 3.465V or 2.625V 150 µA F_SEL1, OE, PLL_SEL VDD = VIN = 3.465V or 2.625V 5 µA F_SEL0, MR, BW_SEL VDD = 3.465V or 2.625V, VIN = 0V -5 µA F_SEL1, OE, PLL_SEL VDD = 3.465V or 2.625V, VIN = 0V -150 µA Input High Current Input Low Current Table 4D. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol IIH IIL Parameter Test Conditions Minimum Typical Maximum Units CLK VDD = VIN = 3.465V or 2.625V 150 µA nCLK VDD = VIN = 3.465V or 2.625V 5 µA CLK VDD = 3.465V or 2.625V, VIN = 0V -5 µA nCLK VDD = 3.465V or 2.625V, VIN = 0V -150 µA Input High Current Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 0.15 1.3 V GND + 0.5 VDD – 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4E. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS VOS Magnitude Change ICS874001AGI-02 REVISION A AUGUST 30, 2010 Test Conditions Minimum Typical Maximum Units 300 390 480 mV 50 mV 1.6 V 50 mV 1.2 6 1.4 ©2010 Integrated Device Technology, Inc. ICS74001I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Table 4F. LVDS DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 300 390 480 mV 50 mV 1.4 V 50 mV 1.0 1.2 AC Electrical Characteristics Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 tjit(per) RMS Period Jitter; NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 98 2 Maximum Units 640 MHz 15 ps 3 ps 470 ps 20% to 80% 230 N≠1 47 53 % N=1 40 60 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. Table 5B. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 tjit(per) RMS Period Jitter; NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 98 2 20% to 80% 230 Maximum Units 640 MHz 20 ps 4 ps 500 ps N≠1 47 53 % N=1 40 60 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. ICS874001AGI-02 REVISION A AUGUST 30, 2010 7 ©2010 Integrated Device Technology, Inc. ICS74001I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Parameter Measurement Information SCOPE SCOPE VDD, VDDO 3.3V±5% POWER SUPPLY + Float GND – 2.5V±5% POWER SUPPLY + Float GND – Q VDDA VDD, VDDO Q VDDA nQ nQ 3.3V LVDS Output Load AC Test Circuit 2.5V LVDS Output Load AC Test Circuit VDD nQ Q nCLK ➤ V Cross Points PP ➤ V ➤ tcycle n CMR tcycle n+1 ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles CLK GND Differential Input Level Cycle-to-Cycle Jitter nQ nQ Q 80% 80% t PW t VOD Q 20% 20% tR tF odc = PERIOD t PW x 100% t PERIOD Output Duty Cycle/Pulse Width/Period Output Rise/Fall Time ICS874001AGI-02 REVISION A AUGUST 30, 2010 8 ©2010 Integrated Device Technology, Inc. ICS74001I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Parameter Measurement Information, continued VOH VDD VREF LVDS out Histogram ➤ VOS/∆ VOS ➤ (Trigger Edge) DC Input ➤ VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Reference Point out Mean Period (First edge after trigger) RMS Period Jitter Offset Voltage Setup VDD LVDS 100 ➤ VOD/∆ VOD out ➤ DC Input ➤ out Differential Output Voltage Setup ICS874001AGI-02 REVISION A AUGUST 30, 2010 9 ©2010 Integrated Device Technology, Inc. ICS74001I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR ApplicationS Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS874001I-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V or 2.5V VDD .01µF 10Ω .01µF 10µF VDDA Figure 1. Power Supply Filtering Wiring the Differential Input to Accept Single-Ended Levels Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50Ω applications, R3 and R4 can be 100Ω. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS874001AGI-02 REVISION A AUGUST 30, 2010 10 ©2010 Integrated Device Technology, Inc. ICS74001I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK CLK Zo = 50Ω Zo = 50Ω nCLK nCLK Differential Input LVHSTL R1 50Ω IDT LVHSTL Driver R2 50Ω Differential Input LVPECL R1 50Ω R2 50Ω R2 50Ω 3A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver Figure 3B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V R3 125Ω 3.3V 3.3V R4 125Ω Zo = 50Ω Zo = 50Ω CLK CLK R1 100Ω Zo = 50Ω nCLK R1 84Ω R2 84Ω nCLK Zo = 50Ω Differential Input LVPECL Receiver LVDS Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver 2.5V 3.3V 3.3V 3.3V 2.5V *R3 33Ω R3 120Ω Zo = 50Ω R4 120Ω Zo = 60Ω CLK CLK Zo = 50Ω Zo = 60Ω nCLK nCLK HCSL *R4 33Ω R1 50Ω R2 50Ω Differential Input SSTL R1 120Ω R2 120Ω Differential Input *Optional – R3 and R4 can be 0Ω Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver Figure 3E. CLK/nCLK Input Driven by a 3.3V HCSL Driver ICS874001AGI-02 REVISION A AUGUST 30, 2010 11 ©2010 Integrated Device Technology, Inc. ICS74001I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Recommendations for Unused Input Pins Inputs: LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. LVDS Driver Termination A general LVDS interface is shown in Figure 4. Standard termination for LVDS type output structure requires both a 100Ω parallel resistor at the receiver and a 100Ω differential transmission line environment. In order to avoid any transmission line reflection issues, the 100Ω resistor must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 4 can be used with either type of output structure. If using a non-standard termination, it is recommended to contact IDT and confirm if the output is a current source or a voltage source type structure. In addition, since these outputs are LVDS compatible, the amplitude and common mode input range of the input receivers should be verified for compatibility with the output. + LVDS Driver LVDS Receiver 100Ω – 100Ω Differential Transmission Line Figure 4. Typical LVDS Driver Termination ICS874001AGI-02 REVISION A AUGUST 30, 2010 12 ©2010 Integrated Device Technology, Inc. ICS74001I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Schematic Layout possible to the power pin. The input is driven by a 3.3V LVPECL driver. Figure 5 shows an example of ICS874001I-02 application schematic. In this example, the device is operated at VDD = 3.3V. The decoupling capacitors should be located as close as U1 PLL_SEL 1 2 3 4 5 6 7 8 9 10 VDD = 3.3V VDD MR BW_SEL F_SEL1 VDDA 10 R2 F_SEL0 C1 0.1u C2 10u VDDO = 3.3V PLL_SEL nc nc nc MR BW_SEL F_SEL1 VDDA F_SEL0 VDD nc VDDO Q nQ nc nc GND nCLK CLK OE 20 19 18 17 16 15 14 13 12 11 VDDO Q nQ Q Zo = 50 Ohm + GND nCLK CLK OE R1 100 nQ - Zo = 50 Ohm Zo = 50 Ohm Zo = 50 Ohm LVPECL Driv er R6 50 R7 50 Logic Control Input Examples Set Logic Input to '1' VDD RU1 1K Set Logic Input to '0' VDD R8 50 Q VDDO (U1:19) C5 .1uf RU2 Not Install To Logic Input pins RD1 Not Install RD2 1K VDD(U1:10) C6 10uf R4 50 C7 .1uf nQ To Logic Input pins Zo = 50 Ohm Zo = 50 Ohm C3 0.1uF R5 50 + - Alternate LVDS Termination Figure 5. ICS874001I-02 Schematic Layout ICS874001AGI-02 REVISION A AUGUST 30, 2010 13 ©2010 Integrated Device Technology, Inc. ICS74001I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Power Considerations This section provides information on power dissipation and junction temperature for theICS874001I-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS874001I-02 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (72mA + 12mA) = 291.06mW • Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 24mA = 83.16mW Total Power_MAX = 291.06mW + 83.16mW = 374.22mW • 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 86.7°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.374W * 86.7°C/W = 117°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS874001AGI-02 REVISION A AUGUST 30, 2010 0 1 2.5 86.7°C/W 82.4°C/W 80.2°C/W 14 ©2010 Integrated Device Technology, Inc. ICS74001I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Reliability Information Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 86.7°C/W 82.4°C/W 80.2°C/W Transistor Count The transistor count for ICS874001I-02 is: 1,608 Package Outline and Package Dimensions Package Outline - G Suffix for 20 Lead TSSOP Table 8 Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS874001AGI-02 REVISION A AUGUST 30, 2010 15 ©2010 Integrated Device Technology, Inc. ICS74001I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Ordering Information Table 9. Ordering Information Part/Order Number 874001AGI-02LF 874001AGI-02LFT Marking ICS4001AI02L ICS4001AI02L Package “Lead-Free” 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. ICS874001AGI-02 REVISION A AUGUST 30, 2010 16 ©2010 Integrated Device Technology, Inc. ICS74001I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. 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