87946AYI-01LF

87946I-01 1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL 2.5V, 3.3V Fanout Buffer Datasheet PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 General Description Features The 87946I-01 is a low skew, ÷1, ÷2 Fanout Buffer. The 87946I-01 has one LVPECL clock input pair. The PCLK/nPCLK pair can accept LVPECL, CML, or SSTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 10 to 20 by utilizing the ability of the outputs to drive two series terminated lines. • Ten single ended LVCMOS/LVTTL outputs, 7 typical output impedance • • LVPECL clock input pair • • • • • • Maximum input frequency: 250MHz • • Available in lead-free (RoHS 6) package The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master reset input, MR/nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. The 87946I-01 is characterized at 3.3V core/3.3V output and 3.3V core/2.5V output. Guaranteed bank, output and part-to-part skew characteristics make the 87946I-01 ideal for those clock distribution applications demanding well defined performance and repeatability. PCLK/nPCLK supports the following input levels: LVPECL, CML, SSTL Output skew: 120ps (maximum) Part-to-part skew: 700ps (maximum) Multiple frequency skew: 320ps (maximum) Additive phase jitter, RMS: 0.19ps (typical) 3.3V core, 3.3V or 2.5V output supply modes-40°C to 85°C ambient operating temperature For functional replacement use 87946i-147 Pin Assignment VDDA QA2 GND QA1 VDDA QA0 GND MR/nOE Block Diagram 32 31 30 29 28 27 26 25 0 3 QB0:QB2 1 DIV_SELB Pulldown 0 4 QB0 22 VDDB nPCLK 4 21 QB1 DIV_SELA 5 20 GND DIV_SELB 6 19 QB2 DIV_SELC 7 18 VDDB GND 8 17 VDDC 9 10 11 12 13 14 15 16 87946I-01 QC0:QC3 32-Lead LQFP 7mm x 7mm x 1.45mm package body Y Package Top View 1 DIV_SELC Pulldown MR/nOE Pulldown ©2015 Integrated Device Technology, Inc. 23 3 QC3 DIV_SELA Pulldown 2 QC2 1 VDD PCLK GND ÷2 GND QC1 QA0:QA2 24 VDDC 3 GND 0 QC0 ÷1 1 VDDC PCLK Pulldown nPCLK Pullup nc 1 Revision C, September 20, 2016 87946I-01 Datasheet Table 1. Pin Descriptions Number Name 1 nc Unused 2 VDD Power 3 PCLK Input Pulldown 4 nPCLK Input Pullup 5 DIV_SELA Input Pulldown Controls frequency division for Bank A outputs. See Table 3 LVCMOS/LVTTL interface levels. 6 DIV_SELB Input Pulldown Controls frequency division for Bank B outputs. See Table 3. LVCMOS/LVTTL interface levels. 7 DIV_SELC Input Pulldown Controls frequency division for Bank C outputs. See Table 3. LVCMOS/LVTTL interface levels. 8, 11, 15, 20, 24, 27, 31 GND Power Power supply ground. 9, 13, 17 VDDC Power Output supply pins for Bank C outputs. 10, 12, 14, 16 QC0, QC1, QC2, QC3 Output Single-ended Bank C clock outputs. LVCMOS/LVTTL interface levels. 7 typical output impedance. 18, 22 VDDB Power Output supply pins for Bank B outputs. 19, 21, 23 QB2, QB1, QB0 Output Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels. 7 typical output impedance. 25, 29 VDDA Power Output supply pins for Bank A outputs. 26, 28, 30 QA2, QA1, QA0 Output Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels. 7 typical output impedance. 32 MR/nOE Type Input Description No connect. Power supply pin. Pulldown Non-inverting differential LVPECL clock input. Inverting differential LVPECL clock input. Active HIGH Master Reset. Active LOW Output Enable. When logic HIGH, the internal dividers are reset and the outputs are High-Impedance (Hi-Z). When logic LOW, the internal dividers and the outputs are enabled. See Table 3. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance RPULLUP Input Pullup Resistor Test Conditions Minimum VDD = VDDA = VDDB = VDDC = 3.465V Output Impedance ©2015 Integrated Device Technology, Inc. Maximum 4 5 2 Units pF 23 RPULLDOWN Input Pulldown Resistor ROUT Typical pF 51 k 51 k 7 12  Revision C, September 20, 2016 87946I-01 Datasheet Function Tables Table 3. Clock Input Function Table Inputs Outputs MR/nOE DIV_SELA DIV_SELB DIV_SELC QA0:QA2 QB0:QB2 QC0:QC3 1 X X X High-Impedance High-Impedance High-Impedance 0 0 X X fIN/1 Active Active 0 1 X X fIN/2 Active Active 0 X 0 X Active fIN/1 Active 0 X 1 X Active fIN/2 Active 0 X X 0 Active Active fIN/1 0 X X 1 Active Active fIN/2 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDx + 0.5V Package Thermal Impedance, JA 47.9C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = VDDA = VDDB = VDDC = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V VDDA, VDDB, VDDC Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 54 mA IDDA, IDDB, IDDC Output Supply Current 23 mA ©2015 Integrated Device Technology, Inc. Test Conditions 3 Revision C, September 20, 2016 87946I-01 Datasheet Table 4B. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDA = VDDB = VDDC = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions VDD Positive Supply Voltage VDDA, VDDB, VDDC Output Supply Voltage Minimum Typical Maximum Units 3.135 3.3 3.465 V 2.375 2.5 2.625 V IDD Power Supply Current 54 mA IDDA, IDDB, IDDC Output Supply Current 22 mA Maximum Units Table 4C. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum VIH Typical Input High Voltage VDD = 3.465V 2 VDD + 0.3 V VIL Input Low Voltage VDD = 3.465V -0.3 0.8 V IIH Input High Current VDD = VIN = 3.465V 150 µA IIL Input Low Current VDD = 3.465V, VIN = 0V -5 µA VOH OUtput High Voltage; NOTE 1 VDDA = VDDB = VDDC = 3.465V 2.6 V VOL Output Low Voltage; NOTE 1 VDDA = VDDB = VDDC = 3.465V or 2.525V IOZL Output Hi-Z Current Low IOZH Output Hi-Z Current High 0.5 -5 V µA 5 µA NOTE 1: Outputs terminated with 50 to VDDx/2. See Parameter Measurement Information section. Load Test Circuit diagrams. Table 4D. LVPECL DC Characteristics, TA = -40°C to 85°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage VCMR Common Mode Input Voltage; NOTE 1 Minimum Typical Maximum Units PCLK VDD = VIN = 3.465V 150 µA nPCLK VDD = VIN = 3.465V 5 µA PCLK VDD = 3.465V, VIN = 0V -5 µA nPCLK VDD = 3.465V, VIN = 0V -150 µA 0.3 1.0 V GND + 1.5 VDD V NOTE 1: Common mode input voltage is defined as VIH. ©2015 Integrated Device Technology, Inc. 4 Revision C, September 20, 2016 87946I-01 Datasheet AC Electrical Characteristics Table 5A. AC Characteristics, VDD = VDDA = VDDB = VDDC = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter fMAX Output Frequency Test Conditions ƒ  250MHz Minimum 2.3 Typical Units 250 MHz tPD Propagation Delay; NOTE 1 3.8 ns tsk(b) Bank Skew, NOTE 2, 7 Measured on rising edge at VDDX/2 30 ps tsk(o) Output Skew; NOTE 3, 7 Measured on rising edge at VDDX/2 130 ps tsk(w) Multiple Frequency Skew; NOTE 4, 7 Measured on rising edge at VDDX/2 320 ps tsk(pp) Part-to-Part Skew; NOTE 5, 7 Measured on rising edge at VDDX/2 700 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section t R / tF Output Rise/Fall Time odc Output Duty Cycle tEN Output Enable Time; NOTE 6 tDIS Output Disable Time; NOTE 6 125MHz, 12kHz – 20MHz 20% to 80% 3.1 Maximum 0.19 400 ps 950 ps 60 % ƒ = 10MHz 3 ns ƒ = 10MHz 3 ns 40 50 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to VDDX/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDX/2. NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltage and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDX/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. Table 5B. AC Characteristics, VDD = 3.3V ± 5%, VDDA = VDDB = VDDC = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 tsk(b) Bank Skew, NOTE 2, 7 tsk(o) Test Conditions Maximum Units 250 MHz 3.8 ns Measured on rising edge at VDDX/2 35 ps Output Skew; NOTE 3, 7 Measured on rising edge at VDDX/2 120 ps tsk(w) Multiple Frequency Skew; NOTE 4, 7 Measured on rising edge at VDDX/2 325 ps tsk(pp) Part-to-Part Skew; NOTE 5, 7 Measured on rising edge at VDDX/2 700 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section t R / tF Output Rise/Fall Time odc Output Duty Cycle 57 % tEN Output Enable Time; NOTE 6 ƒ = 10MHz 3 ns tDIS Output Disable Time; NOTE 6 ƒ = 10MHz 3 ns 5 Revision C, September 20, 2016 ƒ  250MHz Minimum 2.5 125MHz, 12kHz – 20MHz 20% to 80% Typical 3.2 0.19 350 40 ps 800 50 ps For NOTES, please see Table 5A above. ©2015 Integrated Device Technology, Inc. 87946I-01 Datasheet Additive Phase Jitter fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the SSB Phase Noise dBc/Hz Additive Phase Jitter @ 125MHz 12kHz to 20MHz = 0.19ps (typical) Offset Frequency (Hz) This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. ©2015 Integrated Device Technology, Inc. 6 Revision C, September 20, 2016 87946I-01 Datasheet Parameter Measurement Information 2.05V¬±5 1.65V¬±5 1.25V¬±5 SCOPE VDD, VDDA, VDDB, VDDC SCOPE VDD VDDA, VDDB, VDDC Qx Qx GND GND 1.65V¬±5 -1.25V¬±5 3.3V Output Load AC Test Circuit 3.3V/2.5V Output Load AC Test Circuit VDD V DDO nPCLK Qx V Cross Points PP 2 V CMR PCLK V DDO Qy GND Differential Input Level QX0:QXx 2 tsk(o) Output Skew VDDx 2 QBx, QCx VDDx 2 QX0:QXx tsk(b) QAx tsk(ω) Where X = Bank A, B or C Bank Skew ©2015 Integrated Device Technology, Inc. Multiple Frequency Skew 7 Revision C, September 20, 2016 87946I-01 Datasheet Parameter Measurement Information, continued nPCLK Part 1 V PCLK DDO Qx 2 Part 2 QAx, QBx, QCx V DDO Qy 2 tsk(pp) VDDx 2 t PD Part-to-Part Skew Propagation Delay 80% QAx, QBx, QCx 80% t PW t QAx, QBx, QCx 20% 20% tR tF odc = PERIOD t PW x 100% t PERIOD Output Rise/Fall Time ©2015 Integrated Device Technology, Inc. Output Duty Cycle/Pulse Width/Period 8 Revision C, September 20, 2016 87946I-01 Datasheet Application Information Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVCMOS Outputs All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVCMOS output can be left floating. There should be no trace attached. Wiring the Differential Input to Accept Single Ended Levels Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input PCLK V_REF C1 0.1u nPCLK R2 1K Figure 1. Single-Ended Signal Driving Differential Input ©2015 Integrated Device Technology, Inc. 9 Revision C, September 20, 2016 87946I-01 Datasheet LVPECL Clock Input Interface The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. The differential signal must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the PCLK/nPCLK input driven by the most common driver types. 3.3V 3.3V 3.3V 3.3V R1 50Ω 3.3V Zo = 50Ω R2 50Ω Zo = 50Ω PCLK PCLK R1 100Ω Zo = 50Ω Zo = 50Ω nPCLK LVPECL Input CML nPCLK LVPECL Input CML Built-In Pullup Figure 2B. PCLK/nPCLK Input Driven by a Built-In Pullup CML Driver Figure 2A. PCLK/nPCLK Input Driven by a CML Driver 3.3V 3.3V 3.3V R3 125Ω R4 125Ω Zo = 50Ω PCLK Zo = 50Ω nPCLK LVPECL Input LVPECL R2 84Ω R1 84Ω Figure 2C. PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver Figure 2D. PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple 2.5V 3.3V 2.5V R3 120 R4 120 Zo = 60Ω PCLK Zo = 60Ω nPCLK SSTL R1 120 R2 120 LVPECL Input Figure 2E. PCLK/nPCLK Input Driven by an SSTL Driver ©2015 Integrated Device Technology, Inc. Figure 2F. PCLK/nPCLK Input Driven by a 3.3V LVDS Driver 10 Revision C, September 20, 2016 87946I-01 Datasheet Reliability Information Table 6. JA vs. Air Flow Table for a 32 Lead LQFP JA vs. Air Flow Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for 87946I-01 is: 1204 ©2015 Integrated Device Technology, Inc. 11 Revision C, September 20, 2016 87946I-01 Datasheet Package Outline and Package Dimension Package Outline - Y Suffix for 32 Lead LQFP Table 7. Package Dimensions for 32 Lead LQFP JEDEC Variation: BBC - HD All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 1.60 A1 0.05 0.10 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 D&E 9.00 Basic D1 & E1 7.00 Basic D2 & E2 5.60 Ref. e 0.80 Basic L 0.45 0.60 0.75  0° 7° ccc 0.10 Reference Document: JEDEC Publication 95, MS-026 ©2015 Integrated Device Technology, Inc. 12 Revision C, September 20, 2016 87946I-01 Datasheet Ordering Information Table 8. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 87946AYI-01LF ICS7946AI01L “Lead-Free” 32 Lead LQFP Tray -40C to 85C 87946AYI-01LFT ICS7946AI01L “Lead-Free” 32 Lead LQFP Tape & Reel -40C to 85C ©2015 Integrated Device Technology, Inc. 13 Revision C, September 20, 2016 87946I-01 Datasheet Revision History Sheet Rev Table Page T5A & T5B 1 5 6 9 Features section added Additive Phase Jitter and Lead-Free bullets AC Characteristics Tables - added Additive Phase Jitter row. Added Additive Phase Jitter section. Application Section - added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free Part/Order Number and Note. Updated format throughout the datasheet. T8 13 Ordering Information Table - added lead-free marking. Updated header/footer of datasheet. 11/10/09 T8 13 Ordering Information - removed leaded devices. Updated data sheet format. 7/21/15 T8 13 Ordering Information - Deleted LF note below table. Product Discontinuation Notice - Last time buy expires May 6, 2017. PDN CQ-16-01 Updated header and footer. 6/28/16 Corrected datasheet title. Corrected General Description, first sentence from Clock Generator to Fanout Buffer. 9/20/16 B 13 B B B 1 C Description of Change ©2015 Integrated Device Technology, Inc. Date 14 5/4/07 Revision C, September 20, 2016 87946I-01 Datasheet Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. 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