89HPES12N3A
Data Sheet
12-lane 3-Port
PCI Express® Switch
®
Device Overview
Flexible Architecture with Numerous Configuration Options
– Automatic per port link width negotiation to x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
◆
Legacy Support
– PCI compatible INTx emulation
– Bus locking
◆
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates twelve 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
◆
Reliability, Availability, and Serviceability (RAS) Features
– Supports ECRC and Advanced Error Reporting
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC and
server motherboards
◆
The 89HPES12N3A is a member of the IDT PRECISE™ family of
PCI Express® switching solutions. The PES12N3A is a 12-lane, 3-port
peripheral chip that performs PCI Express packet switching with a
feature set optimized for high performance applications such as servers,
storage, and communications/networking. It provides connectivity and
switching functions between a PCI Express upstream port and two
downstream ports and supports switching between downstream ports.
Features
◆
High Performance PCI Express Switch
– Twelve 2.5Gbps PCI Express lanes
– Three switch ports
– Upstream port configurable up to x4
– Downstream ports configurable up to x4
– Low-latency cut-through switch architecture
– Support for Max Payload Sizes up to 2048 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
Block Diagram
3-Port Switch Core
Frame Buffer
Scheduler
Scheduler
Transaction Layer
Transaction Layer
Transaction Layer
Data Link Layer
Data Link Layer
Data Link Layer
Multiplexer/Demultiplexer
Phy
Logical
Layer
Port
Arbitration
Route Table
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
SerDes SerDes SerDes SerDes
Multiplexer/Demultiplexer
Phy
Logical
Layer
Multiplexer/Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
SerDes SerDes SerDes
SerDes
SerDes SerDes SerDes SerDes
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
12 PCI Express Lanes
One x4 Upstream Port and Two x4 Downstream Ports
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 31
April 9, 2010
DSC 6922
IDT 89HPES12N3A Data Sheet
Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Supports PCI Power Management Interface specification
(PCI-PM 1.1)
• Supports device power management states: D0, D3hot and
D3cold
– Unused SerDes are disabled
◆
Testability and Debug Features
– Ability to read and write any internal register via the SMBus
◆
Eight General Purpose Input/Output Pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
◆
Packaged in 19x19mm 324-ball BGA with 1mm ball spacing
◆
Product Description
Utilizing standard PCI Express interconnect, the PES12N3A
provides the most efficient I/O connectivity solution for applications
requiring high throughput, low latency, and simple board layout with a
minimum number of board layers. It provides connectivity for up to 3
ports across 12 integrated serial lanes. Each lane provides 2.5 Gbps of
bandwidth in both directions and is fully compliant with PCI Express
Base specification revision 1.1.
SMBus Interface
The PES12N3A contains two SMBus interfaces. The slave interface
provides full access to the configuration registers in the PES12N3A,
allowing every configuration register in the device to be read or written
by an external agent. The master interface allows the default configuration register values of the PES12N3A to be overridden following a reset
with values programmed in an external serial EEPROM. The master
interface is also used by an external Hot-Plug I/O expander.
Bit
Slave
SMBus
Address
Master
SMBus
Address
4
0
MSMBADDR[4]
5
SSMBADDR[5]
1
6
1
0
7
1
1
Table 1 Master and Slave SMBus Address Assignment
As shown in Figure 2, the master and slave SMBuses may be used
in a unified or split configuration. In the unified configuration, shown in
Figure 2(a), the master and slave SMBuses are tied together and the
PES12N3A acts both as a SMBus master as well as a SMBus slave on
this bus. This requires that the SMBus master or processor that has
access to PES12N3A registers supports SMBus arbitration. In some
systems, this SMBus master interface may be implemented using
general purpose I/O pins on a processor or micro controller, and may
not support SMBus arbitration. To support these systems, the
PES12N3A may be configured to operate in a split configuration as
shown in Figure 2(b).
In the split configuration, the master and slave SMBuses operate as
two independent buses and thus multi-master arbitration is never
required. The PES12N3A supports reading and writing of the serial
EEPROM on the master SMBus via the slave SMBus, allowing in
system programming of the serial EEPROM.
Six pins make up each of the two SMBus interfaces. These pins
consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus
address pins. In the slave interface, these address pins allow the
SMBus address to which the device responds to be configured. In the
master interface, these address pins allow the SMBus address of the
serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up on negation of PERSTN by
sampling the corresponding address pins. When the pins are sampled,
the resulting address is assigned as shown in Table 1.
Bit
Slave
SMBus
Address
Master
SMBus
Address
1
SSMBADDR[1]
MSMBADDR[1]
2
SSMBADDR[2]
MSMBADDR[2]
3
SSMBADDR[3]
MSMBADDR[3]
Table 1 Master and Slave SMBus Address Assignment
2 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
PES12N3A
Processor
SMBus
Master
Serial
EEPROM
...
Other
SMBus
Devices
PES12N3A
SSMBCLK
SSMBDAT
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
MSMBCLK
MSMBDAT
Processor
SMBus
Master
...
Other
SMBus
Devices
Serial
EEPROM
(b) Split Configuration and Management Buses
(a) Unified Configuration and Management Bus
Figure 2 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES12N3A supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES12N3A
utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES12N3A generates an SMBus transaction to the I/O expander with the new
value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin
(alternate function of GPIO) of the PES12N3A. In response to an I/O expander interrupt, the PES12N3A generates an SMBus transaction to read the
state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES12N3A provides eight General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO
pin may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
The PES12N3A is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 1.1. The PES12N3A can operate either as a store and forward or cutthrough switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with
sophisticated resource management to enable efficient switching and I/O connectivity for servers, storage, and embedded applications.
Processor
North
Bridge
PES12N3A
PCI Express
Slots
PES12N3A
I/O
Dual
GbE
I/O
Dual
GbE
Memory
Memory
Memory
Memory
PES12N3A
I/O
SATA
I/O
SATA
Figure 3 I/O Expansion Application
3 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Pin Description
The following tables list the functions of the pins provided on the PES12N3A. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Note: In the PES12N3A, the two downstream ports are labeled port 2 and port 4.
Signal
Type
Name/Description
PE0RP[3:0]
PE0RN[3:0]
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0.
PE0TP[3:0]
PE0TN[3:0]
O
PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for port 0.
PE2RP[3:0]
PE2RN[3:0]
I
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PE2TP[3:0]
PE2TN[3:0]
O
PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for port 2.
PE4RP[3:0]
PE4RN[3:0]
I
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pairs for port 4.
PE4TP[3:0]
PE4TN[3:0]
O
PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pairs for port 4.
PEREFCLKP[2:1]
PEREFCLKN[2:1]
I
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal.
REFCLKM
I
PCI Express Reference Clock Mode Select. This signal selects the frequency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 2 PCI Express Interface Pins
Signal
Type
Name/Description
MSMBADDR[4:1]
I
Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
MSMBCLK
I/O
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus. It is active and generating the clock only
when the EEPROM or I/O Expanders are being accessed.
MSMBDAT
I/O
Master SMBus Data. This bidirectional signal is used for data on the master SMBus.
SSMBADDR[5,3:1]
I
SSMBCLK
I/O
Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the slave SMBus.
SSMBDAT
I/O
Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
Slave SMBus Address. These pins determine the SMBus address to
which the slave SMBus interface responds.
Table 3 SMBus Interface Pins
4 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Signal
Type
Name/Description
GPIO[0]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2
GPIO[1]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P4RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 4
GPIO[2]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN0
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 0 input
GPIO[3]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[4]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN2
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 2 input
GPIO[5]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[6]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[7]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: GPEN
Alternate function pin type: Output
Alternate function: General Purpose Event (GPE) output
Table 4 General Purpose I/O Pins
Signal
Type
Name/Description
CCLKDS
I
Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a common clock is being used between the downstream device
and the downstream port.
CCLKUS
I
Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a common clock is being used between the upstream device and
the upstream port.
MSMBSMODE
I
Master SMBus Slow Mode. The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 KHz. This value
may not be overridden.
Table 5 System Pins (Part 1 of 2)
5 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Signal
Type
Name/Description
PERSTN
I
Fundamental Reset. Assertion of this signal resets all logic inside the
PES12N3A and initiates a PCI Express fundamental reset.
RSTHALT
I
Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, the PES12N3A executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is
cleared in the SWCTL register by an SMBus master.
SWMODE[3:0]
I
Switch Mode. These configuration pins determine the PES12N3A switch
operating mode. These pins should be static and not change after the
negation of PERSTN.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0xF Reserved
Table 5 System Pins (Part 2 of 2)
Signal
Type
Name/Description
JTAG_TCK
I
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG_TDI
I
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG_TDO
O
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS
I
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N
I
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 6 Test Pins
Signal
Type
Name/Description
VDDCORE
I
Core VDD. Power supply for core logic.
VDDIO
I
I/O VDD. LVTTL I/O buffer power supply.
VDDPE
I
PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
Table 7 Power and Ground Pins
6 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Signal
Type
Name/Description
VDDAPE
I
PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
VTTPE
I
PCI Express Termination Power.
VSS
I
Ground.
Table 7 Power and Ground Pins
7 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Pin Characteristics
Note: Some input pads of the PES12N3A do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate
levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
Function
PCI Express Interface
SMBus
Type
Buffer
I/O
Type
PE0RN[3:0]
I
CML
Serial link
PE0RP[3:0]
I
PE0TN[3:0]
O
PE0TP[3:0]
O
PE2RN[3:0]
I
PE2RP[3:0]
I
PE2TN[3:0]
O
PE2TP[3:0]
O
PE4RN[3:0]
I
PE4RP[3:0]
I
PE4TN[3:0]
O
PE4TP[3:0]
O
PEREFCLKN[2:1]
I
PEREFCLKP[2:1]
I
LVPECL/
CML
Diff. Clock
Input
REFCLKM
I
LVTTL
Input
pull-down
MSMBADDR[4:1]
I
LVTTL
Input
pull-up
Pin Name
2
Internal
Resistor1
Notes
Refer to Table 9
MSMBCLK
I/O
STI
pull-up on board
MSMBDAT
I/O
STI
pull-up on board
I
Input
SSMBCLK
I/O
STI
pull-up on board
SSMBDAT
I/O
STI
pull-up on board
General Purpose I/O
GPIO[7:0]
I/O
LVTTL
High Drive
pull-up
System Pins
CCLKDS
I
LVTTL
Input
pull-up
CCLKUS
I
pull-up
MSMBSMODE
I
pull-down
PERSTN
I
RSTHALT
I
pull-down
SWMODE[3:0]
I
pull-down
SSMBADDR[5,3:1]
pull-up
Table 8 Pin Characteristics (Part 1 of 2)
8 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Type
Buffer
I/O
Type
Internal
Resistor1
JTAG_TCK
I
LVTTL
STI
pull-up
JTAG_TDI
I
STI
pull-up
JTAG_TDO
O
JTAG_TMS
I
STI
pull-up
JTAG_TRST_N
I
STI
pull-up
Function
JTAG
Pin Name
Notes
External pull-down
Table 8 Pin Characteristics (Part 2 of 2)
1.
Internal resistor values under typical operating conditions are 54K Ω for pull-up and 251K Ω for pull-down.
2. Schmitt Trigger Input (STI).
9 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Logic Diagram — PES12N3A
PE0TP[0]
PE0TN[0]
PE0RP[1]
PE0RN[1]
PE0TP[1]
PE0TN[1]
...
PE0RP[0]
PE0RN[0]
PE0RP[3]
PE0RN[3]
PE0TP[3]
PE0TN[3]
PE2RP[0]
PE2RN[0]
PE2TP[0]
PE2TN[0]
PE2RP[1]
PE2RN[1]
PE2TP[1]
PE2TN[1]
...
PCI Express
Switch
SerDes Input
Port 2
2
...
PCI Express
Switch
SerDes Input
Port 0
2
PEREFCLKP
PEREFCLKN
REFCLKM
...
Reference
Clocks
PE2RP[3]
PE2RN[3]
PES12N3A
PE4TP[0]
PE4TN[0]
PE4TP[1]
PE4TN[1]
PE4RP[1]
PE4RN[1]
...
...
PE4RP[3]
PE4RN[3]
Master
SMBus Interface
Slave
SMBus Interface
System
Functions
MSMBADDR[4:1]
MSMBCLK
MSMBDAT
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
MSMBSMODE
CCLKDS
CCLKUS
RSTHALT
PERSTN
SWMODE[3:0]
PCI Express
Switch
SerDes Output
Port 2
PE2TP[3]
PE2TN[3]
PE4RP[0]
PE4RN[0]
PCI Express
Switch
SerDes Input
Port 4
PCI Express
Switch
SerDes Output
Port 0
PCI Express
Switch
SerDes Output
Port 4
PE4TP[3]
PE4TN[3]
4
8
GPIO[7:0]
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
4
VDDCORE
VDDIO
VDDPE
VDDAPE
VSS
4
General Purpose
I/O
JTAG
Power/Ground
VTTPE
Figure 4 PES12N3A Logic Diagram
10 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14.
Parameter
Description
Min
RefclkFREQ
Input reference clock frequency range
100
RefclkDC2
Duty cycle of input clock
40
TR, TF
Rise/Fall time of input clocks
VSW
Differential input voltage swing4
Tjitter
Input clock jitter (cycle-to-cycle)
RT
Termination Resistor
Typical
50
0.6
Max
Unit
1251
MHz
60
%
0.2*RCUI
RCUI3
1.6
V
125
ps
110
Ohms
Table 9 Input Clock Requirements
1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM.
2. ClkIn must be AC coupled. Use 0.01 — 0.1 µF ceramic capacitors.
3.
RCUI (Reference Clock Unit Interval) refers to the reference clock period.
4. AC coupling required.
AC Timing Characteristics
Parameter
Description
Min1
Typical1
Max1
Units
399.88
400
400.12
ps
0.7
.9
PCIe Transmit
UI
Unit Interval
TTX-EYE
Minimum Tx Eye Width
TTX-EYE-MEDIAN-toMAX-JITTER
Maximum time between the jitter median and maximum
deviation from the median
TTX-RISE, TTX-FALL
D+ / D- Tx output rise/fall time
50
TTX- IDLE-MIN
Minimum time in idle
50
TTX-IDLE-SET-TO-
Maximum time to transition to a valid Idle after sending
an Idle ordered set
20
UI
IDLE
TTX-IDLE-TO-DIFF-
Maximum time to transition from valid idle to diff data
20
UI
500
1300
ps
400
400.12
ps
UI
0.15
90
UI
ps
UI
DATA
TTX-SKEW
Transmitter data skew between any 2 lanes
PCIe Receive
UI
Unit Interval
399.88
TRX-EYE (with jitter)
Minimum Receiver Eye Width (jitter tolerance)
0.4
UI
Table 10 PCIe AC Timing Characteristics (Part 1 of 2)
11 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Max1
Units
Max time between jitter median & max deviation
0.3
UI
Unexpected Idle Enter Detect Threshold Integration Time
10
ms
Lane to lane input skew
20
ns
Parameter
Min1
Description
TRX-EYE-MEDIUM TO
Typical1
MAX JITTER
TRX-IDLE-DET-DIFFENTER TIME
TRX-SKEW
Table 10 PCIe AC Timing Characteristics (Part 2 of 2)
1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1
Signal
Symbol
Reference
Min Max Unit
Edge
Timing
Diagram
Reference
GPIO
GPIO[7:0]1
Tpw_13b2
None
50
—
ns
Table 11 GPIO AC Timing Characteristics
1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if
they are asynchronous.
2. The values for this symbol were determined by calculation, not by testing.
GPIO (synchronous output)
Tpw_13b
GPIO (asynchronous input)
12 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Signal
Symbol
Reference
Edge
Min
Max
Unit
Timing
Diagram
Reference
Tper_16a
none
50.0
—
ns
See Figure 5.
10.0
25.0
ns
2.4
—
ns
1.0
—
ns
—
20
ns
—
20
ns
25.0
—
ns
JTAG
JTAG_TCK
Thigh_16a,
Tlow_16a
JTAG_TMS1,
JTAG_TDI
Tsu_16b
JTAG_TCK rising
Thld_16b
JTAG_TDO
Tdo_16c
Tdz_16c
JTAG_TRST_N
JTAG_TCK falling
2
Tpw_16d2
none
Table 12 JTAG AC Timing Characteristics
1. The
JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
2. The values for this symbol were determined by calculation, not by testing.
Tlow_16a
Tper_16a
Thigh_16a
JTAG_TCK
Thld_16b
Tsu_16b
JTAG_TDI
Thld_16b
Tsu_16b
JTAG_TMS
Tdo_16c
Tdz_16c
JTAG_TDO
Tpw_16d
JTAG_TRST_N
Figure 5 JTAG AC Timing Waveform
13 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Recommended Operating Supply Voltages
Symbol
Parameter
Minimum
Typical
Maximum
Unit
VDDCORE
Internal logic supply
0.9
1.0
1.1
V
VDDI/O
I/O supply except for SerDes LVPECL/CML
3.0
3.3
3.6
V
VDDPE
PCI Express Digital Power
0.9
1.0
1.1
V
VDDAPE
PCI Express Analog Power
0.9
1.0
1.1
V
VTTPE
PCI Express Serial Data Transmit
Termination Voltage
1.425
1.5
1.575
V
VSS
Common ground
0
0
0
V
Table 13 PES12N3A Operating Voltages
Power-Up Sequence
This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the
PES12N3A, the power-up sequence must be as follows:
1. VDDI/O — 3.3V
2. VDDCore, VDDPE, VDDAPE — 1.0V
3. VTTPE — 1.5V
When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues
are avoided. There are no maximum time limitations in ramping to valid power levels. The power-down sequence must be in the reverse order of the
power-up sequence.
Recommended Operating Temperature
Grade
Temperature
Commercial
0°C to +70°C Ambient
Industrial
-40°C to +85°C Ambient
Table 14 PES12N3A Operating Temperatures
Power Consumption
Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13
(and also listed below).
Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in
Table 13 (and also listed below).
14 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Core Supply
PCIe Digital
Supply
PCIe Analog
Supply
PCIe Termination Supply
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
1.5V
Max
1.575V
Typ
3.3V
Max
3.6V
Typ
Power
Max
Power
mA
723
928
578
693
223
251
291
345
1
1
1.96W
2.6W
Watts
0.72
1.02
0.58
0.76
0.22
0.28
0.44
0.54
0.004
0.004
mA
618
746
398
458
207
223
142
160
1
1
1.44W
1.8W
Watts
0.62
0.82
0.4
0.5
0.21
0.25
0.21
0.25
0.003
0.003
Number of active
Lanes per Port
4/4/4
4/1/1
I/O Supply
Total
Table 15 PES12N3A Power Consumption
Thermal Considerations
This section describes thermal considerations for the PES12N3A (19mm2 BCG324 package). The data in Table 16 below contains information that
is relevant to the thermal performance of the PES12N3A switch.
Symbol
Parameter
Value
Units
Conditions
TJ(max)
Junction Temperature
125
oC
Maximum
70
oC
Maximum for commercial-rated products
21.8
oC/W
Zero air flow
15.1
oC/W
1 m/S air flow
13.9
oC/W
2 m/S air flow
TA(max)
θJA(effective)
Ambient Temperature
Effective Thermal Resistance, Junction-to-Ambient
θJB
Thermal Resistance, Junction-to-Board
11.4
oC/W
θJC
Thermal Resistance, Junction-to-Case
5.1
oC/W
P
Power Dissipation of the Device
2.6
Watts
Maximum
Table 16 Thermal Specifications for PES12N3A, 19x19 mm BCG324 Package
Note: The parameter θJA(eff) is not the absolute thermal resistance for the package as defined by JEDEC (JESD-51). Because resistance
can vary with the number of board layers, size of the board, and airflow, θJA(eff) is the effective thermal resistance. The values for effective
θJA given above are based on a 10-layer, standard height, full length (4.3”x12.2”) PCIe add-in card.
Heat Sink
Table 17 lists heat sink requirements for the PES12N3A under three common usage scenarios. As shown in this table, a heat sink is not required
in most cases.
Air Flow
Board Size
Board Layers
Heat Sink Requirement
Zero
4.3”x12.2” (standard height, full length form factor) or larger
4 or more
No heat sink required
Zero
Any
6 or more
No heat sink required
1 m/S or more
Any
Any
No heat sink required
Table 17 Heat Sink Requirements Based on Air Flow and Board Characteristics
15 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Thermal Usage Examples
The junction-to-ambient thermal resistance is a measure of a device’s ability to dissipate heat from the die to its surroundings in the absence of a
heat sink. The general formula to determine θJA is:
θJA = (TJ - TA)/P
Thermal reliability of a device is generally assured when the actual value of TJ in the specific system environment being considered is less than the
maximum TJ specified for the device. Using an ambient temperature of 70oC and assuming a system with 1m/S airflow, the actual value of TJ is:
TJ(actual) = TA + P * θJA(eff) = 70oC + 2.6W * 9.9W/oC = 96oC
The actual TJ of 96oC is well below the maximum TJ of 125oC specified for the device (shown in Table 16). Therefore, no heat sink is needed in this
scenario. The formula is also useful from a system design perspective. It can be used to determine if a heat sink should be added to the device based
on some desired value of TJ. For example, if for reliability purposes the desired TJ is 100oC, then the maximum allowable TA is:
TA(allowed) = TJ(desired) - (P * θJA(effective))
TA(allowed) = 100oC - (2.6W * 9.9W/oC) = 100oC - 26oC = 74oC
An appropriate level of increased air flow and/or a heat sink can be added to achieve this lower ambient temperature Please contact
ssdhelp@idt.com for further assistance.
16 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 13.
Note: See Table 8, Pin Characteristics, for a complete I/O listing.
I/O Type
Parameter
Serial Link
PCIe Transmit
Min1
Description
Typ1
Max1
Unit
800
1200
mV
-3
-4
dB
3.7
V
VTX-DIFFp-p
Differential peak-to-peak output voltage
VTX-DE-RATIO
De-emphasized differential output voltage
VTX-DC-CM
DC Common mode voltage
VTX-CM-ACP
RMS AC peak common mode output voltage
20
mV
VTX-CM-DC-
Abs delta of DC common mode voltage
between L0 and idle
100
mV
25
mV
delta
Abs delta of DC common mode voltage
between D+ and D-
VTX-Idle-DiffP
Electrical idle diff peak output
20
mV
VTX-RCV-Detect
Voltage change during receiver detection
600
mV
RLTX-DIFF
Transmitter Differential Return loss
12
dB
RLTX-CM
Transmitter Common Mode Return loss
6
dB
ZTX-DEFF-DC
DC Differential TX impedance
80
100
120
Ω
ZOSE
Single ended TX Impedance
40
50
60
Ω
Transmitter Eye
Diagram
TX Eye Height (De-emphasized bits)
505
650
mV
Transmitter Eye
Diagram
TX Eye Height (Transition bits)
800
950
mV
VRX-DIFFp-p
Differential input voltage (peak-to-peak)
175
VRX-CM-AC
Receiver common-mode voltage for AC
coupling
RLRX-DIFF
Receiver Differential Return Loss
15
dB
RLRX-CM
Receiver Common Mode Return Loss
6
dB
ZRX-DIFF-DC
Differential input impedance (DC)
80
100
120
Ω
ZRX-COMM-DC
Single-ended input impedance
40
50
60
Ω
ZRX-COMM-HIGH-
200k
350k
Z-DC
Powered down input common mode
impedance (DC)
VRX-IDLE-DET-
Electrical idle detect threshold
65
Input Capacitance
1.5
active-idle-delta
VTX-CM-DC-line-
-0.1
1
Conditions
PCIe Receive
1200
mV
150
mV
Ω
175
mV
DIFFp-p
PCIe REFCLK
CIN
—
pF
Table 18 DC Electrical Characteristics (Part 1 of 2)
17 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
I/O Type
Min1
Typ1
Max1
Unit
Conditions
IOL
—
2.5
—
mA
VOL = 0.4v
IOH
—
-5.5
—
mA
VOH = 1.5V
IOL
—
12.0
—
mA
VOL = 0.4v
IOH
—
-20.0
—
mA
VOH = 1.5V
Parameter
Description
Other I/Os
LOW Drive
Output
High Drive
Output
Schmitt Trigger Input
(STI)
VIL
-0.3
—
0.8
V
—
VIH
2.0
—
VDDIO +
0.5
V
—
Input
VIL
-0.3
—
0.8
V
—
VIH
2.0
—
VDDIO +
0.5
V
—
Capacitance
CIN
—
—
8.5
pF
—
Leakage
Inputs
—
—
+ 10
μA
VDDI/O (max)
I/OLEAK W/O
Pull-ups/downs
—
—
+ 10
μA
VDDI/O (max)
I/OLEAK WITH
Pull-ups/downs
—
—
+ 80
μA
VDDI/O (max)
Table 18 DC Electrical Characteristics (Part 2 of 2)
1.
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a.
18 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Package Pinout — 324-BGA Signal Pinout for PES12N3A
The following table lists the pin numbers and signal names for the PES12N3A device.
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
A1
VSS
E10
VDDPE
K1
VDDCORE
P10
VDDIO
A2
VSS
E11
VSS
K2
VSS
P11
VDDIO
A3
PE0RP03
E12
VDDPE
K3
VTTPE
P12
VDDIO
A4
VDDCORE
E13
VSS
K4
VDDCORE
P13
VDDIO
A5
PE0TN03
E14
VDDCORE
K5
VDDPE
P14
VDDIO
A6
VDDCORE
E15
VDDAPE
K6
VSS
P15
VSS
A7
PE0TP02
E16
VSS
K7
VSS
P16
VTTPE
A8
VDDCORE
E17
PE4TP03
K8
VSS
P17
VSS
A9
PE0RN02
E18
PE4TN03
K9
VSS
P18
VDDCORE
A10
VDDCORE
F1
VDDCORE
K10
VSS
R1
PE2TN03
A11
PE0RP01
F2
VSS
K11
VSS
R2
PE2TP03
A12
VDDCORE
F3
VDDCORE
K12
VSS
R3
VSS
A13
PE0TP01
F4
VDDAPE
K13
VSS
R4
VDDIO
A14
VDDCORE
F5
VSS
K14
VSS
R5
VSS
A15
VDDCORE
F6
VDDCORE
K15
VDDPE
R6
VDDCORE
A16
PE0TN00
F7
VSS
K16
VTTPE
R7
MSMBDAT
A17
VSS
F8
VDDCORE
K17
VSS
R8
SSMBADDR_5
A18
VSS
F9
VSS
K18
VDDCORE
R9
NC
B1
VDDCORE
F10
VDDCORE
L1
PE2RN02
R10
SWMODE_2
B2
VDDCORE
F11
VSS
L2
PE2RP02
R11
RSTHALT
B3
PE0RN03
F12
VSS
L3
VSS
R12
GPIO_04
B4
VSS
F13
VDDPE
L4
VDDPE
R13
VDDCORE
B5
PE0TP03
F14
VSS
L5
VSS
R14
VSS
B6
VSS
F15
VDDIO
L6
VDDCORE
R15
VDDIO
B7
PE0TN02
F16
VSS
L7
VDDCORE
R16
VSS
B8
VSS
F17
VSS
L8
VDDCORE
R17
PE4TP00
B9
PE0RP02
F18
VDDCORE
L9
VDDCORE
R18
PE4TN00
B10
VSS
G1
PE2TP01
L10
VDDCORE
T1
VDDCORE
B11
PE0RN01
G2
PE2TN01
L11
VDDCORE
T2
VSS
B12
VSS
G3
VSS
L12
VDDCORE
T3
VSS
B13
PE0TN01
G4
VDDPE
L13
VDDCORE
T4
JTAG_TCK
B14
VSS
G5
VDDAPE
L14
VSS
T5
JTAG_TDO
B15
VSS
G6
VSS
L15
VDDPE
T6
MSMBADDR_1
B16
PE0TP00
G7
VSS
L16
VSS
T7
MSMBCLK
Alt
1
Table 19 PES12N3A 324-pin Signal Pin-Out (Part 1 of 3)
19 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
B17
VDDCORE
G8
VDDIO
L17
PE4RP01
T8
SSMBADDR_2
B18
VDDCORE
G9
VSS
L18
PE4RN01
T9
CCLKDS
C1
PE2RP00
G10
VDDIO
M1
VDDCORE
T10
SWMODE_1
C2
PE2RN00
G11
VSS
M2
VSS
T11
PERSTN
C3
VSS
G12
VDDCORE
M3
VSS
T12
GPIO_03
C4
VDDCORE
G13
VSS
M4
VDDAPE
T13
GPIO_07
C5
VSS
G14
VDDAPE
M5
VSS
T14
VSS
C6
VTTPE
G15
VDDPE
M6
VDDCORE
T15
REFCLKM
C7
VSS
G16
VSS
M7
VSS
T16
VSS
C8
VTTPE
G17
PE4TN02
M8
VSS
T17
VSS
C9
VSS
G18
PE4TP02
M9
VDDCORE
T18
VDDCORE
C10
VTTPE
H1
VDDCORE
M10
VDDCORE
U1
PE2RP03
C11
VSS
H2
VSS
M11
VSS
U2
PE2RN03
C12
VTTPE
H3
VTTPE
M12
VSS
U3
VSS
C13
VDDCORE
H4
VDDAPE
M13
VDDCORE
U4
JTAG_TDI
C14
PE0RP00
H5
VSS
M14
VSS
U5
JTAG_TMS
C15
PE0RN00
H6
VSS
M15
VDDAPE
U6
MSMBADDR_2
C16
VDDCORE
H7
VDDCORE
M16
VSS
U7
MSMBADDR_4
C17
PE4RN03
H8
VSS
M17
VSS
U8
SSMBADDR_3
C18
PE4RP03
H9
VDDCORE
M18
VDDCORE
U9
CCLKUS
D1
VDDCORE
H10
VDDCORE
N1
PE2TP02
U10
SWMODE_0
D2
VSS
H11
VSS
N2
PE2TN02
U11
NC
D3
VSS
H12
VDDCORE
N3
VTTPE
U12
GPIO_00
1
D4
VDDCORE
H13
VSS
N4
VDDAPE
U13
GPIO_02
1
D5
VSS
H14
VDDAPE
N5
VSS
U14
GPIO_06
D6
VDDAPE
H15
VDDPE
N6
VSS
U15
MSMBSMODE
D7
VSS
H16
VTTPE
N7
VSS
U16
VSS
D8
VDDAPE
H17
VSS
N8
VSS
U17
PE4RN00
D9
VSS
H18
VDDCORE
N9
VSS
U18
PE4RP00
D10
VDDAPE
J1
PE2RP01
N10
VSS
V1
VDDCORE
D11
VSS
J2
PE2RN01
N11
VSS
V2
VSS
D12
VDDAPE
J3
VSS
N12
VSS
V3
PEREFCLKP1
D13
VSS
J4
VDDPE
N13
VSS
V4
PEREFCLKN1
D14
VDDCORE
J5
VSS
N14
VSS
V5
JTAG_TRST_N
D15
VSS
J6
VDDCORE
N15
VDDAPE
V6
MSMBADDR_3
D16
VSS
J7
VSS
N16
VTTPE
V7
SSMBADDR_1
D17
VSS
J8
VSS
N17
PE4TN01
V8
SSMBCLK
1
Table 19 PES12N3A 324-pin Signal Pin-Out (Part 2 of 3)
20 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
D18
VDDCORE
J9
VDDCORE
N18
PE4TP01
V9
SSMBDAT
E1
PE2TN00
J10
VDDCORE
P1
VDDCORE
V10
NC
E2
PE2TP00
J11
VSS
P2
VSS
V11
SWMODE_3
E3
VDDCORE
J12
VSS
P3
VTTPE
V12
VDDIO
E4
VSS
J13
VDDCORE
P4
VSS
V13
GPIO_01
E5
VDDCORE
J14
VSS
P5
VDDIO
V14
GPIO_05
E6
VSS
J15
VDDCORE
P6
VDDIO
V15
PEREFCLKP2
E7
VSS
J16
VSS
P7
VDDIO
V16
PEREFCLKN2
E8
VDDPE
J17
PE4RP02
P8
VDDIO
V17
VSS
E9
VSS
J18
PE4RN02
P9
VDDIO
V18
VDDCORE
Alt
1
Table 19 PES12N3A 324-pin Signal Pin-Out (Part 3 of 3)
Alternate Signal Functions
Pin
GPIO
Alternate
U12
GPIO_00
P2RSTN
V13
GPIO_01
P4RSTN
U13
GPIO_02
IOEXPINTN0
R12
GPIO_04
IOEXPINTN2
T13
GPIO_07
GPEN
Table 20 PES12N3A Alternate Signal Functions
21 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Power Pins
VDDCore
VDDCore
VDDCore
VDDIO
VDDPE
VDDAPE
VTTPE
A4
F3
L8
F15
E8
D6
C6
A6
F6
L9
G8
E10
D8
C8
A8
F8
L10
G10
E12
D10
C10
A10
F10
L11
P5
F13
D12
C12
A12
F18
L12
P6
G4
E15
H3
A14
G12
L13
P7
G15
F4
H16
A15
H1
M1
P8
H15
G5
K3
B1
H7
M6
P9
J4
G14
K16
B2
H9
M9
P10
K5
H4
N3
B17
H10
M10
P11
K15
H14
N16
B18
H12
M13
P12
L4
M4
P3
C4
H18
M18
P13
L15
M15
P16
C13
J6
P1
P14
N4
C16
J9
P18
R4
N15
D1
J10
R6
R15
D4
J13
R13
V12
D14
J15
T1
D18
K1
T18
E3
K4
V1
E5
K18
V18
E14
L6
F1
L7
Table 21 PES12N3A Power Pins
22 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Ground Pins
Vss
Vss
Vss
Vss
Vss
A1
D15
G11
K10
N8
A2
D16
G13
K11
N9
A17
D17
G16
K12
N10
A18
E4
H2
K13
N11
B4
E6
H5
K14
N12
B6
E7
H6
K17
N13
B8
E9
H8
L3
N14
B10
E11
H11
L5
P2
B12
E13
H13
L14
P4
B14
E16
H17
L16
P15
B15
F2
J3
M2
P17
C3
F5
J5
M3
R3
C5
F7
J7
M5
R5
C7
F9
J8
M7
R14
C9
F11
J11
M8
R16
C11
F12
J12
M11
T2
D2
F14
J14
M12
T3
D3
F16
J16
M14
T14
D5
F17
K2
M16
T16
D7
G3
K6
M17
T17
D9
G6
K7
N5
U3
D11
G7
K8
N6
U16
D13
G9
K9
N7
V2
V17
Table 22 PES12N3A Ground Pins
23 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Signals Listed Alphabetically
Signal Name
I/O Type
Location
Signal Category
CCLKDS
I
T9
System
CCLKUS
I
U9
GPIO_00
I/O
U12
GPIO_01
I/O
V13
GPIO_02
I/O
U13
GPIO_03
I/O
T12
GPIO_04
I/O
R12
GPIO_05
I/O
V14
GPIO_06
I/O
U14
GPIO_07
I/O
T13
JTAG_TCK
I
T4
JTAG_TDI
I
U4
JTAG_TDO
O
T5
JTAG_TMS
I
U5
JTAG_TRST_N
I
V5
MSMBADDR_1
I
T6
MSMBADDR_2
I
U6
MSMBADDR_3
I
V6
MSMBADDR_4
I
U7
MSMBCLK
I/O
T7
MSMBDAT
I/O
R7
I
U15
System
NC
R9
PCI Express
NC
U11
NC
V10
MSMBSMODE
PE0RN00
I
C15
PE0RN01
I
B11
PE0RN02
I
A9
PE0RN03
I
B3
PE0RP00
I
C14
PE0RP01
I
A11
PE0RP02
I
B9
PE0RP03
I
A3
PE0TN00
O
A16
General Purpose Input/Output
JTAG
SMBus
Table 23 PES12N3A Alphabetical Signal List (Part 1 of 3)
24 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Signal Name
I/O Type
Location
Signal Category
PE0TN01
O
B13
PCI Express (cont.)
PE0TN02
O
B7
PE0TN03
O
A5
PE0TP00
O
B16
PE0TP01
O
A13
PE0TP02
O
A7
PE0TP03
O
B5
PE2RN00
I
C2
PE2RN01
I
J2
PE2RN02
I
L1
PE2RN03
I
U2
PE2RP00
I
C1
PE2RP01
I
J1
PE2RP02
I
L2
PE2RP03
I
U1
PE2TN00
O
E1
PE2TN01
O
G2
PE2TN02
O
N2
PE2TN03
O
R1
PE2TP00
O
E2
PE2TP01
O
G1
PE2TP02
O
N1
PE2TP03
O
R2
PE4RN00
I
U17
PE4RN01
I
L18
PE4RN02
I
J18
PE4RN03
I
C17
PE4RP00
I
U18
PE4RP01
I
L17
PE4RP02
I
J17
PE4RP03
I
C18
PE4TN00
O
R18
PE4TN01
O
N17
PE4TN02
O
G17
PE4TN03
O
E18
PE4TP00
O
R17
Table 23 PES12N3A Alphabetical Signal List (Part 2 of 3)
25 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Signal Name
I/O Type
Location
Signal Category
PE4TP01
O
N18
PCI Express (cont.)
PE4TP02
O
G18
PE4TP03
O
E17
PEREFCLKN1
I
V4
PEREFCLKN2
I
V16
PEREFCLKP1
I
V3
PEREFCLKP2
I
V15
PERSTN
I
T11
System
REFCLKM
I
T15
PCI Express
RSTHALT
I
R11
System
SSMBADDR_1
I
V7
SMBus
SSMBADDR_2
I
T8
SSMBADDR_3
I
U8
SSMBADDR_5
I
R8
SSMBCLK
I/O
V8
SSMBDAT
I/O
V9
SWMODE_0
I
U10
SWMODE_1
I
T10
SWMODE_2
I
R10
SWMODE_3
I
V11
SMBus
System
VDDCORE,
VDDAPE, VDDIO,
VDDPE, VTTPE
See Table 21 for a listing of power pins.
VSS
See Table 22 for a listing of ground pins.
Table 23 PES12N3A Alphabetical Signal List (Part 3 of 3)
26 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
PES12N3A Pinout — Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
VDDCore (Power)
VTTPE (Power)
VDDI/O (Power)
VDDPE (Power)
Vss (Ground)
Signals
No Connection
VDDAPE (Power)
27 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
PES12N3A Package Drawing — 324-Pin BC324/BCG324
28 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
PES12N3A Package Drawing — Page Two
29 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Revision History
February 8, 2007: Initial publication.
April 4, 2007: In Table 3, revised description for MSMBCLK signal.
May 30, 2007: Added ZG device revision to Ordering Information.
November 14, 2007: Added new parameter, Termination Resistor, to Table 9, Input Clock Requirements.
March 27, 2008: In Table 16, Thermal Specifications, added θJB and θJC parameters and revised the values for θJA.
August 7, 2008: Added revision 1ZC to Ordering Information page.
February 19, 2009: Added industrial temperature to Table 14 and to Order page.
April 9, 2010: Revised package drawing on pages 28 and 29.
30 of 31
April 9, 2010
IDT 89HPES12N3A Data Sheet
Ordering Information
NN
A
AAA
NNAN
AA
Product
Family
Operating
Voltage
Device
Family
Product
Detail
Device
Revision
AA
Legend
A = Alpha Character
N = Numeric Character
A
Package Temp Range
Blank
I
Commercial Temperature
(0°C to +70°C Ambient)
Industrial Temperature
(-40° C to +85° C Ambient)
BC
BC324 324-ball CABGA
BCG
BCG324 324-ball CABGA, Green
ZC
ZG
1ZC
ZC revision
ZG revision
1ZC revision
12N3A
12-lane, 3-port
PES
PCI Express Switch
H
1.0V +/- 0.1V Core Voltage
89
Serial Switching Product
Valid Combinations
89HPES12N3AZCBC
324-pin BC324 package, Commercial Temp.
89HPES12N3AZCBCI
324-pin BC324 package, Industrial Temp.
89HPES12N3AZGBC
324-pin BC324 package, Commercial Temp.
89HPES12N3AZGBCI
324-pin BC324 package, Industrial Temp.
89HPES12N3A1ZCBC
324-pin BC324 package, Commercial Temp.
89HPES12N3A1ZCBCI
324-pin BC324 package, Industrial Temp.
89HPES12N3AZCBCG
324-pin Green BC324 package, Commercial Temp. 89HPES12N3AZCBCGI
324-pin Green BC324 package, Industrial Temp.
89HPES12N3AZGBCG
324-pin Green BC324 package, Commercial Temp. 89HPES12N3AZGBCGI
324-pin Green BC324 package, Industrial Temp.
89HPES12N3A1ZCBCG
324-pin Green BC324 package, Commercial Temp. 89HPES12N3A1ZCBCGI 324-pin Green BC324 package, Industrial Temp.
®
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
31 of 31
for Tech Support:
email: ssdhelp@idt.com
phone: 408-284-8208
April 9, 2010
IMPORTANT NOTICE AND DISCLAIMER
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL
SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
(Rev.1.0 Mar 2020)
Corporate Headquarters
Contact Information
TOYOSU FORESIA, 3-2-24 Toyosu,
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com
For further information on a product, technology, the most
up-to-date version of a document, or your nearest sales
office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas
Electronics Corporation. All trademarks and registered
trademarks are the property of their respective owners.
© 2020 Renesas Electronics Corporation. All rights reserved.
工商网监
湘ICP备2023018690号
