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89HPES48H12ZABRI

89HPES48H12ZABRI

  • 厂商:

    RENESAS(瑞萨)

  • 封装:

    1156-BBGA,FCBGA

  • 描述:

    IC INTFACE SPECIALIZED 1156FCBGA

  • 数据手册
  • 价格&库存
89HPES48H12ZABRI 数据手册
89HPES48H12 Data Sheet 48-Lane 12-Port PCI Express® System Interconnect Switch ® Device Overview ◆ The 89HPES48H12 is a member of the IDT PRECISE™ family of PCI Express® switching solutions. The PES48H12 is a 48-lane, 12-port system interconnect switch optimized for PCI Express packet switching in high-performance applications, supporting multiple simultaneous peer-to-peer traffic flows. Target applications include servers, storage, communications, and embedded systems. Features ◆ High Performance PCI Express Switch – Twelve maximum switch ports • Six main ports each of which consists of 8 SerDes • Each x8 main port can further bifurcate to 2 x4-ports – Forty-eight 2.5 Gbps embedded SerDes • Supports pre-emphasis and receive equalization on per-port basis – Delivers 192 Gbps (24 GBps) of aggregate switching capacity – Low-latency cut-through switch architecture – Support for Max Payload Size up to 2048 bytes – Supports two virtual channels and eight traffic classes – PCI Express Base Specification Revision 1.1 compliant ◆ ◆ Flexible Architecture with Numerous Configuration Options – Port arbitration schemes utilizing round robin algorithms – Virtual channels arbitration based on priority – Automatic per port link width negotiation to x8, x4, x2 or x1 – Supports automatic lane reversal on all ports – Supports automatic polarity inversion on all lanes – Supports locked transactions, allowing use with legacy software – Ability to load device configuration from serial EEPROM – Ability to control device via SMBus Highly Integrated Solution – Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates forty-eight 2.5 Gbps embedded full duplex SerDes, 8B/10B encoder/decoder (no separate transceivers needed) Reliability, Availability, and Serviceability (RAS) Features – Redundant upstream port failover capability – Supports optional PCI Express end-to-end CRC checking – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) Block Diagram x8/x4/x2/x1 x8/x4/x2/x1 x8/x4/x2/x1 SerDes SerDes SerDes DL/Transaction Layer DL/Transaction Layer DL/Transaction Layer Port Arbitration Route Table 12-Port Switch Core Scheduler Frame Buffer DL/Transaction Layer DL/Transaction Layer DL/Transaction Layer SerDes SerDes SerDes x8/x4/x2/x1 x8/x4/x2/x1 x8/x4/x2/x1 48 PCI Express Lanes Up to 6 x8 ports or 12 x4 Ports Figure 1 Internal Block Diagram IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 48 © 2008 Integrated Device Technology, Inc. October 7, 2008 DSC 6925 IDT 89HPES48H12 Data Sheet – Supports optional PCI Express Advanced Error Reporting – Supports PCI Express Hot-Plug • Compatible with Hot-Plug I/O expanders used on PC motherboards – Supports Hot-Swap ◆ Power Management – Supports PCI Power Management Interface specification, Revision 1.1 (PCI-PM) • Supports powerdown modes at the link level (L0, L0s, L1, L2/L3 Ready and L3) and at the device level (D0, D3hot) – Unused SerDes disabled ◆ Testability and Debug Features – Built in SerDes Pseudo-Random Bit Stream (PRBS) generator – Ability to read and write any internal register via the SMBus – Ability to bypass link training and force any link into any mode – Provides statistics and performance counters ◆ Thirty-two General Purpose Input/Output pins – Each pin may be individually configured as an input or output – Each pin may be individually configured as an interrupt input – Some pins have selectable alternate functions ◆ Packaged in a 35mm x 35mm 1156-ball Flip Chip BGA with 1mm ball spacing Product Description The PES48H12 is based on a flexible and efficient layered architecture. The PCI Express layers consist of SerDes, Physical, Data Link and Transaction layers. The PES48H12 can operate either as a store and forward switch or a cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and two Virtual Channels (VCs) with sophisticated resource management to enable efficient switching and I/O connectivity. SMBus Interface The PES48H12 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES48H12, allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of the PES48H12 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in Table 1. Utilizing standard PCI Express interconnect, the PES48H12 provides the most efficient system interconnect switching solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It provides 192 Gbps of aggregated, full-duplex switching capacity through 48 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification 1.1. Fully Bifurcated Non-bifurcated x8 x8 x8 3 2 1 0 x4 11 x8 10 4 5 6 7 8 9 x8 x8 2 x4 1 x4 0 11 x4 4 10 x4 5 9 x4 x4 3 x4 x4 6 x4 7 x4 8 x4 Figure 2 Port Configuration Examples Note: The configurations in the above diagram show the maximum port widths. The PES48H12 can negotiate to narrower port widths — x4, x2, or x1. 2 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Bit Slave SMBus Address Master SMBus Address 1 SSMBADDR[1] MSMBADDR[1] 2 SSMBADDR[2] MSMBADDR[2] 3 SSMBADDR[3] MSMBADDR[3] 4 0 MSMBADDR[4] 5 SSMBADDR[5] 1 6 1 0 7 1 1 Table 1 Master and Slave SMBus Address Assignment As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 3(a), the master and slave SMBuses are tied together and the PES48H12 acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has access to PES48H12 registers supports SMBus arbitration. In some systems, this SMBus master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support these systems, the PES48H12 may be configured to operate in a split configuration as shown in Figure 3(b). In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required. The PES48H12 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the serial EEPROM. PES48H12 Processor SMBus Master Serial EEPROM ... Other SMBus Devices PES48H12 SSMBCLK SSMBDAT SSMBCLK SSMBDAT MSMBCLK MSMBDAT MSMBCLK MSMBDAT Processor SMBus Master ... Other SMBus Devices Serial EEPROM (b) Split Configuration and Management Buses (a) Unified Configuration and Management Bus Figure 3 SMBus Interface Configuration Examples Hot-Plug Interface The PES48H12 supports PCI Express Hot-Plug on each downstream port (ports 1 through 11). To reduce the number of pins required on the device, the PES48H12 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES48H12 generates an SMBus transaction to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate function of GPIO) of the PES48H12. In response to an I/O expander interrupt, the PES48H12 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander. General Purpose Input/Output The PES48H12 provides 32 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose outputs, or alternate functions. Some GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM. 3 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Pin Description The following tables lists the functions of the pins provided on the PES48H12. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Differential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal ending in “N” is the negative portion of the differential pair. Signal Type Name/Description PE0RP[3:0] PE0RN[3:0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for port 0. Port 0 is the upstream port. PE0TP[3:0] PE0TN[3:0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for port 0. Port 0 is the upstream port. PE1RP[3:0] PE1RN[3:0] I PCI Express Port 1 Serial Data Receive. Differential PCI Express receive pairs for port 1. When port 0 is merged with port 1, these signals become port 0 receive pairs for lanes 4 through 7. PE1TP[3:0] PE1TN[3:0] O PCI Express Port 1 Serial Data Transmit. Differential PCI Express transmit pairs for port 1. When port 0 is merged with port 1, these signals become port 0 transmit pairs for lanes 4 through 7. PE2RP[3:0] PE2RN[3:0] I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for port 2. PE2TP[3:0] PE2TN[3:0] O PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for port 2. PE3RP[3:0] PE3RN[3:0] I PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pairs for port 3. When port 2 is merged with port 3, these signals become port 2 receive pairs for lanes 4 through 7. PE3TP[3:0] PE3TN[3:0] O PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit pairs for port 2. When port 2 is merged with port 3, these signals become port 2 transmit pairs for lanes 4 through 7. PE4RP[3:0] PE4RN[3:0] I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for port 4. PE4TP[3:0] PE4TN[3:0] O PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pairs for port 4. PE5RP[3:0] PE5RN[3:0] I PCI Express Port 5 Serial Data Receive. Differential PCI Express receive pairs for port 5. When port 4 is merged with port 5, these signals become port 4 receive pairs for lanes 4 through 7. PE5TP[3:0] PE5TN[3:0] O PCI Express Port 5 Serial Data Transmit. Differential PCI Express transmit pairs for port 5. When port 4 is merged with port 5, these signals become port 4 transmit pairs for lanes 4 through 7. PE6RP[3:0] PE6RN[3:0] I PCI Express Port 6 Serial Data Receive. Differential PCI Express receive pairs for port 6. PE6TP[3:0] PE6TN[3:0] O PCI Express Port 6 Serial Data Transmit. Differential PCI Express transmit pairs for port 6. PE7RP[3:0] PE7RN[3:0] I PCI Express Port 7 Serial Data Receive. Differential PCI Express receive pairs for port 7. When port 6 is merged with port 7, these signals become port 6 receive pairs for lanes 4 through 7. Table 2 PCI Express Interface Pins (Part 1 of 2) 4 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Signal Type Name/Description PE7TP[3:0] PE7TN[3:0] O PCI Express Port 7 Serial Data Transmit. Differential PCI Express transmit pairs for port 7. When port 6 is merged with port 7, these signals become port 6 transmit pairs for lanes 4 through 7. PE8RP[3:0] PE8RN[3:0] I PCI Express Port 8 Serial Data Receive. Differential PCI Express receive pairs for port 8. PE8TP[3:0] PE8TN[3:0] O PCI Express Port 8 Serial Data Transmit. Differential PCI Express transmit pairs for port 8. PE9RP[3:0] PE9RN[3:0] I PCI Express Port 9 Serial Data Receive. Differential PCI Express receive pairs for port 9. When port 8 is merged with port 9, these signals become port 8 receive pairs for lanes 4 through 7. PE9TP[3:0] PE9TN[3:0] O PCI Express Port 9 Serial Data Transmit. Differential PCI Express transmit pairs for port 9. When port 8 is merged with port 9, these signals become port 8 transmit pairs for lanes 4 through 7. PE10RP[3:0] PE10RN[3:0] I PCI Express Port 10 Serial Data Receive. Differential PCI Express receive pairs for port 10. PE10TP[3:0] PE10TN[3:0] O PCI Express Port 10 Serial Data Transmit. Differential PCI Express transmit pairs for port 10. PE11RP[3:0] PE11RN[3:0] I PCI Express Port 11 Serial Data Receive. Differential PCI Express receive pairs for port 11. When port 10 is merged with port 11, these signals become port 10 receive pairs for lanes 4 through 7. PE11TP[3:0] PE11TN[3:0] O PCI Express Port 11 Serial Data Transmit. Differential PCI Express transmit pairs for port 11. When port 10 is merged with port 11, these signals become port 10 transmit pairs for lanes 4 through 7. REFCLKM I PCI Express Reference Clock Mode Select. This signal selects the frequency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz REFCLKP[3:0] REFCLKN[3:0] I PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal. Table 2 PCI Express Interface Pins (Part 2 of 2) Signal Type Name/Description MSMBADDR[4:1] I MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. It is active and generating the clock only when the EEPROM or I/O Expanders are being accessed. MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the master SMBus. Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. Table 3 SMBus Interface Pins (Part 1 of 2) 5 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Signal Type Name/Description SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the slave SMBus. SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Table 3 SMBus Interface Pins (Part 2 of 2) Signal Type Name/Description GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[1] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[2] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[3] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[4] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[5] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output GPIO[6] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P1RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 1 GPIO[7] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 GPIO[8] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P3RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 3 GPIO[9] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P4RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 4 Table 4 General Purpose I/O Pins (Part 1 of 3) 6 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Signal Type Name/Description GPIO[10] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P5RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 5 GPIO[11] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P6RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 6 GPIO[12] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P7RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 7 GPIO[13] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P8RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 8 GPIO[14] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P9RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 9 GPIO[15] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P10RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 10 GPIO[16] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P11RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 11 GPIO[17] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[18] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[19] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[20] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[21] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 0 Table 4 General Purpose I/O Pins (Part 2 of 3) 7 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Signal Type Name/Description GPIO[22] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN1 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 1 GPIO[23] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN2 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 2 GPIO[24] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN3 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 3 GPIO[25] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN4 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 4 GPIO[26] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN5 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 5 GPIO[27] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[28] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[29] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[30] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[31] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN10 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 10 Table 4 General Purpose I/O Pins (Part 3 of 3) Signal Type Name/Description CCLKDS I Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a common clock is being used between the downstream device and the downstream port. CCLKUS I Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a common clock is being used between the upstream device and the upstream port. MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden. Table 5 System Pins (Part 1 of 2) 8 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Signal Type Name/Description P01MERGEN I Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled low internally via a 251K ohm resistor. When this pin is low, port 0 is merged with port 1 to form a single x8 port. The Serdes lanes associated with port 1 become lanes 4 through 7 of port 0. When this pin is high, port 0 and port 1 are not merged, and each operates as a single x4 port. P23MERGEN I Port 2 and 3 Merge. P23MERGEN is an active low signal. It is pulled low internally via a 251K ohm resistor. When this pin is low, port 2 is merged with port 3 to form a single x8 port. The Serdes lanes associated with port 3 become lanes 4 through 7 of port 2. When this pin is high, port 2 and port 3 are not merged, and each operates as a single x4 port. P45MERGEN I Port 4 and 5 Merge. P45MERGEN is an active low signal. It is pulled low internally via a 251K ohm resistor. When this pin is low, port 4 is merged with port 5 to form a single x8 port. The Serdes lanes associated with port 5 become lanes 4 through 7 of port 4. When this pin is high, port 4 and port 5 are not merged, and each operates as a single x4 port. P67MERGEN I Port 6 and 7 Merge. P67MERGEN is an active low signal. It is pulled low internally via a 251K ohm resistor. When this pin is low, port 6 is merged with port 7 to form a single x8 port. The Serdes lanes associated with port 7 become lanes 4 through 7 of port 6. When this pin is high, port 6 and port 7 are not merged, and each operates as a single x4 port. P89MERGEN I Port 8 and 9 Merge. P89MERGEN is an active low signal. It is pulled low internally via a 251K ohm resistor. When this pin is low, port 8 is merged with port 9 to form a single x8 port. The Serdes lanes associated with port 9 become lanes 4 through 7 of port 8. When this pin is high, port 8 and port 9 are not merged, and each operates as a single x4 port. P1011MERGEN I Port 10 and 11 Merge. P67MERGEN is an active low signal. It is pulled low internally via a 251K ohm resistor. When this pin is low, port 10 is merged with port 11 to form a single x8 port. The Serdes lanes associated with port 11 become lanes 4 through 7 of port 10. When this pin is high, port 10 and port 11 are not merged, and each operates as a single x4 port. PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside PES48H12 and initiates a PCI Express fundamental reset. RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, PES48H12 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the PA_SWCTL register by an SMBus master. SWMODE[3:0] I Switch Mode. These configuration pins determine the PES48H12 switch operating mode. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 through 0x7 - Reserved 0x8 - Normal switch mode with upstream port failover (port 0 selected as the upstream port) 0x9 - Normal switch mode with upstream port failover (port 2 selected as the upstream port) 0xA - Normal switch mode with Serial EEPROM initialization and upstream port failover (port 0 selected as the upstream port) 0xB - Normal switch mode with Serial EEPROM initialization and upstream port failover (port 2 selected as the upstream port) 0xC through 0xF - Reserved Table 5 System Pins (Part 2 of 2) 9 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Signal Type Name/Description JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 6 Test Pins Signal Type Name/Description VDDCORE I Core VDD. Power supply for core logic. VDDIO I I/O VDD. LVTTL I/O buffer power supply. VDDPE I PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. VDDAPE I PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. VSS I Ground. VTTPE I PCI Express Serial Data Transmit Termination Voltage. This pin allows the driver termination voltage to be set, enabling the system designer to control the Common Mode Voltage and output voltage swing of the corresponding PCI Serial Data Transmit differential pair. Table 7 Power and Ground Pins 10 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Pin Characteristics Note: Some input pads of the PES48H12 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption. Function Pin Name Type Buffer I/O Type PCI Express Interface PE0RN[3:0] I CML Serial Link PE0RP[3:0] I PE0TN[3:0] O PE0TP[3:0] O PE1RN[3:0] I PE1RP[3:0] I PE1TN[3:0] O PE1TP[3:0] O PE2RN[3:0] I PE2RP[3:0] I PE2TN[3:0] O PE2TP[3:0] O PE3RN[3:0] I PE3RP[3:0] I PE3TN[3:0] O PE3TP[3:0] O PE4RN[3:0] I PE4RP[3:0] I PE4TN[3:0] O PE4TP[3:0] O PE5RN[3:0] I PE5RP[3:0] I PE5TN[3:0] O PE5TP[3:0] O PE6RN[3:0] I PE6RP[3:0] I PE6TN[3:0] O PE6TP[3:0] O PE7RN[3:0] I PE7RP[3:0] I PE7TN[3:0] O PE7TP[3:0] O Internal Resistor Notes Table 8 Pin Characteristics (Part 1 of 3) 11 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Function Pin Name Type Buffer I/O Type PCI Express Interface (cont.) PE8RN[3:0] I CML Serial Link LVPECL/ CML Diff. Clock Input SMBus Interface PE8RP[3:0] I PE8TN[3:0] O PE8TP[3:0] O PE9RN[3:0] I PE9RP[3:0] I PE9TN[3:0] O PE9TP[3:0] O PE10RN[3:0] I PE10RP[3:0] I PE10TN[3:0] O PE10TP[3:0] O PE11RN[3:0] I PE11RP[3:0] I PE11TN[3:0] O PE11TP[3:0] O PEREFCLKN[3:0] I Internal Resistor Refer to Table 9 PEREFCLKP[3:0] I REFCLKM I LVTTL Input pull-down MSMBADDR[4:1] I LVTTL STI1 pull-up MSMBCLK I/O STI MSMBDAT I/O STI SSMBADDR[5,3:1] I Notes pull-up SSMBCLK I/O STI SSMBDAT I/O STI General Purpose I/O GPIO[31:0] I/O LVTTL System Pins CCLKDS I LVTTL CCLKUS I pull-up MSMBSMODE I pull-down P01MERGEN I pull-down P23MERGEN I pull-down P45MERGEN I pull-down P67MERGEN I pull-down P89MERGEN I pull-down P1011MERGEN I pull-down PERSTN I RSTHALT I pull-down SWMODE[3:0] I pull-down pull-up Input pull-up Table 8 Pin Characteristics (Part 2 of 3) 12 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Function Pin Name Type Buffer I/O Type Internal Resistor EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up STI pull-up 1. JTAG_TDI I JTAG_TDO O JTAG_TMS I STI pull-up JTAG_TRST_N I STI pull-up Schmitt Trigger Input (STI). Notes External pull-down Table 8 Pin Characteristics (Part 3 of 3) 13 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Logic Diagram — PES48H12 Reference Clock PEREFCLKP[3:0] PEREFCLKN[3:0] REFCLKM 4 4 PE0TP[0] PE0TN[0] PE0RP[0] PE0RN[0] PE0RP[3] PE0RN[3] PE0TP[3] PE0TN[3] PCI Express Switch SerDes Input Port 1 PE1RP[0] PE1RN[0] PE1TP[0] PE1TN[0] PE1RP[3] PE1RN[3] PE1TP[3] PE1TN[3] PCI Express Switch SerDes Input Port 2 PE2RP[0] PE2RN[0] PE2TP[0] PE2TN[0] PE2RP[3] PE2RN[3] PE2TP[3] PE2TN[3] PCI Express Switch SerDes Input Port 3 PE3RP[0] PE3RN[0] PE3TP[0] PE3TN[0] PCI Express Switch SerDes Input Port 11 PE11RP[0] PE11RN[0] ... ... ... ... ... ... ... ... PCI Express Switch SerDes Input Port 0 PE3TP[3] PE3TN[3] PES48H12 ... PE11TP[0] PE11TN[0] ... Master SMBus Interface PE11RP[3] PE11RN[3] MSMBADDR[4:1] MSMBCLK MSMBDAT PE11TP[3] PE11TN[3] 4 4 32 System Pins MSMBSMODE CCLKDS CCLKUS RSTHALT PERSTN SWMODE[3:0] P01MERGEN P23MERGEN P45MERGEN P67MERGEN P89MERGEN P1011MERGEN PCI Express Switch SerDes Output Port 1 PCI Express Switch SerDes Output Port 2 PCI Express Switch SerDes Output Port 3 ... ... PE3RP[3] PE3RN[3] PCI Express Switch SerDes Output Port 0 SSMBADDR[5,3:1] SSMBCLK SSMBDAT GPIO[31:0] JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N 4 VDDCORE VDDIO VDDPE VDDAPE VSS PCI Express Switch SerDes Output Port 11 Slave SMBus Interface General Purpose I/O JTAG Pins Power/Ground VTTPE Figure 4 PES48H12 Logic Diagram 14 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. Parameter Description Min Typical Max Unit 1251 MHz 60 % 0.2*RCUI RCUI3 1.6 V 125 ps PEREFCLK RefclkFREQ Input reference clock frequency range 100 RefclkDC2 Duty cycle of input clock 40 TR, TF Rise/Fall time of input clocks VSW Differential input voltage swing4 Tjitter Input clock jitter (cycle-to-cycle) RT Termination Resistor 50 0.6 110 Ohms Table 9 Input Clock Requirements 1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM. 2. ClkIn must be AC coupled. Use 0.01 — 0.1 µF ceramic capacitors. 3. RCUI (Reference Clock Unit Interval) refers to the reference clock period. 4. AC coupling required. AC Timing Characteristics Parameter Description Min1 Typical1 Max1 Units 399.88 400 400.12 ps 0.7 .9 PCIe Transmit UI Unit Interval TTX-EYE Minimum Tx Eye Width TTX-EYE-MEDIAN-toMAX-JITTER Maximum time between the jitter median and maximum deviation from the median TTX-RISE, TTX-FALL D+ / D- Tx output rise/fall time 50 TTX- IDLE-MIN Minimum time in idle 50 TTX-IDLE-SET-TO- Maximum time to transition to a valid Idle after sending an Idle ordered set 20 UI IDLE TTX-IDLE-TO-DIFF- Maximum time to transition from valid idle to diff data 20 UI 500 1300 ps 400 400.12 ps UI 0.15 90 UI ps UI DATA TTX-SKEW Transmitter data skew between any 2 lanes PCIe Receive UI Unit Interval 399.88 TRX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) TRX-EYE-MEDIUM TO Max time between jitter median & max deviation 0.3 UI Unexpected Idle Enter Detect Threshold Integration Time 10 ms Lane to lane input skew 20 ns 0.4 UI MAX JITTER TRX-IDLE-DET-DIFFENTER TIME TRX-SKEW Table 10 PCIe AC Timing Characteristics 15 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1 Signal Symbol Reference Edge Min Tpw_13b2 None 50 Max Unit Timing Diagram Reference GPIO GPIO[31:0]1 — ns See Figure 5. Table 11 GPIO AC Timing Characteristics 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. 2. The values for this symbol were determined by calculation, not by testing. EXTCLK Tpw_13b GPIO (asynchronous input) Figure 5 GPIO AC Timing Waveform Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference Tper_16a none 50.0 — ns See Figure 6. 10.0 25.0 ns 2.4 — ns 1.0 — ns — 20 ns — 20 ns 25.0 — ns JTAG JTAG_TCK Thigh_16a, Tlow_16a JTAG_TMS1, JTAG_TDI JTAG_TDO Tsu_16b JTAG_TCK rising Thld_16b Tdo_16c JTAG_TCK falling Tdz_16c2 JTAG_TRST_N Tpw_16d2 none Table 12 JTAG AC Timing Characteristics 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. 2. The values for this symbol were determined by calculation, not by testing. 16 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Tlow_16a Tper_16a Thigh_16a JTAG_TCK Thld_16b Tsu_16b JTAG_TDI Thld_16b Tsu_16b JTAG_TMS Tdo_16c Tdz_16c JTAG_TDO Tpw_16d JTAG_TRST_N Figure 6 JTAG AC Timing Waveform Recommended Operating Supply Voltages Symbol Parameter Minimum Typical Maximum Unit VDDCORE Internal logic supply 0.9 1.0 1.1 V VDDI/O I/O supply except for SerDes LVPECL/CML 3.0 3.3 3.6 V VDDPE PCI Express Digital Power 0.9 1.0 1.1 V VDDAPE PCI Express Analog Power 0.9 1.0 1.1 V VTTPE PCI Express Serial Data Transmit Termination Voltage 1.425 1.5 1.575 V VSS Common ground 0 0 0 V Table 13 PES48H12 Operating Voltages Power-Up Sequence This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the PES48H12, the power-up sequence must be as follows: 1. VDDI/O — 3.3V 2. VDDCore, VDDPE, VDDAPE — 1.0V 3. VTTPE — 1.5V When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations in ramping to valid power levels. The power-down sequence must be in the reverse order of the power-up sequence. 17 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Recommended Operating Temperature Grade Temperature Commercial 0°C to +70°C Ambient Industrial -40°C to +85°C Ambient Table 14 PES48H12 Operating Temperatures Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below). Core Supply PCIe Digital Supply PCIe Analog Supply PCIe Termination Supply Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 1.5V Max 1.575V Typ 3.3V Max 3.6V mA 2254 2774 2268 2797 966 1186 1133 1397 4 4 Watts 2.26 3.05 2.27 3.08 0.97 1.31 1.7 2.2 0.01 0.01 Number of active Lanes per Port 8/8/8/8/8/8 I/O Supply Total Typ Power Max Power 7.21W 9.65W Table 15 PES48H12 Power Consumption 18 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Thermal Considerations This section describes thermal considerations for the PES48H12 (35mm2 FCBGA1156 package). The data in Table 16 below contains information that is relevant to the thermal performance of the PES48H12 switch. Symbol Parameter Value TJ(max) Junction Temperature 125 o Maximum 70 o TA(max) θJA(effective) θJB Ambient Temperature Effective Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Board Units Conditions C C Maximum for commercial-rated products 12.6 o C/W Zero air flow 6.4 o 1 m/S air flow 5.4 o 2 m/S air flow 2.1 o C/W C/W C/W θJC Thermal Resistance, Junction-to-Case 0.1 oC/W P Power Dissipation of the Device 6.82 Watts Maximum Table 16 Thermal Specifications for PES48H12, 35x35mm FCBGA1156 Package Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value specified in Table 16. Consequently, the effective junction to ambient thermal resistance (θJA) for the worst case scenario must be maintained below the value determined by the formula: θJA = (TJ(max) - TA(max))/P Given that the values of TJ(max), TA(max), and P are known, the value of desired θJA becomes a known entity to the system designer. How to achieve the desired θJA is left up to the board or system designer, but in general, it can be achieved by adding the effects of θJC (value provided in Table 16), thermal resistance of the chosen adhesive (θCS), that of the heat sink (θSA), amount of airflow, and properties of the circuit board (number of layers and size of the board). As a general guideline, this device will not need a heat sink if the board has 10 or more layers AND the board size is larger than 4"x12" AND airflow in excess of 1 m/s is available. It is strongly recommended that users perform their own thermal analysis for their own board and system design scenarios. 19 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Serial Link Parameter Min1 Description Typ1 Max1 Unit 800 1200 mV -3 -4 dB 3.7 V Conditions PCIe Transmit VTX-DIFFp-p VTX-DE-RATIO Differential peak-to-peak output voltage De-emphasized differential output voltage VTX-DC-CM DC Common mode voltage VTX-CM-ACP RMS AC peak common mode output voltage 20 mV VTX-CM-DC- Abs delta of DC common mode voltage between L0 and idle 100 mV Abs delta of DC common mode voltage between D+ and D- 25 mV Electrical idle diff peak output 20 mV Voltage change during receiver detection 600 mV active-idle-delta VTX-CM-DC-linedelta VTX-Idle-DiffP VTX-RCV-Detect -0.1 1 RLTX-DIFF Transmitter Differential Return loss 12 dB RLTX-CM Transmitter Common Mode Return loss 6 dB ZTX-DEFF-DC DC Differential TX impedance 80 100 120 Ω ZOSE Single ended TX Impedance 40 50 60 Ω Transmitter Eye Diagram TX Eye Height (De-emphasized bits) 505 650 mV Transmitter Eye Diagram TX Eye Height (Transition bits) 800 950 mV VRX-DIFFp-p Differential input voltage (peak-to-peak) 175 VRX-CM-AC Receiver common-mode voltage for AC coupling RLRX-DIFF Receiver Differential Return Loss 15 dB RLRX-CM Receiver Common Mode Return Loss 6 dB Differential input impedance (DC) 80 100 120 Ω Single-ended input impedance 40 50 60 Ω 200k 350k PCIe Receive ZRX-DIFF-DC ZRX-COMM-DC ZRX-COMM-HIGH- Powered down input common mode impedance (DC) Z-DC VRX-IDLE-DET- Electrical idle detect threshold 65 Input Capacitance 1.5 1200 mV 150 mV Ω 175 mV DIFFp-p PCIe REFCLK CIN — pF Table 17 DC Electrical Characteristics (Part 1 of 2) 20 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet I/O Type Min1 Typ1 Max1 Unit Conditions IOL — 2.5 — mA VOL = 0.4v IOH — -5.5 — mA VOH = 1.5V IOL — 12.0 — mA VOL = 0.4v IOH — -20.0 — mA VOH = 1.5V Parameter Description Other I/Os LOW Drive Output High Drive Output Schmitt Trigger Input (STI) VIL -0.3 — 0.8 V — VIH 2.0 — VDDIO + 0.5 V — Input VIL -0.3 — 0.8 V — VIH 2.0 — VDDIO + 0.5 V — CIN — — 8.5 pF — Inputs — — + 10 μA VDDI/O (max) I/OLEAK W/O Pull-ups/downs — — + 10 μA VDDI/O (max) I/OLEAK WITH Pull-ups/downs — — + 80 μA VDDI/O (max) Capacitance Leakage Table 17 DC Electrical Characteristics (Part 2 of 2) 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a. 21 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Package Pinout — 1156-BGA Signal Pinout for PES48H12 The following table lists the pin numbers and signal names for the PES48H12 device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function A1 VSS B1 VSS C1 GPIO_29 D1 GPIO_28 A2 VSS B2 VDDIO C2 GPIO_27 D2 GPIO_26 A3 GPIO_19 B3 GPIO_18 C3 GPIO_21 1 D3 VDDIO A4 VDDIO B4 GPIO_17 C4 GPIO_16 1 D4 GPIO_23 A5 VSS B5 VSS C5 VSS D5 VSS A6 PE9TP03 B6 PE9TN03 C6 VSS D6 PE9RP03 A7 PE9TP02 B7 PE9TN02 C7 VSS D7 PE9RP02 A8 VSS B8 VSS C8 VSS D8 VSS A9 PE9TP01 B9 PE9TN01 C9 VSS D9 PE9RP01 A10 PE9TP00 B10 PE9TN00 C10 VSS D10 PE9RP00 A11 VSS B11 VSS C11 VSS D11 VSS A12 PE8TP03 B12 PE8TN03 C12 VSS D12 PE8RP03 A13 PE8TP02 B13 PE8TN02 C13 VSS D13 PE8RP02 A14 VSS B14 VSS C14 VSS D14 VSS A15 PE8TP01 B15 PE8TN01 C15 VSS D15 PE8RP01 A16 PE8TP00 B16 PE8TN00 C16 VSS D16 PE8RP00 A17 VSS B17 VSS C17 VSS D17 VSS A18 PE3TP03 B18 PE3TN03 C18 VSS D18 PE3RP03 A19 PE3TP02 B19 PE3TN02 C19 VSS D19 PE3RP02 A20 VSS B20 VSS C20 VSS D20 VSS A21 PE3TP01 B21 PE3TN01 C21 VSS D21 PE3RP01 A22 PE3TP00 B22 PE3TN00 C22 VSS D22 PE3RP00 A23 VSS B23 VSS C23 VSS D23 VSS A24 PE2TP03 B24 PE2TN03 C24 VSS D24 PE2RP03 A25 PE2TP02 B25 PE2TN02 C25 VSS D25 PE2RP02 A26 VSS B26 VSS C26 VSS D26 VSS A27 PE2TP01 B27 PE2TN01 C27 VSS D27 PE2RP01 A28 PE2TP00 B28 PE2TN00 C28 VSS D28 PE2RP00 A29 VSS B29 VSS C29 VSS D29 VSS A30 VDDIO B30 MSMBADDR_3 C30 MSMBADDR_4 D30 JTAG_TMS A31 MSMBADDR_1 B31 MSMBADDR_2 C31 JTAG_TDI D31 VDDIO A32 MSMBSMODE B32 PERSTN C32 JTAG_TRST_N D32 SSMBADDR_5 A33 VSS B33 VDDIO C33 SSMBADDR_2 D33 SSMBADDR_3 A34 VSS B34 VSS C34 SSMBADDR_1 D34 VDDIO Alt 1 1 Table 18 PES48H12 1156-pin Signal Pin-Out (Part 1 of 9) 22 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Pin Function Alt Pin Function Alt Pin Function Alt Pin Function E1 VDDIO F1 VSS G1 PE10TP00 H1 PE10TP01 E2 GPIO_30 F2 VSS G2 PE10TN00 H2 PE10TN01 E3 GPIO_31 1 F3 VSS G3 VSS H3 VSS E4 GPIO_24 1 F4 VSS G4 PE10RP00 H4 PE10RP01 E5 VSS F5 VSS G5 PE10RN00 H5 PE10RN01 E6 PE9RN03 F6 VSS G6 VSS H6 VSS E7 PE9RN02 F7 VSS G7 VSS H7 VSS E8 VSS F8 VSS G8 VSS H8 GPIO_20 E9 PE9RN01 F9 VSS G9 VSS H9 VDDIO E10 PE9RN00 F10 VSS G10 VSS H10 VSS E11 VSS F11 VSS G11 VSS H11 VSS E12 PE8RN03 F12 VSS G12 VSS H12 VSS E13 PE8RN02 F13 VSS G13 VSS H13 VTTPE E14 VSS F14 VSS G14 VSS H14 VSS E15 PE8RN01 F15 VSS G15 VSS H15 VDDAPE E16 PE8RN00 F16 VSS G16 VSS H16 VSS E17 VSS F17 VSS G17 PEREFCLKP1 H17 VSS E18 PE3RN03 F18 VSS G18 PEREFCLKN1 H18 VSS E19 PE3RN02 F19 VSS G19 VSS H19 VSS E20 VSS F20 VSS G20 VSS H20 VDDAPE E21 PE3RN01 F21 VSS G21 VSS H21 VSS E22 PE3RN00 F22 VSS G22 VSS H22 VTTPE E23 VSS F23 VSS G23 VSS H23 VSS E24 PE2RN03 F24 VSS G24 VSS H24 VSS E25 PE2RN02 F25 VSS G25 VSS H25 VSS E26 VSS F26 VSS G26 VSS H26 MSMBDAT E27 PE2RN01 F27 VSS G27 MSMBCLK H27 VDDIO E28 PE2RN00 F28 VSS G28 VSS H28 SSMBCLK E29 VSS F29 VSS G29 VSS H29 VSS E30 VSS F30 PE1RN03 G30 PE1RN02 H30 VSS E31 VSS F31 PE1RP03 G31 PE1RP02 H31 VSS E32 VSS F32 VSS G32 VSS H32 VSS E33 VSS F33 PE1TN03 G33 PE1TN02 H33 VSS E34 VSS F34 PE1TP03 G34 PE1TP02 H34 VSS Alt Table 18 PES48H12 1156-pin Signal Pin-Out (Part 2 of 9) 23 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Pin Function Alt Pin Function Alt Pin Function Alt Pin Function J1 VSS K1 PE10TP02 L1 PE10TP03 M1 VSS J2 VSS K2 PE10TN02 L2 PE10TN03 M2 VSS J3 VSS K3 VSS L3 VSS M3 VSS J4 VSS K4 PE10RP02 L4 PE10RP03 M4 VSS J5 VSS K5 PE10RN02 L5 PE10RN03 M5 VSS J6 VSS K6 VSS L6 VSS M6 VSS J7 VSS K7 VSS L7 VSS M7 VSS J8 VSS K8 VSS L8 VSS M8 VSS J9 GPIO_25 K9 VDDIO L9 VSS M9 VSS J10 VSS K10 GPIO_22 L10 VSS M10 VSS J11 VSS K11 VSS L11 VSS M11 VSS J12 VSS K12 VSS L12 VSS M12 VSS J13 VSS K13 VTTPE L13 VDDPE M13 VDDPE J14 VDDPE K14 VSS L14 VDDPE M14 VSS J15 VSS K15 VDDAPE L15 VDDPE M15 VDDPE J16 VSS K16 VSS L16 VSS M16 VSS J17 VTTPE K17 VTTPE L17 VDDPE M17 VDDPE J18 VTTPE K18 VTTPE L18 VDDPE M18 VDDPE J19 VSS K19 VSS L19 VSS M19 VSS J20 VSS K20 VDDAPE L20 VDDPE M20 VDDPE J21 VDDPE K21 VSS L21 VDDPE M21 VSS J22 VSS K22 VTTPE L22 VDDPE M22 VDDPE J23 VSS K23 VSS L23 VSS M23 VSS J24 VSS K24 VSS L24 VSS M24 VSS J25 JTAG_TDO K25 CCLKDS L25 VSS M25 VSS J26 VDDIO K26 JTAG_TCK L26 VSS M26 VSS J27 SSMBDAT K27 VSS L27 VSS M27 VSS J28 VSS K28 VSS L28 VSS M28 VSS J29 VSS K29 VSS L29 VSS M29 VSS J30 PE1RN01 K30 PE1RN00 L30 VSS M30 PE0RN03 J31 PE1RP01 K31 PE1RP00 L31 VSS M31 PE0RP03 J32 VSS K32 VSS L32 VSS M32 VSS J33 PE1TN01 K33 PE1TN00 L33 VSS M33 PE0TN03 J34 PE1TP01 K34 PE1TP00 L34 VSS M34 PE0TP03 1 1 Alt Table 18 PES48H12 1156-pin Signal Pin-Out (Part 3 of 9) 24 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Pin Function Alt Pin Function Alt Pin Function Alt Pin Function N1 PE11TP00 P1 PE11TP01 R1 VSS T1 PE11TP02 N2 PE11TN00 P2 PE11TN01 R2 VSS T2 PE11TN02 N3 VSS P3 VSS R3 VSS T3 VSS N4 PE11RP00 P4 PE11RP01 R4 VSS T4 PE11RP02 N5 PE11RN00 P5 PE11RN01 R5 VSS T5 PE11RN02 N6 VSS P6 VSS R6 VSS T6 VSS N7 VSS P7 VSS R7 VSS T7 VSS N8 VTTPE P8 VSS R8 VDDAPE T8 VSS N9 VSS P9 VDDPE R9 VSS T9 VSS N10 VTTPE P10 VSS R10 VDDAPE T10 VSS N11 VDDPE P11 VDDPE R11 VDDPE T11 VSS N12 VDDPE P12 VSS R12 VDDPE T12 VSS N13 VDDCORE P13 VDDCORE R13 VDDCORE T13 VSS N14 VDDCORE P14 VSS R14 VDDCORE T14 VSS N15 VDDCORE P15 VDDCORE R15 VSS T15 VDDCORE N16 VSS P16 VSS R16 VDDCORE T16 VSS N17 VDDCORE P17 VDDCORE R17 VSS T17 VDDCORE N18 VSS P18 VSS R18 VDDCORE T18 VSS N19 VDDCORE P19 VDDCORE R19 VSS T19 VDDCORE N20 VDDCORE P20 VSS R20 VDDCORE T20 VSS N21 VDDCORE P21 VDDCORE R21 VSS T21 VDDCORE N22 VDDCORE P22 VDDCORE R22 VDDCORE T22 VDDCORE N23 VDDPE P23 VSS R23 VDDPE T23 VSS N24 VDDPE P24 VDDPE R24 VDDPE T24 VSS N25 VTTPE P25 VSS R25 VDDAPE T25 VSS N26 VSS P26 VDDPE R26 VSS T26 VSS N27 VTTPE P27 VSS R27 VDDAPE T27 VSS N28 VSS P28 VSS R28 VSS T28 VSS N29 VSS P29 VSS R29 VSS T29 VSS N30 PE0RN02 P30 VSS R30 PE0RN01 T30 PE0RN00 N31 PE0RP02 P31 VSS R31 PE0RP01 T31 PE0RP00 N32 VSS P32 VSS R32 VSS T32 VSS N33 PE0TN02 P33 VSS R33 PE0TN01 T33 PE0TN00 N34 PE0TP02 P34 VSS R34 PE0TP01 T34 PE0TP00 Alt Table 18 PES48H12 1156-pin Signal Pin-Out (Part 4 of 9) 25 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Pin Function Alt Pin Function Alt Pin Function Alt Pin Function U1 PE11TP03 V1 VSS W1 PE4TP00 Y1 PE4TP01 U2 PE11TN03 V2 VSS W2 PE4TN00 Y2 PE4TN01 U3 VSS V3 VSS W3 VSS Y3 VSS U4 PE11RP03 V4 VSS W4 PE4RP00 Y4 PE4RP01 U5 PE11RN03 V5 VSS W5 PE4RN00 Y5 PE4RN01 U6 VSS V6 VSS W6 VSS Y6 VSS U7 PEREFCLKN2 V7 PEREFCLKP2 W7 VSS Y7 VSS U8 VSS V8 VSS W8 VSS Y8 VDDAPE U9 VTTPE V9 VTTPE W9 VSS Y9 VSS U10 VTTPE V10 VTTPE W10 VSS Y10 VDDAPE U11 VDDPE V11 VDDPE W11 VSS Y11 VDDPE U12 VDDPE V12 VDDPE W12 VSS Y12 VDDPE U13 VDDCORE V13 VSS W13 VDDCORE Y13 VDDCORE U14 VDDCORE V14 VSS W14 VDDCORE Y14 VSS U15 VSS V15 VDDCORE W15 VSS Y15 VDDCORE U16 VDDCORE V16 VSS W16 VDDCORE Y16 VSS U17 VSS V17 VDDCORE W17 VSS Y17 VDDCORE U18 VDDCORE V18 VSS W18 VDDCORE Y18 VSS U19 VSS V19 VDDCORE W19 VSS Y19 VDDCORE U20 VDDCORE V20 VSS W20 VDDCORE Y20 VSS U21 VSS V21 VDDCORE W21 VSS Y21 VDDCORE U22 VSS V22 VDDCORE W22 VSS Y22 VDDCORE U23 VDDPE V23 VDDPE W23 VSS Y23 VDDPE U24 VDDPE V24 VDDPE W24 VSS Y24 VDDPE U25 VTTPE V25 VTTPE W25 VSS Y25 VDDAPE U26 VTTPE V26 VTTPE W26 VSS Y26 VSS U27 VSS V27 VSS W27 VSS Y27 VDDAPE U28 PEREFCLKP0 V28 PEREFCLKN0 W28 VSS Y28 VSS U29 VSS V29 VSS W29 VSS Y29 VSS U30 VSS V30 NC W30 NC Y30 VSS U31 VSS V31 NC W31 NC Y31 VSS U32 VSS V32 VSS W32 VSS Y32 VSS U33 VSS V33 NC W33 NC Y33 VSS U34 VSS V34 NC W34 NC Y34 VSS Alt Table 18 PES48H12 1156-pin Signal Pin-Out (Part 5 of 9) 26 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Pin Function Alt Pin Function Alt Pin Function Alt Pin Function AA1 VSS AB1 PE4TP02 AC1 PE4TP03 AD1 VSS AA2 VSS AB2 PE4TN02 AC2 PE4TN03 AD2 VSS AA3 VSS AB3 VSS AC3 VSS AD3 VSS AA4 VSS AB4 PE4RP02 AC4 PE4RP03 AD4 VSS AA5 VSS AB5 PE4RN02 AC5 PE4RN03 AD5 VSS AA6 VSS AB6 VSS AC6 VSS AD6 VSS AA7 VSS AB7 VSS AC7 VSS AD7 VSS AA8 VSS AB8 VTTPE AC8 VSS AD8 VSS AA9 VDDPE AB9 VSS AC9 VSS AD9 VSS AA10 VSS AB10 VTTPE AC10 VSS AD10 VSS AA11 VDDPE AB11 VDDPE AC11 VSS AD11 VSS AA12 VSS AB12 VDDPE AC12 VSS AD12 VSS AA13 VDDCORE AB13 VDDCORE AC13 VDDPE AD13 VDDPE AA14 VDDCORE AB14 VDDCORE AC14 VSS AD14 VDDPE AA15 VSS AB15 VDDCORE AC15 VDDPE AD15 VDDPE AA16 VDDCORE AB16 VDDCORE AC16 VSS AD16 VSS AA17 VSS AB17 VSS AC17 VDDPE AD17 VDDPE AA18 VDDCORE AB18 VDDCORE AC18 VDDPE AD18 VDDPE AA19 VSS AB19 VSS AC19 VSS AD19 VSS AA20 VDDCORE AB20 VDDCORE AC20 VDDPE AD20 VDDPE AA21 VSS AB21 VDDCORE AC21 VSS AD21 VDDPE AA22 VDDCORE AB22 VDDCORE AC22 VDDPE AD22 VDDPE AA23 VSS AB23 VDDPE AC23 VSS AD23 VSS AA24 VDDPE AB24 VDDPE AC24 VSS AD24 VSS AA25 VSS AB25 VTTPE AC25 VSS AD25 VSS AA26 VDDPE AB26 VSS AC26 VSS AD26 VSS AA27 VSS AB27 VTTPE AC27 VSS AD27 VSS AA28 VSS AB28 VSS AC28 VSS AD28 VSS AA29 VSS AB29 VSS AC29 VSS AD29 VSS AA30 NC AB30 NC AC30 VSS AD30 NC AA31 NC AB31 NC AC31 VSS AD31 NC AA32 VSS AB32 VSS AC32 VSS AD32 VSS AA33 NC AB33 NC AC33 VSS AD33 NC AA34 NC AB34 NC AC34 VSS AD34 NC Alt Table 18 PES48H12 1156-pin Signal Pin-Out (Part 6 of 9) 27 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Pin Function Alt Pin Function Alt Pin Function Alt Pin Function AE1 PE5TP00 AF1 PE5TP01 AG1 VSS AH1 PE5TP02 AE2 PE5TN00 AF2 PE5TN01 AG2 VSS AH2 PE5TN02 AE3 VSS AF3 VSS AG3 VSS AH3 VSS AE4 PE5RP00 AF4 PE5RP01 AG4 VSS AH4 PE5RP02 AE5 PE5RN00 AF5 PE5RN01 AG5 VSS AH5 PE5RN02 AE6 VSS AF6 VSS AG6 VSS AH6 VSS AE7 VSS AF7 VSS AG7 CCLKUS AH7 VSS AE8 VSS AF8 VSS AG8 VDDIO AH8 REFCLKM AE9 VDDIO AF9 VDDIO AG9 VDDIO AH9 VSS AE10 VSS AF10 VDDIO AG10 VSS AH10 VSS AE11 VSS AF11 VSS AG11 VSS AH11 VSS AE12 VSS AF12 VSS AG12 VSS AH12 VSS AE13 VTTPE AF13 VSS AG13 VTTPE AH13 VSS AE14 VSS AF14 VDDPE AG14 VSS AH14 VSS AE15 VDDAPE AF15 VSS AG15 VDDAPE AH15 VSS AE16 VSS AF16 VSS AG16 VSS AH16 VSS AE17 VTTPE AF17 VTTPE AG17 VSS AH17 PEREFCLKN3 AE18 VTTPE AF18 VTTPE AG18 VSS AH18 PEREFCLKP3 AE19 VSS AF19 VSS AG19 VSS AH19 VSS AE20 VDDAPE AF20 VSS AG20 VDDAPE AH20 VSS AE21 VSS AF21 VDDPE AG21 VSS AH21 VSS AE22 VTTPE AF22 VSS AG22 VTTPE AH22 VSS AE23 VSS AF23 VSS AG23 VSS AH23 VSS AE24 VSS AF24 VSS AG24 VSS AH24 VSS AE25 GPIO_06 AF25 VSS AG25 VSS AH25 VSS AE26 VDDIO AF26 GPIO_09 AG26 VDDIO AH26 VSS AE27 VSS AF27 VSS AG27 GPIO_04 AH27 VSS AE28 VSS AF28 VSS AG28 VSS AH28 VSS AE29 VSS AF29 VSS AG29 VSS AH29 VSS AE30 NC AF30 VSS AG30 NC AH30 NC AE31 NC AF31 VSS AG31 NC AH31 NC AE32 VSS AF32 VSS AG32 VSS AH32 VSS AE33 NC AF33 VSS AG33 NC AH33 NC AE34 NC AF34 VSS AG34 NC AH34 NC 1 1 Alt Table 18 PES48H12 1156-pin Signal Pin-Out (Part 7 of 9) 28 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Pin Function Alt Pin Function Alt Pin Function Alt Pin Function AJ1 PE5TP03 AK1 VSS AL1 VDDIO AM1 P23MERGEN AJ2 PE5TN03 AK2 VSS AL2 P01MERGEN AM2 P67MERGEN AJ3 VSS AK3 VSS AL3 P45MERGEN AM3 VSS AJ4 PE5RP03 AK4 VSS AL4 VDDIO AM4 P1011MERGEN AJ5 PE5RN03 AK5 VSS AL5 P89MERGEN AM5 SWMODE_3 AJ6 VSS AK6 VSS AL6 VSS AM6 VSS AJ7 VSS AK7 PE6RN00 AL7 PE06RP00 AM7 VSS AJ8 VSS AK8 PE6RN01 AL8 PE06RP01 AM8 VSS AJ9 VSS AK9 VSS AL9 VSS AM9 VSS AJ10 VSS AK10 PE6RN02 AL10 PE6RP02 AM10 VSS AJ11 VSS AK11 PE6RN03 AL11 PE6RP03 AM11 VSS AJ12 VSS AK12 VSS AL12 VSS AM12 VSS AJ13 VSS AK13 PE7RN00 AL13 PE7RP00 AM13 VSS AJ14 VSS AK14 PE7RN01 AL14 PE7RP01 AM14 VSS AJ15 VSS AK15 VSS AL15 VSS AM15 VSS AJ16 VSS AK16 PE7RN02 AL16 PE7RP02 AM16 VSS AJ17 VSS AK17 PE7RN03 AL17 PE7RP03 AM17 VSS AJ18 VSS AK18 VSS AL18 VSS AM18 VSS AJ19 VSS AK19 NC AL19 NC AM19 VSS AJ20 VSS AK20 NC AL20 NC AM20 VSS AJ21 VSS AK21 VSS AL21 VSS AM21 VSS AJ22 VSS AK22 NC AL22 NC AM22 VSS AJ23 VSS AK23 NC AL23 NC AM23 VSS AJ24 VSS AK24 VSS AL24 VSS AM24 VSS AJ25 VSS AK25 NC AL25 NC AM25 VSS AJ26 VSS AK26 NC AL26 NC AM26 VSS AJ27 VSS AK27 VSS AL27 VSS AM27 VSS AJ28 VSS AK28 NC AL28 NC AM28 VSS AJ29 VSS AK29 NC AL29 NC AM29 VSS AJ30 VSS AK30 VSS AL30 VSS AM30 VSS AJ31 VSS AK31 GPIO_08 1 AL31 GPIO_07 AJ32 VSS AK32 GPIO_15 1 AL32 VDDIO AJ33 VSS AK33 GPIO_14 1 AL33 GPIO_10 AJ34 VSS AK34 VDDIO AL34 GPIO_12 1 Alt AM31 GPIO_00 AM32 GPIO_05 1 1 AM33 GPIO_11 1 1 AM34 GPIO_13 1 Table 18 PES48H12 1156-pin Signal Pin-Out (Part 8 of 9) 29 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Pin Function Alt Pin Function Alt Pin Function Alt Pin Function AN1 VSS AN18 VSS AP1 VSS AP18 VSS AN2 VDDIO AN19 NC AP2 VSS AP19 NC AN3 VSS AN20 NC AP3 RSTHALT AP20 NC AN4 SWMODE_0 AN21 VSS AP4 SWMODE_1 AP21 VSS AN5 SWMODE_2 AN22 NC AP5 VDDIO AP22 NC AN6 VSS AN23 NC AP6 VSS AP23 NC AN7 PE6TN00 AN24 VSS AP7 PE6TP00 AP24 VSS AN8 PE6TN01 AN25 NC AP8 PE6TP01 AP25 NC AN9 VSS AN26 NC AP9 VSS AP26 NC AN10 PE6TN02 AN27 VSS AP10 PE6TP02 AP27 VSS AN11 PE6TN03 AN28 NC AP11 PE6TP03 AP28 NC AN12 VSS AN29 NC AP12 VSS AP29 NC AN13 PE7TN00 AN30 VSS AP13 PE7TP00 AP30 VSS AN14 PE7TN01 AN31 GPIO_01 AP14 PE7TP01 AP31 VDDIO AN15 VSS AN32 GPIO_02 AP15 VSS AP32 GPIO_03 AN16 PE7TN02 AN33 VDDIO AP16 PE7TP02 AP33 VSS AN17 PE7TN03 AN34 VSS AP17 PE7TP03 AP34 VSS Alt Table 18 PES48H12 1156-pin Signal Pin-Out (Part 9 of 9) Alternate Signal Functions Pin GPIO Alternate Pin GPIO Alternate AM32 GPIO_05 GPEN AK32 GPIO_15 P10RSTN AE25 GPIO_06 P1RSTN C4 GPIO_16 P11RSTN AL31 GPIO_07 P2RSTN C3 GPIO_21 IOEXPINTN0 AK31 GPIO_08 P3RSTN K10 GPIO_22 IOEXPINTN1 AF26 GPIO_09 P4RSTN D4 GPIO_23 IOEXPINTN2 AL33 GPIO_10 P5RSTN E4 GPIO_24 IOEXPINTN3 AM33 GPIO_11 P6RSTN J9 GPIO_25 IOEXPINTN4 AL34 GPIO_12 P7RSTN D2 GPIO_26 IOEXPINTN5 AM34 GPIO_13 P8RSTN E3 GPIO_31 IOEXPINTN10 AK33 GPIO_14 P9RSTN Table 19 PES48H12 Alternate Signal Functions 30 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Power Pins VDDCore VDDCore VDDIO VDDPE VDDPE VDDAPE VTTPE N13 V19 A4 J14 V11 H15 H13 N14 V21 A30 J21 V12 H20 H22 N15 V22 B2 L13 V23 K15 J17 N17 W13 B33 L14 V24 K20 J18 N19 W14 D3 L15 Y11 R8 K13 N20 W16 D31 L17 Y12 R10 K17 N21 W18 D34 L18 Y23 R25 K18 N22 W20 E1 L20 Y24 R27 K22 P13 Y13 H9 L21 AA9 Y8 N8 P15 Y15 H27 L22 AA11 Y10 N10 P17 Y17 J26 M13 AA24 Y25 N25 P19 Y19 K9 M15 AA26 Y27 N27 P21 Y21 AE9 M17 AB11 AE15 U9 P22 Y22 AE26 M18 AB12 AE20 U10 R13 AA13 AF9 M20 AB23 AG15 U25 R14 AA14 AF10 M22 AB24 AG20 U26 R16 AA16 AG8 N11 AC13 V9 R18 AA18 AG9 N12 AC15 V10 R20 AA20 AG26 N23 AC17 V25 R22 AA22 AK34 N24 AC18 V26 T15 AB13 AL1 P9 AC20 AB8 T17 AB14 AL4 P11 AC22 AB10 T19 AB15 AL32 P24 AD13 AB25 T21 AB16 AN2 P26 AD14 AB27 T22 AB18 AN33 R11 AD15 AE13 U13 AB20 AP5 R12 AD17 AE17 U14 AB21 AP31 R23 AD18 AE18 U16 AB22 R24 AD20 AE22 U18 U11 AD21 AF17 U20 U12 AD22 AF18 V15 U23 AF14 AG13 V17 U24 AF21 AG22 Table 20 PES48H12 Power Pins 31 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Ground Pins VSS VSS VSS VSS VSS VSS VSS VSS A1 C16 E33 G8 H29 K16 M5 P12 A2 C17 E34 G9 H30 K19 M6 P14 A5 C18 F1 G10 H31 K21 M7 P16 A8 C19 F2 G11 H32 K23 M8 P18 A11 C20 F3 G12 H33 K24 M9 P20 A14 C21 F4 G13 H34 K27 M10 P23 A17 C22 F5 G14 J1 K28 M11 P25 A20 C23 F6 G15 J2 K29 M12 P27 A23 C24 F7 G16 J3 K32 M14 P28 A26 C25 F8 G19 J4 L3 M16 P29 A29 C26 F9 G20 J5 L6 M19 P30 A33 C27 F10 G21 J6 L7 M21 P31 A34 C28 F11 G22 J7 L8 M23 P32 B1 C29 F12 G23 J8 L9 M24 P33 B5 D5 F13 G24 J10 L10 M25 P34 B8 D8 F14 G25 J11 L11 M26 R1 B11 D11 F15 G26 J12 L12 M27 R2 B14 D14 F16 G28 J13 L16 M28 R3 B17 D17 F17 G29 J15 L19 M29 R4 B20 D20 F18 G32 J16 L23 M32 R5 B23 D23 F19 H3 J19 L24 N3 R6 B26 D26 F20 H6 J20 L25 N6 R7 B29 D29 F21 H7 J22 L26 N7 R9 B34 E5 F22 H10 J23 L27 N9 R15 C5 E8 F23 H11 J24 L28 N16 R17 C6 E11 F24 H12 J28 L29 N18 R19 C7 E14 F25 H14 J29 L30 N26 R21 C8 E17 F26 H16 J32 L31 N28 R26 C9 E20 F27 H17 K3 L32 N29 R28 C10 E23 F28 H18 K6 L33 N32 R29 C11 E26 F29 H19 K7 L34 P3 R32 C12 E29 F32 H21 K8 M1 P6 T3 C13 E30 G3 H23 K11 M2 P7 T6 C14 E31 G6 H24 K12 M3 P8 T7 C15 E32 G7 H25 K14 M4 P10 T8 Table 21 PES48H12 Ground Pins (Part 1 of 3) 32 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet VSS VSS VSS VSS VSS VSS VSS VSS T9 V6 Y18 AB28 AD11 AF16 AH6 AJ20 T10 V8 Y20 AB29 AD12 AF19 AH7 AJ21 T11 V13 Y26 AB32 AD16 AF20 AH9 AJ22 T12 V14 Y28 AC3 AD19 AF22 AH10 AJ23 T13 V16 Y29 AC6 AD23 AF23 AH11 AJ24 T14 V18 Y30 AC7 AD24 AF24 AH12 AJ25 T16 V20 Y31 AC8 AD25 AF25 AH13 AJ26 T18 V27 Y32 AC9 AD26 AF27 AH14 AJ27 T20 V29 Y33 AC10 AD27 AF28 AH15 AJ28 T23 V32 Y34 AC11 AD28 AF29 AH16 AJ29 T24 W3 AA1 AC12 AD29 AF30 AH19 AJ30 T25 W6 AA2 AC14 AD32 AF31 AH20 AJ31 T26 W7 AA3 AC16 AE3 AF32 AH21 AJ32 T27 W8 AA4 AC19 AE6 AF33 AH22 AJ33 T28 W9 AA5 AC21 AE7 AF34 AH23 AJ34 T29 W10 AA6 AC23 AE8 AG1 AH24 AK1 T32 W11 AA7 AC24 AE10 AG2 AH25 AK2 U3 W12 AA8 AC25 AE11 AG3 AH26 AK3 U6 W15 AA10 AC26 AE12 AG4 AH27 AK4 U8 W17 AA12 AC27 AE14 AG5 AH28 AK5 U15 W19 AA15 AC28 AE16 AG6 AH29 AK6 U17 W21 AA17 AC29 AE19 AG10 AH32 AK9 U19 W22 AA19 AC30 AE21 AG11 AJ3 AK12 U21 W23 AA21 AC31 AE23 AG12 AJ6 AK15 U22 W24 AA23 AC32 AE24 AG14 AJ7 AK18 U27 W25 AA25 AC33 AE27 AG16 AJ8 AK21 U29 W26 AA27 AC34 AE28 AG17 AJ9 AK24 U30 W27 AA28 AD1 AE29 AG18 AJ10 AK27 U31 W28 AA29 AD2 AE32 AG19 AJ11 AK30 U32 W29 AA32 AD3 AF3 AG21 AJ12 AL6 U33 W32 AB3 AD4 AF6 AG23 AJ13 AL9 U34 Y3 AB6 AD5 AF7 AG24 AJ14 AL12 V1 Y6 AB7 AD6 AF8 AG25 AJ15 AL15 V2 Y7 AB9 AD7 AF11 AG28 AJ16 AL18 V3 Y9 AB17 AD8 AF12 AG29 AJ17 AL21 V4 Y14 AB19 AD9 AF13 AG32 AJ18 AL24 V5 Y16 AB26 AD10 AF15 AH3 AJ19 AL27 Table 21 PES48H12 Ground Pins (Part 2 of 3) 33 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet VSS VSS VSS VSS VSS VSS VSS VSS AL30 AM11 AM18 AM25 AN3 AN24 AP9 AP30 AM3 AM12 AM19 AM26 AN6 AN27 AP12 AP33 AM6 AM13 AM20 AM27 AN9 AN30 AP15 AP34 AM7 AM14 AM21 AM28 AN12 AN34 AP18 AM8 AM15 AM22 AM29 AN15 AP1 AP21 AM9 AM16 AM23 AM30 AN18 AP2 AP24 AM10 AM17 AM24 AN1 AN21 AP6 AP27 Table 21 PES48H12 Ground Pins (Part 3 of 3) No Connect Pins NC NC NC NC NC NC NC NC V30 AA31 AD33 AG34 AK25 AL26 AN28 AP29 V31 AA33 AD34 AH30 AK26 AL28 AN29 V33 AA34 AE30 AH31 AK28 AL29 AP19 V34 AB30 AE31 AH33 AK29 AN19 AP20 W30 AB31 AE33 AH34 AL19 AN20 AP22 W31 AB33 AE34 AK19 AL20 AN22 AP23 W33 AB34 AG30 AK20 AL22 AN23 AP25 W34 AD30 AG31 AK22 AL23 AN25 AP26 AA30 AD31 AG33 AK23 AL25 AN26 AP28 Table 22 PES48H12 No Connect Pins Signals Listed Alphabetically Signal Name I/O Type Location Signal Category CCLKDS I K25 System CCLKUS I AG7 Table 23 89PES48H12 Alphabetical Signal List (Part 1 of 10) 34 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Signal Name I/O Type Location Signal Category GPIO_00 I/O AM31 General Purpose I/O GPIO_01 I/O AN31 GPIO_02 I/O AN32 GPIO_03 I/O AP32 GPIO_04 I/O AG27 GPIO_05 I/O AM32 GPIO_06 I/O AE25 GPIO_07 I/O AL31 GPIO_08 I/O AK31 GPIO_09 I/O AF26 GPIO_10 I/O AL33 GPIO_11 I/O AM33 GPIO_12 I/O AL34 GPIO_13 I/O AM34 GPIO_14 I/O AK33 GPIO_15 I/O AK32 GPIO_16 I/O C4 GPIO_17 I/O B4 GPIO_18 I/O B3 GPIO_19 I/O A3 GPIO_20 I/O H8 GPIO_21 I/O C3 GPIO_22 I/O K10 GPIO_23 I/O D4 GPIO_24 I/O E4 GPIO_25 I/O J9 GPIO_26 I/O D2 GPIO_27 I/O C2 GPIO_28 I/O D1 GPIO_29 I/O C1 GPIO_30 I/O E2 GPIO_31 I/O E3 General Purpose I/O (cont.) Table 23 89PES48H12 Alphabetical Signal List (Part 2 of 10) 35 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Signal Name I/O Type Location Signal Category JTAG_TCK I K26 Test JTAG_TDI I C31 JTAG_TDO O J25 JTAG_TMS I D30 JTAG_TRST_N I C32 MSMBADDR_1 I A31 MSMBADDR_2 I B31 MSMBADDR_3 I B30 MSMBADDR_4 I C30 MSMBCLK I/O G27 MSMBDAT I/O H26 I A32 MSMBSMODE NC SMBus Interface System See Table 22 for a listing of no connect pins. P01MERGEN I AL2 P23MERGEN I AM1 P45MERGEN I AL3 P67MERGEN I AM2 P89MERGEN I AL5 P1011MERGEN I AM4 System Table 23 89PES48H12 Alphabetical Signal List (Part 3 of 10) 36 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Signal Name I/O Type Location Signal Category PE0RN00 I T30 PCI Express Interface PE0RN01 I R30 PE0RN02 I N30 PE0RN03 I M30 PE0RP00 I T31 PE0RP01 I R31 PE0RP02 I N31 PE0RP03 I M31 PE0TN00 O T33 PE0TN01 O R33 PE0TN02 O N33 PE0TN03 O M33 PE0TP00 O T34 PE0TP01 O R34 PE0TP02 O N34 PE0TP03 O M34 PE1RN00 I K30 PE1RN01 I J30 PE1RN02 I G30 PE1RN03 I F30 PE1RP00 I K31 PE1RP01 I J31 PE1RP02 I G31 PE1RP03 I F31 PE1TN00 O K33 PE1TN01 O J33 PE1TN02 O G33 PE1TN03 O F33 PE1TP00 O K34 Table 23 89PES48H12 Alphabetical Signal List (Part 4 of 10) 37 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Signal Name I/O Type Location Signal Category PE1TP01 O J34 PCI Express Interface (cont.) PE1TP02 O G34 PE1TP03 O F34 PE2RN00 I E28 PE2RN01 I E27 PE2RN02 I E25 PE2RN03 I E24 PE2RP00 I D28 PE2RP01 I D27 PE2RP02 I D25 PE2RP03 I D24 PE2TN00 O B28 PE2TN01 O B27 PE2TN02 O B25 PE2TN03 O B24 PE2TP00 O A28 PE2TP01 O A27 PE2TP02 O A25 PE2TP03 O A24 PE3RN00 I E22 PE3RN01 I E21 PE3RN02 I E19 PE3RN03 I E18 PE3RP00 I D22 PE3RP01 I D21 PE3RP02 I D19 PE3RP03 I D18 PE3TN00 O B22 PE3TN01 O B21 PE3TN02 O B19 PE3TN03 O B18 PE3TP00 O A22 PE3TP01 O A21 PE3TP02 O A19 PE3TP03 O A18 PE4RN00 I W5 Table 23 89PES48H12 Alphabetical Signal List (Part 5 of 10) 38 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Signal Name I/O Type Location Signal Category PE4RN01 I Y5 PCI Express Interface (cont.) PE4RN02 I AB5 PE4RN03 I AC5 PE4RP00 I W4 PE4RP01 I Y4 PE4RP02 I AB4 PE4RP03 I AC4 PE4TN00 O W2 PE4TN01 O Y2 PE4TN02 O AB2 PE4TN03 O AC2 PE4TP00 O W1 PE4TP01 O Y1 PE4TP02 O AB1 PE4TP03 O AC1 PE5RN00 I AE5 PE5RN01 I AF5 PE5RN02 I AH5 PE5RN03 I AJ5 PE5RP00 I AE4 PE5RP01 I AF4 PE5RP02 I AH4 PE5RP03 I AJ4 PE5TN00 O AE2 PE5TN01 O AF2 PE5TN02 O AH2 PE5TN03 O AJ2 PE5TP00 O AE1 PE5TP01 O AF1 PE5TP02 O AH1 PE5TP03 O AJ1 PE6RN00 I AK7 PE6RN01 I AK8 PE6RN02 I AK10 PE6RN03 I AK11 PE6RP00 I AL7 Table 23 89PES48H12 Alphabetical Signal List (Part 6 of 10) 39 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Signal Name I/O Type Location Signal Category PE6RP01 I AL8 PCI Express Interface (cont.) PE6RP02 I AL10 PE6RP03 I AL11 PE6TN00 O AN7 PE6TN01 O AN8 PE6TN02 O AN10 PE6TN03 O AN11 PE6TP00 O AP7 PE6TP01 O AP8 PE6TP02 O AP10 PE6TP03 O AP11 PE7RN00 I AK13 PE7RN01 I AK14 PE7RN02 I AK16 PE7RN03 I AK17 PE7RP00 I AL13 PE7RP01 I AL14 PE7RP02 I AL16 PE7RP03 I AL17 PE7TN00 O AN13 PE7TN01 O AN14 PE7TN02 O AN16 PE7TN03 O AN17 PE7TP00 O AP13 PE7TP01 O AP14 PE7TP02 O AP16 PE7TP03 O AP17 PE8RN00 I E16 PE8RN01 I E15 PE8RN02 I E13 PE8RN03 I E12 PE8RP00 I D16 PE8RP01 I D15 PE8RP02 I D13 PE8RP03 I D12 PE8TN00 O B16 Table 23 89PES48H12 Alphabetical Signal List (Part 7 of 10) 40 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Signal Name I/O Type Location Signal Category PE8TN01 O B15 PCI Express Interface (cont.) PE8TN02 O B13 PE8TN03 O B12 PE8TP00 O A16 PE8TP01 O A15 PE8TP02 O A13 PE8TP03 O A12 PE9RN00 I E10 PE9RN01 I E9 PE9RN02 I E7 PE9RN03 I E6 PE9RP00 I D10 PE9RP01 I D9 PE9RP02 I D7 PE9RP03 I D6 PE9TN00 O B10 PE9TN01 O B9 PE9TN02 O B7 PE9TN03 O B6 PE9TP00 O A10 PE9TP01 O A9 PE9TP02 O A7 PE9TP03 O A6 PE10RN00 I G5 PE10RN01 I H5 PE10RN02 I K5 PE10RN03 I L5 PE10RP00 I G4 PE10RP01 I H4 PE10RP02 I K4 PE10RP03 I L4 PE10TN00 O G2 PE10TN01 O H2 PE10TN02 O K2 PE10TN03 O L2 PE10TP00 O G1 Table 23 89PES48H12 Alphabetical Signal List (Part 8 of 10) 41 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Signal Name I/O Type Location Signal Category PE10TP01 O H1 PCI Express Interface (cont.) PE10TP02 O K1 PE10TP03 O L1 PE11RN00 I N5 PE11RN01 I P5 PE11RN02 I T5 PE11RN03 I U5 PE11RP00 I N4 PE11RP01 I P4 PE11RP02 I T4 PE11RP03 I U4 PE11TN00 O N2 PE11TN01 O P2 PE11TN02 O T2 PE11TN03 O U2 PE11TP00 O N1 PE11TP01 O P1 PE11TP02 O T1 PE11TP03 O U1 PEREFCLKN0 I V28 PEREFCLKN1 I G18 PEREFCLKN2 I U7 PEREFCLKN3 I AH17 PEREFCLKP0 I U28 PEREFCLKP1 I G17 PEREFCLKP2 I V7 PEREFCLKP3 I AH18 PERSTN I B32 System REFCLKM I AH8 PCI Express Interface RSTHALT I AP3 System SSMBADDR_1 I C34 SMBus Interface SSMBADDR_2 I C33 SSMBADDR_3 I D33 SSMBADDR_5 I D32 SSMBCLK I/0 H28 SSMBDAT I/O J27 Table 23 89PES48H12 Alphabetical Signal List (Part 9 of 10) 42 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Signal Name I/O Type Location Signal Category SWMODE_0 I AN4 System SWMODE_1 I AP4 SWMODE_2 I AN5 SWMODE_3 I AM5 VDDCORE, VDDAPE, VDDIO, VDDPE, VTTPE See Table 20 for a listing of power pins. VSS See Table 21 for a listing of ground pins. Table 23 89PES48H12 Alphabetical Signal List (Part 10 of 10) 43 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet PES48H12 Pinout — Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 A A B B C C D D E E F F G G X H J X K X X X X X H J X K L L M M X X N X X N P P R R T T XX XX U V XX XX XX X X XX XX W Y X X X V W Y X X X X AA X X X X AB AA AB U X AC AC X X X X AD X X X X AE AD X AE AF X X X X X X AG XX X X XX XX X AH AJ X X XX XX XX X X XX XX XX AK AL AM 1 2 3 4 5 6 7 8 AG AH AJ AK AL AM X X XX XX XX X X XX XX XX AN AP AF AN AP 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VDDCore (Power) VDDAPE (Power) VDDI/O (Power) VDDPE (Power) VTTPE (Power) Signals Vss (Ground) X 44 of 48 No connect October 7, 2008 IDT 89HPES48H12 Data Sheet PES48H12 Package Drawing — 1156-Pin BL1156/BR1156 45 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet PES48H12 Package Drawing — Page Two 46 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Revision History July 19, 2007: Initial publication of data sheet. November 14, 2007: Added new parameter, Termination Resistor, to Table 9, Input Clock Requirements. April 16, 2008: In Table 16, Thermal Specifications, revised values for θJA, θJB, and θJC. October 7, 2008: In Table 5, revised description of PxxMERGEN pins. 47 of 48 October 7, 2008 IDT 89HPES48H12 Data Sheet Ordering Information NN A AAA NNAN AA Product Family Operating Voltage Device Family Product Detail Device Revision AA Legend A = Alpha Character N = Numeric Character A Package Temp Range Blank Commercial Temperature (0°C to +70°C Ambient) I Industrial Temperature (-40° C to +85° C Ambient) BL 1156-ball FCBGA BR 1156-ball FCBGA, RoHS ZA ZA revision 48H12 48-lane, 12-port PES PCI Express Switch H 1.0V +/- 0.1V Core Voltage 89 Serial Switching Product Valid Combinations 89HPES48H12ZABL 1156-ball FCBGA package, Commercial Temperature 89HPES48H12ZABR 1156-ball RoHS FCBGA package, Commercial Temperature 89HPES48H12ZABLI 1156-ball FCBGA package, Industrial Temperature 89HPES48H12ZABRI 1156-ball RoHS FCBGA package, Industrial Temperature ® CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 48 of 48 for Tech Support: email: ssdhelp@idt.com phone: 408-284-8208 October 7, 2008
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