8N4S271LC-1118CDI

IDT8N4S271 LVDS Frequency-Programmable Crystal Oscillator DATA SHEET General Description Features The IDT8N4S271 is a Factory Frequency-Programmable Crystal Oscillator with very flexible frequency programming capabilities. The device uses IDT’s fourth generation FemtoClock® NG technology for an optimum of high clock frequency and low phase noise performance. The device accepts 2.5V or 3.3V supply and is packaged in a small, lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm package. • • Fourth generation FemtoClock® NG technology • • • Frequency programming resolution is 218Hz and better The device can be factory programmed to any in the range from 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz and supports a very high degree of frequency precision of 218Hz or better. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. • RMS phase jitter @ 231.25MHz (12kHz - 20MHz):  0.48ps (typical), integer PLL feedback configuration • RMS phase jitter @ 231.25MHz (1kHz - 40MHz):  0.50ps (typical), integer PLL feedback configuration • • • 2.5V or 3.3V supply Factory-programmable clock output frequency from 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz One 2.5V, 3.3V LVDS clock output Output enable control (positive polarity), LVCMOS/LVTTL compatible -40°C to 85°C ambient operating temperature Available in a lead-free (RoHS 6) 6-pin ceramic package Block Diagram Pin Assignment ÷P OSC PFD & LPF DNU 1 FemtoClock® NG VCO 1950-2600MHz Q nQ ÷N OE 2 GND 3 6 VDD 5 nQ 4 Q fXTAL 2 ÷MINT, MFRAC 7 25 IDT8N4S271 6-lead ceramic 5mm x 7mm x 1.55mm package body CD Package Top View Configuration Register (ROM) OE Pullup IDT8N4S271CCD REVISION A NOVEMBER 29, 2012 1 ©2012 Integrated Device Technology, Inc. IDT8N4S271 Data Sheet LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR Pin Description and Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1 DNU 2 OE Input 3 GND Power Power supply ground. 4, 5 Q, nQ Output Differential clock output pair. LVDS interface levels. 6 VDD Power Power supply pin. Do not use (factory use only). Pullup Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface levels. NOTE: Pullup refers to an internal input resistor. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 5.5 pF RPULLUP Input Pullup Resistor 50 k Function Tables Table 3A. OE Configuration Input OE Output Enable 0 Outputs Q, nQ are in high-impedance state 1 (default) Outputs are enabled NOTE: OE is an asynchronous control. Table 3B. Output Frequency Range 15.476MHz to 866.67MHz 975MHz to 1,300MHz NOTE: Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of 218Hz or better. IDT8N4S271CCD REVISION A NOVEMBER 29, 2012 2 ©2012 Integrated Device Technology, Inc. IDT8N4S271 Data Sheet LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR Principles of Operation 18-bit fractional portion (MFRAC) and provides the means for high-resolution frequency generation. The output frequency fOUT is calculated by: The block diagram consists of the internal 3rd overtone crystal and oscillator which provide the reference clock fXTAL of either 114.285MHz or 100MHz. The PLL includes the FemtoClock NG VCO along with the Pre-divider (P), the feedback divider (M) and the post divider (N). The P, M, and N dividers determine the output frequency based on the fXTAL reference. The feedback divider is fractional supporting a huge number of output frequencies. The configuration of the feedback divider to integer-only values results in an improved output phase noise characteristics at the expense of the range of output frequencies. Internal registers are used to hold one factory pre-set P, M, and N configuration setting. The P, M, and N frequency configuration supports an output frequency range from 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz. 1 + 0.5f OUT = f XTAL  ------------  MINT + MFRAC -----------------------------------PN 18 2 Frequency Configuration An order code is assigned to each frequency configuration programmed by the factory (default frequencies). For more information on the available default frequencies and order codes, please see the Ordering Information section in this document. For available order codes, see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document. The devices use the fractional feedback divider with a delta-sigma modulator for noise shaping and robust frequency synthesis capability. The relatively high reference frequency minimizes phase noise generated by frequency multiplication and allows more efficient shaping of noise by the delta-sigma modulator. For more information on programming capabilities of the device for custom frequency and pull-range configurations, see the FemtoClock NG Ceramic 5x7 Module Programming Guide. The output frequency is determined by the 2-bit pre-divider (P), the feedback divider (M) and the 7-bit post divider (N). The feedback divider (M) consists of both a 7-bit integer portion (MINT) and an IDT8N4S271CCD REVISION A NOVEMBER 29, 2012 3 ©2012 Integrated Device Technology, Inc. IDT8N4S271 Data Sheet LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 3.63V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuous Current Surge Current  10mA 15mA Package Thermal Impedance, JA 49.4C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions VDD Power Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 134 160 mA Minimum Typical Maximum Units 2.375 2.5 2.625 V 129 155 mA Table 4B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions VDD Power Supply Voltage IDD Power Supply Current Table 4C. LVCMOS/LVTTL DC Characteristic, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current OE VDD = VIN = 3.465V or 2.625V IIL Input Low Current OE VDD = 3.465V or 2.625V, VIN = 0V IDT8N4S271CCD OE OE REVISION A NOVEMBER 29, 2012 Test Conditions Minimum VDD = 3.3V Maximum Units 2 VDD + 0.3 V VDD = 2.5V 1.7 VDD + 0.3 V VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V 10 µA 4 -150 Typical µA ©2012 Integrated Device Technology, Inc. IDT8N4S271 Data Sheet LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR Table 4D. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 247 370 454 mV 50 mV 1.375 V 50 mV 1.125 1.22 Table 4E. LVDS DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 247 360 454 mV 50 mV 1.375 V 50 mV 1.125 1.21 AC Electrical Characteristics Table 5. AC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency fI Initial Accuracy fS fA Test Conditions fT Total Stability tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 tjit(per) RMS Period Jitter; NOTE 1 IDT8N4S271CCD Typical Maximum Units 15.476 866.67 MHz 975 1,300 MHz Measured @ 25°C ±10 ppm Option code = A or B ±100 ppm Option code = E or F ±50 ppm Option code = K or L ±20 ppm Frequency drift over 10 year life ±3 ppm Frequency drift over 15 year life ±5 ppm Option code A, B (10 year life) ±113 ppm Option code E, F (10 year life) ±63 ppm Option code K, L (10 year life) ±33 ppm 20 ps 5 ps Temperature Stability Aging Minimum REVISION A NOVEMBER 29, 2012 3 5 ©2012 Integrated Device Technology, Inc. IDT8N4S271 Data Sheet LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR Table 5 (continued). AC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter Typical Maximum Units 17MHz  fOUT 1300MHz, Integration range: 12kHz-20MHz 0.497 0.882 ps 500MHz fOUT 1300MHz, Integration range: 12kHz-20MHz 0.232 0.322 ps 125MHz fOUT 500MHz, Integration range: 12kHz-20MHz 0.250 0.450 ps 17MHz fOUT 125MHz, Integration range: 12kHz-20MHz 0.275 0.405 ps fOUT 156.25MHz, Integration range: 12kHz-20MHz 0.242 0.311 ps fOUT 231.25MHz, Integration range: 12kHz-20MHz 0.476 0.680 ps fOUT 156.25MHz, Integration range: 12kHz-20MHz 0.275 0.359 ps fOUT 231.25MHz, Integration range: 12kHz-20MHz 0.504 0.700 ps RMS Phase Jitter (Random) Fractional PLL feedback and fXTAL=114.285MHz (0xxx order codes), NOTES 2, 3, 6 17MHz fOUT 1300MHz, Integration range: 12kHz-20MHz 0.474 0.986 ps N(100) Single-side Band Phase Noise,  100Hz from Carrier fOUT 231.25MHz -88 dBc/Hz N(1k) Single-side Band Phase Noise,  1kHz from Carrier fOUT 231.25MHz -110 dBc/Hz N(10k) Single-side Band Phase Noise,  10kHz from Carrier fOUT 231.25MHz -123 dBc/Hz N(100k) Single-side Band Phase Noise,  100kHz from Carrier fOUT 231.25MHz -125 dBc/Hz N(1M) Single-side Band Phase Noise,  1MHz from Carrier fOUT 231.25MHz -137 dBc/Hz N(10M) Single-side band phase noise,  10MHz from Carrier fOUT 231.25MHz -141 dBc/Hz tR / tF Output Rise/Fall Time odc Output Duty Cycle tSTARTUP Device Startup Time After Power Up RMS Phase Jitter (Random); Fractional PLL feedback and fXTAL=100.000MHz (2xxx order  codes), NOTES 2, 3, 4 tjit(Ø) RMS Phase Jitter (Random); Integer PLL feedback and fXTAL=100.00MHz  (1xxx order codes),  NOTES 2, 3, 5 Test Conditions 20% to 80% Minimum 50 450 ps 47 53 % 20 ms NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing. NOTE 1: This parameter is defined in accordance with JEDEC standard 65. NOTE 2: Refer to the phase noise plot. NOTE 3: See the FemtoClock NG Ceramic 5x7 Modules Programming guide for more information on PLL feedback modes and the optimum configuration for phase noise. Integer PLL feedback is the default operation for the dddd = 1xxx order codes. NOTE 4: Applies to output frequencies: 81MHz, 122.88MHz, 231.25MHz, 622.08MHz, 866.67MHz and 1124MHz. NOTE 5: Applies to output frequencies: 75MHz, 100MHz, 106.25MHz, 125MHz, 156.25MHz, 425MHz, 500MHz, 625MHz, 975MHz  and 1300MHz. NOTE 6: Applies to output frequencies: 15.4762MHz, 38.88MHz, 114.285MHz, 496MHz, 669.32MHz and 658MHz. IDT8N4S271CCD REVISION A NOVEMBER 29, 2012 6 ©2012 Integrated Device Technology, Inc. IDT8N4S271 Data Sheet LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR Noise Power dBc/Hz Typical Phase Noise at 231.25MHz (12kHz - 20MHz) Offset Frequency (Hz) IDT8N4S271CCD REVISION A NOVEMBER 29, 2012 7 ©2012 Integrated Device Technology, Inc. IDT8N4S271 Data Sheet LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR Parameter Measurement Information SCOPE SCOPE Q VDD 2.5V±5% POWER SUPPLY + Float GND – 3.3V±5% POWER SUPPLY + Float GND – Q VDD nQ nQ 3.3V LVDS Output Load Test Circuit 2.5V LVDS Output Load Test Circuit Phase Noise Plot Noise Power VOH VREF VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Offset Frequency f1 f2 RMS Phase Jitter = 1 * Area Under Curve Defined by the Offset Frequency Markers 2* *ƒ Histogram Reference Point Mean Period (Trigger Edge) (First edge after trigger) RMS Period Jitter RMS Phase Jitter nQ nQ Q Q t PW ➤ tcycle n ➤ t tcycle n+1 ➤ ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles odc = PERIOD t PW x 100% t PERIOD Output Duty Cycle/Pulse Width/Period Cycle-to-Cycle Jitter IDT8N4S271CCD REVISION A NOVEMBER 29, 2012 8 ©2012 Integrated Device Technology, Inc. IDT8N4S271 Data Sheet LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR Parameter Measurement Information, continued VDD out nQ 80% 80% VOD Q DC Input LVDS 20% 20% tR out tF VOS/Δ VOS ä Output Rise/Fall Time Offset Voltage Setup VDD out DC Input LVDS 100 out Differential Output Voltage Setup IDT8N4S271CCD REVISION A NOVEMBER 29, 2012 9 ©2012 Integrated Device Technology, Inc. IDT8N4S271 Data Sheet LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR Applications Information LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The LVDS Driver standard termination schematic as shown in Figure 1A can be used with either type of output structure. Figure 1B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output. ZO  Z T ZT LVDS Receiver Figure 1A. Standard Termination LVDS Driver ZO  ZT C ZT 2 LVDS ZT Receiver 2 Figure 1B. Optional Termination Figure 1. Typical LVDS Driver Termination IDT8N4S271CCD REVISION A NOVEMBER 29, 2012 10 ©2012 Integrated Device Technology, Inc. IDT8N4S271 Data Sheet LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR Schematic Layout Figure 2 shows an example IDT8N4S271 application schematic. The schematic example focuses on functional connections and is intended as an example only and may not represent the exact user configuration. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. For example OE can be configured from an FPGA instead of set with pull up and pull down resistors as shown. capacitor on the VDD pin must be placed on the device side with direct return to the ground plane though vias. The remaining filter components can be on the opposite side of the PCB. Power supply filter component recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise, so to achieve optimum jitter performance isolation of the VDD pin from power supply is required. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1µF Logic Control Input Examples VDD Set Logic Input to '1' VD D R U1 1K Set Logic Input to '0' RU 2 Not Ins tall To Logic Input pins To Logic Input pins R D1 N ot Ins ta ll RD 2 1K 3.3V U3 OE 2 3 DNU OE GN D VD D nQ Q 6 5 1 BLM18BB221SN 1 C4 10uF 1 FB1 2 VDD C5 0.1 uF C3 0.1uF Place 0.1uF bypass cap directly adjacent to the VDD pin. Zo = 50 Ohm R1 100 4 + Zo = 50 Ohm - ID T8N 4S27 1C C D LVDS R ec eiv er Figure 2. IDT8N4S271 Schematic Example IDT8N4S271CCD REVISION A NOVEMBER 29, 2012 11 ©2012 Integrated Device Technology, Inc. IDT8N4S271 Data Sheet LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR Power Considerations This section provides information on power dissipation and junction temperature for the IDT8N4S271. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the IDT8N4S271 is the sum of the core power plus the output power dissipated due to the loading. The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 160mA = 554.4mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 49.4°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.554W * 49.4°C/W = 112.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 6 Lead Ceramic 5mm x 7mm Package, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards IDT8N4S271CCD REVISION A NOVEMBER 29, 2012 0 1 2.5 49.4°C/W 44.2°C/W 42.1°C/W 12 ©2012 Integrated Device Technology, Inc. IDT8N4S271 Data Sheet LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR Reliability Information Table 7. JA vs. Air Flow Table for a 6-lead Ceramic 5mm x 7mm Package JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 49.4°C/W 44.2°C/W 42.1°C/W Transistor Count The transistor count for IDT8N4S271 is: 47,511 IDT8N4S271CCD REVISION A NOVEMBER 29, 2012 13 ©2012 Integrated Device Technology, Inc. IDT8N4S271 Data Sheet LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR Package Outline and Package Dimensions IDT8N4S271CCD REVISION A NOVEMBER 29, 2012 14 ©2012 Integrated Device Technology, Inc. IDT8N4S271 Data Sheet LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR Ordering Information for FemtoClock NG Ceramic-Package XO and VCXO Products The programmable VCXO and XO devices support a variety of devices options such as the output type, number of default frequencies, internal crystal frequency, power supply voltage, ambient temperature range and the frequency accuracy. The device options, default frequencies and default VCXO pull range must be specified at the time of order and are programmed by IDT before the shipment. The table below specifies the available order codes, including the device options and default frequency configurations. Example part number: the order code 8N3QV01FG-0001CDI specifies a programmable, quad default-frequency VCXO with a voltage supply of 2.5V, a LVPECL output, a 50ppm crystal frequency accuracy, contains a 114.285MHz internal crystal as frequency source, industrial temperature range, a lead-free (6/6 RoHS) 6-lead ceramic 5mm x 7mm x 1.55mm package and is factory-programmed to the default frequencies of 100MHz, 122.88MHz, 125MHz and 156.25MHz and to the VCXO pull range of min. 100ppm. Other default frequencies and order codes are available from IDT on request. For more information on available default frequencies, see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document. Part/Order Numbers 8N X X XXX X X - dddd XX X X Shipping Package 8: Tape & Reel (no letter): Tray FemtoClock NG Ambient Temperature Range “I”: Industrial: (TA = -40°C to 85°C) (no letter) : (TA = 0°C to 70°C) I/O Identifier 0: LVCMOS 3: LVPECL 4: LVDS Package Code CD: Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm Number of Default Frequencies S: 1: Single D: 2: Dual Q: 4: Quad Part Number Function #pins OE fct. at pin 001 XO 10 OE@2 003 XO 10 OE@1 V01 VCXO 10 OE@2 V03 VCXO 10 OE@1 V75 VCXO 6 OE@2 V76 VCXO 6 nOE@2 V85 VCXO 6 — 085 XO 6 OE@1 270 XO 6 OE@1 271 XO 6 OE@2 272 XO 6 nOE@2 273 XO 6 nOE@1 IDT8N4S271CCD REVISION A NOVEMBER 29, 2012 Default-Frequency and VCXO Pull Range See document FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information. dddd fXTAL (MHz) PLL Feedback Use for 0000 to 0999 114.285 Fractional VCXO, XO Integer XO Fractional XO 1000 to 1999 2000 to 2999 100.000 Last digit = L: configuration pre-programmed and not changeable Die Revision C Option Code (Supply Voltage and Frequency-Stability) A: VCC = 3.3V±5%, ±100ppm B: VCC = 2.5V±5%, ±100ppm E: VCC = 3.3V±5%, ±50ppm F: VCC = 2.5V±5%, ±50ppm K: VCC = 3.3V±5%, ±20ppm L: VCC = 2.5V±5%, ±20ppm 15 ©2012 Integrated Device Technology, Inc. IDT8N4S271 Data Sheet LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR Table 9. Device Marking Marking Industrial Temperature Range (TA = -40°C to 85°C) Commercial Temperature Range (TA = 0°C to 70°C) IDT8N4S271yC- ddddCDI IDT8N4S271yC- ddddCD y = Option Code, dddd=Default-Frequency and VCXO Pull Range IDT8N4S271CCD REVISION A NOVEMBER 29, 2012 16 ©2012 Integrated Device Technology, Inc. IDT8N4S271 Data Sheet LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR Revision History Sheet Rev A Table Page T9 15 16 IDT8N4S271CCD Description of Change Date Ordering Information Table - corrected Die Revision from “G” to “C”. Marking Table - corrected marking. REVISION A NOVEMBER 29, 2012 17 11/29/2012 ©2012 Integrated Device Technology, Inc. IDT8N4S271Data Sheet LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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