Low Skew, ÷2, ÷4, ÷8 Differential-to-LVPECL
Clock Divider
ICS8S73034I
DATA SHEET
General Description
Features
The ICS8S73034I is a high-speed, differential-to- LVPECL clock
divider designed for high-performance telecommunication,
computing and networking applications. High clock frequency
capability and the differential design make the ICS8S73034I an ideal
choice for performance clock distribution networks. The device
frequency-divides the input clock by ÷2, ÷4 and ÷8. Each
frequency-divided clock signal is output at a separate LVPECL
output. The differential input pair can be driven by LVPECL, LVDS,
CML and SSTL signals. Single-ended input signals are supported by
using the integrated bias voltage generator (VBB). The ICS8S73034I
is optimized for 3.3V and 2.5V power supply voltages and the
temperature range of -40 to +85°C. The device is available in
space-saving 16-lead TSSOP and SOIC packages.
•
•
•
•
÷2, ÷4 and ÷8 clock frequency divider
•
VBB bias voltage generator supports single-ended LVPECL clock
input signals
•
•
•
LVCMOS control inputs
•
LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
•
•
Block Diagram
nEN Pulldown
Three differential LVPECL output pairs
One differential PCLK, nPCLK input pair
PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, LVDS, CML
Maximum input frequency: 3.2GHz
Translates any single-ended input signal to 3.3V LVPECL levels
with bias resistors on nPCLK input
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
Q0
nQ0
VCC
Q1
nQ1
VCC
Q2
nQ2
D
Q
LE
PCLK Pulldown
nPCLK Pullup/Pulldown
÷2
Q0
nQ0
R
÷4
Q1
nQ1
R
VBB
÷8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
nEN
nc
PCLK
nPCLK
VBB
MR
VEE
ICS8S73034I
Q2
16-Lead SOIC, 150 Mil
3.9mm x 9.9mm x 1.375mm package body
M Package
Top View
nQ2
R
MR Pulldown
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
ICS8S73034AMI REVISION A JUNE 8, 2011
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©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
Table 1. Pin Descriptions
Number
Name
1, 2
Q0, nQ0
Output
Type
Differential output pair. LVPECL interface levels.
Description
3, 6, 16
VCC
Power
Power supply pins.
4, 5
Q1, nQ1
Output
Differential output pair. LVPECL interface levels.
7, 8
Q2, nQ2
Output
Differential output pair. LVPECL interface levels.
9
VEE
Power
Negative supply pin.
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
10
MR
Input
11
VBB
Output
12
nPCLK
Input
Pullup/
Pulldown
Pulldown
13
PCLK
Input
14
nc
Unused
15
nEN
Input
Pulldown
Bias voltage.
Inverting differential clock input. Defaults to 2/3 * VCC when left open.
LVPECL interface levels.
Non-inverting differential clock input. LVPECL interface levels.
No connect.
Synchronous clock enable. When logic LOW, the clock is enabled and
frequency-divided. When logic HIGH, the clock is disabled and the outputs remain
stopped in the same logic state (hold). LVTTL / LVCMOS interface levels.
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
RPULLDOWN
Input Pulldown Resistor
RPULLUP
Input Pullup Resistor
Minimum
Typical
Maximum
Units
75
kΩ
37.5
kΩ
Function Table
Table 3. Truth Table
Inputs
PCLK
nEN
MR
Function
↓
L
L
Divide
↑
H
L
Hold Q[0:2]
X
X
H
Reset Q[0:2]
↑ = Rising edge transition
↓ = Falling edge transition
X = Don’t care
ICS8S73034AMI REVISION A JUNE 8, 2011
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©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V (LVPECL mode, VEE = 0V)
Inputs, VI (LVPECL mode)
-0.5V to VCC + 0.5V
Outputs, IO
Continuos Current
Surge Current
50mA
100mA
VBB Sink/Source, IBB
±0.5mA
Operating Temperature Range, TA
-40°C to +85°C
Package Thermal Impedance, θJA
16 Lead SOIC, Junction-to-Ambient
16 Lead TSSOP, Junction-to-Ambient
70.2°C/W (0 mps)
100°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VCC
Power Supply Voltage
IEE
Power Supply Current
ICS8S73034AMI REVISION A JUNE 8, 2011
Test Conditions
3
Minimum
Typical
Maximum
Units
2.375
3.3
3.8
V
45
mA
©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
Table 4B. DC Characteristics, VCC = 2.375V to 3.8V, VEE = 0V; TA = -40°C to 85°C
-40°C
Symbol
Parameter
VOH
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
Output High
Voltage; NOTE 1
VCC-1.070
VCC-0.867
VCC-0.635
VCC-1.070
VCC-0.867
VCC-0.635
VCC-1.070
VCC-0.867
VCC-0.635
V
VOL
Output Low Voltage;
NOTE 1
VCC-1.960
VCC-1.780
VCC-1.590
VCC-1.960
VCC-1.780
VCC-1.590
VCC-1.960
VCC-1.780
VCC-1.590
V
VIH
Input High Voltage
(Single-ended)
0.7VCC
VCC + 0.3
0.7VCC
VCC + 0.3
0.7VCC
VCC + 0.3
V
VIL
Input Low Voltage
(Single-ended)
-0.3
0.3VCC
-0.3
0.3VCC
-0.3
0.3VCC
V
VBB
Output Voltage
Reference
VCC - 1.44
VCC - 1.32
VCC - 1.44
VCC - 1.32
VCC - 1.44
VCC - 1.32
V
VPP
Peak-to-Peak Input
Voltage
0.15
1.3
0.15
1.3
0.15
1.3
V
VCMR
Input High Voltage
Common Mode
Range; NOTE 2
1.2
VCC
1.2
VCC
1.2
VCC
V
IIH
Input
PCLK/
High
nPCLK,
Current MR, nEN
150
µA
IIL
PCLK,
Input
MR, nEN
Low
Current nPCLK
0.8
0.8
150
150
0.8
-10
-10
-10
µA
-150
-150
-150
µA
NOTE Input and output parameters vary 1:1 with VCC.
NOTE 1: Outputs terminated with 50Ω to VCC – 2V.
NOTE 2: Common mode voltage is defined as VIH.
ICS8S73034AMI REVISION A JUNE 8, 2011
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©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = 2.375V to 3.8V, VEE = 0V; TA = -40°C to 85°C
-40°C
Symbol
Parameter
fIN
Input Frequency
fOUT
Output
Frequency
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Units
3.2
3.2
3.2
GHz
Q0, nQ0
1.6
1.6
1.6
GHz
Q1, nQ1
800
800
800
MHz
Q2, nQ2
400
400
400
MHz
565
ps
50
ps
500
ps
tPD
Propagation Delay; NOTE 1
270
370
470
310
410
tsk(o)
Output Skew; NOTE 2
tRR
Set/Reset Recovery
tS
Setup Time
nEN
400
400
400
ps
tH
Hold Time
nEN
200
200
200
ps
tR / tF
Output
Rise/Fall Time
20% to 80%
230
ps
odc
Output Duty Cycle
52
%
50
320
80
48
145
510
330
450
50
500
320
210
85
52
48
150
500
320
215
100
52
48
165
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters are measured at fIN ≤ 1.5GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Output skew at coincident rising edges.
ICS8S73034AMI REVISION A JUNE 8, 2011
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©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
Parameter Measurement Information
2V
VCC
VCC
Qx
SCOPE
nPCLK
V
V
Cross Points
PP
CMR
PCLK
LVPECL
nQx
VEE
VEE
-0.375V to -1.8V
LVPECL Output Load AC Test Circuit
Differential Input Level
nPCLK
nQx
PCLK
Qx
nQ[0:2]
nQy
Q[0:2]
Qy
tPD
tsk(o)
Propagation Delay
Output Skew
nQ[0:2]
PCLK
Q[0:2]
nPCLK
t PW
t
nEN
t SET-UP t HOLD
odc =
PERIOD
t PW
x 100%
t PERIOD
Setup and Hold Time
ICS8S73034AMI REVISION A JUNE 8, 2011
Output Duty Cycle
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©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
Parameter Measurement Information, continued
nQ[0:2]
80%
80%
VSW I N G
Q[0:2]
20%
20%
tR
tF
Output Rise/Fall Time
Application Information
Recommendations for Unused Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVPECL Outputs
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
ICS8S73034AMI REVISION A JUNE 8, 2011
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©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VCC/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the VREF in the center of the input voltage swing.
For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and
R2 value should be adjusted to set VREF at 1.25V. The values below
are for when both the single ended swing and VCC are at the same
voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50Ω applications, R3 and R4 can be 100Ω.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some
of the recommended components might not be used, the pads should
be placed in the layout. They can be utilized for debugging purposes.
The datasheet specifications are characterized and guaranteed by
using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS8S73034AMI REVISION A JUNE 8, 2011
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©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
3.3V LVPECL Clock Input Interface
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
The PCLK/nPCLK accepts LVPECL, LVDS, CML and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 2A to 2E show interface examples
for the PCLK/nPCLK input driven by the most common driver types.
3.3V
3.3V
3.3V
3.3V
3.3V
R1
50Ω
Zo = 50Ω
R2
50Ω
Zo = 50Ω
PCLK
R1
100Ω
PCLK
Zo = 50Ω
nPCLK
Zo = 50Ω
nPCLK
LVPECL
Input
CML
LVPECL
Input
CML Built-In Pullup
Figure 2A. PCLK/nPCLK Input Driven by a CML Driver
Figure 2B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
3.3V
3.3V
3.3V
3.3V
R3
125Ω
3.3V
R4
125Ω
3.3V LVPECL
Zo = 50Ω
Zo = 50Ω
C1
Zo = 50Ω
C2
PCLK
PCLK
VBB
nPCLK
Zo = 50Ω
nPCLK
R1
84Ω
R5
R6
100Ω - 200Ω 100Ω - 200Ω
LVPECL
Input
LVPECL
R2
84Ω
Figure 2C. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
R1
50Ω
R2
50Ω
LVPECL
Input
Figure 2D. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
3.3V
3.3V
Zo = 50Ω
C1
PCLK
R5
100Ω
VBB
C2
nPCLK
Zo = 50Ω
LVPECL
Input
LVDS
R1
1k
R2
1k
C3
0.1µF
Figure 2E. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver
ICS8S73034AMI REVISION A JUNE 8, 2011
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©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
2.5V LVPECL Clock Input Interface
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
The PCLK /nPCLK accepts LVPECL, LVDS, CML and other
differential signals. The differential signal must meet the VPP and
VCMR input requirements. Figures 3A to 3E show interface examples
for the PCLK/nPCLK input driven by the most common driver types.
2.5V
2.5V
Zo = 50Ω
2.5V
2.5V
C1
PCLK
R5
100Ω
2.5V LVPECL
Zo = 50Ω
C1
Zo = 50Ω
C2
PCLK
VBB
C2
nPCLK
Zo = 50Ω
R1
1k
VBB
LVPECL
Input
LVDS
R2
1k
nPCLK
R5
R6
100Ω - 200Ω 100Ω - 200Ω
R1
50Ω
LVPECL
Input
R2
50Ω
C3
0.1µF
Figure 3A. PCLK/nPCLK Input Driven by a 2.5V LVDS
Driver
Figure 3B. PCLK/nPCLK Input Driven by a 3.3V
LVPECL Driver with AC Couple
2.5V
2.5V
2.5V
2.5V
R3
125Ω
2.5V
R4
125Ω
2.5V
R1
50Ω
Zo = 50Ω
R2
50Ω
Zo = 50Ω
PCLK
PCLK
Zo = 50Ω
Zo = 50Ω
nPCLK
LVPECL
R1
84Ω
R2
84Ω
nPCLK
LVPECL
Input
CML
Figure 3C. PCLK/nPCLK Input Driven by a 2.5V
LVPECL Driver
LVPECL
Input
Figure 3D. PCLK/nPCLK Input Driven by a CML Driver
2.5V
2.5V
Zo = 50Ω
PCLK
R1
100Ω
Zo = 50Ω
CML Built-In Pullup
nPCLK
LVPECL
Input
Figure 3E. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
ICS8S73034AMI REVISION A JUNE 8, 2011
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©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
R3
125Ω
3.3V
3.3V
Zo = 50Ω
3.3V
R4
125Ω
3.3V
3.3V
+
Zo = 50Ω
+
_
LVPECL
Input
Zo = 50Ω
R1
50Ω
_
LVPECL
R2
50Ω
R1
84Ω
VCC - 2V
RTT =
1
* Zo
((VOH + VOL) / (VCC – 2)) – 2
R2
84Ω
RTT
Figure 4A. 3.3V LVPECL Output Termination
ICS8S73034AMI REVISION A JUNE 8, 2011
Input
Zo = 50Ω
Figure 4B. 3.3V LVPECL Output Termination
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©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
Termination for 2.5V LVPECL Outputs
level. The R3 in Figure 5B can be eliminated and the termination is
shown in Figure 5C.
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50Ω
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground
2.5V
VCC = 2.5V
2.5V
2.5V
VCC = 2.5V
R1
250Ω
50Ω
R3
250Ω
+
50Ω
50Ω
+
–
50Ω
2.5V LVPECL Driver
–
R1
50Ω
2.5V LVPECL Driver
R2
62.5Ω
R2
50Ω
R4
62.5Ω
R3
18Ω
Figure 5A. 2.5V LVPECL Driver Termination Example
Figure 5B. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50Ω
R2
50Ω
Figure 5C. 2.5V LVPECL Driver Termination Example
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ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
Application Schematic Example
Figure 6 shows an example of ICS8S73034I application schematic.
In this example, the device is operated at VCC= 3.3V. The decoupling
capacitor should be located as close as possible to the power pin.
The input is driven by a 3.3V LVPECL driver. For the LVPECL output
drivers, only two terminations examples are shown in this schematic.
More termination approaches are shown in the LVPECL Termination
Application Note.
3.3V
3.3V
R1
133
U1
9
10
11
12
13
14
15
16
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
LVPECL
R9
50
R8
50
VEE
MR
VBB
nCLK
CLK
nc
nEN
VCC
nQ2
Q2
VCC
nQ1
Q1
VCC
nQ0
Q0
8
7
6
5
4
3
2
1
R3
133
Zo = 50 Ohm
+
Zo = 50 Ohm
-
R2
82.5
R4
82.5
ICS873034
R10
50
Zo = 50 Ohm
+
Zo = 50 Ohm
-
(U1-3)
3.3V
C1
0.1uF
(U1-6)
C2
0.1uF
(U1-16)
R5
50
C3
0.1uF
Optional
Y-Termination
R6
50
R7
50
Figure 6. ICS8S73034I Application Schematic Example
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©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8S73034I.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8S73034I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 45mA = 171mW
•
Power (outputs)MAX = 30.3mW/Loaded Output pair
If all outputs are loaded, the total power is 3 * 30.3mW = 90.9mW
Total Power_MAX (3.8V, with all outputs switching) = 171mW + 90.9mW = 261.9mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 100°C/W per Table 6B below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.262W * 100°C/W = 111.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6A. Thermal Resistance θJA for 16 Lead SOIC Forced Convection
θJA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
70.2°C/W
64.7°C/W
61.6°C/W
0
1
2.5
100.0°C/W
94.2°C/W
90.2°C/W
Table 6B. Thermal Resistance θJA for 16 Lead TSSOP Forced Convection
θJA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
ICS8S73034AMI REVISION A JUNE 8, 2011
14
©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 7.
VCC
Q1
VOUT
RL
50Ω
VCC - 2V
Figure 7. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of
VCC – 2V.
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.635V
(VCC_MAX – VOH_MAX) = 0.635V
•
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.59V
(VCC_MAX – VOL_MAX) = 1.59V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.635V)/50Ω] * 0.635V = 17.3mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.59V)/50Ω] * 1.59V = 13mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.3mW
ICS8S73034AMI REVISION A JUNE 8, 2011
15
©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
Reliability Information
Table 7A. θJA vs. Air Flow Table for an 16 Lead SOIC
θJA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
70.2°C/W
64.7°C/W
61.6°C/W
0
1
2.5
100.0°C/W
94.2°C/W
90.2°C/W
Table 7B. θJA vs. Air Flow Table for an 16 Lead TSSOP Forced Convection
θJA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
Transistor Count
The transistor count for ICS8S73034I is: 375
This device is pin and function compatible and a suggested replacement for ICS873034.
ICS8S73034AMI REVISION A JUNE 8, 2011
16
©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
Package Outlines and Package Dimensions
Package Outline - G Suffix for 16 Lead TSSOP
Package Outline - M Suffix for 16 Lead SOIC
A2
Table 8B. Package Dimensions
Table 8A. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
16
A
1.35
1.75
A1
0.10
0.25
B
0.33
0.51
C
0.19
0.25
D
9.80
10.00
E
3.80
4.00
e
1.27 Basic
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27
α
0°
8°
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
16
A
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
4.90
5.10
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
α
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MS-012
Reference Document: JEDEC Publication 95, MO-153
ICS8S73034AMI REVISION A JUNE 8, 2011
17
©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
Ordering Information
Table 9. Ordering Information
Part/Order Number
8S73034AMILF
8S73034AMILFT
8S73034AGILF
8S73034AGILFT
Marking
8S73034AMIL
8S73034AMIL
73034AIL
73034AIL
Package
“Lead-Free” 16 Lead SOIC
“Lead-Free” 16 Lead SOIC
“Lead-Free” 16 Lead TSSOP
“Lead-Free” 16 Lead TSSOP
Shipping Packaging
Tube
1000 Tape & Reel
Tube
2500 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
ICS8S73034AMI REVISION A JUNE 8, 2011
18
©2011 Integrated Device Technology, Inc.
ICS8S73034I Data Sheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
Revision History Sheet
Rev
Table
Page
Description of Change
1
A
2
8
9-10
Pin Description Table - corrected pin 1 as Q0 and pin 2 as nQ0.
Updated Wiring the Differential Input to Accept Single-ended Levels section.
Updated LVPECL Clock Input Interface sections.
11/8/10
A
1
Features Section - corrected Maximum input frequency bullet, from 2.8MHz to 3.2MHz.
6/8/11
ICS8S73034AMI REVISION A JUNE 8, 2011
Date
19
©2011 Integrated Device Technology, Inc.
ICS8S73034I Information Datasheet
LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER
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