8T33FS6111NLGI

Low Voltage 2.5V/3.3V Differential LVPECL/HSTL Fanout Buffer 8T33FS6111 DATA SHEET General Description Features The 8T33FS6111 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the 8T33FS6111 supports various applications that require distribution of precisely aligned differential clock signals. Using SiGe:C technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems. • 1:10 differential clock distribution • 28ps typical output skew • Fully differential architecture from input to all outputs • SiGe:C technology supports near-zero output skew • Supports DC to 2.7GHz operation of clock or data signals • LVPECL compatible differential clock outputs The 8T33FS6111 is designed for low skew clock distribution systems and supports clock frequencies up to 2.7GHz. The device accepts two clock sources. The CLKA input can be driven by LVPECL compatible signals, the CLKB input accepts HSTL or LVPECL compatible signals. The selected input signal is distributed to 10 identical, LVPECL outputs. If VBB is connected to the CLKA input and bypassed to GND by a 10nF capacitor, the 8T33FS6111 can be driven by single-ended LVPECL signals utilizing the VBB bias voltage output. • LVPECL/HSTL compatible differential clock inputs • Single 3.3V or 2.5V supply • Standard 32-Lead VFQFN package • Standard 32-lead LQFP package • Standard 32-lead TQFP package with EPAD • -40°C to 85°C ambient operating temperature In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. Block Diagram Q0 nQ0 The 8T33FS6111 can be operated from a single 3.3V or 2.5V supply. Q1 nQ1 VCC 29   VCC Q1 30 nQ2 nQ0 31 Q2 Q0 32 nQ1 VCC Pin Assignment 28 27 26 25 Q2 nQ2 CLKA nCLKA Q3 nQ3 0 Q4 nQ4 VCC 1 24 Q3 CLK_SEL 2 23 nQ3 CLKA 3 22 Q4 nCLKA 4 21 nQ4 VBB 5 20 Q5 Q8 nQ8 CLKB 6 19 nQ5 nCLKB 7 18 Q6 Q9 nQ9 VEE 8 17 nQ6 9 10 11 12 13 14 15 16 VCC nQ9 Q9 nQ8 Q8 nQ7 Q7 VCC 8T33FS6111 Q5 nQ5 VCC CLKB nCLKB CLK_SEL 1 Q6 nQ6 Q7 nQ7 VBB . 8T33FS6111 REVISION 1 12/02/14 1 ©2014 Integrated Device Technology, Inc. 8T33FS6111 DATA SHEET Pin Description and Characteristics Table 1. Pin Description Number Name Type Description Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation. 1 VCC Power 2 CLK_SEL Input 3 CLKA Input LVPECL Differential reference clock signal input. 4 nCLKA Input LVPECL Differential reference clock signal input. 5 VBB Output 6 CLKB Input HSTL/LVPECL Alternative differential reference clock signal input. 7 nCLKB Input HSTL/LVPECL Alternative differential reference clock signal input. 8 VEE Power Negative power supply. 9 VCC Power Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation. 10 nQ9 Output LVPECL 11 Q9 Output LVPECL 12 nQ8 Output LVPECL 13 Q8 Output LVPECL 14 nQ7 Output LVPECL 15 Q7 Output LVPECL 16 VCC Power 17 nQ6 Output LVPECL 18 Q6 Output LVPECL 19 nQ5 Output LVPECL 20 Q5 Output LVPECL 21 nQ4 Output LVPECL 22 Q4 Output LVPECL 23 nQ3 Output LVPECL 24 Q3 Output LVPECL 25 VCC Power 26 nQ2 Output LVPECL 27 Q2 Output LVPECL 28 nQ1 Output LVPECL 29 Q1 Output LVPECL 30 nQ0 Output LVPECL 31 Q0 Output LVPECL 32 VCC Power Active clock input select. DC Reference voltage output for single ended LVPECL operation. Differential clock outputs. Differential clock outputs. Differential clock outputs. Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation. Differential clock outputs. Differential clock outputs. Differential clock outputs. Differential clock outputs. Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation. Differential clock outputs. Differential clock outputs. Differential clock outputs. Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation. Table 2. Function Table Control Default 0 CLK_SEL 0 CLKA, nCLKA input pair is active. CLKA can be driven by LVPECL compatible signals. LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 2 1 CLKB, nCLKB input pair is active. CLKB can be driven by HSTL or LVPECL compatible signals. REVISION 1 12/02/14 8T33FS6111 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Electrical Characteristics or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Symbol Parameter VCC Supply Voltage VIN Condition Min Typical Max Unit –0.3 3.6 V DC Input Voltage –0.3 VCC + 0.3 V VOUT DC Output Voltage –0.3 VCC + 0.3 V IIN DC Input Current ±20 mA IOUT DC Output Current ±50 mA TS Storage Temperature 125 °C TJ Operating Junction Temperature 125 °C Max Unit –65 Table 3. General Specifications Symbol Characteristics Condition Min Voltage1 Typ VTT Output Termination VCC – 2 HBM ESD Protection  (Human Body Model) 4000 V CDM ESD Protection  (Charged Device Model) 2000 V LU Latch-up Immunity 200 mA CIN Input Capacitance Inputs 2 V pF NOTE 1: Output termination voltage VTT = 0V for VCC = 2.5V operation is supported but the power consumption of the device will increase REVISION 1 12/02/14 3 LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 8T33FS6111 DATA SHEET DC Electrical Characteristics Table 4. LVPECL/HSTL DC Characteristics, VCC = 2.5V ± 5% or VCC = 3.3V ± 5%, VEE = GND, TA = -40°C to +85°C Symbol Characteristics Condition Min Typ Max Unit Control Input CLK_SEL VIL Input Voltage Low VEE VCC – 1.475 V VIH Input Voltage High VCC – 1.165 VCC V IIN Input Current 100 A VIN = VIL or VIN = VIH Clock Input Pair CLKA, nCLKA (LVPECL differential signals) VPP Differential Input Voltage1 1,2 Differential operation 0.15 1.3 V 1.0 VCC – (VPP/2) V 150 A 1.0 V VCC – 1.1 V 200 A VCC – 1.3 VCC – 0.7 V VCC – 1.9 VCC – 1.5 V 100 mA VCC – 1.2 V VCMR Differential Crosspoint Voltage Differential operation IIN Input Current VIN = VIL or VIN = VIH Clock Input Pair CLKB, nCLKB (HSTL/LVPECL differential signals) VDIF Differential Input Voltage3 VX Differential Crosspoint IIN Input Current 0.4 Voltage3,4 0.10 VIN = VX ±0.2V 0.68 – 0.9 LVPECL Clock Outputs (Q[0:9], nQ[0:9]) VOH VOL Output High Voltage Output Low Voltage IOH = –30mA5 IOL = –5mA5 Supply Current and VBB IEE Maximum Quiescent Supply Current without Output Termination Current6 VBB Output Reference Voltage VEE pin IBB = 200A VCC – 1.4 NOTE 1: VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. VIL should not be less than -0.3V. VIH should not be greater than VCC. NOTE 2: VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the  VCMR (DC) range and the input swing lies within the VPP (DC) specification. NOTE 3: VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. VIL should not be less than -0.3V. VIH should not be greater than VCC. NOTE 4: VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the  VX (DC) range and the input swing lies within the VDIF (DC) specification. NOTE 5: Equivalent to a termination of 50 to VTT. NOTE 6: ICC calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE  ICC = (number of differential output pairs used) x (VOH – VTT)/Rload + (VOL – VTT)/Rload + IEE LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 4 REVISION 1 12/02/14 8T33FS6111 DATA SHEET AC Electrical Characteristics Table 5. AC Characteristics, VCC = 3.3V ±5% or VCC = 2.5V ±5%, VEE = GND, TA = -40°C to +85°C1 Symbol Characteristics Condition Min Typ Max Unit 2.7 GHz 530 ps 2.7 GHz 530 ps Clock Input Pair CLKA, nCLKA (LVPECL differential signals) fCLK Input Frequency2 Differential tPD Propagation Delay CLKA or  CLKB to Q[0:9] Differential 200 345 Clock Input Pair CLKB, nCLKB (HSTL/LVPECL differential signals) fCLK Input Frequency Differential tPD Propagation Delay  CLKB to Q[0:9] Differential 200 375 LVPECL Clock Outputs (Q[0:9], nQ[0:9]) Output Voltage (peak-to-peak) VO(P-P) fO < 300MHz 0.45 0.95 V fO < 1.5GHz 0.30 0.95 V fO < 2.7GHz 0.18 0.95 V 50 ps 250 ps 100 fs 75 ps 300 ps tsk(O) Output-to-Output Skew Differential tsk(PP) Part-to-Part Skew Differential tJIT Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section tsk(P) Output Pulse Skew3 t r, t f Output Rise/Fall Time 28 fCLK = 156.25MHz, 74 Integration Range: (12KHz - 20MHz) 20% to 80% 110 NOTE 1: AC characteristics apply for parallel output termination of 50 to VTT. NOTE 2: The 8T33FS6111I is fully operational up to 3.0GHz and is characterized up to 2.7GHz. NOTE 3: Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |. REVISION 1 12/02/14 5 LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 8T33FS6111 DATA SHEET Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase Noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Buffer RMS additive Jitter @ 156.25MHz Integration Range 12kHz - 20Mhz = 74fs (typical) As with most timing specifications, phase noise measurements have issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. Measured using a Wenzel 156.25MHz Oscillator as the input source. LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 6 REVISION 1 12/02/14 8T33FS6111 DATA SHEET Parameter Measurement Information 2V 2V VCC Qx SCOPE VCC Qx SCOPE nQx nQx VEE VEE -1.3V±0.165V -0.5V±0.125V 3.3V LVPECL Output Load AC Test Circuit 2.5V LVPECL Output Load AC Test Circuit VCC VCC nCLK[A,B] nCLK[A,B] CLK[A,B] CLK[A,B] VDIFF Cross Points VX VEE VEE Differential Input Level Differential Input Level Par t 1 nQx nQx Qx Qx nQy Par t 2 nQy Qy Qy tsk(pp) Part-to-Part Skew Output Skew nCLK[A,B] nQx 80% CLK[A,B] 80% VO(P-P) nQ[0:9] 20% 20% Qx Q[0:9] tR tF tPD Propagation Delay REVISION 1 12/02/14 Output Rise/Fall Time 7 LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 8T33FS6111 DATA SHEET Applications Information Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage V1= VCC/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set V1 at 1.25V. The values below are for when both the single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels Recommendations for Unused Input and Output Pins Inputs: Outputs: CLKx/nCLKx Inputs LVPECL Outputs For applications not requiring the use of a differential input, both the CLKx and nCLKx pins can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLKx to ground. For applications All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 8 REVISION 1 12/02/14 8T33FS6111 DATA SHEET Maintaining Lowest Device Skew The 8T33FS6111 guarantees low output-to-output bank skew of 50 ps and a part-to-part skew of max. 250ps. To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. If an entire output bank is not used, it is recommended to leave all of these outputs open and unterminated. This will reduce the device power consumption while maintaining minimum output skew. Power Supply Bypassing The 8T33FS6111 is a mixed analog/digital product. The differential architecture of the 8T33FS6111 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VCC pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. Figure 2. VCC Power Supply Bypass REVISION 1 12/02/14 9 LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 8T33FS6111 DATA SHEET Use of VBB for single ended LVPECL Clocks The VBB output pin often provided by LVPECL devices is designed to generate a temperature compensated logic threshold DC voltage for 3.3V LVPECL logic. This voltage is typically used when an upstream source, for whatever reason, has only one LVPECL output available. In this case the implied logic threshold voltage carried in the complementary LVPECL output of the driver is not available and must be generated at the receiver. In the Application Example below, this option is used to provide functionality of a 1:2 fan out buffer passively. When AC coupling devices from different manufacturers the VBB voltage over temperature does not have to be checked against the logic threshold of the source driver to ensure that there is enough drive level above and below VBB for reliable switching. Figure 3. Application Example - Wiring Differential Inputs to Accept a Single Ended LVPECL Level LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 10 REVISION 1 12/02/14 8T33FS6111 DATA SHEET EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Lead frame Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 4. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale) REVISION 1 12/02/14 11 LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 8T33FS6111 DATA SHEET 3.3V LVPECL Clock Input Interface The CLK /nCLK accepts LVPECL, LVDS, CML and other differential signals. Both differential outputs must meet the VPP and VCMR input requirements. Figure 5A to Figure 5E show interface examples for the CLK/ nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 3.3V 3.3V 3.3V 3.3V 3.3V R3 84 3.3V 3.3V LVPECL Zo = 50Ω C1 Zo = 50Ω C2 R4 84 CLK CLK nCLK nCLK R5 100 - 200 LVPECL Input CML R6 100 - 200 R1 125 LVPECL Input R2 125 Figure 5D. CLK/nCLK Input Driven by a  3.3V LVPECL Driver with AC Couple Figure 5A. CLK/nCLK Input Driven by a CML Driver 3.3V 3.3V 3.3V 3.3V Zo = 50Ω Zo = 50 CLK CLK R1 100 R1 100Ω nCLK Zo = 50Ω Zo = 50 LVPECL CML Built-In Pullup LVDS Input nCLK LVPECL Input Figure 5E. CLK/nCLK Input Driven by a  3.3V LVDS Driver Figure 5B. CLK/nCLK Input Driven by a  Built-In Pullup CML Driver 3.3V 3.3V 3.3V R3 125Ω R4 125Ω Zo = 50Ω CLK Zo = 50Ω nCLK LVPECL R1 84Ω R2 84Ω LVPECL Input Figure 5C. CLK/nCLK Input Driven by a  3.3V LVPECL Driver LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 12 REVISION 1 12/02/14 8T33FS6111 DATA SHEET 2.5V LVPECL Clock Input Interface The CLK /nCLK accepts LVPECL, LVDS, CML and other differential signals. Both differential outputs must meet the VPP and VCMR input requirements. Figure 6A to Figure 6E show interface examples for the CLK/ nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 2.5V 2.5V 2.5V CLK nCLK LVPECL Input CML Figure 6D. CLK/nCLK Input Driven by a 2.5V LVPECL Driver with AC Couple Figure 6A. CLK/nCLK Input Driven by a CML Driver 2.5V 2.5V CLK nCLK LVPECL CML Built-In Pullup Input Figure 6B. CLK/nCLK Input Driven by a  Built-In Pullup CML Driver Figure 6E. CLK/nCLK Input Driven by a 2.5V LVDS Driver 2.5V 2.5V 2.5V CLK nCLK LVPECL LVPECL Input Figure 6C. CLK/nCLK Input Driven by a  2.5V LVPECL Driver REVISION 1 12/02/14 13 LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 8T33FS6111 DATA SHEET Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion.  Figure 7A and Figure 7B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are a low impedance follower output that generate LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 R3 125 3.3V R4 125 3.3V 3.3V Zo = 50 + _ Input Zo = 50 R1 84 Figure 7A. 3.3V LVPECL Output Termination LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER R2 84 Figure 7B. 3.3V LVPECL Output Termination 14 REVISION 1 12/02/14 8T33FS6111 DATA SHEET Termination for 2.5V LVPECL Outputs level. The R3 in Figure 8B can be eliminated and the termination is shown in Figure 8C. Figure 8A and Figure 8B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground 2.5V 2.5V 2.5V VCC = 2.5V R1 250Ω VCC = 2.5V R3 250Ω 50Ω 50Ω + + 50Ω 50Ω – – 2.5V LVPECL Driver 2.5V LVPECL Driver R2 62.5Ω R1 50Ω R4 62.5Ω Figure 8A. 2.5V LVPECL Driver Termination Example R2 50Ω Figure 8C. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50Ω + 50Ω – 2.5V LVPECL Driver R1 50Ω R2 50Ω R3 18Ω Figure 8B. 2.5V LVPECL Driver Termination Example REVISION 1 12/02/14 15 LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 8T33FS6111 DATA SHEET Power Considerations (TQFP with EPAD) This section provides information on power dissipation and junction temperature for the 8T33FS6111.  Equations and example calculations are also provided. 1. Power Dissipation The total power dissipation for the 8T33FS6111 is the sum of the core power plus the power dissipated due to output switching (load).  The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. The maximum core current at 85°C is as follows: IEE_MAX = 100mA Core • Power(core) = VDD_MAX * (IEE_MAX) = 3.465V * 100mA = 346.5mW  LVPECL Output LVPECL driver power dissipation is 33.2mW/Loaded output pair, total power dissipation due to LVPECL outputs switching: • Power (outputs)MAX = 33.2mW/Loaded Output pair If all outputs are loaded, the total power is 10 * 33.2mW = 332mW  Total Power Dissipation • Total Power = Power (core) + Power(outputs) = 346.5mW + 332mW  = 678.5mW  2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 35.3°C/W for TQFP package (with ePAD) per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.679W * 35.3°C/W = 108.9°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 32-Lead TQFP, EPad JA by Velocity Meters per Second 0 1 2 Multi-Layer PCB, JEDEC Standard Test Boards 35.3 31.8 30.3 LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 16 REVISION 1 12/02/14 8T33FS6111 DATA SHEET Power Considerations (LQFP) The 8T33FS6111 device was designed and characterized to operate within the ambient industrial temperature range of -40°C to +85°C. The ambient temperature represents the temperature around the device, not the junction temperature. The LQFP package has no EPAD. When using the device in extreme cases, such as high ambient temperature, external air flow or using less number of outputs or lower supply voltage such as 2.5V may be required in order to ensure a safe and reliable junction temperature. Extreme care must be taken to avoid exceeding 125°C junction temperature. The power calculation examples below were generated using a maximum ambient temperature and 2.5V supply voltage. Depending on the applications, the power consumption can be lower or higher. Please contact IDT technical support for any concerns on calculating the power dissipation for your own specific configuration. This section provides information on power dissipation and junction temperature for the 8T33FS6111.  Equations and example calculations are also provided. 1. Power Dissipation The total power dissipation for the 8T33FS6111 is the sum of the core power plus the power dissipated due to output switching (load).  The following is the power dissipation for VDD = 2.5V +5% = 2.625V. The maximum core current at 85°C is as follows: IEE_MAX = 95mA Core • Power(core) = VDD_MAX * (IEE) = 2.625V * 95mA = 249.4mW  LVPECL Output LVPECL driver power dissipation is 33.2mW/Loaded output pair, total power dissipation due to LVPECL outputs switching: • Power (outputs)MAX = 33.2mW/Loaded Output pair If eight outputs are loaded, the total power is 8 * 33.2mW = 265.6mW Total Power Dissipation Total Power = Power (core) + Power (outputs) = 249.4mW + 265.6mW  = 515mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 76.1°C/W for LQFP package per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.515W *76.1°C/W = 124.2°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance JA for 32-Lead LQFP JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards REVISION 1 12/02/14 0 1 2 76.1 72.4 70.2 17 LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 8T33FS6111 DATA SHEET 3A. Calculations and Equations for LVPECL. The purpose of this section is to calculate power dissipation on the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 9. VDDO Q1 VOUT RL VDDO - 2V Figure 9. LVPECL Driver Circuit and Termination To calculate power dissipation per output pair due to loading, use the following equations which assume a 50 load, and a termination voltage of VDDO – 2V. • For logic high, VOUT = VOH_MAX = VDDO_MAX – 0.7V (VDD_MAX – VOH_MAX) = 0.7V • For logic low, VOUT = VOL_MAX = VDDO_MAX – 1.5V (VDD_MAX – VOL_MAX) = 1.5V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VDDO_MAX – 2V))/RL] * (VDDO_MAX – VOH_MAX) = [(2V – (VDDO_MAX – VOH_MAX))/RL] * (VDDO_MAX – VOH_MAX) = [(2V – 0.7V)/50] * 0.7V = 18.2mW Pd_L = [(VOL_MAX – (VDDO_MAX – 2V))/RL] * (VDDO_MAX – VOL_MAX) = [(2V – (VDDO_MAX – VOL_MAX))/RL] * (VDDO_MAX – VOL_MAX) = [(2V – 1.5V)/50] * 1.5V = 15mW Total Power Dissipation per output pair = Pd_H + Pd_L = 33.2mW LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 18 REVISION 1 12/02/14 8T33FS6111 DATA SHEET Reliability Information Table 8. JA vs. Air Flow Table for a 32-Lead VFQFN, EPad JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2 48.9 42.0 39.4 0 1 2 35.3 31.8 30.3 0 1 2 76.1 72.4 70.2 Table 9. JA vs. Air Flow Table for a 32-Lead TQFP, EPad JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Table 10. JA vs. Air Flow Table for a 32-Lead LQFP JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for 8T33FS6111 is: 989 REVISION 1 12/02/14 19 LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 8T33FS6111 DATA SHEET Package Information, VFQFN with ePAD LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 20 REVISION 1 12/02/14 8T33FS6111 DATA SHEET Package Information, VFQFN with ePAD, continued REVISION 1 12/02/14 21 LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 8T33FS6111 DATA SHEET Package Information, TQFP with ePAD LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 22 REVISION 1 12/02/14 8T33FS6111 DATA SHEET Package Information, TQFP with ePAD, continued REVISION 1 12/02/14 23 LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 8T33FS6111 DATA SHEET Package Information, TQFP with ePAD, continued LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 24 REVISION 1 12/02/14 8T33FS6111 DATA SHEET Package Information, LQFP REVISION 1 12/02/14 25 LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 8T33FS6111 DATA SHEET Package Information, LQFP, continued LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 26 REVISION 1 12/02/14 8T33FS6111 DATA SHEET Ordering Information Table 11. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 8T33FS6111NLGI IDT8T33FS6111NLGI 32-Lead VFQFN (EPAD), Lead-Free Tray -40°C to 85°C 8T33FS6111NLGI8 IDT8T33FS6111NLGI 32-Lead VFQFN (EPAD), Lead-Free Tape & Reel -40°C to 85°C 8T33FS6111DXGI IDT8T33FS6111DXGI 32-Lead TQFP (EPAD), Lead-Free Tray -40°C to 85°C 8T33FS6111DXGI8 IDT8T33FS6111DXGI 32-Lead TQFP (EPAD), Lead-Free Tape & Reel -40°C to 85°C 8T33FS6111PFGI IDT8T33FS6111PFGI 32-Lead LQFP, Lead-Free Tray -40°C to 85°C 8T33FS6111PFGI8 IDT8T33FS6111PFGI 32-Lead LQFP, Lead-Free Tape & Reel -40°C to 85°C NOTE: Parts that are ordered with an “G” suffix to the part number are the Pb-Free configuration and are RoHS compliant. LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL FANOUT BUFFER 27 REVISION 1 12/02/14 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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