FemtoClock® NG Crystal-to-HCSL
Clock Generator
IDT8V41N004I
DATA SHEET
General Description
Features
The IDT8V41N004I is a clock generator designed for Gigabit
Ethernet, 10 Gigabit Ethernet, SGMII and PCI Express™
applications. The device generates a selectable 100MHz, 125MHz,
156.25MHz or 312.5MHz clock signal from 25MHz input. The
IDT8V41N004I uses IDT’s fourth generation FemtoClock®NG
technology to provide low phase noise performance, combined with
excellent power supply noise rejection for optimal performance in the
targeted applications. The device supports a 3.3V supply voltage and
is packaged in a compact, lead-free (RoHS 6) 32-lead VFQFN
package. The industrial temperature range supports high end
computing, telecommunication and networking end equipment
requirements.
•
•
Fourth generation FemtoClock® NG technology
•
•
Selectable external crystal or differential input source
•
Differential CLK, nCLK input pair accepts LVPECL, LVDS,
LVHSTL, HCSL input levels
•
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
•
•
•
•
PCI Express Gen1, Gen2, and Gen 3 compliant
Four 100MHz, 125MHz, 156.25MHz and 312.5MHz clocks for
Gigabit Ethernet, 10 Gigabit Ethernet, SGMII and PCI Express
applications, HCSL interface levels
Crystal oscillator interface designed for 25MHz parallel
resonant crystal
RMS phase jitter 156.25MHz (12kHz - 20MHz): 0.217ps
Full 3.3V supply voltage
-40°C to 85°C ambient operating temperature
23 22
21 20 19 18
nQ3
Q3
GND
nQ2
Q2
VDD
17
16
FSEL1
nQ0
26
15
FSEL0
Q0
27
14
VDD
VDD
28
13
XTAL_OUT
OE3
29
12
XTAL_IN
OE2
30
11
CLK_SEL
VDD
31
10
nREF_OUT
VDDA
32
4
5
OE1
OE0
IREF
6
7
8
nCK
3
CLK
2
VDD
1
OE_REF
IDT8V41N004I
PLL_BYPASS
GND
24
25
nQ1
Q1
Pin Assignment
9
REF_OUT
32 Lead VFQFN
5mm x 5mm x 0.925mm Package Body
3.15mm x 3.15mm EPad Size
NL Package
Top View
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
1
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
Block Diagram
OE_REF
Pulldown
REF_OUT
nREF_OUT
CLK_SEL
Pulldown
Q0
nQ0
1
XTAL_IN
OSC
XTAL_OUT
CLK
nCLK
x2
Pulldown
PU/PD
FSEL[1:0]
0
1
FemtoClock® NG
PLL
2.5GHz
00
01
10
11
÷
÷
÷
÷
16
25
20
8
Q1
nQ1
Q2
0
nQ2
Q3
nQ3
IREF
FSEL1
Pulldown
FSEL0
Pulldown
PLL_BYPASS
Pulldown
OE0
Pulldown
OE1
OE2
OE3
Pulldown
Pulldown
Pulldown
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
2
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
1
PLL_BYPASS
Type
Input
Pulldown
2
OE_REF
Input
Pulldown
3
OE1
Input
Pulldown
Pulldown
Description
Active HIGH PLL bypass. LVCMOS/LVTTL interface levels.
PLL_BYPASS = 0: PLL mode (default)
PLL_BYPASS = 1: Bypass mode
Active HIGH output enable for REF_OUT, nREF_OUT differential output.
LVCMOS/LVTTL interface levels.
OE_REF = 0: Output REF_OUT disabled/high Impedance (default)
OE_REF = 1: Output REF_OUT enabled
Active HIGH output enable for Q1, nQ1 differential output. LVCMOS/LVTTL
interface levels.
OE1 = 0: Output Q1 disabled/high impedance (default)
OE1 = 1: Output Q1 enabled
Active HIGH output enable for Q0, nQ0 differential output. LVCMOS/LVTTL
interface levels.
OE0 = 0: Output Q0 disabled/high impedance (default)
OE0 = 1: Output Q0 enabled
External fixed precision resistor (475) from this pin to ground provides a
reference current used for HCSL outputs.
Supply voltage pins.
4
OE0
Input
5
IREF
Input
6, 14, 22, 28, 31
VDD
Power
7
CLK
Input
Pulldown
Non-inverting differential clock input.
8
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. VDD/2 default when left floating.
9,
10
REF_OUT,
nREF_OUT
Output
Differential reference clock output pair. HCSL interface levels.
Pulldown
Active HIGH clock select input. Selects PLL input source. LVCMOS /LVTTL
interface levels.
CLK_SEL = 0: XTAL_IN, XTAL_OUT (default)
CLK_SEL = 1: CLK, nCLK
11
CLK_SEL
Input
12,
13
XTAL_IN,
XTAL_OUT
Input
Crystal oscillator interface. XTAL_IN is the input., XTAL_OUT is the output.
Output frequency select pins. LVCMOS/LVTTL interface levels.
FSEL[1:0] = 00: FOUT = 156.25MHz (default)
FSEL[1:0] = 01: FOUT = 100MHz
FSEL[1:0] = 10: FOUT = 125MHz
FSEL[1:0] = 11: FOUT = 312.5MHz
15, 16
FSEL0, FSEL1
Input
17, 18
nQ3, Q3
Output
Differential output pair. HCSL interface levels.
19, 25
GND
Power
Power supply ground.
20, 21
nQ2, Q2
Output
Differential output pair. HCSL interface levels.
23, 24
nQ1, Q1
Output
Differential output pair. HSCL interface levels.
26, 27
nQ0, Q0
Output
Differential output pair. HCSL interface levels.
29
OE3
Input
30
OE2
Input
32
VDDA
Power
Pulldown
Pulldown
Active HIGH output enable for Q3, nQ3 differential output.
LVCMOS/LVTTL interface levels.
OE3 = 0: Output Q3 disabled/high impedance (default)
OE3 = 1: Output Q3 enabled
Pulldown
Active HIGH output enable for Q2, nQ2 differential output.
LVCMOS/LVTTL interface levels.
OE2 = 0: Output Q2 disabled/high impedance (default)
OE2 = 1: Output Q2 enabled
Analog supply voltage.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
3
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
3.5
pF
RPULLUP
Input Pullup Resistor
51
K
RPULLDOWN
Input Pulldown Resistor
51
K
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
3.6V
Inputs, VI
XTAL_IN
Other Inputs
0V to 2V
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDD + 0.5V
Package Thermal Impedance, JA
33.1°C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA =-40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA; NOTE 1
Analog Supply Voltage
IDD
Power Supply Current
IDDA
Analog Supply Current
Test Conditions
Outputs Disabled
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VDD – 0.155
3.3
VDD
V
121
mA
31
mA
NOTE 1: This device requires that VDD and VDDA are powered simultaneously. See Power Supply Sequence Requirement application note.
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
4
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
Table 3B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA =-40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
Test Conditions
Input
High Current
FSEL[1:0],
CLK_SEL,
OE_REF,
PLL_BYPASS,
OE0, OE1,
OE2, OE3
VDD = VIN = 3.465V
Input
Low Current
FSEL[1:0],
CLK_SEL,
OE_REF,
PLL_BYPASS,
OE0, OE1,
OE2, OE3
VDD = 3.465V, VIN = 0V
Minimum
Typical
Maximum
Units
2
VDD + 0.3
V
-0.3
0.8
V
150
µA
-5
µA
Table 3C. Differential DC Characteristics, VDD = 3.3V ± 5%, TA =-40°C to 85°C
Symbol
Parameter
Test Conditions
IIH
Input High
Current
IIL
Input Low
Current
VPP
Peak-to-Peak Input Voltage
VCMR
Common Mode Input Voltage;
NOTE 1
CLK, nCLK
Minimum
Typical
VDD = VIN = 3.465V
Maximum
Units
150
µA
CLK
VDD = 3.465V, VIN = 0V
-5
µA
nCLK
VDD = 3.465V, VIN = 0V
-150
µA
0.15
1.3
V
GND + 0.5
VDD – 0.85
V
Maximum
Units
NOTE 1: Common mode voltage is defined as the crosspoint.
Table 4. Crystal Characteristics
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Fundamental
Frequency
25
MHz
Load Capacitance (CL)
12
pF
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
Maximum
Units
NOTE: Characterized using a 12pF parallel resonant crystal.
Table 5. Input Frequency Characteristics, VDD = 3.3V ± 5%, TA =-40°C to 85°C
Symbol
Parameter
fIN
Input
Frequency
fIN_DC
Input Duty
Cycle
Test Conditions
Minimum
Typical
XTAL_IN,
XTAL_OUT
25
MHz
CLK, nCLK
25
MHz
CLK, nCLK
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
45
5
55
%
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
AC Electrical Characteristics
Table 6A. PCI Express Jitter Specifications, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Typical
Maximum
PCIe Industry
Specification
Units
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
11
18
86
ps
Phase Jitter
RMS;
NOTE 2, 4
ƒ = 100MHz, 25MHz Crystal Input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
1.0
1.6
3.10
ps
tREFCLK_LF_RMS
(PCIe Gen 2)
Phase Jitter
RMS;
NOTE 2, 4
ƒ = 100MHz, 25MHz Crystal Input
Low Band: 10kHz - 1.5MHz
0.24
1.1
3.0
ps
tREFCLK_RMS
(PCIe Gen 3)
Phase Jitter
RMS;
NOTE 3, 4
ƒ = 100MHz, 25MHz Crystal Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
0.24
0.41
0.8
ps
Symbol
Parameter
tj
(PCIe Gen 1)
Phase Jitter
Peak-to-Peak;
NOTE 1, 4
tREFCLK_HF_RMS
(PCIe Gen 2)
Test Conditions
Minimum
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 106 clock periods.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS
(High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
6
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
Table 6B. AC Characteristics, VDD = 3.3V ± 5%, TA =-40°C to 85°C
Symbol
fOUT
Parameter
Output
Frequency
Test Conditions
Minimum
Typical
Maximum
Units
Q[0:3], nQ[0:3]
FSEL[1:0] = 00
156.25
MHz
Q[0:3], nQ[0:3]
FSEL[1:0] = 01
100
MHz
Q[0:3], nQ[0:3]
FSEL[1:0] = 10
125
MHz
Q[0:3], nQ[0:3]
FSEL[1:0] = 11
312.5
MHz
XTAL, CLK, nCLK = 25MHz
25
MHz
REF_OUT
N(100)
Single-Side Band Noise
Power, 100Hz from Carrier
25MHz Crystal Input,
fOUT = 156.25MHz
-85
dBc/Hz
N(1k)
Single-Side Band Noise
Power, 1kHz from Carrier
25MHz Crystal Input,
fOUT = 156.25MHz
-118
dBc/Hz
N(10k)
Single-Side Band Noise
Power, 10kHz from Carrier
25MHz Crystal Input,
fOUT = 156.25MHz
-133
dBc/Hz
N(100k)
Single-Side Band Noise
Power, 100kHz from Carrier
25MHz Crystal Input,
fOUT = 156.25MHz
-138
dBc/Hz
N(1M)
Single-Side Band Noise
Power, 1MHz from Carrier
25MHz Crystal Input,
fOUT = 156.25MHz
-143
dBc/Hz
N(10M)
Single-Side Band Noise
Power, 10MHz from Carrier
25MHz Crystal Input,
fOUT = 156.25MHz
-156
dBc/Hz
100MHz,
Integration Range
(12kHz to 20MHz)
0.219
ps
125MHz,
Integration Range:
12kHz – 20MHz
0.205
ps
156.25MHz,
Integration Range:
12kHz – 20MHz
0.217
ps
312.5MHz,
Integration Range:
12kHz – 20MHz
0.215
ps
25MHz crystal input
Integration Range:
12kHz - 5MHz
0.268
ps
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 1, 2
tREF_OUT_RMS
Phase Jitter RMS; NOTE 1
tsk(o)
Output Skew; NOTE 3, 4
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 3
PLL Mode
12
ps
tjit(per)
Period Jitter, RMS; NOTE 3
PLL Mode
3.8
ps
tL
PLL Lock Time
VMAX
Absolute Max. Output Voltage;
NOTE 5, 6
VMIN
Absolute Min. Output Voltage;
NOTE 5, 7
-300
VRB
Ringback Voltage; NOTE 8, 9
-100
tSTABLE
Time before VRB is Allowed;
NOTE 8, 9
500
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
Q[0:3], nQ[0:3]
7
100
ps
30
ms
1150
mV
mV
100
mV
ps
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
Symbol
Parameter
VCROSS
Absolute Crossing Voltage;
NOTE 5, 10, 11
VCROSS
Total Variation of VCROSS Over
all Edges; NOTE 5, 10, 12
PSNR
Power Supply Noise Rejection
tSLEW+
Rising Edge Rate; NOTE 8, 13
0.6
4.0
V/ns
tSLEW-
Falling Edge Rate; NOTE 8, 13
0.6
4.0
V/ns
odc
Output Duty
Cycle;
NOTE 8
45
55
%
Q[0:3], nQ[0:3]
Test Conditions
Minimum
fOUT = 100MHz
230
Typical
Maximum
Units
550
mV
140
mV
45
25MHz Crystal Input
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Refer to Phase Noise Plot section.
NOTE 2: REF_OUT, nREF_OUT is disabled.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 5. Measurement taken from a single ended waveform.
NOTE 6. Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 7: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 8: Measurement taken from a differential waveform.
NOTE 9: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB ±100 mV differential range.
NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx+ equals the falling edge of Qx-.
NOTE 11: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement.
NOTE 12:Defined as the total variation of all crossing voltages of rising Qx+ and falling Qx-, This is the maximum allowed variance in Vcross
for any particular system. See Parameter Measurement Information Section.
NOTE 13: Measured from -150mV to +150mV on the differential waveform (derived from Q minus nQ). The signal must be monotonic through
the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
8
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
Noise Power (dBc/Hz)
Typical Phase Noise at 156.25MHz
Offset Frequency (HZ)
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
9
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
Noise Power (dBc/Hz)
Typical Phase Noise at 25MHz (REF_OUT, nREF_OUT)
Offset Frequency (HZ)
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
10
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
Parameter Measurement Information
3.3V±5%
3.3V±5%
3.3V±5%
3.3V±5%
SCOPE
Measurement
Point
VDD
VDD
50
VDDA
VDDA
2pF
Measurement
Point
IREF
50
IREF
GND
GND
475
2pF
0V
0V
0V
0V
This load condition is used for VMAX, VMIN, VRB, tSTABLE, VCROSS,
VCROSS and tSLEW± measurements.
This load condition is used for tjit(cc), tjit(per), tjit(Ø),
tREF_OUT_RMS, N, tsk(o), and odc measurements.
3.3V HCSL Output Load Test Circuit 1
3.3V HCSL Output Load Test Circuit 2
VDD
nQ[0:3]
nCLK
Q[0:3]
➤
PP
Cross Points
tcycle n
CLK
➤
V
➤
tcycle n+1
➤
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
V
CMR
GND
Differential Input Level
Cycle-to-Cycle Jitter
VOH
nQx
VREF
Qx
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Reference Point
(Trigger Edge)
nQy
Qy
tsk(o)
Histogram
Mean Period
(First edge after trigger)
Period Jitter
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
Output Skew
11
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
Parameter Measurement Information, continued
Noise Power
Phase Noise Plot
Offset Frequency
f1
f2
RMS Phase Jitter =
1
* Area Under Curve Defined by the Offset Frequency Markers
2* *ƒ
PLL Lock Time
RMS Phase Jitter
TSTABLE
Clock Period (Differential)
Positive Duty
Cycle (Differential)
VRB
Negative Duty
Cycle (Differential)
+150mV
VRB = +100mV
0.0V
VRB = -100mV
-150mV
0.0V
Q - nQ
VRB
Q - nQ
TSTABLE
Differential Measurement Points for Ringback
Differential Measurement Points for Duty Cycle/Period
nQ
VMAX
nQ
VCROSS_MAX
VCROSS
VCROSS_MIN
Q
VMIN
Q
Single-ended Measurement Points for Delta Cross Point
Single-ended Measurement Points for Absolute Cross
Point and Swing
Rise Edge Rate
Fall Edge Rate
+150mV
0.0V
-150mV
Q - nQ
Differential Measurement Points for Rise/Fall Edge Rate
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
12
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
Outputs:
Crystal Inputs
Differential Outputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
XTAL_IN to ground.
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1 = VDD/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1 in the center of the input voltage swing.
For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and
R2 value should be adjusted to set V1 at 1.25V. The values below are
for when both the single ended swing and VDD are at the same
voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
13
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both signals must meet the VPP and VCMR input
requirements. Figures 2A to 2E show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
vendor of the driver component to confirm the driver termination
requirements. For example, in Figure 2A, the input termination
applies for IDT open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
Zo = 50Ω
nCLK
nCLK
Differential
Input
LVHSTL
R1
50Ω
IDT
LVHSTL Driver
R2
50Ω
Differential
Input
LVPECL
R1
50Ω
R2
50Ω
R2
50Ω
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
3.3V
3.3V
3.3V
R3
125Ω
3.3V
R4
125Ω
3.3V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100Ω
Zo = 50Ω
nCLK
Differential
Input
LVPECL
R1
84Ω
R2
84Ω
Zo = 50Ω
LVDS
nCLK
Receiver
Figure 2D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
Figure 2C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
3.3V
*R3
33Ω
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
HCSL
*R4
33Ω
R1
50Ω
R2
50Ω
Differential
Input
*Optional – R3 and R4 can be 0Ω
Figure 2E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
14
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
Power Supply Sequence Requirement
The IDT8V41N004I has a power supply sequence requirement. This
device requires that VDD and VDDA are powered simultaneously. This
device has been characterized using the recommended power
supply filtering techniques in Figure 4.
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by one
side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 3A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
VCC
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 3B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
XTAL_OUT
R1
100
Ro
Rs
C1
Zo = 50 ohms
XTAL_IN
R2
100
Zo = Ro + Rs
.1uf
LVCMOS Driver
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_IN
.1uf
Zo = 50 ohms
LVPECL Driver
R1
50
R2
50
R3
50
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
15
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
Schematic Example
Figure 4 (next page) shows an example of an IDT8V41N004I
application schematic. The schematic example focuses on functional
connections and is intended as an example only. It may not represent
the exact user configuration. Refer to the pin description and
functional tables in the datasheet to ensure that the logic control
inputs are properly set. For example, OE[3:0] and FSEL[1:0] can be
configured from an FPGA instead of set with pull up and pull down
resistors as shown.
supply isolation is required. The IDT8V41N004I provides separate
power supply pins to isolate noise from coupling into the internal PLL.
In order to achieve the best possible filtering, it is highly
recommended that the 0.1uF capacitors at the output of the LC filter
be placed on the IDT8V41N004I side of the PCB as close to the
corresponding power pin as possible. This is represented by the
placement of these capacitors in the schematic.
Do not share ground vias; use at least one ground via per 0.1uF cap
or crystal load cap. If space is limited, the ferrite beads, 10uf
capacitors and the 0.1uF capacitors connected directly to 3.3V can
be placed on the opposite side of the PCB. If space permits, place all
filter components on the device side of the board.
For this device, the crystal load capacitors are required for proper
operation. A 12pF parallel resonant 25MHz crystal is used. The load
capacitance C1 = C2 = 1pF is recommended for frequency accuracy.
Depending on the parasitic of the printed circuit board layout, these
values might require a slight adjustment to optimize the frequency
accuracy. Crystals with other load capacitance specifications can be
used, but this will require adjusting C1 and C2.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
The schematic example shows two different HCSL output
terminations; the standard termination when the HCSL receiver is on
the same PCB as the IDT8V41N004I as well as the termination for a
PCIe add-in card.
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
16
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
C8
0.1uF
C6
VDD
C9
0.1uF
0. 1uF
3. 3V
2
1
PLL_BYPASS
OE_R EF
OE0
OE1
OE2
OE3
2
4
3
30
29
F SEL0
F SEL1
15
16
CLK_SEL
11
25MHz (12pf )
C1
1pF
12
X1
OE_REF
OE0
OE1
OE2
OE3
Place ea ch 0.1uF b ypass cap directly
adjacent to its co rrespondi ng VDD or VDDA pin.
Optional
R EF_OUT
XTAL_IN
XTAL_OUT
nQ0
nQ1
7
Zo = 50 Ohm
8
R3 50
CLK
Q2
nQ2
Q3
5
REF _OU T
10
nR EF_OUT
27
Q0
26
nQ 0
24
Q1
23
nQ 1
21
Q2
20
nQ 2
18
Q3
17
nQ 3
0" to 18"
Zo = 50
33
+
R6
33
Zo = 50
HCSL_Receiv er
R12
50
R9
50
PCI Express
Point-to-Poi nt
Connection
HCSL Termination
nCLK
3.3V PECL Driv er
R4
50
R7
9
CLK_SEL
Q1
R2 50
C5
10uF
F SEL0
F SEL1
C2
1pF
Zo = 50 Ohm
C3
0.1uF
VD DA
C7
0.1uF
Q0
XTAL_OUT 13
C4
10uF
R1 5
32
PLL_BYPASS
nR EF_OUT
XTAL_IN
C10
0.1uF
VDD
VDDA
1
BLM18BB221SN 1
6
31
VDD
VD D
VDD
22
14
VDD
U1
28
VD D
C11
0.1uF
FB1
IREF
nQ3
R5
475
VDD
Set Logic
Input to '1'
R U1
1K
VDD
19
25
Logic Control Input Examples
EPAD
R13
33
1" to 14"
Z o = 50
0.5" to 3.5"
Z o = 50
+
33
Z o = 50
R11
50
33
GND
GND
R10
R8
50
Z o = 50
HCSL_Receiv er
PCI Express Add-In Card
Set Logic
Input to '0'
RU2
Not Inst all
To Logic
Input
pins
R D1
N ot Install
To Logic
Input
pins
RD2
1K
Note:
PLL_BYPASS, OE_REF, OE[3:0] and FSEL[1:0] are internally pulled down so no external
components are required to s elect the defaults.
If external pull-up/down needed, see "Logic Control Input Examples" s hown at left.
Figure 4. IDT8V41N004I Schematic Layout
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
17
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
PCI Express Application Note
PCI Express jitter analysis methodology models the system
response to reference clock jitter. The block diagram below shows the
most frequently used Common Clock Architecture in which a copy of
the reference clock is provided to both ends of the PCI Express Link.
In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs
are modeled as well as the phase interpolator in the receiver. These
transfer functions are called H1, H2, and H3 respectively. The overall
system transfer function at the receiver is:
Ht s = H3 s H1 s – H2 s
The jitter spectrum seen by the receiver is the result of applying this
system transfer function to the clock spectrum X(s) and is:
Y s = X s H3 s H1 s – H2 s
In order to generate time domain jitter numbers, an inverse Fourier
Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].
PCIe Gen 2A Magnitude of Transfer Function
PCI Express Common Clock Architecture
For PCI Express Gen 1, one transfer function is defined and the
evaluation is performed over the entire spectrum: DC to Nyquist (e.g
for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is
reported in peak-peak.
PCIe Gen 2B Magnitude of Transfer Function
For PCI Express Gen 3, one transfer function is defined and the
evaluation is performed over the entire spectrum. The transfer
function parameters are different from Gen 1 and the jitter result is
reported in RMS.
PCIe Gen 1 Magnitude of Transfer Function
For PCI Express Gen 2, two transfer functions are defined with 2
evaluation ranges and the final jitter number is reported in rms. The
two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz
(Low Band) and 1.5MHz – Nyquist (High Band). The plots show the
individual transfer functions as well as the overall transfer function Ht.
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
PCIe Gen 3 Magnitude of Transfer Function
For a more thorough overview of PCI Express jitter analysis
methodology, please refer to IDT Application Note PCI Express
Reference Clock Requirements.
18
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 5. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
19
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
Recommended Termination
Figure 6A is the recommended source termination for applications
where the driver and receiver will be on a separate PCBs. This
termination is the standard for PCI Express™ and HCSL output
0.5" Max
Rs
types. All traces should be 50Ω impedance single-ended or 100Ω
differential.
0.5 - 3.5"
1-14"
0-0.2"
22 to 33 +/-5%
L1
L2
L4
L1
L2
L4
L5
L5
PCI Expres s
PCI Expres s
Connector
Driver
0-0.2"
L3
L3
PCI Expres s
Add-in Card
49.9 +/- 5%
Rt
Figure 6A. Recommended Source Termination (where the driver and receiver will be on separate PCBs)
Figure 6B is the recommended termination for applications where a
point-to-point connection can be used. A point-to-point connection
contains both the driver and the receiver on the same PCB. With a
matched termination at the receiver, transmission-line reflections will
0.5" Max
Rs
0 to 33
L1
be minimized. In addition, a series resistor (Rs) at the driver offers
flexibility and can help dampen unwanted reflections. The optional
resistor can range from 0Ω to 33Ω. All traces should be 50Ω
impedance single-ended or 100Ω differential.
0-18"
0-0.2"
L2
L3
L2
L3
0 to 33
L1
PCI Expres s
Driver
49.9 +/- 5%
Rt
Figure 6B. Recommended Termination (where a point-to-point connection can be used)
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
20
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8V41N004I.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the IDT8V41N004I is the sum of the core power plus analog power plus the power dissipation at the outputs.
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipation at the outputs.
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (121mA + 31mA) = 526.7mW
•
Power (outputs)MAX = 44.5mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 44.5mW = 222.5mW
Total Power_MAX = (3.465V, if all outputs are loaded) = 526.7mW + 222.5mW = 749.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 33.1°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.749W * 33.1°C/W = 109.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
0
1
3
33.1°C/W
28.1°C/W
25.4°C/W
21
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pairs.
HCSL output driver circuit and termination are shown in Figure 7.
VDD
IOUT = 17mA
➤
VOUT
RREF =
475Ω ± 1%
RL
50Ω
IC
Figure 7. HCSL Driver Circuit and Termination
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,
use the following equations which assume a 50 load to ground.
The highest power dissipation occurs at VDD_MAX.
Power = (VDD_MAX – VOUT) * IOUT
since VOUT = IOUT * RL
Power
= (VDD_MAX – IOUT * RL) * IOUT
= (3.465V – 17mA * 50) * 17mA
Total Power Dissipation per output pair = 44.5mW
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
22
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
Reliability Information
Table 7. JA vs. Air Flow Table for a 32 Lead VFQFN
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
3
33.1°C/W
28.1°C/W
25.4°C/W
Transistor Count
The transistor count for IDT8V41N004I is: 24,809
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
23
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
32 Lead VFQFN Package Outline and Package Dimensions
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
24
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
Ordering Information
Table 8. Ordering Information
Part/Order Number
8V41N004NLGI
8V41N004NLGI8
Marking
IDT8V41N004NLGI
IDT8V41N004NLGI
IDT8V41N004NLGI REVISION A DECEMBER 18, 2012
Package
“Lead-Free” 32 Lead VFQFN
“Lead-Free” 32 Lead VFQFN
25
Shipping Packaging
Tray
Tape & Reel
Temperature
-40C to 85C
-40C to 85C
©2012 Integrated Device Technology, Inc.
FEMTOCLOCK®NG CRYSTAL-TO-HCSL CLOCK GENERATOR
IDT8V41N004I Data Sheet
We’ve Got Your Timing Solution
6024 Silver Creek Valley Road
San Jose, California 95138
Sales
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
www.IDT.com/go/contactIDT
Technical Support
netcom@idt.com
+480-763-2056
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2012. All rights reserved.
工商网监
湘ICP备2023018690号
