9173B-01CS08LFT

DATASHEET ICS9173B VIDEO GENLOCK PLL Description Features The ICS9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when using a low frequency input clock to generate a high frequency output clock. The ICS9173B contains a phase detector, charge pump, loop filter, and voltage-controlled oscillator (VCO). The ICS674-01 can be used as the external feedback divider. • Phase-detector/VCO circuit block • Ideal for genlock system • Reference clock range 12 kHz to 1 MHz for full output clock range • Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions • • • • A common application of the ICS9173B is the implementation of a video genlock circuit. Because of this, the ICS9173B inputs operate on the negative-going clock edge. On-chip loop filter Single 5 V power supply Low power CMOS technology 8-pin SOIC package The ICS9173B is pin and function compatible to the AV9173-01/15. Block Diagram IDT® VIDEO GENLOCK PLL 1 ICS9173B REV D 012913 ICS9173B VIDEO GENLOCK PLL CLOCK SYNTHESIZER Pin Assignment FBIN 1 8 CLK2 IN 2 7 VDD GND 3 6 CLK1 FS0 4 5 OE 8 pin SOIC Pin Descriptions Pin Number Pin Name Pin Type Pin Description 1 FBIN Input Feedback input. 2 IN Input Input for reference sync pulse. 3 GND Power Ground. 4 FS0 Input Frequency select 0 input. 5 OE Input Output enable. 6 CLK1 Output Clock output 1. 7 VDD Power Power supply (+5 V). 8 CLK2 Output Clock output 2 (divided-by-2 from Clock 1). Allowable Input Frequency to Output Frequency for ICS9173B-01 (in MHz) (ICS9173B-15 outputs run at exactly half of the ICS9173B-01 frequencies) fOUT for FS = 0 fOUT for FS = 1 fIN (kHz) CLK1 Output CLK2 Output CLK1 Output CLK2 Output 12 < fIN < 14 kHz 44.0 to 75 22.0 to 37.5 11.0 to 18.75 5.5 to 9.375 14 < fIN < 17 kHz 30.0 to 75 15.0 to 37.5 7.5 to 18.75 3.75 to 9.375 17 < fIN < 30 kHz 25.0 to 75 12.5 to 37.5 6.25 to 18.75 3.125 to 9.375 30 < fIN < 35 kHz 15.0 to 75 7.5 to 37.5 3.75 to 18.75 1.875 to 9.375 35 < fIN < 1000 kHz 10.0 to 75 5.0 to 37.5 2.5 to 18.75 1.25 to 9.375 IDT® VIDEO GENLOCK PLL 2 ICS9173B REV D 012913 ICS9173B VIDEO GENLOCK PLL CLOCK SYNTHESIZER Using the ICS9173B in Genlock Applications desired dot clock frequency. The primary consideration is the internal VCO which operates over a frequency range of 10 MHz to 75 MHz. Because of the selectable VCO output divider and the additional divider on output CLK2, four distinct output frequency ranges can be achieved. The following Table lists these ranges and the corresponding device configuration. Most video sources, such as video cameras, are asynchronous, free-running devices. To digitize video or synchronize one video source to another free-running reference video source, a video “genlock” (generator lock) circuit is required. The ICS9173B integrates the analog blocks which make the task much easier. In the complete video genlock circuit, the primary function of the ICS9173B is to provide the analog circuitry required to generate the video dot clock within a PLL. This application is illustrated in Figure 1. The input reference signal for this circuit is the horizontal synchronization (H-SYNC) signal. If a composite video reference source is being used, the h-sync pulses must be separated from the composite signal. A video sync separator circuit, such as the National Semiconductor LM1881, can be used for this purpose. FS0 State Output Used Frequency/Range ICS9173B-01 Frequency/Range IcS9173B-15 0 CLK1 10 to 75 MHz 5 to 37.5 MHz 0 CLK2 5 to 37.5 MHz 2.5 to 18.75 MHz 1 CLK1 2.5 to 18.75 MHz 1.25 to 9.375 MHz 1 CLK2 1.25 to 9.375 MHz 0.625 to 4.6875 MHz Note that both outputs, CLK1 and CLK2, are available during operation even though only one is fed back via the external clock divider. The clock feedback divider shown in Figure 1 is a digital divider used within the PLL to multiply the reference frequency. Its divide ratio establishes how many video dot clock cycles occur per h-sync pulse. For example, if 880 pixel clocks are desired per h-sync pulse, then the divider ratio is set to 880. Hence, together the h-sync frequency and external divider ratio establish the dot clock frequency: Pin 5, OE, tristates both CLK1 and CLK2 upon logic low input. This feature can be used to revert dot clock control to the system clock when not in genlock mode (hence, when in genlock mode the system dot clock must be tristated). fOUT = fIN x N where N is external divide ratio When unused, inputs FS0 and OE must be tied to either GND (logic low) or VDD (logic high). Both input pins IN and FBIN respond only to negative-going clock edges of the input signal. The H-SYNC signal must be constant frequency in the 12 kHz to 1 MHz range and stable (low clock jitter) for creation of a stable output clock. The output hook-ups of the ICS9173B are dictated by the Figure 1: Typical Application of ICS9173B in a Video Genlock System IDT® VIDEO GENLOCK PLL 3 ICS9173B REV D 012913 ICS9173B VIDEO GENLOCK PLL CLOCK SYNTHESIZER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS9173B. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V Storage Temperature -65 to +150C Voltage on I/O Pins referenced to GND GND - 0.5 V to VDD + 0.5 V Junction Temperature 125C Soldering Temperature 260C Power Dissipation 0.5 Watts Recommended Operation Conditions Parameter Min. Operating Temperature under Bias Typ. -0 Power Supply Voltage (measured with respect to GND) +4.75 +5 V Max. Units +70 C +5.25 V DC Electrical Characteristics Unless stated otherwise, VDD = 5 V ±5%, Ambient Temperature 0 to +70C Parameter Symbol Conditions Min. Typ. Max. Units 20 50 mA 0.8 V Operating Supply Current IDD No load,50 MHz Input Low Voltage VIH VDD = 5 V Input High Voltage VIL VDD = 5 V 2.0 V Input Low Current IIL VIN = 0V -5 µA Input High Current IIH VIN = VDD -5 Output Low Voltage 5 µA 0.4 V VOL IOL = 8 mA Output High Voltage 1 VOH1 IOH = -1 mA VDD-0.4 V Output High Voltage 1 VOH2 IOH = -4 mA VDD-0.8 V Output High Voltage 1 VOH3 IOH = -8 mA 2.4 V Notes: 1. Duty cycle measured at 1.4 V. 2. Input Reference Frequency = 25 kHz, Output Frequency = 25 MHz. Jitter measured between adjacent vertical pixels. 3. CLK1 frequency applies for FS = 0. For FS = 1 condition, divide allowable CLK1 range by the factor of 4. IDT® VIDEO GENLOCK PLL 4 ICS9173B REV D 012913 ICS9173B VIDEO GENLOCK PLL CLOCK SYNTHESIZER AC Electrical Characteristics Unless stated otherwise, VDD = 5 V ±5%, Ambient Temperature 0 to +70 C Parameter Symbol Output Clock Rise Time Output Clock Fall Time 1 1 Conditions Min. Typ. Max. Units ICLKr 10 ns ICLKf 10 ns Output Rise Time 1 tr1 15 pF load, 0.8 to 2.0V 0.6 1.5 ns Output Rise Time 1 tr2 15 pF load, 20% to 80% VDD 1.3 3.0 ns tf1 15 pF load, 0.8 to 2.0V 0.6 1.5 ns tf2 15 pF load, 80% to 20% VDD 0.7 2.0 ns 47 55 % 120 250 ps ±250 400 ps Output Fall Time 1 Output Fall Time 1 Output Duty Cycle One-Sigma Jitter Jitter, Absolute 15 pF load 1, 5 T1S1 1, 5 One-Sigma Jitter Jitter, Absolute 1 1, 5 1, 5 1 Line-to-Line Jitter , Absolute Input Frequency 1, 2 T1S2 CLK1 frequency < 25 MHz 1 % TABS2 CLK1 frequency < 25 MHz 2 % -400 TLABS fIN fCLK1 CLK1 Frequency, -15 3 CLK1 frequency , 25 MHz 1, 3, 4 1, 3, 4 CLK1 frequency , 25 MHz TABS1 IN or FBIN CLK1 Frequency, -01 40 3 fCLK1 ±4 ns see allowable fi below 12 1000 kHz 12 < fIN < 14 kHz 44 75 MHz 14 < fIN < 17 kHz 30 75 17 < fIN < 30 kHz 25 75 30 < fIN < 35 kHz 15 75 35 < fIN < 1000 kHz 10 75 12 < fIN < 14 kHz 22 37.5 14 < fIN < 17 kHz 15 37.5 17 < fIN < 30 kHz 12.5 37.5 30 < fIN < 35 kHz 7.5 37.5 5 37.5 35 < fIN < 1000 kHz MHz Notes: 1. Parameter is guaranteed by design and characterization. Not 100% tested in production. 2. Input Reference Frequency = 25 kHz, Output Frequency = 25 MHz. Jitter measured between adjacent vertical pixels. 3. CLK1 frequency applies for FS = 0. For FS = 1 condition, divide allowable CLK1 range by the factor of 4. 4. An Application Brief (AB01) documents the operation of the AV9173 for low input frequencies. This provides guidelines for usable output frequencies and feedback ratios required to use inputs below 25 kHz. By following these guidelines, the ICS9173B will operate down to 12 kHz inputs across temperature, voltage and lot-to-lot variation. 5. Jitter values are measured at frequencies > 25 MHz for IDT9173B-01, for ICS9173B-15, jitter is measured at frequency > 12.5 MHz. IDT® VIDEO GENLOCK PLL 5 ICS9173B REV D 012913 ICS9173B VIDEO GENLOCK PLL CLOCK SYNTHESIZER Thermal Characteristics Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient JA Still air 150 C/W JA 1 m/s air flow 140 C/W JA 3 m/s air flow 120 C/W Thermal Resistance Junction to Case JC 40 C/W Thermal Resistance Junction to Top of Case JT 20 C/W Still air Marking Diagram B01CS08L LOT YYWW Notes: 1. Line 1: truncated part number 2. YYWW is the last two digits of the year and week that the part was assembled. 3. “LOT” denotes the lot number. 4. “L” suffix designates RoHS compliant package. 5. Bottom mark: country of origin. IDT® VIDEO GENLOCK PLL 6 ICS9173B REV D 012913 ICS9173B VIDEO GENLOCK PLL CLOCK SYNTHESIZER Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 8 Millimeters Symbol E Min A A1 B C D E e H h L  H INDEX AREA 1 2 D A Inches Max Min 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0 8 Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0 8 h x 45 A1 C -Ce SEATING PLANE B  L .10 (.004) C Ordering Information Part / Order Number Shipping Packaging Package Temperature 9173B-01CS08LF 9173B-01CS08LFT 9173B-15CS08LF 9173B-15CS08LFT Tubes Tape and Reel Tubes Tape and Reel 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C "LF" suffix to the part number denotes Pb-Free configuration, RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT® VIDEO GENLOCK PLL 7 ICS9173B REV D 012913 ICS9173B VIDEO GENLOCK PLL CLOCK SYNTHESIZER Revision History Rev. Originator Date A R.Willner 09/23/08 New datasheet. B RDW 11/12/09 Released to final. C RDW 07/29/11 Corrected typographical errors on page 5 for rise/fall times D LPL 01/29/13 Added top-side device marking IDT® VIDEO GENLOCK PLL Description of Change 8 ICS9173B REV D 012913 ICS9173B VIDEO GENLOCK PLL CLOCK SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. 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