9DB106BGLFT

DATASHEET 9DB106 Six Output Differential Buffer for PCIe Gen 2 Description Features/Benefits The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (CLKREQ#) pins make the 9DB106 suitable for Express Card applications. • • • • • CLKREQ# pin for outputs 1 and 4/ supports Express Card applications PLL or bypass mode/PLL can dejitter incoming clock Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's Spread Spectrum Compatible/tracks spreading input clock for low EMI SMBus Interface/unused outputs can be disabled Recommended Applications 6 Output Differential Buffer for PCIe Gen 2 Key Specifications Output Features • • • Cycle-to-cycle jitter < 50ps Output-to-output skew < 50 ps 6 - 0.7V current mode differential output pairs (HCSL) Functional Block Diagram CLKREQ1# CLKREQ4# PCIEX1 CLK_INT C LK_INC SPREAD COMPATIBLE PLL PCIEX4 PCIEX(0,2,3,5) PLL_BW SMBDAT CONTROL LOGIC SMBCLK IREF IDT® Six Output Differential Buffer for PCIe Gen 2 9DB106 1 REV L 05/24/12 9DB106 Six Output Differential Buffer for PCIe Gen 2 PLL_BW CLK_INT CLK_INC vCLKREQ1# PCIEXT0 PCIEXC0 VDD GND PCIEXT1 PCIEXC1 PCIEXT2 PCIEXC2 VDD SMBDAT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 9DB106 Pin Configuration 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDDA GNDA IREF vCLKR EQ4# PCIEXT5 PCIEXC5 VDD GND PCIEXT4 PCIEXC4 PCIEXT3 PCIEXC3 VDD SMBCLK Note:Pins preceeded by ' v ' have internal 120K ohm pull down resistors 28-pin SSOP & TSSOP Power Groups Pin Number VDD GND 7, 13, 16, 22 8,21 TBD TBD N/A 27 28 27 Description PCI Express Outputs SMBUS IREF Analog VDD & GND for PLL core IDT® Six Output Differential Buffer for PCIe Gen 2 9DB106 2 REV L 05/24/12 9DB106 Six Output Differential Buffer for PCIe Gen 2 Pin Description PIN # PIN NAME PIN TYPE 1 PLL_BW IN 2 3 CLK_INT CLK_INC IN IN 4 vCLKREQ1# IN 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PCIEXT0 PCIEXC0 VDD GND PCIEXT1 PCIEXC1 PCIEXT2 PCIEXC2 VDD SMBDAT SMBCLK VDD PCIEXC3 PCIEXT3 PCIEXC4 PCIEXT4 GND VDD PCIEXC5 PCIEXT5 25 vCLKREQ4# OUT OUT PWR IN OUT OUT OUT OUT PWR I/O IN PWR OUT OUT OUT OUT PWR PWR OUT OUT IN DESCRIPTION 3.3V input for selecting PLL Band Width 0 = low, 1= high True Input for differential reference clock. Complementary Input for differential reference clock. Output enable for PCI Express output pair 1. 0 = enabled, 1 =disabled True clock of differential PCI_Express pair. Complementary clock of differential PCI_Express pair. Power supply, nominal 3.3V Ground pin. True clock of differential PCI_Express pair. Complementary clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Complementary clock of differential PCI_Express pair. Power supply, nominal 3.3V Data pin of SMBUS circuitry, 5V tolerant Clock pin of SMBUS circuitry, 5V tolerant Power supply, nominal 3.3V Complementary clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Complementary clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Ground pin. Power supply, nominal 3.3V Complementary clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Output enable for PCI Express output pair 4. 0 = enabled, 1 =disabled 26 IREF OUT This pin establishes the reference for the differential current-mode output pairs. It requires a fixed precision resistor to ground. 475ohm is the standard value for 100ohm differential impedance. Other impedances require different values. See data sheet. 27 28 GNDA VDDA PWR PWR Ground pin for the PLL core. 3.3V power for the PLL core. Note: Pins preceeded by ' v ' have internal 120K ohm pull down resistors IDT® Six Output Differential Buffer for PCIe Gen 2 9DB106 3 REV L 05/24/12 9DB106 Six Output Differential Buffer for PCIe Gen 2 Electrical Characteristics - Absolute Maximum Ratings 1 2 PARAMETER SYMBOL 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Input Low Voltage Input High Voltage Input High Voltage VDDA VDD VIL VIH VIHSMB Storage Temperature Junction Temperature Input ESD protection Ts Tj ESD prot CONDITIONS MIN TYP MAX 4.6 4.6 GND-0.5 Except for SMBus interface SMBus clock and data pins V DD+0.5V 5.5V -65 Human Body Model 150 125 2000 UNITS NOTES V V V V V 1,2 1,2 1 1 1 1 1 1 ° C °C V Guaranteed by design and characterization, not 100% tested in production. Operation under these conditions is neither implied nor guaranteed. Electrical Characteristics - Input/Supply/Common Output Parameters TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN Ambient Operating Temperature TCOM TIND Commmercial range Industrial range 0 -40 70 85 °C °C 1 1 Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V 1,2 Input Low Voltage Input High Current VIL IIH 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pullup resistors VIN = 0 V; Inputs with pull-up resistors Full Active, CL = Full load; all differential pairs tri-stated VDD = 3.3 V VSS - 0.3 -5 0.8 5 V uA 1,2 1,2 -5 uA 1,2 -200 uA 1,2 150 40 105 7 5 4.5 mA mA MHz nH pF pF 1 1 1 1 1 1.8 ms 1 I IL1 Input Low Current I IL2 Operating Supply Current IDD3.3OP Input Frequency Pin Inductance Fi Lpin CIN COUT Input Capacitance Clk Stabilization TSTAB OE# Latency tLATOE# SMBus Voltage Low-level Output Voltage Current sinking at VOL = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time VDD VOL 130 30 80 Logic Inputs Output pin capacitance From VDD reaching 3.1V and input clock stable Input Spread Spectrum Modulation Frequency TYP 100 MAX UNITS Notes Triangular Modulation 30 33 kHz 1 DIF start after OE# assertion DIF stop after OE# deassertion 1 3 cycles 1,3 2.7 5.5 0.4 V V 1 1 mA 1 1000 ns 1 300 ns 1 @ I PULLUP I PULLUP TRI2C TFI2C 4 (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) 1 Guaranteed by design and characterization, not 100% tested in production. Except differential input clock 2 3 Time from deassertion until outputs are >200mV IDT® Six Output Differential Buffer for PCIe Gen 2 9DB106 4 REV L 05/24/12 9DB106 Six Output Differential Buffer for PCIe Gen 2 Electrical Characteristics - Clock Input Parameters TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL Input High Voltage DIF_IN Input Low Voltage DIF_IN Input Common Mode Voltage - DIF_IN CONDITIONS Differential inputs (single-ended measurement) Differential inputs (single-ended measurement) VIHDIF VILDIF MIN TYP MAX UNITS NOTES 600 800 1150 mV 1 VSS - 300 0 300 mV 1 VCOM Common Mode Input Voltage 300 1000 mV 1 Input Amplitude - DIF_IN VSWING Peak to Peak value 300 1450 mV 1 Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2 Input Leakage Current I IN -5 5 uA 1 Input Duty Cycle dtin VIN = VDD , VIN = GND Measurement from differential wavefrom 45 55 % 1 Input Jitter - Cycle to Cycle J DIFIn 0 125 ps 1 1 2 Differential Measurement Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through +/-75mV window centered around differential zero Electrical Characteristics - PLL Parameters TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% Group Parameter Description Min Typ Max Units Notes PLL Jitter Peaking jpeak-hibw (PLL_BW = 1) 0 1 2.5 dB 1,4 PLL Jitter Peaking jpeak-lobw (PLL_BW = 0) 0 1 2 dB 1,4 PLL Bandwidth PLL Bandwidth pllHIBW pllLOBW (PLL_BW = 1) (PLL_BW = 0) PCIe Gen 1 phase jitter (1.5 - 22 MHz) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz (PLL_BW=1) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz (PLL_BW=0) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Lo-Band