Datasheet
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
Description
Features/Benefits
The 9DB1904 is electrically compatible to the Intel DB1900GS •
Differential Buffer Specification. This buffer provides 19 output clocks
for PCI-Express Gen2 or Intel QPI 6.4GT/s applications. A differential
clock from a CK410B+ main clock generator, such as the •
ICS932S421 drives the 9DB1904. The 9DB1904 can provide •
outputs up to 400MHz in Bypass Mode.
•
Recommended Application
19 Output Differential Buffer for PCIe Gen2 and QPI
•
Key Specifications
•
DIF output cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 150ps across all outputs
Functionality at Power Up (PLL Mode)
CLK_IN
100M_133M#
MHz
1
100MHz
0
133MHz
OUTPUTS
PLL State
ON
OFF
DIF_14
DIF_14#
DIF/DIF#
Running
Hi-Z
CKPWRGD_PD#
DIF_15
DIF_15#
OE15_16#
DIF_ 16
DIF_16#
VDD
DIF_17
DIF_17#
DIF_18
DIF_18#
OE17_18#
CLK_IN
GND
INPUTS
CKPWRGD_ CLK_IN/
PD#
CLK_IN#
1
Running
0
X
DIF_(18:0)
MHz
CLK_IN
CLK_IN
SMB_A2_PLLBYP#
Pin Configuration
Power Down Functionality
CLK_IN#
•
•
Power up default is all outputs in 1:1 mode/No SMBus
programming
Spread spectrum compatible/EMI reductions
Supports output frequencies up to 400 MHz in bypass
mode/flexible fanout buffer
8 Selectable SMBus addresses/no SMBus
segmentation required
SMBus address determines PLL or Bypass mode/pin
savings
Dedicated VDDA and CKPWRGD_PD# pins/easy board
design
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
IREF
GNDA
VDDA
HIGH_BW#
100M_133M#_LV
DIF_0
DIF_0#
DIF_1
DIF_1#
GND
VDD
DIF_2
DIF_2#
DIF_3
DIF_3#
DIF_4
DIF_4#
OE_01234#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
9DB1904BKLF
OE14#
DIF_13#
DIF_13
OE13#
DIF_12#
DIF_12
OE12#
VDD
GND
DIF_11#
DIF_11
OE11#
DIF_10#
DIF_10
OE10#
DIF_9#
DIF_9
OE9#
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
SMB_A1
SMB_A0
DIF_8#
DIF_8
OE8#
DIF_7#
DIF_7
OE7#
GND
VDD
DIF_6#
DIF_6
OE6#
DIF_5#
DIF_5
OE5#
SMBDAT
SMBCLK
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
1607C —04/19/11
1
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
Pin Description
PIN #
PIN NAME
PIN TYPE
1
IREF
OUT
2
3
GNDA
VDDA
PWR
PWR
4
HIGH_BW#
IN
5
100M_133M#_LV
IN
6
7
8
9
10
11
12
13
14
15
16
17
DIF_0
DIF_0#
DIF_1
DIF_1#
GND
VDD
DIF_2
DIF_2#
DIF_3
DIF_3#
DIF_4
DIF_4#
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
18
OE_01234#
IN
19
20
SMBCLK
SMBDAT
IN
I/O
21
OE5#
IN
22
23
DIF_5
DIF_5#
24
OE6#
25
26
27
28
DIF_6
DIF_6#
VDD
GND
29
OE7#
30
31
DIF_7
DIF_7#
32
OE8#
33
34
35
36
DIF_8
DIF_8#
SMB_A0
SMB_A1
OUT
OUT
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
IN
IN
DESCRIPTION
This pin establishes the reference for the differential current-mode output
pairs. It requires a fixed precision resistor to ground. 475ohm is the standard
value for 100ohm differential impedance. Other impedances require different
values. See data sheet.
Ground pin for the PLL core.
3.3V power for the PLL core.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Low Threshold Input to select operating frequency.
See Functionality Table for Definition
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.
1 =disable outputs, 0 = enable outputs
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
Active low input for enabling DIF pair 5.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
Active low input for enabling DIF pair 7.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 8.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
SMBus address bit 0 (LSB)
SMBus address bit 1
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
1607C—04/19/11
2
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
Pin Description (continued)
PIN #
PIN NAME
PIN TYPE
37
OE9#
IN
38
39
DIF_9
DIF_9#
OUT
OUT
40
OE10#
IN
41
42
DIF_10
DIF_10#
43
OE11#
44
45
46
47
DIF_11
DIF_11#
GND
VDD
48
OE12#
49
50
DIF_12
DIF_12#
51
OE13#
52
53
DIF_13
DIF_13#
54
OE14#
55
56
DIF_14
DIF_14#
57
CKPWRGD_PD#
58
59
DIF_15
DIF_15#
60
OE15_16#
61
62
63
64
65
66
67
68
DIF_ 16
DIF_16#
VDD
GND
DIF_17
DIF_17#
DIF_18
DIF_18#
69
OE17_18#
IN
70
71
CLK_IN
CLK_IN#
IN
IN
72
SMB_A2_PLLBYP#
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
DESCRIPTION
Active low input for enabling DIF pair 9.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 10.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 11.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
Active low input for enabling DIF pair 12.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 13.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 14.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
3.3V Input notifies device to sample latched inputs and start up on first high
assertion, or exit Power Down Mode on subsequent assertions. Low enters
Power Down Mode.
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pairs 15 and 16.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pairs 17 and 18.
1 =disable outputs, 0 = enable outputs
True Input for differential reference clock.
Complementary Input for differential reference clock.
SMBus address bit 2. When Low, the part operates as a fanout buffer with the
PLL bypassed. When High, the part operates as a zero-delay buffer (ZDB) with
the PLL operating.
0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used)
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
1607C—04/19/11
3
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
Functional Block Diagram
OE(17_18)#
OE(15_16)#
OE(14:5)#,
OE_01234#
13
PLL
(SS Compatible)
CLK_IN
CLK_IN#
HIGH_BW#
100M_133M#_LV
CKPWRGD_PD#
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
19
DIF(18:0)
Logic
IREF
Power Groups
Pin Number
VDD
GND
3
2
11,27,47,63 10,28,46,64
Description
PLL, Analog
DIF clocks
9DB1904 Frequency Selects for PLL Mode
Byte 9,
bit 2
100M_133M#_LV
1
0
Byte9,
bit 1
FSB
0
0
Byte 9,
bit 0
FSA
1
1
CLK_IN
MHz
DIF Outputs
MHz
100.00
133.33
100.00
133.33
Notes
1
2
Notes:FS_A_410 = 1
1. Powerup Default for 100M_133M# = 1
2. Powerup Default for 100M_133M# = 0
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
1607C—04/19/11
4
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER
SYMBOL
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
VDDA
VDD
VIL
VIH
VIHSMB
Storage Temperature
Junction Temperature
Input ESD protection
Ts
Tj
ESD prot
CONDITIONS
MIN
TYP
MAX
4.6
4.6
GND-0.5
Except for SMBus interface
SMBus clock and data pins
VDD+0.5V
5.5V
-65
Human Body Model
150
125
2000
UNITS NOTES
V
V
V
V
V
°
C
°C
V
1,2
1,2
1
1
1
1
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
Electrical Characteristics - Clock Input Parameters
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
Input High Voltage - DIF_IN
VIHDIF
Input Low Voltage - DIF_IN
VILDIF
Input Common Mode
Voltage - DIF_IN
Input Amplitude - DIF_IN
Input Slew Rate - DIF_IN
Input Leakage Current
Input Duty Cycle
Input Jitter - Cycle to Cycle
CONDITIONS
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
MIN
TYP
MAX
UNITS NOTES
600
800
1150
mV
1
VSS - 300
0
300
mV
1
VCOM
Common Mode Input Voltage
300
1000
mV
1
VSWING
dv/dt
IIN
dtin
J DIFIn
Peak to Peak value
Measured differentially
VIN = VDD , VIN = GND
Measurement from differential wavefrom
Differential Measurement
300
0.4
-5
45
0
1450
8
5
55
125
mV
V/ns
uA
%
ps
1
1,2
1
1, 3
1
1
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through +/-75mV window centered around differential zero
3
Input duty cycle will directly impact output duty cycle in bypass mode. It has no impact in PLL mode.
2
Electrical Characteristics - Current Consumption
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER
Operating Supply Current
Powerdown Current
1
SYMBOL
CONDITIONS
IDD3.3OP
IDD3.3AOP
I DD3.3PD
IDD3.3APD
VDD, All outputs active @100MHz
VDDA, All outputs active @100MHz
VDD
VDDA
MIN
TYP
425
35
20
12
MAX
UNITS
NOTES
450
45
25
15
mA
mA
mA
mA
1
1
1
1
Guaranteed by design and characterization, not 100% tested in production. Zo = 100Ω
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
1607C—04/19/11
5
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
Electrical Characteristics - Input/Supply/Common Parameters
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
Ambient Operating
Temperature
TCOM
Commmercial range
0
70
°C
1
Input High Voltage
VIH
2
VDD + 0.3
V
1
Input Low Voltage
VIL
GND - 0.3
0.8
V
1
Low Threshold InputHigh Voltage
Low Threshold InputLow Voltage
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
TYP
MAX
UNITS NOTES
VIH_FS
3.3 V +/-5%, Applies to 100M_133M#_LV pin
0.7
VDD + 0.3
V
1
VIL_FS
3.3 V +/-5%, Applies to 100M_133M#_LV pin
VSS - 0.3
0.35
V
1
IIN
Single-ended inputs, VIN = GND, VIN = VDD
-5
5
uA
1
IINP
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
-200
200
uA
1
VDD = 3.3 V, Bypass mode
VDD = 3.3 V, 100MHz PLL mode
VDD = 3.3 V, 133.33MHz PLL mode
33
90
120
CINDIF_IN
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
1.5
1.5
400
110
147
7
5
2.7
MHz
MHz
MHz
nH
pF
pF
2
2
2
1
1
1,4
COUT
Output pin capacitance
6
pF
1
Clk Stabilization
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1.8
ms
1,2
Input SS Modulation
Frequency
fMODIN
Allowable Frequency
(Triangular Modulation)
30
33
kHz
1
OE# Latency
tLATOE#
4
12
clocks
1,3
Tdrive_PD#
tDRVPD
300
us
1,3
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tF
tR
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
PD# de-assertion
Fall time of control inputs
Rise time of control inputs
VILSMB
VIHSMB
VOLSMB
IPULLUP
VDDSMB
t RSMB
tFSMB
5
5
0.8
@ IPULLUP
@ VOL
3V to 5V +/- 10%
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
5.5
1000
300
ns
ns
V
V
V
mA
V
ns
ns
1,2
1,2
1
1
1
1
1
1
1
fMAXSMB
Maximum SMBus operating frequency
100
kHz
1,5
Input Current
Input Frequency
Pin Inductance
Capacitance
Fibyp
Fipll
Fipll
Lpin
CIN
2.1
4
2.7
100.00
133.33
VDDSMB
0.4
1
Guaranteed by design and characterization, not 100% tested in production.
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until outputs are >200 mV
4
DIF_IN input
2
5
The differential input clock must be running for the SMBus to be active
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
1607C—04/19/11
6
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Slew rate
Slew rate matching
Trf
ΔTrf
Scope averaging on
Slew rate matching, Scope averaging on
1
2
12.6
Voltage High
VHigh
660
797
Voltage Low
VLow
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Max Voltage
Min Voltage
Vswing
Crossing Voltage (abs)
Crossing Voltage (var)
Vmax
Vmin
Vswing
Vcross_abs
Δ-Vcross
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
Scope averaging off
Scope averaging off
MAX UNITS NOTES
V/ns 1, 2, 3
4
%
20
1, 2, 4
850
1
mV
-150
39
150
857
7
1510
378
57
1150
-300
300
250
550
140
1
mV
mV
mV
mV
1
1
1, 2
1, 5
1, 6
Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475Ω (1%), I REF = 2.32mA.
I OH = 6 x I REF and VOH = 0.7V @ ZO=50Ω (100Ω differential impedance).
1
2
Measured from differential waveform
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope uses for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross
absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
9DBxxx Differential Test Loads
Rs
Differential Zo
2pF
Rs
Rp
2pF
Rp
HSCL Output
Buffer
Differential Output Termination Table
DIF Zo (Ω) Iref (Ω)
Rs (Ω)
Rp (Ω)
100
475
33
50
85
412
27
43.2
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
1607C—04/19/11
7
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
PLL Bandwidth
BW
PLL Jitter Peaking
Duty Cycle
tJPEAK
t DC
Duty Cycle Distortion
t DCD
tpdBYP
Skew, Input to Output
tpdPLL
1
2
DIF_IN, DIF [x:0]
Δt pd_BYP
DIF_IN, DIF [x:0]
Δ tpd_PLL
DIF[X:0]
tJPH
DIF[X:0]
tSSTERROR
Skew, Output to Output
tsk3
Jitter, Cycle to cycle
t jcyc-cyc
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
-3dB point in High BW Mode
-3dB point in Low BW Mode
Peak Pass band Gain
Measured differentially, PLL Mode
Measured differentially, Bypass Mode
@100MHz
Bypass Mode, nominal value @ 25°C, 3.3V,
VT = 50%
PLL Mode, nominal value @ 25°C, 3.3V,
VT = 50%
Input-to-Output Skew Variation in Bypass
mode
(over specified voltage / temperature operating
ranges)
Input-to-Output Skew Variation in PLL mode
(over specified voltage / temperature operating
ranges)
Differential Phase Jitter (RMS Value)
Differential Spread Spectrum Tracking Error
(peak to peak)
VT = 50%
PLL mode
Additive Jitter in Bypass Mode
2
0.7
45
3
1
1.4
49.5
4
1.4
2
55
MHz
MHz
dB
%
1
1
1
1,2
-2
1
2
%
1,2,5
2500
3700
4500
ps
1,2,4
100
300
500
ps
1,2,3
|500|
|600|
ps
1,2,4,6,7,
8,9,13
|250|
|350|
ps
1,2,3,6,7,
8,9,13
2
10
ps
1,7,10
40
80
ps
1,7,12
100
40
25
150
50
50
ps
ps
ps
1
1,2
1,2
Guaranteed by design and characterization, not 100% tested in production. CLOAD = 2pF
Measured from differential cross-point to differential cross-point
3
PLL mode Input-to-Output skew is measured at the first output edge following the corresponding input.
4
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
5
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
VT = 50% of Vout
7
This parameter is deterministic for a given device
6
8
Measured with scope averaging on to find mean value.
9
Long-term variation from nominal of input-to-output skew over temperature and voltage for a single device.
10
This parameter is measured at the outputs of two separate 9DB1904 devices driven by a single main clock. The 9DB1904's must
be set to high bandwidth. Differential phase jitter is the accumulation of the phase jitter not shared by the outputs (eg. not including
the affects of spread spectrum). Target ranges of consideration are agents with BW of 1-22MHz and 11-33MHz.
11
t is the period of the input clock
12
Differential spread spectrum tracking error is the difference in spread spectrum tracking between two 9DB1904 devices This
parameter is measured at the outputs of two separate 9DB1904 devices driven by a single main clock in Spread Spectrum mode.
The 9DB1904's must be set to high bandwidth. The spread spectrum characteristics are: maximum of 0.5%, 30-33KHz modulation
frequency, linear profile.
13
This parameter is an absolute value. It is not a double-sided figure.
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
1607C—04/19/11
8
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
Electrical Characteristics - Phase Jitter Parameters
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER
Phase Jitter, PLL Mode
SYMBOL
tjphPCIeG1
tjphPCIeG2
t jphQPI_SMI
tjphPCIeG1
Additive Phase Jitter,
Bypass mode
tjphPCIeG2
t jphQPI_SMI
1
2
CONDITIONS
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
MIN
TYP
35
MAX
86
1.2
3
2.5
3.1
0.30
0.5
3
10
0.01
0.3
0.8
1.3
0.12
0.3
UNITS
ps (p-p)
ps
(rms)
ps
(rms)
ps
(rms)
ps (p-p)
ps
(rms)
ps
(rms)
ps
(rms)
Notes
1,2,3
1,2
1,2
1,5
1,2,3
1,2,6
1,2,6
1,5,6
Applies to all outputs.
See http://www.pcisig.com for complete specs
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4
Subject to final radification by PCI SIG.
5
Calculated from Intel-supplied Clock Jitter Tool v 1.6.3
6
For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)^2 = (total jittter)^2 - (input jitter)^2
Clock Periods - Differential Outputs with Spread Spectrum Disabled
SSC OFF
Center
Freq.
MHz
DIF
100.00
133.33
Measurement Window
1us
0.1s
0.1s
0.1s
+ ppm
-SSC
- ppm
0 ppm
-c2c jitter
Long-Term
Short-Term Long-Term
Period
AbsPer
Average
Average
Average
Nominal
Min
Max
Min
Min
9.94900
9.99900
10.00000
10.00100
7.44925
7.49925
7.50000
7.50075
1 Clock
1us
+SSC
Short-Term
Average
Max
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.05100
7.55075
ns
ns
1,2
1,2
Clock Periods - Differential Outputs with Spread Spectrum Enabled
SSC ON
Center
Freq.
MHz
DIF
99.75
133.00
Measurement Window
1us
0.1s
0.1s
0.1s
+ ppm
- ppm
-SSC
0 ppm
-c2c jitter
Long-Term
Short-Term Long-Term
Period
AbsPer
Average
Average
Average
Nominal
Min
Max
Min
Min
9.94906
9.99906
10.02406
10.02506
10.02607
7.44930
7.49930
7.51805
7.51880
7.51955
1 Clock
1us
+SSC
Short-Term
Average
Max
10.05107
7.53830
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.10107
7.58830
ns
ns
1,2
1,2
1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK410B+/CK420BQ
accuracy requirements. The 9DB1904 itself does not contribute to ppm error.
2
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
1607C—04/19/11
9
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
DIF Reference Clock
Common Recommendations for Differential Routing
L1 length, route as non-coupled 50ohm trace
L2 length, route as non-coupled 50ohm trace
L3 length, route as non-coupled 50ohm trace
Rs
Rt
Dimension or Value
0.5 max
0.2 max
0.2 max
33
49.9
Unit
inch
inch
inch
ohm
ohm
Figure
1
1
1
1
1
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max
L4 length, route as coupled stripline 100ohm differential trace
1.8 min to 14.4 max
inch
inch
1
1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max
L4 length, route as coupled stripline 100ohm differential trace
0.225 min to 12.6 max
inch
inch
2
2
Figure 1: Down Device Routing
L2
L1
Rs
L4
L4'
L2'
L1'
Rs
HCSL Output Buffer
Rt
Rt
L3'
PCI Express
Down Device
REF_CLK Input
L3
Figure 2: PCI Express Connector Routing
L2
L1
Rs
L4
L4'
L2'
L1'
HCSL Output Buffer
Rs
Rt
Rt
L3'
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
PCI Express
Add-in Board
REF_CLK Input
L3
1607C—04/19/11
10
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
Alternative Termination for LVDS and other Common Differential Signals (figure 3)
Vdiff
Vp-p
Vcm
R1
R2
R3
R4
Note
0.45v
0.22v
1.08
33
150
100
100
0.58
0.28
0.6
33
78.7
137
100
0.80
0.40
0.6
33
78.7
none
100
ICS874003i-02 input compatible
0.60
0.3
1.2
33
174
140
100
Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Figure 3
L2
L1
R3
R1a
L4
R4
L4'
L2'
L1'
R1b
HCSL Output Buffer
R2a
R2b
L3'
Down Device
REF_CLK Input
L3
Cable Connected AC Coupled Application (figure 4)
Component
Value
Note
R5a, R5b
8.2K 5%
R6a, R6b
1K 5%
Cc
0.1 µF
Vcm
0.350 volts
Figure 4
3.3 Volts
R5a
R5b
R6a
R6b
Cc
L4
L4'
Cc
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
PCIe Device
REF_CLK Input
1607C—04/19/11
11
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
9DB1904 SMBus Address Mapping
when using CK410/CK410B, 9FG1200, and
9DB403/803
SMB_A(2:0) = 000
SMB Adr: D0
OR
SMB_A(2:0) = 000
SMB Adr: D0
9FG1201
(DB1200G)
OR
SMB_A(2:0) = 001
SMB Adr: D2
9FG1201
(DB1200G)
OR
SMB_A(2:0) = 010
SMB Adr: D4
9FG1201
(DB1200G)
OR
SMB_A(2:0) = 011
SMB Adr: D6
9FG1201
(DB1200G)
OR
SMB_A(2:0) = 100
SMB Adr: D8
9FG1201
(DB1200G)
OR
SMB_A(2:0) = 101
SMB Adr: DA
9FG1201
(DB1200G)
OR
SMB_A(2:0) = 110
SMB Adr: DC
9FG1201
(DB1200G)
OR
SMB_A(2:0) = 111
SMB Adr: DE
9FG1201
(DB1200G)
PLL BYPASS MODE
SMB_A2_PLLBYP# = 0
9DB1904
SMB_A(2:0) = 001
SMB Adr: D2
9DB1904
SMB_A(2:0) = 010
SMB Adr: D4
9DB1904
SMB_A(2:0) = 011
SMB Adr: D6
9DB1904
SMB_A(2:0) = 100
SMB Adr: D8
9DB1904
PLL ZDB MODE
SMB_A2_PLLBYP# = 1
SMB_A(2:0) = 101
SMB Adr: DA
9DB1904
SMB_A(2:0) = 110
SMB Adr: DC
9DB1904
SMB_A(2:0) = 111
SMB Adr: DE
9DB1904
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
OR
SMB Adr: D2
932S421
CK410B
OR
SMB Adr: DC
9DB403/803
(DB400/800)
1607C—04/19/11
12
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
General SMBus serial interface information for the 9DB1904B
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D4(h)
IDT clock will acknowledge
Controller (host) sends the begining byte location = N
IDT clock will acknowledge
Controller (host) sends the data byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D4(h)*
WR
WRite
Controller (host) will send start bit.
Controller (host) sends the write address D4 (h)
IDT clock will acknowledge
Controller (host) sends the begining byte
location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D5 (h)
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N + X -1
IDT clock sends Byte 0 through byte X (if X(h)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Controller (Host)
T
starT bit
Slave Address D4(h)*
WR
WRite
IDT (Slave/Receiver)
IDT (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D5(h)*
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
Byte N + X - 1
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
Not acknowledge
stoP bit
1607C—04/19/11
13
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
SMBusTable: Reserved Register
Byte 0
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBusTable: Output Control Register
Byte 1
Pin #
Name
DIF_7
Bit 7
DIF_6
Bit 6
DIF_5
Bit 5
DIF_4
Bit 4
DIF_3
Bit 3
DIF_2
Bit 2
DIF_1
Bit 1
DIF_0
Bit 0
Control Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
R
R
R
R
R
R
R
R
0
1
PWD
1
1
1
1
1
0
1
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
SMBusTable: Output and PLL BW Control Register
0
1
Pin #
Name
Control Function
Type
Byte 2
see note
PLL_BW# adjust
Low BW
RW
High BW
Bit 7
see note
BYPASS# test mode / PLL
PLL
RW
Bypass
Bit 6
DIF_13
Output Control
RW
Hi-Z
Enable
Bit 5
DIF_12
Output Control
RW
Hi-Z
Enable
Bit 4
DIF_11
Output Control
RW
Hi-Z
Enable
Bit 3
DIF_10
Output Control
RW
Hi-Z
Enable
Bit 2
DIF_9
Output Control
RW
Hi-Z
Enable
Bit 1
DIF_8
Output Control
RW
Hi-Z
Enable
Bit 0
Note: Bit 7 is wired OR to the HIGH_BW# input, any 0 selects High BW
Note: Bit 6 is wired OR to the SMB_A2_PLLBYP# input, any 0 selects Fanout Bypass mode
SMBusTable: Output Enable Readback Register
Pin #
Name
Control Function
Byte 3
Readback - OE9# Input
Bit 7
Readback - OE8# Input
Bit 6
Readback - OE7# Input
Bit 5
Readback - OE6# Input
Bit 4
Readback - OE5# Input
Bit 3
Readback - OE_01234# Input
Bit 2
8
Readback - HIGH_BW# In
Bit 1
72
Readback - SMB_A2_PLLBYP# In
Bit 0
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
Type
R
R
R
R
R
R
R
R
0
1
Readback
Readback
Readback
Readback
Readback
Readback
Readback
Readback
PWD
1
1
1
1
1
1
1
1
PWD
X
X
X
X
X
X
X
X
1607C—04/19/11
14
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
SMBusTable: Output Enable Readback Register
Byte 4
Pin #
Name
Control Function
Readback - OE17_18# Input
69
Bit 7
60
Readback - OE15_16# Input
Bit 6
Reserved
Bit 5
54
Readback - OE14# Input
Bit 4
51
Readback - OE13# Input
Bit 3
Readback - OE12# Input
48
Bit 2
Readback - OE11# Input
43
Bit 1
40
Readback - OE10# Input
Bit 0
Type
R
R
0
Type
R
R
R
R
R
R
R
R
0
-
SMBusTable: DEVICE ID (194 Decimal or C2 Hex)
Pin #
Name
Control Function
Byte 6
Device ID 7 (MSB)
Bit 7
Device ID 6
Bit 6
Device ID 5
Bit 5
Device ID 4
Bit 4
Device ID 3
Bit 3
Device ID 2
Bit 2
Device ID 1
Bit 1
Device ID 0
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Type
RW
RW
RW
Writing to this register
RW
configures how many
RW
bytes will be read back.
RW
RW
RW
0
-
Control Function
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
PWD
X
X
0
X
X
X
X
X
1
-
PWD
0
0
0
1
0
0
0
1
1
PWD
1
1
0
0
0
0
1
0
1
-
PWD
0
0
0
0
0
1
1
1
Readback
Readback
Readback
Readback
Readback
R
R
R
R
R
SMBusTable: Vendor & Revision ID Register
Byte 5
Pin #
Name
Control Function
RID3
Bit 7
RID2
Bit 6
REVISION ID
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VENDOR ID
VID1
Bit 1
VID0
Bit 0
SMBusTable: Byte Count Register
Pin #
Name
Byte 7
BC7
Bit 7
BC6
Bit 6
BC5
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
1
Readback
Readback
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1607C—04/19/11
15
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
SMBusTable: Control Pin Readback Register
Byte 8
Pin #
Name
Control Function
Bit 7
5
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Readback -100M_133M#_LV
DIF_18
DIF_17
DIF_16
DIF_15
DIF_14
Type
0
Readback
R
RESERVED
RESERVED
Output Control
Output Control
Output Control
Output Control
Output Control
SMBusTable: PLL Operating Set Point Register
Byte 9
Pin #
Name
Control Function
RESERVED
Bit 7
RESERVED
Bit 6
RESERVED
Bit 5
RESERVED
Bit 4
RESERVED
Bit 3
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Enable
Enable
Enable
Enable
Enable
Type
0
1
-
Frequency Select 100M_133M#
RW
Bit 1
Bit 0
-
Frequency Select B
Frequency Select A
RW
RW
PWD
Latch
RW
RW
RW
RW
RW
Bit 2
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
1
See ICS9DB1904 1:1
PLL Programming Table
X
X
1
1
1
1
1
PWD
0
0
0
0
0
Latch
0
1
1607C—04/19/11
16
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
(Ref. )
Seating Plane
(N D - 1)x e
(Ref. )
A1
Index Area
ND & NE
Even
A3
N
L
N
Anvil
Singulation
1
2
E2
OR
E
(N E - 1)x e
E2
(Ref. )
2
Sawn
Singulation
Top View
e (Typ.)
2 If N D & N
E
are Even
1
b
(Ref.)
A
D
e
D2
2
ND & NE
Odd
Thermal
Base
D2
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
C
0.08
C
THERMALLY ENHANCED, VERY THIN, FINE PITCH
QUAD FLAT / NO LEAD PLASTIC PACKAGE
DIMENSIONS
SYMBOL
A
A1
A3
b
e
MIN.
MAX.
0.8
1.0
0
0.05
0.25 Reference
0.18
0.3
0.50 BASIC
SYMBOL
N
ND
NE
D x E BASIC
D2 MIN. / MAX.
E2 MIN. / MAX.
L MIN. / MAX.
ICS 72L
TOLERANCE
72
18
18
10.00 x 10.00
5.75 / 6.15
5.75 / 6.15
0.30/ 0.50
Ordering Information
Part / Order Number
9DB1904BKLF
9DB1904BKLFT
Shipping Packaging
Tubes
Tape and Reel
Package
72-pin MLF
72-pin MLF
Temperature
0 to +70° C
0 to +70° C
"LF" suffix to the part number are the Pb-Free configuration, RoHS compliant.
"B" is the device revision designator (will not correlate with the datasheet revision).
IDT® 19 Output Differential Buffer for PCIe Gen2 and QPI
1607C—04/19/11
17
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
Revision History
Rev.
0.1
0.2
A
B
C
Issue Date Description
7/1/2009 Initial release
7/8/2009 Updated revision ID in Byte 5
Updated electrical characteristics tables.
9/21/2010 Added Test loads and terminations
Corrected minor typo's, move to release.
1. Updated electrical char tables
9/23/2010 2. Updated test loads and termination figures
3. Added Period PPM tables
1. Updated electrical tabels with Typ. Values
4/19/2011 2. Updated Differential Clock Period PPM tables
Page #
13
Various
Various
Various
Innovate with IDT and accelerate your future networks. Contact:
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For Sales
For Tech Support
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408-284-8200
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408-284-6578
pcclockhelp@idt.com
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Europe
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Phone: 44-1372-363339
Fax: 44-1372-378851
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18
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