9DB233AFILF

DATASHEET 9DB233 TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 Description Features/Benefits The 9DB233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9DB233 suitable for Express Card applications. • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in Recommended Application • • downstream PLL's Spread Spectrum Compatible; tracks spreading input clock for low EMI SMBus Interface; allows control of PLL BW and Mode Key Specifications • Cycle-to-cycle jitter < 50 ps • Output-to-output skew < 50 ps • PCIe Gen3 phase jitter < 1.0ps RMS 2 output PCIe Gen3 zero-delay/fanout buffer Output Features • 2 - 0.7V current mode differential HCSL output pairs Block Diagram OE0# OE1# DIF_0 SRC_IN SRC_IN# SPREAD COMPATIBLE PLL DIF_1 PLL_BW SMBDAT SMBCLK CONTROL LOGIC IREF IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 1 9DB233 OCTOBER 20, 2016 9DB233 TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 PLL_BW SRC_IN SRC_IN# vOE0# VDD GND DIF_0 DIF_0# VDD SMBDAT 1 2 3 4 5 6 7 8 9 10 9DB233 Pin Configuration 20 19 18 17 16 15 14 13 12 11 VDDA GNDA IREF vOE1# VDD GND DIF_1 DIF_1# VDD SMBCLK Note: Pins preceeded by ' v ' have internal 120K ohm pull down resistors Power Distribution Table Pin Number VDD GND 5,9,12,16 6,15 9 6 20 19 20 19 Description Differential Outputs SMBUS IREF Analog VDD & GND for PLL core IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 2 9DB233 OCTOBER 20, 2016 9DB233 TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 Pin Descriptions PIN # PIN NAME PIN TYPE IN DESCRIPTION 3.3V input for selecting PLL Band Width 0 = low, 1= high 0.7 V Differential SRC TRUE input 0.7 V Differential SRC COMPLEMENTARY input 1 PLL_BW 2 3 SRC_IN IN SRC_IN# IN 4 vOE0# IN Active low input for enabling DIF pair 0. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 5 6 7 8 9 10 11 12 13 14 15 16 VDD GND DIF_0 DIF_0# VDD SMBDAT SMBCLK VDD DIF_1# DIF_1 GND VDD PWR PWR OUT OUT PWR I/O IN PWR OUT OUT PWR PWR Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential Complementary clock output Power supply, nominal 3.3V Data pin of SMBUS circuitry, 5V tolerant Clock pin of SMBUS circuitry, 5V tolerant Power supply, nominal 3.3V 0.7V differential Complementary clock output 0.7V differential true clock output Ground pin. Power supply, nominal 3.3V 17 vOE1# IN Active low input for enabling DIF pair 1. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 18 IREF OUT 19 20 GNDA VDDA PWR PWR This pin establishes the reference for the differential current-mode output pairs. It requires a fixed precision resistor to ground. 475ohm is the standard value for 100ohm differential impedance. Other impedances require different values. See data sheet. Ground pin for the PLL core. 3.3V power for the PLL core. Note: Pins preceeded by ' v ' have internal 120K ohm pull down resistors IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 3 9DB233 OCTOBER 20, 2016 9DB233 TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9DB233. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PARAMETER SYMBOL 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Input Low Voltage Input High Voltage Input High Voltage VDDA VDD VIL VIH VIHSMB Storage Temperature Junction Temperature Input ESD protection Ts Tj ESD prot CONDITIONS MIN TYP MAX 4.6 4.6 GND-0.5 Except for SMBus interface SMBus clock and data pins VDD+0.5V 5.5V -65 Human Body Model 150 125 2000 UNITS NOTES V V V V V ° C °C V 1,2 1,2 1 1 1 1 1 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. Electrical Characteristics–DIF_IN Clock Input Parameters TAMB=TCOM or TIND unless otherwise indicated, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER Input Crossover Voltage DIF_IN Input Swing - DIF_IN Input Slew Rate - DIF_IN SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES VCROSS Cross Over Voltage 150 375 900 mV VSWING Differential value 300 mV 1 dv/dt Measured differentially 1 8 V/ns 1,2 1 Input Leakage Current IIN VIN = VDD , VIN = GND -5 5 uA Input Duty Cycle dtin Measurement from differential wavefrom 45 55 % 1 Input Jitter - Cycle to Cycle J DIFIn Differential Measurement 0 125 ps 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 Slew rate measured through +/-75mV window centered around differential zero Electrical Characteristics–Current Consumption TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS Operating Supply Current I DD3.3OP IDD3.3PD IDD3.3PDZ All outputs active @100MHz, CL = Full load; All diff pairs driven All differential pairs tri-stated Powerdown Current MIN TYP MAX 70 80 N/A N/A UNITS NOTES mA 1 mA mA 1 1 1 Guaranteed by design and characterization, not 100% tested in production. IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 4 9DB233 OCTOBER 20, 2016 9DB233 TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 Electrical Characteristics–Input/Supply/Common Parameters TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN Ambient Operating Temperature TCOM TIND 0 -40 70 85 °C °C 1 1 Input High Voltage VIH 2 VDD + 0.3 V 1 Input Low Voltage VIL Commmercial range Industrial range Single-ended inputs, except SMBus, low threshold and tri-level inputs Single-ended inputs, except SMBus, low threshold and tri-level inputs Single-ended inputs, VIN = GND, VIN = VDD GND - 0.3 0.8 V 1 -5 5 uA 1 Single-ended inputs VIN = 0 V; Inputs with internal pull-up resistors VIN = VDD; Inputs with internal pull-down resistors -200 200 uA 1 VDD = 3.3 V, Bypass mode VDD = 3.3 V, 100MHz PLL mode 10 33 CINDIF_IN Logic Inputs, except DIF_IN DIF_IN differential clock inputs 1.5 1.5 110 110 7 5 2.7 MHz MHz nH pF pF 2 2 1 1 1,4 COUT Output pin capacitance 6 pF 1 Clk Stabilization TSTAB From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock 1.8 ms 1,2 Input SS Modulation Frequency fMODIN Allowable Frequency (Triangular Modulation) 30 33 kHz 1 OE# Latency tLATOE# 1 3 cycles 1,3 Tdrive_PD# t DRVPD 300 us 1,3 Tfall Trise SMBus Input Low Voltage SMBus Input High Voltage SMBus Output Low Voltage SMBus Sink Current Nominal Bus Voltage SCLK/SDATA Rise Time SCLK/SDATA Fall Time SMBus Operating Frequency tF tR DIF start after OE# assertion DIF stop after OE# deassertion DIF output enable after PD# de-assertion Fall time of control inputs Rise time of control inputs VILSMB VIHSMB VOLSMB IPULLUP VDDSMB t RSMB tFSMB 5 5 0.8 @ I PULLUP @ VOL 3V to 5V +/- 10% (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) 5.5 1000 300 ns ns V V V mA V ns ns 1,2 1,2 1 1 1 1 1 1 1 f MAXSMB Maximum SMBus operating frequency 100 kHz 1,5 I IN Input Current Input Frequency Pin Inductance Capacitance I INP Fibyp Fipll Lpin CIN TYP 100.00 0.800 2.1 4 2.7 MAX VDDSMB 0.4 UNITS NOTES 1 Guaranteed by design and characterization, not 100% tested in production. Control input must be monotonic from 20% to 80% of input swing. 3 Time from deassertion until outputs are >200 mV 4 DIF_IN input 2 5 The differential input clock must be running for the SMBus to be active IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 5 9DB233 OCTOBER 20, 2016 9DB233 TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 Electrical Characteristics–DIF 0.7V Current Mode Differential Outputs TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP Slew rate Slew rate matching Trf ∆Trf Scope averaging on Slew rate matching, Scope averaging on 0.6 2 4.2 4 20 Voltage High VHigh 660 791 850 Voltage Low VLow Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) Max Voltage Min Voltage Vswing Crossing Voltage (abs) Crossing Voltage (var) Vmax Vmin Vswing Vcross_abs ∆-Vcross Measurement on single ended signal using absolute value. (Scope averaging off) Scope averaging off Scope averaging off Scope averaging off MAX UNITS NOTES V/ns % 1, 2, 3 1, 2, 4 1 mV -150 13 150 801 5 1557 367 46 1150 -300 300 250 550 140 1 mV mV mV mV 1 1 1, 2 1, 5 1, 6 Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475Ω (1%), I REF = 2.32mA. IOH = 6 x I REF and VOH = 0.7V @ ZO=50Ω (100Ω differential impedance). 1 2 Measured from differential waveform 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute. Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX 2 0.4 45 2.2 0.5 0.6 48 4 1 1.5 55 UNITS NOTES MHz MHz dB % 1 1 1 1 PLL Bandwidth BW PLL Jitter Peaking Duty Cycle tJPEAK tDC -3dB point in High BW Mode -3dB point in Low BW Mode Peak Pass band Gain Measured differentially, PLL Mode Duty Cycle Distortion tDCD Measured differentially, Bypass Mode @100MHz -2 0.4 2 % 1,4 Jitter, Cycle to cycle tjcyc-cyc Bypass Mode, VT = 50% Hi BW PLL Mode VT = 50% VT = 50% PLL mode Additive Jitter in Bypass Mode 2500 -50 Skew, Output to Output tpdBYP t pdPLL t sk3 3660 136 16 29 0.2 4500 350 50 50 50 ps ps ps ps ps 1 1 1 1,3 1,3 Skew, Input to Output 1 Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. I OH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. 3 Measured from differential waveform 4 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 2 IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 6 9DB233 OCTOBER 20, 2016 9DB233 TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 Electrical Characteristics–PCIe Phase Jitter Parameters TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Phase Jitter, PLL Mode SYMBOL t jphPCIeG1 t jphPCIeG2 t jphPCIeG3 t jphPCIeG1 Additive Phase Jitter, Bypass Mode t jphPCIeG2 t jphPCIeG3 CONDITIONS PCIe Gen 1 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) PCIe Gen 1 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) MIN TYP 34 MAX 86 1 3 2 3.1 1 1 2 5 0.2 0.3 0.1 0.2 0.1 0.2 UNITS Notes ps (p-p) 1,2,3 ps 1,2 (rms) ps 1,2 (rms) ps 1,2,4 (rms) ps (p-p) 1,2,3 ps 1,2 (rms) ps 1,2 (rms) ps 1,2,4 (rms) 1 Applies to all outputs. See http://www.pcisig.com for complete specs 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 4 Subject to final ratification by PCI SIG. 2 IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 7 9DB233 OCTOBER 20, 2016 9DB233 TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, route as non-coupled 50ohm trace 0.5 max L2 length, route as non-coupled 50ohm trace 0.2 max L3 length, route as non-coupled 50ohm trace 0.2 max Rs 33 Rt 49.9 Unit inch inch inch ohm ohm Figure 1 1 1 1 1 Down Device Differential Routing L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch inch 1 1 Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch inch 2 2 Figure 1: Down Device Routing L2 L1 Rs L4 L4' L2' L1' Rs HCSL Output Buffer Rt Rt L3' PCI Express Down Device REF_CLK Input L3 Figure 2: PCI Express Connector Routing L2 L1 Rs L4 L4' L2' L1' HCSL Output Buffer Rs Rt Rt L3' IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 PCI Express Add-in Board REF_CLK Input L3 8 9DB233 OCTOBER 20, 2016 9DB233 TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Figure 3 L2 L1 R3 R1a L4 R4 L4' L2' L1' R1b HCSL Output Buffer R2a R2b L3' Down Device REF_CLK Input L3 Cable Connected AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 µF Vcm 0.350 volts Figure 4 3.3 Volts R5a R5b R6a R6b Cc L4 L4' Cc IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 PCIe Device REF_CLK Input 9 9DB233 OCTOBER 20, 2016 9DB233 TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 General SMBus Serial Interface Information for 9DB233 How to Write How to Read • • • • • • • • • • • • • • • • • • • • • Controller (host) sends a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N+X-1 IDT clock will acknowledge each byte one at a time Controller (host) sends a Stop bit Index Block Write Operation Controller (Host) T Index Block Read Operation IDT (Slave/Receiver) Controller (Host) starT bit T Slave Address WR • • • Controller (host) will send a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N+X-1 IDT clock sends Byte 0 through Byte X (if X(H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit IDT (Slave/Receiver) starT bit Slave Address WRite ACK WR WRite ACK Beginning Byte = N ACK Beginning Byte = N ACK Data Byte Count = X ACK RT Slave Address Beginning Byte N ACK O O RD ReaD ACK X Byte O Repeat starT O Data Byte Count=X O O ACK ACK ACK Beginning Byte N Byte N + X - 1 stoP bit X Byte P O O O O O O Read Address Write Address D5(H) D4(H) IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 Byte N + X - 1 N Not acknowledge P stoP bit 10 9DB233 OCTOBER 20, 2016 9DB233 TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 SMBus Table: Device Control Register, READ/WRITE ADDRESS (D5/D4) Byte 0 Pin # Name Control Function Type 0 PLL Functions Enables SMBus controlled by SW_EN Control of bite 1 RW Bit 7 SMBus and 0 registers RESERVED RW Bit 6 RESERVED RW Bit 5 RESERVED RW Bit 4 RESERVED RW Bit 3 RESERVED RW Bit 2 Selects PLL RW Low BW PLL BW #adjust Bit 1 Bandwidth PLL bypassed Bypasses PLL for RW PLL Enable Bit 0 (fan out mode) board test SMBus Table: Output Enable Register Byte 1 Pin # Name Control Function Type RESERVED RW Bit 7 RESERVED RW Bit 6 RESERVED RW Bit 5 RESERVED RW Bit 4 RESERVED RW Bit 3 RESERVED RW Bit 2 RESERVED RW Bit 1 RESERVED RW Bit 0 0 0 0 - 11 1 High BW 1 PLL enabled (ZDB mode) 1 1 Default X X X X X X X X 1 Default X X X X X X X X 1 - Default 0 0 0 1 0 0 0 1 - SMBus Table: Vendor & Revision ID Register Byte 3 Pin # Name Control Function Type RID3 R Bit 7 RID2 R Bit 6 REVISION ID RID1 R Bit 5 RID0 R Bit 4 VID3 R Bit 3 VID2 R Bit 2 VENDOR ID VID1 R Bit 1 VID0 R Bit 0 Default X X X X X - SMBus Table: Function Select Register Byte 2 Pin # Name Control Function Type RESERVED RW Bit 7 RESERVED RW Bit 6 RESERVED RW Bit 5 RESERVED RW Bit 4 RESERVED RW Bit 3 RW RESERVED Bit 2 RESERVED RW Bit 1 RESERVED RW Bit 0 IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 1 PLL Functions controlled by device pins 9DB233 OCTOBER 20, 2016 9DB233 TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 SMBus Table: DEVICE ID Byte 4 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Control Function Type R R R Device ID R R = 06 Hex R R R 0 1 Default 0 0 0 0 0 1 1 0 - SMBus Table: Byte Count Register Pin # Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - Name Control Function Type 0 1 Default BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Writing to this register will configure how many bytes will be read back, default is 06 = 6 bytes. RW RW RW RW RW RW RW RW - - 0 0 0 0 0 1 1 0 IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 12 9DB233 OCTOBER 20, 2016 9DB233 TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 Marking Diagrams 20-pin SSOP 9DB233AFLF LOT YYWW 9DB233AFILF LOT YYWW 20-pin TSSOP ICS LOT YYWW 9DB233AIL ICS LOT YYWW 9DB233AGL Notes: 1. “LOT” is the lot number. 2. “YYWW” is the last two digits of the year and week that the part was assembled. 3. “L” or “LF” denotes RoHS compliant package. 4. “I” denotes industrial temperature. 5. Bottom marking: country of origin if not USA. IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 13 9DB233 OCTOBER 20, 2016 9DB233 TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Wide Body) Millimeters 20 Symbol E1 A A1 A2 b c D E E1 e L  aaa E INDEX AREA 1 2 D A A2 Min Max 1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 8.55 8.75 5.80 6.20 3.80 4.00 .635 Basic 0.40 1.27 0 8 -0.10 A1 Inches Min Max 0.053 0.069 0.004 0.010 -0.059 0.008 0.012 0.007 0.010 0.337 0.344 0.228 0.244 0.150 0.157 .025 Basic 0.016 0.050 0 8 -0.004 c -Ce b SEATING PLANE  L aaa C IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 14 9DB233 OCTOBER 20, 2016 9DB233 TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 Package Outline and Package Dimensions (20-pin TSSOP, 4.4mm Narrow Body) Millimeters 20 Symbol E1 INDEX AREA A A1 A2 b C D E E1 e L  aaa E 1 2 D Max Min -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 6.40 6.60 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10 Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.252 0.260 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004 *For reference only. Controlling dimensions in mm. A A2 Min Inches* A1 c - Ce SEATING PLANE b  L aaa C Ordering Information Part / Order Number Shipping Packaging 9DB233AFLF Tubes 9DB233AFLFT Tape and Reel 9DB233AFILF Tubes 9DB233AFILFT Tape and Reel 9DB233AGLF Tubes 9DB233AGLFT Tape and Reel 9DB233AGILF Tubes 9DB233AGILFT Tape and Reel Package 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP Temperature 0 to +70°C 0 to +70°C -40 to +85°C -40 to +85°C 0 to +70°C 0 to +70°C -40 to +85°C -40 to +85°C "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. “A” is the device revision designator (will not correlate with the datasheet revision). While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 15 9DB233 OCTOBER 20, 2016 9DB233 TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 Revision History Rev. A B C Who RDW RDW RDW Issue Date 6/30/2010 7/12/2010 4/14/2011 D RDW 4/9/2012 E F Description Released to final 1. Changed PWD to Default in SMBus tables. Changed pull down indicator from '**' to ' v '. Page # 10,11 1. Updated typical electrical characteristics to reflect improved performance 3-6 1. Corrected typo for Read/Write address from D4/D5 to D5/D4 respectively. RDW 2/19/2014 Various 2. Added device marking diagrams. RDW 10/20/2016 Updated input clock electrical table to latest format. No change to form, fit or function of the device IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 16 4 9DB233 OCTOBER 20, 2016 9DB233 TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/support Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. 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