8 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
9DBU0831
DATASHEET
Description
Features/Benefits
The 9DBU0831 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. The device has 8 output enables for clock
management and 3 selectable SMBus addresses.
• LP-HCSL outputs; save 16 resistors compared to standard
•
Recommended Application
•
1.5V PCIe Gen1-2-3 Zero Delay/Fanout Buffer (ZDB/FOB)
Output Features
•
• 8 – 1-167MHz Low-Power (LP) HCSL DIF pairs
•
•
Key Specifications
•
•
•
•
•
DIF cycle-to-cycle jitter 10MHz
200
250
N/A
fs
(rms)
1,6
tjph125M1
125MHz, 12KHz to 20MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
313
350
N/A
fs
(rms)
1,6
1
Guaranteed by design and characterization, not 100% tested in production.
2
See http://www.pcisig.com for complete specs
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4
For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]
5
Driven by 9FGU0831 or equivalent
6
Rohde&Schartz SMA100
8 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB
8
REVISION C 04/22/15
9DBU0831 DATASHEET
Additive Phase Jitter Plot: 125M (12kHz to 20MHz)
RMS additive jitter: 313fs
REVISION C 04/22/15
9
8 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB
9DBU0831 DATASHEET
General SMBus Serial Interface Information
How to Write
How to Read
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
•
•
•
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
T
Index Block Read Operation
IDT (Slave/Receiver)
Controller (Host)
starT bit
T
Slave Address
WR
IDT (Slave/Receiver)
starT bit
Slave Address
WRite
WR
WRite
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
Data Byte Count = X
RT
ACK
Slave Address
Beginning Byte N
RD
ACK
O
O
ACK
O
Data Byte Count=X
O
ACK
O
Beginning Byte N
Byte N + X - 1
ACK
ACK
P
ReaD
stoP bit
X Byte
X Byte
O
Repeat starT
O
O
O
O
O
O
Note: SMBus Address is Latched on SADR pin.
8 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB
Byte N + X - 1
10
N
Not acknowledge
P
stoP bit
REVISION C 04/22/15
9DBU0831 DATASHEET
SMBus Table: Output Enable Register 1
Byte 0
Name
Control Function
Type
0
DIF OE7
Output Enable
RW
Low/Low
Bit 7
DIF OE6
Output Enable
RW
Low/Low
Bit 6
DIF OE5
Output Enable
RW
Low/Low
Bit 5
DIF OE4
Output Enable
RW
Low/Low
Bit 4
DIF OE3
Output Enable
RW
Low/Low
Bit 3
DIF OE2
Output Enable
RW
Low/Low
Bit 2
DIF OE1
Output Enable
RW
Low/Low
Bit 1
DIF OE0
Output Enable
RW
Low/Low
Bit 0
1. A low on these bits will overide the OE# pin and force the differential output Low/Low
SMBus Table: PLL Operating Mode and Output Amplitude Control Register
Byte 1
Name
Control Function
Type
PLLMODERB1
PLL Mode Readback Bit 1
Bit 7
R
PLLMODERB0
PLL
Mode
Readback
Bit
0
Bit 6
R
Bit 5
PLLMODE_SWCNTRL
Enable SW control of PLL Mode RW
PLLMODE1
PLL Mode Control Bit 1
Bit 4
PLLMODE0
PLL Mode Control Bit 0
Bit 3
Reserved
Bit 2
AMPLITUDE 1
Bit 1
Controls Output Amplitude
AMPLITUDE 0
Bit 0
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: DIF Slew Rate Control Register
Byte 2
Name
Control Function
SLEWRATESEL DIF7
Adjust Slew Rate of DIF7
Bit 7
SLEWRATESEL DIF6
Adjust Slew Rate of DIF6
Bit 6
SLEWRATESEL DIF5
Adjust Slew Rate of DIF5
Bit 5
SLEWRATESEL DIF4
Adjust Slew Rate of DIF4
Bit 4
SLEWRATESEL DIF3
Adjust Slew Rate of DIF3
Bit 3
SLEWRATESEL DIF2
Adjust Slew Rate of DIF2
Bit 2
SLEWRATESEL DIF1
Adjust Slew Rate of DIF1
Bit 1
SLEWRATESEL DIF0
Adjust Slew Rate of DIF0
Bit 0
Note: See "Low-Power HCSL Outputs" table for slew rates.
SMBus Table: Frequency Select Control Register
Byte 3
Name
Control Function
Reserved
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
Reserved
Bit 3
Reserved
Bit 2
Reserved
Bit 1
SLEWRATESEL FB
Adjust Slew Rate of FB
Bit 0
1
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Default
1
1
1
1
1
1
1
1
1
Default
Latch
Latch
0
See PLL Operating Mode Table
Values in B1[7:6]
set PLL Mode
Values in B1[4:3]
set PLL Mode
RW 1
RW 1
See PLL Operating Mode Table
RW
RW
00 = 0.55V
10 = 0.7V
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Type
0
RW
Slow Setting
01= 0.65V
11 = 0.8V
Fast
Fast
Fast
Fast
Fast
Fast
Fast
Fast
0
0
0
1
1
0
1
Setting
Setting
Setting
Setting
Setting
Setting
Setting
Setting
Default
1
1
1
1
1
1
1
1
1
Default
1
1
0
0
Fast Setting
0
1
1
1
Byte 4 is Reserved and reads back 'hFF
REVISION C 04/22/15
11
8 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB
9DBU0831 DATASHEET
SMBus Table: Revision and Vendor ID Register
Byte 5
Name
Control Function
RID3
Bit 7
RID2
Bit 6
Revision ID
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VENDOR ID
VID1
Bit 1
VID0
Bit 0
Type
R
R
R
R
R
R
R
R
SMBus Table: Device Type/Device ID
Byte 6
Name
Device Type1
Bit 7
Device Type0
Bit 6
Device ID5
Bit 5
Device ID4
Bit 4
Device ID3
Bit 3
Device ID2
Bit 2
Device ID1
Bit 1
Device ID0
Bit 0
Type
R
R
R
R
R
R
R
R
SMBus Table: Byte Count Register
Byte 7
Name
Bit 7
Bit 6
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
8 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB
Control Function
Device Type
Device ID
Control Function
Reserved
Reserved
Reserved
Byte Count Programming
12
Type
RW
RW
RW
RW
RW
0
1
Default
0
0
0
1
0
0
0
1
A rev
0001 = IDT
0
1
00 = FGx, 01 = DBx ZDB/FOB,
10 = DMx, 11= DBx FOB
001000 binary or 08 hex
0
Default
0
1
0
0
1
0
0
0
1
Default
0
0
0
0
Writing to this register will configure how
1
many bytes will be read back, default is
0
= 8 bytes.
0
0
REVISION C 04/22/15
9DBU0831 DATASHEET
Marking Diagrams
ICS
DBU0831AL
YYWW
COO
LOT
ICS
BU0831AIL
YYWW
COO
LOT
Notes:
1. “LOT” is the lot sequence number.
2. “COO” denotes country of origin.
3. YYWW is the last two digits of the year and week that the part was assembled.
4. Line 2: truncated part number
5. “L” denotes RoHS compliant package.
6. “I” denotes industrial temperature range device.
Thermal Characteristics
PARAMETER
SYMBOL
CONDITIONS
Thermal Resistance
θJC
θJb
θJA0θ
θJA1
θJA3
θJA5
Junction to Case
Junction to Base
Junction to Air, still air
Junction to Air, 1 m/s air flow
Junction to Air, 3 m/s air flow
Junction to Air, 5 m/s air flow
PKG
NDG48
TYP
VALUE
33
2.1
37
30
27
26
UNITS
NOTES
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1
1
1
1
1
1
1
ePad soldered to board
REVISION C 04/22/15
13
8 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB
9DBU0831 DATASHEET
Package Outline and Package Dimensions (NDG48) – use EPAD Option P1
8 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB
14
REVISION C 04/22/15
9DBU0831 DATASHEET
Package Outline and Package Dimensions (NDG48) – use EPAD 4.2 mm SQ
REVISION C 04/22/15
15
8 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB
9DBU0831 DATASHEET
Ordering Information
Part / Order Number Shipping Packaging
9DBU0831AKLF
Trays
9DBU0831AKLFT
Tape and Reel
9DBU0831AKILF
Trays
9DBU0831AKILFT
Tape and Reel
Package
48-pin VFQFPN
48-pin VFQFPN
48-pin VFQFPN
48-pin VFQFPN
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
Revision History
Rev.
A
B
C
Issue Date Initiator Description
1. Updated electrical tables with char data.
2. Added an additive phase jitter plot.
RDW
7/14/2014
3. Added 12kHz to 20MHz additive phase jitter spec.
4. Updated Amplitude control bit descriptions in Byte 1.
Updated SMBus Input High/Low parameters conditions, MAX values, and
RDW
9/19/2014
footnotes.
1. Updated Key Specifications to be consistent acrosss the family.
2. Updated pin out and pin descriptions to show ePad on package
RDW
4/17/2015 connected to ground.
3. Updated Clock Input Parameters table to be consistent with PCIe
Vswing parameter.
8 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB
16
Page #
Various
6
1-6
REVISION C 04/22/15
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Tech Support
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1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com
email: clocks@idt.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
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