9EX21801AKLFT

DATASHEET 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux Description Features/Benefits The 9EX21801 provides 18 output clocks for PCIe Gen2 (100MHz) or QPI (133MHz) applications. The 9EX21801 has 4 selectable SMBus addresses, and dedicated CKPWRGD/PD# and VDDA pins for easy board design. A differential CPU clock from a CK410B+ main clock generator, such as the 932S421, drives the 9EX21801. In fanout mode, the 9EX21801 provides outputs up to 400MHz. • • • • • 9EX21801A Supports output clock frequencies up to 400 MHz 4 Selectable SMBus addresses SMBus address is independent of PLL operating mode Dedicated CKPWRGD/PD# and VDDA pins ease board design Available in industrial temperature range (-40°C to +85°C) Key Specifications • • • • DIF output cycle-to-cycle jitter < 50ps DIF output-to-output skew < 150 ps PCIe Gen2 compliant phase noise QPI 133MHz compliant phase noise Functional Block Diagram OE(17:15)# OE(14:5)#, OE_01234# 12 CLKA_IN CLKA_IN# PLL (SS Compatible) 18 DIF(17:0) CLKB_IN CLKB_IN# HIBW_BYPM_LOBW# 100M_133M# CKPWRGD/PD# SMB_A0 SMB_A1 SEL_A_B# SMBDAT SMBCLK Logic IREF IDT® 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463E — 07/20/11 1 9EX21801A 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux VDD OE7# DIF_7 DIF_7# OE8# DIF_8 DIF_8# HIBW_BYPM_LOBW# SMBCLK SMBDAT SMB_A1 SMB_A0 SEL_A_B# CKPWRGD/PD# DIF_9 DIF_9# OE9# Pin Configuration 100M_133M# Datasheet 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 VDD OE10# DIF_10 DIF_10# OE11# DIF_11 DIF_11# OE12# DIF_12 DIF_12# GND VDD DIF_13 DIF_13# OE13# DIF_14 DIF_14# OE14# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 9EX21801AKLF DIF_6# DIF_6 OE6# DIF_5# DIF_5 OE5# DIF_4# DIF_4 DIF_3# DIF_3 GND VDD DIF_2# DIF_2 DIF_1# DIF_1 DIF_0# DIF_0 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 OE_01234# VDD CLKB_IN# CLKB_IN GND CLKA_IN# CLKA_IN VDDA GNDA IREF DIF_17# DIF_17 DIF_16# DIF_16 OE15_17# VDD DIF_15# DIF_15 72-pin MLF Frequency/Functionality Table Power Groups Byte 0, bit 2 (100_133M# Latch) Byte 0, bit 1 FSB Byte 0, bit 0 FSA Input MHz 1 0 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 1 0 100.00 133.33 166.67 200.00 266.67 333.33 400.00 1 1 1 DIF_x MHz 100.00 133.33 166.67 200.00 266.67 333.33 400.00 Reserved Pin Number VDD GND 29 28 1,12,21,35,43,55 11,32,44 Notes 1 1 2 2 2 2 2 INPUTS CKPWRGD/PD# Input 1 Running 0 X OUTPUTS DIF_x Running Hi-Z PLL State ON OFF SMBus Address Selection (pins 66, 67) SMB_A1 0 0 1 1 HIBW_BYPM_LOBW# Selection (Pin 63) Voltage