BB101MAU-TL-E

BB101M Built in Biasing Circuit MOS FET IC UHF RF Amplifier REJ03G0822-0300 (Previous ADE-208-504A) Rev.3.00 Aug.10.2005 Features • Built in Biasing Circuit; To reduce using parts cost & PC board space. • Low noise characteristics; (NF = 2.0 dB typ. at f = 900 MHz) • Withstanding to ESD; Built in ESD absorbing diode. Withstand up to 200V at C=200pF, Rs=0 conditions. • Provide mini mold packages; MPAK-4(SOT-143Rmod) Outline RENESAS Package code: PLSP0004ZA-A (Package name: MPAK-4) 2 3 1 4 1. Source 2. Gate1 3. Gate2 4. Drain Notes: 1. Marking is “AU–”. 2. BB101M is individual type number of RENESAS BBFET. Rev.3.00 Aug 10, 2005 page 1 of 7 BB101M Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate1 to source voltage Gate2 to source voltage Drain current Channel power dissipation Channel temperature Storage temperature Symbol VDS VG1S VG2S ID Pch Tch Tstg Ratings 6 +6 –0 ±6 25 150 150 –55 to +150 Unit V V V mA mW °C °C Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Gate1 to source breakdown voltage Gate2 to source breakdown voltage Gate1 to source cutoff current Gate2 to source cutoff current Gate1 to source cutoff voltage Gate2 to source cutoff voltage Drain current Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Power gain Noise figure Symbol V(BR)DSS V(BR)G1SS V(BR)G2SS IG1SS IG2SS VG1S(off) VG2S(off) ID(op) |yfs| Ciss Coss Crss PG NF Min 6 +6 ±6 — — 0.2 0.4 10 16 1.2 0.7 — 16 — Typ — — — — — — — 15 22 1.7 1.1 0.012 20 2.0 Max — — — +100 ±100 0.8 1.0 20 — 2.2 1.5 0.03 — 3.0 Unit V V V nA nA V V mA mS pF pF pF dB dB Test conditions ID = 200 µA, VG1S = VG2S = 0 IG1 = +10 µA, VG2S = VDS = 0 IG2 = ±10 µA, VG1S = VDS = 0 VG1S = +5 V, VG2S = VDS = 0 VG2S = ±5 V, VG1S = VDS = 0 VDS = 5 V, VG2S = 4 V ID = 100 µA VDS = 5 V, VG1S = 5 V ID = 100 µA VDS = 5 V, VG1 = 5 V VG2S = 4 V, RG = 220 kΩ VDS = 5 V, VG1 = 5 V, VG2S =4 V RG = 220 kΩ, f = 1 kHz VDS = 5 V, VG1 = 5 V VG2S =4 V, RG = 220 kΩ f = 1 MHz VDS = 5 V, VG1 = 5 V VG2S =4 V, RG = 220 kΩ f = 900 MHz Rev.3.00 Aug 10, 2005 page 2 of 7 BB101M Main Characteristics Test Circuit for Operating Items (ID(op) , |yfs|, Ciss, Coss, Crss, NF, PG) VG2 Gate 2 Gate 1 RG VG1 Drain A ID Source Equivalent Circuit Gate 2 Drain Gate 1 Source Application Circuit VAGC = 4 to 0.3 V BBFET VDS = 5 V RFC Output Input RG VGG = 5 V Rev.3.00 Aug 10, 2005 page 3 of 7 BB101M Maximum Channel Power Dissipation Curve Typical Output Characteristics 25 VG2S = 4 V VG1 = V DS Channel Power Dissipation Pch (mW) 200 Drain Current ID (mA) 150 15 100 10 50 5 R 0 50 100 150 200 0 1 2 3 10 20 Ω k 20 0 k Ω 15 1 kΩ 0 18 k Ω 0 22 k Ω 0 27 k Ω 330 k Ω 390 0 kΩ = 47 G 0 kΩ 4 5 Ambient Temperature Ta (°C) Drain to Source Voltage VDS (V) Drain Current vs. Gate2 to Source Voltage 25 VDS = VG1 = 5 V Drain Current vs. Gate1 Voltage 20 VDS = 5 V RG = 150 kΩ Drain Current ID (mA) Drain Current ID (mA) 20 15 10 5 kΩ Ω 00 2 0 k 11 kΩ 150 k Ω 0 18 kΩ 220 kΩ 270 kΩ 330 k Ω 390 kΩ 470 RG = 16 4 12 V 3 V 2V 8 4 VG2S = 1 V 1 2 3 4 5 0 1 2 3 4 5 0 Gate2 to Source Voltage VG2S (V) Gate1 Voltage VG1 (V) Drain Current vs.Gate1 Voltege 20 VDS = 5 V RG = 220 k Ω 20 Drain Current vs.Gate1 Voltege VDS = 5 V RG = 390 k Ω 12 4V 3V 2V Drain Current ID (mA) Drain Current ID (mA) 16 16 12 8 8 4V 3V 2V VG2S = 1 V 4 VG2S = 1 V 4 0 1 2 3 4 5 0 1 2 3 4 5 Gate1 Voltage VG1 (V) Gate1 Voltage VG1 (V) Rev.3.00 Aug 10, 2005 page 4 of 7 BB101M Forward Transfer Admittance vs. Gate1 Voltage Forward Transfer Admittance |yfs| (mS) 25 Forward Transfer Admittance vs. Gate1 Voltage Forward Transfer Admittance |yfs| (mS) 25 VDS = 5 V RG = 220 kΩ 20 f = 1 kHz 15 VDS = 5 V RG = 150 kΩ 20 f = 1 kHz 4V 3V 4V 3V 15 2V 2V 10 10 5 VG2S = 1 V 0 1 2 3 4 5 5 VG2S = 1 V 0 1 2 3 4 5 Gate1 Voltage VG1 (V) Gate1 Voltage VG1 (V) Forward Transfer Admittance vs. Gate1 Voltage Forward Transfer Admittance |yfs| (mS) 25 VDS = 5 V RG = 390 kΩ f = 1 kHz 30 25 Power Gain vs. Gate Resistance 20 Power Gain PG (dB) 4V 3V 20 15 10 5 0 50 15 2V 10 5 VG2S = 1 V 0 1 2 3 4 5 VDS = 5 V VG1 = 5 V VG2S = 4 V f = 900 MHz 100 200 500 1000 2000 5000 Gate1 Voltage VG1 (V) Gate Resistance RG (kΩ) Noise Figure vs. Gate Resistance 4 30 25 Power Gain vs. Drain Current Noise Figure NF (dB) Power Gain PG (dB) 3 20 15 10 5 VDS = 5 V VG1 = 5 V VG2S = 4 V RG = variable f = 900 MHz 5 10 15 20 25 30 2 1 0 50 VDS = 5 V VG1 = 5 V VG2S = 4 V f = 900 MHz 100 200 500 1000 2000 5000 0 Gate Resistance RG (kΩ) Drain Current ID (mA) Rev.3.00 Aug 10, 2005 page 5 of 7 BB101M Noise Figure vs. Drain Current 4 30 25 Drain Current vs. Gate Resistance Noise Figure NF (dB) 3 Drain Current ID (mA) 20 15 10 5 0 10 VDS = 5 V VG1 = 5 V VG2S = 4 V 30 100 300 1000 3000 10000 2 VDS = 5 V VG1 = 5 V VG2S = 4 V RG = variable f = 900 MHz 5 10 15 20 25 30 1 0 Drain Current ID (mA) Gain Reduction vs. Gate2 to Source Voltage 40 4 VDS = 5 V VG1 = 5 V VG2S = 4 V RG = 220 kΩ f = 900 MHz Gate Resistance RG (kΩ) Input Capacitance vs. Gate2 to Source Voltage VDS = 5 V VG1 = 5 V RG = 220 kΩ f = 1 MHz Input Capacitance Ciss (pF) Gain Reduction GR (dB) 30 3 20 2 10 1 0 1 2 3 4 5 0 1 2 3 4 5 Gate2 to Source Voltage VG2S (V) Gate2 to Source Voltage VG2S (V) Output Capacitance vs. Gate2 to Source Voltage 4 Output Capacitance Coss (pF) 3 VDS = 5 V VG1 = 5 V RG = 220 kΩ f = 1 MHz 2 1 0 1 2 3 4 5 Gate2 to Source Voltage VG2S (V) Rev.3.00 Aug 10, 2005 page 6 of 7 BB101M Package Dimensions JEITA Package Code SC-61AA RENESAS Code PLSP0004ZA-A Package Name MPAK-4 / MPAK-4V MASS[Typ.] 0.013g D e2 b1 B B e A Q c E HE Reference Symbol Dimension in Millimeters L A A xM S A b L1 A3 e2 LP e A2 A I1 b5 yS A1 S e1 b b2 c c1 c b1 b3 c1 I1 b4 A-A Section B-B Section Pattern of terminal position areas A A1 A2 A3 b b1 b2 b3 c c1 D E e e2 HE L L1 LP x y b4 b5 e1 I1 Q Min 1.0 0 1.0 0.35 0.55 Nom 0.1 2.7 1.35 1.1 0.25 0.42 0.62 0.4 0.6 0.13 0.11 1.5 0.95 0.85 2.8 Max 1.3 0.1 1.2 0.5 0.7 0.15 3.1 1.65 2.2 0.35 0.15 0.25 3.0 0.75 0.55 0.65 0.05 0.05 0.55 0.75 1.05 1.95 0.3 Ordering Information Part Name BB101MAU-TL-E Quantity 3000 Shipping Container φ 178 mm Reel, 8 mm Emboss Taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.3.00 Aug 10, 2005 page 7 of 7 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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