EL5177IYZ-T7

DATASHEET EL5177 FN7344 Rev 6.00 August 28, 2012 550MHz Differential Twisted-Pair Driver Features The EL5177 is a high bandwidth amplifier with an output in differential form. It is primarily targeted for applications such as driving twisted-pair lines or any application where common mode injection is likely to occur. The input signal can be in either single-ended or differential form but the output is always in differential form. • Fully differential inputs, outputs, and feedback • Differential input range ±2.3V • 550MHz 3dB bandwidth • 1100V/µs slew rate On the EL5177, two feedback inputs provide the user with the ability to set the device gain (stable at a minimum gain of 1). • Low distortion at 20MHz • Single 5V or dual ±5V supplies The output common mode level is set by the reference pin (REF), which has a -3dB bandwidth of 110MHz. Generally, this pin is grounded but it can be tied to any voltage reference. • 40mA maximum output current • Low power, 12.5mA typical supply current Both outputs (OUT+, OUT-) are short circuit protected to withstand temporary overload condition. • Pb-free (RoHS compliant) The EL5177 is available in the 10 Ld MSOP package and is specified for operation over the full -40°C to +85°C temperature range. • Twisted-pair drivers Applications • Differential line drivers See also EL5174 (EL5177 in 8 Ld MSOP). • VGA over twisted-pair • ADSL/HDSL drivers • Single-ended to differential amplification • Transmission of analog signals in a noisy environment Pinout EL5177 (10 LD MSOP) TOP VIEW FBP 1 10 OUT+ IN+ 2 REF 3 IN- 4 FBN 5 FN7344 Rev 6.00 August 28, 2012 9 VS+ - 8 VS+ 7 EN 6 OUT- Page 1 of 12 EL5177 Pin Descriptions PIN NUMBER PIN NAME PIN DESCRIPTION 1 FBP Non-inverting feedback input; resistor RF1 must be connected from this pin to VOUT 2 IN+ Non-inverting input 3 REF Output common-mode control; the common-mode voltage of VOUT will follow the voltage on this pin 4 IN- Inverting input 5 FBN Inverting feedback input; resistor RF2 must be connected from this pin to VOUT 6 OUT- Inverting output 7 EN Enabled when this pin is floating or the applied voltage  VS+ -1.5 8 VS+ Positive supply 9 VS- Negative supply 10 OUT+ Non-inverting output Ordering Information PART NUMBER (Notes 1, 2, 3) EL5177IYZ PART MARKING BAAKA PACKAGE (Pb-free) 10 Ld MSOP (3.0mm) PKG. DWG. # M10.118A NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for EL5177. For more information on MSL please see tech brief TB363. FN7344 Rev 6.00 August 28, 2012 Page 2 of 12 EL5177 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V VIN, VINB, VREF . . . . . . . . . . . . . . . . . . . VS- + 0.8V (min) to VS+ - 0.8V (max) VIN - VINB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 Supply Voltage Rate-of-rise (dV/dT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs Input Voltage (IN+, IN- to VS+, VS-) . . . . . . . . . . . . . VS- - 0.3V to VS+ + 0.3V Differential Input Voltage (IN+ to IN-). . . . . . . . . . . . . . . . . . . . . . . . . . ±4.8V Maximum Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA Recommended Operating Temperature . . . . . . . . . . . . . . . -40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+135°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications Specified. PARAMETER VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RLD = 1k, RF = 0, RG = OPEN, CLD = 2.7pF, Unless Otherwise DESCRIPTION CONDITIONS MIN (Note 4) TYP MAX (Note 4) UNIT AC PERFORMANCE BW -3dB Bandwidth AV = 1, CLD = 2.7pF 550 MHz AV = 2, RF = 500, CLD = 2.7pF 130 MHz AV = 10, RF = 500, CLD = 2.7pF 20 MHz 120 MHz 1100 V/µs 10 ns 20 ns 200 MHz BW ±0.1dB Bandwidth AV = 1, CLD = 2.7pF SR Slew Rate VOUT = 3VP-P, 20% to 80% tSTL Settling Time to 0.1% VOUT = 2VP-P tOVR Output Overdrive Recovery Time GBWP Gain Bandwidth Product VREFBW (-3dB) VREF -3dB Bandwidth AV =1, CLD = 2.7pF 110 MHz VREFSR+ VREF Slew Rate - Rise VOUT = 2VP-P, 20% to 80% 134 V/µs VREFSR- VREF Slew Rate - Fall VOUT = 2VP-P, 20% to 80% 70 V/µs VN Input Voltage Noise at 10kHz 21 nV/Hz IN Input Current Noise at 10kHz 2.7 pA/Hz HD2 Second Harmonic Distortion VOUT = 2VP-P, 5MHz -95 dBc VOUT = 2VP-P, 20MHz -94 dBc VOUT = 2VP-P, 5MHz -88 dBc VOUT = 2VP-P, 20MHz -87 dBc HD3 Third Harmonic Distortion 800 dG Differential Gain at 3.58MHz RLD = 300, AV = 2 0.06 % d Differential Phase at 3.58MHz RLD = 300, AV = 2 0.13 ° INPUT CHARACTERISTICS VOS Input Referred Offset Voltage IIN Input Bias Current (VIN+, VIN-) IREF Input Bias Current (VREF) RIN Differential Input Resistance CIN Differential Input Capacitance DMIR Differential Mode Input Range CMIR+ Common Mode Positive Input Range at VIN+, VIN- FN7344 Rev 6.00 August 28, 2012 ±1.4 ±25 mV -30 -14 -7 µA 0.5 2.3 4 µA ±2.1 150 k 1 pF ±2.3 3.4 ±2.5 V V Page 3 of 12 EL5177 Electrical Specifications Specified. (Continued) PARAMETER VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RLD = 1k, RF = 0, RG = OPEN, CLD = 2.7pF, Unless Otherwise DESCRIPTION CONDITIONS CMIR- Common Mode Negative Input Range at VIN+, VIN- VREFIN+ Positive Reference Input Voltage Range VIN+ = VIN- = 0V VREFIN- Negative Reference Input Voltage Range VIN+ = VIN- = 0V VREFOS Output Offset Relative to VREF CMRR Input Common Mode Rejection Ratio VIN = ±2.5V Gain Gain Accuracy MIN (Note 4) 3.4 TYP MAX (Note 4) UNIT -4.3 V 3.7 V -3.3 -3 V ±50 ±100 mV 65 78 dB VIN = 1V 0.980 0.995 ±3.6 ±3.8 V 35 50 mA 1.010 V OUTPUT CHARACTERISTICS VOUT Output Voltage Swing RL = 500 to GND IOUT+(Max) Maximum Source Output Current IOUT-(Max) Maximum Sink Output Current RL = 10 VIN+ = 1.1V, VIN- = -1.1V, VREF = 0 ROUT Output Impedance -40 -30 130 mA m SUPPLY VSUPPLY Supply Operating Range IS(ON) Power Supply Current - Per Channel IS(OFF)+ Positive Power Supply Current - Disabled IS(OFF)- Negative Power Supply Current - Disabled PSRR Power Supply Rejection Ratio VS+ to VS- 4.75 10 EN pin tied to 4.8V VS from ±4.5V to ±5.5V 11 V 12.5 14 mA 76 120 µA -200 -120 µA 60 75 dB ns ENABLE tEN Enable Time 130 1.2 tDS Disable Time VIH EN Pin Voltage for Power-Up VIL EN Pin Voltage for Shutdown IIH-EN EN Pin Input Current High At VEN = 5V IIL-EN EN Pin Input Current Low At VEN = 0V µs VS+ -1.5 VS+ -0.5 V 40 -6 V -2.5 50 µA µA NOTE: 4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. FN7344 Rev 6.00 August 28, 2012 Page 4 of 12 EL5177 Connection Diagram RF1 VREF 0 RS3 50 INP 1 FBP RS1 RG 50 OPEN INN- OUT+ 10 2 IN+ VS- 9 -5V 3 REF VS+ 8 +5V 4 IN- RS2 50 OUT+ RLD 1k EN EN 7 5 FBN OUT- OUT- 6 RF2 0 Typical Performance Curves AV = 1, RLD = 1k, CLD = 2.7pF RLD = 1k, CLD = 2.7pF 4 4 MAGNITUDE (dB) NORMALIZED MAGNITUDE (dB) 3 2 VOP-P = 200mV 1 0 -1 -2 VOP-P = 1V -3 -4 -5 -6 1M 10M 100M 3 2 1 AV = 1 0 -1 -3 AV = 10 -5 FREQUENCY (Hz) AV = 1, CLD = 2.7pF 3 CLD = 23pF CLD = 34pF 4 2 0 CLD = 9pF -2 -4 2 MAGNITUDE (dB) MAGNITUDE (dB) 6 CLD = 2.7pF 0 -1 -3 -8 -5 100M FREQUENCY (Hz) FIGURE 3. FREQUENCY RESPONSE vs CLD 1G RLD = 500 -2 -4 10M RLD= 1k 1 -6 FN7344 Rev 6.00 August 28, 2012 1G 4 CLD = 50pF -10 1M 100M FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS GAIN AV = 1, RLD = 1k 8 10M FREQUENCY (Hz) FIGURE 1. FREQUENCY RESPONSE 10 AV = 5 -4 -6 1M 1G AV = 2 -2 RLD= 200 -6 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 4. FREQUENCY RESPONSE vs RLD Page 5 of 12 EL5177 Typical Performance Curves (Continued) AV = 2, RLD = 1k, CLD = 2.7pF AV = 2, CLD = 2.7pF, RF = 750 10 10 9 9 RF = 1k 8 7 MAGNITUDE (dB) MAGNITUDE (dB) 8 6 5 RF = 500 4 RF = 200 3 7 5 2 1 100M RLD = 200 3 2 10M RLD = 500 4 1 0 1M RLD = 1k 6 0 1M 400M 10M FREQUENCY (Hz) FIGURE 5. FREQUENCY RESPONSE 0 -10 3 -20 2 -30 PSRR (dB) MAGNITUDE (dB) 4 1 0 -1 -2 -40 -60 -3 -4 -80 1M 10M PSRR- -50 -70 -5 100k PSRR+ -90 10k 100M 1M 100k 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 8. PSRR vs FREQUENCY FIGURE 7. FREQUENCY RESPONSE - VREF 100 1k VOLTAGE NOISE (nV/Hz), CURRENT NOISE (pA/Hz) 80 CMRR (dB) 400M FIGURE 6. FREQUENCY RESPONSE vs RLD 5 60 40 20 0 -20 1k 100M FREQUENCY (Hz) 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 9. CMRR vs FREQUENCY FN7344 Rev 6.00 August 28, 2012 1G 100 EN 10 IN 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 10. VOLTAGE AND CURRENT NOISE vs FREQUENCY Page 6 of 12 EL5177 Typical Performance Curves (Continued) VS = ±5V, AV = 1, RLD = 1k 100 -40 HD3 (f = 5MHz) DISTORTION (dB) IMPEDANCE () -50 10 1 -60 HD3 (f = 20MHz) -70 -80 -90 0.1 10k 100k 10M 1M -100 1.0 100M HD2 (f = 20MHz) HD2 (f = 5MHz) 1.5 2.0 2.5 FREQUENCY (Hz) 3.0 3.5 4.0 4.5 5.0 VOP-P, DM (V) FIGURE 11. OUTPUT IMPEDANCE vs FREQUENCY FIGURE 12. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE VS = ±5V, AV = 1, VOP-P, DM = 1V VS = ±5V, AV = 2, RLD = 1k -50 -40 -55 -60 DISTORTION (dB) DISTORTION (dB) -50 -60 HD3 (f = 20MHz) -70 -80 H D3 z) 1 2 3 5 4 HD2 (f = 5MHz) 6 8 7 9 -40 -50 HD3 (f = 20MHz) DISTORTION (dB) DISTORTION (dB) HD3 (f = 5MHz) -70 -75 -80 HD2 (f = 20MHz) -95 300 400 500 600 700 RLD () 800 900 FIGURE 15. HARMONIC DISTORTION vs RLD FN7344 Rev 6.00 August 28, 2012 200 20M (f = 5 HD3 Hz ) (f = 5 HD3 (f = 2 0MH z) MHz ) MHz) 300 400 500 600 RLD () 1000 800 700 900 1000 VS = ±5V, RLD = 1k, VOP-P, DM = 1V for AV = 1, VOP-P, DM = 2V for AV = 2 HD3 (AV = 2) -60 HD -70 -80 -100 2 (A V HD3 (AV H -90 HD2 (f = 5MHz) -100 200 HD2 (f = -50 -60 -90 HD2 -85 FIGURE 14. HARMONIC DISTORTION vs RLD VS = ±5V, AV = 2, VOP-P, DM = 2V -85 -80 -100 100 10 FIGURE 13. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE -65 -75 -95 VOP-P, DM (V) -55 -70 -90 Hz) HD2 (f = 20M -90 -100 (f H = 5M -65 0 10 20 30 40 FREQUENCY (MHz) ( D2 AV =2 ) = 1) =1 ) 50 60 FIGURE 16. HARMONIC DISTORTION vs FREQUENCY Page 7 of 12 EL5177 Typical Performance Curves (Continued) 50mV/DIV 0.5V/DIV 10ns/DIV 10ns/DIV FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE FIGURE 18. LARGE SIGNAL TRANSIENT RESPONSE M = 400ns, CH1 = 200mV/DIV, CH2 = 5V/DIV M = 400ns, CH1 = 500mV/DIV, CH2 = 5V/DIV CH1 CH1 CH2 CH2 400ns/DIV 400ns/DIV FIGURE 20. DISABLED RESPONSE FIGURE 19. ENABLED RESPONSE 0.6 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.0 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 486mW POWER DISSIPATION (W) POWER DISSIPATION (W) 0.9 0.5 MSOP8/10 0.4 JA = +206°C/W 0.3 0.2 0.1 0 870mW 0.8 MSOP8/10 0.7 JA = +115°C/W 0.6 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 AMBIENT TEMPERATURE (°C) FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN7344 Rev 6.00 August 28, 2012 125 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (°C) FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Page 8 of 12 EL5177 Simplified Schematic VS+ R1 IN+ IN- R3 R2 FBP R4 R7 R8 FBN VB1 OUT+ RCD REF RCD VB2 CC R9 OUT- R10 CC R5 R6 VS- Description of Operation and Application Information Product Description The EL5177 is a wide bandwidth, low power and single/differential ended to differential output amplifier. It can be used as single/differential ended to differential converter. The EL5177 is internally compensated for closed loop gain of +1 or greater. Connected in gain of 1 and driving a 1k differential load, the EL5177 has a -3dB bandwidth of 550MHz. Driving a 200 differential load at gain of 2, the bandwidth is about 130MHz. The EL5177 is available with a power-down feature to reduce the power while the amplifier is disabled. Input, Output, and Supply Voltage Range The EL5177 has been designed to operate with a single supply voltage of 5V to 10V or a split supplies with its total voltage from 5V to 10V. The amplifiers have an input common mode voltage range from -4.3V to 3.4V for ±5V supply. The differential mode input range (DMIR) between the two inputs is from -2.3V to +2.3V. The input voltage range at the REF pin is from -3.3V to 3.7V. If the input common mode or differential mode signal is outside the above-specified ranges, it will cause the output signal to become distorted. The output of the EL5177 can swing from -3.8V to +3.8V at a 1k differential load at ±5V supply. As the load resistance becomes lower, the output swing is reduced. Differential and Common Mode Gain Settings The voltage applied at REF pin can set the output common mode voltage and the gain is one. The differential gain is set by the RF and RG network. FN7344 Rev 6.00 August 28, 2012 The gain setting for EL5177 is expressed in Equation 1: R F1 + R F2  V ODM =  V IN + – V IN -    1 + ---------------------------- RG   2R F  V ODM =  V IN + – V IN -    1 + ----------- RG   (EQ. 1) V OCM = V REF Where: RF1 = RF2 = RF RF1 FBP VIN+ VINVREF RG VO+ IN+ INREF VO- FBN RF2 FIGURE 23. Choice of Feedback Resistor and Gain Bandwidth Product For applications that require a gain of +1, no feedback resistor is required. Just short the OUT+ pin to FBP pin and OUT- pin to FBN pin. For gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier's phase margin is reduced. This causes ringing in the time domain and peaking in the frequency domain. Therefore, RF has some maximum value that should not be exceeded for optimum performance. If a large value of RF must be used, a small capacitor in the few Pico farad range in parallel with RF can help to reduce the ringing and peaking at the expense of reducing the bandwidth. Page 9 of 12 EL5177 The bandwidth of the EL5177 depends on the load and the feedback network. RF and RG appear in parallel with the load for gains other than +1. As this combination gets smaller, the bandwidth falls off. Consequently, RF also has a minimum value that should not be exceeded for optimum bandwidth performance. For gain of +1, RF = 0 is optimum. For the gains other than +1, optimum response is obtained with RF between 500 to 1k. The EL5177 has a gain bandwidth product of 200MHz for RLD = 1k. For gains 5, its bandwidth can be predicted by Equation 2: Gain  BW = 200MHz (EQ. 2) need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to Equation 3: T JMAX – T AMAX PD MAX = -------------------------------------------- JA (EQ. 3) Where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature JA = Thermal resistance of the package Driving Capacitive Loads and Cables The EL5177 can drive a 23pF differential capacitor in parallel with a 1k differential load with less than 5dB of peaking at gain of +1. If less peaking is desired in applications, a small series resistor (usually between 5 to 50) can be placed in series with each output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than 1, the gain resistor RG can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking. Disable/Power-Down The EL5177 can be disabled and its outputs placed in a high impedance state. The turn-off time is about 1.2µs and the turnon time is about 130ns. When disabled, the amplifier's supply current is reduced to 1.7µA for IS+ and 120µA for IS- typically, thereby effectively eliminating the power consumption. The amplifier's power-down can be controlled by standard CMOS signal levels at the EN pin. The applied logic signal is relative to VS+ pin. Letting the EN pin float or applying a signal that is less than 1.5V below VS+ will enable the amplifier. The amplifier will be disabled when the signal at the EN pin is above VS+ - 0.5V. Output Drive Capability The EL5177 has internal short circuit protection. Its typical short circuit current is ±40mA. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds ±40mA. This limit is set by the design of the internal metal interconnect. Power Dissipation With the high output drive capability of the EL5177, it is possible to exceed the +135°C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types FN7344 Rev 6.00 August 28, 2012 The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: V O  PD = i   V STOT  I SMAX +  V STOT – V O   ------------ R LD   (EQ. 4) Where: VSTOT = Total supply voltage = VS+ - VSISMAX = Maximum quiescent supply current per channel VO = Maximum differential output voltage of the application RLD = Differential load resistance ILOAD = Load current i = Number of channels By setting the two PDMAX equations equal to each other, we can solve the output current and RLD to avoid the device overheat. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire-wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. As the signal is transmitted through a cable, the high frequency signal will be attenuated. One way to compensate this loss is to boost the high frequency gain at the receiver side. Page 10 of 12 EL5177 Typical Applications RF FBP 50 TWISTED PAIR IN+ IN+ RT RG IN- EL5177 EL5175 50 REF ZO = 100 FBN VO INREF RF RFR RGR FIGURE 24. TWISTED PAIR CABLE RECEIVER RF GAIN (dB) FBP RT 75 RGC VO+ IN+ RG IN- CL REF VO- FBN fL RF 2R F DC Gain = 1 + ----------RG 1 f L  ------------------------2R G C C 2R F  HF Gain = 1 + -------------------------R G  R GC 1 f H  ----------------------------2R GC C C fH FREQUENCY FIGURE 25. TRANSMIT EQUALIZER © Copyright Intersil Americas LLC 2003-2012 All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7344 Rev 6.00 August 28, 2012 Page 11 of 12 EL5177 Package Outline Drawing M10.118A (JEDEC MO-187-BA) 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP) Rev 0, 9/09 3.0 ± 0.1 A 0.25 10 DETAIL "X" CAB 0.18 ± 0.05 SIDE VIEW 2 4.9 ± 0.15 3.0 ± 0.1 1.10 Max B PIN# 1 ID 1 2 0.95 BSC 0.5 BSC TOP VIEW Gauge Plane 0.86 ± 0.09 H 0.25 C 3°±3° SEATING PLANE 0.10 ± 0.05 0.23 +0.07/ -0.08 0.08 C A B 0.55 ± 0.15 0.10 C DETAIL "X" SIDE VIEW 1 5.80 4.40 3.00 NOTES: 0.50 0.30 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. Plastic interlead protrusions of 0.25mm max per side are not included. 4. 1.40 5. Dimensions “D” and “E1” are measured at Datum Plane “H”. TYPICAL RECOMMENDED LAND PATTERN 6. This replaces existing drawing # MDP0043 MSOP10L. FN7344 Rev 6.00 August 28, 2012 Page 12 of 12