EL5224ILZ-T7

DATASHEET EL5224, EL5324, EL5424 FN7004 Rev.4.00 Aug 28, 2017 12MHz Rail-to-Rail Buffers + 100mA VCOM Amplifier The EL5224, EL5324, and EL5424 feature 8, 10, and 12 low power buffers, respectively, and one high power output amplifier. They are designed primarily for buffering column driver reference voltages in TFT-LCD applications as well as generation of the VCOM supply. Each low power buffer features a -3dB bandwidth of 12MHz and features rail-to-rail input/output capability. The high power buffer can drive 100mA and swings to within 2V of each rail. Features The 8-channel EL5224 is available in 24 Ld QFN and 24 Ld HTSSOP packages, the 10-channel EL5324 is available in 32 Ld QFN and 28 Ld HTSSOP packages, and the 12-channel EL5424 is available in the 32 Ld QFN package. They are specified for operation across the full -40°C to +85°C temperature range. • Rail-to-rail input/output swing (buffers only) Related Literature • TFT-LCD column driver buffering and VCOM supply • For a full list of related documents, visit our website - EL5224, EL5324, EL5424 product pages • 8, 10, and 12 channel versions • 12MHz -3dB buffer bandwidth • 150mA VCOM buffer • Operating supply voltage from 4.5V to 16.5V • Low supply current - 6mA total (8-channel version) • QFN package - just 0.9mm high • Pb-free (RoHS compliant) Applications • Electronics notebooks • Computer monitors • Electronics games • Touch-screen displays • Portable instrumentation FN7004 Rev.4.00 Aug 28, 2017 Page 1 of 16 EL5224, EL5324, EL5424 Ordering Information PART NUMBER (Notes 1, 2) PACKAGE (RoHS COMPLIANT) TAPE & REEL SIZE/QTY EL5224ILZ (No longer available or supported) 24 Ld QFN - MDP0046 EL5224ILZ-T7 (No longer available or supported) 24 Ld QFN 7”/1k MDP0046 EL5224ILZ-T13 (No longer available or supported) 24 Ld QFN 13”/2.5k MDP0046 EL5224IREZ (No longer available or supported) 24 Ld HTSSOP - MDP0048 EL5224IREZ-T7 (No longer available or supported) 24 Ld HTSSOP 7”/1k MDP0048 EL5224IREZ-T13 (No longer available or supported) 24 Ld HTSSOP 13”/2.5k MDP0048 EL5324ILZ (No longer available or supported) 32 Ld QFN - L32.5x6B EL5324ILZ-T7 (No longer available or supported) 32 Ld QFN 7”/1k L32.5x6B EL5324ILZ-T13 (No longer available or supported) 32 Ld QFN 13”/2.5k L32.5x6B EL5324IREZ 28 Ld HTSSOP - MDP0048 EL5324IREZ-T7 28 Ld HTSSOP 7”/1k MDP0048 EL5324IREZ-T13 28 Ld HTSSOP 13”/2.5k MDP0048 EL5424ILZ (No longer available or supported) 32 Ld QFN - L32.5x6B EL5424ILZ-T7(No longer available or supported) 32 Ld QFN 7”/1k L32.5x6B EL5424ILZ-T13 (No longer available or supported) 32 Ld QFN 13”/2.5k L32.5x6B PKG. DWG. # NOTES: 1. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. For Moisture Sensitivity Level (MSL), see product information pages for EL5224, EL5324, EL5424. For more information on MSL, refer to TB363. FN7004 Rev.4.00 Aug 28, 2017 Page 2 of 16 EL5224, EL5324, EL5424 Pin Configurations EL5324 (28 LD HTSSOP) TOP VIEW EL5224 (24 LD HTSSOP) TOP VIEW VIN1 1 24 VOUT1 VIN1 1 28 VOUT1 VIN2 2 23 VOUT2 VIN2 2 27 VOUT2 VIN3 3 22 VOUT3 VIN3 3 26 VOUT3 21 VOUT4 VIN4 4 25 VOUT4 20 VS- VIN5 5 VIN4 4 THERMAL PAD VS+ 5 24 VOUT5 THERMAL PAD 23 VS- VIN5 6 19 VOUT5 VS+ 6 VIN6 7 18 VOUT6 VIN6 7 22 VOUT6 VIN7 8 17 VOUT7 VIN7 8 21 VOUT7 VIN8 9 16 VOUT8 VIN8 9 20 VOUT8 VSA+ 10 15 VSA- VIN9 10 19 VOUT9 VINA+ 11 14 VINA- VIN10 11 18 VOUT10 13 VOUTA VSA+ 12 17 VSA- VINA+ 13 16 VINA- NC 14 21 VOUT1 22 NC 24 VIN2 26 VOUT2* 27 VOUT1 28 VOUT0 29 NC 30 VIN0 31 VIN1 23 VIN1 EL5224 (24 LD QFN) TOP VIEW EL5324 & EL5424 (32 LD QFN) TOP VIEW 32 VIN2* 15 VOUTA 20 VOUT2 NC 12 VIN3 1 25 VOUT3 VIN3 1 19 VOUT3 VIN4 2 24 VOUT4 VIN4 2 18 VOUT4 VIN5 3 23 VOUT5 VS+ 3 15 VOUT6 VIN7 6 20 VOUT7 VIN7 6 14 VOUT7 VIN8 7 19 VOUT8 VIN8 7 13 VOUT8 VIN9 8 18 VOUT9 VIN10 9 17 VOUT10 VOUT11* 16 VSA- 15 VINA- 14 VOUTA 13 VINA+ 12 VSA+ 11 VIN11* 10 16 VOUT5 VSA- 12 VIN6 5 VINA- 11 21 VOUT6 THERMAL PAD VIN6 5 VOUTA 10 VIN5 4 VINA+ 9 22 VS- VSA+ 8 VS+ 4 17 VSTHERMAL PAD *Not available in EL5324 FN7004 Rev.4.00 Aug 28, 2017 Page 3 of 16 EL5224, EL5324, EL5424 Pin Descriptions 24 Ld HTSSOP 24 Ld QFN 32 Ld QFN 28 Ld HTSSOP PIN NAME PIN FUNCTION 1 23 31 1 VIN1 Input 2 24 32 (Note 3) 2 VIN2 Input 3 1 1 3 VIN3 Input 4 2 2 4 VIN4 Input 5 3 4 6 VS+ Power 6 4 3 5 VIN5 Input 7 5 5 7 VIN6 Input 8 6 6 8 VIN7 Input 9 7 7 9 VIN8 Input 10 8 11 12 VSA+ Power 11 9 12 13 VINA+ Positive input of VCOM 12 22 29 14 NC Not connected 13 10 13 15 VOUTA Output of VCOM 14 11 14 16 VINA- Negative input of VCOM 15 12 15 17 VSA- Power 16 13 19 20 VOUT8 Output 17 14 20 21 VOUT7 Output 18 15 21 22 VOUT6 Output 19 16 23 24 VOUT5 Output 20 17 22 23 VS- Power 21 18 24 25 VOUT4 Output 22 19 25 26 VOUT3 Output 23 20 26 (Note 3) 27 VOUT2 Output 24 21 27 28 VOUT1 Output 8 10 VIN9 Input 9 11 VIN10 Input 10 (Note 3) VIN11 Input 16 (Note 3) VOUT11 Output 17 18 VOUT10 Output 18 19 VOUT9 Output 28 VOUT0 Output 30 VIN0 Input NOTE: 3. Not available in EL5324IL FN7004 Rev.4.00 Aug 28, 2017 Page 4 of 16 EL5224, EL5324, EL5424 Absolute Maximum Ratings (TA = +25°C) Supply Voltage between VS+ and VS-. . . . . . . . . . . . . . . . . . . . . . . . . . . +18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V, VS+ +0.5V Maximum Continuous Output Current (VOUT0-9) . . . . . . . . . . . . . . . . 30mA Maximum Continuous Output Current (VOUTA) . . . . . . . . . . . . . . . . . 150mA Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: All parameters having Min/Max specifications are established. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications VS+ = +15V, VS- = 0, RL = 10kΩ, RF = RG = 20kΩ, CL = 10pF to 0V, Gain of VCOM = -1, and TA = +25°C, unless otherwise specified DESCRIPTION PARAMETER CONDITIONS MIN TYP MAX UNIT 14 mV INPUT CHARACTERISTICS (REFERENCE BUFFERS) Input Offset Voltage Average Offset Voltage Drift VOS VCM = 0V 2 TCVOS (Note 4) 5 VCM = 0V 2 Input Bias Current IB Input Impedance RIN Input Capacitance CIN Voltage Gain AV 1V VOUT 14V VOS VCM = 7.5V µV/C 50 1 1.35 0.992 nA GΩ pF 1.008 V/V 4 mV INPUT CHARACTERISTICS (VCOM BUFFER) Input Offset Voltage Average Offset Voltage Drift TCVOS 1 (Note 4) 3 VCM = 7.5V 2 Input Bias Current IB Input Impedance RIN 1 Input Capacitance CIN 1.35 Load Regulation VREG VCOM = 6V, -100mA < IL < 100mA -20 µV/C 100 nA GΩ pF +20 mV 150 mV OUTPUT CHARACTERISTICS (REFERENCE BUFFERS) Output Swing Low VOL IL = 7.5mA Output Swing High VOH IL = 7.5mA Short-Circuit Current ISC 50 14.85 14.95 V 120 140 mA OUTPUT CHARACTERISTICS (VCOM BUFFER) Output Swing Low VOL 50Ω to 7.5V Output Swing High VOH 50Ω to 7.5V Short-Circuit Current ISC 1 13.5 1.5 V 14 V 160 mA POWER SUPPLY PERFORMANCE Power Supply Rejection Ratio Total Supply Current PSRR IS Reference buffer VS from 5V to 15V 55 80 dB VCOM buffer, VS from 5V to 15V 60 100 dB EL5224 (no load) 5 6.8 8 mA EL5324 (no load) 6 7.8 9.5 mA EL5424 (no load) 7 8.8 11 mA 7 DYNAMIC PERFORMANCE (BUFFER AMPLIFIERS) Slew Rate (Note 5) SR -4V VOUT 4V, 20% to 80% Settling to +0.1% (AV = +1) tS (AV = +1), VO = 2V step 250 ns BW RL = 10kΩ, CL = 10pF 12 MHz -3dB Bandwidth FN7004 Rev.4.00 Aug 28, 2017 15 V/µs Page 5 of 16 EL5224, EL5324, EL5424 Electrical Specifications VS+ = +15V, VS- = 0, RL = 10kΩ, RF = RG = 20kΩ, CL = 10pF to 0V, Gain of VCOM = -1, and TA = +25°C, unless otherwise specified (Continued) DESCRIPTION PARAMETER Gain-Bandwidth Product CONDITIONS MIN TYP MAX UNIT GBWP RL = 10kΩ, CL = 10pF 8 MHz Phase Margin PM RL = 10kΩ, CL = 10pF 50 ° Channel Separation CS f = 5MHz 75 dB NOTES: 4. Measured across operating temperature range. 5. Slew rate is measured on rising and falling edges. Typical Performance Curves 20 VS = ±7.5V CL = 10pF 10 NORMALIZED MAGNITUDE (dB) NORMALIZED MAGNITUDE (dB) 20 10kΩ 1kΩ 0 -10 150Ω 562Ω -20 -30 100k 1M 10M 10 VS = ±7.5V RL = 10kΩ 100pF 0 -10 -20 FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS RL (BUFFER) PSRR- 40 20 0 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 3. PSRR vs FREQUENCY (BUFFER) FN7004 Rev.4.00 Aug 28, 2017 100M 600 OUTPUT IMPEDANCE (Ω) PSRR (dB) 80 60 10M FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS CL (Buffer) VS = ±7.5V PSRR+ 1M FREQUENCY (Hz) FREQUENCY (Hz) 100 12pF 47pF -30 100k 100M 1000pF 10M 480 VS = ±7.5V TA = +25°C 360 240 120 0 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 4. OUTPUT IMPEDANCE vs FREQUENCY (BUFFER) Page 6 of 16 EL5224, EL5324, EL5424 Typical Performance Curves (Continued) 80 VS = ±7.5V RL = 10kΩ VIN = 100mV 70 60 OVERSHOOT (%) VOLTAGE NOISE (nV/Hz) 100 10 50 40 30 20 10 1 10k 100k 1M 10M 0 10 100M 100 FREQUENCY (Hz) FIGURE 5. INPUT NOISE SPECIAL DENSITY vs FREQUENCY (BUFFER) 8 6 0.018 VS = ±7.5V RL = 10kΩ CL = 12pF VS = ±5V RL = 10kΩ VIN = 2VP-P 0.016 4 STEP SIZE (V) FIGURE 6. OVERSHOOT vs LOAD CAPACITANCE (BUFFER) THD + NOISE (%) 10 1K CAPACITANCE (pF) 2 0 -2 -4 -6 0.014 0.012 0.01 0.008 -8 -10 200 250 300 350 400 450 500 550 600 650 0.006 1k 10k SETTLING TIME (ns) FIGURE 7. SETTLING TIME vs STEP SIZE (BUFFER) FIGURE 8. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY (BUFFER) 4 NORMALIZED MAGNITUDE (dB) 12 10 VOP-P (V) 8 6 4 2 100k FREQUENCY (Hz) VS = ±5V RL = 10kΩ 0 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 9. OUTPUT SWING vs FREQUENCY (BUFFER) FN7004 Rev.4.00 Aug 28, 2017 AV = 5 2 AV = 1 0 -2 -4 VS = ±7.5V CL = 1µF -6 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 10. FREQUENCY RESPONSE (VCOM) Page 7 of 16 EL5224, EL5324, EL5424 Typical Performance Curves (Continued) 5mA/DIV 0mA 5mA 5mA/DIV 0mA 5mA RS = 0Ω CL = 200pF RS = 10Ω CL = 1nF 0V 500mV/DIV RS = 10Ω CL = 4.7nF RS = 10Ω CL = 1nF 0V M = 1µs/DIV VS = ±7.5V VIN = 0V M = 1µs/DIV VS = ±7.5V VIN = 0V FIGURE 11. TRANSIENT LOAD REGULATION - SOURCING (BUFFER) RS = 0Ω CL = 200pF RS = 10Ω CL = 4.7nF FIGURE 12. TRANSIENT LOAD REGULATION - SINKING (BUFFER) M = 4µs/DIV, VS = ±7.5V, VIN = 0V 0mA 500mV/DIV M = 4µs/DIV, VS = ±7.5V, VIN = 0V 100mA/DIV -100mA 100mA 0mA 0V 20mV/DIV CL = 1µF FIGURE 13. TRANSIENT LOAD REGULATION - SOURCING (VCOM) 100mA/DIV 0V 20mV/DIV CL = 1µF FIGURE 14. TRANSIENT LOAD REGULATION - SINKING (VCOM) VS = ±7.5V, RL = 10kΩCL = 12pF VS = ±7.5V 1V/DIV 50mV/DIV 200ns/DIV FIGURE 15. SMALL SIGNAL TRANSIENT RESPONSE (BUFFER) FN7004 Rev.4.00 Aug 28, 2017 1µs/DIV FIGURE 16. LARGE SIGNAL TRANSIENT RESPONSE (BUFFER) Page 8 of 16 EL5224, EL5324, EL5424 Typical Performance Curves (Continued) JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY (4-LAYER) TEST BOARD, QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 2.857W 2.5 2.703W QFN32 JA = 35°C/W 2 QFN24 JA = 37°C/W 1.5 1 0.5 0 0 25 50 JEDEC JESD51-3 AND SEMI G42-88 (SINGLE LAYER) TEST BOARD 0.8 POWER DISSIPATION (W) POWER DISSIPATION (W) 3 75 85 100 125 714mW 0.6 QFN32 JA = 132°C/W 0.5 QFN24 JA = 140°C/W 0.4 0.3 0.2 0.1 0 150 758mW 0.7 0 25 AMBIENT TEMPERATURE (°C) FIGURE 17. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD. HTSSOP EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 3.030W HTSSOP28 JA = 30°C/W HTSSOP24 JA = 33°C/W 1.5 1 0.5 0 150 1 909mW 0.9 2.5 2 125 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 3.333W 3 75 85 100 FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE POWER DISSIPATION (W) POWER DISSIPATION (W) 3.5 50 AMBIENT TEMPERATURE (°C) 0.8 833mW 0.7 HTSSOP28 JA = 110°C/W 0.6 0.5 HTSSOP24 JA = 120°C/W 0.4 0.3 0.2 0.1 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN7004 Rev.4.00 Aug 28, 2017 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Page 9 of 16 EL5224, EL5324, EL5424 Applications Information 1V Product Description The EL5224, EL5324, and EL5424 unity gain buffers and 100mA VCOM amplifier are fabricated using a high voltage CMOS process. The buffers exhibit rail-to-rail input and output capability and has low power consumption (600µA per buffer). When driving a load of 10kΩ and 12pF, the buffers have a -3dB bandwidth of 12MHz and exhibits 18V/µs slew rate. The VCOM amplifier exhibits rail-to-rail input. The output can be driving to within 2V of each supply rail. With a 1µF capacitance load, the GBWP is about 1MHz. Correct operation is ensured for a supply range of 4.5V to 16.5V. 10µs 1V VS = ±2.5V TA = +25°C VIN = 6VP-P FIGURE 22. Operation with Beyond-the-Rails Input The Use of the Buffers UNUSED BUFFERS The output swings of the buffers typically extend to within 100mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 21 shows the input and output waveforms for the device. Operation is from ±5V supply with a 10kΩ load connected to GND. The input is a 10VP-P sinusoid. The output voltage is approximately 9.985VP-P. It is recommended that any unused buffers have their inputs tied to the ground plane. 10µs VS = ±5V TA = +25°C VIN = 10VP-P 5V OUTPUT INPUT 5V FIGURE 21. Operation with Rail-to-Rail Input and Output SHORT-CIRCUIT CURRENT LIMIT The buffers will limit the short-circuit current to ±120mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds ±30mA. This limit is set by the design of the internal metal interconnects. OUTPUT PHASE REVERSAL The buffers are immune to phase reversal as long as the input voltage is limited from VS- -0.5V to VS+ +0.5V. Figure 22 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection diodes placed in the input stage of the device begin to conduct and overvoltage damage could occur. FN7004 Rev.4.00 Aug 28, 2017 DRIVING CAPACITIVE LOADS The buffers can drive a wide range of capacitive loads. As load capacitance increases, however, the -3dB bandwidth of the device will decrease and the peaking increase. The buffers drive 10pF loads in parallel with 10kΩ with just 1.5dB of peaking, and 100pF with 6.4dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5Ω and 50Ω) can be placed in series with the output. However, this will obviously reduce the gain slightly. Another method of reducing peaking is to add a snubber circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 150Ω and 10nF are typical. The advantage of a snubber is that it does not draw any DC load current or reduce the gain. The Use of VCOM Amplifier The VCOM amplifier is designed to control the voltage on the back plate of an LCD display. This plate is capacitively coupled to the pixel drive voltage which alternately cycles positive and negative at the line rate for the display. Thus, the amplifier must be capable of sourcing and sinking capacitive pulses of current, which can occasionally be quite large (a few 100mA for typical applications). A simple use of the VCOM amplifier is as a voltage follower, as illustrated in Figure 23 on page 11. Here, a voltage, corresponding to the mid-DAC potential, is generated by a resistive divider and buffered by the amplifier. The amplifier's stability is designed to be dominated by the load capacitance, thus for very short duration pulses (1, then the capacitor will not force the gain to roll off below unity, and subsequent poles can affect stability. The recommended capacitor has an ESR of 10mΩ, but to this must be added the resistance of the board trace between the capacitor and the sense connection - therefore this should be kept short, as illustrated in Figure 21, by the diagonal line to the capacitor. Also ground resistance between the capacitor and the base of R2 must be kept to a minimum. These constraints should be considered when laying out the PCB. The VCOM amplifier's output current is limited to 150mA. This limit level, which is roughly the same for sourcing and sinking, is included to maintain reliable operation of the part. It does not necessarily prevent a large temperature rise if the current is maintained. (In this case the whole chip may be shut down by the thermal trip to protect functionality.) If the display occasionally demands current pulses higher than this limit, the reservoir capacitor will provide the excess and the amplifier will top the reservoir capacitor back up once the pulse has stopped. This will happen on the µs time scale in practical systems and for pulses 2 or 3 times the current limit, the VCOM voltage will have settled again before the next line is processed. Power Dissipation With the high-output drive capability of the EL5224, EL5324, and EL5424 buffer, it is possible to exceed the +125°C “absolute-maximum junction temperature” under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the buffer to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to: T JMAX - T AMAX P DMAX = ------------------------------------------- JA where: • TJMAX = Maximum junction temperature • TAMAX = Maximum ambient temperature • JA = Thermal resistance of the package • PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or: P DMAX = i   V S  I SMAX +  V S + - V OUT i   I LOAD i  +  V SA  I SAA +  V SA + - V OUTA   I LA  when sourcing, and: P DMAX = i   V S  I SMAX +  V OUT i - V S -   I LOAD i  +  V SA  I SAA +  V SA + - V OUTA   I LA  when sinking. If the capacitor is increased above 1µF, stability is generally improved and short pulses of current will cause a smaller “perturbation” on the VCOM voltage. The speed of response of the amplifier is however degraded as its bandwidth is decreased. At capacitor values around 10µF, a subtle interaction with internal DC gain boost circuitry will decrease the phase margin and may give rise to some overshoot in the response. The amplifier will remain stable though. FN7004 Rev.4.00 Aug 28, 2017 Page 11 of 16 EL5224, EL5324, EL5424 where: • i = 1 to total number of buffers • VS = Total supply voltage of buffer • VSA = Total supply voltage of VCOM • ISMAX = Maximum quiescent current per channel • ISA = Maximum quiescent current of VCOM • VOUTi = Maximum output voltage of the application • VOUTA = Maximum output voltage of VCOM • ILOADi = Load current of buffer • ILA = Load current of VCOM If we set the two PDMAX equations equal to each other, we can solve for the RLOAD's to avoid device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if PDMAX exceeds the device's power derating curves. FN7004 Rev.4.00 Aug 28, 2017 Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- and VSA- pins are connected to ground, two 0.1µF ceramic capacitors should be placed from VS+ and VSA+ pins to ground. A 4.7µF tantalum capacitor should then be connected from VS+ and VSA+ pins to ground. One 4.7µF capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. Internally, VS+ and VSA+ are shorted together and VS- and VSA- are shorted together. To avoid high current density, the VS+ pin and VSA+ pin must be shorted in the PCB layout. Also, the VS- pin and VSA- pin must be shorted in the PCB layout. Important Note: The metal plane used for heat sinking of the device is electrically connected to the negative supply potential (VS- and VSA-). If VS- and VSA - are tied to ground, the thermal pad can be connected to ground. Otherwise, the thermal pad must be isolated from any other power planes. Page 12 of 16 EL5224, EL5324, EL5424 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure you have the latest revision. DATE REVISION Aug 28, 2017 FN7004.4 CHANGE Applied new header/footer. Updated Ordering Information table. Added Note 2. Added Revision History and About Intersil sections. Added POD L32.5X6B. Updated POD MDP0046 to the latest revision changes are as follows: -cosmetic edit added dimensions over appropriate columns. Updated POD MDP0048 to the latest revision changes are as follows: -Added dimensions (MILLIMETERS) to table About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets. For the most updated datasheet, application notes, related documentation, and related parts, see the respective product information page found at www.intersil.com. For a listing of definitions and abbreviations of common terms used in our documents, visit www.intersil.com/glossary. You can report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. © Copyright Intersil Americas LLC 2003-2017. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7004 Rev.4.00 Aug 28, 2017 Page 13 of 16 EL5224, EL5324, EL5424 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L32.5x6B (One of 10 Packages in MDP0046) 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220) A MILLIMETERS D N (N-1) (N-2) B 1 2 3 SYMBOL MIN NOMINAL MAX NOTES A 0.80 0.90 1.00 - A1 0.00 0.02 0.05 - D PIN #1 I.D. MARK E 5.00 BSC - D2 3.60 REF - E 6.00 BSC - E2 (N/2) 2X 0.075 C 2X 0.075 C 0.10 M C A B b L 0.45 b 0.20 - 0.50 0.55 - 0.22 0.24 - c 0.20 REF - e 0.50 BSC - N 32 REF 4 ND 7 REF 6 NE 9 REF 5 Rev 0 9/05 NOTES: (N-2) (N-1) N N LEADS TOP VIEW 4.60 REF L PIN #1 I.D. 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 3 2. Tiebar view shown is a non-functional feature. 1 2 3 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. 5. NE is the number of terminals on the “E” side of the package (or Y-direction). (E2) 6. ND is the number of terminals on the “D” side of the package (or X-direction). ND = (N/2)-NE. NE 5 (N/2) 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 7 (D2) BOTTOM VIEW 0.10 C e C (c) SEATING PLANE 0.08 C N LEADS & EXPOSED PAD C 2 A (L) SEE DETAIL "X" A1 SIDE VIEW N LEADS DETAIL X For the most recent package outline drawing, see L32.5x6B. FN7004 Rev.4.00 Aug 28, 2017 Page 14 of 16 EL5224, EL5324, EL5424 QFN (Quad Flat No-Lead) Package Family MDP0046 QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-220) A MILLIMETERS D N (N-1) (N-2) B 1 2 3 PIN #1 I.D. MARK E (N/2) 2X 0.075 C 2X 0.075 C N LEADS TOP VIEW 0.10 M C A B (N-2) (N-1) N b L SYMBOL QFN44 QFN38 TOLERANCE NOTES A 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 +0.03/-0.02 - b 0.25 0.25 0.23 0.22 ±0.02 - c 0.20 0.20 0.20 0.20 Reference - D 7.00 5.00 8.00 5.00 Basic - Reference 8 Basic - Reference 8 Basic - D2 5.10 3.80 5.80 3.60/2.48 E 7.00 7.00 8.00 1 2 3 6.00 E2 5.10 5.80 5.80 4.60/3.40 e 0.50 0.50 0.80 0.50 L 0.55 0.40 0.53 0.50 ±0.05 - N 44 38 32 32 Reference 4 ND 11 7 8 7 Reference 6 NE 11 12 8 9 Reference 5 MILLIMETERS PIN #1 I.D. 3 QFN32 SYMBOL QFN28 QFN24 QFN20 QFN16 A 0.90 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 0.02 +0.03/ -0.02 - b 0.25 0.25 0.30 0.25 0.33 ±0.02 - c 0.20 0.20 0.20 0.20 0.20 Reference - D 4.00 4.00 5.00 4.00 4.00 Basic - D2 2.65 2.80 3.70 2.70 2.40 Reference - (E2) (N/2) NE 5 7 (D2) BOTTOM VIEW 0.10 C e C SEATING PLANE TOLERANCE NOTES E 5.00 5.00 5.00 4.00 4.00 Basic - E2 3.65 3.80 3.70 2.70 2.40 Reference - e 0.50 0.50 0.65 0.50 0.65 Basic - L 0.40 0.40 0.40 0.40 0.60 ±0.05 - N 28 24 20 20 16 Reference 4 ND 6 5 5 5 4 Reference 6 NE 8 7 5 5 4 Reference 5 Rev 11 2/07 0.08 C N LEADS & EXPOSED PAD SEE DETAIL "X" NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Tiebar view shown is a non-functional feature. SIDE VIEW 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. (c) C 5. NE is the number of terminals on the “E” side of the package (or Y-direction). 2 A (L) A1 DETAIL X N LEADS 6. ND is the number of terminals on the “D” side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. For the most recent package outline drawing, see MDP0046. FN7004 Rev.4.00 Aug 28, 2017 Page 15 of 16 EL5224, EL5324, EL5424 HTSSOP (Heat-Sink TSSOP) Family MDP0048 HTSSOP (HEAT-SINK TSSOP) FAMILY 0.25 M C A B D MILLIMETERS A SYMBOL 14 LD 20 LD 24 LD 28 LD 38 LD TOLERANCE (N/2)+1 N PIN #1 I.D. E E1 0.20 C B A 1 2X N/2 LEAD TIPS (N/2) TOP VIEW B D1 EXPOSED THERMAL PAD E2 A 1.20 1.20 1.20 1.20 1.20 Max A1 0.075 0.075 0.075 0.075 0.075 ±0.075 A2 0.90 0.90 0.90 0.90 0.90 +0.15/-0.10 b 0.25 0.25 0.25 0.25 0.22 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 D 5.00 6.50 7.80 9.70 9.70 ±0.10 D1 3.2 4.2 4.3 5.0 7.25 Reference E 6.40 6.40 6.40 6.40 6.40 Basic E1 4.40 4.40 4.40 4.40 4.40 ±0.10 E2 3.0 3.0 3.0 3.0 3.0 Reference e 0.65 0.65 0.65 0.65 0.50 Basic L 0.60 0.60 0.60 0.60 0.60 ±0.15 L1 1.00 1.00 1.00 1.00 1.00 Reference N 14 20 24 28 38 Reference Rev. 3 2/07 NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. BOTTOM VIEW 0.05 e C H 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions “D” and “E1” are measured at Datum Plane H. SEATING PLANE 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 0.10 M C A B b 0.10 C N LEADS SIDE VIEW SEE DETAIL “X” c END VIEW L1 A A2 GAUGE PLANE 0.25 L A1 0° - 8° DETAIL X For the most recent package outline drawing, see MDP0048. FN7004 Rev.4.00 Aug 28, 2017 Page 16 of 16