DATASHEET
EL5175, EL5375
FN7306
Rev 7.00
August 25, 2010
550MHz Differential Line Receivers
The EL5175 and EL5375 are single and triple high bandwidth
amplifiers designed to extract the difference signal from noisy
environments. They are primarily targeted for applications such
as receiving signals from twisted-pair lines or any application
where common mode noise injection is likely to occur.
The EL5175 and EL5375 are stable for a gain of one and
requires two external resistors to set the voltage gain for
each channel.
The output common mode level is set by the reference pin
(VREF), which has a -3dB bandwidth of over 450MHz.
Generally, this pin is grounded but it can be tied to any
voltage reference.
The output can deliver a maximum of ±60mA and is short
circuit protected to withstand a temporary overload condition.
The EL5175 is available in the 8 Ld SOIC and 8 Ld MSOP
packages and the EL5375 in the 24 Ld QSOP package. All
are specified for operation over the full -40°C to +85°C
temperature range.
Pinouts
EL5175
(8 LD SOIC, MSOP)
TOP VIEW
FB 1
IN+ 2
IN- 3
+
-
REF 4
INP2 6
+
-
INN2 7
INN3 11
NC 12
FN7306 Rev 7.00
August 25, 2010
Applications
• Twisted-pair receivers
• Differential line receivers
• VGA over twisted-pair
• Differential to single-ended amplification
• Reception of analog signals in a noisy environment
Ordering Information
PART
NUMBER
PART
MARKING
PACKAGE
PKG.
DWG. #
5175ISZ
8 Ld SOIC (Pb-free)
(150 mil)
MDP0027
EL5175IY*
5
8 Ld MSOP (3.0mm)
MDP0043
EL5175IYZ*
(Note)
BAAAB
8 Ld MSOP (Pb-free) MDP0043
(3.0mm)
EL5375IU*
EL5375IU
24 Ld QSOP (150 mil) MDP0040
EL5375IUZ*
(Note)
EL5375IUZ
24 Ld QSOP (Pb-free) MDP0040
(150 mil)
6 VS+
23 FB1
19 VSN
*Add “-T7” or “-T13” suffix for tape and reel. Please refer to TB347
for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
17 FB2
REF3 9
INP3 10
• Pb-free available (RoHS compliant)
EL5175ISZ*
(Note)
18 NC
NC 8
• Low power, 9.6mA per channel
7 VS-
20 VSP
REF2 5
• Single 5V or dual ±5V supplies
MDP0027
21 NC
NC 4
• 60mA maximum output current
8 Ld SOIC (150 mil)
22 OUT1
INN1 3
• 900V/µs slew rate
5175IS
24 NC
+
-
• 550MHz 3dB bandwidth
EL5175IS*
EL5375
(24 LD QSOP)
TOP VIEW
INP1 2
• Differential input range ±2.3V
8 OUT
5 EN
REF1 1
Features
16 OUT2
+
-
15 EN
14 FB3
13 OUT3
Page 1 of 15
EL5175, EL5375
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Supply Voltage Rate-of-rise (dV/dT) . . . . . . . . . . . . . . . . . . . . 1V/µs
Input Voltage (IN+, IN- to VS+, VS-). . . . . . VS- - 0.3V to VS+ + 0.3V
Differential Input Voltage (IN+ to IN-) . . . . . . . . . . . . . . . . . . . . ±4.8V
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RL = 500, RF = 0, RG = OPEN, CL = 2.7pF, Unless Otherwise
Specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
-3dB Bandwidth
AV = 1, CL = 2.7pF
550
MHz
AV = 2, RF = 806, CL = 2.7pF
190
MHz
AV = 10, RF = 806, CL = 2.7pF
20
MHz
BW
± 0.1dB Bandwidth
AV = 1, CL = 2.7pF
60
MHz
SR
Slew Rate
VOUT = 3VP-P, 20% to 80%, RL = 100
600
V/µs
VOUT = 3VP-P, 20% to 80%, RL = 500
900
V/µs
VOUT = 2VP-P
10
ns
tSTL
Settling Time to 0.1%
tOVR
Output Overdrive Recovery Time
20
ns
GBWP
Gain Bandwidth Product
200
MHz
VREFBW (-3dB) VREF -3dB Bandwidth
AV = 1, CL = 2.7pF
450
MHz
VREFSR
VREF Slew Rate
VOUT = 2VP-P, 20% to 80%
1000
V/µs
VN
Input Voltage Noise
At f = 10kHz
21
nV/Hz
IN
Input Current Noise
At f = 10kHz
2.7
pA/Hz
HD2
Second Harmonic Distortion
VOUT = 1VP-P, 5MHz
-70
dBc
HD2
Second Harmonic Distortion
VOUT = 1VP-P, 5MHz
-66
dBc
HD3
Third Harmonic Distortion
VOUT = 1VP-P, 5MHz
-94
dBc
HD3
Third Harmonic Distortion
VOUT = 1VP-P, 5MHz
-84
dBc
dG
Differential Gain at 3.58MHz
RL = 150AV = 2
0.1
%
d
Differential Phase at 3.58MHz
RL = 150AV = 2
0.1
°
eS
Channel Separation (EL5375)
At f = 100kHz
90
dB
EL5175
-3
±40
mV
EL5375
-3
±30
mV
-12.5
-6
µA
INPUT CHARACTERISTICS
VOS
Input Referred Offset Voltage
IIN
Input Bias Current (VIN, VINB, VREF)
RIN
Differential Input Resistance
CIN
Differential Input Capacitance
DMIR
Differential Mode Input Range
±2.1
CMIR
Common Mode Input Range at VIN+, VIN-
-4.3
FN7306 Rev 7.00
August 25, 2010
-25
150
k
1
pF
±2.3
±2.5
V
+3.3
V
Page 2 of 15
EL5175, EL5375
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RL = 500, RF = 0, RG = OPEN, CL = 2.7pF, Unless Otherwise
Specified. (Continued)
DESCRIPTION
CONDITIONS
VREFIN+
Reference Input - Positive
VIN+ = VIN- = 0V
VREFIN-
Reference Input - Negative
VIN+ = VIN- = 0V
CMRR
Input Common Mode Rejection Ratio
VIN = ±2.5V
Gain
Gain Accuracy
MIN
TYP
3.3
3.5
-3.9
MAX
UNIT
V
-3.6
V
75
95
dB
EL5175, VIN = 1V
0.979
0.994
1.009
V
EL5375, VIN = 1V
0.977
0.992
1.007
V
Positive Output Voltage Swing
RL = 500 to GND
3.3
3.54
Negative Output Voltage Swing
RL = 500 to GND
IOUT(Max)
Maximum Output Current
RL = 10
ROUT
Output Impedance
OUTPUT CHARACTERISTICS
VOUT
-3.95
±40
V
-3.6
V
±67
mA
130
m
SUPPLY
VSUPPLY
Supply Operating Range
IS (ON)
Power Supply Current Per Channel Enabled
IS (OFF)+
Positive Power Supply Current - Disabled
IS (OFF)-
Negative Power Supply Current - Disabled
PSRR
Power Supply Rejection Ratio
VS+ to VS-
4.75
11
V
9.6
11
mA
EN pin tied to 4.8V, EL5175
80
100
µA
EN pin tied to 4.8V, EL5375
1.7
5
µA
-150
-120
-90
µA
45
56
dB
8
VS from ±4.5V to ±5.5V
ENABLE
tEN
Enable Time
80
ns
tDS
Disable Time
1.2
µs
VIH
EN Pin Voltage for Power-up
VIL
EN Pin Voltage for Shutdown
IIH-EN
EN Pin Input Current High Per Channel
At VEN = 5V
IIL-EN
EN Pin Input Current Low Per Channel
At VEN = 0V
FN7306 Rev 7.00
August 25, 2010
VS+ - 1.5
VS+ - 0.5
V
40
-10
V
-3
60
µA
µA
Page 3 of 15
EL5175, EL5375
Pin Descriptions
EL5175
EL5375
PIN NAME
PIN FUNCTION
1
FB
Feedback input
2
IN+
Non-inverting input
3
IN-
Inverting input
4
REF
5
EN
Enabled when this pin is floating or the applied voltage VS+ - 1.5
6
VS+
Positive supply voltage
7
VS-
Negative supply voltage
8
OUT
Output voltage
1, 5, 9
REF1, REF2, REF3
2, 6, 10
INP1, INP2, INP3
Non-inverting inputs
3, 7, 11
INN1, INN2, INN3
Inverting inputs
4, 8, 12, 18, 21, 24
NC
22, 16, 13
FN7306 Rev 7.00
August 25, 2010
Sets the common mode output voltage level to VREF
Reference input, controls common-mode output voltage
No connect, grounded for best crosstalk performance
OUT1, OUT2, OUT3 Non-inverting outputs
23, 17, 14
FB1, FB2, FB3
Feedback from outputs
15
EN
19
VSN
Negative supply
20
VSP
Positive supply
Enabled when this pin is floating or the applied voltage VS+ - 1.5
Page 4 of 15
EL5175, EL5375
FN7306 Rev 7.00
August 25, 2010
Connection Diagrams
RG
RF = 0
1 FB
-5V
INP
2 INP
VSN 7
INN
3 INN
VSP 6
REF
4 REF
EN 5
RS2
50
RS2
50
VOUT
OUT 8
RS3
50
RL
500
CL
2.7pF
EN
+5V
FIGURE 1. EL5175
RG
REF1
1 REF1
NC 24
INP1
2 INP1
FB1 23
INN1
3 INN1
OUT1 22
4 NC
+5V
RF
NC 21
REF2
5 REF2
VSP 20
INP2
6 INP2
VSN 19
INN2
7 INN2
NC 18
OUT1
CL1
2.7pF
RL1
500
RG
RF
8 NC
REF3
9 REF3
FB2 17
OUT2
OUT2 16
INP3
10 INP3
EN 15
INN3
11 INN3
FB3 14
RL2
500
RG
RF
Page 5 of 15
RSP1
50
RSN1
50
RSR1
50
RSP2
50
RSN2
50
RSR2
50
RSP3
50
RSN3
50
RSR3
50
12 NC
OUT3 13
-5V
ENABLE
FIGURE 2. EL5375
CL2
2.7pF
CL3
2.7pF
RL3
500
OUT3
EL5175, EL5375
Typical Performance Curves
4
4
AV = 1
RL = 100
2 CL = 2.7pF
MAGNITUDE (dB)
MAGNITUDE (dB)
AV = 1
RL = 500
2 CL = 2.7pF
VS = ±5V
0
VS = ±2.5V
-2
0
VS = ±5V
VS = ±2.5V
-2
-4
-4
-6
1M
10M
100M
-6
1M
1G
10M
FIGURE 3. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
FIGURE 4. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
5
VS = ±5V
RL = 500
2 CL = 2.7pF
VS = ±5V
RL = 500
3 AV = 1
MAGNITUDE (dB)
NORMALIZED GAIN (dB)
4
AV = 1
0
AV = 5
AV = 10
AV = 2
-4
10M
100M
CL = 10pF
1
-1
CL = 2.7pF
CL = 0pF
-5
1M
1G
10M
FREQUENCY (Hz)
CL = 15pF
NORMALIZED GAIN (dB)
MAGNITUDE (dB)
3
CL = 10pF
1
-1
CL = 2.7pF
-3
-5
1M
CL = 0pF
10M
100M
FREQUENCY (Hz)
FIGURE 7. FREQUENCY RESPONSE vs CL
FN7306 Rev 7.00
August 25, 2010
1G
FIGURE 6. FREQUENCY RESPONSE vs CL
4
VS = ± 2.5V
RL = 500
AV = 1
100M
FREQUENCY (Hz)
FIGURE 5. FREQUENCY RESPONSE vs VARIOUS GAIN
5
CL = 15pF
-3
-6
1M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
-2
100M
1G
2
VS = ±5V
RL = 500
AV = 2
CL = 2.7pF
RF = 1k
RF = 806
0
-2
RF = 500
RF = 200
-4
-6
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 8. FREQUENCY RESPONSE FOR VARIOUS RF
Page 6 of 15
EL5175, EL5375
2
RL = 500
AV = 1
CL = 2.7pF
0
GAIN (dB)
NORMALIZED GAIN (dB)
4
(Continued)
VS = ±5V
VS = ±2.5V
-2
-4
-6
1M
10M
100M
60
90
40
0
20
-90
0
-180
-20
-270
-40
10k
1G
100k
1M
10M
100M
PHASE (°)
Typical Performance Curves
-360
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. FREQUENCY RESPONSE FOR VREF
FIGURE 10. OPEN LOOP GAIN
100
30
10
PSRR (dB)
IMPEDANCE ()
10
1
-10
-30
-50
PSRR+
-70
0.1
10k
100k
1M
10M
-90
10k
100M
PSRR-
100k
FIGURE 11. OUTPUT IMPEDANCE vs FREQUENCY
100M
1k
VOLTAGE NOISE (nV/Hz),
CURRENT NOISE (pA/Hz)
100
CMRR (dB)
10M
FIGURE 12. PSRR vs FREQUENCY
120
80
60
40
20
-90
1k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 13. CMRR vs FREQUENCY
FN7306 Rev 7.00
August 25, 2010
1G
100
EN
10
IN
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 14. VOLTAGE AND CURRENT NOISE vs FREQUENCY
Page 7 of 15
EL5175, EL5375
Typical Performance Curves
(Continued)
0
-40
DISTORTION (dB)
GAIN (dB)
-20
-40
-60
VS = ±5V
f = 5MHz
RL = 500
-50
CH1 CH2, CH2 CH3
CH1 CH3
-80
-100
100k
10M
100M
HD2 (AV
-70
= 1)
HD3 (AV
-80
-100
1G
HD
1
AV
3(
=1
3
2
5
4
7
6
VOP-P (V)
FIGURE 15. CHANNEL ISOLATION vs FREQUENCY
(EL5375 ONLY)
FIGURE 16. HARMONIC DISTORTION vs OUTPUT VOLTAGE
-50
-50
-60
-70
HD2 (AV = 1)
-80
H D3
(AV =
2)
VS = ±5V
-90 f = 5MHz
HD3 (AV = 1)
VOP-P = 1V (AV = 1)
VOP-P = 2V (AV = 2)
-100
100 200 300 400 500 600 700 800 900
2
HD
-60
HD2 (AV = 2)
DISTORTION (dB)
DISTORTION (dB)
= 2)
)
FREQUENCY (Hz)
(A V
=2
HD2 (AV
-70
)
= 1)
3 (A V
HD
-80
HD
=2
3 (A V
)
=1
1k
-100
FIGURE 17. HARMONIC DISTORTION vs LOAD RESISTANCE
50mV/DIV
0
5
10
15
)
VS = ±5V
RL = 500
VOP-P = 1V (AV = 1)
VOP-P = 2V (AV = 2)
-90
RLOAD ()
20
25
30
35
40
RLOAD ()
FIGURE 18. HARMONIC DISTORTION vs FREQUENCY
0.5V/DIV
10ns/DIV
FIGURE 19. SMALL SIGNAL TRANSIENT RESPONSE
FN7306 Rev 7.00
August 25, 2010
= 2)
-60
-90
1M
(AV
HD2
10ns/DIV
FIGURE 20. LARGE SIGNAL TRANSIENT RESPONSE
Page 8 of 15
EL5175, EL5375
Typical Performance Curves
(Continued)
M = 100ns
CH1 = 200mV/DIV
CH2 = 5V/DIV
M = 400ns
CH1 = 200mV/DIV
CH2 = 5V/DIV
CH1
CH1
CH2
CH2
100ns/DIV
400ns/DIV
FIGURE 21. ENABLED RESPONSE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.0
870mW
QSOP24
JA = +115°C/W
0.8
625mW
0.6
SO8
JA = +160°C/W
0.4 486mW
MSOP8
JA = +206°C/W
0.2
0
0
25
50
75 85 100
125
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.4
POWER DISSIPATION (W)
POWER DISSIPATION (W)
1.2
FIGURE 22. DISABLED RESPONSE
1.2 1.136W
SO8
JA = +110°C/W
0.8 870mW
0.6
MSOP8
JA = +115°C/W
0.4
0.2
0
150
QSOP24
JA = +88°C/W
1.0 909mW
0
AMBIENT TEMPERATURE (°C)
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 23. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Simplified Schematic
VS+
I1
VIN+
Q1
I2
RD1
VINQ2
I3
VREF
Q3
I4
RD2
FB
Q4
R3
R4
Q8
Q7
VB1
Q9
x1
VOUT
Q6
25
VB2
CC
R1
R2
VS-
FN7306 Rev 7.00
August 25, 2010
Page 9 of 15
EL5175, EL5375
Description of Operation and Application
Information
Product Description
The EL5175 and EL5375 are wide bandwidth, low power
and single/differential ended to single-ended output
amplifiers. The EL5175 is a single channel differential to
single-ended amplifier. The EL5375 is a triple channel
differential to single ended amplifier. The EL5175 and
EL5375 are internally compensated for closed loop gain of
+1 orgreater. Connected in gain of 1 and driving a 500
load, the EL5175 and EL5375 have a -3dB bandwidth of
550MHz. Driving a 150 load at gain of 2, the bandwidth is
about 130MHz. The bandwidth at the REF input is about
450MHz. The EL5175 and EL5375 is available with a
power-down feature to reduce the power while the amplifier
is disabled.
Input, Output and Supply Voltage Range
The EL5175 and EL5375 have been designed to operate
with a single supply voltage of 5V to 10V or a split supplies
with its total voltage from 5V to 10V. The amplifiers have an
input common mode voltage range from -4.3V to 3.3V for
±5V supply. The differential mode input range (DMIR)
between the two inputs is approximately -2.3V to +2.3V. The
input voltage range at the REF pin is from -3.6V to 3.3V. If
the input common mode or differential mode signal is outside
the above-specified ranges, it will cause the output signal to
become distorted.
The output of the EL5175 and EL5375 can swing from -3.9V
to 3.5V at 500 load at ±5V supply. As the load resistance
becomes lower, the output swing is reduced respectively.
Overall Gain Settings
The gain setting for the EL5175 and EL5375 is similar to the
conventional operational amplifier. The output voltage is
equal to the difference of the inputs plus VREF and then
times the gain.
RF
V O = V IN + – V IN - + V REF 1 + --------
R
G
(EQ. 1)
EN
VIN+
VIN-
+
VREF
FB
G/B
+
RF
RG
FIGURE 25.
FN7306 Rev 7.00
August 25, 2010
VO
Choice of Feedback Resistor and Gain Bandwidth
Product
For applications that require a gain of +1, no feedback
resistor is required. Just short the OUT+ pin to FBP pin and
OUT- pin to FBN pin. For gains greater than +1, the
feedback resistor forms a pole with the parasitic capacitance
at the inverting input. As this pole becomes smaller, the
amplifier's phase margin is reduced. This causes ringing in
the time domain and peaking in the frequency domain.
Therefore, RF has some maximum value that should not be
exceeded for optimum performance. If a large value of RF
must be used, a small capacitor in the few Pico farad range
in parallel with RF can help to reduce the ringing and
peaking at the expense of reducing the bandwidth.
The bandwidth of the EL5175 and EL5375 depends on the
load and the feedback network. RF and RG appear in
parallel with the load for gains other than +1. As this
combination gets smaller, the bandwidth falls off.
Consequently, RF also has a minimum value that should not
be exceeded for optimum bandwidth performance. For gain
of +1, RF = 0 is optimum. For the gains other than +1,
optimum response is obtained with RF between 500 to
1k. For AV = 2 and RF = RG = 806, the BW is about
190MHz and the frequency response is very flat.
The EL5175 and EL5375 have a gain bandwidth product of
200MHz. For gains 5, its bandwidth can be predicted by
using Equation 2:
(EQ. 2)
Gain BW = 200MHz
Driving Capacitive Loads and Cables
The EL5175 and EL5375 can drive 15pF capacitance in
parallel with 500 load to ground with less than 4.5dB of
peaking at a gain of +1. If less peaking is desired in
applications, a small series resistor (usually between 5 to
50) can be placed in series with each output to eliminate
most peaking. However, this will reduce the gain slightly. If
the gain setting is greater than 1, the gain resistor RG can
then be chosen to make up for any gain loss, which may be
created by the additional series resistor at the output.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
Disable/Power-Down
The EL5175 and EL5375 can be disabled and its outputs
placed in a high impedance state. The turn-off time is about
1.2µs and the turn-on time is about 80ns. When disabled,
the amplifier's supply current is reduced to 80µA for IS+ and
120µA for IS- typically, thereby effectively eliminating the
Page 10 of 15
EL5175, EL5375
power consumption. The amplifier's power-down can be
controlled by standard CMOS signal levels at the ENABLE
pin. The applied logic signal is relative to the VS+ pin. Letting
the EN pin float or applying a signal that is less than 1.5V
below VS+ will enable the amplifier. The amplifier will be
disabled when the signal at the EN pin is above VS+ - 0.5V.
If a TTL signal is used to control the enabled/disabled
function, Figure 26 could be used to convert the TTL signal
to CMOS signal.
Assume the REF pin is tired to GND for VS = ±5V
application, the maximum power dissipation actually
produced by an IC is the total quiescent supply current times
the total power supply voltage, plus the power in the IC due
to the load, or:
For sourcing, see Equation 4:
V OUT
PD MAX = V S I SMAX + V S + – V OUT -------------------- i
R
5V
For sinking, see Equation 5:
10k
1k
(EQ. 4)
LOAD
EN
PD MAX = V S I SMAX + V OUT – V S - I LOAD i
CMOS/TTL
(EQ. 5)
Where:
FIGURE 26. CONVERSION OF TTL SIGNAL TO CMOS SIGNAL
• VS = Total supply voltage
Output Drive Capability
• ISMAX = Maximum quiescent supply current per channel
The EL5175 and EL5375 have internal short circuit
protection. Its typical short circuit current is ±67mA. If the
output is shorted indefinitely, the power dissipation could
easily increase such that the part will be destroyed.
Maximum reliability is maintained if the output current never
exceeds ±60mA. This limit is set by the design of the internal
metal interconnections.
Power Dissipation
With the high output drive capability of the EL5175 and
EL5375, it is possible to exceed the +135°C absolute
maximum junction temperature under certain load current
conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if the load conditions or package types need to be
modified for the amplifier to remain in the safe operating
area.
The maximum power dissipation allowed in a package is
determined according to Equation 3:
T JMAX – T AMAX
PD MAX = -------------------------------------------- JA
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
• JA = Thermal resistance of the package
FN7306 Rev 7.00
August 25, 2010
(EQ. 3)
• VOUT = Maximum output voltage of the application
• RLOAD = Load resistance
• ILOAD = Load current
• i = Number of channels
By setting the two PDMAX equations equal to each other, we
can solve the output current and RLOAD to avoid the device
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as short as possible. The power supply
pin must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the VS- pin is
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from VS+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the VS- pin becomes the negative
supply rail.
For good AC performance, parasitic capacitance should be
kept to a minimum. Use of wire-wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
Page 11 of 15
EL5175, EL5375
Typical Applications
0
50
VFB
50
EL5173,
EL5373
VIN
50
VINB
50
ZO = 100
EL5175/
EL5375
VOUT
VREF
FIGURE 27. TWISTED PAIR CABLE RECEIVER
R3
R1
R2
GAIN
(dB)
C1
50
ZO = 100
50
1 + R2/R1
VFB
VIN
VINB
EL5175,
EL5375
VOUT
1 + R2 / (R1 + R3)
VREF
fA
fC
f
FIGURE 28. COMPENSATED LINE RECEIVER
As the signal is transmitted through a cable, the high
frequency signal will be attenuated. One way to compensate
this loss is to boost the high frequency gain at the receiver
side.
Level Shifter and Signal Summer
The EL5175 and EL5375 contains two pairs of differential
pair input stages. It makes the inputs all high impedance. To
take advantage of the two high impedance inputs, the
EL5175 and EL5375 can be used as a signal summer to add
two signals together. One signal can be applied to VIN+; the
second signal can be applied to REF and VIN- is ground.
The output is equal to Equation 6:
V O = V IN + + V REF Gain
(EQ. 6)
Also, the EL5175 and EL5375 can be used as a level shifter
by applying a level control signal to the REF input.
FN7306 Rev 7.00
August 25, 2010
Page 12 of 15
EL5175, EL5375
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
NOTES:
Rev. M 2/07
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN7306 Rev 7.00
August 25, 2010
Page 13 of 15
EL5175, EL5375
Mini SO Package Family (MSOP)
0.25 M C A B
D
MINI SO PACKAGE FAMILY
(N/2)+1
N
E
MDP0043
A
E1
MILLIMETERS
PIN #1
I.D.
1
B
(N/2)
e
H
C
SEATING
PLANE
0.10 C
N LEADS
0.08 M C A B
b
SYMBOL
MSOP8
MSOP10
TOLERANCE
NOTES
A
1.10
1.10
Max.
-
A1
0.10
0.10
±0.05
-
A2
0.86
0.86
±0.09
-
b
0.33
0.23
+0.07/-0.08
-
c
0.18
0.18
±0.05
-
D
3.00
3.00
±0.10
1, 3
E
4.90
4.90
±0.15
-
E1
3.00
3.00
±0.10
2, 3
e
0.65
0.50
Basic
-
L
0.55
0.55
±0.15
-
L1
0.95
0.95
Basic
-
N
8
10
Reference
Rev. D 2/07
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
L1
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
A
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
A1
L
0.25
3° ±3°
DETAIL X
FN7306 Rev 7.00
August 25, 2010
Page 14 of 15
EL5175, EL5375
Quarter Size Outline Plastic Packages Family (QSOP)
MDP0040
A
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
D
(N/2)+1
N
INCHES
SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
E
PIN #1
I.D. MARK
E1
1
(N/2)
B
0.010
C A B
e
H
C
SEATING
PLANE
0.007
0.004 C
b
C A B
A
0.068
0.068
0.068
Max.
-
A1
0.006
0.006
0.006
±0.002
-
A2
0.056
0.056
0.056
±0.004
-
b
0.010
0.010
0.010
±0.002
-
c
0.008
0.008
0.008
±0.001
-
D
0.193
0.341
0.390
±0.004
1, 3
E
0.236
0.236
0.236
±0.008
-
E1
0.154
0.154
0.154
±0.004
2, 3
e
0.025
0.025
0.025
Basic
-
L
0.025
0.025
0.025
±0.009
-
L1
0.041
0.041
0.041
Basic
-
N
16
24
28
Reference
Rev. F 2/07
NOTES:
L1
A
1. Plastic or metal protrusions of 0.006” maximum per side are not
included.
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
c
SEE DETAIL "X"
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010
A2
GAUGE
PLANE
L
A1
4°±4°
DETAIL X
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modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
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FN7306 Rev 7.00
August 25, 2010
Page 15 of 15
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