H83003

To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com Renesas Technology Corp. Customer Support Dept. April 1, 2003 Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. 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Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. H8/3003 Hardware Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. ADE-602-055A Preface The H8/3003 is a high-performance microcontroller that integrates system supporting functions together with an H8/300H CPU core. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space. The on-chip system supporting functions include RAM, a 16-bit integrated timer unit (ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, I/O ports, a direct memory access controller (DMAC), a refresh controller, and other facilities. The four operating modes offer a choice of data bus width and address space size, enabling the H8/3003 to adapt quickly and flexibly to a variety of conditions. This manual describes the H8/3003 hardware. For details of the instruction set, refer to the H8/300H Programming Manual. Contents Section 1 1.1 1.2 1.3 1.4 Overview...................................................................................................... 1 Overview ........................................................................................................................ 1 Block Diagram................................................................................................................ 5 Pin Description ............................................................................................................... 6 1.3.1 Pin Arrangement............................................................................................. 6 1.3.2 Pin Functions .................................................................................................. 7 Pin Functions .................................................................................................................. 11 17 17 17 18 19 20 21 21 22 23 24 25 25 26 28 28 29 30 40 41 41 41 44 48 48 49 49 51 52 52 52 Section 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 CPU ............................................................................................................... Overview ........................................................................................................................ 2.1.1 Features........................................................................................................... 2.1.2 Differences from H8/300 CPU ....................................................................... CPU Operating Modes.................................................................................................... Address Space................................................................................................................. Register Configuration.................................................................................................... 2.4.1 Overview......................................................................................................... 2.4.2 General Registers............................................................................................ 2.4.3 Control Registers ............................................................................................ 2.4.4 Initial CPU Register Values ............................................................................ Data Formats................................................................................................................... 2.5.1 General Register Data Formats....................................................................... 2.5.2 Memory Data Formats .................................................................................... Instruction Set................................................................................................................. 2.6.1 Instruction Set Overview ................................................................................ 2.6.2 Instructions and Addressing Modes................................................................ 2.6.3 Tables of Instructions Classified by Function................................................. 2.6.4 Basic Instruction Formats ............................................................................... 2.6.5 Notes on Use of Bit Manipulation Instructions .............................................. Addressing Modes and Effective Address Calculation .................................................. 2.7.1 Addressing Modes .......................................................................................... 2.7.2 Effective Address Calculation ........................................................................ Processing States ............................................................................................................ 2.8.1 Overview......................................................................................................... 2.8.2 Program Execution State ................................................................................ 2.8.3 Exception-Handling State............................................................................... 2.8.4 Exception-Handling Sequences ...................................................................... 2.8.5 Bus-Released State ......................................................................................... 2.8.6 Reset State ...................................................................................................... 2.8.7 Power-Down State .......................................................................................... 2.9 Basic Operational Timing............................................................................................... 2.9.1 Overview......................................................................................................... 2.9.2 On-Chip Memory Access Timing................................................................... 2.9.3 On-Chip Supporting Module Access Timing ................................................. 2.9.4 Access to External Address Space.................................................................. 53 53 53 55 56 57 57 57 58 59 60 62 62 62 62 62 63 63 65 65 65 65 66 67 67 67 69 70 71 71 72 73 73 73 74 75 75 Section 3 3.1 3.2 3.3 3.4 3.5 3.6 MCU Operating Modes ........................................................................... Overview ........................................................................................................................ 3.1.1 Operating Mode Selection .............................................................................. 3.1.2 Register Configuration.................................................................................... Mode Control Register (MDCR) .................................................................................... System Control Register (SYSCR)................................................................................. Operating Mode Descriptions......................................................................................... 3.4.1 Mode 1 ............................................................................................................ 3.4.2 Mode 2 ............................................................................................................ 3.4.3 Mode 3 ............................................................................................................ 3.4.4 Mode 4 ............................................................................................................ Pin Functions in Each Operating Mode.......................................................................... Memory Map in Each Operating Mode.......................................................................... Exception Handling .................................................................................. Overview ........................................................................................................................ 4.1.1 Exception Handling Types and Priority.......................................................... 4.1.2 Exception Handling Operation ....................................................................... 4.1.3 Exception Vector Table................................................................................... Reset ........................................................................................................................ 4.2.1 Overview......................................................................................................... 4.2.2 Reset Sequence ............................................................................................... 4.2.3 Interrupts after Reset....................................................................................... Interrupts ........................................................................................................................ Trap Instruction............................................................................................................... Stack Status after Exception Handling ........................................................................... Notes on Stack Usage ..................................................................................................... Interrupt Controller................................................................................... Overview ........................................................................................................................ 5.1.1 Features........................................................................................................... 5.1.2 Block Diagram................................................................................................ 5.1.3 Pin Configuration............................................................................................ 5.1.4 Register Configuration.................................................................................... Section 4 4.1 4.2 4.3 4.4 4.5 4.6 Section 5 5.1 5.2 5.3 5.4 5.5 Register Descriptions...................................................................................................... 5.2.1 System Control Register (SYSCR)................................................................. 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ....................................... 5.2.3 IRQ Status Register (ISR) .............................................................................. 5.2.4 IRQ Enable Register (IER) ............................................................................. 5.2.5 IRQ Sense Control Register (ISCR) ............................................................... Interrupt Sources............................................................................................................. 5.3.1 External Interrupts .......................................................................................... 5.3.2 Internal Interrupts ........................................................................................... 5.3.3 Interrupt Vector Table ..................................................................................... Interrupt Operation ......................................................................................................... 5.4.1 Interrupt Handling Process ............................................................................. 5.4.2 Interrupt Sequence .......................................................................................... 5.4.3 Interrupt Response Time................................................................................. Usage Notes .................................................................................................................... 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction ................ 5.5.2 Instructions that Inhibit Interrupts .................................................................. 5.5.3 Interrupts during EEPMOV Instruction Execution......................................... 76 76 77 84 85 86 87 87 88 88 91 91 96 97 98 98 99 99 Section 6 6.1 Bus Controller ............................................................................................ 101 6.2 6.3 6.4 Overview ........................................................................................................................ 101 6.1.1 Features........................................................................................................... 101 6.1.2 Block Diagram................................................................................................ 102 6.1.3 Input/Output Pins............................................................................................ 103 6.1.4 Register Configuration.................................................................................... 103 Register Descriptions...................................................................................................... 104 6.2.1 Bus Width Control Register (ABWCR) ......................................................... 104 6.2.2 Access State Control Register (ASTCR) ........................................................ 105 6.2.3 Wait Control Register (WCR)......................................................................... 106 6.2.4 Wait State Control Enable Register (WCER) ................................................. 107 6.2.5 Bus Release Control Register (BRCR)........................................................... 108 Operation ........................................................................................................................ 109 6.3.1 Area Division.................................................................................................. 109 6.3.2 Chip Select Signals ......................................................................................... 111 6.3.3 Data Bus.......................................................................................................... 112 6.3.4 Bus Control Signal Timing ............................................................................. 113 6.3.5 Wait Modes ..................................................................................................... 121 6.3.6 Interconnections with Memory (Example)..................................................... 127 6.3.7 Bus Arbiter Operation..................................................................................... 129 Usage Notes .................................................................................................................... 132 6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM ................................ 132 6.4.2 6.4.3 Register Write Timing .................................................................................... 132 BREQ Input Timing........................................................................................ 133 Section 7 7.1 Refresh Controller .................................................................................... 135 7.2 7.3 7.4 7.5 Overview ........................................................................................................................ 135 7.1.1 Features........................................................................................................... 135 7.1.2 Block Diagram................................................................................................ 136 7.1.3 Input/Output Pins............................................................................................ 137 7.1.4 Register Configuration.................................................................................... 137 Register Descriptions...................................................................................................... 138 7.2.1 Refresh Control Register (RFSHCR) ............................................................. 138 7.2.2 Refresh Timer Control/Status Register (RTMCSR) ....................................... 141 7.2.3 Refresh Timer Counter (RTCNT)................................................................... 143 7.2.4 Refresh Time Constant Register (RTCOR) .................................................... 143 Operation ........................................................................................................................ 144 7.3.1 Area Division.................................................................................................. 144 7.3.2 DRAM Refresh Control.................................................................................. 145 7.3.3 Pseudo-Static RAM Refresh Control.............................................................. 160 7.3.4 Interval Timing ............................................................................................... 165 Interrupt Source .............................................................................................................. 171 Usage Notes .................................................................................................................... 171 Section 8 8.1 8.2 8.3 8.4 DMA Controller ........................................................................................ 173 Overview ........................................................................................................................ 173 8.1.1 Features........................................................................................................... 173 8.1.2 Block Diagram................................................................................................ 174 8.1.3 Functional Overview....................................................................................... 175 8.1.4 Input/Output Pins............................................................................................ 176 8.1.5 Register Configuration.................................................................................... 176 Register Descriptions (1) (Short Address Mode) ........................................................... 179 8.2.1 Memory Address Registers (MAR)................................................................ 180 8.2.2 I/O Address Registers (IOAR)........................................................................ 181 8.2.3 Execute Transfer Count Registers (ETCR)..................................................... 181 8.2.4 Data Transfer Control Registers (DTCR) ....................................................... 183 Register Descriptions (2) (Full Address Mode).............................................................. 187 8.3.1 Memory Address Registers (MAR)................................................................ 187 8.3.2 I/O Address Registers (IOAR)........................................................................ 187 8.3.3 Execute Transfer Count Registers (ETCR)..................................................... 188 8.3.4 Data Transfer Control Registers (DTCR) ....................................................... 190 Operation ........................................................................................................................ 196 8.4.1 Overview......................................................................................................... 196 8.5 8.6 8.4.2 I/O Mode......................................................................................................... 198 8.4.3 Idle Mode........................................................................................................ 200 8.4.4 Repeat Mode................................................................................................... 203 8.4.5 Normal Mode.................................................................................................. 206 8.4.6 Block Transfer Mode ...................................................................................... 209 8.4.7 DMAC Activation........................................................................................... 214 8.4.8 DMAC Bus Cycle ........................................................................................... 216 8.4.9 Multiple-Channel Operation........................................................................... 222 8.4.10 External Bus Requests, Refresh Controller, and DMAC................................ 225 8.4.11 NMI Interrupts and DMAC ............................................................................ 226 8.4.12 Aborting a DMA Transfer .............................................................................. 227 8.4.13 Exiting Full Address Mode............................................................................. 228 8.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode .................... 229 Interrupts ........................................................................................................................ 230 Usage Notes .................................................................................................................... 232 8.6.1 Note on Word Data Transfer........................................................................... 232 8.6.2 DMAC Self-Access ........................................................................................ 232 8.6.3 Longword Access to Memory Address Registers........................................... 232 8.6.4 Note on Full Address Mode Setup.................................................................. 232 8.6.5 Note on Activating DMAC by Internal Interrupts .......................................... 233 8.6.6 NMI Interrupts and Block Transfer Mode ...................................................... 234 8.6.7 Memory and I/O Address Register Values ..................................................... 234 8.6.8 Bus Cycle when Transfer is Aborted .............................................................. 235 Section 9 9.1 9.2 9.3 9.4 I/O Ports ....................................................................................................... 237 Overview ........................................................................................................................ 237 Port 4 ........................................................................................................................ 240 9.2.1 Overview......................................................................................................... 240 9.2.2 Register Descriptions...................................................................................... 241 9.2.3 Pin Functions in Each Mode........................................................................... 243 9.2.4 Input Pull-Up Transistors................................................................................ 244 Port 5 ........................................................................................................................ 245 9.3.1 Overview......................................................................................................... 245 9.3.2 Register Descriptions...................................................................................... 245 9.3.3 Pin Functions in Each Mode........................................................................... 248 9.3.4 Input Pull-Up Transistors................................................................................ 249 Port 6 ........................................................................................................................ 250 9.4.1 Overview......................................................................................................... 250 9.4.2 Register Descriptions...................................................................................... 250 9.4.3 Pin Functions .................................................................................................. 252 9.5 9.6 9.7 9.8 9.9 9.10 Port 7 9.5.1 9.5.2 Port 8 9.6.1 9.6.2 9.6.3 Port 9 9.7.1 9.7.2 9.7.3 Port A 9.8.1 9.8.2 9.8.3 Port B 9.9.1 9.9.2 9.9.3 Port C 9.10.1 9.10.2 9.10.3 ........................................................................................................................ 252 Overview......................................................................................................... 252 Register Description ....................................................................................... 253 ........................................................................................................................ 254 Overview......................................................................................................... 254 Register Descriptions...................................................................................... 254 Pin Functions .................................................................................................. 256 ........................................................................................................................ 257 Overview......................................................................................................... 257 Register Descriptions...................................................................................... 257 Pin Functions .................................................................................................. 259 ........................................................................................................................ 261 Overview......................................................................................................... 261 Register Descriptions...................................................................................... 261 Pin Functions .................................................................................................. 263 ........................................................................................................................ 268 Overview......................................................................................................... 268 Register Descriptions...................................................................................... 268 Pin Functions .................................................................................................. 270 ........................................................................................................................ 276 Overview......................................................................................................... 276 Register Descriptions...................................................................................... 276 Pin Functions .................................................................................................. 278 Section 10 10.1 10.2 16-Bit Integrated Timer Unit (ITU)..................................................... 281 Overview ........................................................................................................................ 281 10.1.1 Features........................................................................................................... 281 10.1.2 Block Diagrams .............................................................................................. 284 10.1.3 Input/Output Pins............................................................................................ 289 10.1.4 Register Configuration.................................................................................... 290 Register Descriptions...................................................................................................... 293 10.2.1 Timer Start Register (TSTR) .......................................................................... 293 10.2.2 Timer Synchro Register (TSNC) .................................................................... 294 10.2.3 Timer Mode Register (TMDR)....................................................................... 296 10.2.4 Timer Function Control Register (TFCR) ...................................................... 299 10.2.5 Timer Output Master Enable Register (TOER) .............................................. 301 10.2.6 Timer Output Control Register (TOCR)......................................................... 304 10.2.7 Timer Counters (TCNT) ................................................................................. 305 10.2.8 General Registers (GRA, GRB) ..................................................................... 306 10.2.9 Buffer Registers (BRA, BRB) ........................................................................ 307 10.2.10 Timer Control Registers (TCR) ...................................................................... 308 10.3 10.4 10.5 10.6 10.2.11 Timer I/O Control Register (TIOR)................................................................ 310 10.2.12 Timer Status Register (TSR)........................................................................... 312 10.2.13 Timer Interrupt Enable Register (TIER)......................................................... 315 CPU Interface ................................................................................................................. 317 10.3.1 16-Bit Accessible Registers ............................................................................ 317 10.3.2 8-Bit Accessible Registers .............................................................................. 319 Operation ........................................................................................................................ 321 10.4.1 Overview......................................................................................................... 321 10.4.2 Basic Functions............................................................................................... 322 10.4.3 Synchronization .............................................................................................. 332 10.4.4 PWM Mode .................................................................................................... 334 10.4.5 Reset-Synchronized PWM Mode ................................................................... 338 10.4.6 Complementary PWM Mode.......................................................................... 341 10.4.7 Phase Counting Mode..................................................................................... 351 10.4.8 Buffering......................................................................................................... 353 10.4.9 ITU Output Timing......................................................................................... 360 Interrupts ........................................................................................................................ 362 10.5.1 Setting of Status Flags .................................................................................... 362 10.5.2 Clearing of Status Flags.................................................................................. 364 10.5.3 Interrupt Sources and DMA Controller Activation ........................................ 365 Usage Notes .................................................................................................................... 366 Section 11 11.1 11.2 11.3 Programmable Timing Pattern Controller ......................................... 381 Overview ........................................................................................................................ 381 11.1.1 Features........................................................................................................... 381 11.1.2 Block Diagram................................................................................................ 382 11.1.3 TPC Pins ......................................................................................................... 383 11.1.4 Registers ......................................................................................................... 384 Register Descriptions...................................................................................................... 385 11.2.1 Port A Data Direction Register (PADDR) ...................................................... 385 11.2.2 Port A Data Register (PADR) ......................................................................... 385 11.2.3 Port B Data Direction Register (PBDDR) ...................................................... 386 11.2.4 Port B Data Register (PBDR) ......................................................................... 386 11.2.5 Next Data Register A (NDRA)....................................................................... 387 11.2.6 Next Data Register B (NDRB) ....................................................................... 389 11.2.7 Next Data Enable Register A (NDERA) ........................................................ 391 11.2.8 Next Data Enable Register B (NDERB)......................................................... 392 11.2.9 TPC Output Control Register (TPCR)............................................................ 393 11.2.10 TPC Output Mode Register (TPMR).............................................................. 396 Operation ........................................................................................................................ 398 11.3.1 Overview......................................................................................................... 398 11.4 11.3.2 Output Timing................................................................................................. 399 11.3.3 Normal TPC Output........................................................................................ 400 11.3.4 Non-Overlapping TPC Output........................................................................ 402 11.3.5 TPC Output Triggering by Input Capture....................................................... 404 Usage Notes .................................................................................................................... 405 11.4.1 Operation of TPC Output Pins........................................................................ 405 11.4.2 Note on Non-Overlapping Output .................................................................. 405 Section 12 12.1 12.2 12.3 12.4 12.5 Watchdog Timer ........................................................................................ 407 Overview ........................................................................................................................ 407 12.1.1 Features........................................................................................................... 407 12.1.2 Block Diagram................................................................................................ 408 12.1.3 Pin Configuration............................................................................................ 408 12.1.4 Register Configuration.................................................................................... 409 Register Descriptions...................................................................................................... 410 12.2.1 Timer Counter (TCNT)................................................................................... 410 12.2.2 Timer Control/Status Register (TCSR)........................................................... 411 12.2.3 Reset Control/Status Register (RSTCSR) ...................................................... 413 12.2.4 Notes on Register Access ............................................................................... 415 Operation ........................................................................................................................ 417 12.3.1 Watchdog Timer Operation............................................................................. 417 12.3.2 Interval Timer Operation ................................................................................ 418 12.3.3 Timing of Setting of Overflow Flag (OVF) .................................................... 419 12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) ............................. 420 Interrupts ........................................................................................................................ 421 Usage Notes .................................................................................................................... 421 Serial Communication Interface ........................................................... 423 Section 13 13.1 13.2 Overview ........................................................................................................................ 423 13.1.1 Features........................................................................................................... 423 13.1.2 Block Diagram................................................................................................ 425 13.1.3 Input/Output Pins............................................................................................ 426 13.1.4 Register Configuration.................................................................................... 426 Register Descriptions...................................................................................................... 427 13.2.1 Receive Shift Register (RSR) ......................................................................... 427 13.2.2 Receive Data Register (RDR)......................................................................... 427 13.2.3 Transmit Shift Register (TSR) ........................................................................ 428 13.2.4 Transmit Data Register (TDR)........................................................................ 428 13.2.5 Serial Mode Register (SMR) .......................................................................... 429 13.2.6 Serial Control Register (SCR) ........................................................................ 433 13.2.7 Serial Status Register (SSR) ........................................................................... 437 13.3 13.4 13.5 13.2.8 Bit Rate Register (BRR) ................................................................................. 441 Operation ........................................................................................................................ 450 13.3.1 Overview......................................................................................................... 450 13.3.2 Operation in Asynchronous Mode.................................................................. 452 13.3.3 Multiprocessor Communication ..................................................................... 461 13.3.4 Synchronous Operation .................................................................................. 468 SCI Interrupts.................................................................................................................. 477 Usage Notes .................................................................................................................... 478 Section 14 14.1 14.2 14.3 14.4 14.5 14.6 A/D Converter ............................................................................................ 483 Overview ........................................................................................................................ 483 14.1.1 Features........................................................................................................... 483 14.1.2 Block Diagram................................................................................................ 484 14.1.3 Input Pins ........................................................................................................ 485 14.1.4 Register Configuration.................................................................................... 486 Register Descriptions...................................................................................................... 487 14.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ........................................ 487 14.2.2 A/D Control/Status Register (ADCSR) .......................................................... 488 14.2.3 A/D Control Register (ADCR) ....................................................................... 491 CPU Interface ................................................................................................................. 492 Operation ........................................................................................................................ 493 14.4.1 Single Mode (SCAN = 0) ............................................................................... 493 14.4.2 Scan Mode (SCAN = 1).................................................................................. 495 14.4.3 Input Sampling and A/D Conversion Time .................................................... 497 14.4.4 External Trigger Input Timing........................................................................ 498 Interrupts ........................................................................................................................ 499 Usage Notes .................................................................................................................... 499 Section 15 15.1 15.2 15.3 RAM ............................................................................................................. 501 Overview ........................................................................................................................ 501 15.1.1 Block Diagram................................................................................................ 501 15.1.2 Register Configuration.................................................................................... 502 System Control Register (SYSCR)................................................................................. 503 Operation ........................................................................................................................ 504 Clock Pulse Generator ............................................................................. 505 Section 16 16.1 16.2 Overview ........................................................................................................................ 505 16.1.1 Block Diagram................................................................................................ 505 Oscillator Circuit ............................................................................................................ 506 16.2.1 Connecting a Crystal Resonator ..................................................................... 506 16.2.2 External Clock Input....................................................................................... 508 16.3 16.4 16.5 System Clock Divider (Clock-Halving Version) ............................................................ 510 Duty Adjustment Circuit (1:1 Version)........................................................................... 510 Prescalers ........................................................................................................................ 510 Section 17 17.1 17.2 17.3 17.4 17.5 Power-Down State .................................................................................... 511 Overview ........................................................................................................................ 511 Register Configuration.................................................................................................... 512 17.2.1 System Control Register (SYSCR)................................................................. 512 Sleep Mode ..................................................................................................................... 514 17.3.1 Transition to Sleep Mode................................................................................ 514 17.3.2 Exit from Sleep Mode..................................................................................... 514 Software Standby Mode ................................................................................................. 515 17.4.1 Transition to Software Standby Mode ............................................................ 515 17.4.2 Exit from Software Standby Mode ................................................................. 515 17.4.3 Selection of Waiting Time for Exit from Software Standby Mode ................ 516 17.4.4 Sample Application of Software Standby Mode ............................................ 517 17.4.5 Note................................................................................................................. 517 Hardware Standby Mode ................................................................................................ 518 17.5.1 Transition to Hardware Standby Mode........................................................... 518 17.5.2 Exit from Hardware Standby Mode................................................................ 518 17.5.3 Timing for Hardware Standby Mode.............................................................. 518 Section 18 18.1 18.2 18.3 Electrical Characteristics ........................................................................ 519 Absolute Maximum Ratings ........................................................................................... 519 Electrical Characteristics ................................................................................................ 520 18.2.1 DC Characteristics .......................................................................................... 520 18.2.2 AC Characteristics .......................................................................................... 529 18.2.3 A/D Conversion Characteristics ..................................................................... 536 Operational Timing......................................................................................................... 537 18.3.1 Bus Timing ..................................................................................................... 537 18.3.2 Refresh Controller Bus Timing....................................................................... 541 18.3.3 Control Signal Timing .................................................................................... 546 18.3.4 Clock Timing .................................................................................................. 548 18.3.5 TPC and I/O Port Timing................................................................................ 548 18.3.6 ITU Timing ..................................................................................................... 549 18.3.7 SCI Input/Output Timing................................................................................ 550 18.3.8 DMAC Timing................................................................................................ 551 Appendix A Instruction Set ............................................................................................ 553 A.1 A.2 A.3 Instruction List................................................................................................................ 553 Operation Code Map....................................................................................................... 568 Number of States Required for Execution...................................................................... 571 Appendix B Register Field ............................................................................................. 580 B.1 B.2 Register Addresses and Bit Names................................................................................. 580 Register Descriptions...................................................................................................... 589 Appendix C I/O Port Block Diagrams ........................................................................ 668 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 Port 4 Block Diagram ..................................................................................................... 668 Port 5 Block Diagram ..................................................................................................... 669 Port 6 Block Diagrams.................................................................................................... 670 Port 7 Block Diagram ..................................................................................................... 673 Port 8 Block Diagrams.................................................................................................... 674 Port 9 Block Diagrams.................................................................................................... 677 Port A Block Diagrams................................................................................................... 680 Port B Block Diagrams................................................................................................... 683 Port C Block Diagrams................................................................................................... 687 Appendix D Pin States ..................................................................................................... 691 D.1 D.2 Port States in Each Mode................................................................................................ 691 Pin States at Reset........................................................................................................... 693 Appendix E Appendix F Timing of Transition to and Recovery from Hardware Standby Mode.............................................................. 696 Package Dimensions ................................................................................ 697 Major Revisions and Additions in This Version Page P96 Item Figure 5-7 Interrupt Sequence (Mode 2, Two-State Access, Stack in External Memory) Interrupt Response Time Programmable Wait Mode ASTCR Write Timing Contention between RTCNT Write and Clear Contention between RTCNT Write and Increment Contention between RTCOR Write and Compare Match DMAC functional overview Operation in Normal Mode Timing of DMAC Activation by Low DREQ Level in Normal Mode Port B Pin Functions Description Operation timing amended P97 P125 P132 P166 Table 5-5 Figure 6-15 Figure 6-20 Figure 7-20 Table values changed Operation timing amended Operation timing amended Operation timing amended P167 Figure 7-21 Operation timing amended P168 Figure 7-22 Address bus amended P175 P207 P220 Table 8-1 Figure 8-8 Figure 8-17 Table contents amended Signal descriptions amended Operation timing amended P270 to Table 9-16 P272 P279 P343 Table 9-18 Table contents amended Port C Pin Functions Table contents amended Description added Figure 10-34 Clearing Procedure for Complementary PWM Mode Table 12-1 WDT Pin Sample Flowchart for Receiving Serial Data Usage Notes Damping Resistance Value Crystal Resonator Parameters Clock Timing External Clock Input Timing P408 Note deleted Flowchart amended P458 to Figure 13-7 P459 P480 P506 P507 P509 P509 13.5 Table 16-1 Table 16-2 Table 16-3 Figure 16-6 Formula amended Values added to table Values added to table Table values changed Figure amended Page P514 Item 17.3.2 Exit from Sleep Mode Exit by Interrupt Electrical Characteristics Description Description amended P529 to Table 18-4 P536 to 18-8 P520 to Table 18-2 P526 P529 to Table 18-4 P531 P532 P536 P541 Table 18-5 Table 18-8 Figure 18-7 Condition values amended DC Characteristics Values changed and added to table Bus Timing Values changed Refresh Controller Bus Timing A/D Conversion Characteristics DRAM Bus Timing (Read/Write): Three-State Access — 2WE Mode — Values changed Values changed *added P543 Figure 18-10 DRAM Bus Timing (Read/Write): Three-State Access — 2CAS Mode — Figure 18-13 PSRAM Bus Timing (Read/Write): Three-State Access Table A-1 Instruction Set MOV. B Rs, @(d:16, ERd) Instruction Set MOV. B Rs, @(d:24, ERd) Instruction Set MOV. W Rs, @(d:16, ERd) Instruction Set MOV. W Rs, @(d:24, ERd) *added P545 *added P555 Operation amended Table A-1 Operation amended P556 Table A-1 Operation amended Table A-1 Operation and number of execution states amended Table A-1 Table A-1 P557 P566 P575 Table A-1 Table A-1 Table A-3 Instruction Set MOV. L #xx:32, Rd Number of execution states amended Instruction Set POP, L ERn Instruction Set PUSH. L ERn Instruction Set STC Number of Cycles per Instruction BSRd:16 Port 7 Block Diagram (Pin P7n) Number of execution states amended Number of execution states amended Menmonics amended (3 places) Internal operation added P673 Figure C-4 Figure amended Section 1 Overview 1.1 Overview The H8/3003 is a microcontroller (MCU) that integrates system supporting functions together with an H8/300H CPU core having an original Hitachi architecture. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU, enabling easy porting of software from the H8/300 Series. The on-chip system supporting functions include RAM, a 16-bit integrated timer unit (ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, I/O ports, a direct memory access controller (DMAC), a refresh controller, and other facilities. Four MCU operating modes offer a choice of data bus width and address space size. Table 1-1 summarizes the H8/3003 features. Table 1-1 Features Feature CPU Description Upward-compatible with the H8/300 CPU at the object-code level General-register machine • Sixteen 16-bit general registers (also useable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation • Maximum clock rate: 16 MHz • Add/subtract: 125 ns • Multiply/divide: 875 ns Two CPU operating modes • Normal mode (64-kbyte address space, not available in the H8/3003) • Advanced mode (16-Mbyte address space) Instruction features • • • • • 8/16/32-bit data transfer, arithmetic, and logic instructions Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16 bits) Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits) Bit accumulator function Bit manipulation instructions with register-indirect specification of bit positions 1 Table 1-1 Features (cont) Feature Memory Interrupt controller Bus controller Description RAM: 512 bytes • Nine external interrupt pins: NMI, IRQ0 to IRQ7 • 34 internal interrupts • Three selectable interrupt priority levels • Address space can be partitioned into eight areas, with independent bus specifications in each area • Chip select output available for each area • 8-bit access or 16-bit access selectable for each area • Two-state or three-state access selectable for each area • Selection of four wait modes • Bus arbitration function DRAM refresh • Directly connectable to 16-bit-wide DRAM • CAS-before-RAS refresh • Self-refresh mode selectable Pseudo-static RAM refresh • Self-refresh mode selectable Usable as an interval timer DMA controller (DMAC) Short address mode • Maximum eight channels available • Selection of I/O mode, idle mode, or repeat mode • Can be activated by compare match/input capture A interrupts from ITU channels 0 to 3, SCI transmit-data-empty and receive-data-full interrupts, or external requests Full address mode • Maximum four channels available • Selection of normal mode or block transfer mode • Can be activated by compare match/input capture A interrupts from ITU channels 0 to 3, external requests, or auto-request Refresh controller 2 Table 1-1 Features (cont) Feature 16-bit integrated timer unit (ITU) Description • Five 16-bit timer channels, capable of processing up to 12 pulse outputs or 10 pulse inputs • 16-bit timer counter (channels 0 to 4) • Two multiplexed output compare/input capture pins (channels 0 to 4) • Operation can be synchronized (channels 0 to 4) • PWM mode available (channels 0 to 4) • Phase counting mode available (channel 2) • Buffering available (channels 3 and 4) • Reset-synchronized PWM mode available (channels 3 and 4) • Complementary PWM mode available (channels 3 and 4) • DMAC can be activated by compare match/input capture A interrupt (channels 0 to 3) • • • • Maximum 16-bit pulse output, using ITU as time base Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups) Non-overlap mode available Output data can be transferred by DMAC Programmable timing pattern controller (TPC) Watchdog timer (WDT), 1 channel Serial communication interface (SCI), 2 channels A/D converter • Reset signal can be generated by overflow • Reset signal can be output externally • Usable as an interval timer • Selection of asynchronous or synchronous mode • Full duplex: can transmit and receive simultaneously • On-chip baud-rate generator • • • • • Resolution: 10 bits Eight channels, with selection of single or scan mode Variable analog conversion voltage range Sample-and-hold function Can be externally triggered I/O ports • 50 input/output pins • 8 input-only pins 3 Table 1-1 Features (cont) Feature Description Operating modes Four MCU operating modes Mode Mode 1 Mode 2 Mode 3 Mode 4 Power-down state Other features Product lineup Address Space 1 Mbyte 1 Mbyte 16 Mbyte 16 Mbyte Address Pins A0 to A19 A0 to A19 A0 to A23 A0 to A23 Initial Bus Max. Bus Width Width 8 bits 16 bits 8 bits 16 bits 16 bits 16 bits 16 bits 16 bits • Sleep mode • Software standby mode • Hardware standby mode • On-chip clock oscillator Model HD6413003RF HD6413003RVF HD6413003TF HD6413003TVF Package 112-pin QFP (QFP-112) Oscillator Divide-by-2 oscillator 1:1 oscillator Power Supply Voltage 5 V ±10% 2.7 V to 5.5 V 5 V ±10% 2.7 V to 5.5 V 4 1.2 Block Diagram Figure 1-1 shows an internal block diagram. P47 /D7 P46 /D6 P45 /D5 P44 /D4 P43 /D3 P42 /D2 P41 /D1 P40 /D0 VCC VCC VCC VSS VSS VSS VSS VSS VSS D15 D14 D13 D12 D11 D10 D9 Data bus D8 Port 4 P57 /A 23 Port 5 Data bus (upper) Data bus (lower) Address bus MD 2 MD 1 MD 0 EXTAL XTAL ø STBY RES RESO NMI AS RD HWR LWR Port 6 P62 /BACK P6 1 /BREQ P6 0 /WAIT P84 /CS 0 Port 8 P83 /CS1 /IRQ 3 P82 /CS2 /IRQ 2 P81 /CS3 /IRQ 1 P8 0 /RFSH/IRQ 0 PC7 /IRQ 7 PC6 /IRQ 6 PC 5 /DREQ3 /CS 7 Port C PC4 /TEND3 /CS 6 PC 3 /DREQ2 /CS 5 PC2 /TEND2 /CS 4 PC 1 PC 0 16-bit integrated timer unit (ITU) Watchdog timer (WDT) RAM 512 bytes Refresh controller DMA controller (DMAC) Interrupt controller Bus controller Clock osc. H8/300H CPU P56 /A 22 P55 /A 21 P54 /A 20 A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 Address bus Port 9 Port 7 P75 /AN 5 P74 /AN 4 P73 /AN 3 P72 /AN 2 P71 /AN 1 P70 /AN 0 A 11 A 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 P95 /SCK 1 /IRQ 5 Serial communication interface (SCI) × 2 channels Programmable timing pattern controller (TPC) P94 /SCK 0 /IRQ 4 A/D converter P93 /RxD1 P92 /RxD0 P91 /TxD 1 P90 /TxD 0 Port B PB 7 /TP15/DREQ 1/ADTRG PB5 /TP13 /TOCXB 4 PB4 /TP12 /TOCXA 4 PB 3 /TP11 /TIOCB 4 PB 2 /TP10 /TIOCA 4 PB 1 /TP9 /TIOCB 3 PB 0 /TP8 /TIOCA 3 PA 7 /TP7 /TIOCB 2 PA 6 /TP6 /TIOCA 2 PA 5 /TP5 /TIOCB 1 PB 6/TP14 /DREQ 0 Port A PA 3 /TP 3 /TIOCB0 /TCLKD PA 2 /TP 2 /TIOCA0 /TCLKC P77 /AN 7 PA 4 /TP4 /TIOCA 1 PA 1/TP1 /TCLKB/TEND 1 PA 0/TP0 /TCLKA/TEND 0 P76 /AN 6 AVCC AVSS VREF Figure 1-1 Block Diagram 5 1.3 Pin Description 1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the H8/3003’s QFP-112 package. PA 3 /TP3 /TIOCB0/TCLKD PA 2 /TP2 /TIOCA0/TCLKC PA 1 /TP1 /TEND 1 /TCLKB PA 0 /TP0 /TEND 0 /TCLKA PA 7 /TP7 /TIOCB2 PA 6 /TP6 /TIOCA2 PA 5 /TP5 /TIOCB1 PA 4 /TP4 /TIOCA1 P80 /RFSH/IRQ 0 P83 /CS1 /IRQ 3 P82 /CS2 /IRQ 2 P81 /CS3 /IRQ 1 P84 /CS0 P77 /AN7 P76 /AN6 P75 /AN5 P74 /AN4 P73 /AN3 P72 /AN2 P71 /AN1 P70 /AN0 P 7 /A 23 P5 P56 /A 22 P55 /A 21 P54 /A 20 AVSS 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 VCC TIOCA3/TP 8 /PB 0 TIOCB3/TP 9 /PB 1 TIOCA4/TP10 /PB 2 TIOCB4/TP11 /PB 3 TOCXA4/TP12 /PB 4 TOCXB4/TP13 /PB 5 DREQ 0 /TP14 /PB 6 ADTRG/DREQ 1 /TP15 /PB 7 VSS PC 0 PC 1 CS4 /TEND2 /PC 2 CS5 /DREQ2 /PC 3 CS6 /TEND3 /PC 4 CS7 /DREQ3 /PC 5 IRQ6 /PC 6 IRQ7 /PC 7 RESO TxD0 /P9 0 TxD1 /P9 1 RxD0 /P9 2 RxD1 /P9 3 IRQ 4/SCK0 /P9 4 IRQ 5/SCK1 /P9 5 VSS D0 /P4 0 D1 /P4 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 AVCC MD2 MD1 MD0 LWR HWR RD AS VCC XTAL EXTAL VSS NMI RES STBY ø P62 /BACK P61 /BREQ P60 /WAIT A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 28 57 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 D2 /P4 2 D3 /P4 3 D4 /P4 4 D5 /P4 5 D6 /P4 6 D7 /P4 7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 VSS VCC VSS A10 Top view Figure 1-2 Pin Arrangement (QFP-112, Top View) 6 VREF VSS 1.3.2 Pin Functions Pin Assignments in Each Mode: Table 1-2 lists the QFP-112 pin assignments in each mode. Table 1-2 QFP-112 Pin Assignments in Each Mode Pin No. Mode 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 VCC PB0/TP8/TIOCA3 PB1/TP9/TIOCB3 PB2/TP10/TIOCA4 PB3/TP11/TIOCB4 PB4/TP12/TOCXA4 PB5/TP13/TOCXB4 PB6/TP14/DREQ0 PB7/TP15/DREQ1/ADTRG VSS PC0 PC1 PC2/TEND2/CS4 PC3/DREQ2/CS5 PC4/TEND3/CS6 PC5/DREQ3/CS7 PC6/IRQ6 PC7/IRQ7 RESO P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/IRQ4 P95/SCK1/IRQ5 VSS Pin Name Mode 2 VCC PB0/TP8/TIOCA3 PB1/TP9/TIOCB3 PB2/TP10/TIOCA4 PB3/TP11/TIOCB4 PB4/TP12/TOCXA4 PB5/TP13/TOCXB4 PB6/TP14/DREQ0 PB7/TP15/DREQ1/ADTRG VSS PC0 PC1 PC2/TEND2/CS4 PC3/DREQ2/CS5 PC4/TEND3/CS6 PC5/DREQ3/CS7 PC6/IRQ6 PC7/IRQ7 RESO P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/IRQ4 P95/SCK1/IRQ5 VSS Mode 3 VCC PB0/TP8/TIOCA3 PB1/TP9/TIOCB3 PB2/TP10/TIOCA4 PB3/TP11/TIOCB4 PB4/TP12/TOCXA4 PB5/TP13/TOCXB4 PB6/TP14/DREQ0 PB7/TP15/DREQ1/ADTRG VSS PC0 PC1 PC2/TEND2/CS4 PC3/DREQ2/CS5 PC4/TEND3/CS6 PC5/DREQ3/CS7 PC6/IRQ6 PC7/IRQ7 RESO P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/IRQ4 P95/SCK1/IRQ5 VSS Mode 4 VCC PB0/TP8/TIOCA3 PB1/TP9/TIOCB3 PB2/TP10/TIOCA4 PB3/TP11/TIOCB4 PB4/TP12/TOCXA4 PB5/TP13/TOCXB4 PB6/TP14/DREQ0 PB7/TP15/DREQ1/ADTRG VSS PC0 PC1 PC2/TEND2/CS4 PC3/DREQ2/CS5 PC4/TEND3/CS6 PC5/DREQ3/CS7 PC6/IRQ6 PC7/IRQ7 RESO P90/TxD0 P91/TxD1 P92/RxD0 P93/RxD1 P94/SCK0/IRQ4 P95/SCK1/IRQ5 VSS 7 Table 1-2 QFP-112 Pin Assignments in Each Mode (cont) Pin No. Mode 1 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 P40/D0*1 P41/D1*1 P42/D2*1 P43/D3*1 P44/D4*1 P45/D5*1 P46/D6*1 P47/D7*1 VSS D8 D9 D10 D11 D12 D13 D14 D15 VCC A0 A1 A2 A3 A4 A5 A6 A7 VSS A8 A9 Pin Name Mode 2 P40/D0*2 P41/D1*2 P42/D2*2 P43/D3*2 P44/D4*2 P45/D5*2 P46/D6*2 P47/D7*2 VSS D8 D9 D10 D11 D12 D13 D14 D15 VCC A0 A1 A2 A3 A4 A5 A6 A7 VSS A8 A9 Mode 3 P40/D0* P41/D1* P42/D2* P43/D3* P44/D4* P45/D5* P46/D6* P47/D7* VSS D8 D9 D10 D11 D12 D13 D14 D15 VCC A0 A1 A2 A3 A4 A5 A6 A7 VSS A8 A9 Mode 4 D0 D1 D2 D3 D4 D5 D6 D7 VSS D8 D9 D10 D11 D12 D13 D14 D15 VCC A0 A1 A2 A3 A4 A5 A6 A7 VSS A8 A9 Notes: 1. In modes 1 and 3 the P40 to P47 functions of pins P40/D0 to P47/D7 are selected after a reset, but they can be changed by software. 2. In modes 2 and 4 the D0 to D7 functions of pins P40/D0 to D47/D7 are selected after a reset, but they can be changed by software. 8 Table 1-2 QFP-112 Pin Assignments in Each Mode (cont) Pin No. Mode 1 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 P60/WAIT P61/BREQ P62/BACK ø STBY RES NMI VSS EXTAL XTAL VCC AS RD HWR LWR MD0 MD1 MD2 Pin Name Mode 2 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 P60/WAIT P61/BREQ P62/BACK ø STBY RES NMI VSS EXTAL XTAL VCC AS RD HWR LWR MD0 MD1 MD2 Mode 3 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 P60/WAIT P61/BREQ P62/BACK ø STBY RES NMI VSS EXTAL XTAL VCC AS RD HWR LWR MD0 MD1 MD2 Mode 4 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 P60/WAIT P61/BREQ P62/BACK ø STBY RES NMI VSS EXTAL XTAL VCC AS RD HWR LWR MD0 MD1 MD2 9 Table 1-2 QFP-112 Pin Assignments in Each Mode (cont) Pin No. Mode 1 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 AVCC Vref P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS P54 P55 P56 P57 VSS Pin Name Mode 2 AVCC Vref P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS P54 P55 P56 P57 VSS P80/RFSH/IRQ0 P81/CS3/IRQ1 P82/CS2/IRQ2 P83/CS1/IRQ3 P84/CS0 PA0/TP0/TEND0/TCLKA PA1/TP1/TEND1/TCLKB Mode 3 AVCC Vref P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS A20 A21 A22 A23 VSS P80/RFSH/IRQ0 P81/CS3/IRQ1 P82/CS2/IRQ2 P83/CS1/IRQ3 P84/CS0 PA0/TP0/TEND0/TCLKA PA1/TP1/TEND1/TCLKB PA2/TP2/TIOCA0/TCLKC PA3/TP3/TIOCB0/TCLKD PA4/TP4/TIOCA1 PA5/TP5/TIOCB1 PA6/TP6/TIOCA2 PA7/TP7/TIOCB2 Mode 4 AVCC Vref P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS A20 A21 A22 A23 VSS P80/RFSH/IRQ0 P81/CS3/IRQ1 P82/CS2/IRQ2 P83/CS1/IRQ3 P84/CS0 PA0/TP0/TEND0/TCLKA PA1/TP1/TEND1/TCLKB PA2/TP2/TIOCA0/TCLKC PA3/TP3/TIOCB0/TCLKD PA4/TP4/TIOCA1 PA5/TP5/TIOCB1 PA6/TP6/TIOCA2 PA7/TP7/TIOCB2 100 P80/RFSH/IRQ0 101 P81/CS3/IRQ1 102 P82/CS2/IRQ2 103 P83/CS1/IRQ3 104 P84/CS0 105 PA0/TP0/TEND0/TCLKA 106 PA1/TP1/TEND1/TCLKB 107 PA2/TP2/TIOCA0/TCLKC PA2/TP2/TIOCA0/TCLKC 108 PA3/TP3/TIOCB0/TCLKD PA3/TP3/TIOCB0/TCLKD 109 PA4/TP4/TIOCA1 110 PA5/TP5/TIOCB1 111 PA6/TP6/TIOCA2 112 PA7/TP7/TIOCB2 PA4/TP4/TIOCA1 PA5/TP5/TIOCB1 PA6/TP6/TIOCA2 PA7/TP7/TIOCB2 10 1.4 Pin Functions Table 1-3 summarizes the pin functions. Table 1-3 Pin Functions Pin No. Type Power Symbol VCC QFP-112 1, 44, 76 I/O Input Name and Function Power: For connection to the power supply (+5 V). Connect all VCC pins to the +5-V system power supply. Ground: For connection to ground (0 V). Connect all VSS pins to the 0-V system power supply. For connection to a crystal resonator. For examples of crystal resonator and external clock input, see section 16, Clock Oscillator. For connection to a crystal resonator or input of an external clock signal. For examples of crystal resonator and external clock input, see section 16, Clock Pulse Generator. VSS 10, 26, 35, Input 53, 73, 99 75 Input Clock XTAL EXTAL 74 Input ø Operating mode control 69 Output System clock: Supplies the system clock to external devices Input Mode 2 to mode 0: For setting the operating mode, as follows MD2 0 0 0 0 1 1 1 1 MD1 0 0 1 1 0 0 1 1 MD0 0 1 0 1 0 1 0 1 Operating Mode — Mode 1 Mode 2 Mode 3 Mode 4 — — — MD2 to MD0 83 to 81 11 Table 1-3 Pin Functions (cont) Pin No. Type Symbol QFP-112 71 19 70 67 68 I/O Input Name and Function Reset input: When driven low, this pin resets the H8/3003 System control RES RESO STBY BREQ BACK Output Reset output: Outputs a reset signal to external devices Input Input Standby: When driven low, this pin forces a transition to hardware standby mode Bus request: Used by an external bus master to request the bus right from the H8/3003 Output Bus request acknowledge: Indicates that the bus has been granted to an external bus master Input Nonmaskable interrupt: Requests a nonmaskable interrupt Interrupt request 7 to 0: Maskable interrupt request pins Interrupts NMI IRQ7 to IRQ0 72 18 to 17, Input 25 to 24, 103 to 101 98 to 95, 65 to 54, 52 to 45 43 to 36 34 to 27 Address bus A23 to A0 Output Address bus: Outputs address signals Data bus Bus control D15 to D0 Input/ output Data bus: Bidirectional data bus CS7 to CS0 16 to 13 Output Chip select: Select signals for areas 7 to 0 101 to 104 AS RD HWR 77 78 79 Output Address strobe: Goes low to indicate valid address output on the address bus Output Read: Goes low to indicate reading from the external address space Output High write: Goes low to indicate writing to the external address space; indicates valid data on the upper data bus (D15 to D8). Output Low write: Goes low to indicate writing to the external address space; indicates valid data on the lower data bus (D7 to D0). Input Wait: Requests insertion of wait states in bus cycles during access to the external address space LWR 80 WAIT 66 12 Table 1-3 Pin Functions (cont) Pin No. Type Refresh controller Symbol RFSH CS3 RD QFP-112 100 101 78 I/O Name and Function Output Refresh: Indicates a refresh cycle Output Row address strobe RAS: Row address strobe signal for DRAM connected to area 3 Output Column address strobe CAS: Column address strobe signal for bit DRAM connected to area 3; used with 2WE DRAM. Write enable: Write enable signal for DRAM connected to area 3; used with 2CAS DRAM. HWR 79 Output Upper write: Write enable signal for DRAM connected to area 3; used with 2WE DRAM. Upper column address strobe: Column address strobe signal for DRAM connected to area 3; used with 2CAS DRAM. LWR 80 Output Lower write: Write enable signal for DRAM connected to area 3; used with 2WE DRAM. Lower column address strobe: Column address strobe signal for DRAM connected to area 3; used with 2CAS DRAM. DMA controller (DMAC) DREQ3 to DREQ0 TEND3 to TEND0 TCLKD to TCLKA TIOCA4 to TIOCA0 TIOCB4 to TIOCB0 TOCXA4 TOCXB4 16, 14 9, 8 15, 13, 106, 105 Input DMA request 3 to 0: DMAC activation requests Output Transfer end 3 to 0: These signals indicate that the DMAC has ended a data transfer Clock input A to D: External clock inputs Input capture/output compare A4 to A0: GRA4 to GRA0 output compare or input capture, or PWM output Input capture/output compare B4 to B0: GRB4 to GRB0 output compare or input capture, or PWM output 16-bit integrated time unit (ITU) 108 to 105 Input 4, 2, 111, 109, 107 5, 3, 112, 110, 108 6 7 Input/ output Input/ output Output Output compare XA4: PWM output Output Output compare XB4: PWM output 13 Table 1-3 Pin Functions (cont) Pin No. Type Symbol QFP-112 I/O Name and Function Programmable TP15 to timing pattern TP0 controller (TPC) Serial communication interface (SCI) TxD1, TxD0 RxD1, RxD0 SCK0, SCK1 A/D converter ADTRG AVCC 9 to 2 Output TPC output 15 to 0: Pulse output 112 to 105 21, 20 23, 22 25, 24 Output Transmit data (channels 0 and 1): SCI data output Input Input/ output Input Input Input Receive data (channels 0 and 1): SCI data input Serial clock (channels 0 and 1): SCI clock input/output Analog 7 to 0: Analog input pins A/D trigger: External trigger input for starting A/D conversion Power supply pin for the A/D converter. Connect to the system power supply (+5 V) when not using the A/D converter. Ground pin for the A/D converter. Connect to system ground (0 V) when not using the A/D converter. Reference voltage input pin for the A/D converter. Connect to the system power supply (+5 V) when not using the A/D converter. Port 4: Eight input/output pins. The direction of each pin can be selected in the port 4 data direction register (P4DDR). Port 5: Four input/output pins. The direction of each pin can be selected in the port 5 data direction register (P5DDR). Port 6: Three input/output pins. The direction of each pin can be selected in the port 6 data direction register (P6DDR). Port 7: Eight input pins Port 8: Five input/output pins. The direction of each pin can be selected in the port 8 data direction register (P8DDR). AN7 to AN0 93 to 86 9 84 AVSS 94 Input VREF 85 Input I/O ports P47 to P40 34 to 27 Input/ output Input/ output Input/ output Input P57 to P54 98 to 95 P62 to P60 68 to 66 P77 to P70 P84 to P80 93 to 86 104 to 100 Input/ output 14 Table 1-3 Pin Functions (cont) Pin No. Type I/O ports Symbol P95 to P90 QFP-112 25 to 20 I/O Input/ output Name and Function Port 9: Six input/output pins. The direction of each pin can be selected in the port 9 data direction register (P9DDR). Port A: Eight input/output pins. The direction of each pin can be selected in the port A data direction register (PADDR). Port B: Eight input/output pins. The direction of each pin can be selected in the port B data direction register (PBDDR). Port C: Eight input/output pins. The direction of each pin can be selected in the port C data direction register (PCDDR). PA7 to PA0 112 to 105 Input/ output Input/ output Input/ output PB7 to PB0 9 to 2 PC7 to PC0 18 to 11 15 16 Section 2 CPU 2.1 Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. 2.1.1 Features The H8/300H CPU has the following features. • Upward compatibility with H8/300 CPU Can execute H8/300 series object programs without alteration • General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • Sixty-two basic instructions — 8/16/32-bit arithmetic and logic instructions — Multiply and divide instructions — Powerful bit-manipulation instructions • Eight addressing modes — — — — — — — — • Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn] Absolute address [@aa:8, @aa:16, or @aa:24] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8, PC) or @(d:16, PC)] Memory indirect [@@aa:8] 16-Mbyte linear address space 17 • High-speed operation — — — — — — — All frequently-used instructions execute in two to four states Maximum clock frequency: 16 MHz 8/16/32-bit register-register add/subtract: 125 ns 8 × 8-bit register-register multiply: 875 ns 16 ÷ 8-bit register-register divide: 875 ns 16 × 16-bit register-register multiply: 1.375 µs 32 ÷ 16-bit register-register divide: 1.375 µs • Two CPU operating modes — Normal mode (not available in H8/3003) — Advanced mode • Low-power mode Transition to power-down state by SLEEP instruction 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8/300H has the following enhancements. • More general registers Eight 16-bit registers have been added. • Expanded address space — Advanced mode supports a maximum 16-Mbyte address space. — Normal mode supports the same 64-kbyte address space as the H8/300 CPU. • Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. • Enhanced instructions — Data transfer, arithmetic, and logic instructions can operate on 32-bit data. — Signed multiply/divide instructions and other instructions have been added. 18 2.2 CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. See figure 2-1. The H8/3003 uses only advanced mode. Normal mode * Maximum 64 kbytes, program and data areas combined CPU operating modes Maximum 16 Mbytes, program and data areas combined Advanced mode Note: * Normal mode is not available in the H8/3003. Figure 2-1 CPU Operating Modes 19 2.3 Address Space The maximum address space of the H8/300H CPU is 16 Mbytes. The H8/3003 has two operating modes (MCU modes), one providing a 1-Mbyte address space, the other supporting the full 16 Mbytes. Figure 2-2 shows the H8/3003’s address ranges. For further details see section 3.6, Memory Map in Each Operating Mode. The 1-Mbyte operating mode uses 20-bit addressing. The upper 4 bits of effective addresses are ignored. H'00000 H'000000 H'FFFFF H'FFFFFF a. 1-Mbyte mode b. 16-Mbyte mode Figure 2-2 Memory Map 20 2.4 Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2-3. There are two types of registers: general registers and control registers. General Registers (ERn) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 Control Registers (CR) 23 PC 76543210 CCR I UI H U N Z V C Legend SP: Stack pointer PC: Program counter CCR: Condition code register Interrupt mask bit I: User bit or interrupt mask bit UI: Half-carry flag H: User bit U: Negative flag N: Zero flag Z: Overflow flag V: Carry flag C: 0 E0 E1 E2 E3 E4 E5 E6 E7 (SP) 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Figure 2-3 CPU Registers 21 2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2-4 illustrates the usage of the general registers. The usage of each register can be selected independently. • Address registers • 32-bit registers • 16-bit registers E registers (extended registers) E0 to E7 • 8-bit registers ER registers ER0 to ER7 R registers R0 to R7 RH registers R0H to R7H RL registers R0L to R7L Figure 2-4 Usage of General Registers 22 General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-5 shows the stack. Free area SP (ER7) Stack area Figure 2-5 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition code register (CCR). Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word) or a multiple of 2 bytes, so the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is regarded as 0. Condition Code Register (CCR): This 8-bit register contains internal CPU status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details see section 5, Interrupt Controller. 23 Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of data. Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: • • • Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional branch (Bcc) instructions. For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and UI bits, see section 5, Interrupt Controller. 2.4.4 Initial CPU Register Values In reset exception handling, PC is initialized to a value loaded from the vector table, and the I bit in CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer must therefore be initialized by an MOV.L instruction executed immediately after a reset. 24 2.5 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figures 2-6 and 2-7 show the data formats in general registers. Data Type General Register Data Format 7 0 Don’t care 7 0 1-bit data RnH 76543210 1-bit data RnL 7 Don’t care 43 0 76543210 4-bit BCD data RnH Upper digit Lower digit Don’t care 7 43 0 4-bit BCD data RnL 7 Don’t care 0 Upper digit Lower digit Byte data RnH MSB LSB 7 Don’t care 0 LSB Byte data RnL Don’t care MSB Figure 2-6 General Register Data Formats (1) 25 Data Type General Register Data Format 15 0 LSB 0 LSB 16 15 0 LSB Word data Rn MSB 15 Word data En MSB 31 Longword data ERn MSB Legend ERn: General register En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2-7 General Register Data Formats (2) 2.5.2 Memory Data Formats Figure 2-8 shows the data formats on memory. The H8/300H CPU can access word data and longword data on memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. 26 Data Type Address Data Format 7 1-bit data Byte data Word data Address Address Address 2m Address 2m + 1 Address 2n Longword data Address 2n + 1 Address 2n + 2 Address 2n + 3 MSB 0 6 5 4 3 2 1 0 LSB 7 MSB MSB LSB LSB Figure 2-8 Memory Data Formats When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size. 27 2.6 Instruction Set 2.6.1 Instruction Set Overview The H8/300H CPU has 62 types of instructions, which are classified in table 2-1. Table 2-1 Instruction Classification Function Data transfer Arithmetic operations Logic operations Shift operations Bit manipulation Branch System control Block data transfer Total 62 types Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn. PUSH.W Rn is identical to MOV.W Rn, @–SP. POP.L ERn is identical to MOV.L @SP+, Rn. PUSH.L ERn is identical to MOV.L Rn, @–SP. 2. They are not available on H8/3003. 3. Bcc is a generic branching instruction. Instruction MOV, PUSH*1, POP*1, MOVTPE*2, MOVFPE*2 Types 3 18 4 8 14 5 9 1 ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, MULXS, DIVXS, CMP, NEG, EXTS, EXTU AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc*3, JMP, BSR, JSR, RTS TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP EEPMOV 28 2.6.2 Instructions and Addressing Modes Table 2-2 indicates the instructions available in the H8/300H CPU. Table 2-2 Instructions and Addressing Modes Addressing Modes @ @ (d:16, (d:24, @ERn+/ @ @ERn ERn) ERn) @–ERn aa:8 BWL — — — — — — — — — BWL — — — — — — — — — BWL — — — — — — — — — B — — — — — — — — — @ aa:16 BWL — B — — — — — — — @ @ (d:8, aa:24 PC) BWL — — — — — — — — — — — — — — — — — — — @ (d:16, @@ PC) aa:8 — — — — — — — — — — — — — — — — — — — — Function Data transfer Instruction MOV POP, PUSH MOVFPE, MOVTPE #xx Rn Implied — WL — — — — — — — — BWL BWL BWL — — — — — — Arithmetic ADD, CMP operations SUB BWL BWL — WL BWL — B L — — ADDX, SUBX B ADDS, SUBS — INC, DEC DAA, DAS DIVXU, MULXS, MULXU, DIVXS NEG EXTU, EXTS Logic AND, OR, operations XOR NOT Shift instructions Bit manipulation Branch Bcc, BSR JMP, JSR RTS System control TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP Block data transfer Legend B: Byte W: Word L: Longword — — — BWL — B BW — — — — BWL — WL — — — — — — — — — — — — — — — — — — — — — W W — — — — — — — — — — — — — — — W W — — — — — — — — B — — — — — — — — — — — — — — — — — — — — — — — W W — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — BWL BWL — — — — — — — — — — B — B — — BWL — BWL — B — — — — — — B B — — — — — — — W W — — — B — — — — — — W W — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — W W — — — — — — BW 29 2.6.3 Tables of Instructions Classified by Function Tables 2-3 to 2-10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation Rd Rs Rn ERn (EAd) (EAs) CCR N Z V C PC SP #IMM disp + – × ÷ ∧ ∨ ⊕ → ¬ :3/:8/:16/:24 General register (destination)* General register (source)* General register* General register (32-bit register or address register) Destination operand Source operand Condition code register N (negative) flag of CCR Z (zero) flag of CCR V (overflow) flag of CCR C (carry) flag of CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move NOT (logical complement) 3-, 8-, 16-, or 24-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7). 30 Table 2-3 Data Transfer Instructions Instruction Size* MOV B/W/L Function (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) → Rd Cannot be used in the H8/3003. MOVTPE B Rs → (EAs) Cannot be used in the H8/3003. POP W/L @SP+ → Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. Similarly, POP.L ERn is identical to MOV.L @SP+, ERn. PUSH W/L Rn → @–SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @–SP. Similarly, PUSH.L ERn is identical to MOV.L ERn, @–SP. Note: * Size refers to the operand size. B: Byte W: Word L: Longword 31 Table 2-4 Arithmetic Operation Instructions Instruction Size* ADD, SUB B/W/L Function Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register. Use the SUBX or ADD instruction.) B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd Performs addition or subtraction with carry or borrow on data in two general registers, or on immediate data and data in a general register. B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. B Rd decimal adjust → Rd Decimal-adjusts an addition or subtraction result in a general register by referring to CCR to produce 4-bit BCD data. B/W Rd × Rs → Rd Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. MULXS B/W Rd × Rs → Rd Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. Note: * Size refers to the operand size. B: Byte W: Word L: Longword ADDX, SUBX INC, DEC ADDS, SUBS DAA, DAS MULXU 32 Table 2-4 Arithmetic Operation Instructions (cont) Instruction Size* DIVXU B/W Function Rd ÷ Rs → Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR according to the result. NEG B/W/L 0 – Rd → Rd Takes the two’s complement (arithmetic complement) of data in a general register. EXTS W/L Rd (sign extension) → Rd Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by extending the sign bit. EXTU W/L Rd (zero extension) → Rd Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by padding with zeros. Note: * Size refers to the operand size. B: Byte W: Word L: Longword 33 Table 2-5 Logic Operation Instructions Instruction Size* AND B/W/L Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B/W/L ¬ Rd → Rd Takes the one’s complement of general register contents. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Table 2-6 Shift Instructions Instruction Size* SHAL, SHAR SHLL, SHLR ROTL, ROTR ROTXL, ROTXR B/W/L Function Rd (shift) → Rd Performs an arithmetic shift on general register contents. B/W/L Rd (shift) → Rd Performs a logical shift on general register contents. B/W/L Rd (rotate) → Rd Rotates general register contents. B/W/L Rd (rotate) → Rd Rotates general register contents through the carry bit. Note: * Size refers to the operand size. B: Byte W: Word L: Longword 34 Table 2-7 Bit Manipulation Instructions Instruction Size* BSET B Function 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register. BNOT B ¬ ( of ) → ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register. BTST B ¬ ( of ) → Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register. BAND B C ∧ ( of ) → C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIAND B C ∧ [¬ ( of )] → C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. Note: * Size refers to the operand size. B: Byte 35 Table 2-7 Bit Manipulation Instructions (cont) Instruction Size* BOR B Function C ∨ ( of ) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIOR B C ∨ [¬ ( of )] → C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BXOR B C ⊕ ( of ) → C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ [¬ ( of )] → C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B ( of ) → C Transfers a specified bit in a general register or memory operand to the carry flag. BILD B ¬ ( of ) → C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. BST B C → ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. BIST B C → ¬ ( of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. Note: * Size refers to the operand size. B: Byte 36 Table 2-8 Branching Instructions Instruction Size Bcc — Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS Bcc (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE JMP BSR JSR RTS — — — — Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never C∨Z=0 C∨Z=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 N⊕V=0 N⊕V=1 Z ∨ (N ⊕ V) = 0 Z ∨ (N ⊕ V) = 1 Branches unconditionally to a specified address Branches to a subroutine at a specified address Branches to a subroutine at a specified address Returns from a subroutine 37 Table 2-9 System Control Instructions Instruction Size* TRAPA RTE SLEEP LDC — — — B/W Function Starts trap-instruction exception handling Returns from an exception-handling routine Causes a transition to the power-down state (EAs) → CCR Moves the source operand contents to the condition code register. The condition code register size is one byte, but in transfer from memory, data is read by word access. STC B/W CCR → (EAd) Transfers the CCR contents to a destination location. The condition code register size is one byte, but in transfer to memory, data is written by word access. ANDC B CCR ∧ #IMM → CCR Logically ANDs the condition code register with immediate data. ORC B CCR ∨ #IMM → CCR Logically ORs the condition code register with immediate data. XORC B CCR ⊕ #IMM → CCR Logically exclusive-ORs the condition code register with immediate data. NOP — PC + 2 → PC Only increments the program counter. Note: * Size refers to the operand size. B: Byte W: Word 38 Table 2-10 Block Transfer Instruction Instruction Size EEPMOV.B — Function if R4L ≠ 0 then repeat @ER5+ → @ER6+, R4L – 1 → R4L until R4L = 0 else next; if R4 ≠ 0 then repeat @ER5+ → @ER6+, R4 – 1 → R4 until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6. R4L or R4: Size of block (bytes) ER5: Starting source address ER6: Starting destination address Execution of the next instruction begins as soon as the transfer is completed. EEPMOV.W — 39 2.6.4 Basic Instruction Formats The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (OP field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first 4 bits of the instruction. Some instructions have two operation fields. Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A 24-bit address or displacement is treated as 32-bit data in which the first 8 bits are 0 (H'00). Condition Field: Specifies the branching condition of Bcc instructions. Figure 2-9 shows examples of instruction formats. Operation field only op Operation field and register fields op rn rm ADD.B Rn, Rm, etc. NOP, RTS, etc. Operation field, register fields, and effective address extension op EA (disp) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:8 rn rm MOV.B @(d:16, Rn), Rm Figure 2-9 Instruction Formats 40 2.6.5 Notes on Use of Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the byte, then write the byte back. Care is required when these instructions are used to access registers with write-only bits, or to access ports. The BCLR instruction can be used to clear flags in the on-chip registers. In an interrupt-handling routine, for example, if it is known that the flag is set to 1, it is not necessary to read the flag ahead of time. 2.7 Addressing Modes and Effective Address Calculation 2.7.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2-11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2-11 Addressing Modes No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16, ERn)/@d:24, ERn) @ERn+ @–ERn @aa:8/@aa:16/@aa:24 #xx:8/#xx:16/#xx:32 @(d:8, PC)/@(d:16, PC) @@aa:8 41 1 Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2 Register Indirect—@ERn: The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand. 3 Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit displacement contained in the instruction code is added to the contents of an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum specify the address of a memory operand. A 16-bit displacement is sign-extended when added. 4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the register value should be even. • Register indirect with pre-decrement—@–ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the lower 24 bits of the result become the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the resulting register value should be even. 5 Absolute Address—@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the entire address space. Table 2-12 indicates the accessible address ranges. 42 Table 2-12 Absolute Address Access Ranges Absolute Address 8 bits (@aa:8) 16 bits (@aa:16) 1-Mbyte Modes H'FFF00 to H'FFFFF (1048320 to 1048575) H'00000 to H'07FFF, H'F8000 to H'FFFFF (0 to 32767, 1015808 to 1048575) H'00000 to H'FFFFF (0 to 1048575) 16-Mbyte Modes H'FFFF00 to H'FFFFFF (16776960 to 16777215) H'000000 to H'007FFF, H'FF8000 to H'FFFFFF (0 to 32767, 16744448 to 16777215) H'000000 to H'FFFFFF (0 to 16777215) 24 bits (@aa:24) 6 Immediate—#xx:8, #xx:16, or #xx:32: The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data specifying a vector address. 7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is signextended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an even number. 8 Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The memory operand is accessed by longword access. The first byte of the memory operand is ignored, generating a 24-bit branch address. See figure 2-10. The upper bits of the 8-bit absolute address are assumed to be 0 (H'0000), so the address range is 0 to 255 (H'000000 to H'0000FF). Note that the first part of this range is also the exception vector area. For further details see section 5, Interrupt Controller. 43 Specified by @aa:8 Reserved Branch address Figure 2-10 Memory-Indirect Branch Address Specification When a word-size or longword-size memory operand is specified, or when a branch address is specified, if the specified memory address is odd, the least significant bit is regarded as 0. The accessed data or instruction code therefore begins at the preceding address. See section 2.5.2, Memory Data Formats. 2.7.2 Effective Address Calculation Table 2-13 explains how an effective address is calculated in each addressing mode. In the 1-Mbyte operating modes the upper 4 bits of the calculated address are ignored in order to generate a 20-bit effective address. 44 Table 2-13 Effective Address Calculation Effective Address Calculation Operand is general register contents 31 23 General register contents op 31 General register contents 0 23 0 r 0 0 Effective Address No. Addressing Mode and Instruction Format 1 op rm rn Register direct (Rn) 2 Register indirect (@ERn) 3 Register indirect with displacement @(d:16, ERn)/@(d:24, ERn) op Sign extension disp r disp 45 31 General register contents op 31 General register contents r 1, 2, or 4 op r 1, 2, or 4 4 Register indirect with post-increment or pre-decrement 0 23 0 Register indirect with post-increment @ERn+ Register indirect with pre-decrement @–ERn 0 23 0 1 for a byte operand, 2 for a word operand, 4 for a longword operand Table 2-13 Effective Address Calculation (cont) Effective Address Calculation 23 H'FFFF 87 0 Effective Address No. Addressing Mode and Instruction Format 5 op 23 Sign extension Absolute address @aa:8 abs 16 15 0 @aa:16 op 23 op abs abs 0 @aa:24 46 op IMM 23 PC contents 0 Sign extension 6 Immediate #xx:8, #xx:16, or #xx:32 Operand is immediate data 7 Program-counter relative @(d:8, PC) or @(d:16, PC) 23 disp 0 op disp Table 2-13 Effective Address Calculation (cont) Effective Address Calculation Effective Address No. Addressing Mode and Instruction Format 8 op 23 H'0000 31 23 Memory contents 0 abs 87 0 abs Memory indirect @@aa:8 0 47 Legend r, rm, rn: op: disp: IMM: abs: Register field Operation field Displacement Immediate data Absolute address 2.8 Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2-11 classifies the processing states. Figure 2-13 indicates the state transitions. Processing states Program execution state The CPU executes program instructions in sequence Exception-handling state A transient state in which the CPU executes a hardware sequence (saving PC and CCR, fetching a vector, etc.) in response to a reset, interrupt, or other exception Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU Reset state The CPU and all on-chip supporting modules are initialized and halted Power-down state The CPU is halted to conserve power Sleep mode Software standby mode Hardware standby mode Figure 2-11 Processing States 48 2.8.2 Program Execution State In this state the CPU executes program instructions in normal sequence. 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address. In interrupt and trap exception handling the CPU references the stack pointer (ER7) and saves the program counter and condition code register. Types of Exception Handling and Their Priority: Exception handling is performed for resets, interrupts, and trap instructions. Table 2-14 indicates the types of exception handling and their priority. Trap instruction exceptions are accepted at all times in the program execution state. Table 2-14 Exception Handling Types and Priority Priority Type of Exception Detection Timing High Reset Interrupt Synchronized with clock End of instruction execution or end of exception handling* When TRAPA instruction is executed Start of Exception Handling Exception handling starts immediately when RES changes from low to high When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Exception handling starts when a trap (TRAPA) instruction is executed Trap instruction Low Note: * Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. Figure 2-12 classifies the exception sources. For further details about exception sources, vector numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt Controller. 49 Reset External interrupts Exception sources Interrupt Internal interrupts (from on-chip supporting modules) Trap instruction Figure 2-12 Classification of Exception Sources End of bus release Bus request Program execution state End of bus release Bus request Exception Bus-released state End of exception handling Exception-handling state SLEEP instruction with SSBY = 0 Sleep mode Interrupt NMI, IRQ 0 , IRQ 1, or IRQ 2 interrupt SLEEP instruction with SSBY = 1 Software standby mode RES = 1 STBY = 1, RES = 0 Reset state*1 Hardware standby mode Power-down state *2 Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. Figure 2-13 State Transitions 50 2.8.4 Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is entered when the RES signal goes low. Reset exception handling starts after that, when RES changes from low to high. When reset exception handling starts the CPU fetches a start address from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during the reset exception-handling sequence and immediately after it ends. Interrupt Exception Handling and Trap Instruction Exception Handling: When these exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the program counter and condition code register on the stack. Next, if the UE bit in the system control register (SYSCR) is set to 1, the CPU sets the I bit in the condition code register to 1. If the UE bit is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then the CPU fetches a start address from the exception vector table and execution branches to that address. Figure 2-14 shows the stack after the exception-handling sequence. SP–4 SP–3 SP–2 SP–1 SP (ER7) Stack area SP (ER7) SP+1 SP+2 SP+3 SP+4 CCR PC Even address Before exception handling starts Legend CCR: Condition code register SP: Stack pointer Pushed on stack After exception handling ends Notes: 1. PC is the address of the first instruction executed after the return from the exception-handling routine. 2. Registers must be saved and restored by word access or longword access, starting at an even address. Figure 2-14 Stack Structure after Exception Handling 51 2.8.5 Bus-Released State In this state the bus is released to a bus master other than the CPU, in response to a bus request. The bus masters other than the CPU are the DMA controller, the refresh controller, and an external bus master. While the bus is released, the CPU halts except for internal operations. Interrupt requests are not accepted. For details see section 6.3.7, Bus Arbiter Operation 2.8.6 Reset State When the RES input goes low all current processing stops and the CPU enters the reset state. The I bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details see section 12, Watchdog Timer. 2.8.7 Power-Down State In the power-down state the CPU stops operating to conserve power. There are three modes: sleep mode, software standby mode, and hardware standby mode. Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the SSBY bit is cleared to 0 in the system control register (SYSCR). CPU operations stop immediately after execution of the SLEEP instruction, but the contents of CPU registers are retained. Software Standby Mode: A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states. Hardware Standby Mode: A transition to hardware standby mode is made when the STBY input goes low. As in software standby mode, the CPU and clock halt and the on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. For further information see section 17, Power-Down State. 52 2.9 Basic Operational Timing 2.9.1 Overview The H8/300H CPU operates according to the system clock (ø). The interval from one rise of the system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of two or three states. The CPU uses different methods to access on-chip memory, the on-chip supporting modules, and the external address space. Access to the external address space can be controlled by the bus controller. 2.9.2 On-Chip Memory Access Timing On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and word access. Figure 2-15 shows the on-chip memory access cycle. Figure 2-16 indicates the pin states. Bus cycle T1 state ø Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access) Write data Read data Address T2 state Figure 2-15 On-Chip Memory Access Cycle 53 T1 ø Address bus AS , RD, HWR , LWR Address T2 High High impedance D15 to D0 Figure 2-16 Pin States during On-Chip Memory Access 54 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide, depending on the register being accessed. Figure 2-17 shows the on-chip supporting module access timing. Figure 2-18 indicates the pin states. Bus cycle T1 state ø Address T2 state T3 state Address bus Internal read signal Internal data bus Read access Read data Internal write signal Write access Internal data bus Write data Figure 2-17 Access Cycle for On-Chip Supporting Modules 55 T1 ø Address bus AS , RD, HWR , LWR T2 T3 Address High High impedance D15 to D0 Figure 2-18 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in two or three states. For details see section 6, Bus Controller. 56 Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8/3003 has four operating modes (modes 1 to 4) that are selected by the mode pins (MD2 to MD0) as indicated in table 3-1. The input at these pins determines the size of the address space and the initial bus mode. Table 3-1 Operating Mode Selection Mode Pins Operating Mode — Mode 1 Mode 2 Mode 3 Mode 4 — — — MD2 MD1 MD0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Address Space — 1 Mbyte 1 Mbyte 16 Mbytes 16 Mbytes — — — Description Initial Bus Mode*1 — 8 bits 16 bits 8 bits 16 bits — — — On-Chip RAM — Enabled*2 Enabled*2 Enabled*2 Enabled*2 — — — Notes: 1. In all modes, an 8-bit or 16-bit data bus can be selected on a per-area basis by settings made in the area bus width control register (ABWCR). For details see section 6, Bus Controller. 2. If the RAM enable bit (RAME) in the system control register (SYSCR) is cleared to 0, these addresses become external addresses. For the address space size there are two choices: 1 Mbyte or 16 Mbytes. The external data bus is either 8 or 16 bits wide depending on the settings in the area bus width control register (ABWCR). If 8-bit access is selected for all areas, the external data bus is 8 bits wide. For details see section 6, Bus Controller. Modes 1 to 4 are externally expanded modes that enable access to external memory and peripheral devices. Modes 1 and 2 support a maximum address space of 1 Mbyte. Modes 3 and 4 support a maximum address space of 16 Mbytes. The H8/3003 can only be used in modes 1 to 4. The inputs at the mode pins must select one of these four modes. The inputs at the mode pins must not be changed during operation. 57 3.1.2 Register Configuration The H8/3003 has a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR). Table 3-2 summarizes these registers. Table 3-2 Registers Address* H'FFF1 H'FFF2 Name Mode control register System control register Abbreviation MDCR SYSCR R/W R R/W Initial Value Undetermined H'0B Note: * The lower 16 bits of the address are indicated. 58 3.2 Mode Control Register (MDCR) MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3003. Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 0 — 4 — 0 — Reserved bits 3 — 0 — 2 MDS2 —* R 1 MDS1 —* R 0 MDS0 —* R Reserved bits Mode select 2 to 0 Bits indicating the current operating mode Note: * Determined by pins MD 2 to MD0 . Bits 7 and 6—Reserved: Read-only bits, always read as 1. Bits 5 to 3—Reserved: Read-only bits, always read as 0. Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the logic levels at pins MD2 to MD0 (the current operating mode). MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are read-only bits. The mode pin (MD2 to MD0) levels are latched when MDCR is read. 59 3.3 System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3003. Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W 2 NMIEG 0 R/W 1 — 1 — 0 RAME 1 R/W RAM enable Enables or disables on-chip RAM Reserved bit NMI edge select Selects the valid edge of the NMI input User bit enable Selects whether to use UI bit in CCR 6 as a user bit or an interrupt mask bit Standby timer select 2 to 0 These bits select the waiting time at recovery from software standby mode Software standby Enables transition to software standby mode Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further information about software standby mode see section 17, Power-Down State.) When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear this bit, write 0. Bit 7 SSBY 0 1 Description SLEEP instruction causes transition to sleep mode SLEEP instruction causes transition to software standby mode (Initial value) 60 Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt. Set these bits so that the waiting time will be at least 8 ms at the system clock rate. For further information about waiting time selection, see section 17.4.3, Selection of Oscillator Waiting Time after Exit from Software Standby Mode. Bit 6 STS2 0 0 0 0 1 1 Bit 5 STS1 0 0 1 1 0 1 Bit 4 STS0 0 1 0 1 — — Description Waiting time = 8192 states Waiting time = 16384 states Waiting time = 32768 states Waiting time = 65536 states Waiting time = 131072 states Waiting time = 4 states (Initial value) Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a user bit or an interrupt mask bit. Bit 3 UE 0 1 Description UI bit in CCR is used as an interrupt mask bit UI bit in CCR is used as a user bit (Initial value) Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input. Bit 2 NMIEG 0 1 Description An interrupt is requested at the falling edge of NMI An interrupt is requested at the rising edge of NMI (Initial value) Bit 1—Reserved: Read-only bit, always read as 1. Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized by the rising edge of the RES signal. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) 61 3.4 Operating Mode Descriptions 3.4.1 Mode 1 Address pins A19 to A0 are enabled, permitting access to a maximum 1-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits. 3.4.2 Mode 2 Address pins A19 to A0 are enabled, permitting access to a maximum 1-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits. 3.4.3 Mode 3 Address pins A23 to A0 are enabled, permitting access to a maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits. 3.4.4 Mode 4 Address pins A23 to A0 are enabled, permitting access to a maximum 16-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits. 62 3.5 Pin Functions in Each Operating Mode The pin functions of ports 4 and 5 vary depending on the operating mode. Table 3-3 indicates their functions in each operating mode. Table 3-3 Pin Functions in Each Mode Port Port 4 Port 5 Mode 1 P47 to P40* P57 to P54 Mode 2 D7 to D0* P57 to P54 Mode 3 P47 to P40* A23 to A20 Mode 4 D7 to D0* A23 to A20 Note: * Initial state. The bus mode can be switched by settings in ABWCR. These pins function as P47 to P40 in 8-bit bus mode, and as D7 to D0 in 16-bit bus mode. 3.6 Memory Map in Each Operating Mode Figure 3-1 shows a memory map for modes 1 to 4. The address space is divided into eight areas. The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4. The address locations of the on-chip RAM and on-chip registers differ between the 1-Mbyte modes (modes 1 and 2) and 16-Mbyte modes (modes 3 and 4). The address range specifiable by the CPU in its 8and 16-bit absolute addressing modes (@aa:8 and @aa:16) also differs. 63 Modes 1 and 2 (1-Mbyte modes) H'00000 Vector table H'000000 Modes 3 and 4 (16-Mbyte modes) Vector table H'07FFF Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 16-bit absolute addresses H'007FFFF Area 0 H'1FFFFF H'200000 Area 1 H'3FFFFF H'400000 Area 2 H'5FFFFF H'600000 H'7FFFFF H'800000 H'9FFFFF H'A00000 Area 5 H'BFFFFF H'C00000 External address space 16-bit absolute addresses H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 Area 3 Area 4 H'F8000 H'FFD0F H'FFD10 H'FFF00 H'FFF0F H'FFF10 H'FFF1B H'FFF1C F'FFFFF On-chip RAM* 16-bit absolute addresses 8-bit absolute addresses Area 6 H'DFFFFF H'E00000 Area 7 External address space On-chip registers H'FF8000 H'FFFD0F H'FFFD10 H'FFFF00 H'FFFF0F H'FFFF10 H'FFFF1B H'FFFF1C On-chip registers H'FFFFFF On-chip RAM* 16-bit absolute addresses 8-bit absolute addresses External address space Note: * External addresses can be accessed by clearing the RAME bit to 0 in the system control register (SYSCR). Figure 3-1 Memory Map in Each Operating Mode 64 Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in priority order. Trap instruction exceptions are accepted at all times in the program execution state. Table 4-1 Exception Types and Priority Priority Exception Type High Reset Interrupt Low Start of Exception Handling Starts immediately after a low-to-high transition at the RES pin Interrupt requests are handled when execution of the current instruction or handling of the current exception is completed Trap instruction (TRAPA) Started by execution of a trap instruction (TRAPA) 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows. 1. 2. 3. The program counter (PC) and condition code register (CCR) are pushed onto the stack. The CCR interrupt mask bit is set to 1. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out. 65 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4-1. Different vectors are assigned to different exception sources. Table 4-2 lists the exception sources and their vector addresses. • Reset External interrupts: NMI, IRQ 0 to IRQ7 Exception sources • Interrupts Internal interrupts: 34 interrupts from on-chip supporting modules • Trap instruction Figure 4-1 Exception Sources Table 4-2 Exception Vector Table Exception Source Reset Reserved for system use Vector Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 to 60 Vector Address*1 H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 to H'00F0 to H'00F3 External interrupt (NMI) Trap instruction (4 sources) External interrupt IRQ0 External interrupt IRQ1 External interrupt IRQ2 External interrupt IRQ3 External interrupt IRQ4 External interrupt IRQ5 External interrupt IRQ6 External interrupt IRQ7 Internal interrupts*2 Notes: 1. Lower 16 bits of the address. 2. For the internal interrupt vectors, see section 5.3.3, Interrupt Vector Table. 66 4.2 Reset 4.2.1 Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the H8/3003 enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules. Reset exception handling begins when the RES pin changes from low to high. The H8/3003 can also be reset by overflow of the watchdog timer. For details see section 12, Watchdog Timer. 4.2.2 Reset Sequence The H8/3003 enters the reset state when the RES pin goes low. To ensure that the H8/3003 is reset, hold the RES pin low for at least 20 ms at power-up. To reset the H8/3003 during operation, hold the RES pin low for at least 10 system clock (ø) cycles. See appendix D.2, Pin States at Reset, for the states of the pins in the reset state. When the RES pin goes high after being held low for the necessary time, the H8/3003 starts reset exception handling as follows. • The internal state of the CPU and the registers of the on-chip supporting modules are initialized, and the I bit is set to 1 in CCR. The contents of the reset vector address (H'0000 to H'0003) are read, and program execution starts from the address indicated in the vector address. • Figure 4-2 shows the reset sequence in modes 1 and 3. Figure 4-3 shows the reset sequence in modes 2 and 4. 67 Vector fetch Prefetch of first program instruction Internal processing ø RES Address bus (1) (3) (5) (7) (9) RD Figure 4-2 Reset Sequence (Modes 1 and 3) 68 High (2) (4) (6) (8) HWR , LWR D15 to D8 (10) (1), (3), (5), (7) (2), (4), (6), (8) (9) (10) Address of reset vector: (1) = H'00000, (3) = H'00001, (5) = H'00002, (7) = H'00003 Start address (contents of reset vector) Start address First instruction of program Note: After a reset, the wait-state controller inserts three wait states in every bus cycle. Vector fetch Internal processing Prefetch of first program instruction ø RES Address bus (1) (3) (5) RD HWR , LWR D15 to D0 High (2) (4) (6) (1), (3) (2), (4) (5) (6) Address of reset vector: (1) = H'00000, (3) = H'00002 Start address (contents of reset vector) Start address First instruction of program Note: After a reset, the wait-state controller inserts three wait states in every bus cycle. Figure 4-3 Reset Sequence (Modes 2 and 4) 4.2.3 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. The first instruction of the program is always executed immediately after the reset state ends. This instruction should initialize the stack pointer (example: MOV.L #xx:32, SP). 69 4.3 Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ0 to IRQ7) and 34 internal sources in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources and indicates the number of interrupts of each type. The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), refresh controller, 16-bit integrated timer-pulse unit (ITU), DMA controller (DMAC), serial communication interface (SCI), and A/D converter. Each interrupt source has a separate vector address. NMI is the highest-priority interrupt and is always accepted. Interrupts are controlled by the interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt priority registers A and B (IPRA and IPRB) in the interrupt controller. For details on interrupts see section 5, Interrupt Controller. External interrupts Interrupts NMI (1) IRQ 0 to IRQ 7 (8) WDT *1 (1) Refresh controller *2 (1) ITU (15) DMAC (8) SCI (8) A/D converter (1) Internal interrupts Notes: Numbers in parentheses are the number of interrupt sources. 1. When the watchdog timer is used as an interval timer, it generates an interrupt request at every counter overflow. 2. When the refresh controller is used as an interval timer, it generates an interrupt request at compare match. Figure 4-4 Interrupt Sources and Number of Interrupts 70 4.4 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1 in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, which is specified in the instruction code. 4.5 Stack Status after Exception Handling Figure 4-5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP CCR PC Note: In modes 1 and 2 only 20 PC bits are valid; the upper 4 bits are ignored. Figure 4-5 Stack after Completion of Exception Handling 71 4.6 Notes on Stack Usage When accessing word data or longword data, the H8/3003 regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @–SP) PUSH.L ERn (or MOV.L ERn, @–SP) Use the following instructions to restore registers: POP.W Rn POP.L ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4-6 shows an example of what happens when the SP value is odd. CCR SP PC SP RIL H'FFFEFA H'FFFEFB PC H'FFFEFC H'FFFEFD H'FFFEFF SP TRAPA instruction executed MOV. B RIL, @-ER7 SP set to H'FFFEFF Legend CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Data saved above SP CCR contents lost Note: The diagram illustrates modes 3 and 4. Figure 4-6 Operation when SP Value is Odd 72 Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The interrupt controller has the following features: • Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt priority registers A and B (IPRA and IPRB). • • Three-level masking by the I and UI bits in the CPU condition code register (CCR) Independent vector addresses All interrupts are independently vectored; the interrupt service routine does not have to identify the interrupt source. • Nine external interrupt pins NMI has the highest priority and is always accepted; either the rising or falling edge can be selected. For each of IRQ0 to IRQ7, sensing of the falling edge or level sensing can be selected independently. 73 5.1.2 Block Diagram Figure 5-1 shows a block diagram of the interrupt controller. CPU ISCR NMI input IRQ input OVF TME . . . . . . . ADI ADIE IRQ input section ISR Priority decision logic IER IPRA, IPRB Interrupt request Vector number . . . I Interrupt controller UE SYSCR Legend I: IER: IPRA: IPRB: ISCR: ISR: SYSCR: UE: UI: Interrupt mask bit IRQ enable register Interrupt priority register A Interrupt priority register B IRQ sense control register IRQ status register System control register User bit enable User bit/interrupt mask bit UI CCR Figure 5-1 Interrupt Controller Block Diagram 74 5.1.3 Pin Configuration Table 5-1 lists the interrupt pins. Table 5-1 Interrupt Pins Name Nonmaskable interrupt Abbreviation NMI I/O Input Input Function Nonmaskable interrupt, rising edge or falling edge selectable Maskable interrupts, falling edge or level sensing selectable External interrupt request 7 to 0 IRQ7 to IRQ0 5.1.4 Register Configuration Table 5-2 lists the registers of the interrupt controller. Table 5-2 Interrupt Controller Registers Address*1 H'FFF2 H'FFF4 H'FFF5 H'FFF6 H'FFF8 H'FFF9 Name System control register IRQ sense control register IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B Abbreviation SYSCR ISCR IER ISR IPRA IPRB R/W R/W R/W R/W R/(W)*2 R/W R/W Initial Value H'0B H'00 H'00 H'00 H'00 H'00 Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written, to clear flags. 75 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM. Only bits 3 and 2 are described here. For bits 7 to 4, see section 17.2, Register Configuration. For bit 0, see section 15.2, System Control Register (SYSCR). SYSCR is initialized to H'0B by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W 2 NMIEG 0 R/W 1 — 1 R/W 0 RAME 1 R/W RAM enable Reserved bit Standby timer select 2 to 0 Software standby NMI edge select Selects the NMI input edge User bit enable Selects whether to use CCR bit 6 as a user bit or interrupt mask bit 76 Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3 UE 0 1 Description UI bit in CCR is used as interrupt mask bit UI bit in CCR is used as user bit (Initial value) Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge. Bit 2 NMIEG 0 1 Description Interrupt is requested at falling edge of NMI input Interrupt is requested at rising edge of NMI input (Initial value) 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority. 77 Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit Initial value Read/Write 7 IPRA7 0 R/W 6 IPRA6 0 R/W 5 IPRA5 0 R/W 4 IPRA4 0 R/W 3 IPRA3 0 R/W 2 IPRA2 0 R/W 1 IPRA1 0 R/W 0 IPRA0 0 R/W Priority level A0 Selects the priority level of ITU channel 2 interrupt requests Priority level A1 Selects the priority level of ITU channel 1 interrupt requests Priority level A2 Selects the priority level of ITU channel 0 interrupt requests Priority level A3 Selects the priority level of WDT and refresh controller interrupt requests Priority level A4 Selects the priority level of IRQ4 to IRQ 7 interrupt requests Priority level A5 Selects the priority level of IRQ 2 and IRQ 3 interrupt requests Priority level A6 Selects the priority level of IRQ1 interrupt requests Priority level A7 Selects the priority level of IRQ 0 interrupt requests IPRA is initialized to H'00 by a reset and in hardware standby mode. 78 Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ0 interrupt requests. Bit 7 IPRA7 0 1 Description IRQ0 interrupt requests have priority level 0 (low priority) IRQ0 interrupt requests have priority level 1 (high priority) (Initial value) Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ1 interrupt requests. Bit 6 IPRA6 0 1 Description IRQ1 interrupt requests have priority level 0 (low priority) IRQ1 interrupt requests have priority level 1 (high priority) (Initial value) Bit 5—Priority Level A5 (IPRA5): Selects the priority level of IRQ2 and IRQ3 interrupt requests. Bit 5 IPRA5 0 1 Description IRQ2 and IRQ3 interrupt requests have priority level 0 (low priority) IRQ2 and IRQ3 interrupt requests have priority level 1 (high priority) (Initial value) Bit 4—Priority Level A4 (IPRA4): Selects the priority level of IRQ4 to IRQ7 interrupt requests. Bit 4 IPRA4 0 1 Description IRQ4 to IRQ7 interrupt requests have priority level 0 (low priority) IRQ4 to IRQ7 interrupt requests have priority level 1 (high priority) (Initial value) 79 Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WDT and refresh controller interrupt requests. Bit 3 IPRA3 0 1 Description WDT and refresh controller interrupt requests have priority level 0 (low priority) (Initial value) WDT and refresh controller interrupt requests have priority level 1 (high priority) Bit 2—Priority Level A2 (IPRA2): Selects the priority level of ITU channel 0 interrupt requests. Bit 2 IPRA2 0 1 Description ITU channel 0 interrupt requests have priority level 0 (low priority) ITU channel 0 interrupt requests have priority level 1 (high priority) (Initial value) Bit 1—Priority Level A1 (IPRA1): Selects the priority level of ITU channel 1 interrupt requests. Bit 1 IPRA1 0 1 Description ITU channel 1 interrupt requests have priority level 0 (low priority) ITU channel 1 interrupt requests have priority level 1 (high priority) (Initial value) Bit 0—Priority Level A0 (IPRA0): Selects the priority level of ITU channel 2 interrupt requests. Bit 0 IPRA0 0 1 Description ITU channel 2 interrupt requests have priority level 0 (low priority) ITU channel 2 interrupt requests have priority level 1 (high priority) (Initial value) 80 Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit Initial value Read/Write 7 IPRB7 0 R/W 6 IPRB6 0 R/W 5 IPRB5 0 R/W 4 IPRB4 0 R/W 3 IPRB3 0 R/W 2 IPRB2 0 R/W 1 IPRB1 0 R/W 0 — 0 R/W Reserved bit Priority level B1 Selects the priority level of A/D converter interrupt request Priority level B2 Selects the priority level of SCI channel 1 interrupt requests Priority level B3 Selects the priority level of SCI channel 0 interrupt requests Priority level B4 Selects the priority level of DMAC group 1 interrupt requests (channels 2 and 3) Priority level B5 Selects the priority level of DMAC group 0 interrupt requests (channels 0 and 1) Priority level B6 Selects the priority level of ITU channel 4 interrupt requests Priority level B7 Selects the priority level of ITU channel 3 interrupt requests IPRB is initialized to H'00 by a reset and in hardware standby mode. 81 Bit 7—Priority Level B7 (IPRB7): Selects the priority level of ITU channel 3 interrupt requests. Bit 7 IPRB7 0 1 Description ITU channel 3 interrupt requests have priority level 0 (low priority) ITU channel 3 interrupt requests have priority level 1 (high priority) (Initial value) Bit 6—Priority Level B6 (IPRB6): Selects the priority level of ITU channel 4 interrupt requests. Bit 6 IPRB6 0 1 Description ITU channel 4 interrupt requests have priority level 0 (low priority) ITU channel 4 interrupt requests have priority level 1 (high priority) (Initial value) Bit 5—Priority Level B5 (IPRB5): Selects the priority level of DMAC group 0 interrupt requests (channels 0 and 1). Bit 5 IPRB5 0 1 Description DMAC group 0 interrupt requests (channels 0 and 1) have priority level 0 (low priority) (Initial value) DMAC group 0 interrupt requests (channels 0 and 1) have priority level 1 (high priority) Bit 4—Priority Level B4 (IPRB4): Selects the priority level of DMAC group 1 interrupt requests (channels 2 and 3). Bit 4 IPRB4 0 1 Description DMAC group 1 interrupt requests (channels 2 and 3) have priority level 0 (low priority) (Initial value) DMAC group 1 interrupt requests (channels 2 and 3) have priority level 1 (high priority) 82 Bit 3—Priority Level B3 (IPRB3): Selects the priority level of SCI channel 0 interrupt requests. Bit 3 IPRB3 0 1 Description SCI0 interrupt requests have priority level 0 (low priority) SCI0 interrupt requests have priority level 1 (high priority) (Initial value) Bit 2—Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests. Bit 2 IPRB2 0 1 Description SCI1 interrupt requests have priority level 0 (low priority) SCI1 interrupt requests have priority level 1 (high priority) (Initial value) Bit 1—Priority Level B1 (IPRB1): Selects the priority level of A/D converter interrupt requests. Bit 1 IPRB1 0 1 Description A/D converter interrupt requests have priority level 0 (low priority) A/D converter interrupt requests have priority level 1 (high priority) (Initial value) Bit 0—Reserved: Although reserved, this bit can be written and read. 83 5.2.3 IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ0 to IRQ7 interrupt requests. Bit Initial value Read/Write 7 IRQ7F 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* IRQ 7 to IRQ0 flags These bits indicate IRQ 7 to IRQ 0 interrupt request status Note: * Only 0 can be written, to clear flags. ISR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0—IRQ7 to IRQ0 Flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests. Bits 7 to 0 IRQ7F to IRQ0F 0 Description [Clearing conditions] (Initial value) 0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1. IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out. IRQnSC = 1 and IRQn interrupt exception handling is carried out. [Setting conditions] IRQnSC = 0 and IRQn input is low. IRQnSC = 1 and IRQn input changes from high to low. 1 Note: n = 7 to 0 84 5.2.4 IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ0 to IRQ7 interrupt requests. Bit Initial value Read/Write 7 IRQ7E 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W IRQ 7 to IRQ0 enable These bits enable or disable IRQ 7 to IRQ 0 interrupts IER is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits enable or disable IRQ7 to IRQ0 interrupts. Bits 7 to 0 IRQ7E to IRQ0E 0 1 Description IRQ7 to IRQ0 interrupts are disabled IRQ7 to IRQ0 interrupts are enabled (Initial value) 85 5.2.5 IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ7 to IRQ0. Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC IRQ 7 to IRQ0 sense control These bits select level sensing or falling-edge sensing for IRQ 7 to IRQ 0 interrupts ISCR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0—IRQ7 to IRQ0 Sense Control (IRQ7SC to IRQ0SC): These bits selects whether interrupts IRQ7 to IRQ0 are requested by level sensing of pins IRQ7 to IRQ0, or by falling-edge sensing. Bits 7 to 0 IRQ7SC to IRQ0SC 0 1 Description Interrupts are requested when IRQ7 to IRQ0 inputs are low Interrupts are requested by falling-edge input at IRQ7 to IRQ0 (Initial value) 86 5.3 Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ0 to IRQ7) and 34 internal interrupts. 5.3.1 External Interrupts There are nine external interrupts: NMI, and IRQ0 to IRQ7. Of these, NMI, IRQ0, IRQ1, and IRQ2 can be used to exit software standby mode. NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the I and UI bits in CCR. The NMIEG bit in SYSCR selects whether an interrupt is requested by the rising or falling edge of the input at the NMI pin. NMI interrupt exception handling has vector number 7. IRQ0 to IRQ7 Interrupts: These interrupts are requested by input signals at pins IRQ0 to IRQ7. The IRQ0 to IRQ7 interrupts have the following features. • ISCR settings can select whether an interrupt is requested by the low level of the input at pins IRQ0 to IRQ7, or by the falling edge. IER settings can enable or disable the IRQ0 to IRQ7 interrupts. Interrupt priority levels can be assigned by four bits in IPRA (IPRA7 to IPRA4). The status of IRQ0 to IRQ7 interrupt requests is indicated in ISR. The ISR flags can be cleared to 0 by software. • • Figure 5-2 shows a block diagram of interrupts IRQ0 to IRQ7. IRQnSC IRQnF Edge/level sense circuit IRQn input S R Clear signal Note: n = 7 to 0 Q IRQnE IRQn interrupt request Figure 5-2 Block Diagram of Interrupts IRQ0 to IRQ7 87 Figure 5-3 shows the timing of the setting of the interrupt flags (IRQnF). ø IRQn input pin IRQnF Figure 5-3 Timing of Setting of IRQnF Interrupts IRQ0 to IRQ7 have vector numbers 12 to 19. These interrupts are detected regardless of whether the corresponding pin is set for input or output. When using a pin for external interrupt input, clear its DDR bit to 0 and do not use the pin for chip select output, refresh output, or SCI input or output. 5.3.2 Internal Interrupts Thirty-four internal interrupts are requested from the on-chip supporting modules. • Each on-chip supporting module has status flags for indicating interrupt status, and enable bits for enabling or disabling interrupts. Interrupt priority levels can be assigned in IPRA and IPRB. ITU and SCI interrupt requests can activate the DMAC, in which case no interrupt request is sent to the interrupt controller, and the I and UI bits are disregarded. • • 5.3.3 Interrupt Vector Table Table 5-3 lists the interrupt sources, their vector addresses, and their default priority order. In the default priority order, smaller vector numbers have higher priority. The priority of interrupts other than NMI can be changed in IPRA and IPRB. The priority order after a reset is the default order shown in table 5-3. 88 Table 5-3 Interrupt Sources, Vector Addresses, and Priority Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 WOVI (interval timer) CMI (compare match) Reserved Watchdog timer Refresh controller — Origin External pins Vector Number 7 12 13 14 15 16 17 18 19 20 21 22 23 IMIA0 (compare match/input capture A0) IMIB0 (compare match/input capture B0) OVI0 (overflow 0) Reserved IMIA1 (compare match/input capture A1) IMIB1 (compare match/input capture B1) OVI1 (overflow 1) Reserved IMIA2 (compare match/input capture A2) IMIB2 (compare match/input capture B2) OVI2 (overflow 2) Reserved — — ITU channel 2 — ITU channel 1 ITU channel 0 24 25 26 27 28 29 30 31 32 33 34 35 Vector Address* H'001C to H'001F H'0030 to H'0033 H'0034 to H0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063 H'0064 to H'0067 H'0068 to H'006B H'006C to H'006F H'0070 to H'0073 H'0074 to H'0077 H'0078 to H'007B H'007C to H'007F H'0080 to H'0083 H'0084 to H'0087 H'0088 to H'008B H'008C to H'008F Low IPRA0 IPRA1 IPRA2 IPRA3 IPRA4 IPR — IPRA7 IPRA6 IPRA5 Priority High Note: * Lower 16 bits of the address. 89 Table 5-3 Interrupt Sources, Vector Addresses, and Priority (cont) Interrupt Source IMIA3 (compare match/input capture A3) IMIB3 (compare match/input capture B3) OVI3 (overflow 3) Reserved IMIA4 (compare match/input capture A4) IMIB4 (compare match/input capture B4) OVI4 (overflow 4) Reserved DEND0A DEND0B DEND1A DEND1B DEND2A DEND2B DEND3A DEND3B ERI0 (receive error 0) RXI0 (receive data full 0) TXI0 (transmit data empty 0) TEI0 (transmit end 0) ERI1 (receive error 1) RXI1 (receive data full 1) TXI1 (transmit data empty 1) TEI1 (transmit end 1) ADI (A/D end) A/D SCI channel 1 SCI channel 0 DMAC group 1 — DMAC group 0 — ITU channel 4 Origin ITU channel 3 Vector Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Vector Address* H'0090 to H'0093 H'0094 to H'0097 H'0098 to H'009B H'009C to H'009F H'00A0 to H'00A3 H'00A4 to H'00A7 H'00A8 to H'00AB H'00AC to H'00AF H'00B0 to H'00B3 H'00B4 to H'00B7 H'00B8 to H'00BB H'00BC to H'00BF H'00C0 to H'00C3 IPRB4 H'00C4 to H'00C7 H'00C8 to H'00CB H'00CC to H'00CF H'00D0 to H'00D3 IPRB3 H'00D4 to H'00D7 H'00D8 to H'00DB H'00DC to H'00DF H'00E0 to H'00E3 H'00E4 to H'00E7 H'00E8 to H'00EB H'00EC to H'00EF H'00F0 to H'00F3 IPRB1 Low IPRB2 IPRB5 IPRB6 IPR Priority IPRB7 High Note: * Lower 16 bits of the address. 90 5.4 Interrupt Operation 5.4.1 Interrupt Handling Process The H8/3003 handles interrupts differently depending on the setting of the UE bit. When UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits. Table 5-4 indicates how interrupts are handled for all setting combinations of the UE, I, and UI bits. NMI interrupts are always accepted except in the reset and hardware standby states. IRQ interrupts and interrupts from the on-chip supporting modules have their own enable bits. Interrupt requests are ignored when the enable bits are cleared to 0. Table 5-4 UE, I, and UI Bit Settings and Interrupt Handling SYSCR UE 1 I 0 1 0 0 1 CCR UI — — — 0 1 Description All interrupts are accepted. Interrupts with priority level 1 have higher priority. No interrupts are accepted except NMI. All interrupts are accepted. Interrupts with priority level 1 have higher priority. NMI and interrupts with priority level 1 are accepted. No interrupts are accepted except NMI. UE = 1: Interrupts IRQ0 to IRQ7 and interrupts from the on-chip supporting modules can all be masked by the I bit in the CPU’s CCR. Interrupts are masked when the I bit is set to 1, and unmasked when the I bit is cleared to 0. Interrupts with priority level 1 have higher priority. Figure 5-4 is a flowchart showing how interrupts are accepted when UE = 1. 91 Program execution state No Interrupt requested? Yes Yes NMI No No Priority level 1? Yes No No Pending IRQ 0 Yes IRQ 0 No Yes IRQ 1 Yes IRQ 1 Yes No ADI Yes ADI Yes No I=0 Yes Save PC and CCR I ←1 Read vector address Branch to interrupt service routine Figure 5-4 Process Up to Interrupt Acceptance when UE = 1 92 • If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. When the interrupt controller receives one or more interrupt requests, it selects the highestpriority request, following the IPR interrupt priority settings, and holds other requests pending. If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt controller follows the priority order shown in table 5-3. The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request is accepted. If the I bit is set to 1, only NMI is accepted; other interrupt requests are held pending. When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is saved indicates the address of the first instruction that will be executed after the return from the interrupt service routine. Next the I bit is set to 1 in CCR, masking all interrupts except NMI. The vector address of the accepted interrupt is generated, and the interrupt service routine starts executing from the address indicated by the contents of the vector address. • • • • • • UE = 0: The I and UI bits in the CPU’s CCR and the IPR bits enable three-level masking of IRQ0 to IRQ7 interrupts and interrupts from the on-chip supporting modules. • Interrupt requests with priority level 0 are masked when the I bit is set to 1, and are unmasked when the I bit is cleared to 0. Interrupt requests with priority level 1 are masked when the I and UI bits are both set to 1, and are unmasked when either the I bit or the UI bit is cleared to 0. For example, if the interrupt enable bits of all interrupt requests are set to 1, IPRA is set to H'20, and IPRB is set to H'00 (giving IRQ2 and IRQ3 interrupt requests priority over other interrupts), interrupts are masked as follows: a. If I = 0, all interrupts are unmasked (priority order: NMI > IRQ2 > IRQ3 >IRQ0 …). b. If I = 1 and UI = 0, only NMI, IRQ2, and IRQ3 are unmasked. c. If I = 1 and UI = 1, all interrupts are masked except NMI. • 93 Figure 5-5 shows the transitions among the above states. I←0 a. All interrupts are unmasked I ← 1, UI ← 0 b. Only NMI, IRQ 2 , and IRQ 3 are unmasked I←0 Exception handling, or I ← 1, UI ← 1 UI ← 0 Exception handling, or UI ← 1 c. All interrupts are masked except NMI Figure 5-5 Interrupt Masking State Transitions (Example) Figure 5-6 is a flowchart showing how interrupts are accepted when UE = 0. • If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. When the interrupt controller receives one or more interrupt requests, it selects the highestpriority request, following the IPR interrupt priority settings, and holds other requests pending. If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt controller follows the priority order shown in table 5-3. The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request is accepted regardless of its IPR setting, and regardless of the UI bit. If the I bit is set to 1 and the UI bit is cleared to 0, only NMI and interrupts with priority level 1 are accepted; interrupt requests with priority level 0 are held pending. If the I bit and UI bit are both set to 1, only NMI is accepted; all other interrupt requests are held pending. When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is saved indicates the address of the first instruction that will be executed after the return from the interrupt service routine. The I and UI bits are set to 1 in CCR, masking all interrupts except NMI. The vector address of the accepted interrupt is generated, and the interrupt service routine starts executing from the address indicated by the contents of the vector address. 94 • • • • • • Program execution state No Interrupt requested? Yes Yes NMI No No Priority level 1? Yes No No Pending IRQ 0 Yes IRQ 0 No Yes IRQ 1 Yes IRQ 1 Yes No ADI Yes ADI Yes No I=0 Yes No UI = 0 Yes I=0 Yes No Save PC and CCR I ← 1, UI ← 1 Read vector address Branch to interrupt service routine Figure 5-6 Process Up to Interrupt Acceptance when UE = 0 95 Interrupt accepted 5.4.2 Interrupt Sequence Interrupt level decision and wait for end of instruction Instruction Internal prefetch processing Stack Vector fetch Prefetch of interrupt Internal service routine processing instruction ø Interrupt request signal (1) (3) (5) (7) (9) (11) (13) A19 to A 0 RD High (2) (4) (6) (8) (10) (12) (14) Figure 5-7 shows the interrupt sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Figure 5-7 Interrupt Sequence (Mode 2, Two-State Access, Stack in External Memory) (6), (8) PC and CCR saved to stack (9), (11) Vector address (10), (12) Starting address of interrupt service routine (contents of vector address) (13) Starting address of interrupt service routine; (13) = (10), (12) (14) First instruction of interrupt service routine 96 HWR , LWR D15 to D0 (1) Instruction prefetch address (not executed; return address, same as PC contents) (2), (4) Instruction code (not executed) Instruction prefetch address (not executed) (3) SP – 2 (5) SP – 4 (7) Note: Mode 2, with program code and stack in external memory area accessed in two states via 16-bit bus. 5.4.3 Interrupt Response Time Table 5-5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5-5 Interrupt Response Time External Memory On-Chip Memory 2*1 1 to 23 4 4 4 4 19 to 41 8-Bit Bus 2 States 2*1 1 to 27 8 8 8 4 31 to 57 3 States 2*1 1 to 31*4 12*4 12*4 12*4 4 43 to 73 16-Bit Bus 2 States 2*1 1 to 23 4 4 4 4 19 to 41 3 States 2*1 1 to 25*4 6*4 6*4 6*4 4 25 to 49 No. Item 1 2 3 4 5 6 Total Interrupt priority decision Maximum number of states until end of current instruction Saving PC and CCR to stack Vector fetch Instruction prefetch*2 Internal processing*3 Notes: 1. 1 state for internal interrupts. 2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the interrupt service routine. 3. Internal processing after the interrupt is accepted and internal processing after prefetch. 4. The number of states increases if wait states are inserted in external memory access. 97 5.5 Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR, MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out. If a higher-priority interrupt is also requested, however, interrupt exception handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored. This also applies to the clearing of an interrupt flag. Figure 5-8 shows an example in which an IMIEA bit is cleared to 0 in the ITU. TIER write cycle by CPU ø Internal address bus Internal write signal IMIEA IMIA exception handling TIER address IMIA IMFA interrupt signal Figure 5-8 Contention between Interrupt and Interrupt-Disabling Instruction This type of contention will not occur if the interrupt is masked when the interrupt enable bit or flag is cleared to 0. 98 5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the CPU always continues by executing the next instruction. 5.5.3 Interrupts during EEPMOV Instruction Execution The EEPMOV.B and EEPMOV.W instructions differ in their reaction to interrupt requests. When the EEPMOV.B instruction is executing a transfer, no interrupts are accepted until the transfer is completed, not even NMI. When the EEPMOV.W instruction is executing a transfer, interrupt requests other than NMI are not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts at a transfer cycle boundary. The PC value saved on the stack is the address of the next instruction. Programs should be coded as follows to allow for NMI interrupts during EEPMOV.W execution: L1: EEPMOV.W MOV.W R4,R4 BNE L1 99 100 Section 6 Bus Controller 6.1 Overview The H8/3003 has an on-chip bus controller that divides the address space into eight areas and can assign different bus specifications to each. This enables different types of memory to be connected easily. A bus arbitration function of the bus controller controls the operation of the DMA controller (DMAC) and refresh controller. The bus controller can also release the bus to an external device. 6.1.1 Features Features of the bus controller are listed below. • Independent settings for address areas 0 to 7 — — — — • 128-kbyte areas in 1-Mbyte modes; 2-Mbyte areas in 16-Mbyte modes. Chip select signals (CS0 to CS7) can be output for areas 0 to 7. Areas can be designated for 8-bit or 16-bit access. Areas can be designated for two-state or three-state access. Four wait modes — Programmable wait mode, pin auto-wait mode, and pin wait modes 0 and 1 can be selected. — Zero to three wait states can be inserted automatically. • Bus arbitration function — A built-in bus arbiter grants the bus right to the CPU, DMAC, refresh controller, or an external bus master. 101 6.1.2 Block Diagram Figure 6-1 shows a block diagram of the bus controller. CS0 to CS7 ABWCR Internal address bus ASTCR Area decoder WCER Bus control circuit Internal signals Bus mode control signal Bus size control signal Access state control signal Wait request signal WAIT Wait-state controller WCR Internal signals CPU bus request signal DMAC bus request signal Refresh controller bus request signal CPU bus acknowledge signal DMAC bus acknowledge signal Refresh controller bus acknowledge signal BRCR Bus arbiter BACK Legend ABWCR: ASTCR: WCER: WCR: BRCR: Bus width control register Access state control register Wait state controller enable register Wait control register Bus release control register BREQ Figure 6-1 Block Diagram of Bus Controller 102 Internal data bus 6.1.3 Input/Output Pins Table 6-1 summarizes the bus controller’s input/output pins. Table 6-1 Bus Controller Pins Name Chip select 0 to 7 Address strobe Read High write Abbreviation CS0 to CS7 AS RD HWR I/O Output Output Output Output Function Strobe signals selecting areas 0 to 7 Strobe signal indicating valid address output on the address bus Strobe signal indicating reading from the external address space Strobe signal indicating writing to the external address space, with valid data on the upper data bus (D15 to D8) Strobe signal indicating writing to the external address space, with valid data on the lower data bus (D7 to D0) Wait request signal for access to external threestate-access areas Request signal for releasing the bus to an external device Acknowledge signal indicating the bus is released to an external device Low write LWR Output Wait Bus request Bus acknowledge WAIT BREQ BACK Input Input Output 6.1.4 Register Configuration Table 6-2 summarizes the bus controller’s registers. Table 6-2 Bus Controller Registers Abbreviation R/W ABWCR ASTCR WCR WCER BRCR R/W R/W R/W R/W R/W Initial Value Modes 1 & 3 Modes 2 & 4 H'FF H'FF H'F3 H'FF H'FE H'00 H'FF H'F3 H'FF H'FE Address* H'FFEC H'FFED H'FFEE H'FFEF H'FFF3 Name Bus width control register Access state control register Wait control register Wait state controller enable register Bus release control register Note: * Lower 16 bits of the address. 103 6.2 Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area. Bit Initial Mode 1, 3 value Mode 2, 4 Read/Write 7 ABW7 1 0 R/W 6 ABW6 1 0 R/W 5 ABW5 1 0 R/W 4 ABW4 1 0 R/W 3 ABW3 1 0 R/W 2 ABW2 1 0 R/W 1 ABW1 1 0 R/W 0 ABW0 1 0 R/W Bits selecting bus width for each area When ABWCR contains H'FF (selecting 8-bit access for all areas), the H8/3003 operates in 8-bit bus mode: the upper data bus (D15 to D8) is valid, and port 4 is an input/output port. When at least one bit is cleared to 0 in ABWCR, the H8/3003 operates in 16-bit bus mode with a 16-bit data bus (D15 to D0). In modes 1 and 3, ABWCR is initialized to H'FF by a reset and in hardware standby mode. In modes 2 and 4, ABWCR is initialized to H'00 by a reset and in hardware standby mode. ABWCR is not initialized in software standby mode. Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access or 16-bit access to the corresponding address areas. Bits 7 to 0 ABW7 to ABW0 0 1 Description Areas 7 to 0 are 16-bit access areas Areas 7 to 0 are 8-bit access areas ABWCR specifies the bus width of external memory areas. The bus width of on-chip memory and registers is fixed and does not depend on ABWCR settings. 104 6.2.2 Access State Control Register (ASTCR) ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two states or three states. Bit Initial value Read/Write 7 AST7 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W 3 AST3 1 R/W 2 AST2 1 R/W 1 AST1 1 R/W 0 AST0 1 R/W Bits selecting number of states for access to each area ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is accessed in two or three states. Bits 7 to 0 AST7 to AST0 0 1 Description Areas 7 to 0 are accessed in two states Areas 7 to 0 are accessed in three states (Initial value) ASTCR specifies the number of states in which external areas are accessed. On-chip memory and registers are accessed in a fixed number of states that does not depend on ASTCR settings. 105 6.2.3 Wait Control Register (WCR) WCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller (WSC) and specifies the number of wait states. Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 WMS1 0 R/W 2 WMS2 0 R/W 1 WC1 1 R/W 0 WC0 1 R/W Reserved bits Wait count 1/0 These bits select the number of wait states inserted Wait mode select 1/0 These bits select the wait mode WCR is initialized to H'F3 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 4—Reserved: Read-only bits, always read as 1. Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1/0): These bits select the wait mode. Bit 3 WMS1 0 Bit 2 WMS0 0 1 1 0 1 Description Programmable wait mode No wait states inserted by wait-state controller Pin wait mode 1 Pin auto-wait mode (Initial value) 106 Bits 1 and 0—Wait Count 1 and 0 (WC1/0): These bits select the number of wait states inserted in access to external three-state-access areas. Bit 1 WC1 0 Bit 0 WC0 0 1 1 0 1 Description No wait states inserted by wait-state controller 1 state inserted 2 states inserted 3 states inserted (Initial value) 6.2.4 Wait State Control Enable Register (WCER) WCER is an 8-bit readable/writable register that enables or disables wait-state control of external three-state-access areas by the wait-state controller. Bit Initial value Read/Write 7 WCE7 1 R/W 6 WCE6 1 R/W 5 WCE5 1 R/W 4 WCE4 1 R/W 3 WCE3 1 R/W 2 WCE2 1 R/W 1 WCE1 1 R/W 0 WCE0 1 R/W Wait state controller enable 7 to 0 These bits enable or disable wait-state control WCER is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0—Wait-State Control Enable 7 to 0 (WCE7 to WCE0): These bits enable or disable wait-state control of external three-state-access areas. Bits 7 to 0 WCE7 to WCE0 0 1 Description Wait-state control disabled (pin wait mode 0) Wait-state control enabled (Initial value) 107 6.2.5 Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables or disables release of the bus to an external device. Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — Reserved bits 3 — 1 — 2 — 1 — 1 — 1 — 0 BRLE 0 R/W Bus release enable Enables or disables release of the bus to an external device BRCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 1—Reserved: Read-only bits, always read as 1. Bit 0—Bus Release Enable (BRLE): Enables or disables release of the bus to an external device. Bit 0 BRLE 0 1 Description The bus cannot be released to an external device; BREQ and BACK can be used as input/output pins The bus can be released to an external device (Initial value) 108 6.3 Operation 6.3.1 Area Division The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1-Mbyte modes, or 2 Mbytes in the 16-Mbyte modes. Figure 6-2 shows a general view of the memory map. H'00000 Area 0 (128 kbytes) H'1FFFF H'20000 Area 1 (128 kbytes) H'3FFFF H'40000 Area 2 (128 kbytes) H'5FFFF H'60000 Area 3 (128 kbytes) H'7FFFF H'80000 Area 4 (128 kbytes) H'9FFFF H'A0000 Area 5 (128 kbytes) H'BFFFF H'C0000 Area 6 (128 kbytes) H'DFFFF H'E0000 Area 7 (128 kbytes) On-chip RAM * 1, *2 H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) On-chip RAM * 1, *2 External address space*3 H'FFFFFF On-chip registers* 1 b. 16-Mbyte modes (modes 3 and 4) External address space*3 H'FFFFF On-chip registers * 1 a. 1-Mbyte modes (modes 1 and 2) Notes: 1. The on-chip RAM and on-chip registers have a fixed bus width and are accessed in a fixed number of states. 2. When the RAME bit is cleared to 0 in SYSCR, this area conforms to the specifications of area 7. 3. The 12-byte external address space conforms to the specifications of area 7. Figure 6-2 Access Area Map for Modes 1 to 4 109 Chip select signals (CS0 to CS7) can be output for each area. The bus specifications for each area can be selected in ABWCR, ASTCR, WCER, and WCR as shown in table 6-3. Table 6-3 Bus Specifications ABWCR ASTCR WCER ABWn 0 ASTn 0 1 WCEn — 0 1 WCR WMS1 — — 0 WMS0 — — 0 1 1 0 1 1 0 1 — 0 1 — — 0 — — 0 1 1 0 1 Note: n = 0 to 7 Bus Width 16 16 16 16 16 16 8 8 8 8 8 8 Bus Specifications Access States Wait Mode 2 3 3 3 3 3 2 3 3 3 3 3 Disabled Pin wait mode 0 Programmable wait mode Disabled Pin wait mode 1 Pin auto-wait mode Disabled Pin wait mode 0 Programmable wait mode Disabled Pin wait mode 1 Pin auto-wait mode 110 6.3.2 Chip Select Signals For each of areas 0 to 7, the H8/3003 can output a chip select signal (CS0 to CS7) that goes low to indicate when the area is selected. Figure 6-3 shows the output timing of a CSn signal. Output of the CSn signal is enabled or disabled in the data direction register (DDR) of the corresponding port. A reset leaves pin CS0 in the output state and pins CS1 to CS7 in the input state. To output chip select signals CS1 to CS7, the corresponding DDR bits must be set to 1. For details see section 9, I/O Ports. When the on-chip RAM and on-chip registers are accessed, CS7 goes low but the AS, RD, HWR, and LWR signals remain high. The CSn signals are decoded from the address signals. They can be used as chip select signals for SRAM and other devices. T1 ø T2 T3 Address External address in area n CSn Figure 6-3 CSn Output Timing 111 6.3.3 Data Bus The H8/3003 allows either 8-bit access or 16-bit access to be designated for each of areas 0 to 7. An 8-bit-access area uses the upper data bus (D15 to D8). A 16-bit-access area uses both the upper data bus (D15 to D8) and lower data bus (D7 to D0). In read access the RD signal applies without distinction to both the upper and lower data bus. In write access the HWR signal applies to the upper data bus, and the LWR signal applies to the lower data bus. Table 6-4 indicates how the two parts of the data bus are used under different access conditions. Table 6-4 Access Conditions and Data Bus Usage Area 8-bit-access area Access Read/ Size Write — Read Write Read Valid Address Strobe — — Even Odd Write Even Odd Word Read Write — — HWR LWR RD RD HWR RD Valid Invalid Valid Upper Data Bus (D15 to D8) Valid Lower Data Bus (D7 to D0) Invalid Undetermined data Invalid Valid Undetermined data 16-bit-access Byte area Undetermined data Valid Valid Valid Valid HWR, LWR Valid Note: Undetermined data means that unpredictable data is output. Invalid means that the bus is in the input state and the input is ignored. 112 6.3.4 Bus Control Signal Timing 8-Bit, Three-State-Access Areas: Figure 6-4 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper address bus (D15 to D8) is used to access these areas. The LWR pin is always high. Wait states can be inserted. Bus cycle T1 ø T2 T3 Address bus External address in area n CS n AS RD Read access D15 to D8 Valid D 7 to D 0 HWR Invalid Write access LWR High D15 to D8 Valid D 7 to D 0 Undetermined data Note: n = 7 to 0 Figure 6-4 Bus Control Signal Timing for 8-Bit, Three-State-Access Area 113 8-Bit, Two-State-Access Areas: Figure 6-5 shows the timing of bus control signals for an 8-bit, two-state-access area. The upper address bus (D15 to D8) is used to access these areas. The LWR pin is always high. Wait states cannot be inserted. Bus cycle T1 ø T2 Address bus External address in area n CS n AS RD Read access D15 to D8 Valid D 7 to D 0 HWR Invalid LWR Write access D15 to D8 High Valid D 7 to D 0 Undetermined data Note: n = 7 to 0 Figure 6-5 Bus Control Signal Timing for 8-Bit, Two-State-Access Area 114 16-Bit, Three-State-Access Areas: Figures 6-6 to 6-8 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper address bus (D15 to D8) is used to access even addresses and the lower address bus (D7 to D0) is used to access odd addresses. Wait states can be inserted. Bus cycle T1 ø T2 T3 Address bus Even external address in area n CS n AS RD Read access D15 to D8 Valid D 7 to D 0 HWR Invalid LWR Write access D15 to D8 High Valid D 7 to D 0 Note: n = 7 to 0 Undetermined data Figure 6-6 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1) (Byte Access to Even Address) 115 Bus cycle T1 ø T2 T3 Address bus Odd external address in area n CS n AS RD Read access D15 to D8 Invalid D 7 to D 0 HWR Valid High LWR Write access D15 to D8 Undetermined data D 7 to D 0 Valid Figure 6-7 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2) (Byte Access to Odd Address) 116 Bus cycle T1 ø T2 T3 Address bus External address in area n CS n AS RD Read access D15 to D8 Valid D 7 to D 0 HWR Valid LWR Write access D15 to D8 Valid D 7 to D 0 Valid Figure 6-8 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3) (Word Access) 117 16-Bit, Two-State-Access Areas: Figures 6-9 to 6-11 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper address bus (D15 to D8) is used to access even addresses and the lower address bus (D7 to D0) is used to access odd addresses. Wait states cannot be inserted. Bus cycle T1 ø T2 Address bus Even external address in area n CS n AS RD Read access D15 to D8 Valid D 7 to D 0 HWR Invalid LWR Write access D15 to D8 High Valid D 7 to D 0 Undetermined data Note: n = 7 to 0 Figure 6-9 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1) (Byte Access to Even Address) 118 Bus cycle T1 ø T2 Address bus Odd external address in area n CS n AS RD Read access D15 to D8 Invalid D 7 to D 0 HWR High Valid LWR Write access D15 to D8 Undetermined data D 7 to D 0 Valid Note: n = 7 to 0 Figure 6-10 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2) (Byte Access to Odd Address) 119 Bus cycle T1 ø T2 Address bus External address in area n CS n AS RD Read access D15 to D8 Valid D 7 to D 0 HWR Valid LWR Write access D15 to D8 Valid D 7 to D 0 Valid Note: n = 7 to 0 Figure 6-11 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3) (Word Access) 120 6.3.5 Wait Modes Four wait modes can be selected for each area as shown in table 6-5. Table 6-5 Wait Mode Selection ASTCR WCER WCR Wait Mode No wait states Pin wait mode 0 Programmable wait mode No wait states Pin wait mode 1 Pin auto-wait mode ASTn Bit WCEn Bit WMS1 Bit WMS0 Bit WSC Control 0 1 — 0 1 — — 0 — — 0 1 1 0 1 Note: n = 7 to 0 Disabled Disabled Enabled Enabled Enabled Enabled The ASTn and WCEn bits can be set independently for each area. Bits WMS1 and WMS0 apply to all areas. All areas for which WSC control is enabled operate in the same wait mode. 121 Pin Wait Mode 0: The wait state controller is disabled. Wait states can only be inserted by WAIT pin control. During access to an external three-state-access area, if the WAIT pin is low at the fall of the system clock (ø) in the T2 state, a wait state (TW) is inserted. If the WAIT pin remains low, wait states continue to be inserted until the WAIT signal goes high. Figure 6-12 shows the timing. Inserted by WAIT signal T1 ø T2 TW TW T3 * * * WAIT pin Address bus AS RD Read access Data bus HWR , LWR Write access Data bus Note: * Arrows indicate time of sampling of the WAIT pin. Write data Read data External address Figure 6-12 Pin Wait Mode 0 122 Pin Wait Mode 1: In all accesses to external three-state-access areas, the number of wait states (TW) selected by bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system clock (ø) in the last of these wait states, an additional wait state is inserted. If the WAIT pin remains low, wait states continue to be inserted until the WAIT signal goes high. Pin wait mode 1 is useful for inserting four or more wait states, or for inserting different numbers of wait states for different external devices. If the wait count is 0, this mode operates in the same way as pin wait mode 0. Figure 6-13 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1) and one additional wait state is inserted by WAIT input. Inserted by wait count T1 ø T2 TW Inserted by WAIT signal TW T3 * * WAIT pin Address bus AS RD Read data Data bus HWR , LWR Write access Data bus Note: * Arrows indicate time of sampling of the WAIT pin. Write data External address Read access Figure 6-13 Pin Wait Mode 1 123 Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (TW) selected by bits WC1 and WC0 are inserted. In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock (ø) in the T2 state, the number of wait states (TW) selected by bits WC1 and WC0 are inserted. No additional wait states are inserted even if the WAIT pin remains low. Pin auto-wait mode can be used for an easy interface to low-speed memory, simply by routing the chip select signal to the WAIT pin. Figure 6-14 shows the timing when the wait count is 1. T1 T2 T3 T1 T2 TW T3 ø * * WAIT Address bus External address External address AS RD, RS Read access Data bus Read data Read data HWR , LWR Write access Data bus Write data Write data Note: * Arrows indicate time of sampling of the WAIT pin. Figure 6-14 Pin Auto-Wait Mode 124 Programmable Wait Mode: The number of wait states (TW) selected by bits WC1 and WC0 are inserted in all accesses to external three-state-access areas. Figure 6-15 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1). T1 T2 TW T3 ø Address bus External address AS RD Read access Data bus Read data HWR , LW Write access Data bus Write data Figure 6-15 Programmable Wait Mode 125 Example of Wait State Control Settings: A reset initializes ASTCR and WCER to H'FF and WCR to H'F3, selecting programmable wait mode and three wait states for all areas. Software can select other wait modes for individual areas by modifying the ASTCR, WCER, and WCR settings. Figure 6-16 shows an example of wait mode settings. Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 3-state-access area, programmable wait mode 3-state-access area, programmable wait mode 3-state-access area, pin wait mode 0 3-state-access area, pin wait mode 0 2-state-access area, no wait states inserted 2-state-access area, no wait states inserted 2-state-access area, no wait states inserted 2-state-access area, no wait states inserted Bit: ASTCR H'0F: 7 0 6 0 5 0 4 0 3 1 2 1 1 1 0 1 WCER H'33: 0 0 1 1 0 0 1 1 WCR H'F3: — — — — 0 0 1 1 Note: Wait states cannot be inserted in areas designated for two-state access by ASTCR. Figure 6-16 Wait Mode Settings (Example) 126 6.3.6 Interconnections with Memory (Example) For each area, the bus controller can select two- or three-state access and an 8- or 16-bit data bus width. In three-state-access areas, wait states can be inserted in a variety of modes, simplifying the connection of both high-speed and low-speed devices. Figure 6-18 shows an example of interconnections between the H8/3003 and memory. Figure 6-17 shows a memory map for this example. A 256-kword × 16-bit EPROM is connected to area 0. This device is accessed in three states via a 16-bit bus. Two 32-kword × 8-bit SRAM devices (SRAM1 and SRAM2) are connected to area 1. These devices are accessed in two states via a 16-bit bus. One 32-kword × 8-bit SRAM (SRAM3) is connected to area 7. This device is accessed via an 8-bit bus, using three-state access with an additional wait state inserted in pin auto-wait mode. H'000000 EPROM H'03FFFF Not used H'1FFFFF H'200000 SRAM 1, 2 H'20FFFF H'210000 Not used H'3FFFFF Area 1 16-bit, two-state-access area Area 0 16-bit, three-state-access area H'E00000 SRAM 3 H'E07FFF Not used On-chip RAM H'FFFFFF On-chip registers Area 7 8-bit, three-state-access area (one auto-wait state) Figure 6-17 Memory Map (Example) 127 EPROM A19 to A 1 A 18 to A 0 I/O 15 to I/O8 H8/3003 CS 0 CS 1 CS 7 SRAM1 (even addresses) A15 to A 1 A14 to A 0 I/O 7 to I/O 0 WAIT RD HWR LWR CS OE WE I/O 7 to I/O 0 CE OE SRAM2 (odd addresses) A15 to A 1 A 14 to A 0 I/O 7 to I/O 0 CS OE WE A 23 to A 0 D15 to D 8 D 7 to D 0 SRAM3 A14 to A 0 A 14 to A 0 I/O 7 to I/O 0 CS OE WE Figure 6-18 Interconnections between H8/3003 and Memory (Example) 128 6.3.7 Bus Arbiter Operation The bus controller has a built-in bus arbiter that arbitrates between different bus masters. There are four bus masters: the CPU, DMA controller (DMAC), refresh controller, and an external bus master. When a bus master has the bus right it can carry out read, write, or refresh access. Each bus master uses a bus request signal to request the bus right. At fixed times the bus arbiter determines priority and uses a bus acknowledge signal to grant the bus to a bus master, which can then operate using the bus. The bus arbiter checks whether the bus request signal from a bus master is active or inactive, and returns an acknowledge signal to the bus master if the bus request signal is active. When two or more bus masters request the bus, the highest-priority bus master receives an acknowledge signal. The bus master that receives an acknowledge signal can continue to use the bus until the acknowledge signal is deactivated. The bus master priority order is: (High) External bus master > refresh controller > DMAC > CPU (Low) The bus arbiter samples the bus request signals and determines priority at all times, but it does not always grant the bus immediately, even when it receives a bus request from a bus master with higher priority than the current bus master. Each bus master has certain times at which it can release the bus to a higher-priority bus master. CPU: The CPU is the lowest-priority bus master. If the DMAC, refresh controller, or an external bus master requests the bus while the CPU has the bus right, the bus arbiter transfers the bus right to the bus master that requested it. The bus right is transferred at the following times: • The bus right is transferred at the boundary of a bus cycle. If word data is accessed by two consecutive byte accesses, however, the bus right is not transferred between the two byte accesses. If another bus master requests the bus while the CPU is performing internal operations, such as executing a multiply or divide instruction, the bus right is transferred immediately. The CPU continues its internal operations. If another bus master requests the bus while the CPU is in sleep mode, the bus right is transferred immediately. • • 129 DMAC: When the DMAC receives an activation request, it requests the bus right from the bus arbiter. If DMAC is a bus master and the refresh controller or an external bus master requests the bus, the bus arbiter transfers the bus right from the DMAC to the bus master that requested the bus. The bus right is transferred at the following times. The bus right is transferred when the DMAC finishes transferring 1 byte or 1 word. A DMAC transfer cycle consists of a read cycle and a write cycle. The bus right is not transferred between the read cycle and the write cycle. There is a priority order among the DMAC channels. For details see section 8.4.9, MultipleChannel Operation. Refresh Controller: When a refresh cycle is requested, the refresh controller requests the bus right from the bus arbiter. When the refresh cycle is completed, the refresh controller releases the bus. For details see section 7, Refresh Controller. External Bus Master: When the BRLE bit is set to 1 in BRCR, the bus can be released to an external bus master. The external bus master has highest priority, and requests the bus right from the bus arbiter by driving the BREQ signal low. Once the external bus master gets the bus, it keeps the bus right until the BREQ signal goes high. While the bus is released to an external bus master, the H8/3003 holds the address bus and data bus control signals (AS, RD, HWR, and LWR) in the high-impedance state, and holds the BACK pin in the low output state. The bus arbiter samples the BREQ pin at the rise of the system clock (ø). If BREQ is low, the bus is released to the external bus master at the appropriate opportunity. The BREQ signal should be held low until the BACK signal goes low. When the BREQ pin is high in two consecutive samples, the BACK signal is driven high to end the bus-release cycle. 130 Figure 6-19 shows the timing when the bus right is requested by an external bus master during a read cycle in a two-state-access area. There is a minimum interval of two states from when the BREQ signal goes low until the bus is released. CPU cycles T0 ø T1 T2 External bus released CPU cycles High-impedance Address Data bus (D15 to D0 ) AS , RD High Address High-impedance High-impedance HWR , LWR High-impedance BREQ BACK Minimum 2 cycles 1 1 2 3 4, 5 6 2 3 4 5 6 Low BREQ signal is sampled at rise of T0 state. BACK signal goes low at end of CPU read cycle, releasing bus right to external bus master. BREQ pin continues to be sampled while bus is released to external bus master. High BREQ signal is sampled twice consecutively. BREQ signal goes high, ending bus-release cycle. Figure 6-19 External-Bus-Released State (Two-State-Access Area, During Read Cycle) 131 6.4 Usage Notes 6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM A different bus control signal timing applies when dynamic RAM or pseudo-static RAM is connected to area 3. For details see section 7, Refresh Controller. 6.4.2 Register Write Timing ABWCR, ASTCR, and WCER Write Timing: Data written to ABWCR, ASTCR, or WCER takes effect starting from the next bus cycle. Figure 6-20 shows the timing when an instruction fetched from area 0 changes area 0 from three-state access to two-state access. T1 ø T2 T3 T1 T2 T3 T1 T2 Address 3-state access to area 0 ASTCR address 2-state access to area 0 Figure 6-20 ASTCR Write Timing 132 DDR Write Timing: Data written to a data direction register (DDR) to change a CSn pin from CSn output to generic input, or vice versa, takes effect starting from the T3 state of the DDR write cycle. Figure 6-21 shows the timing when the CS1 pin is changed from generic input to CS1 output. T1 ø T2 T3 Address P8DDR address CS1 High impedance Figure 6-21 DDR Write Timing 6.4.3 BREQ Input Timing After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high level before BACK goes low, the bus arbiter may operate incorrectly. To terminate the external-bus-released state, hold the BREQ signal high for at least three states. If BREQ is high for too short an interval, the bus arbiter may operate incorrectly. 133 134 Section 7 Refresh Controller 7.1 Overview The H8/3003 has an on-chip refresh controller that enables direct connection of 16-bit-wide DRAM or pseudo-static RAM (PSRAM). DRAM or pseudo-static RAM can be directly connected to area 3 of the external address space. A maximum 128 kbytes can be connected in modes 1 and 2 (1-Mbyte modes). A maximum 2 Mbytes can be connected in modes 3 and 4 (16-Mbyte modes). Systems that do not need to refresh DRAM or pseudo-static RAM can use the refresh controller as an 8-bit interval timer. 7.1.1 Features The refresh controller can be used for one of three functions: DRAM refresh control, pseudo-static RAM refresh control, or 8-bit interval timing. Features of the refresh controller are listed below. Features as a DRAM Refresh Controller • • • Enables direct connection of 16-bit-wide DRAM Selection of 2CAS or 2WE mode Selection of 8-bit or 9-bit column address multiplexing for DRAM address input Examples: — 1-Mbit DRAM: 8-bit row address × 8-bit column address — 4-Mbit DRAM: 9-bit row address × 9-bit column address — 4-Mbit DRAM: 10-bit row address × 8-bit column address • • • • CAS-before-RAS refresh control Software-selectable refresh interval Software-selectable self-refresh mode Wait states can be inserted Features as a Pseudo-Static RAM Refresh Controller • • • • RFSH signal output for refresh control Software-selectable refresh interval Software-selectable self-refresh mode Wait states can be inserted 135 Features as an Interval Timer • • • Refresh timer counter (RTCNT) can be used as an 8-bit up-counter Selection of seven counter clock sources: ø/2, ø/8, ø/32, ø/128, ø/512, ø/2048, ø/4096 Interrupts can be generated by compare match between RTCNT and the refresh time constant register (RTCOR) 7.1.2 Block Diagram Figure 7-1 shows a block diagram of the refresh controller. ø/2, ø/8, ø/32, ø/128, ø/512, ø/2048, ø/4096 Refresh signal Clock selector Control logic Comparator CMI interrupt RTMCSR RFSHCR RTCOR RTCNT Module data bus Legend RTCNT: RTCOR: RTMCSR: RFSHCR: Refresh timer counter Refresh time constant register Refresh timer control/status register Refresh control register Figure 7-1 Block Diagram of Refresh Controller 136 Internal data bus Bus interface 7.1.3 Input/Output Pins Table 7-1 summarizes the refresh controller’s input/output pins. Table 7-1 Refresh Controller Pins Signal Pin RFSH HWR LWR RD CS3 Name Refresh Upper write/upper column address strobe Lower write/lower column address strobe Column address strobe/ write enable Row address strobe Abbr. RFSH UW/UCAS LW/LCAS CAS/WE RAS I/O Output Output Output Output Output Function Goes low during refresh cycles; used to refresh DRAM and PSRAM Connects to the UW pin of 2WE DRAM or UCAS pin of 2CAS DRAM Connects to the LW pin of 2WE DRAM or LCAS pin of 2CAS DRAM Connects to the CAS pin of 2WE DRAM or WE pin of 2CAS DRAM Connects to the RAS pin of DRAM 7.1.4 Register Configuration Table 7-2 summarizes the refresh controller’s registers. Table 7-2 Refresh Controller Registers Address* H'FFAC H'FFAD H'FFAE H'FFAF Name Refresh control register Refresh timer control/status register Refresh timer counter Refresh time constant register Abbreviation RFSHCR RTMCSR RTCNT RTCOR R/W R/W R/W R/W R/W Initial Value H'02 H'07 H'00 H'FF Note: * Lower 16 bits of the address. 137 7.2 Register Descriptions 7.2.1 Refresh Control Register (RFSHCR) RFSHCR is an 8-bit readable/writable register that selects the operating mode of the refresh controller. Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 RFSHE 0 R/W 1 — 1 — 0 RCYCE 0 R/W SRFMD PSRAME DRAME CAS/WE M9/M8 Refresh cycle enable Enables or disables insertion of refresh cycles Reserved bit Refresh pin enable Enables refresh signal output from the refresh pin Address multiplex mode select Selects the number of column address bits Strobe mode select Selects 2CAS or 2WE strobing of DRAM PSRAM enable and DRAM enable These bits enable or disable connection of pseudo-static RAM and DRAM Self-refresh mode Selects self-refresh mode RFSHCR is initialized to H'02 by a reset and in hardware standby mode. 138 Bit 7—Self-Refresh Mode (SRFMD): Specifies DRAM or pseudo-static RAM self-refresh during software standby mode. When PSRAME = 1 and DRAME = 0, after the SRFMD bit is set to 1, pseudo-static RAM can be self-refreshed when the H8/3003 enters software standby mode. When PSRAME = 0 and DRAME = 1, after the SRFMD bit is set to 1, DRAM can be selfrefreshed when the H8/3003 enters software standby mode. In either case, the normal access state resumes on exit from software standby mode. Bit 7 SRFMD Description 0 1 DRAM or PSRAM self-refresh is disabled in software standby mode DRAM or PSRAM self-refresh is enabled in software standby mode (Initial value) Bit 6—PSRAM Enable (PSRAME) and Bit 5—DRAM Enable (DRAME): These bits enable or disable connection of pseudo-static RAM and DRAM to area 3 of the external address space. When DRAM or pseudo-static RAM is connected, the bus cycle and refresh cycle of area 3 consist of three states, regardless of the setting in the access state control register (ASTCR). If AST3 = 0 in ASTCR, wait states cannot be inserted. When the PSRAME or DRAME bit is set to 1, bits 0, 2, 3, and 4 in RFSHCR and registers RTMCSR, RTCNT, and RTCOR are write-disabled, except that the CMF flag in RTMCSR can be cleared by writing 0. Bit 6 PSRAME 0 Bit 5 DRAME 0 1 1 0 1 Description Can be used as an interval timer DRAM can be connected PSRAM can be connected Illegal setting (Initial value) 139 Bit 4—Strobe Mode Select (CAS/WE): Selects 2CAS or 2WE mode. The setting of this bit is valid when PSRAME = 0 and DRAME = 1. This bit is write-disabled when the PSRAME or DRAME bit is set to 1. Bit 4 CAS/WE 0 1 Description 2WE mode 2CAS mode (Initial value) Bit 3—Address Multiplex Mode Select (M9/M8): Selects 8-bit or 9-bit column addressing. The setting of this bit is valid when PSRAME = 0 and DRAME = 1. This bit is write-disabled when the PSRAME or DRAME bit is set to 1. Bit 3 M9/M8 0 1 Description 8-bit column address mode 9-bit column address mode (Initial value) Bit 2—Refresh Pin Enable (RFSHE): Enables or disables refresh signal output from the RFSH pin. This bit is write-disabled when the PSRAME or DRAME bit is set to 1. Bit 2 RFSHE 0 1 Description Refresh signal output at the RFSH pin is disabled (the RFSH pin can be used as a generic input/output port) Refresh signal output at the RFSH pin is enabled (Initial value) Bit 1—Reserved: Read-only bit, always read as 1. Bit 0—Refresh Cycle Enable (RCYCE): Enables or disables insertion of refresh cycles. The setting of this bit is valid when PSRAME = 1 or DRAME = 1. When PSRAME = 0 and DRAME = 0, refresh cycles are not inserted regardless of the setting of this bit. Bit 0 RCYCE Description 0 1 Refresh cycles are disabled Refresh cycles are enabled for area 3 (Initial value) 140 7.2.2 Refresh Timer Control/Status Register (RTMCSR) RTMCSR is an 8-bit readable/writable register that selects the clock source for RTCNT. It also enables or disables interrupt requests when the refresh controller is used as an interval timer. Bit Initial value Read/Write 7 CMF 0 R/(W)* 6 CMIE 0 R/W 5 CKS2 0 R/W 4 CKS1 0 R/W 3 CKS0 0 R/W 2 — 1 — 1 — 1 — Reserved bits 0 — 1 — Clock select 2 to 0 These bits select an internal clock source for input to RTCNT Compare match interrupt enable Enables or disables the CMI interrupt requested by CMF Compare match flag Status flag indicating that RTCNT has matched RTCOR Note: * Only 0 can be written, to clear the flag. Bits 7 and 6 are initialized by a reset and in standby mode. Bits 5 to 3 are initialized by a reset and in hardware standby mode, but retain their previous values on transition to software standby mode. Bit 7—Compare Match Flag (CMF): This status flag indicates that the RTCNT and RTCOR values have matched. Bit 7 CMF 0 1 Description [Clearing condition] Cleared by reading CMF when CMF = 1, then writing 0 in CMF [Setting condition] When RTCNT = RTCOR 141 Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt requested when the CMF flag is set to 1 in RTMCSR. The CMIE bit is always cleared to 0 when PSRAME = 1 or DRAME = 1. Bit 6 CMIE 0 1 Description The CMI interrupt requested by CMF is disabled The CMI interrupt requested by CMF is enabled (Initial value) Bits 5 to 3—Clock Select 2 to 0 (CKS2 to CKS0): These bits select an internal clock source for input to RTCNT. When used for refresh control, the refresh controller outputs a refresh request at periodic intervals determined by compare match between RTCNT and RTCOR. When used as an interval timer, the refresh controller generates CMI interrupts at periodic intervals determined by compare match. These bits are write-disabled when the PSRAME bit or DRAME bit is set to 1. Bit 5 CKS2 0 Bit 4 CKS1 0 Bit 3 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Clock input is disabled ø/2 clock source ø/8 clock source ø/32 clock source ø/128 clock source ø/512 clock source ø/2048 clock source ø/4096 clock source (Initial value) Bits 2 to 0—Reserved: Read-only bits, always read as 1. 142 7.2.3 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit readable/writable up-counter. Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W RTCNT is an up-counter that is incremented by an internal clock selected by bits CKS2 to CKS0 in RTMCSR. When RTCNT matches RTCOR (compare match), the CMF flag is set to 1 and RTCNT is cleared to H'00. RTCNT is write-disabled when the PSRAME bit or DRAME bit is set to 1. RTCNT is initialized to H'00 by a reset and in standby mode. 7.2.4 Refresh Time Constant Register (RTCOR) RTCOR is an 8-bit readable/writable register that determines the interval at which RTCNT is cleared. Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W RTCOR and RTCNT are constantly compared. When their values match, the CMF flag is set to 1 in RTMCSR, and RTCNT is simultaneously cleared to H'00. RTCOR is write-disabled when the PSRAME bit or DRAME bit is set to 1. RTCOR is initialized to H'FF by a reset and in hardware standby mode. In software standby mode it retains its previous value. 143 7.3 Operation 7.3.1 Area Division One of three functions can be selected for the H8/3003 refresh controller: interfacing to DRAM connected to area 3, interfacing to pseudo-static RAM connected to area 3, or interval timing. Table 7-3 summarizes the register settings when these three functions are used. Table 7-3 Refresh Controller Settings Usage Register Settings RFSHCR SRFMD PSRAME DRAME CAS/WE M9/M8 RFSHE RCYCE RTCOR RTMCSR CKS2 to CKS0 CMF CMIE P8DDR ABWCR P81DDR ABW3 Set to 1 when RTCNT = RTCOR Cleared to 0 Set to 1 (CS3 output) Cleared to 0 Enables or disables interrupt requests Set to 0 or 1 — DRAM Interface PSRAM Interface Interval Timer Cleared to 0 Cleared to 0 Cleared to 0 — — Cleared to 0 — Interrupt interval setting Selects self-refresh mode Cleared to 0 Set to 1 Selects 2CAS or 2WE mode Selects column addressing mode Set to 1 Cleared to 0 — — Selects RFSH signal output Selects insertion of refresh cycles Refresh interval setting DRAM Interface: To set up area 3 for connection to 16-bit-wide DRAM, initialize RTCOR, RTMCSR, and RFSHCR in that order, clearing bit PSRAME to 0 and setting bit DRAME to 1. Set bit P81DDR to 1 in the port 8 data direction register (P8DDR) to enable CS3 output. In ABWCR, make area 3 a 16-bit-access area. Pseudo-Static RAM Interface: To set up area 3 for connection to pseudo-static RAM, initialize RTCOR, RTMCSR, and RFSHCR in that order, setting bit PSRAME to 1 and clearing bit DRAME to 0. Set bit P81DDR to 1 in P8DDR to enable CS3 output. 144 Interval Timer: When PSRAME = 0 and DRAME = 0, the refresh controller operates as an interval timer. After setting RTCOR, select an input clock in RTMCSR and set the CMIE bit to 1. CMI interrupts will be requested at compare match intervals determined by RTCOR and bits CKS2 to CKS0 in RTMCSR. When setting RTCOR, RTMCSR, and RFSHCR, make sure that PSRAME = 0 and DRAME = 0. Writing is disabled when either of these bits is set to 1. 7.3.2 DRAM Refresh Control Refresh Request Interval and Refresh Cycle Execution: The refresh request interval is determined by the settings of RTCOR and bits CKS2 to CKS0 in RTMCSR. Figure 7-2 illustrates the refresh request interval. RTCOR RTCNT H'00 Refresh request Figure 7-2 Refresh Request Interval (RCYCE = 1) Refresh requests are generated at regular intervals as shown in figure 7-2, but the refresh cycle is not actually executed until the refresh controller gets the bus right. Table 7-4 summarizes the relationship among area 3 settings, DRAM read/write cycles, and refresh cycles. 145 Table 7-4 Area 3 Settings, DRAM Access Cycles, and Refresh Cycles Area 3 Settings 2-state-access area (AST3 = 0) 3-state-access area (AST3 = 1) Read/Write Cycle by CPU or DMAC • 3 states • Wait states cannot be inserted • 3 states • Wait states can be inserted Refresh Cycle • 3 states • Wait states cannot be inserted • 3 states • Wait states can be inserted To insert refresh cycles, set the RCYCE bit to 1 in RFSHCR. Figure 7-3 shows the state transitions for execution of refresh cycles. When the first refresh request occurs after exit from the reset state or standby mode, the refresh controller does not execute a refresh cycle, but goes into the refresh request pending state. Note this point when using a DRAM that requires a refresh cycle for initialization. When a refresh request occurs in the refresh request pending state, the refresh controller acquires the bus right, then executes a refresh cycle. If another refresh request occurs during execution of the refresh cycle, it is ignored. Exit from reset or standby mode Refresh request Refresh request pending state End of refresh cycle* Refresh request Refresh request * Requesting bus right Bus granted Refresh request * Executing refresh cycle Note: * A refresh request is ignored if it occurs while the refresh controller is requesting the bus right or executing a refresh cycle. Figure 7-3 State Transitions for Refresh Cycle Execution 146 Address Multiplexing: Address multiplexing depends on the setting of the M9/M8 bit in RFSHCR, as described in table 7-5. Figure 7-4 shows the address output timing. Address output is multiplexed only in area 3. Table 7-5 Address Multiplexing Address Pins Address signals during row address output A23 to A10 A9 A23 to A10 A9 A9 A8 A8 A9 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 A0 Address signals during M9/M8 = 0 A23 to A10 column address output M9/M8 = 1 A23 to A10 A16 A15 A14 A13 A12 A11 A10 A0 A18 A17 A16 A15 A14 A13 A12 A11 A10 A0 T1 ø T2 T3 A 23 to A 9 , A 0 Address bus A 8 to A 1 A 8 to A1 Row address a. M9/ M8 = 0 A 23 to A 9, A 0 A 16 to A 9 Column address T1 ø T2 T3 A 23 to A10 , A 0 Address bus A 9 to A 1 A 9 to A1 Row address b. M9/ M8 = 1 A 23 to A10 , A 0 A 18 to A 10 Column address Figure 7-4 Multiplexed Address Output (Example without Wait States) 147 2CAS and 2WE Modes: The CAS/WE bit in RFSHCR can select two control modes for 16-bitwide DRAM: one using UCAS and LCAS; the other using UW and LW. These DRAM pins correspond to H8/3003 pins as shown in table 7-6. Table 7-6 DRAM Pins and H8/3003 Pins DRAM Pin H8/3003 Pin HWR LWR RD CS3 CAS/WE = 0 (2WE mode) UW LW CAS RAS CAS/WE = 1 (2CAS mode) UCAS LCAS WE RAS Figure 7-5 (1) shows the interface timing for 2WE DRAM. Figure 7-5 (2) shows the interface timing for 2CAS DRAM. Read cycle Write cycle* Refresh cycle ø Address bus CS 3 (RAS ) RD (CAS ) HWR (UW ) LWR (LW ) RFSH AS Note: * 16-bit access Row Column Row Column Area 3 top address Figure 7-5 DRAM Control Signal Output Timing (1) (2WE Mode) 148 Read cycle Write cycle* Refresh cycle ø Address bus CS3 (RAS ) HWR (UCAS ) LWR (LCAS ) RD (WE ) RFSH AS Note: * 16-bit access Row Column Row Column Area 3 top address Figure 7-5 DRAM Control Signal Output Timing (2) (2CAS Mode) Refresh Cycle Priority Order: When there are simultaneous bus requests, the priority order is: (High) External bus master > refresh controller > DMA controller > CPU (Low) For details see section 6.3.7, Bus Arbiter Operation. Wait State Insertion: When bit AST3 is set to 1 in ASTCR, bus controller settings can cause wait states to be inserted into bus cycles and refresh cycles. For details see section 6.3.5, Wait Modes. 149 Self-Refresh Mode: Some DRAM devices have a self-refresh function. After the SRFMD bit is set to 1 in RFSHCR, when a transition to software standby mode occurs, the CAS and RAS outputs go low in that order so that the DRAM self-refresh function can be used. On exit from software standby mode, the CAS and RAS outputs both go high. Table 7-7 shows the pin states in software standby mode. Figure 7-6 shows the signal output timing. Table 7-7 Pin States in Software Standby Mode (1) (PSRAME = 0, DRAME = 1) Software Standby Mode SRFMD = 0 Signal HWR LWR RD CS3 RFSH CAS/WE = 0 High-impedance High-impedance High-impedance High High CAS/WE = 1 High-impedance High-impedance High-impedance High High SRFMD = 1 (self-refresh mode) CAS/WE = 0 High High Low Low Low CAS/WE = 1 Low Low High Low Low 150 Software standby mode ø Address bus CS 3 (RAS) RD (CAS) High-impedance Oscillator settling time HWR (UW) High LWR (LW) High RFSH a. 2 WE mode (SRFMD = 1) Software standby mode ø High-impedance Oscillator settling time Address CS 3 (RAS) HWR (UCAS) LWR (LCAS) RD (WE) RFSH b. 2 CAS mode (SRFMD = 1) Figure 7-6 Signal Output Timing in Self-Refresh Mode (PSRAME = 0, DRAME = 1) 151 Operation in Power-Down State: The refresh controller operates in sleep mode. It does not operate in hardware standby mode. In software standby mode RTCNT is initialized, but RFSHCR, RTMCSR bits 5 to 3, and RTCOR retain their settings prior to the transition to software standby mode. Example 1: Connection to 2WE 1-Mbit DRAM (1-Mbyte Mode): Figure 7-7 shows typical interconnections to a 2WE 1-Mbit DRAM, and the corresponding address map. Figure 7-8 shows a setup procedure to be followed by a program for this example. After power-up the DRAM must be refreshed to initialize its internal state. Initialization takes a certain length of time, which can be measured by using an interrupt from another timer module, or by counting the number of times RTMCSR bit 7 (CMF) is set. Note that no refresh cycle is executed for the first refresh request after exit from the reset state or standby mode (the first time the CMF flag is set; see figure 7-3). When using this example, check the DRAM device characteristics carefully and use a procedure that fits them. 2 WE 1-Mbit DRAM with × 16-bit organization H8/3003 A8 A7 A6 A5 A4 A3 A2 A1 CS 3 RD HWR LWR D15 to D 0 a. Interconnections (example) A7 A6 A5 A4 A3 A2 A1 A0 RAS CAS UW LW OE I/O 15 to I/O 0 H'60000 DRAM area H'7FFFF b. Address map Area 3 (1-Mbyte mode) Figure 7-7 Interconnections and Address Map for 2WE 1-Mbit DRAM (Example) 152 Set area 3 for 16-bit access Set P81 DDR to 1 for CS3 output Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H'23 in RFSHCR Wait for DRAM to be initialized DRAM can be accessed Figure 7-8 Setup Procedure for 2WE 1-Mbit DRAM (1-Mbyte Mode) 153 Example 2: Connection to 2WE 4-Mbit DRAM (16-Mbyte Mode): Figure 7-9 shows typical interconnections to a single 2WE 4-Mbit DRAM, and the corresponding address map. Figure 7-10 shows a setup procedure to be followed by a program for this example. The DRAM in this example has 10-bit row addresses and 8-bit column addresses. Its address area is H'600000 to H'67FFFF. 2 WE 4-Mbit DRAM with 10-bit row address, 8-bit column address, and × 16-bit organization H8/3003 A18 A17 A8 A7 A6 A5 A4 A3 A2 A1 CS 3 RD HWR LWR D15 to D 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RAS CAS UW LW OE I/O 15 to I/O 0 a. Interconnections (example) H'600000 DRAM area H'67FFFF H'680000 Area 3 (16-Mbyte mode) Not used H'7FFFFF b. Address map Figure 7-9 Interconnections and Address Map for 2WE 4-Mbit DRAM (Example) 154 Set area 3 for 16-bit access Set P81 DDR to 1 for CS3 output Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H'23 in RFSHCR Wait for DRAM to be initialized DRAM can be accessed Figure 7-10 Setup Procedure for 2WE 4-Mbit DRAM with 10-Bit Row Address and 8-Bit Column Address (16-Mbyte Mode) 155 Example 3: Connection to 2CAS 4-Mbit DRAM (16-Mbyte Mode): Figure 7-11 shows typical interconnections to a single 2CAS 4-Mbit DRAM, and the corresponding address map. Figure 7-12 shows a setup procedure to be followed by a program for this example. The DRAM in this example has 9-bit row addresses and 9-bit column addresses. Its address area is H'600000 to H'67FFFF. 2 CAS 4-Mbit DRAM with 9-bit row address, 9-bit column address, and × 16-bit organization H8/3003 A9 A8 A7 A6 A5 A4 A3 A2 A1 CS 3 HWR LWR RD D15 to D 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 RAS UCAS LCAS WE OE I/O 15 to I/O 0 a. Interconnections (example) H'600000 DRAM area H'67FFFF H'680000 Not used Area 3 (16-Mbyte mode) H'7FFFFF b. Address map Figure 7-11 Interconnections and Address Map for 2CAS 4-Mbit DRAM (Example) 156 Set area 3 for 16-bit access Set P81 DDR to 1 for CS3 output Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H'3B in RFSHCR Wait for DRAM to be initialized DRAM can be accessed Figure 7-12 Setup Procedure for 2CAS 4-Mbit DRAM with 9-Bit Row Address and 9-Bit Column Address (16-Mbyte Mode) 157 Example 4: Connection to Two 4-Mbit DRAM Chips (16-Mbyte Mode): Figure 7-13 shows an example of interconnections to two 2CAS 4-Mbit DRAM chips, and the corresponding address map. Up to four DRAM chips can be connected to area 3 by decoding upper address bits A19 and A20. Figure 7-14 shows a setup procedure to be followed by a program for this example. The DRAM in this example has 9-bit row addresses and 9-bit column addresses. Both chips must be refreshed simultaneously, so the RFSH pin must be used. 2 CAS 4-Mbit DRAM with 9-bit row address, 9-bit column address, and × 16-bit organization H8/3003 A19 A 9 to A 1 A 8 to A 0 RAS UCAS LCAS WE OE I/O15 to I/O 0 No. 1 A 8 to A 0 CS 3 HWR LWR RD RFSH D15 to D 0 a. Interconnections (example) H'600000 H'67FFFF H'680000 H'6FFFFF H'700000 No. 1 DRAM area No. 2 DRAM area Area 3 (16-Mbyte mode) Not used H'7FFFFF b. Address map RAS UCAS LCAS WE OE I/O15 to I/O 0 No. 2 Figure 7-13 Interconnections and Address Map for Multiple 2CAS 4-Mbit DRAM Chips (Example) 158 Set area 3 for 16-bit access Set P81 DDR to 1 for CS 3 output Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H'3F in RFSHCR Wait for DRAM to be initialized DRAM can be accessed Figure 7-14 Setup Procedure for Multiple 2CAS 4-Mbit DRAM Chips with 9-Bit Row Address and 9-Bit Column Address (16-Mbyte Mode) 159 7.3.3 Pseudo-Static RAM Refresh Control Refresh Request Interval and Refresh Cycle Execution: The refresh request interval is determined as in a DRAM interface, by the settings of RTCOR and bits CKS2 to CKS0 in RTMCSR. The numbers of states required for pseudo-static RAM read/write cycles and refresh cycles are the same as for DRAM (see table 7-4). The state transitions are as shown in figure 7-3. Pseudo-Static RAM Control Signals: Figure 7-15 shows the control signals for pseudo-static RAM read, write, and refresh cycles. Read cycle ø Address bus CS 3 RD HWR LWR RFSH AS Write cycle * Refresh cycle Area 3 top address Note: * 16-bit access Figure 7-15 Pseudo-Static RAM Control Signal Output Timing 160 Refresh Cycle Priority Order: When there are simultaneous bus requests, the priority order is: (High) External bus master > refresh controller > DMA controller > CPU (Low) For details see section 6.3.7, Bus Arbiter Operation. Wait State Insertion: When bit AST3 is set to 1 in ASTCR, the wait state controller (WSC) can insert wait states into bus cycles and refresh cycles. For details see section 6.3.5, Wait Modes. Self-Refresh Mode: Some pseudo-static RAM devices have a self-refresh function. After the SRFMD bit is set to 1 in RFSHCR, when a transition to software standby mode occurs, the H8/3003’s CS3 output goes high and its RFSH output goes low so that the pseudo-static RAM self-refresh function can be used. On exit from software standby mode, the RFSH output goes high. Table 7-8 shows the pin states in software standby mode. Figure 7-16 shows the signal output timing. Table 7-8 Pin States in Software Standby Mode (2) (PSRAME = 1, DRAME = 0) Software Standby Mode Signal CS3 RD HWR LWR RFSF SRFMD = 0 High High-impedance High-impedance High-impedance High SRFMD = 1 (self-refresh mode) High High-impedance High-impedance High-impedance Low 161 Software standby mode ø Address bus CS 3 RD HWR LWR RFSH High High-impedance High-impedance High-impedance High-impedance Oscillator settling time Figure 7-16 Signal Output Timing in Self-Refresh Mode (PSRAME = 1, DRAME = 0) Operation in Power-Down State: The refresh controller operates in sleep mode. It does not operate in hardware standby mode. In software standby mode RTCNT is initialized, but RFSHCR, RTMCSR bits 5 to 3, and RTCOR retain their settings prior to the transition to software standby mode. 162 Example: Pseudo-static RAM may have separate OE and RFSH pins, or these may be combined into a single OE/RFSH pin. Figure 7-17 shows an example of a circuit for generating an OE/RFSH signal. Check the device characteristics carefully, and design a circuit that fits them. Figure 7-18 shows a setup procedure to be followed by a program. LSI PSRAM RD OE / RFSH RFSH Figure 7-17 Interconnection to Pseudo-Static RAM with OE/RFSH Signal (Example) 163 Set P81 DDR to 1 for CS 3 output Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H'47 in RFSHCR Wait for PSRAM to be initialized PSRAM can be accessed Figure 7-18 Setup Procedure for Pseudo-Static RAM 164 7.3.4 Interval Timing To use the refresh controller as an interval timer, clear the PSRAME and DRAME both to 0. After setting RTCOR, select a clock source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit to 1. Timing of Setting of Compare Match Flag and Clearing by Compare Match: The CMF flag in RTCSR is set to 1 by a compare match signal output when the RTCOR and RTCNT values match. The compare match signal is generated in the last state in which the values match (when RTCNT is updated from the matching value to a new value). Accordingly, when RTCNT and RTCOR match, the compare match signal is not generated until the next counter clock pulse. Figure 7-19 shows the timing. ø RTCNT N H'00 RTCOR Compare match signal CMF flag N Figure 7-19 Timing of Setting of CMF Flag Operation in Power-Down State: The interval timer function operates in sleep mode. It does not operate in hardware standby mode. In software standby mode RTCNT and RTMCSR bits 7 and 6 are initialized, but RTMCSR bits 5 to 3 and RTCOR retain their settings prior to the transition to software standby mode. 165 Contention between RTCNT Write and Counter Clear: If a counter clear signal occurs in the T3 state of an RTCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 7-20. RTCNT write cycle by CPU T1 T2 T3 ø Address RTCNT address Internal write signal Counter clear signal RTCNT N H'00 Figure 7-20 Contention between RTCNT Write and Clear 166 Contention between RTCNT Write and Increment: If an increment pulse occurs in the T3 state of an RTCNT write cycle, writing takes priority and RTCNT is not incremented. See figure 7-21. RTCNT write cycle by CPU T1 T2 T3 ø Address RTCNT address Internal write signal RTCNT input clock RTCNT N M Counter write data Figure 7-21 Contention between RTCNT Write and Increment 167 Contention between RTCOR Write and Compare Match: If a compare match occurs in the T3 state of an RTCOR write cycle, writing takes priority and the compare match signal is inhibited. See figure 7-22. RTCOR write cycle by CPU T1 T2 T3 ø Address RTCOR address Internal write signal RTCNT N N+1 RTCOR N M RTCOR write data Compare match signal Inhibited Figure 7-22 Contention between RTCOR Write and Compare Match RTCNT Operation at Internal Clock Source Switchover: Switching internal clock sources may cause RTCNT to increment, depending on the switchover timing. Table 7-9 shows the relation between the time of the switchover (by writing to bits CKS2 to CKS0) and the operation of RTCNT. The RTCNT input clock is generated from the internal clock source by detecting the falling edge of the internal clock. If a switchover is made from a high clock source to a low clock source, as in case No. 3 in table 7-9, the switchover will be regarded as a falling edge, an RTCNT clock pulse will be generated, and RTCNT will be incremented. 168 Table 7-9 Internal Clock Switchover and RTCNT Operation No. 1 CKS2 to CKS0 Write Timing Low → low switchover*1 Old clock source New clock source RTCNT clock RTCNT Operation RTCNT N CKS bits rewritten N+1 2 Low → high switchover*2 Old clock source New clock source RTCNT clock RTCNT N N+1 N+2 CKS bits rewritten Notes: 1. Including switchovers from a low clock source to the halted state, and from the halted state to a low clock source. 2. Including switchover from the halted state to a high clock source. 169 Table 7-9 Internal Clock Switchover and RTCNT Operation (cont) No. 3 CKS2 to CKS0 Write Timing High → low switchover*1 Old clock source New clock source RTCNT clock *2 RTCNT Operation RTCNT N N+1 CKS bits rewritten N+2 4 High → high switchover Old clock source New clock source RTCNT clock RTCNT N N+1 N+2 CKS bits rewritten Notes: 1. Including switchover from a high clock source to the halted state. 2. The switchover is regarded as a falling edge, causing RTCNT to increment. 170 7.4 Interrupt Source Compare match interrupts (CMI) can be generated when the refresh controller is used as an interval timer. Compare match interrupt requests are masked/unmasked with the CMIE bit of RTMCSR. 7.5 Usage Notes When using the DRAM or pseudo-static RAM refresh function, note the following points: • Refresh cycles are not executed while the bus is released, during software standby mode, and when a bus cycle is greatly prolonged by insertion of wait states. When these conditions occur, other means of refreshing are required. If refresh requests occur while the bus is released, the first request is held and one refresh cycle is executed after the bus-released state ends. Figure 7-23 shows the bus cycles in this case. • Bus-released state ø RFSH Refresh request BACK Refresh cycle CPU cycle Refresh cycle Figure 7-23 Refresh Cycles when Bus is Released 171 • If a bus cycle is prolonged by insertion of wait states, the first refresh request is held, as in the bus-released state. If contention occurs between a transition to software standby mode and a bus request from an external bus master, the bus may be released for one state just before the transition to software standby mode (see figure 7-24). When using software standby mode, clear the BRLE bit to 0 in BRCR before executing the SLEEP instruction. If similar contention occurs in a transition to self-refresh mode, strobe waveforms may not be output correctly. This can also be prevented by clearing the BRLE bit to 0 in BRCR. • Bus-released state ø Software standby mode BREQ BACK Address Strobe Figure 7-24 Contention between Bus-Released State and Software Standby Mode 172 Section 8 DMA Controller 8.1 Overview The H8/3003 has an on-chip DMA controller (DMAC) that can transfer data on up to eight channels. 8.1.1 Features DMAC features are listed below. • Selection of short address mode or full address mode Short address mode — 8-bit source address and 24-bit destination address, or vice versa — Maximum eight channels available — Selection of I/O mode, idle mode, or repeat mode Full address mode — 24-bit source and destination addresses — Maximum four channels available — Selection of normal mode or block transfer mode • • • Directly addressable 16-Mbyte address space Selection of byte or word transfer Activation by internal interrupts, external requests, or auto-request (depending on transfer mode) — — — — ITU compare match/input capture interrupts (four) SCI transmit-data-empty/receive-data-full interrupts External requests Auto-request 173 8.1.2 Block Diagram Figure 8-1 shows a DMAC block diagram. The DMAC is divided into two groups (group 0 and group 1) of four channels each. Internal address bus Internal interrupts IMIA0 IMIA1 IMIA2 IMIA3 TXI0 RXI0 DREQ0 DREQ1 TEND0 TEND1 Control logic Channel 0 Address buffer Arithmetic-logic unit MAR0A Channel 0A IOAR0A Module data bus ETCR0A MAR0B Channel 0B DTCR0A DTCR0B DTCR1A DTCR1B Channel 1 Channel 1B Channel 1A IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B Interrupt DEND0A DEND0B signals DEND1A DEND1B Data buffer Internal data bus Legend DTCR: Data transfer control register MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register Figure 8-1 Block Diagram of DMA Controller (Group 0: Four Channels) 174 8.1.3 Functional Overview Table 8-1 gives an overview of the DMAC functions. Table 8-1 DMAC Functional Overview Address Reg. Length Transfer Mode Short I/O mode address • Transfers one byte or one word mode per request • Increments or decrements the memory address by 1 or 2 • Executes 1 to 65,536 transfers Idle mode • Transfers one byte or one word per request • Holds the memory address fixed • Executes 1 to 65,536 transfers Repeat mode • Transfers one byte or one word per request • Increments or decrements the memory address by 1 or 2 • Executes a specified number (1 to 255) of transfers, then returns to the initial state and continues Full address mode Normal mode • Auto-request — Retains the transfer request internally — Executes a specified number (1 to 65,536) of transfers continuously — Selection of burst mode or cycle-steal mode • External request — Transfers one byte or one word per request — Executes 1 to 65,536 transfers Block transfer • Transfers one block of a specified size per request • Executes 1 to 65,536 transfers • Allows either the source or destination to be a fixed block area • Block size can be 1 to 255 bytes or words Activation DestinaSource tion 8 • Compare match/input 24 capture A interrupts from ITU channels 0 to 3 • Transmit-data-empty interrupt from serial communication interface • Receive-data-full interrupt from serial communication interface • External request 8 24 24 8 • Auto-request • External request 24 24 • Compare match/ input capture A interrupts from ITU channels 0 to 3 • External request 24 24 175 8.1.4 Input/Output Pins Table 8-2 lists the DMAC pins. Table 8-2 DMAC Pins Group Channel 0 0 Name DMA request 0 Transfer end 0 1 DMA request 1 Transfer end 1 1 2 DMA request 2 Transfer end 2 3 DMA request 3 Transfer end 3 Abbrevia- Input/ tion Output DREQ0 TEND0 DREQ1 TEND1 DREQ2 TEND2 DREQ3 TEND3 Input Output Input Output Input Output Input Output Function External request for DMAC channel 0 Transfer end on DMAC channel 0 External request for DMAC channel 1 Transfer end on DMAC channel 1 External request for DMAC channel 2 Transfer end on DMAC channel 2 External request for DMAC channel 3 Transfer end on DMAC channel 3 Note: External requests cannot be made to channel A in short address mode. 8.1.5 Register Configuration Table 8-3 lists the DMAC registers. 176 Table 8-3 DMAC Registers Group Channel 0 0 Address* H'FF20 H'FF21 H'FF22 H'FF23 H'FF26 H'FF24 H'FF25 H'FF27 H'FF28 H'FF29 H'FF2A H'FF2B H'FF2E H'FF2C H'FF2D H'FF2F 1 H'FF30 H'FF31 H'FF32 H'FF33 H'FF36 H'FF34 H'FF35 H'FF37 H'FF38 H'FF39 H'FF3A H'FF3B H'FF3E H'FF3C H'FF3D H'FF3F Name Memory address register 0AR Memory address register 0AE Memory address register 0AH Memory address register 0AL I/O address register 0A Execute transfer count register 0AH Execute transfer count register 0AL Data transfer control register 0A Memory address register 0BR Memory address register 0BE Memory address register 0BH Memory address register 0BL I/O address register 0B Execute transfer count register 0BH Execute transfer count register 0BL Data transfer control register 0B Memory address register 1AR Memory address register 1AE Memory address register 1AH Memory address register 1AL I/O address register 1A Execute transfer count register 1AH Execute transfer count register 1AL Data transfer control register 1A Memory address register 1BR Memory address register 1BE Memory address register 1BH Memory address register 1BL I/O address register 1B Execute transfer count register 1BH Execute transfer count register 1BL Data transfer control register 1B Abbreviation MAR0AR MAR0AE MAR0AH MAR0AL IOAR0A ETCR0AH ETCR0AL DTCR0A MAR0BR MAR0BE MAR0BH MAR0BL IOAR0B ETCR0BH ETCR0BL DTCR0B MAR1AR MAR1AE MAR1AH MAR1AL IOAR1A ETCR1AH ETCR1AL DTCR1A MAR1BR MAR1BE MAR1BH MAR1BL IOAR1B ETCR1BH ETCR1BL DTCR1B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined H'00 Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined H'00 Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined H'00 Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined H'00 Note: * The lower 16 bits of the address are indicated. 177 Table 8-3 DMAC Registers (cont) Group Channel 1 2 Address* H'FF40 H'FF41 H'FF42 H'FF43 H'FF46 H'FF44 H'FF45 H'FF47 H'FF48 H'FF49 H'FF4A H'FF4B H'FF4E H'FF4C H'FF4D H'FF4F 3 H'FF50 H'FF51 H'FF52 H'FF53 H'FF56 H'FF54 H'FF55 H'FF57 H'FF58 H'FF59 H'FF5A H'FF5B H'FF5E H'FF5C H'FF5D H'FF5F Name Memory address register 2AR Memory address register 2AE Memory address register 2AH Memory address register 2AL I/O address register 2A Execute transfer count register 2AH Execute transfer count register 2AL Data transfer control register 2A Memory address register 2BR Memory address register 2BE Memory address register 2BH Memory address register 2BL I/O address register 2B Execute transfer count register 2BH Execute transfer count register 2BL Data transfer control register 2B Memory address register 3AR Memory address register 3AE Memory address register 3AH Memory address register 3AL I/O address register 3A Execute transfer count register 3AH Execute transfer count register 3AL Data transfer control register 3A Memory address register 3BR Memory address register 3BE Memory address register 3BH Memory address register 3BL I/O address register 3B Execute transfer count register 3BH Execute transfer count register 3BL Data transfer control register 3B Abbreviation MAR2AR MAR2AE MAR2AH MAR2AL IOAR2A ETCR2AH ETCR2AL DTCR2A MAR2BR MAR2BE MAR2BH MAR2BL IOAR2B ETCR2BH ETCR2BL DTCR2B MAR3AR MAR3AE MAR3AH MAR3AL IOAR3A ETCR3AH ETCR3AL DTCR3A MAR3BR MAR3BE MAR3BH MAR3BL IOAR3B ETCR3BH ETCR3BL DTCR3B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined H'00 Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined H'00 Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined H'00 Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined H'00 Note: * The lower 16 bits of the address are indicated. 178 8.2 Register Descriptions (1) (Short Address Mode) In short address mode, transfers can be carried out independently on channels A and B. Short address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA) as indicated in table 8-4. Table 8-4 Selection of Short and Full Address Modes Channel 0 Bit 2 DTS2A 1 Bit 1 DTS1A 1 Description DMAC channel 0 operates as one channel in full address mode DMAC channels 0A and 0B operate as two independent channels in short address mode DMAC channel 1 operates as one channel in full address mode DMAC channels 1A and 1B operate as two independent channels in short address mode DMAC channel 2 operates as one channel in full address mode DMAC channels 2A and 2B operate as two independent channels in short address mode DMAC channel 3 operates as one channel in full address mode DMAC channels 3A and 3B operate as two independent channels in short address mode Other than above 1 1 1 Other than above 2 1 1 Other than above 3 1 1 Other than above 179 8.2.1 Memory Address Registers (MAR) A memory address register (MAR) is a 32-bit readable/writable register that specifies a source or destination address. The transfer direction is determined automatically from the activation source. An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits of MARR are reserved: they cannot be modified and always read 1. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Read/Write Undetermined — — — — — — — — R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W MARR MARE MARH MARL Source or destination address An MAR functions as a source or destination address register depending on how the DMAC is activated: as a destination address register if activation is by a receive-data-full interrupt from the serial communication interface (SCI), and as a source address register otherwise. The MAR value is incremented or decremented each time one byte or word is transferred, automatically updating the source or destination memory address. For details, see section 8.2.4, Data Transfer Control Registers (DTCR). The MARs are not initialized by a reset or in standby mode. 180 8.2.2 I/O Address Registers (IOAR) An I/O address register (IOAR) is an 8-bit readable/writable register that specifies a source or destination address. The IOAR value is the lower 8 bits of the address. The upper 16 address bits are all 1 (H'FFFF). Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W Source or destination address An IOAR functions as a source or destination address register depending on how the DMAC is activated: as a source address register if activation is by a receive-data-full interrupt from the SCI, and as a destination address register otherwise. The IOAR value is held fixed. It is not incremented or decremented when a transfer is executed. The IOARs are not initialized by a reset or in standby mode. 8.2.3 Execute Transfer Count Registers (ETCR) An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the number of transfers to be executed. These registers function in one way in I/O mode and idle mode, and another way in repeat mode. • I/O mode and idle mode Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter In I/O mode and idle mode, ETCR functions as a 16-bit counter. The count is decremented by 1 each time one transfer is executed. The transfer ends when the count reaches H'0000. 181 • Repeat mode Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCRH Transfer counter Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCRL Initial count In repeat mode, ETCRH functions as an 8-bit transfer counter and ETCRL holds the initial transfer count. ETCRH is decremented by 1 each time one transfer is executed. When ETCRH reaches H'00, the value in ETCRL is reloaded into ETCRH and the same operation is repeated. The ETCRs are not initialized by a reset or in standby mode. 182 8.2.4 Data Transfer Control Registers (DTCR) A data transfer control register (DTCR) is an 8-bit readable/writable register that controls the operation of one DMAC channel. Bit Initial value Read/Write 7 DTE 0 R/W 6 DTSZ 0 R/W 5 DTID 0 R/W 4 RPE 0 R/W 3 DTIE 0 R/W 2 DTS2 0 R/W 1 DTS1 0 R/W 0 DTS0 0 R/W Data transfer enable Enables or disables data transfer Data transfer size Selects byte or word size Data transfer increment/decrement Selects whether to increment or decrement the memory address register Repeat enable Selects repeat mode Data transfer select These bits select the data transfer activation source Data transfer interrupt enable Enables or disables the CPU interrupt at the end of the transfer The DTCRs are initialized to H'00 by a reset and in standby mode. Bit 7—Data Transfer Enable (DTE): Enables or disables data transfer on a channel. When the DTE bit is set to 1, the channel waits for a transfer to be requested, and executes the transfer when activated as specified by bits DTS2 to DTS0 . When DTE is 0, the channel is disabled and does not accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then writing 1. Bit 7 DTE 0 1 Description Data transfer is disabled. In I/O mode or idle mode, DTE is cleared to 0 when the specified number of transfers have been completed. Data transfer is enabled (Initial value) If DTIE is set to 1, a CPU interrupt is requested when DTE is cleared to 0. 183 Bit 6—Data Transfer Size (DTSZ): Selects the data size of each transfer. Bit 6 DTSZ 0 1 Description Byte-size transfer Word-size transfer (Initial value) Bit 5—Data Transfer Increment/Decrement (DTID): Selects whether to increment or decrement the memory address register (MAR) after a data transfer in I/O mode or repeat mode. Bit 5 DTID 0 Description MAR is incremented after each data transfer • If DTSZ = 0, MAR is incremented by 1 after each transfer • If DTSZ = 1, MAR is incremented by 2 after each transfer 1 MAR is decremented after each data transfer • If DTSZ = 0, MAR is decremented by 1 after each transfer • If DTSZ = 1, MAR is decremented by 2 after each transfer (Initial value) MAR is not incremented or decremented in idle mode. Bit 4—Repeat Enable (RPE): Selects whether to transfer data in I/O mode, idle mode, or repeat mode. Bit 4 RPE 0 Bit 3 DTIE 0 1 1 0 1 Repeat mode Idle mode Description I/O mode (Initial value) Operations in these modes are described in sections 8.4.2, I/O Mode, 8.4.3, Idle Mode, and 8.4.4, Repeat Mode. 184 Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND) requested when the DTE bit is cleared to 0. Bit 3 DTIE 0 1 Description The DEND interrupt requested by DTE is disabled The DEND interrupt requested by DTE is enabled (Initial value) Bits 2 to 0—Data Transfer Select (DTS2, DTS1, DTS0): These bits select the data transfer activation source. Some of the selectable sources differ between channels A and B. Channel A Bit 2 DTS2A 0 Bit 1 DTS1A 0 Bit 0 DTS0A 0 1 1 0 1 1 0 0 1 1 —*1 Description Compare match/input capture A interrupt from ITU channel 0 (Initial value) Compare match/input capture A interrupt from ITU channel 1 Compare match/input capture A interrupt from ITU channel 2 Compare match/input capture A interrupt from ITU channel 3 Transmit-data-empty interrupt from SCI channel 0 or 1*2 Receive-data-full interrupt from SCI channel 0 or 1*2 Transfer in full address mode Notes: 1. See section 8.3.4, Data Transfer Control Register (DTCR). 2. DMAC channels 0 and 1 accept transmit-data-empty and receive-data-full interrupts from SCI channel 0. DMAC channels 2 and 3 accept transmit-data-empty and receivedata-full interrupts from SCI channel 1. 185 Channel B Bit 2 DTS2B 0 Bit 1 DTS1B 0 Bit 0 DTS0B 0 1 1 0 1 1 0 0 1 1 0 1 Description Compare match/input capture A interrupt from ITU channel 0 (Initial value) Compare match/input capture A interrupt from ITU channel 1 Compare match/input capture A interrupt from ITU channel 2 Compare match/input capture A interrupt from ITU channel 3 Transmit-data-empty interrupt from SCI channel 0 or 1* Receive-data-full interrupt from SCI channel 0 or 1* Falling edge of DREQ input Low level of DREQ input Note: * DMAC channels 0 and 1 accept transmit-data-empty and receive-data-full interrupts from SCI channel 0. DMAC channels 2 and 3 accept transmit-data-empty and receive-data-full interrupts from SCI channel 1. The same internal interrupt can be selected as an activation source for two or more channels at once. In that case the channels are activated in a priority order, highest-priority channel first. For the priority order, see section 8.4.9, Multiple-Channel Operation. When a channel is enabled (DTE = 1), its selected DMAC activation source cannot generate a CPU interrupt. 186 8.3 Register Descriptions (2) (Full Address Mode) In full address mode the A and B channels operate together. Full address mode is selected as indicated in table 8-4. 8.3.1 Memory Address Registers (MAR) A memory address register (MAR) is a 32-bit readable/writable register. MARA functions as the source address register of the transfer, and MARB as the destination address register. An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits of MARR are reserved: they cannot be modified and always read 1. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value Read/Write 1 1 1 1 1 1 1 1 Undetermined — — — — — — — — R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W MARR MARE MARH MARL Source or destination address The MAR value is incremented or decremented each time one byte or word is transferred, automatically updating the source or destination memory address. For details, see section 8.3.4, Data Transfer Control Registers (DTCR). The MARs are not initialized by a reset or in standby mode. 8.3.2 I/O Address Registers (IOAR) The I/O address registers (IOARs) are not used in full address mode. 187 8.3.3 Execute Transfer Count Registers (ETCR) An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the number of transfers to be executed. The functions of these registers differ between normal mode and block transfer mode. • Normal mode ETCRA Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter ETCRB: Is not used in normal mode. In normal mode ETCRA functions as a 16-bit transfer counter. The count is decremented by 1 each time one transfer is executed. The transfer ends when the count reaches H'0000. ETCRB is not used. 188 • Block mode ETCRA Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCRAH Block size counter Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCRAL Initial block size ETCRB Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Block transfer counter In block transfer mode, ETCRAH functions as an 8-bit block size counter. ETCRAL holds the initial block size. ETCRAH is decremented by 1 each time one byte or word is transferred. When the count reaches H'00, ETCRAH is reloaded from ETCRAL. Blocks consisting of an arbitrary number of bytes or words can be transferred repeatedly by setting the same initial block size value in ETCRAH and ETCRAL. In block transfer mode ETCRB functions as a 16-bit block transfer counter. ETCRB is decremented by 1 each time one block is transferred. The transfer ends when the count reaches H'0000. The ETCRs are not initialized by a reset or in standby mode. 189 8.3.4 Data Transfer Control Registers (DTCR) The data transfer control registers (DTCRs) are 8-bit readable/writable registers that control the operation of the DMAC channels. A channel operates in full address mode when bits DTS2A and DTS1A are both set to 1 in DTCRA. DTCRA and DTCRB have different functions in full address mode. DTCRA Bit Initial value Read/Write 7 DTE 0 R/W 6 DTSZ 0 R/W 5 SAID 0 R/W 4 SAIDE 0 R/W 3 DTIE 0 R/W 2 DTS2A 0 R/W 1 DTS1A 0 R/W 0 DTS0A 0 R/W Data transfer enable Enables or disables data transfer Data transfer size Selects byte or word size Data transfer interrupt enable Enables or disables the CPU interrupt at the end of the transfer Data transfer select 0A Selects block transfer mode Source address increment/decrement Source address increment/ decrement enable These bits select whether the source address register (MARA) is incremented, decremented, or held fixed during the data transfer Data transfer select 2A and 1A These bits must both be set to 1 DTCRA is initialized to H'00 by a reset and in standby mode. 190 Bit 7—Data Transfer Enable (DTE): Together with the DTME bit in DTCRB, this bit enables or disables data transfer on the channel. When the DTME and DTE bits are both set to 1, the channel is enabled. If auto-request is specified, data transfer begins immediately. Otherwise, the channel waits for transfers to be requested. When the specified number of transfers have been completed, the DTE bit is automatically cleared to 0. When DTE is 0, the channel is disabled and does not accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then writing 1. Bit 7 DTE 0 1 Description Data transfer is disabled (DTE is cleared to 0 when the specified number of transfers have been completed) Data transfer is enabled (Initial value) If DTIE is set to 1, a CPU interrupt is requested when DTE is cleared to 0. Bit 6—Data Transfer Size (DTSZ): Selects the data size of each transfer. Bit 6 DTSZ 0 1 Description Byte-size transfer Word-size transfer (Initial value) Bit 5—Source Address Increment/Decrement (SAID) and Bit 4—Source Address Increment/Decrement Enable (SAIDE): These bits select whether the source address register (MARA) is incremented, decremented, or held fixed during the data transfer. Bit 5 SAID 0 Bit 4 SAIDE 0 1 Description MARA is held fixed MARA is incremented after each data transfer • If DTSZ = 0, MARA is incremented by 1 after each transfer • If DTSZ = 1, MARA is incremented by 2 after each transfer 1 0 1 MARA is held fixed MARA is decremented after each data transfer • If DTSZ = 0, MARA is decremented by 1 after each transfer • If DTSZ = 1, MARA is decremented by 2 after each transfer (Initial value) 191 Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND) requested when the DTE bit is cleared to 0. Bit 3 DTIE 0 1 Description The DEND interrupt requested by DTE is disabled The DEND interrupt requested by DTE is enabled (Initial value) Bits 2 and 1—Data Transfer Select 2A and 1A (DTS2A, DTS1A): A channel operates in full address mode when DTS2A and DTS1A are both set to 1. Bit 0—Data Transfer Select 0A (DTS0A): Selects normal mode or block transfer mode. Bit 0 DTS0A 0 1 Description Normal mode Block transfer mode (Initial value) Operations in these modes are described in sections 8.4.5, Normal Mode, and 8.4.6, Block Transfer Mode. 192 DTCRB Bit Initial value Read/Write 7 DTME 0 R/W 6 — 0 R/W 5 DAID 0 R/W 4 DAIDE 0 R/W 3 TMS 0 R/W 2 DTS2B 0 R/W 1 DTS1B 0 R/W 0 DTS0B 0 R/W Data transfer master enable Enables or disables data transfer, together with the DTE bit, and is cleared to 0 by an interrupt Reserved bit Transfer mode select Selects whether the block area is the source or destination in block transfer mode Data transfer select 2B to 0B These bits select the data transfer activation source Destination address increment/decrement Destination address increment/decrement enable These bits select whether the destination address register (MARB) is incremented, decremented, or held fixed during the data transfer DTCRB is initialized to H'00 by a reset and in standby mode. Bit 7—Data Transfer Master Enable (DTME): Together with the DTE bit in DTCRA, this bit enables or disables data transfer. When the DTME and DTE bits are both set to 1, the channel is enabled. When an NMI interrupt occurs DTME is cleared to 0, suspending the transfer so that the CPU can use the bus. The suspended transfer resumes when DTME is set to 1 again. For further information on operation in block transfer mode, see section 8.6.6, NMI Interrupts and Block Transfer Mode. DTME is set to 1 by reading the register while DTME = 0, then writing 1. Bit 7 DTME 0 1 Description Data transfer is disabled (DTME is cleared to 0 when an NMI interrupt occurs) Data transfer is enabled (Initial value) 193 Bit 6—Reserved: Although reserved, this bit can be written and read. Bit 5—Destination Address Increment/Decrement (DAID) and Bit 4—Destination Address Increment/Decrement Enable (DAIDE): These bits select whether the destination address register (MARB), is incremented, decremented, or held fixed during the data transfer. Bit 5 DAID 0 Bit 4 DAIDE 0 1 Description MARB is held fixed MARB is incremented after each data transfer • If DTSZ = 0, MARB is incremented by 1 after each data transfer • If DTSZ = 1, MARB is incremented by 2 after each data transfer 1 0 1 MARB is held fixed MARB is decremented after each data transfer • If DTSZ = 0, MARB is decremented by 1 after each data transfer • If DTSZ = 1, MARB is decremented by 2 after each data transfer (Initial value) Bit 3—Transfer Mode Select (TMS): Selects whether the source or destination is the block area in block transfer mode. Bit 3 TMS 0 1 Description Destination is the block area in block transfer mode Source is the block area in block transfer mode (Initial value) 194 Bits 2 to 0—Data Transfer Select (DTS2B, DTS1B, DTS0B): These bits select the data transfer activation source. The selectable activation sources differ between normal mode and block transfer mode. Normal mode Bit 2 DTS2B 0 Bit 1 DTS1B 0 Bit 0 DTS0B 0 1 1 0 1 1 0 0 1 1 0 1 Description Auto-request (burst mode) * Auto-request (cycle-steal mode) * * * Falling edge of DREQ Low level input at DREQ (Initial value) Note: Settings marked with asterisks (*) cannot be used. Block transfer mode Bit 2 Bit 1 Bit 0 DTS2B DTS1B DTS0B Description 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Compare match/input capture A interrupt from ITU channel 0 (Initial value) Compare match/input capture A interrupt from ITU channel 1 Compare match/input capture A interrupt from ITU channel 2 Compare match/input capture A interrupt from ITU channel 3 * * Falling edge of DREQ * Note: Settings marked with asterisks (*) cannot be used. The same internal interrupt can be selected to activate two or more channels. The channels are activated in a priority order, highest priority first. For the priority order, see section 8.4.9, Multiple-Channel Operation. 195 8.4 Operation 8.4.1 Overview Table 8-5 summarizes the DMAC modes. Table 8-5 DMAC Modes Transfer Mode Short address mode Activation I/O mode Idle mode Repeat mode Notes Compare match/input capture A interrupt from ITU channels 0 to 3 SCI transmit-data-empty and receive-data-full interrupts External request Full address mode Normal mode Auto-request External request Block transfer mode Compare match/input capture A interrupt from ITU channels 0 to 3 External request • A and B channels are paired; up to four channels are available • Burst mode or cyclesteal mode can be selected for autorequests • Up to eight channels can operate independently • Only the B channels support external requests A summary of operations in these modes follows. I/O Mode: One byte or word is transferred per request. A designated number of these transfers are executed. A CPU interrupt can be requested at completion of the designated number of transfers. One 24-bit address and one 8-bit address are specified. The transfer direction is determined automatically from the activation source. Idle Mode: One byte or word is transferred per request. A designated number of these transfers are executed. A CPU interrupt can be requested at completion of the designated number of transfers. One 24-bit address and one 8-bit address are specified. The addresses are held fixed. The transfer direction is determined automatically from the activation source. Repeat Mode: One byte or word is transferred per request. A designated number of these transfers are executed. When the designated number of transfers are completed, the initial address and counter value are restored and operation continues. No CPU interrupt is requested. One 24-bit address and one 8-bit address are specified. The transfer direction is determined automatically from the activation source. 196 Normal Mode • Auto-request The DMAC is activated by register setup alone, and continues executing transfers until the designated number of transfers have been completed. A CPU interrupt can be requested at completion of the transfers. Both addresses are 24-bit addresses. — Cycle-steal mode The bus is released to another bus master after each byte or word is transferred. — Burst mode Unless requested by a higher-priority bus master, the bus is not released until the designated number of transfers have been completed. • External request One byte or word is transferred per request. A designated number of these transfers are executed. A CPU interrupt can be requested at completion of the designated number of transfers. Both addresses are 24-bit addresses. Block Transfer Mode: One block of a specified size is transferred per request. A designated number of block transfers are executed. At the end of each block transfer, one address is restored to its initial value. When the designated number of blocks have been transferred, a CPU interrupt can be requested. Both addresses are 24-bit addresses. 197 8.4.2 I/O Mode I/O mode can be selected independently for each channel. One byte or word is transferred at each transfer request in I/O mode. A designated number of these transfers are executed. One address is specified in the memory address register (MAR), the other in the I/O address register (IOAR). The direction of transfer is determined automatically from the activation source. The transfer is from the address specified in IOAR to the address specified in MAR if activated by an SCI receive-data-full interrupt, and from the address specified in MAR to the address specified in IOAR otherwise. Table 8-6 indicates the register functions in I/O mode. Table 8-6 Register Functions in I/O Mode Function Activated by SCI ReceiveData-Full Interrupt 0 MAR 23 All 1s 15 ETCR 7 IOAR 0 0 Destination address register Source address register Register 23 Other Activation Source address register Destination address register Initial Setting Destination or source address Source or destination address Decremented transfers Operation Incremented or decremented once per transfer Held fixed Transfer counterNumber of once per transfer until H'0000 is reached and transfer ends Legend MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or destination address, which is incremented or decremented as each byte or word is transferred. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not incremented or decremented. Figure 8-2 illustrates how I/O mode operates. 198 Address T Transfer IOAR 1 byte or word is transferred per request Address B Legend L = initial setting of MAR N = initial setting of ETCR Address T = L Address B = L + (–1) DTID • (2 DTSZ • N – 1) Figure 8-2 Operation in I/O Mode The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared and the transfer ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this time. The maximum transfer count is 65,536, obtained by setting ETCR to H'0000. Transfers can be requested (activated) by compare match/input capture A interrupts from ITU channels 0 to 3, SCI transmit-data-empty and receive-data-full interrupts, and external request signals. For the detailed settings see section 8.2.4, Data Transfer Control Registers (DTCR). 199 Figure 8-3 shows a sample setup procedure for I/O mode. I/O Set source and destination addresses 1 Set transfer count 2 Read DTCR 3 1. Set the source and destination addresses in MAR and IOAR. The transfer direction is determined automatically from the activation source. 2. Set the transfer count in ETCR. 3. Read DTCR while the DTE bit is cleared to 0. 4. Set the DTCR bits as follows. • Select the DMAC activation source with bits DTS2 to DTS0. • Set or clear the DTIE bit to enable or disable the CPU interrupt at the end of the transfer. • Clear the RPE bit to 0 to select I/O mode. • Select MAR increment or decrement with the DTID bit. • Select byte size or word size with the DTSZ bit. • Set the DTE bit to 1 to enable the transfer. Set DTCR 4 I/O mode Figure 8-3 I/O Mode Setup Procedure (Example) 8.4.3 Idle Mode Idle mode can be selected independently for each channel. One byte or word is transferred at each transfer request in idle mode. A designated number of these transfers are executed. One address is specified in the memory address register (MAR), the other in the I/O address register (IOAR). The direction of transfer is determined automatically from the activation source. The transfer is from the address specified in IOAR to the address specified in MAR if activated by an SCI receive-data-full interrupt, and from the address specified in MAR to the address specified in IOAR otherwise. Table 8-7 indicates the register functions in idle mode. 200 Table 8-7 Register Functions in Idle Mode Function Activated by SCI ReceiveData-Full Interrupt 0 MAR 23 All 1s 15 ETCR 7 IOAR 0 0 Destination address register Source address register Register 23 Other Activation Source address register Destination address register Initial Setting Destination or source address Source or destination address Decremented transfers Operation Held fixed Held fixed Transfer counterNumber of once per transfer until H'0000 is reached and transfer ends Legend MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. MAR and IOAR are not incremented or decremented. Figure 8-4 illustrates how idle mode operates. MAR Transfer IOAR 1 byte or word is transferred per request Figure 8-4 Operation in Idle Mode 201 The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared, the transfer ends, and a CPU interrupt is requested. The maximum transfer count is 65,536, obtained by setting ETCR to H'0000. Transfers can be requested (activated) by compare match/input capture A interrupts from ITU channels 0 to 3, SCI transmit-data-empty and receive-data-full interrupts, and external request signals. For the detailed settings see section 8.2.4, Data Transfer Control Registers (DTCR). Figure 8-5 shows a sample setup procedure for idle mode. Idle mode Set source and destination addresses 1 Set transfer count 2 1. Set the source and destination addresses in MAR and IOAR. The transfer direction is determined automatically from the activation source. 2. Set the transfer count in ETCR. 3. Read DTCR while the DTE bit is cleared to 0. 4. Set the DTCR bits as follows. • Select the DMAC activation source with bits DTS2 to DTS0. • Set the DTIE and RPE bits to 1 to select idle mode. • Select byte size or word size with the DTSZ bit. • Set the DTE bit to 1 to enable the transfer. Read DTCR 3 Set DTCR 4 Idle mode Figure 8-5 Idle Mode Setup Procedure (Example) 202 8.4.4 Repeat Mode Repeat mode is useful for cyclically transferring a bit pattern from a table to the programmable timing pattern controller (TPC) in synchronization, for example, with ITU compare match. Repeat mode can be selected for each channel independently. One byte or word is transferred per request in repeat mode, as in I/O mode. A designated number of these transfers are executed. One address is specified in the memory address register (MAR), the other in the I/O address register (IOAR). At the end of the designated number of transfers, MAR and ETCR are restored to their original values and operation continues. The direction of transfer is determined automatically from the activation source. The transfer is from the address specified in IOAR to the address specified in MAR if activated by an SCI receive-data-full interrupt, and from the address specified in MAR to the address specified in IOAR otherwise. Table 8-8 indicates the register functions in repeat mode. Table 8-8 Register Functions in Repeat Mode Function Activated by SCI ReceiveData-Full Interrupt Destination address register Register Other Activation Initial Setting Source address register Operation 23 MAR 0 Destination or Incremented or source address decremented at each transfer until ETCRH reaches H'0000, then restored to initial value Held fixed 23 All 1s 7 IOAR 0 Source address register Transfer counter Destination Source or address destination register address Number of transfers 7 0 ETCRH Decremented once per transfer unti H'0000 is reached, then reloaded from ETCRL Held fixed 7 0 Initial transfer count ETCRL Legend MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register Number of transfers 203 In repeat mode ETCRH is used as the transfer counter while ETCRL holds the initial transfer count. ETCRH is decremented by 1 at each transfer until it reaches H'00, then is reloaded from ETCRL. MAR is also restored to its initial value, which is calculated from the DTSZ and DTID bits in DTCR. Specifically, MAR is restored as follows: MAR ← MAR – (–1)DTID · 2DTSZ · ETCRL ETCRH and ETCRL should be initially set to the same value. In repeat mode transfers continue until the CPU clears the DTE bit to 0. After DTE is cleared to 0, if the CPU sets DTE to 1 again, transfers resume from the state at which DTE was cleared. No CPU interrupt is requested. As in I/O mode, MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not incremented or decremented. Figure 8-6 illustrates how repeat mode operates. Address T Transfer IOAR 1 byte or word is transferred per request Address B Legend L = initial setting of MAR N = initial setting of ETCRH and ETCRL Address T = L Address B = L + (–1) DTID • (2 DTSZ • N – 1) Figure 8-6 Operation in Repeat Mode 204 The transfer count is specified as an 8-bit value in ETCRH and ETCRL. The maximum transfer count is 255, obtained by setting both ETCRH and ETCRL to H'FF. Transfers can be requested (activated) by compare match/input capture A interrupts from ITU channels 0 to 3, SCI transmit-data-empty and receive-data-full interrupts, and external request signals. For the detailed settings see section 8.2.4, Data Transfer Control Registers (DTCR). Figure 8-7 shows a sample setup procedure for repeat mode. Repeat mode Set source and destination addresses 1 Set transfer count 2 1. Set the source and destination addresses in MAR and IOAR. The transfer direction is determined automatically from the activation source. 2. Set the transfer count in both ETCRH and ETCRL. 3. Read DTCR while the DTE bit is cleared to 0. 4. Set the DTCR bits as follows. • Select the DMAC activation source with bits DTS2 to DTS0. • Clear the DTIE bit to 0 and set the RPE bit to 1 to select repeat mode. • Select MAR increment or decrement with the DTID bit. • Select byte size or word size with the DTSZ bit. • Set the DTE bit to 1 to enable the transfer. Read DTCR 3 Set DTCR 4 Repeat mode Figure 8-7 Repeat Mode Setup Procedure (Example) 205 8.4.5 Normal Mode In normal mode the A and B channels are combined. One byte or word is transferred per request. A designated number of these transfers are executed. Addresses are specified in MARA and MARB. Table 8-9 indicates the register functions in I/O mode. Table 8-9 Register Functions in Normal Mode Register 23 MARA 23 MARB 15 ETCRA Legend MARA: Memory address register A MARB: Memory address register B ETCRA: Execute transfer count register A 0 0 0 Function Source address register Destination address register Transfer counter Initial Setting Source address Operation Incremented or decremented once per transfer, or held fixed Incremented or decremented once per transfer, or held fixed Decremented once per transfer Destination address Number of transfers The source and destination addresses are both 24-bit addresses. MARA specifies the source address. MARB specifies the destination address. MARA and MARB can be independently incremented, decremented, or held fixed as data is transferred. The transfer count is specified as a 16-bit value in ETCRA. The ETCRA value is decremented by 1 at each transfer. When the ETCRA value reaches H'0000, the DTE bit is cleared and the transfer ends. If the DTIE bit is set, a CPU interrupt is requested at this time. The maximum transfer count is 65,536, obtained by setting ETCRA to H'0000. Figure 8-8 illustrates how normal mode operates. 206 Address TA Transfer Address T B Address BA Address B B Legend L A = initial setting of MARA L B = initial setting of MARB N = initial setting of ETCRA TA = LA BA = L A + SAIDE • (–1) SAID • (2 DTSZ • N – 1) TB = LB BB = L B + DAIDE • (–1)DAID • (2 DTSZ • N – 1) Figure 8-8 Operation in Normal Mode Transfers can be requested (activated) by an external request or auto-request. An auto-requested transfer is activated by the register settings alone. The designated number of transfers are executed automatically. Either cycle-steal or burst mode can be selected. In cycle-steal mode the DMAC releases the bus temporarily after each transfer. In burst mode the DMAC keeps the bus until the transfers are completed, unless there is a bus request from a higher-priority bus master. For the detailed settings see section 8.3.4, Data Transfer Control Registers (DTCR). 207 Figure 8-9 shows a sample setup procedure for normal mode. Normal mode Set initial source address 1 1. 2. 3. 4. Set initial destination address 2 5. Set transfer count 3 Set DTCRB (1) 4 Set DTCRA (1) 5 Read DTCRB 6 6. 7. 8. 9. Set the initial source address in MARA. Set the initial destination address in MARB. Set the transfer count in ETCRA. Set the DTCRB bits as follows. • Clear the DTME bit to 0. • Set the DAID and DAIDE bits to select whether MARB is incremented, decremented, or held fixed. • Select the DMAC activation source with bits DTS2B to DTS0B. Set the DTCRA bits as follows. • Clear the DTE bit to 0. • Select byte or word size with the DTSZ bit. • Set the SAID and SAIDE bits to select whether MARA is incremented, decremented, or held fixed. • Set or clear the DTIE bit to enable or disable the CPU interrupt at the end of the transfer. • Clear the DTS0A bit to 0 and set the DTS2A and DTS1A bits to 1 to select normal mode. Read DTCRB with DTME cleared to 0. Set the DTME bit to 1 in DTCRB. Read DTCRA with DTE cleared to 0. Set the DTE bit to 1 in DTCRA to enable the transfer. Set DTCRB (2) 7 Read DTCRA 8 Set DTCRA (2) 9 Normal mode Note: * Carry out settings 1 to 9 with the DEND interrupt masked in the CPU. Figure 8-9 Normal Mode Setup Procedure (Example) 208 8.4.6 Block Transfer Mode In block transfer mode the A and B channels are combined. One block of a specified size is transferred per request. A designated number of block transfers are executed. Addresses are specified in MARA and MARB. The block area address can be either held fixed or cycled. Table 8-10 indicates the register functions in block transfer mode. Table 8-10 Register Functions in Block Transfer Mode Register 23 MARA 23 MARB 7 0 0 0 Function Source address register Destination address register Initial Setting Source address Operation Incremented or decremented once per transfer, or held fixed Incremented or decremented once per transfer, or held fixed Decremented once per transfer until H'00 is reached, then reloaded from ETCRAL Held fixed Destination address Block size counter Block size ETCRAH 7 0 Initial block size Block size ETCRAL 15 ETCRB Legend MARA: MARB: ETCRA: ETCRB: 0 Block transfer counter Number of block transfers Decremented once per block transfer until H'0000 is reached and the transfer ends Memory address register A Memory address register B Execute transfer count register A Execute transfer count register B The source and destination addresses are both 24-bit addresses. MARA specifies the source address. MARB specifies the destination address. MARA and MARB can be independently incremented, decremented, or held fixed as data is transferred. One of these registers operates as a block area register: even if it is incremented or decremented, it is restored to its initial value at the end of each block transfer. The TMS bit in DTCRB selects whether the block area is the source or destination. 209 If M (1 to 255) is the size of the block transferred at each request and N (1 to 65,536) is the number of blocks to be transferred, then ETCRAH and ETCRAL should initially be set to M and ETCRB should initially be set to N. Figure 8-10 illustrates how block transfer mode operates. In this figure, bit TMS is cleared to 0, meaning the block area is the destination. TA Transfer Block 1 Block area BA Address T B Address B B Block 2 M bytes or words are transferred per request Block N Legend L A = initial setting of MARA L B = initial setting of MARB M = initial setting of ETCRAH and ETCRAL N = initial setting of ETCRB T A = LA B A = L A + SAIDE • (–1) SAID • (2 DTSZ • M – 1) T B = LB B B = L B + DAIDE • (–1)DAID • (2 DTSZ • M – 1) Figure 8-10 Operation in Block Transfer Mode 210 When activated by a transfer request, the DMAC executes a burst transfer. During the transfer MARA and MARB are updated according to the DTCR settings, and ETCRAH is decremented. When ETCRAH reaches H'00, it is reloaded from ETCRAL to restore the initial value. The memory address register of the block area is also restored to its initial value, and ETCRB is decremented. If ETCRB is not H'0000, the DMAC then waits for the next transfer request. ETCRAH and ETCRAL should be initially set to the same value. The above operation is repeated until ETCRB reaches H'0000, at which point the DTE bit is cleared to 0 and the transfer ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this time. Figure 8-11 shows examples of a block transfer with byte data size when the block area is the destination. In (a) the block area address is cycled. In (b) the block area address is held fixed. Transfers can be requested (activated) by compare match/input capture A interrupts from ITU channels 0 to 3, and by external request signals. For the detailed settings see section 8.3.4, Data Transfer Control Registers (DTCR). 211 Start (DTE = DTME = 1) Start (DTE = DTME = 1) Transfer requested? Yes Get bus No Transfer requested? Yes Get bus No Read from MARA address MARA = MARA + 1 Write to MARB address MARB = MARB + 1 ETCRAH = ETCRAH – 1 No ETCRAH = H'00 Yes Release bus ETCRAH = ETCRAL MARB = MARB – ETCRAL ETCRB = ETCRB – 1 No Read from MARA address MARA = MARA + 1 Write to MARB address ETCRAH = ETCRAH – 1 No ETCRAH = H'00 Yes Release bus ETCRAH = ETCRAL ETCRB = ETCRB – 1 No ETCRB = H'0000 Yes Clear DTE to 0 and end transfer ETCRB = H'0000 Yes Clear DTE to 0 and end transfer a. DTSZ = TMS = 0 SAID = DAID = 0 SAIDE = DAIDE = 1 b. DTSZ = TMS = 0 SAID = 0 SAIDE = 1 DAIDE = 0 Figure 8-11 Block Transfer Mode Flowcharts (Examples) 212 Figure 8-12 shows a sample setup procedure for block transfer mode. Block transfer mode Set source address 1 Set destination address 2 Set block transfer count 3 Set block size 4 Set DTCRB (1) 5 Set DTCRA (1) 6 Read DTCRB 7 Set the source address in MARA. Set the destination address in MARB. Set the block transfer count in ETCRB. Set the block size (number of bytes or words) in both ETCRAH and ETCRAL. 5. Set the DTCRB bits as follows. • Clear the DTME bit to 0. • Set the DAID and DAIDE bits to select whether MARB is incremented, decremented, or held fixed. • Set or clear the TMS bit to make the block area the source or destination. • Select the DMAC activation source with bits DTS2B to DTS0B. 6. Set the DTCRA bits as follows. • Clear the DTE to 0. • Select byte size or word size with the DTSZ bit. • Set the SAID and SAIDE bits to select whether MARA is incremented, decremented, or held fixed. • Set or clear the DTIE bit to enable or disable the CPU interrupt at the end of the transfer. • Set bits DTS2A to DTS0A all to 1 to select block transfer mode. 7. Read DTCRB with DTME cleared to 0. 8. Set the DTME bit to 1 in DTCRB. 9. Read DTCRA with DTE cleared to 0. 10. Set the DTE bit to 1 in DTCRA to enable the transfer. 1. 2. 3. 4. Set DTCRB (2) 8 Read DTCRA 9 Set DTCRA (2) 10 Block transfer mode Note: * Carry out settings 1 to 10 with the DEND interrupt masked in the CPU. Figure 8-12 Block Transfer Mode Setup Procedure (Example) 213 8.4.7 DMAC Activation The DMAC can be activated by an internal interrupt, external request, or auto-request. The available activation sources differ depending on the transfer mode and channel as indicated in table 8-11. Table 8-11 DMAC Activation Sources Short Address Mode Activation Source Internal interrupts IMIA0 IMIA1 IMIA2 IMIA3 TXI0 RXI0 TXI1 RXI1 External requests Falling edge of DREQ Low input at DREQ Auto-request × × × × × × × × × × × × × × × × × × Channels Channels 0A and 1A 0B and 1B Channels Channels 2A and 3A 2B and 3B Full Address Mode Normal × × × × × × × × × × × × Block Activation by Internal Interrupts: When an interrupt request is selected as a DMAC activation source and the DTE bit is set to 1, that interrupt request is not sent to the CPU. It is not possible for an interrupt request to activate the DMAC and simultaneously generate a CPU interrupt. When the DMAC is activated by an interrupt request, the interrupt request flag is cleared automatically. If the same interrupt is selected to activate two or more channels, the interrupt request flag is cleared when the highest-priority channel is activated, but the transfer request is held pending on the other channels in the DMAC, which are activated in their priority order. 214 Activation by External Request: If an external request (DREQ pin) is selected as an activation source, the DREQ pin becomes an input pin and the corresponding TEND pin becomes an output pin, regardless of the port data direction register (DDR) settings. The DREQ input can be levelsensitive or edge-sensitive. In short address mode and normal mode, an external request operates as follows. If edge sensing is selected, one byte or word is transferred each time a high-to-low transition of the DREQ input is detected. If the next edge is input before the transfer is completed, the next transfer may not be executed. If level sensing is selected, the transfer continues while DREQ is low, until the transfer is completed. The bus is released temporarily after each byte or word has been transferred, however. If the DREQ input goes high during a transfer, the transfer is suspended after the current byte or word has been transferred. When DREQ goes low, the request is held internally until one byte or word has been transferred. The TEND signal goes low during the last write cycle. In block transfer mode, an external request operates as follows. Only edge-sensitive transfer requests are possible in block transfer mode. Each time a high-to-low transition of the DREQ input is detected, a block of the specified size is transferred. The TEND signal goes low during the last write cycle in each block. Activation by Auto-Request: The transfer starts as soon as enabled by register setup, and continues until completed. Cycle-steal mode or burst mode can be selected. In cycle-steal mode the DMAC releases the bus temporarily after transferring each byte or word. Normally, DMAC cycles alternate with CPU cycles. In burst mode the DMAC keeps the bus until the transfer is completed, unless there is a higherpriority bus request. If there is a higher-priority bus request, the bus is released after the current byte or word has been transferred. 215 8.4.8 DMAC Bus Cycle Figure 8-13 shows an example of the timing of the basic DMAC bus cycle. This example shows a word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the DMAC gets the bus from the CPU, after one dead cycle (Td), it reads from the source address and writes to the destination address. During these read and write operations the bus is not released even if there is another bus request. DMAC cycles comply with bus controller settings in the same way as CPU cycles. CPU cycle T1 ø T2 T1 T2 Td T1 DMAC cycle (word transfer) T2 T1 T2 T3 T1 T2 T3 T1 CPU cycle T2 T1 T2 Source address A 23 to A 0 RD Destination address HWR LWR Figure 8-13 DMA Transfer Bus Timing (Example) Figure 8-14 shows the timing when the DMAC is activated by low input at a DREQ pin. This example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state access area. The DMAC continues the transfer while the DREQ pin is held low. 216 CPU cycle T1 ø T2 T3 Td DMAC cycle T1 T2 T1 T2 CPU cycle T1 T2 Td DMAC cycle (last transfer cycle) T1 T2 T1 T2 CPU cycle T1 T2 DREQ A 23 to A 0 RD Source Destination address address Source Destination address address HWR , LWR TEND Figure 8-14 Bus Timing of DMA Transfer Requested by Low DREQ Input Figure 8-15 shows an auto-requested burst-mode transfer. This example shows a transfer of three words from a 16-bit two-state access area to another 16-bit two-state access area. 217 CPU cycle T1 ø Source address A 23 to A 0 RD Destination address T2 Td T1 T2 T1 T2 DMAC cycle T1 T2 T1 T2 T1 T2 T1 T2 CPU cycle T1 T2 HWR , LWR Figure 8-15 Burst DMA Bus Timing When the DMAC is activated from a DREQ pin there is a minimum interval of four states from when the transfer is requested until the DMAC starts operating. The DREQ pin is not sampled during the time between the transfer request and the start of the transfer. In short address mode and normal mode, the pin is next sampled at the end of the read cycle. In block transfer mode, the pin is next sampled at the end of one block transfer. Figure 8-16 shows the timing when the DMAC is activated by the falling edge of DREQ in normal mode. 218 CPU cycle T2 ø T1 T2 T1 T2 Td DMAC cycle T1 T2 T1 T2 T1 CPU cycle T2 DMAC cycle Td T1 T2 DREQ A 23 to A 0 RD HWR , LWR Minimum 4 states Next sampling point Figure 8-16 Timing of DMAC Activation by Falling Edge of DREQ in Normal Mode Figure 8-17 shows the timing when the DMAC is activated by level-sensitive low DREQ input in normal mode. 219 CPU cycle T2 ø T1 T2 T1 T2 Td DMAC cycle T1 T2 T1 T2 T1 CPU cycle T2 T1 T2 T1 DREQ A 23 to A 0 RD HWR , LWR Minimum 4 states Next sampling point Figure 8-17 Timing of DMAC Activation by Low DREQ Level in Normal Mode Figure 8-18 shows the timing when the DMAC is activated by the falling edge of DREQ in block transfer mode. 220 End of 1 block transfer DMAC cycle T1 ø DREQ T2 T1 T2 T1 T2 T1 T2 T1 CPU cycle T2 T1 T2 DMAC cycle Td T1 T2 A 23 to A 0 RD HWR , LWR TEND Next sampling Minimum 4 states Figure 8-18 Timing of DMAC Activation by Falling Edge of DREQ in Block Transfer Mode 221 8.4.9 Multiple-Channel Operation The DMAC channel priority order is: channel 0 > channel 1 > channel 2 > channel 3, and channel A > channel B. Table 8-12 shows the complete priority order. Group 0 and group 1 operate as two independent bus masters. Table 8-12 Channel Priority Order Bus Master Group 0 Short Address Mode Channel 0A Channel 0B Channel 1A Channel 1B Group 1 Channel 2A Channel 2B Channel 3A Channel 3B Channel 3 Low Channel 2 Channel 1 Full Address Mode Channel 0 Priority High Multiple-Channel Operation in the Same Group: If transfers are requested on two or more channels simultaneously in the same group, or if a transfer on one channel is requested during a transfer on another channel in the same group, the DMAC operates as follows. • When a transfer is requested, the DMAC requests the bus right. When it gets the bus right, it starts a transfer on the highest-priority channel at that time. Once a transfer starts on one channel, requests to other channels in the same group are held pending until that channel releases the bus. After each transfer in short address mode, and each externally-requested or cycle-steal transfer in normal mode, the DMAC releases the bus and returns to step 1. After releasing the bus, if there is a transfer request for another channel in the same group, the DMAC requests the bus again. After completion of a burst-mode transfer, or after transfer of one block in block transfer mode, the DMAC releases the bus and returns to step 1. If there is a transfer request for a higher-priority channel or a bus request from a higher-priority bus master, however, the DMAC releases the bus after completing the transfer of the current byte or word. After releasing the bus, if there is a transfer request for another channel in the same group, the DMAC requests the bus again. • • • 222 Figure 8-19 shows the timing when channel 0A is set up for I/O mode and channel 1 for burst mode, and a transfer request for channel 0A is received while channel 1 is active. DMAC cycle (channel 1) T1 ø T2 T1 CPU cycle T2 Td DMAC cycle (channel 0A) T1 T2 T1 T2 T1 CPU cycle T2 Td DMAC cycle (channel 1) T1 T2 T1 T2 A 23 to A 0 RD HWR , LWR Figure 8-19 Timing of Multiple-Channel Operations in the Same Group Multiple-Channel Operation in Different Groups: If transfers are requested on channels in groups 0 and 1 simultaneously, or if a transfer in one group is requested during a transfer in the other group, the DMAC operates as follows. • When a transfer is requested, the DMAC requests the bus right. When it gets the bus right, it activates the highest-priority channel at that time. If there are transfer requests for both DMAC groups 0 and 1, a channel in group 0 is activated. Once a transfer starts on a channel in one group, requests to other channels are held pending until that channel releases the bus. After each transfer in short address mode, and each externally-requested or cycle-steal transfer in normal mode, the DMAC releases the bus and returns to step 1. If there is a transfer request for a channel in the other group, that channel is activated immediately. After completion of a burst-mode transfer, or after transfer of one block in block transfer mode, the DMAC releases the bus and returns to step 1. If there is a transfer request for a group-0 channel while a group-1 channel is active, however, the group-1 channel releases the bus after completing the transfer of the current byte or word. When the bus is released, if there is a transfer request for a channel in the other group, the DMAC is activated immediately. 223 • • • Figure 8-20 shows the timing when channel 0A is set up for I/O mode and channel 2 for burst mode, and a transfer request for channel 0A is received while channel 2 is active. DMAC cycle (channel 2) T1 ø T2 Td DMAC cycle (channel 0A) T1 T2 T1 T2 Td DMAC cycle (channel 2) T1 T2 T1 T2 T1 T2 A 23 to A 0 RD HWR , LWR Figure 8-20 Timing of Multiple-Channel Operations in Different Groups If cycle-steal mode is selected in both groups 0 and 1, the DMAC may activate channels in these two groups alternately without passing the bus right to the CPU. 224 8.4.10 External Bus Requests, Refresh Controller, and DMAC During a DMA transfer, if the bus right is requested by an external bus request signal (BREQ) or by the refresh controller, the DMAC releases the bus after completing the transfer of the current byte or word. If there is a transfer request at this point, the DMAC requests the bus right again. Figure 8-21 shows an example of the timing of insertion of a refresh cycle during a burst transfer on channel 0. DMAC cycle (channel 0) T1 ø T2 T1 T2 T1 T2 T1 T2 Refresh cycle T1 T2 Td DMAC cycle (channel 0) T1 T2 T1 T2 T1 T2 A 23 to A 0 RD HWR , LWR Figure 8-21 Bus Timing of Refresh Controller and DMAC 225 8.4.11 NMI Interrupts and DMAC NMI interrupts do not affect DMAC operations in short address mode. If an NMI interrupt occurs during a transfer in full address mode, the DMAC suspends operations. In full address mode, a channel is enabled when its DTE and DTME bits are both set to 1. NMI input clears the DTME bit to 0. After transferring the current byte or word, the DMAC releases the bus to the CPU. In normal mode, the suspended transfer resumes when the CPU sets the DTME bit to 1 again. Check that the DTE bit is set to 1 and the DTME bit is cleared to 0 before setting the DTME bit to 1. Figure 8-22 shows the procedure for resuming a DMA transfer in normal mode on channel 0 after the transfer was halted by NMI input. Resuming DMA transfer in normal mode 1. Check that DTE = 1 and DTME = 0. 2. Read DTCRB while DTME = 0, then write 1 in the DTME bit. DTE = 1 DTME = 0 Yes Set DTME to 1 No 2 DMA transfer continues End Figure 8-22 Procedure for Resuming a DMA Transfer Halted by NMI (Example) For information about NMI interrupts in block transfer mode, see section 8.6.6, NMI Interrupts and Block Transfer Mode. 226 8.4.12 Aborting a DMA Transfer When the DTE bit in an active channel is cleared to 0, the DMAC halts after transferring the current byte or word. The DMAC starts again when the DTE bit is set to 1. In full address mode, the DTME bit can be used for the same purpose. Figure 8-23 shows the procedure for aborting a DMA transfer by software. DMA transfer abort 1. Clear the DTE bit to 0 in DTCR. To avoid generating an interrupt when aborting a DMA transfer, clear the DTIE bit to 0 simultaneously. 1 Set DTCR DMA transfer aborted Figure 8-23 Procedure for Aborting a DMA Transfer 227 8.4.13 Exiting Full Address Mode Figure 8-24 shows the procedure for exiting full address mode and initializing the pair of channels. To set the channels up in another mode after exiting full address mode, follow the setup procedure for the relevant mode. Exiting full address mode Halt the channel 1 1. Clear the DTE bit to 0 in DTCRA, or wait for the transfer to end and the DTE bit to be cleared to 0. 2. Clear all DTCRB bits to 0. 3. Clear all DTCRA bits to 0. Initialize DTCRB 2 Initialize DTCRA 3 Initialized and halted Figure 8-24 Procedure for Exiting Full Address Mode (Example) 228 8.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode When the chip is reset or enters hardware or software standby mode, the DMAC is initialized. DMAC operations continue in sleep mode. Figure 8-25 shows the timing of a cycle-steal transfer in sleep mode. Sleep mode CPU cycle T2 ø Td DMAC cycle T1 T2 T1 T2 Td DMAC cycle T1 T2 T1 T2 A 23 to A 0 RD HWR , LWR Figure 8-25 Timing of Cycle-Steal Transfer in Sleep Mode 229 8.5 Interrupts The DMAC generates only DMA-end interrupts. Table 8-13 lists the interrupts and their priority. Table 8-13 DMAC Interrupts Description Group 0 Interrupt DEND0A DEND0B DEND1A DEND1B 1 DEND2A DEND2B DEND3A DEND3B Short Address Mode End of transfer on channel 0A End of transfer on channel 0B End of transfer on channel 1A End of transfer on channel 1B End of transfer on channel 2A End of transfer on channel 2B End of transfer on channel 3A End of transfer on channel 3B Full Address Mode End of transfer on channel 0 — End of transfer on channel 1 — End of transfer on channel 2 — End of transfer on channel 3 — Low Interrupt Priority High Each interrupt is enabled or disabled by the DTIE bit in the corresponding data transfer control register (DTCR). Separate interrupt signals are sent to the interrupt controller. The interrupt priority order among channels is channel 0 > channel 1 > channel 2 > channel 3, and channel A > channel B. The interrupt priority order between groups can be modified in interrupt priority register B (IPRB). Figure 8-26 shows the DMA-end interrupt logic. An interrupt is requested whenever DTE = 0 and DTIE = 1. 230 DTE DMA-end interrupt DTIE Figure 8-26 DMA-End Interrupt Logic The DMA-end interrupt for the B channels (DENDB) is unavailable in full address mode. The DTME bit does not affect interrupt operations. 231 8.6 Usage Notes 8.6.1 Note on Word Data Transfer Word data cannot be accessed starting at an odd address. When word-size transfer is selected, set even values in the memory and I/O address registers (MAR and IOAR). 8.6.2 DMAC Self-Access The DMAC itself cannot be accessed during a DMAC cycle. DMAC registers cannot be specified as source or destination addresses. 8.6.3 Longword Access to Memory Address Registers A memory address register can be accessed as longword data at the MARR address. Example MOV.L MOV.L #LBL, ER0 ER0, @MARR Four byte accesses are performed. Note that the CPU may release the bus between the second byte (MARE) and third byte (MARH). Memory address registers should be written and read only when the DMAC is halted. 8.6.4 Note on Full Address Mode Setup Full address mode is controlled by two registers: DTCRA and DTCRB. Care must be taken to prevent the B channel from operating in short address mode during the register setup. The enable bits (DTE and DTME) should not be set to 1 until the end of the setup procedure. 232 8.6.5 Note on Activating DMAC by Internal Interrupts When using an internal interrupt to activate the DMAC, make sure that the interrupt selected as the activating source does not occur during the interval after it has been selected but before the DMAC has been enabled. The on-chip supporting module that will generate the interrupt should not be activated until the DMAC has been enabled. If the DMAC must be enabled while the onchip supporting module is active, follow the procedure in figure 8-27. Enabling of DMAC Yes Interrupt handling by CPU Selected interrupt requested? No 1 1. While the DTE bit is cleared to 0, interrupt requests are sent to the CPU. 2. Clear the interrupt enable bit to 0 in the interrupt-generating on-chip supporting module. 3. Enable the DMAC. 4. Enable the DMAC-activating interrupt. Clear selected interrupt’s enable bit to 0 2 Enable DMAC 3 Set selected interrupt’s enable bit to 1 4 DMAC operates Figure 8-27 Procedure for Enabling DMAC while On-Chip Supporting Module is Operating (Example) If the DTE bit is set to 1 but the DTME bit is cleared to 0, the DMAC is halted and the selected activating source cannot generate a CPU interrupt. If the DMAC is halted by an NMI interrupt, for example, the selected activating source cannot generate CPU interrupts. To terminate DMAC operations in this state, clear the DTE bit to 0 to allow CPU interrupts to be requested. To continue DMAC operations, carry out steps 2 and 4 in figure 8-27 before and after setting the DTME bit to 1. 233 When an ITU interrupt activates the DMAC, make sure the next interrupt does not occur before the DMA transfer ends. If one ITU interrupt activates two or more channels, make sure the next interrupt does not occur before the DMA transfers end on all the activated channels. If the next interrupt occurs before a transfer ends, the channel or channels for which that interrupt was selected may fail to accept further activation requests. 8.6.6 NMI Interrupts and Block Transfer Mode If an NMI interrupt occurs in block transfer mode, the DMAC operates as follows. • When the NMI interrupt occurs, the DMAC finishes transferring the current byte or word, then clears the DTME bit to 0 and halts. The halt may occur in the middle of a block. It is possible to find whether a transfer was halted in the middle of a block by checking the block size counter. If the block size counter does not have its initial value, the transfer was halted in the middle of a block. • If the transfer is halted in the middle of a block, the activating interrupt flag is cleared to 0. The activation request is not held pending. While the DTE bit is set to 1 and the DTME bit is cleared to 0, the DMAC is halted and does not accept activating interrupt requests. If an activating interrupt occurs in this state, the DMAC does not operate and does not hold the transfer request pending internally. Neither is a CPU interrupt requested. For this reason, before setting the DTME bit to 1, first clear the enable bit of the activating interrupt to 0. Then, after setting the DTME bit to 1, set the interrupt enable bit to 1 again. See section 8.6.5, Note on Activating DMAC by Internal Interrupts. • When the DTME bit is set to 1, the DMAC waits for the next transfer request. If it was halted in the middle of a block transfer, the rest of the block is transferred when the next transfer request occurs. Otherwise, the next block is transferred when the next transfer request occurs. • 8.6.7 Memory and I/O Address Register Values Table 8-14 indicates the address ranges that can be specified in the memory and I/O address registers (MAR and IOAR). 234 Table 8-14 Address Ranges Specifiable in MAR and IOAR 1-Mbyte Mode MAR IOAR H'00000 to H'FFFFF (0 to 1048575) H'FFF00 to H'FFFFF (1048320 to 1048575) 16-Mbyte Mode H'000000 to H'FFFFFF (0 to 16777215) H'FFFF00 to H'FFFFFF (16776960 to 16777215) MAR bits 23 to 20 are ignored in 1-Mbyte mode. 8.6.8 Bus Cycle when Transfer is Aborted When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME bit, if this halts a channel for which the DMAC has a transfer request pending internally, a dead cycle occurs. This dead cycle does not update the halted channel’s address register or counter value. Figure 8-28 shows an example in which an auto-requested transfer in cycle-steal mode on channel 0 is aborted by clearing the DTE bit in channel 0. CPU cycle T1 ø T2 Td DMAC cycle T1 T2 T1 T2 T1 CPU cycle T2 T3 Td DMAC cycle Td CPU cycle T1 T2 Address bus RD GW, LWR DTE bit is cleared Figure 8-28 Bus Timing at Abort of DMA Transfer in Cycle-Steal Mode 235 236 Section 9 I/O Ports 9.1 Overview The H8/3003 has eight input/output ports (ports 4, 5, 6, 8, 9, A, B, and C) and one input port (port 7). Table 9-1 summarizes the port functions. The pins in each port are multiplexed as shown in table 9-1. Each port has a data direction register (DDR) for selecting input or output, and a data register (DR) for storing output data. In addition to their DDR and DR, ports 4 and 5 have an input pull-up control register (PCR) for switching input pull-up transistors on and off. Ports 4, 5, 6, 8, and C can drive one TTL load and a 90-pF capacitive load. Ports 9, A, and B can drive one TTL load and a 30-pF capacitive load. Ports 4 to 6 and 8 to C can drive a Darlington pair. Ports 5 and B can drive LEDs (with 10-mA current sink). Ports P82 to P80, PA7 to PA0, and PB3 to PB0 have Schmitt-trigger input circuits. For block diagrams of the ports see appendix C, I/O Port Block Diagrams. 237 Table 9-1 Port Functions Port Port 4 Description 8-bit I/O port Input pull-up Pins P47 to P40/D7 to D0 Mode 1 Mode 2 Mode 3 Mode 4 Data bus (D7 to D0) and 8-bit generic input/output 8-bit bus mode: generic input/output 16-bit bus mode: data bus Generic input/ output Address output Port 5 4-bit I/O port Input pull-up Can drive LEDs 3-bit I/O port P57 to P54/A23 to A20 Port 6 P62/BACK P61/BREQ P60/WAIT P77 to P70/AN7 to AN0 P84/CS0 P83/CS1/IRQ3 P82/CS2/IRQ2 P81/CS3/IRQ1 P80/RFSH/IRQ0 Bus control signal input/output (BACK, BREQ, WAIT) and 3-bit generic input/output Analog input (AN7 to AN0) to A/D converter, and 8-bit generic input DDR = 0: generic input DDR = 1 (reset value): CS0 output IRQ3 to IRQ1 input, CS1 to CS3 output, and generic input DDR = 0 (reset value): generic input DDR = 1: CS1 to CS3 output IRQ0 input, RFSH output, and generic input/output Input and output (SCK1, SCK0, RxD1, RxD0, TxD1, TxD0) for serial communication interfaces 1 and 0 (SCI1/0), IRQ5 and IRQ4 input, and 6-bit generic input/output Port 7 Port 8 8-bit input port 5-bit I/O port P82 to P80 have Schmitt inputs Port 9 6-bit I/O port P95/SCK1/IRQ5 P94/SCK0/IRQ4 P93/RxD1 P92/RxD0 P91/TxD1 P90/TxD0 238 Table 9-1 Port Functions (cont) Port Port A Description 8-bit I/O port Schmitt inputs Pins PA7/TP7/TIOCB2 PA6/TP6/TIOCA2 PA5/TP5/TIOCB1 PA4/TP4/TIOCA1 PA3/TP3/TIOCB0/TCLKD PA2/TP2/TIOCA0/TCLKC PA1/TP1/TEND1/TCLKB PA0/TP0/TEND0/TCLKA PB7/TP15/DREQ1/ADTRG PB6/TP14/DREQ0 PB5/TP13/TOCXB4 PB4/TP12/TOCXA4 PB3/TP11/TIOCB4 PB2/TP10/TIOCA4 PB1/TP9/TIOCB3 PB0/TP8/TIOCB3 PC7/IRQ7 PC6/IRQ6 PC5/DREQ3/CS7 PC4/TEND3/CS6 PC3/DREQ2/CS5 PC2/TEND2/CS4 PC1 PC0 Mode 1 Mode 2 Mode 3 Mode 4 Output (TP7 to TP0) from programmable timing pattern controller (TPC), output (TEND1, TEND0) from DMA controller (DMAC), input and output (TCLKD, TCLKC, TCLKB, TCLKA, TIOCB2, TIOCA2, TIOCB1, TIOCA1, TIOCB0, TIOCA0) for 16-bit integrated timer unit (ITU), and 8-bit generic input/output Output (TP15 to TP8) from TPC, input (DREQ1 and DREQ0) to DMAC, trigger input (ADTRG) to A/D converter, ITU input and output (TOCXB4, TOCXA4, TIOCB4, TIOCA4, TIOCB3, TIOCA3), and 8-bit generic input/output Port B 8-bit I/O port Can drive LEDs PB3 to PB0 have Schmitt inputs Port C 8-bit I/O port IRQ7 and IRQ6 input, CS7 to CS4 output, DMAC input and output (DREQ3, TEND3, DREQ2, TEND2), and 8-bit generic input/output 239 9.2 Port 4 9.2.1 Overview Port 4 is an 8-bit input/output port with the pin configuration shown in figure 9-1. The pin functions differ between the 8-bit and 16-bit bus modes. When the bus width control register (ABWCR) designates areas 0 to 7 all as 8-bit-access areas, the H8/3003 operates in 8-bit bus mode and port 4 is a generic input/output port. When at least one of areas 0 to 7 is designated as a 16-bit-access area, the H8/3003 operates in 16-bit bus mode and port 4 becomes the lower data bus. Port 4 has software-programmable built-in pull-up transistors. Pins in port 4 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor pair. Port 4 pins P47 /D7 P46 /D6 P45 /D5 Port 4 P44 /D4 P43 /D3 P42 /D2 P41 /D1 P40 /D0 8-bit bus mode * 1 P47 (input/output) P46 (input/output) P45 (input/output) P44 (input/output) P43 (input/output) P42 (input/output) P41 (input/output) P40 (input/output) 16-bit bus mode * 2 D 7 (input/output) D 6 (input/output) D 5 (input/output) D 4 (input/output) D 3 (input/output) D 2 (input/output) D 1 (input/output) D 0 (input/output) Notes: 1. Initial state in modes 1 and 3. 2. Initial state in modes 2 and 4. Figure 9-1 Port 4 Pin Configuration 240 9.2.2 Register Descriptions Table 9-2 summarizes the registers of port 4. Table 9-2 Port 4 Registers Address* H'FFC5 H'FFC7 H'FFDA Name Port 4 data direction register Port 4 data register Port 4 input pull-up control register Abbreviation P4DDR P4DR P4PCR R/W W R/W R/W Initial Value H'00 H'00 H'00 Note: * Lower 16 bits of the address. Port 4 Data Direction Register (P4DDR): P4DDR is an 8-bit write-only register that can select input or output for each pin in port 4. Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P4 7 DDR P4 6 DDR P4 5 DDR P4 4 DDR P4 3 DDR P4 2 DDR P4 1 DDR P4 0 DDR Port 4 data direction 7 to 0 These bits select input or output for port 4 pins 8-Bit Bus Mode: When all areas are designated as 8-bit-access areas, selecting 8-bit bus mode, port 4 functions as a generic input/output port. A pin in port 4 becomes an output pin if the corresponding P4DDR bit is set to 1, and an input pin if this bit is cleared to 0. 16-Bit Bus Mode: When at least one area is designated as a 16-bit-access area, selecting 16-bit bus mode, port 4 functions as the lower data bus. P4DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P4DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. ABWCR and P4DDR are not initialized in software standby mode. When port 4 functions as a generic input/output port, if a P4DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. 241 Port 4 Data Register (P4DR): P4DR is an 8-bit readable/writable register that stores data for pins P47 to P40. Bit Initial value Read/Write 7 P4 7 DR 0 R/W 6 P4 6 DR 0 R/W 5 P4 5 DR 0 R/W 4 P4 4 DR 0 R/W 3 P4 3 DR 0 R/W 2 P4 2 DR 0 R/W 1 P4 1 DR 0 R/W 0 P4 0 DR 0 R/W Port 4 data 7 to 0 These bits store data for port 4 pins When a bit in P4DDR is set to 1, if port 4 is read the value of the corresponding P4DR bit is returned directly, regardless of the actual state of the pin. When a bit in P4DDR is cleared to 0, if port 4 is read the corresponding pin level is read. This applies in both 8-bit and 16-bit bus modes. P4DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Port 4 Input Pull-Up Control Register (P4PCR): P4PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port 4. Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P4 7 PCR P4 6 PCR P4 5 PCR P4 4 PCR P4 3 PCR P4 2 PCR P4 1 PCR P4 0 PCR Port 4 input pull-up control 7 to 0 These bits control input pull-up transistors built into port 4 In 8-bit bus mode, when a P4DDR bit is cleared to 0 (selecting generic input), if the corresponding P4PCR bit is set to 1, the input pull-up transistor is turned on. P4PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. 242 9.2.3 Pin Functions in Each Mode The functions of port 4 differ depending on whether 8-bit or 16-bit bus mode is selected by ABWCR settings. The pin functions in each mode are described below. 8-Bit Bus Mode: Input or output can be selected separately for each pin in port 4. A pin becomes an output pin if the corresponding P4DDR bit is set to 1 and an input pin if this bit is cleared to 0. Figure 9-2 shows the pin functions in 8-bit bus mode. This is the initial state in modes 1 and 3. P47 (input/output) P46 (input/output) P45 (input/output) Port 4 P44 (input/output) P43 (input/output) P42 (input/output) P41 (input/output) P40 (input/output) Figure 9-2 Pin Functions in 8-Bit Bus Mode (Port 4) 16-Bit Bus Mode: The input/output settings in P4DDR are ignored. Port 4 automatically becomes a bidirectional data bus. Figure 9-3 shows the pin functions in 16-bit bus mode. This is the initial state in modes 2 and 4. 243 D 7 (input/output) D 6 (input/output) D 5 (input/output) Port 4 D 4 (input/output) D 3 (input/output) D 2 (input/output) D 1 (input/output) D 0 (input/output) Figure 9-3 Pin Functions in 16-Bit Bus Mode (Port 4) 9.2.4 Input Pull-Up Transistors Port 4 has built-in MOS input pull-up transistors that can be controlled by software. These input pull-up transistors can be used in 8-bit bus mode. They can be turned on and off individually. In 8-bit bus mode, when a P4PCR bit is set to 1 and the corresponding P4DDR bit is cleared to 0, the input pull-up transistor is turned on. The input pull-up transistors are turned off by a reset and in hardware standby mode. In software standby mode they retain their previous state. Table 9-3 summarizes the states of the input pull-ups in the 8-bit and 16-bit bus modes. Table 9-3 Input Pull-Up Transistor States (Port 4) Mode 8-bit bus mode 16-bit bus mode Reset Off Hardware Standby Mode Software Standby Mode On/off Off Other Modes Legend Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P4PCR = 1 and P4DDR = 0. Otherwise, it is off. 244 9.3 Port 5 9.3.1 Overview Port 5 is a 4-bit input/output port with the pin configuration shown in figure 9-4. The pin functions differ depending on the operating mode. In modes 1 and 2, port 5 is a generic input/output port. In modes 3 and 4, port 5 is used for address output. Port 5 has software-programmable built-in pull-up transistors. Pins in port 5 can drive one TTL load and a 90-pF capacitive load. They can also drive an LED or a darlington transistor pair. Port 5 pins P57 /A 23 Port 5 P56 /A 22 P55 /A 21 P54 /A 20 Modes 1 and 2 P57 (input/output) P56 (input/output) P55 (input/output) P54 (input/output) Modes 3 and 4 A 23 (output) A 22 (output) A 21 (output) A 20 (output) Figure 9-4 Port 5 Pin Configuration 9.3.2 Register Descriptions Table 9-4 summarizes the registers of port 5. Table 9-4 Port 5 Registers Initial Value Address* H'FFC8 H'FFCA H'FFDB Name Port 5 data direction register Port 5 data register Port 5 input pull-up control register Abbreviation P5DDR P5DR P5PCR R/W W R/W R/W Mode 1/2 H'0F H'00 H'00 Mode 3/4 H'FF Note: * Lower 16 bits of the address. 245 Port 5 Data Direction Register (P5DDR): P5DDR is an 8-bit write-only register that can select input or output for each pin in port 5. Bit Mode Initial value 1/2 Read/Write Mode Initial value 3/4 Read/Write 7 0 W 1 — 6 0 W 1 — 5 0 W 1 — 4 0 W 1 — 3 1 — 1 — 2 1 — 1 — 1 1 — 1 — 0 1 — 1 — P5 7 DDR P5 6 DDR P5 5 DDR P5 4 DDR P5 3 DDR P5 2 DDR P5 1 DDR P5 0 DDR Port 5 data direction 7 to 4 These bits select input or output for port 5 pins Reserved bits Modes 1 and 2 (1-Mbyte Modes): Port 5 functions as a generic input/output port. A pin in port 5 becomes an output pin if the corresponding P5DDR bit is set to 1, and an input pin if this bit is cleared to 0. Modes 3 and 4 (16-Mbyte Modes): All P5DDR bits are fixed at 1 and port 5 functions as part of the address bus. Bits P53DDR to P50DDR are reserved and are also fixed at 1. No bit values can be modified. In modes 1 and 2, P5DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P5DDR is initialized to H'0F by a reset and in hardware standby mode. In software standby mode it retains its previous setting, so if a P5DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. 246 Port 5 Data Register (P5DR): P5DR is an 8-bit readable/writable register that stores data for pins P57 to P54. Bit Initial value Read/Write 7 P5 7 0 R/W 6 P5 6 0 R/W 5 P5 5 0 R/W 4 P5 4 0 R/W 3 P5 3 0 R/W 2 P5 2 0 R/W 1 P5 1 0 R/W 0 P5 0 0 R/W Port 5 data 7 to 4 These bits store data for port 5 pins Reserved bits When a bit in P5DDR is set to 1, if port 5 is read the value of the corresponding P5DR bit is returned directly, regardless of the actual state of the pin. When a bit in P5DDR is cleared to 0, if port 5 is read the corresponding pin level is read. Bits P53 to P50 are reserved. They can be written and read, but they cannot be used for port input or output. P5DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Port 5 Input Pull-Up Control Register (P5PCR): P5PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port 5. Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P5 7 PCR P5 6 PCR P5 5 PCR P5 4 PCR P5 3 PCR P5 2 PCR P5 1 PCR P5 0 PCR Port 5 input pull-up control 7 to 4 These bits control input pull-up transistors built into port 5 Reserved bits In modes 1 and 2, when a P5DDR bit is cleared to 0 (selecting generic input), if the corresponding bit from P57PCR to P54PCR is set to 1, the input pull-up transistor is turned on. Bits P53PCR to P50PCR are reserved. They can be written and read, but they do not control input pull-up transistors. P5PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. 247 9.3.3 Pin Functions in Each Mode The functions of port 5 differ between modes 1 and 2 (1-Mbytes modes) and modes 3 and 4 (16-Mbyte modes). The pin functions in each mode are described below. Pin Functions in Modes 1 and 2 (1-Mbytes Modes): Input or output can be selected separately for each pin in port 5. A pin becomes an output pin if the corresponding P5DDR bit is set to 1 and an input pin if this bit is cleared to 0. Figure 9-5 shows the pin functions in modes 1 and 2. P57 (input/output) Port 5 P56 (input/output) P55 (input/output) P54 (input/output) Figure 9-5 Pin Functions in Modes 1 and 2 (Port 5) Pin Functions in Modes 3 and 4 (16-Mbytes Modes): The pins in port 5 are automatically used for address output. Figure 9-6 shows the pin functions in modes 3 and 4. A 23 (output) Port 5 A 22 (output) A 21 (output) A 20 (output) Figure 9-6 Pin Functions in Modes 3 and 4 (Port 5) 248 9.3.4 Input Pull-Up Transistors Port 5 has built-in MOS pull-up transistors that can be controlled by software. These input pull-up transistors can be used in modes 1 and 2. They can be turned on and off individually. In modes 1 and 2, when a P5PCR bit is set to 1 and the corresponding P5DDR bit is cleared to 0, the input pull-up transistor is turned on. The input pull-up transistors are turned off by a reset and in hardware standby mode. In software standby mode they retain their previous state. Table 9-5 summarizes the states of the input pull-ups in each mode. Table 9-5 Input Pull-Up Transistor States (Port 5) Mode 1 2 3 4 Reset Off Hardware Standby Mode Software Standby Mode On/off Off Other Modes Legend Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P5PCR = 1 and P5DDR = 0. Otherwise, it is off. 249 9.4 Port 6 9.4.1 Overview Port 6 is a 3-bit input/output port that is also used for input and output of bus control signals (BACK, BREQ, and WAIT). Port 6 has the same set of pin functions in all operating modes. Figure 9-7 shows the pin configuration of port 6. Pins in port 6 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor pair. Port 6 pins P62 (input/output)/BACK (output) Port 6 P61 (input/output)/BREQ (input) P60 (input/output)/WAIT (input) Figure 9-7 Port 6 Pin Configuration 9.4.2 Register Descriptions Table 9-6 summarizes the registers of port 6. Table 9-6 Port 6 Registers Address* H'FFC9 H'FFCB Name Port 6 data direction register Port 6 data register Abbreviation P6DDR P6DR R/W W R/W Initial Value H'80 H'80 Note: * Lower 16 bits of the address. 250 Port 6 Data Direction Register (P6DDR): P6DDR is an 8-bit write-only register that can select input or output for each pin in port 6. Bit Initial value Read/Write 7 — 1 — 6 0 W 5 0 W Reserved bits 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P6 6 DDR P6 5 DDR P6 4 DDR P6 3 DDR P6 2 DDR P6 1 DDR P6 0 DDR Port 6 data direction 2 to 0 These bits select input or output for port 6 pins A pin in port 6 becomes an output pin if the corresponding P6DDR bit is set to 1, and an input pin if this bit is cleared to 0. Bits 7 to 3 are reserved. P6DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P6DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it retains its previous setting, so if a P6DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. Port 6 Data Register (P6DR): P6DR is an 8-bit readable/writable register that stores data for pins P62 to P60. Bit Initial value Read/Write 7 — 1 — 6 P6 6 0 R/W 5 P6 5 0 R/W 4 P6 4 0 R/W 3 P6 3 0 R/W 2 P6 2 0 R/W 1 P6 1 0 R/W 0 P6 0 0 R/W Reserved bits Port 6 data 2 to 0 These bits store data for port 6 pins When a bit in P6DDR is set to 1, if port 6 is read the value of the corresponding P6DR bit is returned directly. When a bit in P6DDR is cleared to 0, if port 6 is read the corresponding pin level is read. In this case bit 7 reads 1 and bits 6 to 3 have undetermined values. Bits 7 to 3 are reserved. Bits 6 to 3 can be written and read, but they cannot be used for port input or output. Bit 7 cannot be modified and always reads 1. P6DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. 251 9.4.3 Pin Functions The port 6 pins are also used for BACK output and BREQ and WAIT input. Table 9-7 describes the selection of pin functions. Table 9-7 Port 6 Pin Functions Pin P62/BACK Pin Functions and Selection Method Bit BRLE in BRCR and bit P62DDR select the pin function as follows BRLE P62DDR Pin function P61/BREQ 0 P62 input 0 1 P62 output 1 — BACK output Bit BRLE in BRCR and bit P61DDR select the pin function as follows BRLE P61DDR Pin function 0 P61 input 0 1 P61 output 1 — BREQ input P60/WAIT Bits WCE7 to WCE0 in WCER, bit WMS1 in WCR, and bit P60DDR select the pin function as follows WCER WMS1 P60DDR Pin function 0 P60 input 0 1 P60 output All 1s 1 0* Not all 1s — 0* WAIT input Note: * Do not set bit P60DDR to 1. 9.5 Port 7 9.5.1 Overview Port 7 is an 8-bit input port that is also used for analog input to the A/D converter. Port 7 has the same set of pin functions in all operating modes. Figure 9-8 shows the pin configuration of port 7. 252 Port 7 pins P77 (input)/AN 7 (input) P76 (input)/AN 6 (input) P75 (input)/AN 5 (input) Port 7 P74 (input)/AN 4 (input) P73 (input)/AN 3 (input) P72 (input)/AN 2 (input) P71 (input)/AN 1 (input) P70 (input)/AN 0 (input) Figure 9-8 Port 7 Pin Configuration 9.5.2 Register Description Table 9-8 summarizes the port 7 register. Port 7 is an input-only port, so it has no data direction register. Table 9-8 Port 7 Register Address* H'FFCE Name Port 7 data register Abbreviation P7DR R/W R Initial Value Undetermined Note: * Lower 16 bits of the address. Port 7 Data Register (P7DR) Bit Initial value Read/Write 7 P77 —* R 6 P76 —* R 5 P75 —* R 4 P74 —* R 3 P73 —* R 2 P72 —* R 1 P71 —* R 0 P70 —* R Note: * Determined by pins P7 7 to P70 . When port 7 is read, the pin levels are always read. 253 9.6 Port 8 9.6.1 Overview Port 8 is a 5-bit input/output port that is also used for CS3 to CS0 output, RFSH output, and IRQ3 to IRQ0 input. Port 8 has the same set of pin functions in all operating modes. Figure 9-9 shows the pin configuration of port 8. Pins in port 8 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor pair. Pins P82 to P80 have Schmitt-trigger inputs. Port 8 pins P84 (input)/CS0 (output) P83 (input)/CS1 (output)/IRQ 3 (input) Port 8 P82 (input)/CS2 (output)/IRQ 2 (input) P81 (input)/CS3 (output)/IRQ 1 (input) P80 (input/output)/RFSH (output)/IRQ 0 (input) Figure 9-9 Port 8 Pin Configuration 9.6.2 Register Descriptions Table 9-9 summarizes the registers of port 8. Table 9-9 Port 8 Registers Address* H'FFCD H'FFCF Name Port 8 data direction register Port 8 data register Abbreviation P8DDR P8DR R/W W R/W Initial Value H'F0 H'E0 Note: * Lower 16 bits of the address. 254 Port 8 Data Direction Register (P8DDR): P8DDR is an 8-bit write-only register that can select input or output for each pin in port 8. Bit Initial value Read/Write 7 — 1 — 6 — 1 — Reserved bits 5 — 1 — 4 1 W 3 0 W 2 0 W 1 0 W 0 0 W P8 4 DDR P8 3 DDR P8 2 DDR P8 1 DDR P8 0 DDR Port 8 data direction 4 to 0 These bits select input or output for port 8 pins When bits in P8DDR bit are set to 1, P84 to P81 become CS0 to CS3 output pins and P80 becomes a generic output pin. When bits in P8DDR are cleared to 0, the corresponding pins become input pins. P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P8DDR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting, so if a P8DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. Port 8 Data Register (P8DR): P8DR is an 8-bit readable/writable register that stores data for pins P84 to P80. Bit Initial value Read/Write 7 — 1 — 6 — 1 — Reserved bits 5 — 1 — 4 P8 4 0 R/W 3 P8 3 0 R/W 2 P8 2 0 R/W 1 P8 1 0 R/W 0 P8 0 0 R/W Port 8 data 4 to 0 These bits store data for port 8 pins When a bit in P8DDR is set to 1, if port 8 is read the value of the corresponding P8DR bit is returned directly. When a bit in P8DDR is cleared to 0, if port 8 is read the corresponding pin level is read. Bits 7 to 5 are reserved. They cannot be modified and always read 1. P8DR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. 255 9.6.3 Pin Functions The port 8 pins are also used for CS3 to CS0 and RFSH output and IRQ3 to IRQ0 input. Table 9-10 describes the selection of pin functions. Table 9-10 Port 8 Pin Functions Pin P84/CS0 Pin Functions and Selection Method Bit P84DDR selects the pin function as follows P84DDR Pin function P83/CS1/IRQ3 0 P84 input 1 CS0 output Bit P83DDR selects the pin function as follows P83DDR Pin function 0 P83 input IRQ3 input 1 CS1 output P82/CS2/IRQ2 Bit P82DDR selects the pin function as follows P82DDR Pin function 0 P82 input IRQ2 input 1 CS2 output P81/CS3/IRQ1 Bit P81DDR selects the pin function as follows P81DDR Pin function 0 P81 input IRQ1 input 1 CS3 output P80/RFSH/IRQ0 Bit RFSHE in RFSHCR and bit P80DDR select the pin function as follows RFSHE P80DDR Pin function 0 P80 input 0 1 P80 output IRQ0 input 1 — RFSH output 256 9.7 Port 9 9.7.1 Overview Port 9 is a 6-bit input/output port that is also used for input and output (TxD0, TxD1, RxD0, RxD1, SCK0, SCK1) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ5 and IRQ4 input. Port 9 has the same set of pin functions in all operating modes. Figure 9-10 shows the pin configuration of port 9. Pins in port 9 can drive one TTL load and a 30-pF capacitive load. They can also drive a darlington transistor pair. Port 9 pins P95 (input/output)/SCK 1 (input/output)/IRQ 5 (input) P94 (input/output)/SCK 0 (input/output)/IRQ 4 (input) Port 9 P93 (input/output)/RxD1 (input) P92 (input/output)/RxD0 (input) P91 (input/output)/TxD1 (output) P90 (input/output)/TxD0 (output) Figure 9-10 Port 9 Pin Configuration 9.7.2 Register Descriptions Table 9-11 summarizes the registers of port 9. Table 9-11 Port 9 Registers Address* H'FFD0 H'FFD2 Name Port 9 data direction register Port 9 data register Abbreviation P9DDR P9DR R/W W R/W Initial Value H'C0 H'C0 Note: * Lower 16 bits of the address. 257 Port 9 Data Direction Register (P9DDR): P9DDR is an 8-bit write-only register that can select input or output for each pin in port 9. Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P9 5 DDR P9 4 DDR P9 3 DDR P9 2 DDR P9 1 DDR P9 0 DDR Reserved bits Port 9 data direction 5 to 0 These bits select input or output for port 9 pins A pin in port 9 becomes an output pin if the corresponding P9DDR bit is set to 1, and an input pin if this bit is cleared to 0. P9DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P9DDR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting, so if a P9DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. Port 9 Data Register (P9DR): P9DR is an 8-bit readable/writable register that stores data for pins P95 to P90. Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 P9 5 0 R/W 4 P9 4 0 R/W 3 P9 3 0 R/W 2 P9 2 0 R/W 1 P9 1 0 R/W 0 P9 0 0 R/W Reserved bits Port 9 data 5 to 0 These bits store data for port 9 pins When a bit in P9DDR is set to 1, if port 9 is read the value of the corresponding P9DR bit is returned directly. When a bit in P9DDR is cleared to 0, if port 9 is read the corresponding pin level is read. Bits 7 and 6 are reserved. They cannot be modified and always read 1. P9DR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. 258 9.7.3 Pin Functions The port 9 pins are also used for SCI0 and SCI1 input and output (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1), and for IRQ5 and IRQ4 input. Table 9-12 describes the selection of pin functions. Table 9-12 Port 9 Pin Functions Pin P95/SCK1/IRQ5 Pin Functions and Selection Method Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR of SCI1, and bit P95DDR select the pin function as follows CKE1 C/A CKE0 P95DDR Pin function 0 0 1 0 1 — 0 1 — — SCK1 output 1 — — — SCK1 input P95 SCK1 output P95 input output IRQ5 input P94/SCK0/IRQ4 Bit C/A in SMR of SCI0, bits CKE0 and CKE1 in SCR of SCI0, and bit P94DDR select the pin function as follows CKE1 C/A CKE0 P94DDR Pin function 0 0 1 0 1 — 0 1 — — SCK0 output 1 — — — SCK0 input P94 SCK0 output P94 input output IRQ4 input 259 Table 9-12 Port 9 Pin Functions (cont) Pin P93/RxD1 Pin Functions and Selection Method Bit RE in SCR of SCI1 and bit P93DDR select the pin function as follows RE P93DDR Pin function P92/RxD0 0 P93 input 0 1 P93 output 1 — RxD1 input Bit RE in SCR of SCI0 and bit P92DDR select the pin function as follows RE P92DDR Pin function 0 P92 input 0 1 P92 output 1 — RxD0 input P91/TxD1 Bit TE in SCR of SCI1 and bit P91DDR select the pin function as follows TE P91DDR Pin function 0 P91 input 0 1 P91 output 1 — TxD1 output P90/TxD0 Bit TE in SCR of SCI0 and bit P90DDR select the pin function as follows TE P90DDR Pin function 0 P90 input 0 1 P90 output 1 — TxD0 output 260 9.8 Port A 9.8.1 Overview Port A is an 8-bit input/output port that is also used for output (TP7 to TP0) from the programmable timing pattern controller (TPC), input and output (TIOCB2, TIOCA2, TIOCB1, TIOCA1, TIOCB0, TIOCA0, TCLKD, TCLKC, TCLKB, TCLKA) by the 16-bit integrated timerpulse unit (ITU), and output (TEND1, TEND0) from the DMA controller (DMAC). Port A has the same set of pin functions in all operating modes. Figure 9-11 shows the pin configuration of port A. Pins in port A can drive one TTL load and a 30-pF capacitive load. They can also drive a darlington transistor pair. Port A has Schmitt-trigger inputs. Port A pins PA 7 (input/output)/TP7 (output)/TIOCB2 (input/output) PA 6 (input/output)/TP6 (output)/TIOCA2 (input/output) PA 5 (input/output)/TP5 (output)/TIOCB1 (input/output) PA 4 (input/output)/TP4 (output)/TIOCA1 (input/output) Port A PA 3 (input/output)/TP3 (output)/TIOCB0 (input/output)/TCLKD (input) PA 2 (input/output)/TP2 (output)/TIOCA0 (input/output)/TCLKC (input) PA 1 (input/output)/TP1 (output)/TEND1 (output)/TCLKB (input) PA 0 (input/output)/TP0 (output)/TEND0 (output)/TCLKA (input) Figure 9-11 Port A Pin Configuration 9.8.2 Register Descriptions Table 9-13 summarizes the registers of port A. Table 9-13 Port A Registers Address* H'FFD1 H'FFD3 Name Port A data direction register Port A data register Abbreviation PADDR PADR R/W W R/W Initial Value H'00 H'00 Note: * Lower 16 bits of the address. 261 Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select input or output for each pin in port A. Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PA7 DDR PA6 DDR PA5 DDR PA4 DDR PA3 DDR PA2 DDR PA1 DDR PA0 DDR Port A data direction 7 to 0 These bits select input or output for port A pins A pin in port A becomes an output pin if the corresponding PADDR bit is set to 1, and an input pin if this bit is cleared to 0. PADDR is a write-only register. Its value cannot be read. All bits return 1 when read. PADDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting, so if a PADDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores data for pins PA7 to PA0. Bit Initial value Read/Write 7 PA 7 0 R/W 6 PA 6 0 R/W 5 PA 5 0 R/W 4 PA 4 0 R/W 3 PA 3 0 R/W 2 PA 2 0 R/W 1 PA 1 0 R/W 0 PA 0 0 R/W Port A data 7 to 0 These bits store data for port A pins When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned directly. When a bit in PADDR is cleared to 0, if port A is read the corresponding pin level is read. PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. 262 9.8.3 Pin Functions The port A pins are also used for TPC output (TP7 to TP0), ITU input/output (TIOCB2 to TIOCB0, TIOCA2 to TIOCA0) and input (TCLKD, TCLKC, TCLKB, TCLKA), and DMAC output (TEND1, TEND0). Table 9-14 describes the selection of pin functions. Table 9-14 Port A Pin Functions Pin PA7/TP7/TIOCB2 Pin Functions and Selection Method ITU channel 2 settings (bit PWM2 in TMDR and bits IOB2 to IOB0 in TIOR2), bit NDER7 in NDERA, and bit PA7DDR in PADDR select the pin function as follows ITU channel 2 settings PA7DDR NDER7 Pin function 1 in table below — — TIOCB2 output 0 — 2 in table below 1 0 PA7 output 1 1 TP7 output PA7 input TIOCB2 input* Note: * TIOCB2 input when IOB2 = 1 and PWM2 = 0. ITU channel 2 settings IOB2 IOB1 IOB0 0 0 2 0 0 1 1 2 1 1 — — — 263 Table 9-14 Port A Pin Functions (cont) Pin PA6/TP6/TIOCA2 Pin Functions and Selection Method ITU channel 2 settings (bit PWM2 in TMDR and bits IOA2 to IOA0 in TIOR2), bit NDER6 in NDERA, and bit PA6DDR in PADDR select the pin function as follows ITU channel 2 settings PA6DDR NDER6 Pin function 1 in table below — — TIOCA2 output 0 — PA6 input 2 in table below 1 0 PA6 output 1 1 TP6 output TIOCA2 input* Note: * TIOCA2 input when IOA2 = 1. ITU channel 2 settings PWM2 IOA2 IOA1 IOA0 PA5/TP5/TIOCB1 0 0 0 0 1 1 — 2 1 0 1 — — 2 1 1 — — — ITU channel 1 settings (bit PWM1 in TMDR and bits IOB2 to IOB0 in TIOR1), bit NDER5 in NDERA, and bit PA5DDR in PADDR select the pin function as follows ITU channel 2 settings PA5DDR NDER5 Pin function 1 in table below — — TIOCB1 output 0 — PA5 input 2 in table below 1 0 PA5 output 1 1 TP5 output TIOCB1 input* Note: * TIOCB1 input when IOB2 = 1 and PWM1 = 0. ITU channel 1 settings IOB2 IOB1 IOB0 0 0 2 0 0 1 1 — 1 2 1 — — 264 Table 9-14 Port A Pin Functions (cont) Pin PA4/TP4/TIOCA1 Pin Functions and Selection Method ITU channel 1 settings (bit PWM1 in TMDR and bits IOA2 to IOA0 in TIOR1), bit NDER4 in NDERA, and bit PA4DDR in PADDR select the pin function as follows ITU channel 1 settings PA4DDR NDER4 Pin function 1 in table below — — TIOCA1 output 0 — PA4 input 2 in table below 1 0 PA4 output 1 1 TP4 output TIOCA1 input* Note: * TIOCA1 input when IOA2 = 1. ITU channel 1 settings PWM1 IOA2 IOA1 IOA0 PA3/TP3/TIOCB0/ TCLKD 0 0 0 0 1 1 — 2 1 0 1 — — 2 1 1 — — — ITU channel 0 settings (bit PWM0 in TMDR and bits IOB2 to IOB0 in TIOR0), bits TPSC2 to TPSC0 in timer control registers 4 to 0 (TCR4 to TCR0), bit NDER3 in NDERA, and bit PA3DDR in PADDR select the pin function as follows ITU channel 0 settings PA3DDR NDER3 Pin function 1 in table below — — TIOCB0 output 0 — PA3 input 2 in table below 1 0 PA3 output 1 1 TP3 output TIOCB0 input*1 TCLKD input*2 Notes: 1. TIOCB0 input when IOB2 = 1 and PWM0 = 0. 2. TCLKD input when TPSC2 = TPSC1 = TPSC0 = 1 in any of TCR4 to TCR0. ITU channel 0 settings IOB2 IOB1 IOB0 0 0 265 2 0 0 1 1 — 1 2 1 — — Table 9-14 Port A Pin Functions (cont) Pin PA2/TP2/TIOCA0/ TCLKC Pin Functions and Selection Method ITU channel 0 settings (bit PWM0 in TMDR and bits IOA2 to IOA0 in TIOR0), bits TPSC2 to TPSC0 in TCR4 to TCR0, bit NDER2 in NDERA, and bit PA2DDR in PADDR select the pin function as follows ITU channel 0 settings PA2DDR NDER2 Pin function 1 in table below — — TIOCA0 output 0 — PA2 input 2 in table below 1 0 PA2 output 1 1 TP2 output TIOCA0 input*1 and TCLKC input*2 Notes: 1. TIOCA0 input when IOA2 = 1. 2. TCLKC input when TPSC2 = TPSC1 = 1 and TPSC0 = 0 in any of TCR4 to TCR0. ITU channel 0 settings PWM0 IOA2 IOA1 IOA0 0 0 0 0 1 1 — 2 1 0 2 1 1 1 — — — — — 266 Table 9-14 Port A Pin Functions (cont) Pin PA1/TP1/TCLKB/ TEND1 Pin Functions and Selection Method DMAC channel 1 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR1A and DTCR1B), bit NDER1 in NDERA, and bit PA1DDR in PADDR select the pin function as follows DMAC channel 1 settings PA1DDR NDER1 Pin function 1 in table below — — TEND1 output 0 — PA1 input TCLKB input* Note: * TCLKB input when MDF = 1 in TMDR, or when TPSC2 = 1, TPSC1 = 0, and TPSC0 = 1 in any of TCR4 to TCR0. DMAC channel 1 settings DTS2A, DTS1A DTS0A DTS2B DTS1B PA0/TP0/TCLKA/ TEND0 0 — 2 Not both 1 — 1 0 1 1 0 0 — 0 1 — 1 2 1 1 0 — 2 Both 1 1 1 0 1 1 1 1 2 in table below 1 0 PA1 output 1 1 TP1 output DMAC channel 0 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR0A and DTCR0B), bit NDER0 in NDERA, and bit PA0DDR in PADDR select the pin function as follows DMAC channel 0 settings PA0DDR NDER0 Pin function 1 in table below — — TEND0 output 0 — PA0 input TCLKA input* Note: * TCLKA input when MDF = 1 in TMDR, or when TPSC2 = 1 and TPSC1 = 0 in any of TCR4 to TCR0. DMAC channel 0 settings DTS2A, DTS1A DTS0A DTS2B DTS1B 0 — 2 Not both 1 — 1 0 1 1 0 0 — 0 1 — 1 2 1 1 0 — 2 Both 1 1 1 0 1 1 1 1 2 in table below 1 0 PA0 output 1 1 TP0 output 267 9.9 Port B 9.9.1 Overview Port B is an 8-bit input/output port that is also used for output (TP15 to TP8) from the programmable timing pattern controller (TPC), input/output (TIOCB4, TIOCB3, TIOCA4, TIOCA3) and output (TOCXB4, TOCXA4) by the 16-bit integrated timer-pulse unit (ITU), input (DREQ1, DREQ0) to the DMA controller (DMAC), and ADTRG input to the A/D converter. Port B has the same set of pin functions in all operating modes. Figure 9-12 shows the pin configuration of port B. Pins in port B can drive one TTL load and a 30-pF capacitive load. They can also drive a darlington transistor pair. Pins PB3 to PB0 have Schmitt-trigger inputs. Port B pins PB 7 (input/output)/TP15 (output)/DREQ1 (input)/ADTRG (input) PB 6 (input/output)/TP14 (output)/DREQ0 (input) PB 5 (input/output)/TP13 (output)/TOCXB 4 (output) PB 4 (input/output)/TP12 (output)/TOCXA 4 (output) Port B PB 3 (input/output)/TP11 (output)/TIOCB 4 (input/output) PB 2 (input/output)/TP10 (output)/TIOCA 4 (input/output) PB 1 (input/output)/TP9 (output)/TIOCB 3 (input/output) PB 0 (input/output)/TP8 (output)/TIOCA 3 (input/output) Figure 9-12 Port B Pin Configuration 9.9.2 Register Descriptions Table 9-15 summarizes the registers of port B. Table 9-15 Port B Registers Address* H'FFD4 H'FFD6 Name Port B data direction register Port B data register Abbreviation PBDDR PBDR R/W W R/W Initial Value H'00 H'00 Note: * Lower 16 bits of the address. 268 Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select input or output for each pin in port B. Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PB7 DDR PB6 DDR PB5 DDR PB4 DDR PB3 DDR PB2 DDR PB1 DDR PB0 DDR Port B data direction 7 to 0 These bits select input or output for port B pins A pin in port B becomes an output pin if the corresponding PBDDR bit is set to 1, and an input pin if this bit is cleared to 0. PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read. PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting, so if a PBDDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores data for pins PB7 to PB0. Bit Initial value Read/Write 7 PB 7 0 R/W 6 PB 6 0 R/W 5 PB 5 0 R/W 4 PB 4 0 R/W 3 PB 3 0 R/W 2 PB 2 0 R/W 1 PB 1 0 R/W 0 PB 0 0 R/W Port B data 7 to 0 These bits store data for port B pins When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is returned directly. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin level is read. PBDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. 269 9.9.3 Pin Functions The port B pins are also used for TPC output (TP15 to TP8), ITU input/output (TIOCB4, TIOCB3, TIOCA4, TIOCA3) and output (TOCXB4, TOCXA4), DMAC input (DREQ1, DREQ0), and ADTRG input. Table 9-16 describes the selection of pin functions. Table 9-16 Port B Pin Functions Pin Pin Functions and Selection Method PB7/TP15/DREQ1/ DMAC channel 1 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR1A and ADTRG DTCR1B), bit TRGE in ADCR, bit NDER15 in NDERB, and bit PB7DDR in PBDDR select the pin function as follows PB7DDR NDER15 Pin function 0 — PB7 input 1 0 PB7 output DREQ1 input*1 ADTRG input*2 Notes: 1. DREQ1 input under DMAC channel 1 settings 1 in the table below. 2. ADTRG input when TRGE = 1. DMAC channel 1 settings DTS2A, DTS1A DTS0A DTS2B DTS1B 0 — 1 1 TP15 output 2 Not both 1 — 1 0 1 2 1 2 Both 1 2 1 0 1 1 0 — 0 1 — 1 0 — 1 1 0 1 1 1 270 Table 9-16 Port B Pin Functions (cont) Pin PB6/TP14/DREQ0 Pin Functions and Selection Method DMAC channel 0 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR0A and DTCR0B), bit NDER14 in NDERB, and bit PB6DDR in PBDDR select the pin function as follows PB6DDR NDER14 Pin function 0 — PB6 input 1 0 PB6 output DREQ0 input* Note: * DREQ0 input under DMAC channel 0 settings 1 in the table below. DMAC channel 0 settings DTS2A, DTS1A DTS0A DTS2B DTS1B 0 — 1 1 TP14 output 2 Not both 1 — 1 0 1 2 1 2 Both 1 2 1 0 1 1 0 — 0 1 — 1 0 — 1 1 0 1 1 1 PB5/TP13/TOCXB4 ITU channel 4 settings (bit CMD1 in TFCR and bit EXB4 in TOER), bit NDER13 in NDERB, and bit PB5DDR in PBDDR select the pin function as follows EXB4, CMD1 PB5DDR NDER13 Pin function 0 — PB5 input Not both 1 1 0 PB5 output 1 1 TP13 output Both 1 — — TOCXB4 output PB4/TP12/TOCXA4 ITU channel 4 settings (bit CMD1 in TFCR and bit EXA4 in TOER), bit NDER12 in NDERB, and bit PB4DDR in PBDDR select the pin function as follows EXA4, CMD1 PB4DDR NDER12 Pin function 0 — PB4 input Not both 1 1 0 PB4 output 1 1 TP12 output Both 1 — — TOCXA4 output 271 Table 9-16 Port B Pin Functions (cont) Pin Pin Functions and Selection Method PB3/TP11/TIOCB4 ITU channel 4 settings (bit PWM4 in TMDR, bit CMD1 in TFCR, bit EB4 in TOER, and bits IOB2 to IOB0 in TIOR4), bit NDER11 in NDERB, and bit PB3DDR in PBDDR select the pin function as follows ITU channel 4 settings PB3DDR NDER11 Pin function 1 in table below — — TIOCB4 output 0 — PB3 input 2 in table below 1 0 PB3 output 1 1 TP11 output TIOCB4 input* Note: * TIOCB4 input when CMD1 = PWM4 = 0 and IOB2 = 1. ITU channel 4 settings EB4 CMD1 IOB2 IOB1 IOB0 2 0 — — — — 2 1 1 0 2 1 1 0 1 — 1 — — — — — 0 0 0 0 0 1 272 Table 9-16 Port B Pin Functions (cont) Pin Pin Functions and Selection Method PB2/TP10/TIOCA4 ITU channel 4 settings (bit CMD1 in TFCR, bit EA4 in TOER, bit PWM4 in TMDR, and bits IOA2 to IOA0 in TIOR4), bit NDER10 in NDERB, and bit PB2DDR in PBDDR select the pin function as follows ITU channel 4 settings PB2DDR NDER10 Pin function 1 in table below — — TIOCA4 output 0 — PB2 input 2 in table below 1 0 PB2 output 1 1 TP10 output TIOCA4 input* Note: * TIOCA4 input when CMD1 = PWM4 = 0 and IOA2 = 1. ITU channel 4 settings EA4 CMD1 PWM4 IOA2 IOA1 IOA0 2 0 — — — — — 2 1 1 0 0 2 1 1 1 — — — — 0 0 0 0 0 1 0 1 — 1 — — — — — 273 Table 9-16 Port B Pin Functions (cont) Pin PB1/TP9/TIOCB3 Pin Functions and Selection Method ITU channel 3 settings (bit PWM3 in TMDR, bit CMD1 in TFCR, bit EB3 in TOER, and bits IOB2 to IOB0 in TIOR3), bit NDER9 in NDERB, and bit PB1DDR in PBDDR select the pin function as follows ITU channel 3 settings PB1DDR NDER9 Pin function 1 in table below — — TIOCB3 output 0 — PB1 input 2 in table below 1 0 PB1 output 1 1 TP9 output TIOCB3 input* Note: * TIOCB3 input when CMD1 = PWM3 = 0 and IOB2 = 1. ITU channel 3 settings EB3 CMD1 IOB2 IOB1 IOB0 2 0 — — — — 2 1 1 0 2 1 1 0 1 — 1 — — — — — 0 0 0 0 0 1 274 Table 9-16 Port B Pin Functions (cont) Pin PB0/TP8/TIOCA3 Pin Functions and Selection Method ITU channel 3 settings (bit CMD1 in TFCR, bit EA3 in TOER, bit PWM3 in TMDR, and bits IOA2 to IOA0 in TIOR3), bit NDER8 in NDERB, and bit PB0DDR in PBDDR select the pin function as follows ITU channel 3 settings PB0DDR NDER8 Pin function 1 in table below — — TIOCA3 output 0 — PB0 input 2 in table below 1 0 PB0 output 1 1 TP8 output TIOCA3 input* Note: * TIOCA3 input when CMD1 = PWM3 = 0 and IOA2 = 1. ITU channel 3 settings EA3 CMD1 PWM3 IOA2 IOA1 IOA0 2 0 — — — — — 2 1 1 0 0 2 1 1 1 — — — — 0 0 0 0 0 1 0 1 — 1 — — — — — 275 9.10 Port C 9.10.1 Overview Port C is an 8-bit input/output port that is also used for DMAC input and output (DREQ3, DREQ2, TEND3, TEND2), CS7 to CS4 output, and IRQ7 and IRQ6 input. Port C has the same set of pin functions in all operating modes. Figure 9-13 shows the pin configuration of port C. Pins in port C can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor pair. Port C pins PC 7 (input/output)/IRQ 7 (input) PC 6 (input/output)/IRQ 6 (input) PC 5 (input)/DREQ 3 (input)/CS7 (output) Port C PC 4 (input)/TEND3 (output)/CS 6 (output) PC 3 (input)/DREQ 2 (input)/CS5 (output) PC 2 (input)/TEND2 (output)/CS 4 (output) PC 1 (input/output) PC 0 (input/output) Figure 9-13 Port C Pin Configuration 9.10.2 Register Descriptions Table 9-17 summarizes the registers of port C. Table 9-17 Port C Registers Address* H'FFD5 H'FFD7 Name Port C data direction register Port C data register Abbreviation PCDDR PCDR R/W W R/W Initial Value H'00 H'00 Note: * Lower 16 bits of the address. 276 Port C Data Direction Register (PCDDR): PCDDR is an 8-bit write-only register that can select input or output for each pin in port C. Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PC7 DDR PC6 DDR PC5 DDR PC4 DDR PC3 DDR PC2 DDR PC1 DDR PC0 DDR Port C data direction 7 to 0 These bits select input or output for port C pins When bits in PCDDR are set to 1, pins PC7, PC6, PC1, and PC0 become generic output pins and pins PC5 to PC2 become CS7 to CS4 output pins. When bits in PCDDR are cleared to 0, the corresponding pins become input pins. PCDDR is a write-only register. Its value cannot be read. All bits return 1 when read. PCDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting, so if a PCDDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. Port C Data Register (PCDR): PCDR is an 8-bit readable/writable register that stores data for pins PC7 to PC0. Bit Initial value Read/Write 7 PC 7 0 R/W 6 PC 6 0 R/W 5 PC 5 0 R/W 4 PC 4 0 R/W 3 PC 3 0 R/W 2 PC 2 0 R/W 1 PC 1 0 R/W 0 PC 0 0 R/W Port C data 7 to 0 These bits store data for port C pins When a bit in PCDDR is set to 1, if port C is read the value of the corresponding PCDR bit is returned directly. When a bit in PCDDR is cleared to 0, if port C is read the corresponding pin level is read. PCDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. 277 9.10.3 Pin Functions The port C pins are also used for DMA controller input and output (DREQ3, TEND3, DREQ2, TEND2), CS7 to CS4 output, and IRQ7 and IRQ6 input. Table 9-18 describes the selection of functions of pins PC7 to PC2. Table 9-18 Port C Pin Functions Pin PC7/IRQ7 Pin Functions and Selection Method Bit PC7DDR selects the pin function as follows PC7DDR Pin function 0 PC7 input IRQ7 input PC6/IRQ6 Bit PC6DDR selects the pin function as follows PC6DDR Pin function 0 PC6 input IRQ6 input PC5/DREQ3/CS7 DMAC channel 3 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR3A and DTCR3B) and bit PC5DDR in PCDDR select the pin function as follows PC5DDR Pin function 0 PC5 input DREQ3 input* Note: * DREQ3 input under DMAC channel 3 settings 1 in the table below. DMAC channel 3 settings DTS2A, DTS1A DTS0A DTS2B DTS1B 0 — 1 CS7 output 1 PC6 output 1 PC7 output 2 Not both 1 — 1 0 1 2 1 2 Both 1 1 0 1 1 0 — 0 1 — 1 0 — 1 1 0 1 1 1 278 Table 9-18 Port C Pin Functions (cont) Pin PC4/TEND3/CS6 Pin Functions and Selection Method DMAC channel 3 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR3A and DTCR3B) and bit PC4DDR in PCDDR select the pin function as follows DMAC channel 3 settings 1 in table below PC4DDR Pin function — TEND3 output 2 in table below 0 1 3 in table below — Not usable PC4 input CS6 output DMAC channel 3 settings DTS2A, DTS1A DTS0A DTS2B DTS1B PC3/DREQ2/CS5 0 — 2 Not both 1 — 1 0 1 2 3 1 2 Both 1 1 0 1 1 0 — 0 0 1 1 1 0 — 1 1 0 1 1 1 DMAC channel 2 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR2A and DTCR2B) and bit PC3DDR in PCDDR select the pin function as follows PC3DDR Pin function 0 PC3 input DREQ2 input* Note: * DREQ2 input under DMAC channel 2 settings 1 in the table below. DMAC channel 2 settings DTS2A, DTS1A DTS0A DTS2B DTS1B 0 — 1 CS5 output 2 Not both 1 — 1 0 1 2 1 2 Both 1 1 0 1 1 0 — 0 1 — 1 0 — 1 1 0 1 1 1 279 Table 9-18 Port C Pin Functions (cont) Pin PC2/TEND2/CS4 Pin Functions and Selection Method DMAC channel 2 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR2A and DTCR2B) and bit PC2DDR in PCDDR select the pin function as follows DMAC channel 2 settings PC2DDR Pin function 1 in table below — TEND2 output 2 in table below 0 PC2 input 1 CS4 output DMAC channel 2 settings DTS2A, DTS1A DTS0A DTS2B DTS1B 0 — 2 Not both 1 — 1 0 1 2 1 2 Both 1 1 0 1 1 0 — 0 1 — 1 0 — 1 1 0 1 1 1 280 Section 10 16-Bit Integrated Timer Unit (ITU) 10.1 Overview The H8/3003 has a built-in 16-bit integrated timer unit (ITU) with five 16-bit timer channels. 10.1.1 Features ITU features are listed below. • • Capability to process up to 12 pulse outputs or 10 pulse inputs Ten general registers (GRs, two per channel) with independently-assignable output compare or input capture functions Selection of eight counter clock sources for each channel: Internal clocks: ø, ø/2, ø/4, ø/8 External clocks: TCLKA, TCLKB, TCLKC, TCLKD • Five operating modes selectable in all channels: — Waveform output by compare match Selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2) — Input capture function Rising edge, falling edge, or both edges (selectable) — Counter clearing function Counters can be cleared by compare match or input capture — Synchronization Two or more timer counters (TCNTs) can be preset simultaneously, or cleared simultaneously by compare match or input capture. Counter synchronization enables synchronous register input and output. • 281 — PWM mode PWM output can be provided with an arbitrary duty cycle. With synchronization, up to five-phase PWM output is possible • Phase counting mode selectable in channel 2 Two-phase encoder output can be counted automatically. • Three additional modes selectable in channels 3 and 4 — Reset-synchronized PWM mode If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of complementary waveforms. — Complementary PWM mode If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of non-overlapping complementary waveforms. — Buffering Input capture registers can be double-buffered. Output compare registers can be updated automatically. • High-speed access via internal 16-bit bus The 16-bit timer counters, general registers, and buffer registers can be accessed at high speed via a 16-bit bus. • Fifteen interrupt sources Each channel has two compare match/input capture interrupts and an overflow interrupt. All interrupts can be requested independently. • Activation of DMA controller (DMAC) Four of the compare match/input capture interrupts from channels 0 to 3 can start the DMAC. • Output triggering of programmable pattern controller (TPC) Compare match/input capture signals from channels 0 to 3 can be used as TPC output triggers. 282 Table 10-1 summarizes the ITU functions. Table 10-1 ITU Functions Item Clock sources General registers (output compare/input capture registers) Buffer registers Input/output pins Output pins Counter clearing function Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Internal clocks: ø, ø/2, ø/4, ø/8 External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable independently GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 GRA3, GRB3 GRA4, GRB4 — TIOCA0, TIOCB0 — GRA0/GRB0 compare match or input capture — TIOCA1, TIOCB1 — GRA1/GRB1 compare match or input capture — TIOCA2, TIOCB2 — GRA2/GRB2 compare match or input capture BRA3, BRB3 TIOCA3, TIOCB3 — GRA3/GRB3 compare match or input capture BRA4, BRB4 TIOCA4, TIOCB4 TOCXA4, TOCXB4 GRA4/GRB4 compare match or input capture Compare match output 0 1 Toggle — Input capture function Synchronization PWM mode Reset-synchronized PWM mode Complementary PWM mode Phase counting mode Buffering DMAC activation — — — — — — — — — — — — — GRA0 compare GRA1 compare GRA2 compare GRA3 compare — match or match or match or match or input capture input capture input capture input capture Three sources • Compare match/input capture A0 • Compare match/input capture B0 • Overflow Three sources • Compare match/input capture A1 • Compare match/input capture B1 • Overflow Three sources • Compare match/input capture A2 • Compare match/input capture B2 • Overflow Three sources • Compare match/input capture A3 • Compare match/input capture B3 • Overflow Three sources • Compare match/input capture A4 • Compare match/input capture B4 • Overflow Interrupt sources Legend : Available —: Not available 283 10.1.2 Block Diagrams ITU Block Diagram (overall): Figure 10-1 is a block diagram of the ITU. TCLKA to TCLKD ø, ø/2, ø/4, ø/8 TOCXA4, TOCXB4 TIOCA0 to TIOCA4 TIOCB0 to TIOCB4 Clock selector Control logic IMIA0 to IMIA4 IMIB0 to IMIB4 OVI0 to OVI4 Counter control and pulse I/O control unit TODR 16-bit timer channel 4 16-bit timer channel 3 16-bit timer channel 2 16-bit timer channel 1 16-bit timer channel 0 TOCR TSTR TSNC TMDR TFCR On-chip data bus Bus interface Module data bus Legend TOER: TOCR: TSTR: TSNC: TMDR: TFCR: Timer output master enable register (8 bits) Timer output control register (8 bits) Timer start register (8 bits) Timer synchro register (8 bits) Timer mode register (8 bits) Timer function control register (8 bits) Figure 10-1 ITU Block Diagram (Overall) 284 Block Diagram of Channels 0 and 1: ITU channels 0 and 1 are functionally identical. Both have the structure shown in figure 10-2. TCLKA to TCLKD Clock selector ø, ø/2, ø/4, ø/8 Comparator Control logic TIOCA0 TIOCB0 IMIA0 IMIB0 OVI0 TCNT TIOR TIER GRA GRB TCR Module data bus Legend TCNT: GRA, GRB: TCR: TIOR: TIER: TSR: Timer counter (16 bits) General registers A and B (input capture/output compare registers) (16 bits × 2) Timer control register (8 bits) Timer I/O control register (8 bits) Timer interrupt enable register (8 bits) Timer status register (8 bits) Figure 10-2 Block Diagram of Channels 0 and 1 (for Channel 0) 285 TSR Block Diagram of Channel 2: Figure 10-3 is a block diagram of channel 2. This is the channel that provides only 0 output and 1 output. TCLKA to TCLKD Clock selector ø, ø/2, ø/4, ø/8 Comparator Control logic TIOCA2 TIOCB2 IMIA2 IMIB2 OVI2 TCNT2 TIOR2 TIER2 GRA2 GRB2 TCR2 Module data bus Legend Timer counter 2 (16 bits) TCNT2: GRA2, GRB2: General registers A2 and B2 (input capture/output compare registers) (16 bits × 2) Timer control register 2 (8 bits) TCR2: Timer I/O control register 2 (8 bits) TIOR2: Timer interrupt enable register 2 (8 bits) TIER2: Timer status register 2 (8 bits) TSR2: Figure 10-3 Block Diagram of Channel 2 286 TSR2 Block Diagrams of Channels 3 and 4: Figure 10-4 is a block diagram of channel 3. Figure 10-5 is a block diagram of channel 4. TCLKA to TCLKD ø, ø/2, ø/4, ø/8 Clock selector TIOCA3 TIOCB3 Comparator Control logic IMIA3 IMIB3 OVI3 TCNT3 TIOR3 TIER3 GRA3 GRB3 BRA3 BRB3 TCR3 Module data bus Legend Timer counter 3 (16 bits) TCNT3: GRA3, GRB3: General registers A3 and B3 (input capture/output compare registers) (16 bits × 2) BRA3, BRB3: Buffer registers A3 and B3 (input capture/output compare buffer registers) (16 bits × 2) Timer control register 3 (8 bits) TCR3: Timer I/O control register 3 (8 bits) TIOR3: Timer interrupt enable register 3 (8 bits) TIER3: Timer status register 3 (8 bits) TSR3: Figure 10-4 Block Diagram of Channel 3 287 TSR3 TCLKA to TCLKD ø, ø/2, ø/4, ø/8 Clock selector Comparator Control logic TOCXA4 TOCXB4 TIOCA4 TIOCB4 IMIA4 IMIB4 OVI4 TCNT4 TIOR4 TIER4 GRA4 GRB4 BRA4 BRB4 TCR4 Module data bus Legend Timer counter 4 (16 bits) TCNT4: GRA4, GRB4: General registers A4 and B4 (input capture/output compare registers) (16 bits × 2) BRA4, BRB4: Buffer registers A4 and B4 (input capture/output compare buffer registers) (16 bits × 2) Timer control register 4 (8 bits) TCR4: Timer I/O control register 4 (8 bits) TIOR4: Timer interrupt enable register 4 (8 bits) TIER4: Timer status register 4 (8 bits) TSR4: Figure 10-5 Block Diagram of Channel 4 288 TSR4 10.1.3 Input/Output Pins Table 10-2 summarizes the ITU pins. Table 10-2 ITU Pins Channel Name Abbreviation TCLKA TCLKB TCLKC TCLKD TIOCA0 TIOCB0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 Input/ Output Input Input Input Input Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Function External clock A input pin (phase-A input pin in phase counting mode) External clock B input pin (phase-B input pin in phase counting mode) External clock C input pin External clock D input pin GRA0 output compare or input capture pin PWM output pin in PWM mode GRB0 output compare or input capture pin GRA1 output compare or input capture pin PWM output pin in PWM mode GRB1 output compare or input capture pin GRA2 output compare or input capture pin PWM output pin in PWM mode GRB2 output compare or input capture pin GRA3 output compare or input capture pin PWM output pin in PWM mode, complementary PWM mode, or reset-synchronized PWM mode GRB3 output compare or input capture pin PWM output pin in complementary PWM mode or reset-synchronized PWM mode GRA4 output compare or input capture pin PWM output pin in PWM mode, complementary PWM mode, or reset-synchronized PWM mode GRB4 output compare or input capture pin PWM output pin in complementary PWM mode or reset-synchronized PWM mode PWM output pin in complementary PWM mode or reset-synchronized PWM mode PWM output pin in complementary PWM mode or reset-synchronized PWM mode Common Clock input A Clock input B Clock input C Clock input D 0 Input capture/output compare A0 Input capture/output compare B0 1 Input capture/output compare A1 Input capture/output compare B1 2 Input capture/output compare A2 Input capture/output compare B2 3 Input capture/output compare A3 Input capture/output compare B3 4 Input capture/output compare A4 TIOCB3 Input/ output Input/ output TIOCA4 Input capture/output compare B4 TIOCB4 Input/ output Output Output Output compare XA4 TOCXA4 Output compare XB4 TOCXB4 289 10.1.4 Register Configuration Table 10-3 summarizes the ITU registers. Table 10-3 ITU Registers Channel Common Address*1 H'FF60 H'FF61 H'FF62 H'FF63 H'FF90 H'FF91 0 H'FF64 H'FF65 H'FF66 H'FF67 H'FF68 H'FF69 H'FF6A H'FF6B H'FF6C H'FF6D 1 H'FF6E H'FF6F H'FF70 H'FF71 H'FF72 H'FF73 H'FF74 H'FF75 H'FF76 H'FF77 Name Timer start register Timer synchro register Timer mode register Timer function control register Timer output master enable register Timer output control register Timer control register 0 Timer I/O control register 0 Timer interrupt enable register 0 Timer status register 0 Timer counter 0 (high) Timer counter 0 (low) General register A0 (high) General register A0 (low) General register B0 (high) General register B0 (low) Timer control register 1 Timer I/O control register 1 Timer interrupt enable register 1 Timer status register 1 Timer counter 1 (high) Timer counter 1 (low) General register A1 (high) General register A1 (low) General register B1 (high) General register B1 (low) Abbreviation TSTR TSNC TMDR TFCR TOER TOCR TCR0 TIOR0 TIER0 TSR0 TCNT0H TCNT0L GRA0H GRA0L GRB0H GRB0L TCR1 TIOR1 TIER1 TSR1 TCNT1H TCNT1L GRA1H GRA1L GRB1H GRB1L R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/(W)*2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/(W)*2 R/W R/W R/W R/W R/W R/W Initial Value H'E0 H'E0 H'80 H'C0 H'FF H'FF H'80 H'88 H'F8 H'F8 H'00 H'00 H'FF H'FF H'FF H'FF H'80 H'88 H'F8 H'F8 H'00 H'00 H'FF H'FF H'FF H'FF Notes: 1. The lower 16 bits of the address are indicated. 2. Only 0 can be written, to clear flags. 290 Table 10-3 ITU Registers (cont) Channel 2 Address*1 H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF7F H'FF80 H'FF81 3 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF87 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF8F Name Timer control register 2 Timer I/O control register 2 Timer interrupt enable register 2 Timer status register 2 Timer counter 2 (high) Timer counter 2 (low) General register A2 (high) General register A2 (low) General register B2 (high) General register B2 (low) Timer control register 3 Timer I/O control register 3 Timer interrupt enable register 3 Timer status register 3 Timer counter 3 (high) Timer counter 3 (low) General register A3 (high) General register A3 (low) General register B3 (high) General register B3 (low) Buffer register A3 (high) Buffer register A3 (low) Buffer register B3 (high) Buffer register B3 (low) Abbreviation TCR2 TIOR2 TIER2 TSR2 TCNT2H TCNT2L GRA2H GRA2L GRB2H GRB2L TCR3 TIOR3 TIER3 TSR3 TCNT3H TCNT3L GRA3H GRA3L GRB3H GRB3L BRA3H BRA3L BRB3H BRB3L R/W R/W R/W R/W R/(W)*2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/(W)*2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'80 H'88 H'F8 H'F8 H'00 H'00 H'FF H'FF H'FF H'FF H'80 H'88 H'F8 H'F8 H'00 H'00 H'FF H'FF H'FF H'FF H'FF H'FF H'FF H'FF Notes: 1. The lower 16 bits of the address are indicated. 2. Only 0 can be written, to clear flags. 291 Table 10-3 ITU Registers (cont) Channel 4 Address*1 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FF9A H'FF9B H'FF9C H'FF9D H'FF9E H'FF9F Name Timer control register 4 Timer I/O control register 4 Timer interrupt enable register 4 Timer status register 4 Timer counter 4 (high) Timer counter 4 (low) General register A4 (high) General register A4 (low) General register B4 (high) General register B4 (low) Buffer register A4 (high) Buffer register A4 (low) Buffer register B4 (high) Buffer register B4 (low) Abbreviation TCR4 TIOR4 TIER4 TSR4 TCNT4H TCNT4L GRA4H GRA4L GRB4H GRB4L BRA4H BRA4L BRB4H BRB4L R/W R/W R/W R/W R/(W)*2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'80 H'88 H'F8 H'F8 H'00 H'00 H'FF H'FF H'FF H'FF H'FF H'FF H'FF H'FF Notes: 1. The lower 16 bits of the address are indicated. 2. Only 0 can be written, to clear flags. 292 10.2 Register Descriptions 10.2.1 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that starts and stops the timer counter (TCNT) in channels 0 to 4. Bit Initial value Read/Write 7 — 1 — 6 — 1 — Reserved bits 5 — 1 — 4 STR4 0 R/W 3 STR3 0 R/W 2 STR2 0 R/W 1 STR1 0 R/W 0 STR0 0 R/W Counter start 4 to 0 These bits start and stop TCNT4 to TCNT0 TSTR is initialized to H'E0 by a reset and in standby mode. Bits 7 to 5—Reserved: Read-only bits, always read as 1. Bit 4—Counter Start 4 (STR4): Starts and stops timer counter 4 (TCNT4). Bit 4 STR4 0 1 Description TCNT4 is halted TCNT4 is counting (Initial value) Bit 3—Counter Start 3 (STR3): Starts and stops timer counter 3 (TCNT3). Bit 3 STR3 0 1 Description TCNT3 is halted TCNT3 is counting (Initial value) Bit 2—Counter Start 2 (STR2): Starts and stops timer counter 2 (TCNT2). Bit 2 STR2 0 1 Description TCNT2 is halted TCNT2 is counting (Initial value) 293 Bit 1—Counter Start 1 (STR1): Starts and stops timer counter 1 (TCNT1). Bit 1 STR1 0 1 Description TCNT1 is halted TCNT1 is counting (Initial value) Bit 0—Counter Start 0 (STR0): Starts and stops timer counter 0 (TCNT0). Bit 0 STR0 0 1 Description TCNT0 is halted TCNT0 is counting (Initial value) 10.2.2 Timer Synchro Register (TSNC) TSNC is an 8-bit readable/writable register that selects whether channels 0 to 4 operate independently or synchronously. Channels are synchronized by setting the corresponding bits to 1. Bit Initial value Read/Write 7 — 1 — 6 — 1 — Reserved bits 5 — 1 — 4 SYNC4 0 R/W 3 SYNC3 0 R/W 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W Timer sync 4 to 0 These bits synchronize channels 4 to 0 TSNC is initialized to H'E0 by a reset and in standby mode. Bits 7 to 5—Reserved: Read-only bits, always read as 1. Bit 4—Timer Sync 4 (SYNC4): Selects whether channel 4 operates independently or synchronously. Bit 4 SYNC4 0 1 Description Channel 4’s timer counter (TCNT4) operates independently TCNT4 is preset and cleared independently of other channels Channel 4 operates synchronously TCNT4 can be synchronously preset and cleared (Initial value) 294 Bit 3—Timer Sync 3 (SYNC3): Selects whether channel 3 operates independently or synchronously. Bit 3 SYNC3 0 1 Description Channel 3’s timer counter (TCNT3) operates independently TCNT3 is preset and cleared independently of other channels Channel 3 operates synchronously TCNT3 can be synchronously preset and cleared (Initial value) Bit 2—Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or synchronously. Bit 2 SYNC2 0 1 Description Channel 2’s timer counter (TCNT2) operates independently TCNT2 is preset and cleared independently of other channels Channel 2 operates synchronously TCNT2 can be synchronously preset and cleared (Initial value) Bit 1—Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or synchronously. Bit 1 SYNC1 0 1 Description Channel 1’s timer counter (TCNT1) operates independently TCNT1 is preset and cleared independently of other channels Channel 1 operates synchronously TCNT1 can be synchronously preset and cleared (Initial value) Bit 0—Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or synchronously. Bit 0 SYNC0 0 1 Description Channel 0’s timer counter (TCNT0) operates independently TCNT0 is preset and cleared independently of other channels Channel 0 operates synchronously TCNT0 can be synchronously preset and cleared (Initial value) 295 10.2.3 Timer Mode Register (TMDR) TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 4. It also selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2. Bit Initial value Read/Write 7 — 1 — 6 MDF 0 R/W 5 FDIR 0 R/W 4 PWM4 0 R/W 3 PWM3 0 R/W 2 PWM2 0 R/W 1 PWM1 0 R/W 0 PWM0 0 R/W PWM mode 4 to 0 These bits select PWM mode for channels 4 to 0 Flag direction Selects the setting condition for the overflow flag (OVF) in timer status register 2 (TSR2) Phase counting mode flag Selects phase counting mode for channel 2 Reserved bit TMDR is initialized to H'80 by a reset and in standby mode. Bit 7—Reserved: Read-only bit, always read as 1. Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in phase counting mode. Bit 6 MDF 0 1 Description Channel 2 operates normally Channel 2 operates in phase counting mode (Initial value) 296 When MDF is set to 1 to select phase counting mode, timer counter 2 (TCNT2) operates as an up/down-counter and pins TCLKA and TCLKB become counter clock input pins. TCNT2 counts both rising and falling edges of TCLKA and TCLKB, and counts up or down as follows. Counting Direction TCLKA pin TCLKB pin Low Down-Counting High High Low High Up-Counting Low Low High In phase counting mode channel 2 operates as above regardless of the external clock edges selected by bits CKEG1 and CKEG0 and the clock source selected by bits TPSC2 to TPSC0 in timer control register 2 (TCR2). Phase counting mode takes precedence over these settings. The counter clearing condition selected by the CCLR1 and CCLR0 bits in TCR2 and the compare match/input capture settings and interrupt functions of timer I/O control register 2 (TIOR2), timer interrupt enable register 2 (TIER2), and timer status register 2 (TSR2) remain effective in phase counting mode. Bit 5—Flag Direction (FDIR): Designates the setting condition for the overflow flag (OVF) in timer status register 2 (TSR2). The FDIR designation is valid in all modes in channel 2. Bit 5 FDIR 0 1 Description OVF is set to 1 in TSR2 when TCNT2 overflows or underflows OVF is set to 1 in TSR2 when TCNT2 overflows (Initial value) Bit 4—PWM Mode 4 (PWM4): Selects whether channel 4 operates normally or in PWM mode. Bit 4 PWM4 0 1 Description Channel 4 operates normally Channel 4 operates in PWM mode (Initial value) When bit PWM4 is set to 1 to select PWM mode, pin TIOCA4 becomes a PWM output pin. The output goes to 1 at compare match with general register A4 (GRA4), and to 0 at compare match with general register B4 (GRB4). If complementary PWM mode or reset-synchronized PWM mode is selected by bits CMD1 and CMD0 in the timer function control register (TFCR), the CMD1 and CMD0 setting takes precedence and the PWM4 setting is ignored. 297 Bit 3—PWM Mode 3 (PWM3): Selects whether channel 3 operates normally or in PWM mode. Bit 3 PWM3 0 1 Description Channel 3 operates normally Channel 3 operates in PWM mode (Initial value) When bit PWM3 is set to 1 to select PWM mode, pin TIOCA3 becomes a PWM output pin. The output goes to 1 at compare match with general register A3 (GRA3), and to 0 at compare match with general register B3 (GRB3). If complementary PWM mode or reset-synchronized PWM mode is selected by bits CMD1 and CMD0 in the timer function control register (TFCR), the CMD1 and CMD0 setting takes precedence and the PWM3 setting is ignored. Bit 2—PWM Mode 2 (PWM2): Selects whether channel 2 operates normally or in PWM mode. Bit 2 PWM2 0 1 Description Channel 2 operates normally Channel 2 operates in PWM mode (Initial value) When bit PWM2 is set to 1 to select PWM mode, pin TIOCA2 becomes a PWM output pin. The output goes to 1 at compare match with general register A2 (GRA2), and to 0 at compare match with general register B2 (GRB2). Bit 1—PWM Mode 1 (PWM1): Selects whether channel 1 operates normally or in PWM mode. Bit 1 PWM1 0 1 Description Channel 1 operates normally Channel 1 operates in PWM mode (Initial value) When bit PWM1 is set to 1 to select PWM mode, pin TIOCA1 becomes a PWM output pin. The output goes to 1 at compare match with general register A1 (GRA1), and to 0 at compare match with general register B1 (GRB1). 298 Bit 0—PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode. Bit 0 PWM0 0 1 Description Channel 0 operates normally Channel 0 operates in PWM mode (Initial value) When bit PWM0 is set to 1 to select PWM mode, pin TIOCA0 becomes a PWM output pin. The output goes to 1 at compare match with general register A0 (GRA0), and to 0 at compare match with general register B0 (GRB0). 10.2.4 Timer Function Control Register (TFCR) TFCR is an 8-bit readable/writable register that selects complementary PWM mode, resetsynchronized PWM mode, and buffering for channels 3 and 4. Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 CMD1 0 R/W 4 CMD0 0 R/W 3 BFB4 0 R/W 2 BFA4 0 R/W 1 BFB3 0 R/W 0 BFA3 0 R/W Reserved bits Combination mode 1/0 These bits select complementary PWM mode or reset-synchronized PWM mode for channels 3 and 4 Buffer mode B4 and A4 These bits select buffering of general registers (GRB4 and GRA4) by buffer registers (BRB4 and BRA4) in channel 4 Buffer mode B3 and A3 These bits select buffering of general registers (GRB3 and GRA3) by buffer registers (BRB3 and BRA3) in channel 3 TFCR is initialized to H'C0 by a reset and in standby mode. Bits 7 and 6—Reserved: Read-only bits, always read as 1. 299 Bits 5 and 4—Combination Mode 1 and 0 (CMD1, CMD0): These bits select whether channels 3 and 4 operate in normal mode, complementary PWM mode, or reset-synchronized PWM mode. Bit 5 CMD1 0 Bit 4 CMD0 0 1 1 0 1 Channels 3 and 4 operate together in complementary PWM mode Channels 3 and 4 operate together in reset-synchronized PWM mode Description Channels 3 and 4 operate normally (Initial value) Before selecting reset-synchronized PWM mode or complementary PWM mode, halt the timer counter or counters that will be used in these modes. When these bits select complementary PWM mode or reset-synchronized PWM mode, they take precedence over the setting of the PWM mode bits (PWM4 and PWM3) in TMDR. Settings of timer sync bits SYNC4 and SYNC3 in the timer synchro register (TSNC) are valid in complementary PWM mode and reset-synchronized PWM mode, however. When complementary PWM mode is selected, channels 3 and 4 must not be synchronized (do not set bits SYNC3 and SYNC4 both to 1 in TSNC). Bit 3—Buffer Mode B4 (BFB4): Selects whether GRB4 operates normally in channel 4, or whether GRB4 is buffered by BRB4. Bit 3 BFB4 0 1 Description GRB4 operates normally GRB4 is buffered by BRB4 (Initial value) Bit 2—Buffer Mode A4 (BFA4): Selects whether GRA4 operates normally in channel 4, or whether GRA4 is buffered by BRA4. Bit 2 BFA4 0 1 Description GRA4 operates normally GRA4 is buffered by BRA4 (Initial value) 300 Bit 1—Buffer Mode B3 (BFB3): Selects whether GRB3 operates normally in channel 3, or whether GRB3 is buffered by BRB3. Bit 1 BFB3 0 1 Description GRB3 operates normally GRB3 is buffered by BRB3 (Initial value) Bit 0—Buffer Mode A3 (BFA3): Selects whether GRA3 operates normally in channel 3, or whether GRA3 is buffered by BRA3. Bit 0 BFA3 0 1 Description GRA3 operates normally GRA3 is buffered by BRA3 (Initial value) 10.2.5 Timer Output Master Enable Register (TOER) TOER is an 8-bit readable/writable register that enables or disables output settings for channels 3 and 4. Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 EXB4 1 R/W 4 EXA4 1 R/W 3 EB3 1 R/W 2 EB4 1 R/W 1 EA4 1 R/W 0 EA3 1 R/W Reserved bits Master enable TOCXA4, TOCXB4 These bits enable or disable output settings for pins TOCXA4 and TOCXB4 Master enable TIOCA3, TIOCB3 , TIOCA4, TIOCB4 These bits enable or disable output settings for pins TIOCA3, TIOCB3 , TIOCA4, and TIOCB4 TOER is initialized to H'FF by a reset and in standby mode. Bits 7 and 6—Reserved: Read-only bits, always read as 1. 301 Bit 5—Master Enable TOCXB4 (EXB4): Enables or disables ITU output at pin TOCXB4. Bit 5 EXB4 0 Description TOCXB4 output is disabled regardless of TFCR settings (TOCXB4 operates as a generic input/output pin). If XTGD = 0, EXB4 is cleared to 0 when input capture A occurs in channel 1. TOCXB4 is enabled for output according to TFCR settings (Initial value) 1 Bit 4—Master Enable TOCXA4 (EXA4): Enables or disables ITU output at pin TOCXA4. Bit 4 EXA4 0 Description TOCXA4 output is disabled regardless of TFCR settings (TOCXA4 operates as a generic input/output pin). If XTGD = 0, EXA4 is cleared to 0 when input capture A occurs in channel 1. TOCXA4 is enabled for output according to TFCR settings (Initial value) 1 Bit 3—Master Enable TIOCB3 (EB3): Enables or disables ITU output at pin TIOCB3. Bit 3 EB3 0 Description TIOCB3 output is disabled regardless of TIOR3 and TFCR settings (TIOCB3 operates as a generic input/output pin). If XTGD = 0, EB3 is cleared to 0 when input capture A occurs in channel 1. TIOCB3 is enabled for output according to TIOR3 and TFCR settings (Initial value) 1 302 Bit 2—Master Enable TIOCB4 (EB4): Enables or disables ITU output at pin TIOCB4. Bit 2 EB4 0 Description TIOCB4 output is disabled regardless of TIOR4 and TFCR settings (TIOCB4 operates as a generic input/output pin). If XTGD = 0, EB4 is cleared to 0 when input capture A occurs in channel 1. TIOCB4 is enabled for output according to TIOR4 and TFCR settings (Initial value) 1 Bit 1—Master Enable TIOCA4 (EA4): Enables or disables ITU output at pin TIOCA4. Bit 1 EA4 0 Description TIOCA4 output is disabled regardless of TIOR4, TMDR, and TFCR settings (TIOCA4 operates as a generic input/output pin). If XTGD = 0, EA4 is cleared to 0 when input capture A occurs in channel 1. TIOCA4 is enabled for output according to TIOR4, TMDR, and TFCR settings (Initial value) 1 Bit 0—Master Enable TIOCA3 (EA3): Enables or disables ITU output at pin TIOCA3. Bit 0 EA3 0 Description TIOCA3 output is disabled regardless of TIOR3, TMDR, and TFCR settings (TIOCA3 operates as a generic input/output pin). If XTGD = 0, EA3 is cleared to 0 when input capture A occurs in channel 1. TIOCA3 is enabled for output according to TIOR3, TMDR, and TFCR settings (Initial value) 1 303 10.2.6 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that selects externally triggered disabling of output in complementary PWM mode and reset-synchronized PWM mode, and inverts the output levels. Bit Initial value Read/Write 7 — 1 — 6 — 1 — Reserved bits 5 — 1 — 4 XTGD 1 R/W 3 — 1 — 2 — 1 — 1 OLS4 1 R/W 0 OLS3 1 R/W Output level select 3, 4 These bits select output levels in complementary PWM mode and resetsynchronized PWM mode Reserved bits External trigger disable Selects externally triggered disabling of output in complementary PWM mode and reset-synchronized PWM mode The settings of the XTGD, OLS4, and OLS3 bits are valid only in complementary PWM mode and reset-synchronized PWM mode. These settings do not affect other modes. TOCR is initialized to H'FF by a reset and in standby mode. Bits 7 to 5—Reserved: Read-only bits, always read as 1. Bit 4—External Trigger Disable (XTGD): Selects externally triggered disabling of ITU output in complementary PWM mode and reset-synchronized PWM mode. Bit 4 XTGD 0 Description Input capture A in channel 1 is used as an external trigger signal in complementary PWM mode and reset-synchronized PWM mode. When an external trigger occurs, bits 5 to 0 in the timer output master enable register (TOER) are cleared to 0, disabling ITU output. External triggering is disabled (Initial value) 1 304 Bits 3 and 2—Reserved: Read-only bits, always read as 1. Bit 1—Output Level Select 4 (OLS4): Selects output levels in complementary PWM mode and reset-synchronized PWM mode. Bit 1 OLS4 0 1 Description TIOCA3, TIOCA4, and TIOCB4 outputs are inverted TIOCA3, TIOCA4, and TIOCB4 outputs are not inverted (Initial value) Bit 0—Output Level Select 3 (OLS3): Selects output levels in complementary PWM mode and reset-synchronized PWM mode. Bit 0 OLS3 0 1 Description TIOCB3, TOCXA4, and TOCXB4 outputs are inverted TIOCB3, TOCXA4, and TOCXB4 outputs are not inverted (Initial value) 10.2.7 Timer Counters (TCNT) TCNT is a 16-bit counter. The ITU has five TCNTs, one for each channel. Channel 0 1 2 3 4 Abbreviation TCNT0 TCNT1 TCNT2 TCNT3 TCNT4 Phase counting mode: up/down-counter Other modes: up-counter Complementary PWM mode: up/down-counter Other modes: up-counter Function Up-counter Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Each TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock source. The clock source is selected by bits TPSC2 to TPSC0 in the timer control register (TCR). 305 TCNT0 and TCNT1 are up-counters. TCNT2 is an up/down-counter in phase counting mode and an up-counter in other modes. TCNT3 and TCNT4 are up/down-counters in complementary PWM mode and up-counters in other modes. TCNT can be cleared to H'0000 by compare match with general register A or B (GRA or GRB) or by input capture to GRA or GRB (counter clearing function) in the same channel. When TCNT overflows (changes from H'FFFF to H'0000), the overflow flag (OVF) is set to 1 in the timer status register (TSR) of the corresponding channel. When TCNT underflows (changes from H'0000 to H'FFFF), the overflow flag (OVF) is set to 1 in TSR of the corresponding channel. The TCNTs are linked to the CPU by an internal 16-bit bus and can be written or read by either word access or byte access. Each TCNT is initialized to H'0000 by a reset and in standby mode. 10.2.8 General Registers (GRA, GRB) The general registers are 16-bit registers. The ITU has 10 general registers, two in each channel. Channel 0 1 2 3 4 Abbreviation GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 GRA3, GRB3 GRA4, GRB4 Output compare/input capture register; can be buffered by buffer registers BRA and BRB Function Output compare/input capture register Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W A general register is a 16-bit readable/writable register that can function as either an output compare register or an input capture register. The function is selected by settings in the timer I/O control register (TIOR). When a general register is used as an output compare register, its value is constantly compared with the TCNT value. When the two values match (compare match), the IMFA or IMFB flag is set to 1 in the timer status register (TSR). Compare match output can be selected in TIOR. 306 When a general register is used as an input capture register, rising edges, falling edges, or both edges of an external input capture signal are detected and the current TCNT value is stored in the general register. The corresponding IMFA or IMFB flag in TSR is set to 1 at the same time. The valid edge or edges of the input capture signal are selected in TIOR. TIOR settings are ignored in PWM mode, complementary PWM mode, and reset-synchronized PWM mode. General registers are linked to the CPU by an internal 16-bit bus and can be written or read by either word access or byte access. General registers are initialized to the output compare function (with no output signal) by a reset and in standby mode. The initial value is H'FFFF. 10.2.9 Buffer Registers (BRA, BRB) The buffer registers are 16-bit registers. The ITU has four buffer registers, two each in channels 3 and 4. Channel 3 4 Abbreviation BRA3, BRB3 BRA4, BRB4 Function Used for buffering • When the corresponding GRA or GRB functions as an output compare register, BRA or BRB can function as an output compare buffer register: the BRA or BRB value is automatically transferred to GRA or GRB at compare match • When the corresponding GRA or GRB functions as an input capture register, BRA or BRB can function as an input capture buffer register: the GRA or GRB value is automatically transferred to BRA or BRB at input capture Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W A buffer register is a 16-bit readable/writable register that is used when buffering is selected. Buffering can be selected independently by bits BFB4, BFA4, BFB3, and BFA3 in TFCR. The buffer register and general register operate as a pair. When the general register functions as an output compare register, the buffer register functions as an output compare buffer register. When the general register functions as an input capture register, the buffer register functions as an input capture buffer register. 307 The buffer registers are linked to the CPU by an internal 16-bit bus and can be written or read by either word or byte access. Buffer registers are initialized to H'FFFF by a reset and in standby mode. 10.2.10 Timer Control Registers (TCR) TCR is an 8-bit register. The ITU has five TCRs, one in each channel. Channel 0 1 2 3 4 Abbreviation TCR0 TCR1 TCR2 TCR3 TCR4 Function TCR controls the timer counter. The TCRs in all channels are functionally identical. When phase counting mode is selected in channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2 to TPSC0 in TCR2 are ignored. Bit Initial value Read/Write 7 — 1 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W CKEG1 CKEG0 Timer prescaler 2 to 0 These bits select the counter clock Clock edge 1/0 These bits select external clock edges Counter clear 1/0 These bits select the counter clear source Reserved bit Each TCR is an 8-bit readable/writable register that selects the timer counter clock source, selects the edge or edges of external clock sources, and selects how the counter is cleared. TCR is initialized to H'80 by a reset and in standby mode. Bit 7—Reserved: Read-only bit, always read as 1. 308 Bits 6 and 5—Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared. Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT is not cleared TCNT is cleared by GRA compare match or input capture*1 (Initial value) TCNT is cleared by GRB compare match or input capture*1 Synchronous clear: TCNT is cleared in synchronization with other synchronized timers*2 Notes: 1. TCNT is cleared by compare match when the general register functions as a compare match register, and by input capture when the general register functions as an input capture register. 2. Selected in the timer synchro register (TSNC). Bits 4 and 3—Clock Edge 1/0 (CKEG1, CKEG0): These bits select external clock input edges when an external clock source is used. Bit 4 CKEG1 0 Bit 3 CKEG0 0 1 1 — Description Count rising edges Count falling edges Count both edges (Initial value) When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in TCR2 are ignored. Phase counting takes precedence. 309 Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock source. Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Function Internal clock: ø Internal clock: ø/2 Internal clock: ø/4 Internal clock: ø/8 External clock A: TCLKA input External clock B: TCLKB input External clock C: TCLKC input External clock D: TCLKD input (Initial value) When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer counts the edge or edges selected by bits CKEG1 and CKEG0. When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2 to TPSC0 in TCR2 are ignored. Phase counting takes precedence. 10.2.11 Timer I/O Control Register (TIOR) TIOR is an 8-bit register. The ITU has five TIORs, one in each channel. Channel 0 1 2 3 4 Abbreviation TIOR0 TIOR1 TIOR2 TIOR3 TIOR4 Function TIOR controls the general registers. Some functions differ in PWM mode. TIOR3 and TIOR4 settings are ignored when complementary PWM mode or reset-synchronized PWM mode is selected in channels 3 and 4. 310 Bit Initial value Read/Write 7 — 1 — 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 — 1 — 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W I/O control A2 to A0 These bits select GRA functions Reserved bit I/O control B2 to B0 These bits select GRB functions Reserved bit Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture function for GRA and GRB, and specifies the functions of the TIOCA and TIOCB pins. If the output compare function is selected, TIOR also selects the type of output. If input capture is selected, TIOR also selects the edge or edges of the input capture signal. TIOR is initialized to H'88 by a reset and in standby mode. Bit 7—Reserved: Read-only bit, always read as 1. Bits 6 to 4—I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function. Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 Notes: 1. After a reset, the output is 0 until the first compare match. 2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output instead. GRB is an input capture register Function GRB is an output compare register No output at compare match 0 output at GRB compare (Initial value) match*1 1 output at GRB compare match*1 Output toggles at GRB compare match (1 output in channel 2)*1, *2 GRB captures rising edge of input GRB captures falling edge of input GRB captures both edges of input 311 Bit 3—Reserved: Read-only bit, always read as 1. Bits 2 to 0—I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function. Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 Notes: 1. After a reset, the output is 0 until the first compare match. 2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output instead. GRA is an input capture register Function GRA is an output compare register No output at compare match (Initial value) 0 output at GRA compare match*1 1 output at GRA compare match*1 Output toggles at GRA compare match (1 output in channel 2)*1, *2 GRA captures rising edge of input GRA captures falling edge of input GRA captures both edges of input 10.2.12 Timer Status Register (TSR) TSR is an 8-bit register. The ITU has five TSRs, one in each channel. Channel 0 1 2 3 4 Abbreviation TSR0 TSR1 TSR2 TSR3 TSR4 Function Indicates input capture, compare match, and overflow status 312 Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — Reserved bits 4 — 1 — 3 — 1 — 2 OVF 0 R/(W)* 1 IMFB 0 R/(W)* 0 IMFA 0 R/(W)* Overflow flag Status flag indicating overflow or underflow Input capture/compare match flag B Status flag indicating GRB compare match or input capture Input capture/compare match flag A Status flag indicating GRA compare match or input capture Note: * Only 0 can be written, to clear the flag. Each TSR is an 8-bit readable/writable register containing flags that indicate TCNT overflow or underflow and GRA or GRB compare match or input capture. These flags are interrupt sources and generate CPU interrupts if enabled by corresponding bits in the timer interrupt enable register (TIER). TSR is initialized to H'F8 by a reset and in standby mode. Bits 7 to 3—Reserved: Read-only bits, always read as 1. Bit 2—Overflow Flag (OVF): This status flag indicates TCNT overflow or underflow. Bit 2 OVF 0 1 Description [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF (Initial value) [Setting condition] TCNT overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF* Notes: * TCNT underflow occurs when TCNT operates as an up/down-counter. Underflow occurs only under the following conditions: 1. Channel 2 operates in phase counting mode (MDF = 1 in TMDR) 2. Channels 3 and 4 operate in complementary PWM mode (CMD1 = 1 and CMD0 = 0 in TFCR) 313 Bit 1—Input Capture/Compare Match Flag B (IMFB): This status flag indicates GRB compare match or input capture events. Bit 1 IMFB 0 1 Description [Clearing condition] Read IMFB when IMFB = 1, then write 0 in IMFB (Initial value) [Setting conditions] TCNT = GRB when GRB functions as a compare match register. TCNT value is transferred to GRB by an input capture signal, when GRB functions as an input capture register. Bit 0—Input Capture/Compare Match Flag A (IMFA): This status flag indicates GRA compare match or input capture events. Bit 0 IMFA 0 Description [Clearing condition] Read IMFA when IMFA = 1, then write 0 in IMFA. DMAC activated by IMIA interrupt (channels 0 to 3 only). (Initial value) 1 [Setting conditions] TCNT = GRA when GRA functions as a compare match register. TCNT value is transferred to GRA by an input capture signal, when GRA functions as an input capture register. 314 10.2.13 Timer Interrupt Enable Register (TIER) TIER is an 8-bit register. The ITU has five TIERs, one in each channel. Channel 0 1 2 3 4 Abbreviation TIER0 TIER1 TIER2 TIER3 TIER4 Function Enables or disables interrupt requests. Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — Reserved bits 4 — 1 — 3 — 1 — 2 OVIE 0 R/W 1 IMIEB 0 R/W 0 IMIEA 0 R/W Overflow interrupt enable Enables or disables OVF interrupts Input capture/compare match interrupt enable B Enables or disables IMFB interrupts Input capture/compare match interrupt enable A Enables or disables IMFA interrupts Each TIER is an 8-bit readable/writable register that enables and disables overflow interrupt requests and general register compare match and input capture interrupt requests. TIER is initialized to H'F8 by a reset and in standby mode. Bits 7 to 3—Reserved: Read-only bits, always read as 1. 315 Bit 2—Overflow Interrupt Enable (OVIE): Enables or disables the interrupt requested by the overflow flag (OVF) in TSR when OVF is set to 1. Bit 2 OVIE 0 1 Description OVI interrupt requested by OVF is disabled OVI interrupt requested by OVF is enabled (Initial value) Bit 1—Input Capture/Compare Match Interrupt Enable B (IMIEB): Enables or disables the interrupt requested by the IMFB flag in TSR when IMFB is set to 1. Bit 1 IMIEB 0 1 Description IMIB interrupt requested by IMFB is disabled IMIB interrupt requested by IMFB is enabled (Initial value) Bit 0—Input Capture/Compare Match Interrupt Enable A (IMIEA): Enables or disables the interrupt requested by the IMFA flag in TSR when IMFA is set to 1. Bit 0 IMIEA 0 1 Description IMIA interrupt requested by IMFA is disabled IMIA interrupt requested by IMFA is enabled (Initial value) 316 10.3 CPU Interface 10.3.1 16-Bit Accessible Registers The timer counters (TCNTs), general registers A and B (GRAs and GRBs), and buffer registers A and B (BRAs and BRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data bus. These registers can be written or read a word at a time, or a byte at a time. Figures 10-6 and 10-7 show examples of word access to a timer counter (TCNT). Figures 10-8, 10-9, 10-10, and 10-11 show examples of byte access to TCNTH and TCNTL. On-chip data bus H CPU L Bus interface H L Module data bus TCNTH TCNTL Figure 10-6 Access to Timer Counter (CPU Writes to TCNT, Word) On-chip data bus H CPU L Bus interface H L Module data bus TCNTH TCNTL Figure 10-7 Access to Timer Counter (CPU Reads TCNT, Word) 317 On-chip data bus H CPU L Bus interface H L Module data bus TCNTH TCNTL Figure 10-8 Access to Timer Counter (CPU Writes to TCNT, Upper Byte) On-chip data bus H CPU L Bus interface H L Module data bus TCNTH TCNTL Figure 10-9 Access to Timer Counter (CPU Writes to TCNT, Lower Byte) On-chip data bus H CPU L Bus interface H L Module data bus TCNTH TCNTL Figure 10-10 Access to Timer Counter (CPU Reads TCNT, Upper Byte) 318 On-chip data bus H CPU L Bus interface H L Module data bus TCNTH TCNTL Figure 10-11 Access to Timer Counter (CPU Reads TCNT, Lower Byte) 10.3.2 8-Bit Accessible Registers The registers other than the timer counters, general registers, and buffer registers are 8-bit registers. These registers are linked to the CPU by an internal 8-bit data bus. Figures 10-12 and 10-13 show examples of byte read and write access to a TCR. If a word-size data transfer instruction is executed, two byte transfers are performed. On-chip data bus H CPU L Bus interface H L Module data bus TCR Figure 10-12 TCR Access (CPU Writes to TCR) 319 On-chip data bus H CPU L Bus interface H L Module data bus TCR Figure 10-13 TCR Access (CPU Reads TCR) 320 10.4 Operation 10.4.1 Overview A summary of operations in the various modes is given below. Normal Operation: Each channel has a timer counter and general registers. The timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter. General registers A and B can be used for input capture or output compare. Synchronous Operation: The timer counters in designated channels are preset synchronously. Data written to the timer counter in any one of these channels is simultaneously written to the timer counters in the other channels as well. The timer counters can also be cleared synchronously if so designated by the CCLR1 and CCLR0 bits in the TCRs. PWM Mode: A PWM waveform is output from the TIOCA pin. The output goes to 1 at compare match A and to 0 at compare match B. The duty cycle can be varied from 0% to 100% depending on the settings of GRA and GRB. When a channel is set to PWM mode, its GRA and GRB automatically become output compare registers. Reset-Synchronized PWM Mode: Channels 3 and 4 are paired for three-phase PWM output with complementary waveforms. (The three phases are related by having a common transition point.) When reset-synchronized PWM mode is selected GRA3, GRB3, GRA4, and GRB4 automatically function as output compare registers, TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 function as PWM output pins, and TCNT3 operates as an up-counter. TCNT4 operates independently, and is not compared with GRA4 or GRB4. Complementary PWM Mode: Channels 3 and 4 are paired for three-phase PWM output with non-overlapping complementary waveforms. When complementary PWM mode is selected GRA3, GRB3, GRA4, and GRB4 automatically function as output compare registers, and TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 function as PWM output pins. TCNT3 and TCNT4 operate as up/down-counters. Phase Counting Mode: The phase relationship between two clock signals input at TCLKA and TCLKB is detected and TCNT2 counts up or down accordingly. When phase counting mode is selected TCLKA and TCLKB become clock input pins and TCNT2 operates as an up/downcounter. 321 Buffering • If the general register is an output compare register When compare match occurs the buffer register value is transferred to the general register. • If the general register is an input capture register When input capture occurs the TCNT value is transferred to the general register, and the previous general register value is transferred to the buffer register. • Complementary PWM mode The buffer register value is transferred to the general register when TCNT3 and TCNT4 change counting direction. • Reset-synchronized PWM mode The buffer register value is transferred to the general register at GRA3 compare match. 10.4.2 Basic Functions Counter Operation: When one of bits STR0 to STR4 is set to 1 in the timer start register (TSTR), the timer counter (TCNT) in the corresponding channel starts counting. The counting can be free-running or periodic. • Sample setup procedure for counter Figure 10-14 shows a sample procedure for setting up a counter. 322 Counter setup Select counter clock 1 Type of counting? Free-running counting Periodic counting Select counter clear source 2 Select output compare register function 3 Set period 4 Start counter Periodic counter 5 Start counter Free-running counter 5 Figure 10-14 Counter Setup Procedure (Example) 1. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge(s) of the external clock signal. For periodic counting, set CCLR1 and CCLR0 in TCR to have TCNT cleared at GRA compare match or GRB compare match. Set TIOR to select the output compare function of GRA or GRB, whichever was selected in step 2. Write the count period in GRA or GRB, whichever was selected in step 2. Set the STR bit to 1 in TSTR to start the timer counter. 2. 3. 4. 5. 323 • Free-running and periodic counter operation A reset leaves the counters (TCNTs) in ITU channels 0 to 4 all set as free-running counters. A free-running counter starts counting up when the corresponding bit in TSTR is set to 1. When the count overflows from H'FFFF to H'0000, the overflow flag (OVF) is set to 1 in the timer status register (TSR). If the corresponding OVIE bit is set to 1 in the timer interrupt enable register, a CPU interrupt is requested. After the overflow, the counter continues counting up from H'0000. Figure 10-15 illustrates free-running counting. TCNT value H'FFFF H'0000 STR0 to STR4 bit OVF Time Figure 10-15 Free-Running Counter Operation When a channel is set to have its counter cleared by compare match, in that channel TCNT operates as a periodic counter. Select the output compare function of GRA or GRB, set bit CCLR1 or CCLR0 in the timer control register (TCR) to have the counter cleared by compare match, and set the count period in GRA or GRB. After these settings, the counter starts counting up as a periodic counter when the corresponding bit is set to 1 in TSTR. When the count matches GRA or GRB, the IMFA or IMFB flag is set to 1 in TSR and the counter is cleared to H'0000. If the corresponding IMIEA or IMIEB bit is set to 1 in TIER, a CPU interrupt is requested at this time. After the compare match, TCNT continues counting up from H'0000. Figure 10-16 illustrates periodic counting. 324 TCNT value GR Counter cleared by general register compare match H'0000 STR bit IMF Time Figure 10-16 Periodic Counter Operation • Count timing — Internal clock source Bits TPSC2 to TPSC0 in TCR select the system clock (ø) or one of three internal clock sources obtained by prescaling the system clock (ø/2, ø/4, ø/8). Figure 10-17 shows the timing. ø Internal clock TCNT input TCNT N–1 N N+1 Figure 10-17 Count Timing for Internal Clock Sources 325 — External clock source Bits TPSC2 to TPSC0 in TCR select an external clock input pin (TCLKA to TCLKD), and its valid edge or edges are selected by bits CKEG1 and CKEG0. The rising edge, falling edge, or both edges can be selected. The pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected. Shorter pulses will not be counted correctly. Figure 10-18 shows the timing when both edges are detected. ø External clock input TCNT input TCNT N–1 N N+1 Figure 10-18 Count Timing for External Clock Sources (when Both Edges are Detected) 326 Waveform Output by Compare Match: In ITU channels 0, 1, 3, and 4, compare match A or B can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the output can only go to 0 or go to 1. • Sample setup procedure for waveform output by compare match Figure 10-19 shows a sample procedure for setting up waveform output by compare match. Output setup Select waveform output mode 1 1. Select the compare match output mode (0, 1, or toggle) in TIOR. When a waveform output mode is selected, the pin switches from its generic input/ output function to the output compare function (TIOCA or TIOCB). An output compare pin outputs 0 until the first compare match occurs. Set output timing 2 2. Set a value in GRA or GRB to designate the compare match timing. Start counter 3 3. Set the STR bit to 1 in TSTR to start the timer counter. Waveform output Figure 10-19 Setup Procedure for Waveform Output by Compare Match (Example) • Examples of waveform output Figure 10-20 shows examples of 0 and 1 output. TCNT operates as a free-running counter, 0 output is selected for compare match A, and 1 output is selected for compare match B. When the pin is already at the selected output level, the pin level does not change. 327 TCNT value H'FFFF GRB GRA Time TIOCB No change No change 1 output TIOCA No change No change 0 output Figure 10-20 0 and 1 Output (Examples) Figure 10-21 shows examples of toggle output. TCNT operates as a periodic counter, cleared by compare match B. Toggle output is selected for both compare match A and B. TCNT value GRB Counter cleared by compare match with GRB GRA Time TIOCB Toggle output Toggle output TIOCA Figure 10-21 Toggle Output (Example) 328 • Output compare timing The compare match signal is generated in the last state in which TCNT and the general register match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the output compare pin (TIOCA or TIOCB). When TCNT matches a general register, the compare match signal is not generated until the next counter clock pulse. Figure 10-22 shows the output compare timing. ø TCNT input clock TCNT N N+1 GR Compare match signal TIOCA, TIOCB N Figure 10-22 Output Compare Timing Input Capture Function: The TCNT value can be captured into a general register when a transition occurs at an input capture/output compare pin (TIOCA or TIOCB). Capture can take place on the rising edge, falling edge, or both edges. The input capture function can be used to measure pulse width or period. • Sample setup procedure for input capture Figure 10-23 shows a sample procedure for setting up input capture. 329 Input selection Select input-capture input 1 1. Set TIOR to select the input capture function of a general register and the rising edge, falling edge, or both edges of the input capture signal. Clear the port data direction bit to 0 before making these TIOR settings. Start counter 2 2. Set the STR bit to 1 in TSTR to start the timer counter. Input capture Figure 10-23 Setup Procedure for Input Capture (Example) • Examples of input capture Figure 10-24 illustrates input capture when the falling edge of TIOCB and both edges of TIOCA are selected as capture edges. TCNT is cleared by input capture into GRB. TCNT value H'0180 H'0160 H'0005 H'0000 TIOCB Counter cleared by TIOCB input (falling edge) Time TIOCA GRA H'0005 H'0160 GRB H'0180 Figure 10-24 Input Capture (Example) 330 • Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in TIOR. Figure 10-25 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges. ø Input-capture input Internal input capture signal TCNT N GRA, GRB N Figure 10-25 Input Capture Signal Timing 331 10.4.3 Synchronization The synchronization function enables two or more timer counters to be synchronized by writing the same data to them simultaneously (synchronous preset). With appropriate TCR settings, two or more timer counters can also be cleared simultaneously (synchronous clear). Synchronization enables additional general registers to be associated with a single time base. Synchronization can be selected for all channels (0 to 4). Sample Setup Procedure for Synchronization: Figure 10-26 shows a sample procedure for setting up synchronization. Setup for synchronization Select synchronization 1 Synchronous preset Synchronous clear Write to TCNT 2 Clearing synchronized to this channel? Yes Select counter clear source No 3 Select counter clear source 4 Start counter 5 Start counter 5 Synchronous preset Counter clear Synchronous clear 1. Set the SYNC bits to 1 in TSNC for the channels to be synchronized. 2. When a value is written in TCNT in one of the synchronized channels, the same value is simultaneously written in TCNT in the other channels (synchronized preset). 3. Set the CCLR1 or CCLR0 bit in TCR to have the counter cleared by compare match or input capture. 4. Set the CCLR1 and CCLR0 bits in TCR to have the counter cleared synchronously. 5. Set the STR bits in TSTR to 1 to start the synchronized counters. Figure 10-26 Setup Procedure for Synchronization (Example) 332 Example of Synchronization: Figure 10-27 shows an example of synchronization. Channels 0, 1, and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by compare match with GRB0. A three-phase PWM waveform is output from pins TIOCA0, TIOCA1, and TIOCA2. For further information on PWM mode, see section 10.4.4, PWM Mode. Value of TCNT0 to TCNT2 Cleared by compare match with GRB0 GRB0 GRB1 GRA0 GRB2 GRA1 GRA2 Time TIOCA0 TIOCA1 TIOCA2 Figure 10-27 Synchronization (Example) 333 10.4.4 PWM Mode In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin. GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which the PWM output changes to 0. If either GRA or GRB is selected as the counter clear source, a PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin. PWM mode can be selected in all channels (0 to 4). Table 10-4 summarizes the PWM output pins and corresponding registers. If the same value is set in GRA and GRB, the output does not change when compare match occurs. Table 10-4 PWM Output Pins and Registers Channel 0 1 2 3 4 Output Pin TIOCA0 TIOCA1 TIOCA2 TIOCA3 TIOCA4 1 Output GRA0 GRA1 GRA2 GRA3 GRA4 0 Output GRB0 GRB1 GRB2 GRB3 GRB4 334 Sample Setup Procedure for PWM Mode: Figure 10-28 shows a sample procedure for setting up PWM mode. PWM mode Select counter clock 1 Select counter clear source 2 Set GRA 3 Set GRB 4 Select PWM mode 5 Start counter 6 PWM mode 1. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge(s) of the external clock signal. 2. Set bits CCLR1 and CCLR0 in TCR to select the counter clear source. 3. Set the time at which the PWM waveform should go to 1 in GRA. 4. Set the time at which the PWM waveform should go to 0 in GRB. 5. Set the PWM bit in TMDR to select PWM mode. When PWM mode is selected, regardless of the TIOR contents, GRA and GRB become output compare registers specifying the times at which the PWM goes to 1 and 0. The TIOCA pin automatically becomes the PWM output pin. The TIOCB pin conforms to the settings of bits IOB1 and IOB0 in TIOR. If TIOCB output is not desired, clear both IOB1 and IOB0 to 0. 6. Set the STR bit to 1 in TSTR to start the timer counter. Figure 10-28 Setup Procedure for PWM Mode (Example) 335 Examples of PWM Mode: Figure 10-29 shows examples of operation in PWM mode. The PWM waveform is output from the TIOCA pin. The output goes to 1 at compare match with GRA, and to 0 at compare match with GRB. In the examples shown, TCNT is cleared by compare match with GRA or GRB. Synchronized operation and free-running counting are also possible. TCNT value Counter cleared by compare match with GRA GRA GRB H'0000 Time TIOCA a. Counter cleared by GRA TCNT value Counter cleared by compare match with GRB GRB GRA H'0000 Time TIOCA b. Counter cleared by GRB Figure 10-29 PWM Mode (Example 1) 336 Figure 10-30 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%. If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB, the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB is set to a higher value than GRA, the duty cycle is 100%. TCNT value GRB Counter cleared by compare match with GRB GRA H'0000 Time TIOCA Write to GRA a. 0% duty cycle TCNT value GRA Write to GRA Counter cleared by compare match with GRA GRB H'0000 Time TIOCA Write to GRB Write to GRB b. 100% duty cycle Figure 10-30 PWM Mode (Example 2) 337 10.4.5 Reset-Synchronized PWM Mode In reset-synchronized PWM mode channels 3 and 4 are combined to produce three pairs of complementary PWM waveforms, all having one waveform transition point in common. When reset-synchronized PWM mode is selected TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 automatically become PWM output pins, and TCNT3 functions as an upcounter. Table 10-5 lists the PWM output pins. Table 10-6 summarizes the register settings. Table 10-5 Output Pins in Reset-Synchronized PWM Mode Channel 3 Output Pin TIOCA3 TIOCB3 4 TIOCA4 TOCXA4 TIOCB4 TOCXB4 Description PWM output 1 PWM output 1´ (complementary waveform to PWM output 1) PWM output 2 PWM output 2´ (complementary waveform to PWM output 2) PWM output 3 PWM output 3´ (complementary waveform to PWM output 3) Table 10-6 Register Settings in Reset-Synchronized PWM Mode Register TCNT3 TCNT4 GRA3 GRB3 GRA4 GRB4 Setting Initially set to H'0000 Not used (operates independently) Specifies the count period of TCNT3 Specifies a transition point of PWM waveforms output from TIOCA3 and TIOCB3 Specifies a transition point of PWM waveforms output from TIOCA4 and TOCXA4 Specifies a transition point of PWM waveforms output from TIOCB4 and TOCXB4 338 Sample Setup Procedure for Reset-Synchronized PWM Mode: Figure 10-31 shows a sample procedure for setting up reset-synchronized PWM mode. Reset-synchronized PWM mode Stop counter 1 Select counter clock 2 Select counter clear source 3 Select reset-synchronized PWM mode 4 Set TCNT 5 Set general registers 6 Start counter 7 Reset-synchronized PWM mode 1. Clear the STR3 bit in TSTR to 0 to halt TCNT3. Reset-synchronized PWM mode must be set up while TCNT3 is halted. 2. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source for channel 3. If an external clock source is selected, select the external clock edge(s) with bits CKEG1 and CKEG0 in TCR. 3. Set bits CCLR1 and CCLR0 in TCR3 to select GRA3 compare match as the counter clear source. 4. Set bits CMD1 and CMD0 in TFCR to select reset-synchronized PWM mode. TIOCA3, TIOCB3, TIOCA4, TIOCB4, TOCXA4, and TOCXB4 automatically become PWM output pins. 5. Preset TCNT3 to H'0000. TCNT4 need not be preset. 6. GRA3 is the waveform period register. Set the waveform period value in GRA3. Set transition times of the PWM output waveforms in GRB3, GRA4, and GRB4. Set times within the compare match range of TCNT3. X ≤ GRA3 (X: setting value) 7. Set the STR3 bit in TSTR to 1 to start TCNT3. Figure 10-31 Setup Procedure for Reset-Synchronized PWM Mode (Example) 339 Example of Reset-Synchronized PWM Mode: Figure 10-32 shows an example of operation in reset-synchronized PWM mode. TCNT3 operates as an up-counter in this mode. TCNT4 operates independently, detached from GRA4 and GRB4. When TCNT3 matches GRA3, TCNT3 is cleared and resumes counting from H'0000. The PWM outputs toggle at compare match with GRB3, GRA4, GRB4, and TCNT3 respectively, and all toggle when the counter is cleared. TCNT3 value Counter cleared at compare match with GRA3 GRA3 GRB3 GRA4 GRB4 H'0000 Time TIOCA3 TIOCB3 TIOCA4 TOCXA4 TIOCB4 TOCXB4 Figure 10-32 Operation in Reset-Synchronized PWM Mode (When OLS3 = OLS4 = 1) (Example) For the settings and operation when reset-synchronized PWM mode and buffer mode are both selected, see section 10.4.8, Buffering. 340 10.4.6 Complementary PWM Mode In complementary PWM mode channels 3 and 4 are combined to output three pairs of complementary, non-overlapping PWM waveforms. When complementary PWM mode is selected TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 automatically become PWM output pins, and TCNT3 and TCNT4 function as up/down-counters. Table 10-7 lists the PWM output pins. Table 10-8 summarizes the register settings. Table 10-7 Output Pins in Complementary PWM Mode Channel 3 Output Pin TIOCA3 TIOCB3 4 TIOCA4 TOCXA4 TIOCB4 TOCXB4 Description PWM output 1 PWM output 1´ (non-overlapping complementary waveform to PWM output 1) PWM output 2 PWM output 2´ (non-overlapping complementary waveform to PWM output 2) PWM output 3 PWM output 3´ (non-overlapping complementary waveform to PWM output 3) Table 10-8 Register Settings in Complementary PWM Mode Register TCNT3 TCNT4 GRA3 GRB3 GRA4 GRB4 Setting Initially specifies the non-overlap margin (difference to TCNT4) Initially set to H'0000 Specifies the upper limit value of TCNT3 minus 1 Specifies a transition point of PWM waveforms output from TIOCA3 and TIOCB3 Specifies a transition point of PWM waveforms output from TIOCA4 and TOCXA4 Specifies a transition point of PWM waveforms output from TIOCB4 and TOCXB4 341 Setup Procedure for Complementary PWM Mode: Figure 10-33 shows a sample procedure for setting up complementary PWM mode. Complementary PWM mode Stop counting 1 1. Clear bits STR3 and STR4 to 0 in TSTR to halt the timer counters. Complementary PWM mode must be set up while TCNT3 and TCNT4 are halted. 2. Set bits TPSC2 to TPSC0 in TCR to select the same counter clock source for channels 3 and 4. If an external clock source is selected, select the external clock edge(s) with bits CKEG1 and CKEG0 in TCR. Do not select any counter clear source with bits CCLR1 and CCLR0 in TCR. 3. Set bits CMD1 and CMD0 in TFCR to select complementary PWM mode. TIOCA3, TIOCB3, TIOCA4, TIOCB4, TOCXA4, and TOCXB4 automatically become PWM output pins. 4. Clear TCNT4 to H'0000. Set the non-overlap margin in TCNT3. Do not set TCNT3 and TCNT4 to the same value. 5. GRA3 is the waveform period register. Set the upper limit value of TCNT3 minus 1 in GRA3. Set transition times of the PWM output waveforms in GRB3, GRA4, and GRB4. Set times within the compare match range of TCNT3 and TCNT4. T ≤ X (X: initial setting of GRB3, GRA4, or GRB4. T: initial setting of TCNT3) 6. Set bits STR3 and STR4 in TSTR to 1 to start TCNT3 and TCNT4. Select counter clock 2 Select complementary PWM mode 3 Set TCNTs 4 Set general registers 5 Start counters 6 Complementary PWM mode Note: After exiting complementary PWM mode, to resume operating in complementary PWM mode, follow the entire setup procedure from step 1 again. Figure 10-33 Setup Procedure for Complementary PWM Mode (Example) 342 Clearing Procedure for Complementary PWM Mode: Figure 10-34 shows the steps to clear complementary PWM mode. First, (1) set combination mode (CMD) 1 and 0 bits in the timer function control register (TFCR) from 10 back to 00 or 01, to switch from complementary PWM mode to normal operating mode. Next, (2) wait at least one period of the counter input clock used by channels 3 and 4, then clear counter start (STR) 3 and 4 bits in the timer start register (TSTR) to stop operation of counters TCNT3 and TCNT4 in channels 3 and 4. If a procedure other than that described above is used to clear complementary PWM mode, the output waveform may not change according to the setting when complementary PWM mode is set again. Complementary PWM mode 1. Clear the CMD1 bit of TFCR to 0 to set channels 3 and 4 to normal operating mode. 1 2. After setting channels 3 and 4 to normal operating mode, wait at least one counter clock period, then clear bits STR3 and STR4 of TSTR to 0 to stop counter operation of TCNT3 and TCNT4. Clear complementary PWM mode Stop couating 2 Normal operating mode Figure 10-34 Clearing Procedure for Complementary PWM Mode 343 Examples of Complementary PWM Mode: Figure 10-35 shows an example of operation in complementary PWM mode. TCNT3 and TCNT4 operate as up/down-counters, counting down from compare match between TCNT3 and GRA3 and counting up from the point at which TCNT4 underflows. During each up-and-down counting cycle, PWM waveforms are generated by compare match with general registers GRB3, GRA4, and GRB4. Since TCNT3 is initially set to a higher value than TCNT4, compare match events occur in the sequence TCNT3, TCNT4, TCNT4, TCNT3. TCNT3 and TCNT4 values GRA3 Down-counting starts at compare match between TCNT3 and GRA3 TCNT3 GRB3 GRA4 GRB4 H'0000 Up-counting starts when TCNT4 underflows TCNT4 Time TIOCA3 TIOCB3 TIOCA4 TOCXA4 TIOCB4 TOCXB4 Figure 10-35 Operation in Complementary PWM Mode (When OLS3 = OLS4 = 1) (Example 1) 344 Figure 10-36 shows examples of waveforms with 0% and 100% duty cycles (in one phase) in complementary PWM mode. In this example the outputs change at compare match with GRB3, so waveforms with duty cycles of 0% or 100% can be output by setting GRB3 to a value larger than GRA3. The duty cycle can be changed easily during operation by use of the buffer registers. For further information see section 10.4.8, Buffering. TCNT3 and TCNT4 values GRA3 GRB3 H'0000 TIOCA3 TIOCB3 0% duty cycle a. 0% duty cycle TCNT3 and TCNT4 values GRA3 Time GRB3 H'0000 TIOCA3 TIOCB3 100% duty cycle b. 100% duty cycle Time Figure 10-36 Operation in Complementary PWM Mode (When OLS3 = OLS4 = 1) (Example 2) 345 In complementary PWM mode, TCNT3 and TCNT4 overshoot and undershoot at the transitions between up-counting and down-counting. The setting conditions for the IMFA bit in channel 3 and the OVF bit in channel 4 differ from the usual conditions. In buffered operation the buffer transfer conditions also differ. Timing diagrams are shown in figures 10-37 and 10-38. TCNT3 N–1 N N+1 N N–1 GRA3 N IMFA Set to 1 Buffer transfer signal (BR to GR) Flag not set GR Buffer transfer No buffer transfer Figure 10-37 Overshoot Timing 346 Underflow TCNT4 H'0001 H'0000 H'FFFF Overflow H'0000 OVF Set to 1 Buffer transfer signal (BR to GR) Flag not set GR Buffer transfer No buffer transfer Figure 10-38 Undershoot Timing In channel 3, IMFA is set to 1 only during up-counting. In channel 4, OVF is set to 1 only when an underflow occurs. When buffering is selected, buffer register contents are transferred to the general register at compare match A3 during up-counting, and when TCNT4 underflows. General Register Settings in Complementary PWM Mode: When setting up general registers for complementary PWM mode or changing their settings during operation, note the following points. • Initial settings Do not set values from H'0000 to T – 1 (where T is the initial value of TCNT3). After the counters start and the first compare match A3 event has occurred, however, settings in this range also become possible. • Changing settings Use the buffer registers. Correct waveform output may not be obtained if a general register is written to directly. • Cautions on changes of general register settings Figure 10-39 shows six correct examples and one incorrect example. 347 GRA3 GR H'0000 BR Not allowed GR Figure 10-39 Changing a General Register Setting by Buffer Transfer (Example 1) — Buffer transfer at transition from up-counting to down-counting If the general register value is in the range from GRA3 – T + 1 to GRA3, do not transfer a buffer register value outside this range. Conversely, if the general register value is outside this range, do not transfer a value within this range. See figure 10-40. GRA3 + 1 GRA3 Illegal changes GRA3 – T + 1 GRA3 – T TCNT3 TCNT4 Figure 10-40 Changing a General Register Setting by Buffer Transfer (Caution 1) 348 — Buffer transfer at transition from down-counting to up-counting If the general register value is in the range from H'0000 to T – 1, do not transfer a buffer register value outside this range. Conversely, when a general register value is outside this range, do not transfer a value within this range. See figure 10-41. TCNT3 TCNT4 T T–1 Illegal changes H'0000 H'FFFF Figure 10-41 Changing a General Register Setting by Buffer Transfer (Caution 2) 349 — General register settings outside the counting range (H'0000 to GRA3) Waveforms with a duty cycle of 0% or 100% can be output by setting a general register to a value outside the counting range. When a buffer register is set to a value outside the counting range, then later restored to a value within the counting range, the counting direction (up or down) must be the same both times. See figure 10-42. GRA3 GR H'0000 0% duty cycle Output pin Output pin 100% duty cycle BR GR Write during down-counting Write during up-counting Figure 10-42 Changing a General Register Setting by Buffer Transfer (Example 2) Settings can be made in this way by detecting GRA3 compare match or TCNT4 underflow before writing to the buffer register. They can also be made by using GRA3 compare match to activate the DMAC. 350 10.4.7 Phase Counting Mode In phase counting mode the phase difference between two external clock inputs (at the TCLKA and TCLKB pins) is detected, and TCNT2 counts up or down accordingly. In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock input pins and TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to TPSC0, CKEG1, and CKEG0 in TCR2. Settings of bits CCLR1, CCLR0 in TCR2, and settings in TIOR2, TIER2, TSR2, GRA2, and GRB2 are valid. The input capture and output compare functions can be used, and interrupts can be generated. Phase counting is available only in channel 2. Sample Setup Procedure for Phase Counting Mode: Figure 10-43 shows a sample procedure for setting up phase counting mode. Phase counting mode Select phase counting mode 1 Select flag setting condition 2 1. Set the MDF bit in TMDR to 1 to select phase counting mode. 2. Select the flag setting condition with the FDIR bit in TMDR. 3. Set the STR2 bit to 1 in TSTR to start the timer counter. Start counter 3 Phase counting mode Figure 10-43 Setup Procedure for Phase Counting Mode (Example) 351 Example of Phase Counting Mode: Figure 10-44 shows an example of operations in phase counting mode. Table 10-9 lists the up-counting and down-counting conditions for TCNT2. In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must also be at least 1.5 states, and the pulse width must be at least 2.5 states. See figure 10-45. TCNT2 value Counting up Counting down Time TCLKB TCLKA Figure 10-44 Operation in Phase Counting Mode (Example) Table 10-9 Up/Down Counting Conditions Counting Direction TCLKB TCLKA Low Up-Counting High High Low Down-Counting High Low Low High Phase difference Phase difference Pulse width Pulse width TCLKA TCLKB Phase difference and overlap: at least 1.5 states Pulse width: at least 2.5 states Overlap Overlap Figure 10-45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode 352 10.4.8 Buffering Buffering operates differently depending on whether a general register is an output compare register or an input capture register, with further differences in reset-synchronized PWM mode and complementary PWM mode. Buffering is available only in channels 3 and 4. Buffering operations under the conditions mentioned above are described next. • General register used for output compare The buffer register value is transferred to the general register at compare match. See figure 10-46. Compare match signal BR GR Comparator TCNT Figure 10-46 Compare Match Buffering • General register used for input capture The TCNT value is transferred to the general register at input capture. The previous general register value is transferred to the buffer register. See figure 10-47. Input capture signal BR GR TCNT Figure 10-47 Input Capture Buffering 353 • Complementary PWM mode The buffer register value is transferred to the general register when TCNT3 and TCNT4 change counting direction. This occurs at the following two times: — When TCNT3 matches GRA3 — When TCNT4 underflows • Reset-synchronized PWM mode The buffer register value is transferred to the general register at compare match A3. Sample Buffering Setup Procedure: Figure 10-48 shows a sample buffering setup procedure. Buffering Select general register functions 1 Set buffer bits 2 1. Set TIOR to select the output compare or input capture function of the general registers. 2. Set bits BFA3, BFA4, BFB3, and BFB4 in TFCR to select buffering of the required general registers. 3. Set the STR bits to 1 in TSTR to start the timer counters. Start counters 3 Buffered operation Figure 10-48 Buffering Setup Procedure (Example) 354 Examples of Buffering: Figure 10-49 shows an example in which GRA is set to function as an output compare register buffered by BRA, TCNT is set to operate as a periodic counter cleared by GRB compare match, and TIOCA and TIOCB are set to toggle at compare match A and B. Because of the buffer setting, when TIOCA toggles at compare match A, the BRA value is simultaneously transferred to GRA. This operation is repeated each time compare match A occurs. Figure 10-50 shows the transfer timing. TCNT value GRB H'0250 H'0200 H'0100 H'0000 BRA GRA TIOCB TIOCA H'0200 H'0250 Counter cleared by compare match B Time H'0100 H'0200 H'0100 H'0200 H'0200 Toggle output Toggle output Compare match A Figure 10-49 Register Buffering (Example 1: Buffering of Output Compare Register) 355 ø TCNT Compare match signal Buffer transfer signal BR GR n N N n n+1 Figure 10-50 Compare Match and Buffer Transfer Timing (Example) 356 Figure 10-51 shows an example in which GRA is set to function as an input capture register buffered by BRA, and TCNT is cleared by input capture B. The falling edge is selected as the input capture edge at TIOCB. Both edges are selected as input capture edges at TIOCA. Because of the buffer setting, when the TCNT value is captured into GRA at input capture A, the previous GRA value is simultaneously transferred to BRA. Figure 10-52 shows the transfer timing. TCNT value H'0180 H'0160 Counter cleared by input capture B H'0005 H'0000 TIOCB Time TOICA GRA H'0005 H'0160 BRA H'0005 H'0160 GRB H'0180 Input capture A Figure 10-51 Register Buffering (Example 2: Buffering of Input Capture Register) 357 ø TIOC pin Input capture signal TCNT GR BR M m n n M n+1 N n M N n N+1 Figure 10-52 Input Capture and Buffer Transfer Timing (Example) 358 Figure 10-53 shows an example in which GRB3 is buffered by BRB3 in complementary PWM mode. Buffering is used to set GRB3 to a higher value than GRA3, generating a PWM waveform with 0% duty cycle. The BRB3 value is transferred to GRB3 when TCNT3 matches GRA3, and when TCNT4 underflows. TCNT3 and TCNT4 values H'1FFF GRA3 TCNT3 TCNT4 GRB3 H'0999 H'0000 Time BRB3 GRB3 H'0999 H'0999 H'0999 H'1FFF H'1FFF H'1FFF H'0999 H'0999 TIOCA3 TIOCB3 Figure 10-53 Register Buffering (Example 4: Buffering in Complementary PWM Mode) 359 10.4.9 ITU Output Timing The ITU outputs from channels 3 and 4 can be disabled by bit settings in TOER or by an external trigger, or inverted by bit settings in TOCR. Timing of Enabling and Disabling of ITU Output by TOER: In this example an ITU output is disabled by clearing a master enable bit to 0 in TOER. An arbitrary value can be output by appropriate settings of the data register (DR) and data direction register (DDR) of the corresponding input/output port. Figure 10-54 illustrates the timing of the enabling and disabling of ITU output by TOER. T1 ø T2 T3 Address TOER address TOER ITU output pin Timer output I/O port ITU output Generic input/output Figure 10-54 Timing of Disabling of ITU Output by Writing to TOER (Example) 360 Timing of Disabling of ITU Output by External Trigger: If the XTGD bit is cleared to 0 in TOCR in reset-synchronized PWM mode or complementary PWM mode, when an input capture A signal occurs in channel 1, the master enable bits are cleared to 0 in TOER, disabling ITU output. Figure 10-55 shows the timing. ø TIOCA1 pin Input capture signal TOER ITU output pins N ITU output ITU output N: Arbitrary setting (H'C1 to H'FF) H'C0 I/O port Generic input/output N ITU output ITU output H'C0 I/O port Generic input/output Figure 10-55 Timing of Disabling of ITU Output by External Trigger (Example) Timing of Output Inversion by TOCR: The output levels in reset-synchronized PWM mode and complementary PWM mode can be inverted by inverting the output level select bits (OLS4 and OLS3) in TOCR. Figure 10-56 shows the timing. T1 ø T2 T3 Address TOCR address TOCR ITU output pin Inverted Figure 10-56 Timing of Inverting of ITU Output Level by Writing to TOCR (Example) 361 10.5 Interrupts The ITU has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 10.5.1 Setting of Status Flags Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a compare match signal generated when TCNT matches a general register (GR). The compare match signal is generated in the last state in which the values match (when TCNT is updated from the matching count to the next count). Therefore, when TCNT matches a general register, the compare match signal is not generated until the next timer clock input. Figure 10-57 shows the timing of the setting of IMFA and IMFB. ø TCNT input clock TCNT N N+1 GR N Compare match signal IMF IMI Figure 10-57 Timing of Setting of IMFA and IMFB by Compare Match 362 Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an input capture signal. The TCNT contents are simultaneously transferred to the corresponding general register. Figure 10-58 shows the timing. ø Input capture signal IMF TCNT N GR N IMI Figure 10-58 Timing of Setting of IMFA and IMFB by Input Capture Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when TCNT overflows from H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 10-59 shows the timing. 363 ø TCNT H'FFFF H'0000 Overflow signal OVF OVI Figure 10-59 Timing of Setting of OVF 10.5.2 Clearing of Status Flags If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. Figure 10-60 shows the timing. TSR write cycle T1 T2 T3 ø Address TSR address IMF, OVF Figure 10-60 Timing of Clearing of Status Flags 364 10.5.3 Interrupt Sources and DMA Controller Activation Each ITU channel can generate a compare match/input capture A interrupt, a compare match/input capture B interrupt, and an overflow interrupt. In total there are 15 interrupt sources, all independently vectored. An interrupt is requested when the interrupt request flag and interrupt enable bit are both set to 1. The priority order of the channels can be modified in interrupt priority registers A and B (IPRA and IPRB). For details see section 5, Interrupt Controller. Compare match/input capture A interrupts in channels 0 to 3 can activate the DMA controller (DMAC). When the DMAC is activated a CPU interrupt is not requested. Table 10-10 lists the interrupt sources. Table 10-10 ITU Interrupt Sources Channel 0 Interrupt Source IMIA0 IMIB0 OVI0 1 IMIA1 IMIB1 OVI1 2 IMIA2 IMIB2 OVI2 3 IMIA3 IMIB3 OVI3 4 IMIA4 IMIB4 OVI4 Description Compare match/input capture A0 Compare match/input capture B0 Overflow 0 Compare match/input capture A1 Compare match/input capture B1 Overflow 1 Compare match/input capture A2 Compare match/input capture B2 Overflow 2 Compare match/input capture A3 Compare match/input capture B3 Overflow 3 Compare match/input capture A4 Compare match/input capture B4 Overflow 4 DMAC Activatable Yes No No Yes No No Yes No No Yes No No No No No Low Priority* High Note: * The priority immediately after a reset is indicated. Inter-channel priorities can be changed by settings in IPRA and IPRB. 365 10.6 Usage Notes This section describes contention and other matters requiring special attention during ITU operations. Contention between TCNT Write and Clear: If a counter clear signal occurs in the T3 state of a TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 10-61. TCNT write cycle T1 T2 T3 ø Address TCNT address Internal write signal Counter clear signal TCNT N H'0000 Figure 10-61 Contention between TCNT Write and Clear 366 Contention between TCNT Word Write and Increment: If an increment pulse occurs in the T3 state of a TCNT word write cycle, writing takes priority and TCNT is not incremented. See figure 10-62. TCNT word write cycle T1 T2 T3 ø Address TCNT address Internal write signal TCNT input clock TCNT N M TCNT write data Figure 10-62 Contention between TCNT Word Write and Increment 367 Contention between TCNT Byte Write and Increment: If an increment pulse occurs in the T2 or T3 state of a TCNT byte write cycle, writing takes priority and TCNT is not incremented. The TCNT byte that was not written retains its previous value. See figure 10-63, which shows an increment pulse occurring in the T2 state of a byte write to TCNTH. TCNTH byte write cycle T1 T2 T3 ø Address TCNTH address Internal write signal TCNT input clock TCNTH N TCNTH write data M TCNTL X X+1 X Figure 10-63 Contention between TCNT Byte Write and Increment 368 Contention between General Register Write and Compare Match: If a compare match occurs in the T3 state of a general register write cycle, writing takes priority and the compare match signal is inhibited. See figure 10-64. General register write cycle T1 T2 T3 ø Address GR address Internal write signal TCNT N N+1 GR N M General register write data Compare match signal Inhibited Figure 10-64 Contention between General Register Write and Compare Match 369 Contention between TCNT Write and Overflow or Underflow: If an overflow occurs in the T3 state of a TCNT write cycle, writing takes priority and the counter is not incremented. OVF is set to 1.The same holds for underflow. See figure 10-65. TCNT write cycle T1 T2 T3 ø Address TCNT address Internal write signal TCNT input clock Overflow signal TCNT H'FFFF TCNT write data M OVF Figure 10-65 Contention between TCNT Write and Overflow 370 Contention between General Register Read and Input Capture: If an input capture signal occurs during the T3 state of a general register read cycle, the value before input capture is read. See figure 10-66. General register read cycle T1 T2 T3 ø Address GR address Internal read signal Input capture signal GR X M Internal data bus X Figure 10-66 Contention between General Register Read and Input Capture 371 Contention between Counter Clearing by Input Capture and Counter Increment: If an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. The counter is not incremented by the increment signal. The value before the counter is cleared is transferred to the general register. See figure 10-67. ø Input capture signal Counter clear signal TCNT input clock TCNT N H'0000 GR N Figure 10-67 Contention between Counter Clearing by Input Capture and Counter Increment 372 Contention between General Register Write and Input Capture: If an input capture signal occurs in the T3 state of a general register write cycle, input capture takes priority and the write to the general register is not performed. See figure 10-68. General register write cycle T1 T2 T3 ø Address GR address Internal write signal Input capture signal TCNT M GR M Figure 10-68 Contention between General Register Write and Input Capture Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is cleared in the last state at which the TCNT value matches the general register value, at the time when this value would normally be updated to the next count. The actual counter frequency is therefore given by the following formula: f= ø (N + 1) (f: counter frequency. ø: system clock frequency. N: value set in general register.) 373 Contention between Buffer Register Write and Input Capture: If a buffer register is used for input capture buffering and an input capture signal occurs in the T3 state of a write cycle, input capture takes priority and the write to the buffer register is not performed. See figure 10-69. Buffer register write cycle T1 T2 T3 ø Address BR address Internal write signal Input capture signal GR N X TCNT value BR M N Figure 10-69 Contention between Buffer Register Write and Input Capture 374 Note on Synchronous Preset: When channels are synchronized, if a TCNT value is modified by byte write access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. (Example) When channels 2 and 3 are synchronized • Byte write to channel 2 or byte write to channel 3 Write A to upper byte of channel 2 TCNT2 TCNT3 W Y X Z TCNT2 TCNT3 A A X X Upper byte Lower byte Write A to lower byte of channel 3 TCNT2 TCNT3 Upper byte Lower byte Y Y A A Upper byte Lower byte • Word write to channel 2 or word write to channel 3 TCNT2 TCNT3 W Y X Z Write AB word to channel 2 or 3 TCNT2 TCNT3 A A B B Upper byte Lower byte Upper byte Lower byte Note on Setup of Reset-Synchronized PWM Mode and Complementary PWM Mode: When setting bits CMD1 and CMD0 in TFCR, take the following precautions: • • Write to bits CMD1 and CMD0 only when TCNT3 and TCNT4 are stopped. Do not switch directly between reset-synchronized PWM mode and complementary PWM mode. First switch to normal mode (by clearing bit CMD1 to 0), then select resetsynchronized PWM mode or complementary PWM mode. 375 ITU Operating Modes Table 10-11 (a) ITU Operating Modes (Channel 0) Register Settings TSNC TMDR TFCR TOCR TOER TIOR0 TCR0 Operating Mode SYNC0 = 1 — — — — PWM0 = 0 — — — — — — IOA2 = 0 Other bits unrestricted — PWM0 = 1 — — — — — — —* * — — — — — — — Synchronization MDF FDIR PWM IOA IOB ResetComple- SynchroOutput mentary nized BufferLevel PWM PWM ing XTGD Select Master Enable Clear Select Clock Select Synchronous preset PWM mode Output compare A Output compare B — — — — — — — — IOB2 = 0 Other bits unrestricted IOA2 = 1 Other bits unrestricted Input capture A — — PWM0 = 0 — — — — — — Input capture B — — PWM0 = 0 — — — — — — IOB2 = 1 Other bits unrestricted — — CCLR1 = 0 CCLR0 = 1 Counter By compare clearing match/input capture A — — — — — — — — — — — By compare match/input capture B SYNC0 = 1 — — — — — — — CCLR1 = 1 CCLR0 = 0 — — — — CCLR1 = 1 CCLR0 = 1 Synchronous clear Setting available (valid). — Setting does not affect this mode. Legend: Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited. 376 Table 10-11 (b) ITU Operating Modes (Channel 1) Register Settings TSNC TMDR TFCR TOCR TOER TIOR1 TCR1 Operating Mode SYNC1 = 1 — — — — PWM1 = 0 — — — — — — IOA2 = 0 Other bits unrestricted IOB2 = 0 Other bits unrestricted IOA2 = 1 Other bits unrestricted IOB2 = 1 Other bits unrestricted — — PWM1 = 1 — — — — — — — *1 Synchronization MDF — — — — — — — FDIR PWM IOA IOB ResetComple- SynchroOutput mentary nized BufferLevel PWM PWM ing XTGD Select Master Enable Clear Select Clock Select Synchronous preset PWM mode Output compare A Output compare B — — — — — — — — Input capture A — — PWM1 = 0 — — — *2 — — Input capture B — — PWM1 = 0 — — — — — — Counter By compare clearing match/input capture A — — — — — — — — — — — — — CCLR1 = 0 CCLR0 = 1 — — CCLR1 = 1 CCLR0 = 0 By compare match/input capture B SYNC1 = 1 — — — — — Synchronous clear — — — CCLR1 = 1 CCLR0 = 1 Legend: Setting available (valid). — Setting does not affect this mode. Notes: 1. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited. 2. Valid only when channels 3 and 4 are operating in complementary PWM mode or reset-synchronized PWM mode. 377 Table 10-11 (c) ITU Operating Modes (Channel 2) Register Settings TSNC TMDR TFCR TOCR TOER TIOR2 TCR2 Operating Mode SYNC2 = 1 — * — PWM2 = 0 — — — — — — IOA2 = 0 Other bits unrestricted IOB2 = 0 Other bits unrestricted IOA2 = 1 Other bits unrestricted IOB2 = 1 Other bits unrestricted — PWM2 = 1 — — — — — — — — — — — — — — Synchronization MDF FDIR PWM IOA IOB ResetComple- SynchroOutput mentary nized BufferLevel PWM PWM ing XTGD Select Master Enable Clear Select Clock Select Synchronous preset PWM mode Output compare A Output compare B — — — — — — — Input capture A — — PWM2 = 0 — — — — — — Input capture B — — PWM2 = 0 — — — — — — Counter By compare clearing match/input capture A — — — — — — — — — — — CCLR1 = 0 CCLR0 = 1 — — CCLR1 = 1 CCLR0 = 0 By compare match/input capture B SYNC2 = 1 — — — — Synchronous clear MDF = 1 — — — — — CCLR1 = 1 CCLR0 = 1 — — — — — Phase counting mode Legend: Setting available (valid). — Setting does not affect this mode. Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited. 378 Table 10-11 (d) ITU Operating Modes (Channel 3) TSNC Complementary PWM IOA — IOA2 = 0 Other bits unrestricted IOB2 = 0 Other bits unrestricted *2 TMDR TIOR3 TCR3 Operating Mode Synchronous preset PWM mode Output compare A Synchronization MDF SYNC3 = 1 — — — FDIR PWM *3 — — PWM3 = 1 CMD1 = 0 — PWM3 = 0 CMD1 = 0 IOB Register Settings TFCR TOCR TOER ResetOutput SynchroLevel Master nized PWM Buffering XTGD Select Enable *1 — — CMD1 = 0 — — CMD1 = 0 — — Clear Select Clock Select Output compare B — — CMD1 = 0 CMD1 = 0 — — Input capture A — — PWM3 = 0 CMD1 = 0 CMD1 = 0 — — Input capture B — — PWM3 = 0 CMD1 = 0 CMD1 = 0 — — EA3 ignored IOA2 = 1 Other bits Other bits unrestricted unrestricted EA3 ignored IOA2 = 1 Other bits Other bits unrestricted unrestricted *1 Counter clearing — — — — — — — — CCLR1 = 0 CCLR0 = 1 *1 Illegal setting: *4 CMD1 = 1 CMD0 = 0 CMD1 = 0 CMD1 = 0 CCLR1 = 1 CCLR0 = 0 — *1 SYNC3 = 1 — — — CCLR1 = 1 CCLR0 = 1 *6 *3 — — — — — — — — — *6 — — — *1 *5 By compare match/input capture A By compare match/input capture B Synchronous clear Complementary PWM mode Reset-synchronized PWM mode Buffering (BRA) Illegal setting: CMD1 = 1 CMD0 = 0 CMD1 = 1 CMD0 = 0 CMD1 = 1 CMD0 = 1 CMD1 = 1 CMD0 = 0 CMD1 = 1 CMD0 = 1 — — BFA3 = 1 — Other bits unrestricted BFB3 = 1 — Other bits unrestricted — — CCLR1 = 0 CCLR0 = 0 CCLR1 = 0 CCLR0 = 1 Buffering (BRB) *1 Legend: Notes: 1. 2. 3. 4. 5. 6. Setting available (valid). — Setting does not affect this mode. Master enable bit settings are valid only during waveform output. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited. Do not set both channels 3 and 4 for synchronous operation when complementary PWM mode is selected. The counter cannot be cleared by input capture A when reset-synchronized PWM mode is selected. In complementary PWM mode, select the same clock source for channels 3 and 4. Use the input capture A function in channel 1. 379 Table 10-11 (e) ITU Operating Modes (Channel 4) TSNC Complementary PWM IOA — IOA2 = 0 Other bits unrestricted IOB2 = 0 Other bits unrestricted *2 TMDR TIOR4 TCR4 Operating Mode Synchronous preset PWM mode Output compare A Synchronization MDF SYNC4 = 1 — — — FDIR PWM *3 — — PWM4 = 1 CMD1 = 0 — PWM4 = 0 CMD1 = 0 IOB Register Settings TFCR TOCR TOER ResetOutput SynchroLevel Master nized PWM Buffering XTGD Select Enable *1 — — CMD1 = 0 — — CMD1 = 0 — — Clear Select Clock Select Output compare B — — CMD1 = 0 CMD1 = 0 — — Input capture A — — PWM4 = 0 CMD1 = 0 CMD1 = 0 — — Input capture B — — PWM4 = 0 CMD1 = 0 CMD1 = 0 — — EA4 ignored IOA2 = 1 Other bits Other bits unrestricted unrestricted EB4 ignored IOB2 = 1 Other bits Other bits unrestricted unrestricted *1 Counter clearing — — *4 — — *4 — — CCLR1 = 0 CCLR0 = 1 *1 — — CCLR1 = 1 CCLR0 = 0 — *1 SYNC4 = 1 — — *4 — CCLR1 = 1 CCLR0 = 1 — — — *1 *3 — — — — — — — — — — CCLR1 = 0 CCLR0 = 0 *6 *5 By compare match/input capture A By compare match/input capture B Synchronous clear Complementary PWM mode Reset-synchronized PWM mode Buffering (BRA) CMD1 = 1 CMD0 = 0 CMD1 = 1 CMD0 = 1 — — BFA4 = 1 — Other bits unrestricted BFB4 = 1 — Other bits unrestricted — Illegal setting: CMD1 = 1 CMD0 = 0 Illegal setting: CMD1 = 1 CMD0 = 0 Illegal setting: CMD1 = 1 CMD0 = 0 CMD1 = 1 CMD0 = 0 CMD1 = 1 CMD0 = 1 *6 Buffering (BRB) *1 Legend: Notes: 1. 2. 3. 4. 5. 6. Setting available (valid). — Setting does not affect this mode. Master enable bit settings are valid only during waveform output. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited. Do not set both channels 3 and 4 for synchronous operation when complementary PWM mode is selected. When reset-synchronized PWM mode is selected, TCNT4 operates independently and the counter clearing function is available. Waveform output is not affected. In complementary PWM mode, select the same clock source for channels 3 and 4. TCR4 settings are valid in reset-synchronized PWM mode, but TCNT4 operates independently, without affecting waveform output. 380 Section 11 Programmable Timing Pattern Controller 11.1 Overview The H8/3003 has a built-in programmable timing pattern controller (TPC) that provides pulse outputs by using the 16-bit integrated timer-pulse unit (ITU) as a time base. The TPC pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and independently. 11.1.1 Features TPC features are listed below. • 16-bit output data Maximum 16-bit data can be output. TPC output can be enabled on a bit-by-bit basis. • Four output groups Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit outputs. • Selectable output trigger signals Output trigger signals can be selected for each group from the compare-match signals of four ITU channels. • Non-overlap mode A non-overlap margin can be provided between pulse outputs. • Can operate together with the DMA controller (DMAC) The compare-match signals selected as trigger signals can activate the DMAC for sequential output of data without CPU intervention. 381 11.1.2 Block Diagram Figure 11-1 shows a block diagram of the TPC. ITU compare match signals PADDR Control logic NDERA TPMR PBDDR NDERB TPCR TP15 TP14 TP13 TP12 TP11 TP10 TP 9 TP 8 TP 7 TP 6 TP 5 TP 4 TP 3 TP 2 TP 1 TP 0 Legend TPMR: TPCR: NDERB: NDERA: PBDDR: PADDR: NDRB: NDRA: PBDR: PADR: Pulse output pins, group 3 PBDR Pulse output pins, group 2 NDRB Internal data bus Pulse output pins, group 1 PADR Pulse output pins, group 0 NDRA TPC output mode register TPC output control register Next data enable register B Next data enable register A Port B data direction register Port A data direction register Next data register B Next data register A Port B data register Port A data register Figure 11-1 TPC Block Diagram 382 11.1.3 TPC Pins Table 11-1 summarizes the TPC output pins. Table 11-1 TPC Pins Name TPC output 0 TPC output 1 TPC output 2 TPC output 3 TPC output 4 TPC output 5 TPC output 6 TPC output 7 TPC output 8 TPC output 9 TPC output 10 TPC output 11 TPC output 12 TPC output 13 TPC output 14 TPC output 15 Symbol TP0 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 I/O Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Group 3 pulse output Group 2 pulse output Group 1 pulse output Function Group 0 pulse output 383 11.1.4 Registers Table 11-2 summarizes the TPC registers. Table 11-2 TPC Registers Address*1 H'FFD1 H'FFD3 H'FFD4 H'FFD6 H'FFA0 H'FFA1 H'FFA2 H'FFA3 H'FFA5/ H'FFA7*3 H'FFA4 H'FFA6*3 Name Port A data direction register Port A data register Port B data direction register Port B data register TPC output mode register TPC output control register Next data enable register B Next data enable register A Next data register A Next data register B Abbreviation PADDR PADR PBDDR PBDR TPMR TPCR NDERB NDERA NDRA NDRB R/W W R/(W)*2 W R/(W)*2 R/W R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'00 H'00 H'F0 H'FF H'00 H'00 H'00 H'00 Notes: 1. Lower 16 bits of the address. 2. Bits used for TPC output cannot be written. 3. The NDRA address is H'FFA5 when the same output trigger is selected for TPC output groups 0 and 1 by settings in TPCR. When the output triggers are different, the NDRA address is H'FFA7 for group 0 and H'FFA5 for group 1. Similarly, the address of NDRB is H'FFA4 when the same output trigger is selected for TPC output groups 2 and 3 by settings in TPCR. When the output triggers are different, the NDRB address is H'FFA6 for group 2 and H'FFA4 for group 3. 384 11.2 Register Descriptions 11.2.1 Port A Data Direction Register (PADDR) PADDR is an 8-bit write-only register that selects input or output for each pin in port A. Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PA7 DDR PA6 DDR PA5 DDR PA4 DDR PA3 DDR PA2 DDR PA1 DDR PA0 DDR Port A data direction 7 to 0 These bits select input or output for port A pins Port A is multiplexed with pins TP7 to TP0. Bits corresponding to pins used for TPC output must be set to 1. For further information about PADDR, see section 9.8, Port A. 11.2.2 Port A Data Register (PADR) PADR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when these TPC output groups are used. Bit Initial value Read/Write 7 PA 7 0 R/(W)* 6 PA 6 0 R/(W)* 5 PA 5 0 R/(W)* 4 PA 4 0 R/(W)* 3 PA 3 0 R/(W)* 2 PA 2 0 R/(W)* 1 PA 1 0 R/(W)* 0 PA 0 0 R/(W)* Port A data 7 to 0 These bits store output data for TPC output groups 0 and 1 Note: * Bits selected for TPC output by NDERA settings become read-only bits. For further information about PADR, see section 9.8, Port A. 385 11.2.3 Port B Data Direction Register (PBDDR) PBDDR is an 8-bit write-only register that selects input or output for each pin in port B. Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PB7 DDR PB6 DDR PB5 DDR PB4 DDR PB3 DDR PB2 DDR PB1 DDR PB0 DDR Port B data direction 7 to 0 These bits select input or output for port B pins Port B is multiplexed with pins TP15 to TP8. Bits corresponding to pins used for TPC output must be set to 1. For further information about PBDDR, see section 9.9, Port B. 11.2.4 Port B Data Register (PBDR) PBDR is an 8-bit readable/writable register that stores TPC output data for groups 2 and 3, when these TPC output groups are used. Bit Initial value Read/Write 7 PB 7 0 R/(W)* 6 PB 6 0 R/(W)* 5 PB 5 0 R/(W)* 4 PB 4 0 R/(W)* 3 PB 3 0 R/(W)* 2 PB 2 0 R/(W)* 1 PB 1 0 R/(W)* 0 PB 0 0 R/(W)* Port B data 7 to 0 These bits store output data for TPC output groups 2 and 3 Note: * Bits selected for TPC output by NDERB settings become read-only bits. For further information about PBDR, see section 9.9, Port B. 386 11.2.5 Next Data Register A (NDRA) NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups 1 and 0 (pins TP7 to TP0). During TPC output, when an ITU compare match event specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The address of NDRA differs depending on whether TPC output groups 0 and 1 have the same output trigger or different output triggers. NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Same Trigger for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by the same compare match event, the NDRA address is H'FFA5. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FFA7 consists entirely of reserved bits that cannot be modified and always read 1. Address H'FFA5 Bit Initial value Read/Write 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Next data 7 to 4 These bits store the next output data for TPC output group 1 Next data 3 to 0 These bits store the next output data for TPC output group 0 Address H'FFA7 Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Reserved bits 387 Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFA5 and the address of the lower 4 bits (group 0) is H'FFA7. Bits 3 to 0 of address H'FFA5 and bits 7 to 4 of address H'FFA7 are reserved bits that cannot be modified and always read 1. Address H'FFA5 Bit Initial value Read/Write 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Next data 7 to 4 These bits store the next output data for TPC output group 1 Reserved bits Address H'FFA7 Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Reserved bits Next data 3 to 0 These bits store the next output data for TPC output group 0 388 11.2.6 Next Data Register B (NDRB) NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups 3 and 2 (pins TP15 to TP8). During TPC output, when an ITU compare match event specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The address of NDRB differs depending on whether TPC output groups 2 and 3 have the same output trigger or different output triggers. NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Same Trigger for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by the same compare match event, the NDRB address is H'FFA4. The upper 4 bits belong to group 3 and the lower 4 bits to group 2. Address H'FFA6 consists entirely of reserved bits that cannot be modified and always read 1. Address H'FFA4 Bit Initial value Read/Write 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Next data 15 to 12 These bits store the next output data for TPC output group 3 Next data 11 to 8 These bits store the next output data for TPC output group 2 Address H'FFA6 Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Reserved bits 389 Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFA4 and the address of the lower 4 bits (group 2) is H'FFA6. Bits 3 to 0 of address H'FFA4 and bits 7 to 4 of address H'FFA6 are reserved bits that cannot be modified and always read 1. Address H'FFA4 Bit Initial value Read/Write 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Next data 15 to 12 These bits store the next output data for TPC output group 3 Reserved bits Address H'FFA6 Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Reserved bits Next data 11 to 8 These bits store the next output data for TPC output group 2 390 11.2.7 Next Data Enable Register A (NDERA) NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0 (TP7 to TP0) on a bit-by-bit basis. Bit Initial value Read/Write 7 NDER7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 NDER2 0 R/W 1 0 R/W 0 0 R/W NDER6 NDER5 NDER4 NDER3 NDER1 NDER0 Next data enable 7 to 0 These bits enable or disable TPC output groups 1 and 0 If a bit is enabled for TPC output by NDERA, then when the ITU compare match event selected in the TPC output control register (TPCR) occurs, the NDRA value is automatically transferred to the corresponding PADR bit, updating the output value. If TPC output is disabled, the bit value is not transferred from NDRA to PADR and the output value does not change. NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC output groups 1 and 0 (TP7 to TP0) on a bit-by-bit basis. Bits 7 to 0 NDER7 to NDER0 0 1 Description TPC outputs TP7 to TP0 are disabled (NDR7 to NDR0 are not transferred to PA7 to PA0) TPC outputs TP7 to TP0 are enabled (NDR7 to NDR0 are transferred to PA7 to PA0) (Initial value) 391 11.2.8 Next Data Enable Register B (NDERB) NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2 (TP15 to TP8) on a bit-by-bit basis. Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Next data enable 15 to 8 These bits enable or disable TPC output groups 3 and 2 If a bit is enabled for TPC output by NDERB, then when the ITU compare match event selected in the TPC output control register (TPCR) occurs, the NDRB value is automatically transferred to the corresponding PBDR bit, updating the output value. If TPC output is disabled, the bit value is not transferred from NDRB to PBDR and the output value does not change. NDERB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0—Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable TPC output groups 3 and 2 (TP15 to TP8) on a bit-by-bit basis. Bits 7 to 0 NDER15 to NDER8 0 1 Description TPC outputs TP15 to TP8 are disabled (NDR15 to NDR8 are not transferred to PB7 to PB0) TPC outputs TP15 to TP8 are enabled (NDR15 to NDR8 are transferred to PB7 to PB0) (Initial value) 392 11.2.9 TPC Output Control Register (TPCR) TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a group-by-group basis. Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Group 3 compare match select 1 and 0 These bits select the compare match Group 2 compare event that triggers TPC output group 3 match select 1 and 0 These bits select (TP15 to TP12 ) the compare match event that triggers Group 1 compare TPC output group 2 match select 1 and 0 These bits select (TP11 to TP8 ) the compare match event that triggers Group 0 compare TPC output group 1 match select 1 and 0 These bits select (TP7 to TP4 ) the compare match event that triggers TPC output group 0 (TP3 to TP0 ) TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. 393 Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits select the compare match event that triggers TPC output group 3 (TP15 to TP12). Bit 7 G3CMS1 0 Bit 6 G3CMS0 0 1 1 0 1 Description TPC output group 3 (TP15 to TP12) is triggered by compare match in ITU channel 0 TPC output group 3 (TP15 to TP12) is triggered by compare match in ITU channel 1 TPC output group 3 (TP15 to TP12) is triggered by compare match in ITU channel 2 TPC output group 3 (TP15 to TP12) is triggered by compare match in ITU channel 3 (Initial value) Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits select the compare match event that triggers TPC output group 2 (TP11 to TP8). Bit 5 G2CMS1 0 Bit 4 G2CMS0 0 1 1 0 1 Description TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU channel 0 TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU channel 1 TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU channel 2 TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU channel 3 (Initial value) 394 Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match event that triggers TPC output group 1 (TP7 to TP4). Bit 3 G1CMS1 0 Bit 2 G1CMS0 0 1 1 0 1 Description TPC output group 1 (TP7 to TP4) is triggered by compare match in ITU channel 0 TPC output group 1 (TP7 to TP4) is triggered by compare match in ITU channel 1 TPC output group 1 (TP7 to TP4) is triggered by compare match in ITU channel 2 TPC output group 1 (TP7 to TP4) is triggered by compare match in ITU channel 3 (Initial value) Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits select the compare match event that triggers TPC output group 0 (TP3 to TP0). Bit 1 G0CMS1 0 Bit 0 G0CMS0 0 1 1 0 1 Description TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 0 TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 1 TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 2 TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 3 (Initial value) 395 11.2.10 TPC Output Mode Register (TPMR) TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for each group. Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W G3NOV G2NOV G1NOV G0NOV Reserved bits Group 3 non-overlap Selects non-overlapping TPC output for group 3 (TP15 to TP12 ) Group 2 non-overlap Selects non-overlapping TPC output for group 2 (TP11 to TP8 ) Group 1 non-overlap Selects non-overlapping TPC output for group 1 (TP7 to TP4 ) Group 0 non-overlap Selects non-overlapping TPC output for group 0 (TP3 to TP0 ) The output trigger period of a non-overlapping TPC output waveform is set in general register B (GRB) in the ITU channel selected for output triggering. The non-overlap margin is set in general register A (GRA). The output values change at compare match A and B. For details see section 11.3.4, Non-Overlapping TPC Output. TPMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 4—Reserved: Read-only bits, always read as 1. 396 Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for group 3 (TP15 to TP12). Bit 3 G3NOV 0 1 Description Normal TPC output in group 3 (output values change at compare match A in the selected ITU channel) Non-overlapping TPC output in group 3 (independent 1 and 0 output at compare match A and B in the selected ITU channel) (Initial value) Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for group 2 (TP11 to TP8). Bit 2 G2NOV 0 1 Description Normal TPC output in group 2 (output values change at compare match A in the selected ITU channel) Non-overlapping TPC output in group 2 (independent 1 and 0 output at compare match A and B in the selected ITU channel) (Initial value) Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping TPC output for group 1 (TP7 to TP4). Bit 1 G1NOV 0 1 Description Normal TPC output in group 1 (output values change at compare match A in the selected ITU channel) Non-overlapping TPC output in group 1 (independent 1 and 0 output at compare match A and B in the selected ITU channel) (Initial value) Bit 0—Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping TPC output for group 0 (TP3 to TP0). Bit 0 G0NOV 0 1 Description Normal TPC output in group 0 (output values change at compare match A in the selected ITU channel) Non-overlapping TPC output in group 0 (independent 1 and 0 output at compare match A and B in the selected ITU channel) (Initial value) 397 11.3 Operation 11.3.1 Overview When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents. When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit contents are transferred to PADR or PBDR to update the output values. Figure 11-2 illustrates the TPC output operation. Table 11-3 summarizes the TPC operating conditions. DDR Q NDER Q Output trigger signal C Q TPC output pin DR D Q NDR D Internal data bus Figure 11-2 TPC Output Operation Table 11-3 TPC Operating Conditions NDER 0 DDR 0 1 1 0 1 Pin Function Generic input port Generic output port Generic input port (but the DR bit is a read-only bit, and when compare match occurs, the NDR bit value is transferred to the DR bit) TPC pulse output Sequential output of up to 16-bit patterns is possible by writing new output data to NDRA and NDRB before the next compare match. For information on non-overlapping operation, see section 11.3.4, Non-Overlapping TPC Output. 398 11.3.2 Output Timing If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output when the selected compare match event occurs. Figure 11-3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. ø TCNT N N+1 GRA Compare match A signal N NDRB n PBDR TP8 to TP15 m m n n Figure 11-3 Timing of Transfer of Next Data Register Contents and Output (Example) 399 11.3.3 Normal TPC Output Sample Setup Procedure for Normal TPC Output: Figure 11-4 shows a sample procedure for setting up normal TPC output. Normal TPC output Select GR functions Set GRA value ITU setup Select counting operation Select interrupt request 1 2 3 4 1. Set initial output data Select port output Port and TPC setup Enable TPC output Select TPC output trigger Set next TPC output data 5 6 7 8 9 ITU setup Start counter 10 Set TIOR to make GRA an output compare register (with output inhibited). 2. Set the TPC output trigger period. 3. Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. 4. Enable the IMFA interrupt in TIER. The DMAC can also be set up to transfer data to the next data register. 5. Set the initial output values in the DR bits of the input/output port pins to be used for TPC output. 6. Set the DDR bits of the input/output port pins to be used for TPC output to 1. 7. Set the NDER bits of the pins to be used for TPC output to 1. 8. Select the ITU compare match event to be used as the TPC output trigger in TPCR. 9. Set the next TPC output values in the NDR bits. 10. Set the STR bit to 1 in TSTR to start the timer counter. 11. At each IMFA interrupt, set the next output values in the NDR bits. Compare match? Yes Set next TPC output data No 11 Figure 11-4 Setup Procedure for Normal TPC Output (Example) 400 Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 11-5 shows an example in which the TPC is used for cyclic five-phase pulse output. TCNT value TCNT GRA Compare match H'0000 NDRB 80 C0 40 60 20 30 10 18 08 88 80 C0 40 Time PBDR 00 80 C0 40 60 20 30 10 18 08 88 80 C0 TP15 TP14 TP13 TP12 TP11 • • • • The ITU channel to be used as the output trigger channel is set up so that GRA is an output compare register and the counter will be cleared by compare match A. The trigger period is set in GRA. The IMIEA bit is set to 1 in TIER to enable the compare match A interrupt. H'F8 is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in TPCR to select compare match in the ITU channel set up in step 1 as the output trigger. Output data H'80 is written in NDRB. The timer counter in this ITU channel is started. When compare match A occurs, the NDRB contents are transferred to PBDR and output. The compare match/input capture A (IMFA) interrupt service routine writes the next output data (H'C0) in NDRB. Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88… at successive IMFA interrupts. If the DMAC is set for activation by this interrupt, pulse output can be obtained without loading the CPU. Figure 11-5 Normal TPC Output Example (Five-Phase Pulse Output) 401 11.3.4 Non-Overlapping TPC Output Sample Setup Procedure for Non-Overlapping TPC Output: Figure 11-6 shows a sample procedure for setting up non-overlapping TPC output. Non-overlapping TPC output Select GR functions Set GR values ITU setup Select counting operation Select interrupt requests 3 4 1 2 1. Set TIOR to make GRA and GRB output compare registers (with output inhibited). 2. Set the TPC output trigger period in GRB and the non-overlap margin in GRA. 3. Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. 4. Enable the IMFA interrupt in TIER. The DMAC can also be set up to transfer data to the next data register. 5. Set the initial output values in the DR bits of the input/output port pins to be used for TPC output. 6. Set the DDR bits of the input/output port pins to be used for TPC output to 1. 7. Set the NDER bits of the pins to be used for TPC output to 1. 8. In TPCR, select the ITU compare match event to be used as the TPC output trigger. 9. In TPMR, select the groups that will operate in non-overlap mode. 10. Set the next TPC output values in the NDR bits. 11. Set the STR bit to 1 in TSTR to start the timer counter. 12. At each IMFA interrupt, write the next output value in the NDR bits. Set initial output data Set up TPC output Enable TPC transfer Port and TPC setup Select TPC transfer trigger Select non-overlapping groups Set next TPC output data 5 6 7 8 9 10 ITU setup Start counter 11 Compare match A? Yes Set next TPC output data No 12 Figure 11-6 Setup Procedure for Non-Overlapping TPC Output (Example) 402 Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary NonOverlapping Output): Figure 11-7 shows an example of the use of TPC output for four-phase complementary non-overlapping pulse output. TCNT value GRB GRA H'0000 NDRB 95 65 59 56 95 65 Time TCNT PBDR 00 95 05 65 41 59 50 56 14 95 05 65 Non-overlap margin TP15 TP14 TP13 TP12 TP11 TP10 TP9 TP8 • The ITU channel to be used as the output trigger channel is set up so that GRA and GRB are output compare registers and the counter will be cleared by compare match B. The TPC output trigger period is set in GRB. The non-overlap margin is set in GRA. The IMIEA bit is set to 1 in TIER to enable IMFA interrupts. • H'FF is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set Bits G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is written in NDRB. • The timer counter in this ITU channel is started. When compare match B occurs, outputs change from 1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRB. • Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95… at successive IMFA interrupts. If the DMAC is set for activation by this interrupt, pulse output can be obtained without loading the CPU. Figure 11-7 Non-Overlapping TPC Output Example (Four-Phase Complementary Non-Overlapping Pulse Output) 403 11.3.5 TPC Output Triggering by Input Capture TPC output can be triggered by ITU input capture as well as by compare match. If GRA functions as an input capture register in the ITU channel selected in TPCR, TPC output will be triggered by the input capture signal. Figure 11-8 shows the timing. ø TIOC pin Input capture signal NDR N DR M N Figure 11-8 TPC Output Triggering by Input Capture (Example) 404 11.4 Usage Notes 11.4.1 Operation of TPC Output Pins TP0 to TP15 are multiplexed with ITU, DMAC, and other pin functions. When ITU or DMAC output is enabled, the corresponding pins cannot be used for TPC output. The data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin. Pin functions should be changed only under conditions in which the output trigger event will not occur. 11.4.2 Note on Non-Overlapping Output During non-overlapping operation, the transfer of NDR bit values to DR bits takes place as follows. 1. 2. NDR bits are always transferred to DR bits at compare match A. At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 11-9 illustrates the non-overlapping TPC output operation. DDR Q NDER Q Compare match A Compare match B C Q TPC output pin DR D Q NDR D Internal data bus Figure 11-9 Non-Overlapping TPC Output 405 Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the IMFA interrupt service routine write the next data in NDR, or by having the IMFA interrupt activate the DMAC. The next data must be written before the next compare match B occurs. Figure 11-10 shows the timing relationships. Compare match A Compare match B NDR write NDR write NDR DR 0 output 0/1 output Write to NDR in this interval Do not write to NDR in this interval Do not write to NDR in this interval 0 output 0/1 output Write to NDR in this interval Figure 11-10 Non-Overlapping Operation and NDR Write Timing 406 Section 12 Watchdog Timer 12.1 Overview The H8/3003 has an on-chip watchdog timer (WDT). The WDT has two selectable functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an interval timer. As a watchdog timer, it generates a reset signal for the H8/3003 chip if a system crash allows the timer counter (TCNT) to overflow before being rewritten. In interval timer operation, an interval timer interrupt is requested at each TCNT overflow. 12.1.1 Features WDT features are listed below. • Selection of eight counter clock sources ø/2, ø/32, ø/64, ø/128, ø/256, ø/512, ø/2048, or ø/4096 • • Interval timer option Timer counter overflow generates a reset signal or interrupt. The reset signal is generated in watchdog timer operation. An interval timer interrupt is generated in interval timer operation. • Watchdog timer reset signal resets the entire H8/3003 internally, and can also be output externally. The reset signal generated by timer counter overflow during watchdog timer operation resets the entire H8/3003 internally. An external reset signal can be output from the RESO pin to reset other system devices simultaneously. 407 12.1.2 Block Diagram Figure 12-1 shows a block diagram of the WDT. Overflow TCNT Interrupt signal (interval timer) Interrupt control TCSR Read/ write control Internal data bus RSTCSR Internal clock sources ø/2 ø/32 Reset (internal, external) Reset control ø/64 Clock Clock selector ø/128 ø/256 ø/512 ø/2048 ø/4096 Legend TCNT: Timer counter TCSR: Timer control/status register RSTCSR: Reset control/status register Figure 12-1 WDT Block Diagram 12.1.3 Pin Configuration Table 12-1 describes the WDT output pin. Table 12-1 WDT Pin Name Reset output Abbreviation RESO I/O Output Function External output of the watchdog timer reset signal 408 12.1.4 Register Configuration Table 12-2 summarizes the WDT registers. Table 12-2 WDT Registers Address*1 Write*2 H'FFA8 Read H'FFA8 H'FFA9 H'FFAA H'FFAB Name Timer control/status register Timer counter Reset control/status register Abbreviation TCSR TCNT RSTCSR R/W R/(W)*3 R/W R/(W)*3 Initial Value H'18 H'00 H'3F Notes: 1. Lower 16 bits of the address. 2. Write word data starting at this address. 3. Only 0 can be written in bit 7, to clear the flag. 409 12.2 Register Descriptions 12.2.1 Timer Counter (TCNT) TCNT is an 8-bit readable and writable* up-counter. Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), the OVF bit is set to 1 in TCSR. TCNT is initialized to H'00 by a reset and when the TME bit is cleared to 0. Note: * TCNT is write-protected by a password. For details see section 12.2.4, Notes on Register Access. 410 12.2.2 Timer Control/Status Register (TCSR) TCSR is an 8-bit readable and writable*1 register. Its functions include selecting the timer mode and clock source. Bit Initial value Read/Write 7 OVF 0 R/(W)*2 6 WT/IT 0 R/W 5 TME 0 R/W 4 — 1 — 3 — 1 — 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Clock select These bits select the TCNT clock source Reserved bits Timer enable Selects whether TCNT runs or halts Timer mode select Selects the mode Overflow flag Status flag indicating overflow Bits 7 to 5 are initialized to 0 by a reset and in standby mode. Bits 2 to 0 are initialized to 0 by a reset. In software standby mode bits 2 to 0 are not initialized, but retain their previous values. Notes: 1. TCSR is write-protected by a password. For details see section 12.2.4, Notes on Register Access. 2. Only 0 can be written, to clear the flag. 411 Bit 7—Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed from H'FF to H'00. Bit 7 OVF 0 1 Description [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 in OVF [Setting condition] Set when TCNT changes from H'FF to H'00 (Initial value) Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when TCNT overflows. Bit 6 WT/IT 0 1 Description Interval timer: requests interval timer interrupts Watchdog timer: generates a reset signal (Initial value) Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted. Bit 5 TME 0 1 Description TCNT is initialized to H'00 and halted TCNT is counting (Initial value) Bits 4 and 3—Reserved: Read-only bits, always read as 1. 412 Bits 2 to 0—Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock sources, obtained by prescaling the system clock (ø), for input to TCNT. Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Description ø/2 ø/32 ø/64 ø/128 ø/256 ø/512 ø/2048 ø/4096 (Initial value) 12.2.3 Reset Control/Status Register (RSTCSR) RSTCSR is an 8-bit readable and writable*1 register that indicates when a reset signal has been generated by watchdog timer overflow, and controls external output of the reset signal. Bit Initial value Read/Write 7 WRST 0 R/(W)*2 6 RSTOE 0 R/W 5 — 1 — 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Reserved bits Reset output enable Enables or disables external output of the reset signal Watchdog timer reset Indicates that a reset signal has been generated Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by reset signals generated by watchdog timer overflow. Notes: 1. RSTCSR is write-protected by a password. For details see section 12.2.4, Notes on Register Access. 2. Only 0 can be written in bit 7, to clear the flag. 413 Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3003 chip internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to initialize external system devices. Bit 7 WRST 0 1 Description [Clearing condition] Cleared to 0 by reset signal input at RES pin, or by writing 0 (Initial value) [Setting condition] Set when TCNT overflow generates a reset signal during watchdog timer operation Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin of the reset signal generated if TCNT overflows during watchdog timer operation. Bit 6 RSTOE 0 1 Description Reset signal is not output externally Reset signal is output externally (Initial value) Bits 5 to 0—Reserved: Read-only bits, always read as 1. 414 12.2.4 Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte instructions. Figure 12-2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the same write address. The write data must be contained in the lower byte of the written word. The upper byte must contain H'5A (password for TCNT) or H'A5 (password for TCSR). This transfers the write data from the lower byte to TCNT or TCSR. TCNT write Address H'FFA8 * 15 H'5A 87 Write data 0 TCSR write Address H'FFA8 * 15 H'A5 87 Write data 0 Note: * Lower 16 bits of the address. Figure 12-2 Format of Data Written to TCNT and TCSR 415 Writing to RSTCSR: RSTCSR must be written by a word transfer instruction. It cannot be written by byte transfer instructions. Figure 12-3 shows the format of data written to RSTCSR. To write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte. The H'00 in the lower byte clears the WRST bit in RSTCSR to 0. To write to the RSTOE bit, the upper byte must contain H'5A and the lower byte must contain the write data. Writing this word transfers a write data value into the RSTOE bit. Writing 0 in WRST bit Address H'FFAA* 15 H'A5 87 Write data 0 Writing to RSTOE bit Address H'FFAA* 15 H'5A 87 Write data 0 Note: * Lower 16 bits of the address. Figure 12-3 Format of Data Written to RSTCSR Reading TCNT, TCSR, and RSTCSR: These registers are read like other registers. Byte access instructions can be used. The read addresses are H'FFA8 for TCSR, H'FFA9 for TCNT, and H'FFAB for RSTCSR, as listed in table 12-3. Table 12-3 Read Addresses of TCNT, TCSR, and RSTCSR Address* H'FFA8 H'FFA9 H'FFAB Register TCSR TCNT RSTCSR Note: * Lower 16 bits of the address. 416 12.3 Operation Operations when the WDT is used as a watchdog timer and as an interval timer are described below. 12.3.1 Watchdog Timer Operation Figure 12-4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1 in TCSR. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and overflows due to a system crash etc., the H8/3003 is internally reset for a duration of 518 states. The watchdog reset signal can be externally output from the RESO pin to reset external system devices. The reset signal is output externally for 132 states. External output can be enabled or disabled by the RSTOE bit in RSTCSR. A watchdog reset has the same vector as a reset generated by input at the RES pin. Software can distinguish a RES reset from a watchdog reset by checking the WRST bit in RSTCSR. If a RES reset and a watchdog reset occur simultaneously, the RES reset takes priority. H'FF TCNT count value H'00 WDT overflow TME set to 1 OVF = 1 Start Internal reset signal H'00 written in TCNT Reset H'00 written in TCNT 518 states RESO 132 states Figure 12-4 Watchdog Timer Operation 417 12.3.2 Interval Timer Operation Figure 12-5 illustrates interval timer operation. To use the WDT as an interval timer, clear bit WT/IT to 0 and set bit TME to 1 in TCSR. An interval timer interrupt request is generated at each TCNT overflow. This function can be used to generate interval timer interrupts at regular intervals. H'FF TCNT count value Time t H'00 WT/ IT = 0 TME = 1 Interval timer interrupt Interval timer interrupt Interval timer interrupt Interval timer interrupt Figure 12-5 Interval Timer Operation 418 12.3.3 Timing of Setting of Overflow Flag (OVF) Figure 12-6 shows the timing of setting of the OVF flag in TCSR. The OVF flag is set to 1 when TCNT overflows. At the same time, a reset signal is generated in watchdog timer operation, or an interval timer interrupt is generated in interval timer operation. ø TCNT H'FF H'00 Overflow signal OVF Figure 12-6 Timing of Setting of OVF 419 12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR. Figure 12-7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is set to 1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is generated for the entire H8/3003 chip. This internal reset signal clears OVF to 0, but the WRST bit remains set to 1. The reset routine must therefore clear the WRST bit. ø TCNT H'FF H'00 Overflow signal OVF WDT internal reset WRST Figure 12-7 Timing of Setting of WRST Bit and Internal Reset 420 12.4 Interrupts During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR. 12.5 Usage Notes Contention between TCNT Write and Increment: If a timer counter clock pulse is generated during the T3 state of a write cycle to TCNT, the write takes priority and the timer count is not incremented. See figure 12-8. Write cycle: CPU writes to TCNT T1 ø T2 T3 TCNT Internal write signal TCNT input clock TCNT N M Counter write data Figure 12-8 Contention between TCNT Write and Increment Changing CKS2 to CKS0 Values: Halt TCNT by clearing the TME bit to 0 in TCSR before changing the values of bits CKS2 to CKS0. 421 422 Section 13 Serial Communication Interface 13.1 Overview The H8/3003 has a serial communication interface (SCI) with two independent channels. Both channels are functionally identical. The SCI can communicate in asynchronous mode or synchronous mode, and has a multiprocessor communication function for serial communication among two or more processors. 13.1.1 Features SCI features are listed below. • a. Selection of asynchronous or synchronous mode for serial communication Asynchronous mode Serial data communication is synchronized one character at a time. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), asynchronous communication interface adapter (ACIA), or other chip that employs standard asynchronous serial communication. It can also communicate with two or more other processors using the multiprocessor communication function. There are twelve selectable serial data communication formats. — — — — — — b. Data length: Stop bit length: Parity bit: Multiprocessor bit: Receive error detection: Break detection: 7 or 8 bits 1 or 2 bits even, odd, or none 1 or 0 parity, overrun, and framing errors by reading the RxD level directly when a framing error occurs Synchronous mode Serial data communication is synchronized with a clock signal. The SCI can communicate with other chips having a synchronous communication function. There is one serial data communication format. — Data length: 8 bits — Receive error detection: overrun errors 423 • Full duplex communication The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. The transmitting and receiving sections are both double-buffered, so serial data can be transmitted and received continuously. • • Built-in baud rate generator with selectable bit rates Selectable transmit/receive clock sources: internal clock from baud rate generator, or external clock from the SCK pin. Four types of interrupts Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested independently. The transmit-data-empty and receive-data-full interrupts can activate the DMA controller (DMAC) to transfer data. • 424 13.1.2 Block Diagram Figure 13-1 shows a block diagram of the SCI. Bus interface BRR Baud rate generator Clock External clock TEI TXI RXI ERI Internal data bus Module data bus RDR RxD RSR TDR TSR SSR SCR SMR Transmit/ receive control TxD ø ø/4 ø/16 ø/64 Parity generate Parity check SCK Legend RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register BRR: Bit rate register Figure 13-1 SCI Block Diagram 425 13.1.3 Input/Output Pins The SCI has serial pins for each channel as listed in table 13-1. Table 13-1 SCI Pins Channel 0 Name Serial clock pin Receive data pin Transmit data pin 1 Serial clock pin Receive data pin Transmit data pin Abbreviation SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 I/O Input/output Input Output Input/output Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output 13.1.4 Register Configuration The SCI has internal registers as listed in table 13-2. These registers select asynchronous or synchronous mode, specify the data format and bit rate, and control the transmitter and receiver sections. Table 13-2 Registers Channel 0 Address*1 H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 1 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBD Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Abbreviation SMR BRR SCR TDR SSR RDR SMR BRR SCR TDR SSR RDR R/W R/W R/W R/W R/W R/(W)*2 R R/W R/W R/W R/W R/(W)*2 R Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'00 H'FF H'00 H'FF H'84 H'00 Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written, to clear flags. 426 13.2 Register Descriptions 13.2.1 Receive Shift Register (RSR) RSR is the register that receives serial data. Bit Initial value Read/Write — — — — — — — — 7 6 5 4 3 2 1 0 The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first, thereby converting the data to parallel data. When 1 byte has been received, it is automatically transferred to RDR. The CPU cannot read or write RSR directly. 13.2.2 Receive Data Register (RDR) RDR is the register that stores received serial data. Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R When the SCI finishes receiving 1 byte of serial data, it transfers the received data from RSR into RDR for storage. RSR is then ready to receive the next data. This double buffering allows data to be received continuously. RDR is a read-only register. Its contents cannot be modified by the CPU. RDR is initialized to H'00 by a reset and in standby mode. 427 13.2.3 Transmit Shift Register (TSR) TSR is the register that transmits serial data. Bit Initial value Read/Write — — — — — — — — 7 6 5 4 3 2 1 0 The SCI loads transmit data from TDR into TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from TDR into TSR and starts transmitting it. If the TDRE flag is set to 1 in SSR, however, the SCI does not load the TDR contents into TSR. The CPU cannot read or write TSR directly. 13.2.4 Transmit Data Register (TDR) TDR is an 8-bit register that stores data for serial transmission. Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W When the SCI detects that TSR is empty, it moves transmit data written in TDR from TDR into TSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in TDR during serial transmission from TSR. The CPU can always read and write TDR. TDR is initialized to H'FF by a reset and in standby mode. 428 13.2.5 Serial Mode Register (SMR) SMR is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. Bit Initial value Read/Write 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Clock select 1/0 These bits select the baud rate generator’s clock source Multiprocessor mode Selects the multiprocessor function Stop bit length Selects the stop bit length Parity mode Selects even or odd parity Parity enable Selects whether a parity bit is added Character length Selects character length in asynchronous mode Communication mode Selects asynchronous or synchronous mode The CPU can always read and write SMR. SMR is initialized to H'00 by a reset and in standby mode. 429 Bit 7—Communication Mode (C/A): Selects whether the SCI operates in asynchronous or synchronous mode. Bit 7 C/A 0 1 Description Asynchronous mode Synchronous mode (Initial value) Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data length in asynchronous mode. In synchronous mode the data length is 8 bits regardless of the CHR setting. Bit 6 CHR 0 1 Description 8-bit data 7-bit data* (Initial value) Note: * When 7-bit data is selected, the MSB (bit 7) in TDR is not transmitted. Bit 5—Parity Enable (PE): In asynchronous mode, this bit enables or disables the addition of a parity bit to transmit data, and the checking of the parity bit in receive data. In synchronous mode the parity bit is neither added nor checked, regardless of the PE setting. Bit 5 PE 0 1 Description Parity bit not added or checked Parity bit added and checked* (Initial value) Note: * When PE is set to 1, an even or odd parity bit is added to transmit data according to the even or odd parity mode selected by the O/E bit, and the parity bit in receive data is checked to see that it matches the even or odd mode selected by the O/E bit. 430 Bit 4—Parity Mode (O/E): Selects even or odd parity. The O/E bit setting is valid in asynchronous mode when the PE bit is set to 1 to enable the adding and checking of a parity bit. The O/E setting is ignored in synchronous mode, or when parity adding and checking is disabled in asynchronous mode. Bit 4 O/E 0 1 Description Even parity*1 Odd parity*2 (Initial value) Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. Receive data must have an even number of 1s in the received character and parity bit combined. 2. When odd parity is selected, the parity bit added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. Receive data must have an odd number of 1s in the received character and parity bit combined. Bit 3—Stop Bit Length (STOP): Selects one or two stop bits in asynchronous mode. This setting is used only in asynchronous mode. In synchronous mode no stop bit is added, so the STOP bit setting is ignored. Bit 3 STOP 0 1 Description One stop bit*1 Two stop bits*2 (Initial value) Notes: 1. One stop bit (with value 1) is added at the end of each transmitted character. 2. Two stop bits (with value 1) are added at the end of each transmitted character. In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1 it is treated as a stop bit. If the second stop bit is 0 it is treated as the start bit of the next incoming character. 431 Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor format is selected, parity settings made by the PE and O/E bits are ignored. The MP bit setting is valid only in asynchronous mode. It is ignored in synchronous mode. For further information on the multiprocessor communication function, see section 13.3.3, Multiprocessor Communication Function. Bit 2 MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value) Bits 1 and 0—Clock Select 1 and 0 (CKS1/0): These bits select the clock source of the on-chip baud rate generator. Four clock sources are available: ø, ø/4, ø/16, and ø/64. For the relationship between the clock source, bit rate register setting, and baud rate, see section 13.2.8, Bit Rate Register. Bit 1 CKS1 0 0 1 1 Bit 0 CKS0 0 1 0 1 Description ø ø/4 ø/16 ø/64 (Initial value) 432 13.2.6 Serial Control Register (SCR) SCR enables the SCI transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source. Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Clock enable 1/0 These bits select the SCI clock source Transmit end interrupt enable Enables or disables transmitend interrupts (TEI) Multiprocessor interrupt enable Enables or disables multiprocessor interrupts Receive enable Enables or disables the receiver Transmit enable Enables or disables the transmitter Receive interrupt enable Enables or disables receive-data-full interrupts (RXI) and receive-error interrupts (ERI) Transmit interrupt enable Enables or disables transmit-data-empty interrupts (TXI) The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby mode. 433 Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from TDR to TSR. Bit 7 TIE 0 1 Description Transmit-data-empty interrupt request (TXI) is disabled* Transmit-data-empty interrupt request (TXI) is enabled (Initial value) Note: * TXI interrupt requests can be cleared by reading the value 1 from the TDRE flag, then clearing it to 0; or by clearing the TIE bit to 0. Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI) requested when the RDRF flag is set to 1 in SSR due to transfer of serial receive data from RSR to RDR; also enables or disables the receive-error interrupt (ERI). Bit 6 RIE 0 1 Description Receive-end (RXI) and receive-error (ERI) interrupt requests are disabled (Initial value) Receive-end (RXI) and receive-error (ERI) interrupt requests are enabled Note: * RXI and ERI interrupt requests can be cleared by reading the value 1 from the RDRF, FER, PER, or ORER flag, then clearing it to 0; or by clearing the RIE bit to 0. Bit 5—Transmit Enable (TE): Enables or disables the start of SCI serial transmitting operations. Bit 5 TE 0 1 Description Transmitting disabled*1 Transmitting enabled*2 (Initial value) Notes: 1. The TDRE bit is locked at 1 in SSR. 2. In the enabled state, serial transmitting starts when the TDRE bit in SSR is cleared to 0 after writing of transmit data into TDR. Select the transmit format in SMR before setting the TE bit to 1. 434 Bit 4—Receive Enable (RE): Enables or disables the start of SCI serial receiving operations. Bit 4 RE 0 1 Description Receiving disabled*1 Receiving enabled*2 (Initial value) Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These flags retain their previous values. 2. In the enabled state, serial receiving starts when a start bit is detected in asynchronous mode, or serial clock input is detected in synchronous mode. Select the receive format in SMR before setting the RE bit to 1. Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE setting is valid only in asynchronous mode, and only if the MP bit is set to 1 in SMR. The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE 0 Description Multiprocessor interrupts are disabled (normal receive operation) [Clearing conditions] The MPIE bit is cleared to 0. MPB = 1 in received data. (Initial value) 1 Multiprocessor interrupts are enabled* Receive-data-full interrupts (RXI), receive-error interrupts (ERI), and setting of the RDRF, FER, and ORER status flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. Note: * The SCI does not transfer receive data from RSR to RDR, does not detect receive errors, and does not set the RDRF, FER, and ORER flags in SSR. When it receives data in which MPB = 1, the SCI sets the MPB bit to 1 in SSR, automatically clears the MPIE bit to 0, enables RXI and ERI interrupts (if the RIE bit is set to 1 in SCR), and allows the FER and ORER flags to be set. 435 Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain new transmit data when the MSB is transmitted. Bit 2 TEIE 0 1 Description Transmit-end interrupt requests (TEI) are disabled* Transmit-end interrupt requests (TEI) are enabled* (Initial value) Note: * TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in SSR, then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0; or by clearing the TEIE bit to 0. Bits 1 and 0—Clock Enable 1 and 0 (CKE1/0): These bits select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the settings of CKE1 and CKE0, the SCK pin can be used for generic input/output, serial clock output, or serial clock input. The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external clock source is selected (CKE1 = 1). Set the CKE1 and CKE0 bits after selecting the SCI operating mode in SMR. For further details on selection of the SCI clock source, see table 13-9 in section 13.3, Operation. Bit 1 CKE1 0 Bit 0 CKE0 0 Description Asynchronous mode Synchronous mode 0 1 Asynchronous mode Synchronous mode 1 0 Asynchronous mode Synchronous mode 1 1 Asynchronous mode Synchronous mode Internal clock, SCK pin available for generic input/output *1 Internal clock, SCK pin used for serial clock output *1 Internal clock, SCK pin used for clock output *2 Internal clock, SCK pin used for serial clock output External clock, SCK pin used for clock input *3 External clock, SCK pin used for serial clock input External clock, SCK pin used for clock input *3 External clock, SCK pin used for serial clock input Notes: 1. Initial value 2. The output clock frequency is the same as the bit rate. 3. The input clock frequency is 16 times the bit rate. 436 13.2.7 Serial Status Register (SSR) SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate SCI operating status. Bit Initial value Read/Write 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor bit transfer Value of multiprocessor bit to be transmitted Multiprocessor bit Stores the received multiprocessor bit value Transmit end Status flag indicating end of transmission Parity error Status flag indicating detection of a receive parity error Framing error Status flag indicating detection of a receive framing error Overrun error Status flag indicating detection of a receive overrun error Receive data register full Status flag indicating that data has been received and stored in RDR Transmit data register empty Status flag indicating that transmit data has been transferred from TDR into TSR and new data can be written in TDR Note: * Only 0 can be written, to clear the flag. 437 The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER, and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The TEND and MPB flags are read-only bits that cannot be written. SSR is initialized to H'84 by a reset and in standby mode. Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data from TDR into TSR and the next serial transmit data can be written in TDR. Bit 7 TDRE 0 Description TDR contains valid transmit data [Clearing conditions] Software reads TDRE while it is set to 1, then writes 0. The DMAC writes data in TDR. TDR does not contain valid transmit data [Setting conditions] The chip is reset or enters standby mode. The TE bit in SCR is cleared to 0. TDR contents are loaded into TSR, so new data can be written in TDR. (Initial value) 1 Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains new receive data. Bit 6 RDRF 0 Description RDR does not contain new receive data [Clearing conditions] The chip is reset or enters standby mode. Software reads RDRF while it is set to 1, then writes 0. The DMAC reads data from RDR. RDR contains new receive data [Setting condition] When serial data is received normally and transferred from RSR to RDR. (Initial value) 1 Note: The RDR contents and RDRF flag are not affected by detection of receive errors or by clearing of the RE bit to 0 in SCR. They retain their previous values. If the RDRF flag is still set to 1 when reception of the next data ends, an overrun error occurs and receive data is lost. 438 Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5 ORER 0 Description Receiving is in progress or has ended normally [Clearing conditions] The chip is reset or enters standby mode. Software reads ORER while it is set to 1, then writes 0. A receive overrun error occurred*2 [Setting condition] Reception of the next serial data ends when RDRF = 1. (Initial value)*1 1 Notes: 1. Clearing the RE bit to 0 in SCR does not affect the ORER flag, which retains its previous value. 2. RDR continues to hold the receive data before the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while the ORER flag is set to 1. In synchronous mode, serial transmitting is also disabled. Bit 4—Framing Error (FER): Indicates that data reception ended abnormally due to a framing error in asynchronous mode. Bit 4 FER 0 Description Receiving is in progress or has ended normally [Clearing conditions] The chip is reset or enters standby mode. Software reads FER while it is set to 1, then writes 0. A receive framing error occurred*2 [Setting condition] The stop bit at the end of receive data is checked and found to be 0. (Initial value)*1 1 Notes: 1. Clearing the RE bit to 0 in SCR does not affect the FER flag, which retains its previous value. 2. When the stop bit length is 2 bits, only the first bit is checked. The second stop bit is not checked. When a framing error occurs the SCI transfers the receive data into RDR but does not set the RDRF flag. Serial receiving cannot continue while the FER flag is set to 1. In synchronous mode, serial transmitting is also disabled. 439 Bit 3—Parity Error (PER): Indicates that data reception ended abnormally due to a parity error in asynchronous mode. Bit 3 PER 0 Description Receiving is in progress or has ended normally*1 [Clearing conditions] The chip is reset or enters standby mode. Software reads PER while it is set to 1, then writes 0. (Initial value) 1 A receive parity error occurred*2 [Setting condition] The number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of O/E in SMR. Notes: 1. Clearing the RE bit to 0 in SCR does not affect the PER flag, which retains its previous value. 2. When a parity error occurs the SCI transfers the receive data into RDR but does not set the RDRF flag. Serial receiving cannot continue while the PER flag is set to 1. In synchronous mode, serial transmitting is also disabled. Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was transmitted TDR did not contain new transmit data, so transmission has ended. The TEND flag is a read-only bit and cannot be written. Bit 2 TEND 0 Description Transmission is in progress [Clearing conditions] Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag. The DMAC writes data in TDR. End of transmission [Setting conditions] The chip is reset or enters standby mode. The TE bit is cleared to 0 in SCR. TDRE is 1 when the last bit of a serial character is transmitted. (Initial value) 1 440 Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit and cannot be written. Bit 1 MPB 0 1 Description Multiprocessor bit value in receive data is 0* Multiprocessor bit value in receive data is 1 (Initial value) Note: * If the RE bit is cleared to 0 when a multiprocessor format is selected, MPB retains its previous value. Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in asynchronous mode. The MPBT setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the SCI is not transmitting. Bit 0 MPBT 0 1 Description Multiprocessor bit value in transmit data is 0 Multiprocessor bit value in transmit data is 1 (Initial value) 13.2.8 Bit Rate Register (BRR) BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in SMR that select the baud rate generator clock source, determines the serial communication bit rate. Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W The CPU can always read and write BRR. BRR is initialized to H'FF by a reset and in standby mode. The two SCI channels have independent baud rate generator control, so different values can be set in the two channels. Table 13-3 shows examples of BRR settings in asynchronous mode. Table 13-4 shows examples of BRR settings in synchronous mode. 441 Table 13-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode ø (MHz) 2 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 0 0 0 0 N 141 103 207 103 51 25 12 6 2 1 1 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 –6.99 8.51 0 –18.62 n 1 1 0 0 0 0 0 0 0 0 0 2.097152 N 148 108 217 108 54 26 13 6 2 1 1 Error (%) –0.04 0.21 0.21 0.21 –0.70 1.14 –2.48 –2.48 13.78 4.86 –14.67 n 1 1 0 0 0 0 0 0 0 0 0 2.4576 N 174 127 255 127 63 31 15 7 3 1 1 Error (%) –0.26 0 0 0 0 0 0 0 0 22.88 0 n 1 1 1 0 0 0 0 0 0 0 — N 212 155 77 155 77 38 19 9 4 2 — 3 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 –2.34 –2.34 –2.34 0 — ø (MHz) 3.6864 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 — 0 N 64 191 95 191 95 47 23 11 5 — 2 Error (%) 0.70 0 0 0 0 0 0 0 0 — 0 n 2 1 1 0 0 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 6 3 2 4 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 –6.99 0 8.51 n 2 1 1 0 0 0 0 0 0 0 0 4.9152 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) 0.31 0 0 0 0 0 0 0 0 –1.70 0 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) –0.25 0.16 0.16 0.16 0.16 0.16 –1.36 1.73 1.73 0 1.73 442 Table 13-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode (cont) ø (MHz) 6 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (%) –0.44 0.16 0.16 0.16 0.16 0.16 0.16 –2.34 –2.34 0 –2.34 n 2 2 1 1 0 0 0 0 0 0 0 6.144 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) 0.08 0 0 0 0 0 0 0 0 2.40 0 n 2 2 1 1 0 0 0 0 0 0 0 7.3728 N 130 95 191 95 191 95 47 23 11 6 5 Error (%) –0.07 0 0 0 0 0 0 0 0 5.33 0 n 2 2 1 1 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 6 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 –6.99 ø (MHz) 9.8304 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) –0.26 0 0 0 0 0 0 0 0 –1.70 0 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) –0.25 0.16 0.16 0.16 0.16 0.16 0.16 –1.36 1.73 0 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 –2.34 0 –2.34 n 2 2 2 1 1 0 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0 0 0 0 0 0 0 0 2.40 0 443 Table 13-3 Examples of Bit Rates and BRR Settings in Asynchronous Mode (cont) ø (MHz) 14 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 0 N 248 181 90 181 90 181 90 45 22 13 10 Error (%) –0.17 0.16 0.16 0.16 0.16 0.16 0.16 –0.93 –0.93 0 3.57 n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0 0 0 0 0 0 0 0 –1.70 0 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 0.16 444 Table 13-4 Examples of Bit Rates and BRR Settings in Synchronous Mode ø (MHz) Bit Rate (bits/s) 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2M 2.5 M 4M Note: Settings with an error of 1% or less are recommended. Legend Blank: No setting available —: Setting possible, but error occurs *: Continuous transmit/receive not possible The BRR setting is calculated as follows: Asynchronous mode: N= ø 64 × 22n–1 ø 8 × 22n–1 × B ×B × 106 – 1 2 n 3 2 1 1 0 0 0 0 0 0 0 0 N 70 124 249 124 199 99 49 19 9 4 1 0* n — 2 2 1 1 0 0 0 0 0 0 0 0 4 N — 249 124 249 99 199 99 39 19 9 3 1 0* n — 3 2 2 1 1 0 0 0 0 0 0 0 0 — 8 N — 124 249 124 199 99 199 79 39 19 7 3 1 0* — n — — — — 1 1 0 0 0 0 0 0 — — 0 10 N — — — — 249 124 249 99 49 24 9 4 — — 0* n — 3 3 2 2 1 1 0 0 0 0 0 0 0 — 0 16 N — 249 124 249 99 199 99 159 79 39 15 7 3 1 — 0* Synchronous mode: N= B: N: ø: n: × 106 – 1 Bit rate (bits/s) BRR setting for baud rate generator (0 ≤ N ≤ 255) System clock frequency (MHz) Baud rate generator clock source (n = 0, 1, 2, 3) (For the clock sources and values of n, see the table below.) 445 SMR Settings n 0 1 2 3 Clock Source ø ø/4 ø/16 ø/64 CKS1 0 0 1 1 CKS0 0 1 0 1 The bit rate error in asynchronous mode is calculated as follows. ø × 106 Error (%) = (N + 1) × B × 64 × 22n–1 –1 × 100 446 Table 13-5 indicates the maximum bit rates in asynchronous mode for various system clock frequencies. Tables 13-6 and 13-7 indicate the maximum bit rates with external clock input. Table 13-5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode) Settings ø (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 Maximum Bit Rate (bits/s) 62500 65536 76800 93750 115200 125000 153600 156250 187500 192000 230400 250000 307200 312500 375000 384000 437500 460800 500000 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 447 Table 13-6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) ø (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 1.2500 1.5000 1.5360 1.8432 2.0000 2.4576 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 Maximum Bit Rate (bits/s) 31250 32768 38400 46875 57600 62500 76800 78125 93750 96000 115200 125000 153600 156250 187500 192000 218750 230400 250000 448 Table 13-7 Maximum Bit Rates with External Clock Input (Synchronous Mode) ø (MHz) 2 4 6 8 10 12 14 16 External Input Clock (MHz) 0.3333 0.6667 1.0000 1.3333 1.6667 2.0000 2.3333 2.6667 Maximum Bit Rate (bits/s) 333333.3 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 449 13.3 Operation 13.3.1 Overview The SCI has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. Serial communication is possible in either mode. Asynchronous or synchronous mode and the communication format are selected in SMR, as shown in table 13-8. The SCI clock source is selected by the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 13-9. Asynchronous Mode • • Data length is selectable: 7 or 8 bits. Parity and multiprocessor bits are selectable. So is the stop bit length (1 or 2 bits). These selections determine the communication format and character length. In receiving, it is possible to detect framing errors, parity errors, overrun errors, and the break state. An internal or external clock can be selected as the SCI clock source. — When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency matching the bit rate. — When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) Synchronous Mode • • • The communication format has a fixed 8-bit data length. In receiving, it is possible to detect overrun errors. An internal or external clock can be selected as the SCI clock source. — When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices. — When an external clock is selected, the SCI operates on the input serial clock. The on-chip baud rate generator is not used. • • 450 Table 13-8 SMR Settings and Serial Communication Formats SCI Communication Format SMR Settings Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 C/A CHR MP PE STOP Mode 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 1 1 — 0 0 0 0 0 0 0 0 1 1 1 1 — 0 0 1 1 0 0 1 1 — — — — — 0 1 0 1 0 1 0 1 0 1 0 1 — Synchronous mode 8-bit data Absent Asynchronous mode (multiprocessor format) 8-bit data Present Absent Present 7-bit data Absent Asynchronous mode Data Length 8-bit data Multiprocessor Bit Absent Parity Bit Absent Stop Bit Length 1 bit 2 bits Present 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 7-bit data 1 bit 2 bits None Table 13-9 SMR and SCR Settings and SCI Clock Source Selection SMR SCR Settings SCI Transmit/Receive Clock Mode Asynchronous mode Clock Source Internal SCK Pin Function SCI does not use the SCK pin Outputs a clock with frequency matching the bit rate External Inputs a clock with frequency 16 times the bit rate Outputs the serial clock Bit 7 Bit 1 Bit 0 C/A CKE1 CKE0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Synchronous mode Internal External Inputs the serial clock 451 13.3.2 Operation in Asynchronous Mode In asynchronous mode each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible. The transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 13-2 shows the general format of asynchronous serial communication. In asynchronous serial communication the communication line is normally held in the mark (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. 1 Serial data 0 Start bit 1 bit (LSB) D0 D1 D2 D3 D4 D5 D6 (MSB) D7 0/1 Parity bit 1 Idle (mark) state 1 1 Transmit or receive data 7 bits or 8 bits One unit of data (character or frame) Stop bit 1 bit or 1 bit or no bit 2 bits Figure 13-2 Data Format in Asynchronous Communication (Example: 8-Bit Data with Parity and 2 Stop Bits) 452 Communication Formats: Table 13-10 shows the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in SMR. Table 13-10 Serial Communication Formats (Asynchronous Mode) SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 — — — — MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S S S S S S S S S Serial Communication Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP STOP STOP P P STOP STOP STOP P P STOP STOP STOP MPB STOP STOP STOP STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8 bit data S S S 8 bit data 7-bit data 7-bit data MPB STOP STOP MPB STOP MPB STOP STOP Legend S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit 453 Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. See table 13-9. When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 13-3 so that the rising edge of the clock occurs at the center of each transmit data bit. 0 D0 D1 D2 D3 D4 D5 D6 D7 O/I 1 1 1 frame Figure 13-3 Phase Relationship between Output Clock and Serial Data (Asynchronous Mode) Transmitting and Receiving Data SCI Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in SCR, then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and initializes TSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and RDR, which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped. Figure 13-4 is a sample flowchart for initializing the SCI. 454 Start of initialization Clear TE and RE bits to 0 in SCR Set CKE1 and CKE0 bits in SCR (leaving TE and RE bits cleared to 0) 1 1. Select the clock source in SCR. Clear the RIE, TIE, TEIE, MPIE, TE, and RE bits to 0. If clock output is selected in asynchronous mode, clock output starts immediately after the setting is made in SCR. 2. Select the communication format in SMR. 3. Write the value corresponding to the bit rate in BRR. This step is not necessary when an external clock is used. 4. Wait for at least the interval required to transmit or receive 1 bit, then set the TE or RE bit to 1 in SCR. Set the RIE, TIE, TEIE, and MPIE bits as necessary. Setting the TE or RE bit enables the SCI to use the TxD or RxD pin. Select communication format in SMR 2 Set value in BRR Wait 3 1 bit interval elapsed? Yes Set TE or RE bit to 1 in SCR Set RIE, TIE, TEIE, and MPIE bits as necessary No 4 Transmitting or receiving Figure 13-4 Sample Flowchart for SCI Initialization 455 Transmitting Serial Data (Asynchronous Mode): Figure 13-5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. 1 1. SCI initialization: the transmit data output function of the TxD pin is selected automatically. 2. SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0. 3. To continue transmitting serial data: after checking that the TDRE flag is 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0. When the DMAC is activated by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically. 4. To output a break signal at the end of serial transmission: set the DDR bit to 1 and clear the DR bit to 0 (DDR and DR are I/O port registers), then clear the TE bit to 0 in SCR. Initialize Start transmitting Read TDRE flag in SSR 2 No TDRE = 1? Yes Write transmit data in TDR and clear TDRE flag to 0 in SSR All data transmitted? Yes No 3 Read TEND flag in SSR No TEND = 1? Yes Output break signal? Yes Clear DR bit to 0, set DDR bit to 1 Clear TE bit to 0 in SCR No 4 End Figure 13-5 Sample Flowchart for Transmitting Serial Data 456 In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: — Start bit: One 0 bit is output. — Transmit data: 7 or 8 bits are output, LSB first. — Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. — Stop bit: One or two 1 bits (stop bits) are output. — Mark state: Output of 1 bits continues until the start bit of the next transmit data. • The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a transmit-end interrupt (TEI) is requested at this time. • Figure 13-6 shows an example of SCI transmit operation in asynchronous mode. Start bit 0 D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 D0 D1 Parity Stop bit bit D7 0/1 1 1 Data Data 1 Idle (mark) state TDRE TEND TXI interrupt request TXI interrupt handler writes data in TDR and clears TDRE flag to 0 1 frame TXI interrupt request TEI interrupt request Figure 13-6 Example of SCI Transmit Operation in Asynchronous Mode (8-Bit Data with Parity and 1 Stop Bit) 457 Receiving Serial Data (Asynchronous Mode): Figure 13-7 shows a sample flowchart for receiving serial data and indicates the procedure to follow. Initialize 1 Start receiving Read ORER, PER, and FER flags in SSR 2 PER ∨ RER ∨ ORER = 1? No Yes 3 Error handling (continued on next page) Read RDRF flag in SSR 4 No RDRF = 1? Yes Read receive data from RDR, and clear RDRF flag to 0 in SSR 1. SCI initialization: the receive data function of the RxD pin is selected automatically. 2., 3. Receive error handling and break detection: if a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After executing the necessary error handling, clear the ORER, PER, and FER flags all to 0. Receiving cannot resume if any of the ORER, PER, and FER flags remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 4. SCI status check and receive data read: read SSR, check that RDRF is set to 1, then read receive data from RDR and clear the RDRF flag to 0. Notification that the RDRF flag has changed from 0 to 1 can also be given by the RXI interrupt. 5. To continue receiving serial data: check the RDRF flag, read RDR, and clear the RDRF flag to 0 before the stop bit of the current frame is received. If the DMAC is activated by an RXI interrupt to read the RDR value, the RDRF flag is cleared automatically. No Finished receiving? Yes Clear RE bit to 0 in SCR End 5 Figure 13-7 Sample Flowchart for Receiving Serial Data (1) 458 3 Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? No Framing error handling Clear RE bit to 0 in SCR Yes No PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags to 0 in SSR End Figure 13-7 Sample Flowchart for Receiving Serial Data (2) 459 In receiving, the SCI operates as follows. • The SCI monitors the receive data line. When it detects a start bit, the SCI synchronizes internally and starts receiving. Receive data is stored in RSR in order from LSB to MSB. The parity bit and stop bit are received. • • After receiving, the SCI makes the following checks: — Parity check: The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in SMR. — Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit is checked. — Status check: The RDRF flag must be 0 so that receive data can be transferred from RSR into RDR. If these checks all pass, the RDRF flag is set to 1 and the received data is stored in RDR. If one of the checks fails (receive error), the SCI operates as indicated in table 13-11. Note: When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag is not set to 1. Be sure to clear the error flags. • When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt (RXI) is requested. If the ORER, PER, or FER flag is set to 1 and the RIE bit in SCR is also set to 1, a receive-error interrupt (ERI) is requested. Table 13-11 Receive Error Conditions Receive Error Overrun error Abbreviation ORER Condition Receiving of next data ends while RDRF flag is still set to 1 in SSR Stop bit is 0 Parity of receive data differs from even/odd parity setting in SMR Data Transfer Receive data not transferred from RSR to RDR Receive data transferred from RSR to RDR Receive data transferred from RSR to RDR Framing error Parity error FER PER 460 Figure 13-8 shows an example of SCI receive operation in asynchronous mode. 1 Start bit 0 Data D0 D1 D7 Parity Stop Start bit bit bit 0/1 1 0 Data D0 D1 D7 Parity Stop bit bit 0/1 1 1 Idle (mark) state RDRF FER RXI request 1 frame RXI interrupt handler reads data in RDR and clears RDRF flag to 0 Framing error, ERI request Figure 13-8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit) 13.3.3 Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial communication line. The processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by an ID. A serial communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their IDs. The receiving processor with a matching ID continues to receive further incoming data. Processors with IDs not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 13-9 shows an example of communication among different processors using a multiprocessor format. 461 Communication Formats: Four formats are available. Parity-bit settings are ignored when a multiprocessor format is selected. For details see table 13-8. Clock: See the description of asynchronous mode. Transmitting processor Serial communication line Receiving processor A (ID = 01) Receiving processor B (ID = 02) Receiving processor C (ID = 03) Receiving processor D (ID = 04) Serial data H'01 (MPB = 1) ID-sending cycle: receiving processor address H'AA (MPB = 0) Data-sending cycle: data sent to receiving processor specified by ID Legend MPB: Multiprocessor bit Figure 13-9 Example of Communication among Processors using Multiprocessor Format (Sending Data H'AA to Receiving Processor A) 462 Transmitting and Receiving Data Transmitting Multiprocessor Serial Data: Figure 13-10 shows a sample flowchart for transmitting multiprocessor serial data and indicates the procedure to follow. Initialize Start transmitting 1 Read TDRE flag in SSR TDRE = 1? Yes Write transmit data in TDR and set MPBT bit in SSR Clear TDRE flag to 0 No No 2 All data transmitted? Yes Read TEND flag in SSR 3 1. SCI initialization: the transmit data output function of the TxD pin is selected automatically. 2. SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit data in TDR. Also set the MPBT flag to 0 or 1 in SSR. Finally, clear the TDRE flag to 0. 3. To continue transmitting serial data: after checking that the TDRE flag is 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0. When the DMAC is activated by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically. 4. To output a break signal at the end of serial transmission: set the DDR bit to 1 and clear the DR bit to 0 (DDR and DR are I/O port registers), then clear the TE bit to 0 in SCR. TEND = 1? Yes Output break signal? Yes Clear DR bit to 0, set DDR bit to 1 Clear TE bit to 0 in SCR No No 4 End Figure 13-10 Sample Flowchart for Transmitting Multiprocessor Serial Data 463 In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts transmitting. If the TIE bit in SCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. • Serial transmit data is transmitted in the following order from the TxD pin: — — — — — • Start bit: Transmit data: Multiprocessor bit: Stop bit: Mark state: One 0 bit is output. 7 or 8 bits are output, LSB first. One multiprocessor bit (MPBT value) is output. One or two 1 bits (stop bits) are output. Output of 1 bits continues until the start bit of the next transmit data. The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI loads data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If the TDRE flag is 1, the SCI sets the TEND flag in SSR to 1, outputs the stop bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a transmit-end interrupt (TEI) is requested at this time. Figure 13-11 shows an example of SCI transmit operation using a multiprocessor format. Multiprocessor bit 1 Serial data Start bit 0 D0 D1 Data D7 0/1 Stop Start bit bit 1 0 D0 D1 Data D7 Multiprocessor bit Stop bit 0/1 1 1 Idle (mark) state TDRE TEND TXI request TXI interrupt handler writes data in TDR and clears TDRE flag to 0 1 frame TXI request TEI request Figure 13-11 Example of SCI Transmit Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit) 464 Receiving Multiprocessor Serial Data: Figure 13-12 shows a sample flowchart for receiving multiprocessor serial data and indicates the procedure to follow. Initialize Start receiving 1 Set MPIE bit to 1 in SCR 2 Read ORER and FER flags in SSR Yes FER ∨ PRER = 1 No Read RDRF flag in SSR No RDRF = 1? Yes Read receive data from RDR No Own ID? Yes Read ORER and FER flags in SSR 3 1. SCI initialization: the receive data function of the RxD pin is selected automatically. 2. ID receive cycle: set the MPIE bit to 1 in SCR. 3. SCI status check and ID check: read SSR, check that the RDRF flag is set to 1, then read data from RDR and compare with the processor’s own ID. If the ID does not match, set the MPIE bit to 1 again and clear the RDRF flag to 0. If the ID matches, clear the RDRF flag to 0. 4. SCI status check and data receiving: read SSR, check that the RDRF flag is set to 1, then read data from RDR. 5. Receive error handling and break detection: if a receive error occurs, read the ORER and FER flags in SSR to identify the error. After executing the necessary error handling, clear the ORER and FER flags both to 0. Receiving cannot resume while either the ORER or FER flag remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. FER ∨ ORER = 1 No Read RDRF flag in SSR Yes 4 No RDRF = 1? Yes Read receive data from RDR No No Finished receiving? Yes Clear RE bit to 0 in SCR End 5 Error handling (continued on next page) Figure 13-12 Sample Flowchart for Receiving Multiprocessor Serial Data (1) 465 5 Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? No Framing error handling Clear RE bit to 0 in SCR Yes Clear ORER, PER, and FER flags to 0 in SSR End Figure 13-12 Sample Flowchart for Receiving Multiprocessor Serial Data (2) 466 Figure 13-13 shows an example of SCI receive operation using a multiprocessor format. 1 Start bit 0 Data (ID1) MPB D7 1 Stop Start Data (data1) bit bit 1 0 MPB D7 0 Stop bit 1 1 D0 D1 D0 D1 Idle (mark) state MPIE RDRF RDR value RXI request RXI handler reads (multiprocessor RDR data and clears interrupt), MPIE = 0 RDRF flag to 0 ID1 Not own ID, so MPIE bit is set to 1 again No RXI request, RDR not updated a. Own ID does not match data 1 Start bit 0 Data (ID2) MPB D7 1 Stop Start Data (data2) bit bit 1 0 MPB D7 0 Stop bit 1 1 D0 D1 D0 D1 Idle (mark) state MPIE RDRF RDR value ID1 ID2 Data 2 RXI request RXI interrupt handler Own ID, so receiving MPIE bit is set (multiprocessor reads RDR data and continues, with data to 1 again interrupt), MPIE = 0 clears RDRF flag to 0 received by RXI interrupt handler b. Own ID matches data Figure 13-13 Example of SCI Receive Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit) 467 13.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 13-14 shows the general format in synchronous serial communication. Transfer direction One unit (character or frame) of serial data * Serial clock LSB Serial data Don’t care Note: * High except in continuous transmitting or receiving Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don’t care * Figure 13-14 Data Format in Synchronous Communication In synchronous serial communication, each data bit is placed on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rise of the serial clock. In each character, the serial data bits are transmitted in order from LSB (first) to MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In synchronous mode the SCI receives data by synchronizing with the rise of the serial clock. Communication Format: The data length is fixed at 8 bits. No parity bit or multiprocessor bit can be added. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected by clearing or setting the CKE1 bit in SCR. See table 13-9. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. When the SCI is only receiving, it receives in units of two characters, so it outputs 16 clock pulses. To receive in units of one character, an external clock source must be selected. 468 Transmitting and Receiving Data SCI Initialization (Synchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in SCR, then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing the TE bit to 0 sets the TDRE flag to 1 and initializes TSR. Clearing the RE bit to 0, however, does not initialize the RDRF, PER, FER, and ORE flags and RDR, which retain their previous contents. Figure 13-15 is a sample flowchart for initializing the SCI. Start of initialization Clear TE and RE bits to 0 in SCR Set RIE, TIE, TEIE, MPIE, CKE1, and CKE0 bits in SCR (leaving TE and RE bits cleared to 0) 1 1. Select the clock source in SCR. Clear the RIE, TIE, TEIE, MPIE, TE, and RE bits to 0. 2. Select the communication format in SMR. 3. Write the value corresponding to the bit rate in BRR. This step is not necessary when an external clock is used. 4. Wait for at least the interval required to transmit or receive one bit, then set the TE or RE bit to 1 in SCR. Also set the RIE, TIE, TEIE, and MPIE bits as necessary. Setting the TE or RE bit enables the SCI to use the TxD or RxD pin. 2 Select communication format in SMR 3 Set value in BRR Wait 1 bit interval elapsed? Yes Set TE or RE to 1 in SCR Set RIE, TIE, TEIE, and MPIE bits as necessary No 4 Start transmitting or receiving Figure 13-15 Sample Flowchart for SCI Initialization 469 Transmitting Serial Data (Synchronous Mode): Figure 13-16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. Initialize 1 Start transmitting Read TDRE flag in SSR 2 No TDRE = 1? Yes Write transmit data in TDR and clear TDRE flag to 0 in SSR 1. SCI initialization: the transmit data output function of the TxD pin is selected automatically. 2. SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0. 3. To continue transmitting serial data: after checking that the TDRE flag is 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0. When the DMAC is activated by a transmitdata-empty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically. All data transmitted? Yes No 3 Read TEND flag in SSR No TEND = 1? Yes Clear TE bit to 0 in SCR End Figure 13-16 Sample Flowchart for Serial Transmitting 470 In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data is output from the TxD pin in order from LSB (bit 0) to MSB (bit 7). • The SCI checks the TDRE flag when it outputs the MSB (bit 7). If the TDRE flag is 0, the SCI loads data from TDR into TSR and begins serial transmission of the next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, and after transmitting the MSB, holds the TxD pin in the MSB state. If the TEIE bit in SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. After the end of serial transmission, the SCK pin is held in a constant state. • • 471 Figure 13-17 shows an example of SCI transmit operation. Transmit direction Serial clock Serial data TDRE TEND TXI request Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TXI interrupt handler writes data in TDR and clears TDRE flag to 0 1 frame TXI request TEI request Figure 13-17 Example of SCI Transmit Operation 472 Receiving Serial Data: Figure 13-18 shows a sample flowchart for receiving serial data and indicates the procedure to follow. When switching from asynchronous mode to synchronous mode, make sure that the ORER, PER, and FER flags are cleared to 0. If the FER or PER flag is set to 1 the RDRF flag will not be set and both transmitting and receiving will be disabled. Initialize 1 1. Start receiving Read ORER flag in SSR 2 ORER = 1? No Yes 3 Error handling 4 Read RDRF flag in SSR No RDRF = 1? Yes Read receive data from RDR, and clear RDRF flag to 0 in SSR SCI initialization: the receive data function of the RxD pin is selected automatically. 2., 3. Receive error handling: if a receive error occurs, read the ORER flag in SSR, then after executing the necessary error handling, clear the ORER flag to 0. Neither transmitting nor receiving can resume while the ORER flag remains set to 1. 4. SCI status check and receive data read: read SSR, check that the RDRF flag is set to 1, then read receive data from RDR and clear the RDRF flag to 0. Notification that the RDRF flag has changed from 0 to 1 can also be given by the RXI interrupt. 5. To continue receiving serial data: check the RDRF flag, read RDR, and clear the RDRF flag to 0 before the MSB (bit 7) of the current frame is received. If the DMAC is activated by a receive-data-full interrupt request (RXI) to read RDR, the RDRF flag is cleared automatically. 5 No Finished receiving? Yes Clear RE bit to 0 in SCR End Figure 13-18 Sample Flowchart for Serial Receiving (1) 473 3 Error handling Overrun error handling Clear ORER flag to 0 in SSR End Figure 13-18 Sample Flowchart for Serial Receiving (2) In receiving, the SCI operates as follows. • • The SCI synchronizes with serial clock input or output and initializes internally. Receive data is stored in RSR in order from LSB to MSB. After receiving the data, the SCI checks that the RDRF flag is 0 so that receive data can be transferred from RSR to RDR. If this check passes, the RDRF flag is set to 1 and the received data is stored in RDR. If the check does not pass (receive error), the SCI operates as indicated in table 13-11. • After setting the RDRF flag to 1, if the RIE bit is set to 1 in SCR, the SCI requests a receivedata-full interrupt (RXI). If the ORER flag is set to 1 and the RIE bit in SCR is also set to 1, the SCI requests a receive-error interrupt (ERI). 474 Figure 13-19 shows an example of SCI receive operation. Receive direction Serial clock Serial data RDRF Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 ORER RXI request RXI interrupt handler reads data in RDR and clears RDRF flag to 0 1 frame RXI request Overrun error, ERI request Figure 13-19 Example of SCI Receive Operation Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 13-20 shows a sample flowchart for transmitting and receiving serial data simultaneously and indicates the procedure to follow. 475 Initialize Start transmitting and receiving 1 Read TDRE flag in SSR No TDRE = 1? Yes Write transmit data in TDR and clear TDRE flag to 0 in SSR 2 Read ORER flag in SSR Yes ORER = 1? 3 No Read RDRF flag in SSR No RDRF = 1? Yes Read receive data from RDR and clear RDRF flag to 0 in SSR Error handling 4 No End of transmitting and receiving? Yes Clear TE and RE bits to 0 in SCR 5 1. SCI initialization: the transmit data output function of the TxD pin and receive data input function of the RxD pin are selected, enabling simultaneous transmitting and receiving. 2. SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0. Notification that the TDRE flag has changed from 0 to 1 can also be given by the TXI interrupt. 3. Receive error handling: if a receive error occurs, read the ORER flag in SSR, then after executing the necessary error handling, clear the ORER flag to 0. Neither transmitting nor receiving can resume while the ORER flag remains set to 1. 4. SCI status check and receive data read: read SSR, check that the RDRF flag is 1, then read receive data from RDR and clear the RDRF flag to 0. Notification that the RDRF flag has changed from 0 to 1 can also be given by the RXI interrupt. 5. To continue transmitting and receiving serial data: check the RDRF flag, read RDR, and clear the RDRF flag to 0 before the MSB (bit 7) of the current frame is received. Also check that the TDRE flag is (bit 7) of the current frame is received. Also check that the TDRE flag is set to 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0 before the MSB (bit 7) of the current frame is transmitted. When the DMAC is activated by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically. When the DMAC is activated by a receivedata-full interrupt request (RXI) to read RDR, the RDRF flag is cleared automatically. End Note: * When switching from transmitting or receiving to simultaneous transmitting and receiving, clear the TE and RE bits both to 0, then set the TE and RE bits both to 1. Figure 13-20 Sample Flowchart for Serial Transmitting 476 13.4 SCI Interrupts The SCI has four interrupt request sources: TEI (transmit-end interrupt), ERI (receive-error interrupt), RXI (receive-data-full interrupt), and TXI (transmit-data-empty interrupt). Table 13-12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, TEIE, and RIE bits in SCR. Each interrupt request is sent separately to the interrupt controller. The TXI interrupt is requested when the TDRE flag is set to 1 in SSR. The TEI interrupt is requested when the TEND flag is set to 1 in SSR. The TXI interrupt request can activate the DMAC to transfer data. Data transfer by the DMAC automatically clears the TDRE flag to 0. The TEI interrupt request cannot activate the DMAC. The RXI interrupt is requested when the RDRF flag is set to 1 in SSR. The ERI interrupt is requested when the ORER, PER, or FER flag is set to 1 in SSR. The RXI interrupt request can activate the DMAC to transfer data. Data transfer by the DMAC automatically clears the RDRF flag to 0. The ERI interrupt request cannot activate the DMAC. DMAC channels in group 0 can be activated by interrupts from SCI channel 0. DMAC channels in group 1 can be activated by interrupts from SCI channel 1. Table 13-12 SCI Interrupt Sources Interrupt ERI RXI TXI TEI Description Receive error (ORER, FER, or PER) Receive data register full (RDRF) Transmit data register empty (TDRE) Transmit end (TEND) Low Priority High 477 13.5 Usage Notes Note the following points when using the SCI. TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of transmit data from TDR into TSR. The SCI sets the TDRE flag to 1 when it transfers data from TDR to TSR. Data can be written into TDR regardless of the state of the TDRE flag. If new data is written in TDR when the TDRE flag is 0, the old data stored in TDR will be lost because this data has not yet been transferred to TSR. Before writing transmit data in TDR, be sure to check that the TDRE flag is set to 1. Simultaneous Multiple Receive Errors: Table 13-13 indicates the state of SSR status flags when multiple receive errors occur simultaneously. When an overrun error occurs the RSR contents are not transferred to RDR, so receive data is lost. Table 13-13 SSR Status Flags and Transfer of Receive Data SSR Status Flags RDRF 1 0 0 1 1 0 1 Notes: ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 × × × Receive Data Transfer RSR → RDR × Receive Errors Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error : Receive data is transferred from RSR to RDR. × Receive data is not transferred from RSR to RDR. 478 Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again. Sending a Break Signal: When the TE bit is cleared to 0 the TxD pin becomes an I/O port, the level and direction (input or output) of which are determined by DR and DDR bits. This feature can be used to send a break signal. After the serial transmitter is initialized, the DR value substitutes for the mark state until the TE bit is set to 1 (the TxD pin function is not selected until the TE bit is set to 1). The DDR and DR bits should therefore both be set to 1 beforehand. To send a break signal during serial transmission, clear the DR bit to 0, then clear the TE bit to 0. When the TE bit is cleared to 0 the transmitter is initialized, regardless of its current state, so the TxD pin becomes an output port outputting the value 0. Receive Error Flags and Transmitter Operation (Synchronous Mode Only): When a receive error flag (ORER, PER, or FER) is set to 1 the SCI will not start transmitting, even if the TDRE flag is clear to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note that clearing the RE bit to 0 does not clear the receive error flags to 0. Receive Data Sampling Timing in Asynchronous Mode and Receive Margin: In asynchronous mode the SCI operates on a base clock with 16 times the bit rate frequency. In receiving, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. See figure 13-21. 479 16 clocks 8 clocks 0 Internal base clock 7 15 0 7 15 0 Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 13-21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as in equation (1). M = | (0.5 – M: N: D: L: F: 1 | D – 0.5 | ) – (L – 0.5) F – (1 + F) | × 100% ...................(1) 2N N Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute deviation of clock frequency From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation (2). D = 0.5, F = 0 1 M = (0.5 – ) × 100% 2 × 16 = 46.875%.................................................................................................(2) This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. 480 Restrictions on Usage of DMAC • When an external clock source is used for the serial clock, after the DMAC updates TDR, allow an interval of at least five system clock (ø) cycles before input of the serial clock to start transmitting. If the serial clock is input within four states of the TDR update, a malfunction may occur. (See figure 13-22.) To have the DMAC read RDR, be sure to select the SCI receive-data-full interrupt (RXI) as the activation source with bits DTS2 to DTS0 in DTCR. • SCK t TDRE D0 D1 D2 D3 D4 D5 D6 D7 Note: In operation with an external clock source, be sure to be t > 4 states. Figure 13-22 Synchronous Transmission Using DMAC (Example) 481 482 Section 14 A/D Converter 14.1 Overview The H8/3003 includes a 10-bit successive-approximations A/D converter with a selection of up to eight analog input channels. 14.1.1 Features A/D converter features are listed below. • • • 10-bit resolution Eight input channels Selectable analog conversion voltage range The analog voltage conversion range can be programmed by input of an analog reference voltage at the VREF pin. • High-speed conversion Conversion time: maximum 8.4 µs per channel (with 16 MHz system clock) • Two conversion modes Single mode: A/D conversion of one channel Scan mode: continuous conversion on one to four channels • Four 16-bit data registers A/D conversion results are transferred for storage into data registers corresponding to the channels. • • • Sample-and-hold function A/D conversion can be externally triggered A/D interrupt requested at end of conversion At the end of A/D conversion, an A/D end interrupt (ADI) can be requested. 483 14.1.2 Block Diagram Figure 14-1 shows a block diagram of the A/D converter. Module data bus Bus interface ADDRC ADDRD ADDRA ADDRB ADCSR + – Analog multiplexer Comparator Control circuit Sample-andhold circuit ADCR On-chip data bus AVCC V REF AV SS 10-bit D/A AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 Successiveapproximations register ø/8 ø/16 ADI ADTRG Legend ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D Figure 14-1 A/D Converter Block Diagram 484 14.1.3 Input Pins Table 14-1 summarizes the A/D converter’s input pins. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the power supply for the analog circuits in the A/D converter. VREF is the A/D conversion reference voltage. Table 14-1 A/D Converter Pins Pin Name Analog power supply pin Analog ground pin Reference voltage pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin Abbreviation I/O AVCC AVSS VREF AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG Input Input Input Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Group 1 analog inputs Function Analog power supply Analog ground and reference voltage Analog reference voltage Group 0 analog inputs 485 14.1.4 Register Configuration Table 14-2 summarizes the A/D converter’s registers. Table 14-2 A/D Converter Registers Address*1 H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 Name A/D data register A (high) A/D data register A (low) A/D data register B (high) A/D data register B (low) A/D data register C (high) A/D data register C (low) A/D data register D (high) A/D data register D (low) A/D control/status register A/D control register Abbreviation ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR R/W R R R R R R R R R/(W)*2 R/W Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'7E Notes: 1. Lower 16 bits of the address 2. Only 0 can be written in bit 7, to clear the flag. 486 14.2 Register Descriptions 14.2.1 A/D Data Registers A to D (ADDRA to ADDRD) Bit ADDRn Initial value Read/Write (n = A to D) 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R 0 — 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — A/D conversion data 10-bit data giving an A/D conversion result Reserved bits The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion. An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D data register are reserved bits that always read 0. Table 14-3 indicates the pairings of analog input channels and A/D data registers. The CPU can always read and write the A/D data registers. The upper byte can be read directly, but the lower byte is read through a temporary register (TEMP). For details see section 14.3, CPU Interface. The A/D data registers are initialized to H'0000 by a reset and in standby mode. Table 14-3 Analog Input Channels and A/D Data Registers Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD 487 14.2.2 A/D Control/Status Register (ADCSR) Bit Initial value Read/Write 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Channel select 2 to 0 These bits select analog input channels Clock select Selects the A/D conversion time Scan mode Selects single mode or scan mode A/D start Starts or stops A/D conversion A/D interrupt enable Enables and disables A/D end interrupts A/D end flag Indicates end of A/D conversion Note: * Only 0 can be written, to clear the flag. ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter. ADCSR is initialized to H'00 by a reset and in standby mode. 488 Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7 ADF 0 1 Description [Clearing condition] Cleared by reading ADF while ADF = 1, then writing 0 in ADF [Setting conditions] Single mode: A/D conversion ends Scan mode: A/D conversion ends in all selected channels (Initial value) Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Bit 6 ADIE 0 1 Description A/D end interrupt request (ADI) is disabled A/D end interrupt request (ADI) is enabled (Initial value) Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin. Bit 5 ADST 0 1 Description A/D conversion is stopped (Initial value) Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends. Scan mode: A/D conversion starts and continues, cycling among the selected channels, until ADST is cleared to 0 by software, by a reset, or by a transition to standby mode. 489 Bit 4—Scan Mode (SCAN): Selects single mode or scan mode. For further information on operation in these modes, see section 14.4, Operation. Clear the ADST bit to 0 before switching the conversion mode. Bit 4 SCAN 0 1 Description Single mode Scan mode (Initial value) Bit 3—Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before switching the conversion time. Bit 3 CKS 0 1 Description Conversion time = 266 states (maximum) Conversion time = 134 states (maximum) (Initial value) Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection. Group Selection CH2 0 CH1 0 Channel Selection CH0 0 1 1 0 1 1 0 0 1 1 0 1 Single Mode AN0 (Initial value) AN1 AN2 AN3 AN4 AN5 AN6 AN7 Description Scan Mode AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 490 14.2.3 A/D Control Register (ADCR) Bit Initial value Read/Write 7 TRGE 0 R/W 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — Reserved bits Trigger enable Enables or disables external triggering of A/D conversion 2 — 1 — 1 — 1 — 0 — 1 — ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion. ADCR is initialized to H'7F by a reset and in standby mode. Bit 7—Trigger Enable (TRGE): Enables or disables external triggering of A/D conversion. Bit 7 TRGE 0 1 Description A/D conversion cannot be externally triggered (Initial value) A/D conversion starts at the falling edge of the external trigger signal (ADTRG) Bits 6 to 0—Reserved: Read-only bits, always read as 1. 491 14.3 CPU Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read through an 8-bit temporary register (TEMP). An A/D data register is read as follows. When the upper byte is read, the upper-byte value is transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading an A/D data register, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 14-2 shows the data flow for access to an A/D data register. Upper-byte read CPU (H'AA) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Lower-byte read CPU (H'40) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Figure 14-2 A/D Data Register Access Operation (Reading H'AA40) 492 14.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 14.4.1 Single Mode (SCAN = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when conversion ends. When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF. When the mode or analog input channel must be switched during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the mode or channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 14-3 shows a timing diagram for this example. 1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). When A/D conversion is completed, the result is transferred into ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. The A/D interrupt handling routine starts. The routine reads ADCSR, then writes 0 in the ADF flag. The routine reads and processes the conversion result (ADDRB). Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps 2 to 7 are repeated. 2. 3. 4. 5. 6. 7. 493 Set * ADIE A/D conversion starts Clear * Clear * Set * Set * ADST ADF Idle State of channel 0 (AN 0) Idle A/D conversion 1 State of channel 1 (AN 1) Idle A/D conversion 2 Idle State of channel 2 (AN 2) Idle Idle Figure 14-3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Read conversion result A/D conversion result 1 Read conversion result A/D conversion result 2 494 State of channel 3 (AN 3) ADDRA ADDRB ADDRC ADDRD Note: * Vertical arrows ( ) indicate instructions executed by software. 14.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data registers corresponding to the channels. When the mode or analog input channel selection must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are described next. Figure 14-4 shows a timing diagram for this example. 1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). When A/D conversion of the first channel (AN0) is completed, the result is transferred into ADDRA. Next, conversion of the second channel (AN1) starts automatically. Conversion proceeds in the same way through the third channel (AN2). When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI interrupt is requested at this time. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). 2. 3. 4. 5. 495 Continuous A/D conversion Set *1 Clear*1 ADST Clear* 1 A/D conversion time Idle A/D conversion 1 ADF Idle A/D conversion 4 Idle State of channel 0 (AN 0) Idle A/D conversion 2 Idle A/D conversion 5 *2 State of channel 1 (AN 1) Idle A/D conversion 3 Idle Idle State of channel 2 (AN 2) Idle Transfer A/D conversion result 1 Figure 14-4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) A/D conversion result 4 A/D conversion result 2 A/D conversion result 3 496 State of channel 3 (AN 3) ADDRA ADDRB ADDRC ADDRD Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. 14.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 14-5 shows the A/D conversion timing. Table 14-4 indicates the A/D conversion time. As indicated in figure 14-5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 14-4. In scan mode, the values given in table 14-4 apply to the first conversion. In the second and subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states when CKS = 1. (1) ø Address bus (2) Write signal Input sampling timing ADF tD t SPL t CONV Legend (1): ADCSR write cycle (2): ADCSR address tD : Synchronization delay t SPL : Input sampling time t CONV: A/D conversion time Figure 14-5 A/D Conversion Timing 497 Table 14-4 A/D Conversion Time (Single Mode) CKS = 0 Symbol Synchronization delay Input sampling time A/D conversion time tD tSPL tCONV Min 10 — 259 Typ — 80 — Max 17 — 266 Min 6 — 131 CKS = 1 Typ — 40 — Max 9 — 134 Note: Values in the table are numbers of states. 14.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR, external trigger input is enabled at the ADTRG pin. A high-to-low transition at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit had been set to 1 by software. Figure 14-6 shows the timing. ø ADTRG Internal trigger signal ADST A/D conversion Figure 14-6 External Trigger Input Timing 498 14.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. 14.6 Usage Notes When using the A/D converter, note the following points: Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input pins ANn should be in the range AVSS ≤ ANn ≤ VREF. (n = 0 to 7) AVCC and AVSS Input Voltages: AVSS should have the following values: AVSS = VSS. If the A/D converter is not used, the values should be AVCC = VCC and AVSS = VSS. VREF Input Range: The analog reference voltage input at the VREF pin should be in the range VREF ≤ AVCC. If the A/D converter is not used, the value should be VREF = VCC. 499 500 Section 15 RAM 15.1 Overview The H8/3003 has 512 bytes of on-chip static RAM. The RAM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, making the RAM suitable for rapid data transfer. The on-chip RAM is assigned to addresses H'FFD10 to H'FFF0F in modes 1 and 2, and addresses H'FFFD10 to H'FFFF0F in modes 3 and 4. The RAM enable bit (RAME) in the system control register (SYSCR) can enable or disable the on-chip RAM. 15.1.1 Block Diagram Figure 15-1 shows a block diagram of the on-chip RAM. On-chip data bus (upper 8 bits) On-chip data bus (lower 8 bits) Bus interface H'FD10* H'FD12 On-chip RAM H'FD11* H'FD13* H'FF0E* Even addresses Note: * Lower 16 bits of the address H'FF0F* Odd addresses Figure 15-1 RAM Block Diagram 501 15.1.2 Register Configuration The on-chip RAM is controlled by the system control register (SYSCR). Table 15-1 gives the address and initial value of SYSCR. Table 15-1 RAM Control Register Address* H'FFF2 Name System control register Abbreviation SYSCR R/W R/W Initial Value H'0B Note: * Lower 16 bits of the address 502 15.2 System Control Register (SYSCR) Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W 2 NMIEG 0 R/W 1 — 1 — 0 RAME 1 R/W RAM enable bit Enables or disables on-chip RAM Reserved bit NMI edge select User bit enable Standby timer select 2 to 0 Software standby One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3, System Control Register. Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized at the rising edge of the input at the RES pin. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) 503 15.3 Operation When the RAME bit is set to 1, accesses to addresses H'FFD10 to H'FFF0F in modes 1 and 2, and to addresses H'FFFD10 to H'FFFF0F in modes 3 and 4, are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written and read by word access. It can also be written and read by byte access. Byte data is accessed in two states using the upper 8 bits of the data bus. Word data starting at an even address is accessed in two states using all 16 bits of the data bus. 504 Section 16 Clock Pulse Generator 16.1 Overview The H8/3003 has a built-in clock pulse generator (CPG) that generates the system clock (ø) and other internal clock signals (ø/2 to ø/4096). The H8/3003 is available in a clock-halving version and a 1:1 version, which have different clock pulse generator configurations. The clock pulse generator of the clock-halving version consists of an oscillator circuit, a system clock divider, and prescalers for the on-chip supporting modules. The clock pulse generator of the 1:1 version consists of an oscillator circuit, a duty adjustment circuit, and the prescalers. 16.1.1 Block Diagram Figure 16-1 shows block diagrams of the clock pulse generator. CPG XTAL Oscillator EXTAL Frequency divider (1/2) Prescalers ø ø/2 to ø/4096 a. Clock pulse generator of clock-halving version CPG XTAL Oscillator EXTAL Duty adjustment circuit Prescalers ø b. Clock pulse generator of 1:1 version ø/2 to ø/4096 Figure 16-1 Block Diagram of Clock Pulse Generator 505 16.2 Oscillator Circuit Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock signal. 16.2.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as in the example in figure 16-2. The damping resistance Rd should be selected according to table 16-1. An AT-cut parallelresonance crystal should be used. C L1 EXTAL XTAL C L2 C L1 = C L2 = 10 pF to 22 pF Figure 16-2 Connection of Crystal Resonator (Example) Table 16-1 Damping Resistance Value Frequency (MHz) Rd (Ω) 2 1k 4 500 8 200 10 70 12 0 16 0 20 0 24 0 Crystal Resonator: Figure 16-3 shows an equivalent circuit of the crystal resonator. The crystal resonator should have the characteristics listed in table 16-2. CL L XTAL Rs EXTAL CO AT-cut parallel-resonance type Figure 16-3 Crystal Resonator Equivalent Circuit 506 Table 16-2 Crystal Resonator Parameters Frequency (MHz) Rs max (Ω) Co (pF) 2 500 4 120 8 80 10 70 12 60 7 pF max 16 50 20 40 24 40 Clock-Halving Version: Use a crystal resonator with a frequency equal to twice the system clock frequency (ø). 1:1 Version: Use a crystal resonator with a frequency equal to the system clock frequency (ø). Notes on Board Design: When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 16-4. When the board is designed, the crystal resonator and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins. Avoid C L2 Signal A Signal B H8/3003 XTAL EXTAL C L1 Figure 16-4 Example of Incorrect Board Design 507 16.2.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 16-5. In example b, the clock should be held high in standby mode. If the XTAL pin is left open, the stray capacitance should be 10 pF. EXTAL External clock input XTAL Open a. XTAL pin left open EXTAL External clock input XTAL 74HC04 b. Complementary clock input at XTAL pin Figure 16-5 External Clock Input (Examples) 508 External Clock • Clock-halving version The external clock signal should have a frequency equal to twice the system clock frequency (ø) and a duty cycle of 40% to 60%. • 1:1 version The external clock frequency should be equal to the system clock frequency (ø). Table 16-3 and figure 16-6 indicate the clock timing. Table 16-3 Clock Timing VCC = 2.7 to 5.5 V VCC = 5.0 V ± 10% Item External clock rise time External clock fall time External clock input duty (a/tcyc) ø clock width duty (b/tcyc) Symbol tEXr tEXf Min — — 30 40 — 40 Max 10 10 70 60 60 Min — — 30 40 40 Max 5 5 70 60 60 Unit Test Conditions ns ns % % % ø ≥ 5 MHz ø < 5 MHz Figure 16-6 — tcyc a EXTAL VCC × 0.5 tEXr tEXf t cyc b Ø VCC × 0.5 Figure 16-6 External Clock Input Timing 509 16.3 System Clock Divider (Clock-Halving Version) The system clock divider divides the oscillator output by 2 to generate the system clock (ø). 16.4 Duty Adjustment Circuit (1:1 Version) When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate a system clock (ø). 16.5 Prescalers The prescalers divide the system clock (ø) to generate internal clocks (ø/2 to ø/4096). 510 Section 17 Power-Down State 17.1 Overview The H8/3003 has a power-down state that greatly reduces power consumption by halting CPU functions. The power-down state includes the following three modes: • • • Sleep mode Software standby mode Hardware standby mode Table 17-1 indicates the methods of entering and exiting these power-down modes and the status of the CPU and on-chip supporting modules in each mode. Table 17-1 Power-Down State State Mode Sleep mode Entering Conditions Clock CPU CPU Refresh Supporting Registers DMAC Controller Functions RAM Active Active Active Held I/O Ports Held Exiting Conditions • Interrupt • RES • STBY • • • • NMI IRQ0 to IRQ2 RES STBY SLEEP instruc- Active tion executed while SSBY = 0 in SYSCR Halted Held Software standby mode SLEEP instruc- Halted Halted Held tion executed while SSBY = 1 in SYSCR Halted Halted Undeter mined Halted Halted and and reset held*1 Halted Halted and and reset reset Halted and reset Halted and reset Held Held Hardware Low input at standby STBY pin mode Held*2 High • STBY impedance • RES Notes: 1. The refresh timer counter (RTCNT) and bits 7 and 6 of the refresh timer control/status register (RTMCSR) are initialized. Other bits and registers hold their previous states. 2. The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state to hardware standby mode. Legend SYSCR: System control register SSBY: Software standby bit 511 17.2 Register Configuration The H8/3003’s system control register (SYSCR) controls the power-down state. Table 17-2 summarizes this register. Table 17-2 Control Register Address* H'FFF2 Name System control register Abbreviation SYSCR R/W R/W Initial Value H'0B Note: * Lower 16 bits of the address. 17.2.1 System Control Register (SYSCR) Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W 2 NMIEG 0 R/W 1 — 1 — 0 RAME 1 R/W RAM enable Reserved bit NMI edge select User bit enable Standby timer select 2 to 0 These bits select the waiting time at exit from software standby mode Software standby Enables transition to software standby mode SYSCR is an 8-bit readable/writable register. Bit 7 (SSBY) and bits 6 to 4 (STS2 to STS0) control the power-down state. For information on the other SYSCR bits, see section 3.3, System Control Register. 512 Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal operation. To clear this bit, write 0. Bit 7 SSBY 0 1 Description SLEEP instruction causes transition to sleep mode SLEEP instruction causes transition to software standby mode (Initial value) Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the clock to settle when software standby mode is exited by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to the clock frequency so that the waiting time will be at least 8 ms. See table 17-3. If an external clock is used, any setting is permitted. Bit 6 STS2 0 Bit 5 STS1 0 Bit 4 STS0 0 1 1 0 1 1 0 1 — — Description Waiting time = 8192 states Waiting time = 16384 states Waiting time = 32768 states Waiting time = 65536 states Waiting time = 131072 states Waiting time = 4 states* (Initial value) Note: * Do not use this setting for the 1:1 clock version. 513 17.3 Sleep Mode 17.3.1 Transition to Sleep Mode When the SSBY bit is cleared to 0 in the system control register (SYSCR), execution of the SLEEP instruction causes a transition from the program execution state to sleep mode. Immediately after executing the SLEEP instruction the CPU halts, but the contents of its internal registers are retained. The DMA controller (DMAC), refresh controller, and on-chip supporting modules do not halt in sleep mode. 17.3.2 Exit from Sleep Mode Sleep mode is exited by an interrupt, or by input at the RES or STBY pin. Exit by Interrupt: An interrupt terminates sleep mode and causes a transition to the interrupt exception handling state. Sleep mode is not exited by an interrupt source in an on-chip supporting module if the interrupt is disabled in the on-chip supporting module. Sleep mode is not exited by an interrupt other than NMI if the interrupt is masked by IPR and the I and UI bits in CCR. Exit by RES Input: Low input at the RES pin exits from sleep mode to the reset state. Exit by STBY Input: Low input at the STBY pin exits from sleep mode to hardware standby mode. 514 17.4 Software Standby Mode 17.4.1 Transition to Software Standby Mode To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in SYSCR. In software standby mode, current dissipation is reduced to an extremely low level because the CPU, clock, and on-chip supporting modules all halt. The DMAC and on-chip supporting modules are reset. As long as the specified voltage is supplied, however, CPU register contents and on-chip RAM data are retained. The settings of the I/O ports and refresh controller* are also held. Note: * The refresh timer counter (RTCNT) and bits 7 and 6 of the refresh timer control/status register (RTMCSR) are initialized. Other bits and registers hold their previous states. 17.4.2 Exit from Software Standby Mode Software standby mode can be exited by input of an external interrupt at the NMI, IRQ0, IRQ1, or IRQ2 pin, or by input at the RES or STBY pin. Exit by Interrupt: When an NMI, IRQ0, IRQ1, or IRQ2 interrupt request signal is received, the clock oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0 in SYSCR, stable clock signals are supplied to the entire H8/3003 chip, software standby mode ends, and interrupt exception handling begins. Software standby mode is not exited if the interrupt enable bits of interrupts IRQ0, IRQ1, and IRQ2 are cleared to 0, or if these interrupts are masked in the CPU. Exit by RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are supplied immediately to the entire H8/3003 chip. The RES signal must be held low long enough for the clock oscillator to stabilize. When RES goes high, the CPU starts reset exception handling. Exit by STBY Input: Low input at the STBY pin causes a transition to hardware standby mode. 515 17.4.3 Selection of Waiting Time for Exit from Software Standby Mode Bits STS2 to STS0 in SYSCR should be set as follows. Crystal Resonator: Set STS2 to STS0 so that the waiting time (for the clock to stabilize) is at least 8 ms. Table 17-3 indicates the waiting times that are selected by STS2 to STS0 settings at various system clock frequencies. External Clock: Any value may be set in the clock-halving version. Normally the minimum value (STS2 = STS1 = STS0 = 1) is recommended. In the 1:1 clock version, any value other than the minimum value may be set. Table 17-3 Clock Frequency and Waiting Time for Clock to Settle Waiting STS2 STS1 STS0 Time 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 — — 8192 states 16384 states 32768 states 65536 states 131072 states 16 MHZ 12 MHz 10 MHz 8 MHz 0.51 1.0 2.0 4.1 8.2 0.65 1.3 2.7 5.5 10.9 0.33 0.8 1.6 3.3 6.6 13.1 0.4 1.0 2.0 4.1 8.2 16.4 0.5 6 MHz 1.3 2.7 5.5 10.9 21.8 0.67 4 MHz 2.0 4.1 8.2 16.4 32.8 1.0 2 MHz 4.1 8.2 16.4 32.8 65.5 2.0 µs Unit ms 4 states* 0.25 : Recommended setting Note: * This setting cannot be used in the 1:1 clock version. 516 17.4.4 Sample Application of Software Standby Mode Figure 17-1 shows an example in which software standby mode is entered at the fall of NMI and exited at the rise of NMI. With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an NMI interrupt occurs. Next the NMIEG bit is set to 1 (selecting the rising edge) and the SSBY bit is set to 1; then the SLEEP instruction is executed to enter software standby mode. Software standby mode is exited at the next rising edge of the NMI signal . Clock oscillator ø NMI NMIEG SSBY NMI interrupt handler NMIEG = 1 SSBY = 1 Software standby mode (powerdown state) Oscillator settling time (tosc2) NMI exception handling SLEEP instruction Figure 17-1 NMI Timing for Software Standby Mode (Example) 17.4.5 Note The I/O ports retain their existing states in software standby mode. If a port is in the high output state, its output current is not reduced. 517 17.5 Hardware Standby Mode 17.5.1 Transition to Hardware Standby Mode Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin goes low. Hardware standby mode reduces power consumption drastically by halting all functions of the CPU, DMAC, refresh controller, and on-chip supporting modules. All modules are reset except the on-chip RAM. As long as the specified voltage is supplied, on-chip RAM data is retained*. I/O ports are placed in the high-impedance state. The inputs at the mode pins (MD2 to MD0) should not be changed during hardware standby mode. Note: * Clear the RAME bit to 0 in SYSCR before STBY goes low to retain on-chip RAM data. 17.5.2 Exit from Hardware Standby Mode Hardware standby mode is exited by inputs at the STBY and RES pins. While RES is low, when STBY goes high, the clock oscillator starts running. RES should be held low long enough for the clock oscillator to settle. When RES goes high, reset exception handling begins, followed by a transition to the program execution state. 17.5.3 Timing for Hardware Standby Mode Figure 17-2 shows the timing relationships for hardware standby mode. To enter hardware standby mode, first drive RES low, then drive STBY low. To exit hardware standby mode, first drive STBY high, wait for the clock to settle, then bring RES from low to high. Clock oscillator RES STBY Oscillator settling time Reset exception handling Figure 17-2 Hardware Standby Mode Timing 518 Section 18 Electrical Characteristics 18.1 Absolute Maximum Ratings Table 18-1 lists the absolute maximum ratings. Table 18-1 Absolute Maximum Ratings Item Power supply voltage Input voltage (except port 7) Input voltage (port 7) Reference voltage Analog power supply voltage Analog input voltage Operating temperature Storage temperature Symbol VCC VIN VIN VREF AVCC VAN Topr Tstg Value –0.3 to +7.0 –0.3 to VCC +0.3 –0.3 to AVCC +0.3 –0.3 to AVCC +0.3 –0.3 to +7.0 –0.3 to AVCC +0.3 Regular specifications: –20 to +75 Wide-range specifications: –40 to +85 –55 to +125 Unit V V V V V V °C °C °C Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. 519 18.2 Electrical Characteristics 18.2.1 DC Characteristics Table 18-2 lists the DC characteristics. Table 18-3 lists the permissible output currents. Table 18-2 DC Characteristics Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC, VSS = AVSS = 0 V*, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Schmitt trigger input voltages Input high voltage Port A, P80 to P82, PB0 to PB3 RES, STBY, NMI, MD2 to MD0 EXTAL Port 7 Ports 4, 5, 6, 9, C, P83, P84, PB4 to PB7, D15 to D8 Input low voltage RES, STBY, MD2 to MD0 NMI, EXTAL, ports 4, 5, 6, 7, 9, C, P83, P84, PB4 to PB7, D15 to D8 Output high voltage All output pins VOH VIL Symbol VT VT – + + – Min 1.0 — 0.4 Typ — — — Max — Unit Test Conditions V VCC × 0.7 V — V VCC + 0.3 V VT – VT VIH VCC – 0.7 — VCC × 0.7 — 2.0 2.0 — — VCC + 0.3 V AVCC + 0.3 V VCC + 0.3 V –0.3 –0.3 — — 0.5 0.8 V V VCC – 0.5 — 3.5 — — — V V IOH = –200 µA IOH = –1 mA Note: * If the A/D converter is not used, do not leave the AVCC, AVSS, and VREF pins open. Connect AVCC and VREF to VCC, and connect AVSS to VSS. 520 Table 18-2 DC Characteristics (cont) Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC , VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Output low voltage Symbol All output pins VOL (except RESO) Ports 5 and B, A19 to A0 RESO Input leakage STBY, NMI, current RES, MD2 to MD0 Port 7 Three-state leakage current (off state) Ports 4, 5, 6, 8 to C, A19 to A0, D15 to D8 RESO –IP CIN |ITS1| |IIN| Min — — — — Typ — — — — Max 0.4 1.0 0.4 1.0 Unit V V V µA Test Conditions IOL = 1.6 mA IOL = 10 mA IOL = 2.6 mA VIN = 0.5 to VCC – 0.5 V VIN = 0.5 to AVCC – 0.5 V VIN = 0.5 to VCC – 0.5 V VIN = 0.5 to VCC – 0.5 V VIN = 0 V VIN = 0 V f = 1 MHz Ta = 25°C f = 10 MHz f = 12 MHz f = 16 MHz f = 10 MHz f = 12 MHz f = 16 MHz Ta ≤ 50°C 50°C < Ta — — — — 1.0 1.0 µA µA — 50 — — ICC — — — — — — — — — — 35 40 50 25 30 35 0.01 — 10.0 300 50 15 55 65 80 40 45 60 5.0 20.0 µA µA pF Input pull-up Ports 4 and 5 current Input NMI capacitance All input pins except NMI Current Normal dissipation*2 operation mA mA mA mA mA mA µA µA Sleep mode Standby mode*3 — — Notes: 1. If the A/D converter is not used, do not leave the AVCC, AVSS, and VREF pins open. Connect AVCC and VREF to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIHmin = VCC – 0.5 V and VILmax = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM ≤ VCC < 4.5 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V. 521 Table 18-2 DC Characteristics (cont) Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Analog power During A/D supply current conversion Idle Reference current During A/D conversion Idle RAM standby voltage VRAM AICC Symbol AICC Min — — — — 2.0 Typ 1.2 0.01 0.3 0.01 — Max 2.0 5.0 0.6 5.0 — Unit Test Conditions mA µA mA µA V VREF = 5.0 V Notes: 1. If the A/D converter is not used, do not leave the AVCC, AVSS, and VREF pins open. Connect AVCC and VREF to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIHmin = VCC – 0.5 V and VILmax = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM < VCC < 4.5 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V. Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V*, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Schmitt trigger input voltages Input high voltage Port A, P80 to P82, PB0 to PB3 RES, STBY, NMI, MD2 to MD0 EXTAL Port 7 Ports 4, 5, 6, 9, C, P83, P84, PB4 to PB7, D15 to D8 Symbol VT– VT+ VIH Min VCC × 0.2 — VCC × 0.9 Typ — — Max — VCC × 0.7 — VCC + 0.3 Unit Test Conditions V V V V VT+ – VT– VCC × 0.07 — — VCC × 0.7 VCC × 0.7 VCC × 0.7 — — — VCC + 0.3 VCC + 0.3 V AVCC + 0.3 V V Note: * If the A/D converter is not used, do not leave the AVCC, AVSS, and VREF pins open. Connect AVCC and VREF to VCC, and connect AVSS to VSS. 522 Table 18-2 DC Characteristics (cont) Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V*, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Input low voltage RES, STBY, MD2 to MD0 NMI, EXTAL, ports 4, 5, 6, 7, 9, C, P83, P84 PB4 to PB7, D15 to D8 Output high voltage All output pins VOH Symbol VIL Min –0.3 –0.3 Typ — — Max VCC × 0.1 VCC × 0.2 Unit Test Conditions V V VCC < 4.0 V 0.8 VCC – 0.5 — VCC – 1.0 — 3.5 — — — — — — 0.4 1.0 V V V V V V VCC = 4.0 to 5.5 V IOH = –200 µA VCC ≤ 4.5 V IOH = –1 mA. 4.5 V < VCC ≤ 5.5 V IOH = –1 mA IOL = 1.6 mA VCC ≤ 4 V IOL = 8 mA, 4 V < VCC ≤ 5.5 V IOL = 10 mA IOL = 2.6 mA VIN = 0.5 to VCC – 0.5 V VIN = 0.5 to AVCC – 0.5 V VIN = 0.5 to VCC – 0.5 V VIN = 0.5 to VCC – 0.5 V VCC = 2.7 V to 5.5 V, VIN = 0 V Output low voltage All output pins VOL (except RESO) Ports 5 and B, A19 to A0 — — RESO Input leakage STBY, NMI, current RES, MD2 to MD0 Port 7 Three-state leakage current (off state) Ports 4, 5, 6, 8 to C, A19 to A0, D15 to D8 RESO –IP |ITS1| |IIN| — — — — 0.4 1.0 V µA — — — — 1.0 1.0 µA µA — 10 — — 10.0 300 µA µA Input pull-up Ports 4 and 5 current Note: * If the A/D converter is not used, do not leave the AVCC, AVSS, and VREF pins open. Connect AVCC and VREF to VCC, and connect AVSS to VSS. 523 Table 18-2 DC Characteristics (cont) Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Input capacitance NMI All input pins except NMI Normal operation Sleep mode Standby mode*3 Analog power During A/D supply current conversion Idle Reference current During A/D conversion Idle RAM standby voltage VRAM AICC AICC ICC*4 Symbol CIN Min — — — — — — — — — — — — 2.0 Typ — — 30 (5.0 V) 20 (5.0 V) 0.01 — 1.0 1.2 0.01 0.2 0.3 0.01 — Max 50 15 36.2 (5.5 V) 27.4 (5.5 V) 5.0 20.0 2.0 — 5.0 0.4 — 5.0 — mA mA µA µA mA mA µA mA mA µA V VREF = 3.0 V VREF = 5.0 V Unit Test Conditions pF VIN = 0 V f = 1 MHz Ta = 25°C f = 8 MHz f = 8 MHz Ta ≤ 50°C 50°C < Ta AVCC = 3.0 V AVCC = 5.0 V Current dissipation*2 Notes: 1. If the A/D converter is not used, do not leave the AVCC, AVSS, and VREF pins open. Connect AVCC and VREF to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIHmin = VCC – 0.5 V and VILmax = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM ≤ VCC < 2.7 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V. 4. ICC depends on VCC and f as follows: ICCmax = 1.0 (mA) + 0.8 (mA/MHz · V) × VCC × f [normal mode] ICCmax = 1.0 (mA) + 0.6 (mA/MHz · V) × VCC × f [sleep mode] 524 Table 18-2 DC Characteristics (cont) Conditions: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (normalspecification product), Ta = –40°C to +85°C (extended temperature range specification product) Item Port A, Schmitt trigger input P80 to P82, voltage PB0 to PB3 Input high voltage RES, STBY, NMI, MD2 to MD0 EXTAL Port 7 Ports 4, 5, 6, 9, C, P83, P84, PB4 to PB7, D15 to D8 Input low voltage RES, STBY, MD2 to MD0 NMI, EXTAL, Ports 4, 5, 6, 7, 9, C, P83, P84, PB4 to PB7, D15 to D8 Output high All output pins voltage VOH VIL Symbol VT– VT+ VIH Min Typ Max — VCC × 0.7 — VCC + 0.3 Unit Test Conditions V V V V VCC × 0.2 — — — VT+ – VT– VCC × 0.07 — VCC × 0.9 — VCC × 0.7 — VCC × 0.7 — VCC × 0.7 — VCC + 0.3 VCC + 0.3 V AVCC + 0.3 V V –0.3 –0.3 — — VCC × 0.1 VCC × 0.2 0.8 V V VCC < 4.0 V VCC = 4.0 to 5.5 V VCC – 0.5 — VCC – 1.0 — 3.5 — — — — — — 0.4 1.0 V V V V V IOH = –200 µA VCC ≤ 4.5 V IOH = –1 mA 4.5 V < VCC ≤ 5.5 V IOH = –1 mA IOL = 1.6 mA VCC ≤ 4.0 V, IOL = 8 mA, 4.0 V < VCC ≤ 5.5 V, IOL = 10 mA IOL = 2.6 mA VIN = 0.5 to VCC – 0.5 V VIN = 0.5 to AVCC – 0.5 V Output low voltage All output pins (except RESO) Ports 5 and B, A19 to A0 VOL — — RESO Input leakage current STBY, NMI, RES, MD2 to MD0 Port 7 |IIN| — — — — 0.4 1.0 V µA — — 1.0 µA 525 Table 18-2 DC Characteristics (cont) Conditions: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (normalspecification product), Ta = –40°C to +85°C (extended temperature range specification product) Item Three-state leakage current (off state) Input pull -up current Ports 4, 5, 6, 8 to C, A19 to A0, D15 to D8 RESO Ports 4 and 5 –IP Symbol |ITS1| Min — Typ — Max 1.0 Unit Test Conditions µA VIN = 0.5 to VCC – 0.5 V — 10 — — 10.0 300 µA µA VCC = 3.0 V to 5.5 V, VIN = 0 V VIN = 0 V f = 1MHz Ta = 25°C f = 10 MHz f = 10 MHz Ta ≤ 50°C 50°C < Ta mA AVCC = 3.0 V AVCC = 5.0 V µA mA VREF = 3.0 V VREF = 5.0 V µA V NMI Input capacitance All input pins except NMI Normal Current dissipation*2 operation Sleep Standby*3-[ Analog power supply During A/D conversion A/D conversion standby Reference power supply current During A/D conversion A/D conversion standby CIN — — — — 50 15 pF pF mA mA µA ICC*4 — — — — — — 38 45 (5.0 V) (5.5 V) 27 34 (5.0 V) (5.5 V) 0.01 — 1.0 1.2 0.01 0.2 0.3 0.01 — 5.0 20.0 2.0 — 5.0 0.4 — 5.0 — AICC — — — AICC — — — RAM standby voltage VRAM 2.0 Notes: 1. When the A/D converter is not used, do not leave the AVCC, VREF, and AVSS pins open. Connect the AVCC and VREF pins to VCC, and the AVSS pin to VSS. 2. The current dissipation value is the value when all output pins are unloaded and the onchip pull-up MOS is off under the following conditions: VIH min = VCC to 0.5 V, VIL max = 0.5 V. 3. When VRAM ≤ VCC < 3.0 V, the value is for the case where VIHmin = VCC × 0.9, and VILmax = 0.3 V. 4. ICC is dependent upon VCC and f in accordance with the following formulas. ICCmax = 1.0 (mA) + 0.8 (mA/MHz · V) × VCC × f [normal mode] ICCmax = 1.0 (mA) + 0.6 (mA/MHz · V) × VCC × f [sleep mode] 526 Table 18-3 Permissible Output Currents Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Permissible output low current (per pin) Permissible output low current (total) Ports 5 and B, A19 to A0 Other output pins Total of 32 pins including ports 5 and B and A19 to A0 Total of all output pins, including the above Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins IOH ΣIOH ΣIOL Symbol IOL Min — — — — — — Typ — — — — — — Max 10 2.0 80 120 2.0 40 Unit mA mA mA mA mA mA Notes: 1. To protect chip reliability, do not exceed the output current values in table 18-3. 2. When driving a darlington pair or LED, always insert a current-limiting resistor in the output line, as shown in figures 18-1 and 18-2. 527 H8/3003 2 kΩ Port Darlington pair Figure 18-1 Darlington Pair Drive Circuit (Example) H8/3003 Ports 5 and B 600 Ω LED Figure 18-2 LED Drive Circuit (Example) 528 18.2.2 AC Characteristics Bus timing parameters are listed in table 18-4. Control signal timing parameters are listed in table 18-5. Refresh controller bus timing parameters are listed in table 18-6. Timing parameters of the on-chip supporting modules are listed in table 18-7. Table 18-4 Bus Timing Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Condition B Condition C 8 MHz Item Clock cycle time Clock low pulse width Clock high pulse width Clock rise time Clock fall time Address delay time Address hold time Address strobe delay time Write strobe delay time Strobe delay time Write data strobe pulse width 1 Write data strobe pulse width 2 Address setup time 1 Address setup time 2 Read data setup time Read data hold time Symbol tCYC tCL tCH tCR tCF tAD tAH tASD tWSD tSD tWSW1* tWSW2* tAS1 tAS2 tRDS tRDH Min 125 40 40 — — — 25 — — — 85 150 20 80 50 0 Max 500 — — 20 20 60 — 60 60 60 — — — — — — 10 MHz Min 100 30 30 — — — 20 — — — 60 110 15 65 35 0 Max 500 — — 15 15 50 — 40 50 50 — — — — — — 16 MHz Min 62.5 20 20 — — — 10 — — — 35 65 10 40 20 0 Max 500 — — 10 10 30 — 30 30 30 — — — — — — Unit ns Test Conditions Figure 18-4, Figure 18-5 529 Table 18-4 Bus Timing (cont) Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Condition B Condition C 8 MHz Item Write data delay time Write data setup time 1 Write data setup time 2 Write data hold time Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Precharge time Wait setup time Wait hold time Bus request setup ime Bus acknowledge delay time 1 Bus acknowledge delay time 2 Bus-floating time Symbol tWDD tWDS1 tWDS2 tWDH tACC1* tACC2* tACC3* tACC4* tPCH* tWTS tWTH tBRQS tBACD1 tBACD2 tBZD Min — 60 15 25 — — — — 85 40 10 40 — — — Max 75 — — — 110 230 55 160 — — — — 60 60 70 10 MHz Min — 65 10 20 — — — — 60 40 10 40 — — — Max 75 — — — 100 200 50 150 — — — — 50 50 70 16 MHz Min — 35 5 20 — — — — 40 25 5 40 — — — Max 60 — — — 55 115 25 85 — — — — 30 30 40 ns Figure 18-18 ns Figure 18-6 Unit ns Test Conditions Figure 18-4, Figure 18-5 Note is on next page. 530 Note: At 8 MHz, the times below depend as indicated on the clock cycle time. tACC1 = 1.5 × tcyc – 78 (ns) tWSW1 = 1.0 × tcyc – 40 (ns) tACC2 = 2.5 × tcyc – 83 (ns) tWSW2 = 1.5 × tcyc – 38 (ns) tACC3 = 1.0 × tcyc – 70 (ns) tPCH = 1.0 × tcyc – 40 (ns) tACC4 = 2.0 × tcyc – 90 (ns) At 10 MHz, the times below depend as indicated on the clock cycle time. tACC1 = 1.5 × tcyc – 50 (ns) tWSW1 = 1.0 × tcyc – 40 (ns) tACC2 = 2.5 × tcyc – 50 (ns) tWSW2 = 1.5 × tcyc – 40 (ns) tACC3 = 1.0 × tcyc – 50 (ns) tPCH = 1.0 × tcyc – 40 (ns) tACC4 = 2.0 × tcyc – 50 (ns) At 16 MHz, the times below depend as indicated on the clock cycle time. tACC1 = 1.5 × tcyc – 39 (ns) tWSW1 = 1.0 × tcyc – 28 (ns) tACC2 = 2.5 × tcyc – 41 (ns) tWSW2 = 1.5 × tcyc – 28 (ns) tACC3 = 1.0 × tcyc – 38 (ns) tPCH = 1.0 × tcyc – 23 (ns) tACC4 = 2.0 × tcyc – 40 (ns) 531 Table 18-5 Refresh Controller Bus Timing Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC , VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Condition B Condition C 8 MHz Item RAS delay time 1 RAS delay time 2 RAS delay time 3 Row address hold time* RAS precharge time* CAS to RAS precharge time* CAS pulse width RAS access time* Address access time CAS access time Write data setup time 3 CAS setup time* Read strobe delay time Symbol tRAD1 tRAD2 tRAD3 tRAH tRP tCRP tCAS tRAC tAA tCAC tWDS3 tCSR tRSD Min — — — 25 85 85 110 — — — 75 20 — Max 60 60 60 — — — — 160 105 50 — — 60 10 MHz Min — — — 20 70 70 85 — — — 50 15 — Max 50 50 50 — — — — 150 75 50 — — 50 16 MHz Min — — — 15 40 40 40 — — — 40 15 — Max 30 30 30 — — — — 85 55 25 — — 30 Unit ns Test Conditions Figure 18-7 to Figure 18-13 Note: At 8 MHz, the times below depend as indicated on the clock cycle time. tRAH = 0.5 × tcyc – 38 (ns) tCAC = 1.0 × tcyc – 75 (ns) tRAC = 2.0 × tcyc – 90 (ns) tCSR = 0.5 × tcyc – 43 (ns) tRP = tCRP = 1.0 × tcyc – 40 (ns) At 10 MHz, the times below depend as indicated on the clock cycle time. tRAH = 0.5 × tcyc – 30 (ns) tCAC = 1.0 × tcyc – 50 (ns) tRAC = 2.0 × tcyc – 50 (ns) tCSR = 0.5 × tcyc – 35 (ns) tRP = tCRP = 1.0 × tcyc – 30 (ns) At 16 MHz, the times below depend as indicated on the clock cycle time. tRAH = 0.5 × tcyc – 16 (ns) tCAC = 1.0 × tcyc – 38 (ns) tRAC = 2.0 × tcyc – 40 (ns) tCSR = 0.5 × tcyc – 16 (ns) tRP = tCRP = 1.0 × tcyc – 23 (ns) 532 Table 18-6 Control Signal Timing Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Condition B Condition C 8 MHz Item RES setup time RES pulse width RESO output delay time RESO output pulse width NMI setup time (NMI, IRQ7 to IRQ0) NMI hold time (NMI, IRQ7 to IRQ0) Interrupt pulse width (NMI, IRQ2 to IRQ0 when exiting software standby mode) Clock oscillator settling time at reset (crystal) Clock oscillator settling time in software standby (crystal) Symbol tRESS tRESW tRESD tRESOW tNMIS tNMIH tNMIW Min 200 10 — 132 150 10 200 Max — — 100 — — — — 10 MHz Min 200 10 — 132 150 10 200 Max — — 100 — — — — 16 MHz Min 200 10 — 132 150 10 200 Max — — 100 — — — — Unit ns tCYC ns tCYC ns Figure 18-17 Figure 18-16 Test Conditions Figure 18-15 tOSC1 tOSC2 20 8 — — 20 8 — — 20 8 — — ms Figure 18-19 Figure 17-1 533 Table 18-7 Timing of On-Chip Supporting Modules Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Condition B Condition C 8 MHz Item DMAC DREQ setup time DREQ hold time TEND delay time 1 TEND delay time 2 ITU Timer output delay time Timer input setup time Timer clock input setup time Timer Single clock edge pulse Both width edges SCI Input clock cycle Symbol tDRQS tDRQH tTED1 tTED2 tTOCD tTICS tTCKS tTCKWH tTCKWL Min 40 10 — — — 50 50 1.5 2.5 4 6 — — 0.4 Max — — 100 100 100 — — — — — — 1.5 1.5 0.6 10 MHz Min 30 10 — — — 50 50 1.5 2.5 4 6 — — 0.4 Max — — 50 50 100 — — — — — — 1.5 1.5 0.6 16 MHz Min 30 10 — — — 50 50 1.5 2.5 4 6 — — 0.4 Max — — 50 50 100 — — — — — — 1.5 1.5 0.6 tSCYC Figure 18-23 tCYC Figure 18-22 ns Figure 18-21 Figure 18-25, Figure 18-26 Unit ns Test Conditions Figure 18-27 AsyntSCYC chronous SyntSCYC chronous tSCKR tSCKR tSCKW Input clock rise time Input clock fall time Input clock pulse width 534 Table 18-7 Timing of On-Chip Supporting Modules (cont) Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Condition B Condition C 8 MHz Item SCI Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) Ports and TPC Output data delay time Input data setup time (synchronous) Input data hold time (synchronous) Symbol tTXD tRXS Min — 100 Max 100 — 10 MHz Min — 100 Max 100 — 16 MHz Min — 100 Max 100 — Unit ns Test Conditions Figure 18-24 tRXH 100 — 100 — 100 — tPWD tPRS — 50 100 — — 50 100 — — 50 100 — ns Figure 18-20 tPRH 50 — 50 — 50 — 5V C = 90 pF: ports 4, 5, 6, 8, C, A19 to A 0 , D15 to D8 , ø, AS , RD, HWR , LWR C = 30 pF: ports 9, A, B R L = 2.4 kΩ R H = 12 kΩ C RH Input/output timing measurement levels • Low: 0.8 V • High: 2.0 V RL H8/3003 output pin Figure 18-3 Output Load Circuit 535 18.2.3 A/D Conversion Characteristics Table 18-8 lists the A/D conversion characteristics. Table 18-8 A/D Converter Characteristics Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 8 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VREF = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A 8 MHz Item Resolution Conversion time Analog input capacitance Permissible signalsource impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Notes: 1. 2. 3. 4. 5. Min 10 — — — — — — — — — Typ 10 — — — — — — — — — Max 10 16.8 20 10*1 5*2 ±6.0 ±4.0 ±4.0 ±0.5 ±8.0 Min 10 — — — — — — — — — Condition B 10 MHz Typ 10 — — — — — — — — — Max 10 13.4 20 10*1 5*5 ±6.0 ±4.0 ±4.0 ±0.5 ±8.0 Min 10 — — — — — — — — — Condition C 16 MHz Typ 10 — — — — — — — — — Max 10 8.4 20 10*3 5*4 ±3.0 ±2.0 ±2.0 ±0.5 ±4.0 LSB LSB LSB LSB LSB Unit bits µs pF kΩ The value is for 4.0 ≤ AVCC ≤ 5.5. The value is for 2.7 ≤ AVCC < 4.0. The value is for ø ≤ 12 MHz. The value is for ø > 12 MHz. The value is for 3.0 ≤ AVCC < 4.0. 536 18.3 Operational Timing This section shows timing diagrams. 18.3.1 Bus Timing Bus timing is shown as follows: • Basic bus cycle: two-state access Figure 18-4 shows the timing of the external two-state access cycle. • Basic bus cycle: three-state access Figure 18-5 shows the timing of the external three-state access cycle. • Basic bus cycle: three-state access with one wait state Figure 18-6 shows the timing of the external three-state access cycle with one wait state inserted. 537 T1 tcyc tCH ø tCF tAD A23 to A0 CS 7 to CS 0 tASD AS tAS1 tACC3 tCR tCL T2 tPCH tSD tAH tPCH tASD RD (read) tAS1 tACC1 D15 to D0 (read) tASD HWR, LWR (write) tAS1 tWSW1 tWDD D15 to D0 (write) tWDS1 tWDH tSD tAH tRDS tRDH tACC3 tSD tAH tPCH Figure 18-4 Basic Bus Cycle: Two-State Access 538 T1 ø T2 T3 A23 to A0 tACC4 AS tACC4 RD (read) tACC2 D15 to D0 (read) tWSD HWR, LWR (write) D15 to D0 (write) tAS2 tWDS2 tWSW2 tRDS Figure 18-5 Basic Bus Cycle: Three-State Access 539 T1 ø T2 TW T3 A23 to A0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS WAIT tWTH tWTS tWTH Figure 18-6 Basic Bus Cycle: Three-State Access with One Wait State 540 18.3.2 Refresh Controller Bus Timing Refresh controller bus timing is shown as follows: • DRAM bus timing Figures 18-7 to 18-12 show the DRAM bus timing in each operating mode. • PSRAM bus timing Figures 18-13 and 18-14 show the pseudo-static RAM bus timing in each operating mode. T1 ø tAD tAD T2 T3 A9 to A1 AS tRAD1 CS3 (RAS) tAS1 tASD RD (CAS) HWR (UW), LWR (LW), (read) HWR (UW), LWR (LW), (write) RFSH D15 to D0 (read) tWDS3 D15 to D0 (write) Note: * Stipulation from earliest CS3 and RD negate timing. tASD tAS1 tCAS tSD tCRP tRAH tRAD3 tRP tRAC tAA tCAC tSD tWDH tRDS tRDH* Figure 18-7 DRAM Bus Timing (Read/Write): Three-State Access — 2WE Mode — 541 T1 ø T2 T3 A9 to A1 tASD AS tCSR CS3 (RAS) tASD RD (CAS) HWR (UW), LWR (LW) tRAD2 RFSH tCSR tRAD3 tRAD2 tSD tRAD3 tSD Figure 18-8 DRAM Bus Timing (Refresh Cycle): Three-State Access — 2WE Mode — ø CS3 (RAS) RD (CAS) tCSR tCSR RFSH Figure 18-9 DRAM Bus Timing (Self-Refresh Mode) — 2WE Mode — 542 T1 ø tAD tAD T2 T3 A9 to A1 AS tRAD1 tRAH tASD HWR (UCAS), LWR (LCAS) RD (WE) (read) tASD RD (WE) (write) RFSH D15 to D0 (read) tWDS3 D15 to D0 (write) tAS1 tCAS tRAD3 tRP tSD tCRP CS3 (RAS) tAS1 tRAC tAA tCAC tSD tWDH tRDS tRDH* Note: * Stipulation from earliest CS3 and RD negate timing. Figure 18-10 DRAM Bus Timing (Read/Write): Three-State Access — 2CAS Mode — 543 T1 ø T2 T3 A9 to A1 tASD AS tCSR CS3 (RAS) tASD HWR (UCAS), LWR (LCAS) RD (WE ) tRAD2 RFSH tCSR tRAD3 tRAD2 tSD tRAD3 tSD Figure 18-11 DRAM Bus Timing (Refresh Cycle): Three-State Access — 2CAS Mode — ø CS3 (RAS) HWR (UCAS), LWR (LCAS ) RFSH tCSR tCSR Figure 18-12 DRAM Bus Timing (Self-Refresh Mode) — 2CAS Mode — 544 T1 ø tAD T2 T3 A23 to A0 AS tRAD1 CS3 RD (read) tAS1 tRSD tRDS D15 to D0 (read) HWR, LWR (write) tWDS2 D15 to D0 (write) RFSH Note: * Stipulation from earliest CS3 and RD negate timing. tRDH* tRAD3 tRP tSD tWSD tSD Figure 18-13 PSRAM Bus Timing (Read/Write): Three-State Access T1 ø A23 to A0 AS CS3, HWR, LWR, RD RFSH tRAD2 T2 T3 tRAD3 Figure 18-14 PSRAM Bus Timing (Refresh Cycle): Three-State Access 545 18.3.3 Control Signal Timing Control signal timing is shown as follows: • Reset input timing Figure 18-15 shows the reset input timing. • Reset output timing Figure 18-16 shows the reset output timing. • Interrupt input timing Figure 18-17 shows the input timing for NMI and IRQ7 to IRQ0. • Bus-release mode timing Figure 18-18 shows the bus-release mode timing. ø tRESS RES tRESW tRESS Figure 18-15 Reset Input Timing ø tRESD RES tRESOW tRESD Figure 18-16 Reset Output Timing 546 ø tNMIS NMI tNMIS IRQ E tNMIS IRQ L IRQ E : Edge-sensitive IRQ I IRQ L : Level-sensitive IRQ I (I = 0 to 7) tNMIW NMI IRQ J (J = 0 to 2) tNMIH tNMIH Figure 18-17 Interrupt Input Timing ø tBRQS BREQ tBRQS tBACD2 tBACD1 BACK A23 to A0, AS, RD, HWR, LWR tBZD tBZD Figure 18-18 Bus-Release Mode Timing 547 18.3.4 Clock Timing Clock timing is shown as follows: • Oscillator settling timing Figure 18-19 shows the oscillator settling timing. ø VCC STBY tOSC1 RES tOSC1 Figure 18-19 Oscillator Settling Timing 18.3.5 TPC and I/O Port Timing TPC and I/O port timing is shown as follows. T1 ø tPRS Port 4 to C (read) T2 T3 tPRH tPWD Port 4 to 6, 8 to C (write) Figure 18-20 TPC and I/O Port Input/Output Timing 548 18.3.6 ITU Timing ITU timing is shown as follows: • ITU input/output timing Figure 18-21 shows the ITU input/output timing. • ITU external clock input timing Figure 18-22 shows the ITU external clock input timing. ø tTOCD Output compare*1 tTICS Input capture*2 Notes: 1. TIOCA0 to TIOCA4, TIOCB0 to TIOCB4, TOCXA4, TOCXB4 2. TIOCA0 to TIOCA4, TIOCB0 to TIOCB4 Figure 18-21 ITU Input/Output Timing tTCKS ø tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 18-22 ITU Clock Input Timing 549 18.3.7 SCI Input/Output Timing SCI timing is shown as follows: • SCI input clock timing Figure 18-23 shows the SCI input clock timing. • SCI input/output timing (synchronous mode) Figure 18-24 shows the SCI input/output timing in synchronous mode. tSCKW SCK0, SCK1 tSCKR tSCKR tSCYC Figure 18-23 SCK Input Clock Timing tSCYC SCK0, SCK1 tTXD TxD0, TxD1 (transmit data) RxD0, RxD1 (receive data) tRXS tRXH Figure 18-24 SCI Input/Output Timing in Synchronous Mode 550 18.3.8 DMAC Timing DMAC timing is shown as follows. • DMAC TEND output timing/2 state access Figure 18-25 shows the DMAC TEND output timing/2 state access • DMAC TEND output timing/3 state access Figure 18-26 shows the DMAC TEND output timing/3 state access. • DMAC DREQ input timing Figure 18-27 shows DMAC DREQ input timing. T1 ø tTED1 TEND T2 tTED2 Figure 18-25 DMAC TEND Output Timing/2 State Access T1 ø tTED1 TEND T2 T3 tTED2 Figure 18-26 DMAC TEND Output Timing/3 State Access 551 ø tDRQS DREQ tDRQH Figure 18-27 DMAC DREQ Input Timing 552 Appendix A Instruction Set A.1 Instruction List Operand Notation Symbol Rd Rs Rn ERd ERs ERn (EAd) (EAs) PC SP CCR N Z V C disp → + – × ÷ ∧ ∨ ⊕ ¬ ( ), < > Description General destination register General source register General register General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) Destination operand Source operand Program counter Stack pointer Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Displacement Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Addition of the operands on both sides Subtraction of the operand on the right from the operand on the left Multiplication of the operands on both sides Division of the operand on the left by the operand on the right Logical AND of the operands on both sides Logical OR of the operands on both sides Exclusive logical OR of the operands on both sides NOT (logical complement) Contents of operand Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7). 553 Condition Code Notation Symbol ¤ * 0 1 — ∆ Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 Not affected by execution of the instruction Varies depending on conditions, described in notes 554 Table A-1 Instruction Set 1. Data transfer instructions Addressing Mode and Instruction Length (bytes) @–ERn/@ERn+ No. of States *1 Operand Size @(d, ERn) Mnemonic MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd Operation #xx:8 → Rd8 Rs8 → Rd8 @ERs → Rd8 @(d:16, ERs) → Rd8 @(d:24, ERs) → Rd8 @ERs → RD8 ERs32+1 → ERs32 @aa:8 → Rd8 @aa:16 → Rd8 @aa:24 → Rd8 Rs8 → @ERd Rs8 → @(d:16, ERd) Rs8 → @(d:24, ERd) ERd32–1 → ERd32 Rs8 → @ERd Rs8 → @aa:8 Rs8 → @aa:16 Rs8 → @aa:24 @aa Condition Code I HN Z ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ V C B B B B 2 2 2 4 —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ 4 —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ 2 2 4 —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ 0— 0— 0— 0— 2 2 4 6 B 8 0— 10 B 2 0— 6 MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @ERd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @ERd B B B B B 2 4 6 2 0— 0— 0— 0— 0— 4 6 8 4 6 B 8 0— 10 B 2 0— 6 MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd MOV.W @(d:16, ERs), Rd MOV.W @(d:24, ERs), Rd MOV.W @ERs+, Rd B B B 2 4 6 4 0— 0— 0— 0— 0— 0— 0— 4 6 8 4 2 4 6 W #xx:16 → Rd16 W Rs16 → Rd16 W @ERs → Rd16 W @(d:16, ERs) → Rd16 W @(d:24, ERs) → Rd16 W @ERs → Rd16 ERs32+2 → @ERd32 W @aa:16 → Rd16 8 0— 10 2 0— 6 MOV.W @aa:16, Rd 4 0— 6 555 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Table A-1 Instruction Set (cont) Addressing Mode and Instruction Length (bytes) @–ERn/@ERn+ No. of States *1 Operand Size @(d, ERn) Mnemonic MOV.W @aa:24, Rd MOV.W Rs, @ERd MOV.W Rs, @(d:16, ERd) MOV.W Rs, @(d:24, ERd) MOV.W Rs, @–ERd Operation @aa Condition Code I HN Z ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ V C W @aa:24 → Rd16 W Rs16 → @ERd W Rs16 → @(d:16, ERd) W Rs 16 → @(d:24, ERd) 2 4 6 —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ 0— 0— 0— 8 4 6 8 0— 10 W ERd32–2 → ERd32 Rs16 → @ERd W Rs16 → @aa:16 W Rs16 → @aa:24 L L L L #xx:32 → Rd32 ERs32 → ERd32 @ERs → ERd32 @(d:16, ERs) → ERd32 @(d:24, ERs) → ERd32 @ERs → ERd32 ERs32+4 → ERs32 @aa:16 → ERd32 @aa:24 → ERd32 ERs32 → @ERd ERs32 → @(d:16, ERd) ERs32 → @(d:24, ERd) ERd32–4 → ERd32 ERs32 → @ERd ERs32 → @aa:16 ERs32 → @aa:24 4 6 6 2 4 6 2 0— 6 MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, Rd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16, ERs), ERd MOV.L @(d:24, ERs), ERd MOV.L @ERs+, ERd 4 6 0— 0— 0— 0— 0— 0— 6 8 6 2 8 10 —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ 2 —— ¤ 4 —— ¤ L 10 0— 14 L 4 0— 10 MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs, @ERd MOV.L ERs, @(d:16, ERd) MOV.L ERs, @(d:24, ERd) MOV.L ERs, @–ERd L L L L 6 8 0— 0— 0— 0— 10 12 8 10 L 10 0— 14 L 4 0— 10 MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 POP.W Rn L L 6 8 0— 0— 0— 10 12 6 W @SP → Rn16 SP+2 → SP L @SP → ERn32 SP+4 → SP POP.L ERn 0— 10 556 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Table A-1 Instruction Set (cont) Addressing Mode and Instruction Length (bytes) @–ERn/@ERn+ No. of States *1 Operand Size @(d, ERn) Mnemonic PUSH.W Rn Operation @aa Condition Code I HN Z ¤ ¤ V C W SP–2 → SP Rn16 → @SP L SP–4 → SP ERn32 → @SP Cannot be used in the H8/3003 Cannot be used in the H8/3003 4 2 —— ¤ 4 —— ¤ 0— 6 PUSH.L ERn 0— 10 MOVFPE @aa:16, Rd MOVTPE Rs, @aa:16 B Cannot be used in the H8/3003 B 4 Cannot be used in the H8/3003 2. Arithmetic instructions Addressing Mode and Instruction Length (bytes) @–ERn/@ERn+ No. of States *1 Operand Size @(d, ERn) Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd Operation Rd8+#xx:8 → Rd8 Rd8+Rs8 → Rd8 @aa Condition Code I HN ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ Z ¤ ¤ ¤ ¤ ¤ ¤ V ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ C ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ B B 2 2 4 2 6 —¤ —¤ —1 —1 —2 2 2 4 2 6 W Rd16+#xx:16 → Rd16 W Rd16+Rs16 → Rd16 L ERd32+#xx:32 → ERd32 ERd32+ERs32 → ERd32 Rd8+#xx:8 +C → Rd8 Rd8+Rs8 +C → Rd8 ERd32+1 → ERd32 ERd32+2 → ERd32 ERd32+4 → ERd32 Rd8+1 → Rd8 ADD.L ERs, ERd L 2 —2 —¤ 2 ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS.L #1, ERd ADDS.L #2, ERd ADDS.L #4, ERd INC.B Rd INC.W #1, Rd INC.W #2, Rd B B L L L B 2 2 2 2 2 2 2 2 3 3 2 2 2 2 2 2 2 2 —¤ —————— —————— —————— —— ¤ —— ¤ —— ¤ ¤ ¤ ¤ ¤— ¤— ¤— W Rd16+1 → Rd16 W Rd16+2 → Rd16 557 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn TIable A-1 Instruction Set (cont) Addressing Mode and Instruction Length (bytes) @–ERn/@ERn+ No. of States *1 Operand Size @(d, ERn) Mnemonic INC.L #1, ERd INC.L #2, ERd DAA Rd Operation ERd32+1 → ERd32 ERd32+2 → ERd32 Rd8 decimal adjust → Rd8 Rd8–Rs8 → Rd8 @aa Condition Code I HN Z ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ V C L L B 2 2 2 —— ¤ —— ¤ —* —¤ —1 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤— ¤— *— ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ 2 2 2 SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd B 2 4 2 6 2 4 2 6 W Rd16–#xx:16 → Rd16 W Rd16–Rs16 → Rd16 L ERd32–#xx:32 → ERd32 ERd32–ERs32 → ERd32 Rd8–#xx:8–C → Rd8 Rd8–Rs8–C → Rd8 ERd32–1 → ERd32 ERd32–2 → ERd32 ERd32–4 → ERd32 Rd8–1 → Rd8 —1 —2 SUB.L ERs, ERd L 2 —2 —¤ 2 SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS.L #1, ERd SUBS.L #2, ERd SUBS.L #4, ERd DEC.B Rd DEC.W #1, Rd DEC.W #2, Rd DEC.L #1, ERd DEC.L #2, ERd DAS.Rd B B L L L B 2 2 2 2 2 2 2 2 2 2 2 3 3 2 2 2 2 2 2 2 2 2 2 2 —¤ —————— —————— —————— —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —* ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤— ¤— ¤— ¤— ¤— *— W Rd16–1 → Rd16 W Rd16–2 → Rd16 L L B ERd32–1 → ERd32 ERd32–2 → ERd32 Rd8 decimal adjust → Rd8 Rd8 × Rs8 → Rd16 (unsigned multiplication) MULXU. B Rs, Rd B 2 —————— 14 MULXU. W Rs, ERd W Rd16 × Rs16 → ERd32 (unsigned multiplication) B Rd8 × Rs8 → Rd16 (signed multiplication) 2 —————— —— ¤ —— ¤ ¤ —— ¤ —— 22 MULXS. B Rs, Rd 4 16 MULXS. W Rs, ERd W Rd16 × Rs16 → ERd32 (signed multiplication) B Rd16 ÷ Rs8 → Rd16 (RdH: remainder, RdL: quotient) (unsigned division) 4 24 DIVXU. B Rs, Rd 2 ——6 7 —— 14 558 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Table A-1 Instruction Set (cont) Addressing Mode and Instruction Length (bytes) @–ERn/@ERn+ No. of States *1 Operand Size @(d, ERn) Mnemonic DIVXU. W Rs, ERd Operation @aa Condition Code I HN Z V C W ERd32 ÷ Rs16 →ERd32 (Ed: remainder, Rd: quotient) (unsigned division) B Rd16 ÷ Rs8 → Rd16 (RdH: remainder, RdL: quotient) (signed division) 2 ——6 7 —— 22 DIVXS. B Rs, Rd 4 ——8 7 —— 16 DIVXS. W Rs, ERd W ERd32 ÷ Rs16 → ERd32 (Ed: remainder, Rd: quotient) (signed division) B B Rd8–#xx:8 Rd8–Rs8 4 2 4 ——8 7 —— 24 CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd NEG.B Rd NEG.W Rd NEG.L ERd EXTU.W Rd —¤ 2 —¤ —1 2 —1 —2 2 2 2 2 2 —2 —¤ —¤ —¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ 2 2 4 2 4 2 2 2 2 2 W Rd16–#xx:16 W Rd16–Rs16 L L B ERd32–#xx:32 ERd32–ERs32 0–Rd8 → Rd8 6 W 0–Rd16 → Rd16 L 0–ERd32 → ERd32 W 0 → ( of Rd16) L 0 → ( of Rd32) —— 0 0— EXTU.L ERd 2 —— 0 —— ¤ —— ¤ 0— 2 EXTS.W Rd W ( of Rd16) → ( of Rd16) L ( of Rd32) → ( of ERd32) 2 0— 2 EXTS.L ERd 2 0— 2 559 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Table A-1 Instruction Set (cont) 3. Logic instructions Addressing Mode and Instruction Length (bytes) @–ERn/@ERn+ No. of States *1 Operand Size @(d, ERn) Mnemonic AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd NOT.B Rd NOT.W Rd NOT.L ERd Operation Rd8∧#xx:8 → Rd8 Rd8∧Rs8 → Rd8 @aa Condition Code I HN Z ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ V C B B 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 W Rd16∧#xx:16 → Rd16 W Rd16∧Rs16 → Rd16 L L B B ERd32∧#xx:32 → ERd32 ERd32∧ERs32 → ERd32 Rd8∨#xx:8 → Rd8 Rd8∨Rs8 → Rd8 W Rd16∨#xx:16 → Rd16 W Rd16∨Rs16 → Rd16 L L B B ERd32∨#xx:32 → ERd32 ERd32∨ERs32 → ERd32 Rd8⊕#xx:8 → Rd8 Rd8⊕Rs8 → Rd8 W Rd16⊕#xx:16 → Rd16 W Rd16⊕Rs16 → Rd16 L L B ERd32⊕#xx:32 → ERd32 ERd32⊕ERs32 → ERd32 ¬ Rd8 → Rd8 W ¬ Rd16 → Rd16 L ¬ Rd32 → Rd32 560 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Table A-1 Instruction Set (cont) 4. Shift instructions Addressing Mode and Instruction Length (bytes) @–ERn/@ERn+ No. of States *1 Operand Size @(d, ERn) Mnemonic SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR.B Rd SHLR.W Rd SHLR.L ERd ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR.B Rd ROTR.W Rd ROTR.L ERd Operation @aa Condition Code I HN Z ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ V ¤ ¤ ¤ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ B W L B W L B W L B W L B W L B W L B W L B W L 2 —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ —— ¤ 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C MSB LSB 0 2 2 2 C MSB LSB 2 2 2 C MSB LSB 0 2 2 2 0 MSB LSB C 2 2 2 C MSB LSB 2 2 2 C MSB LSB 2 2 2 C MSB LSB 2 2 2 C MSB LSB 2 2 561 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Table A-1 Instruction Set (cont) 5. Bit manipulation instructions Addressing Mode and Instruction Length (bytes) @–ERn/@ERn+ No. of States *1 Operand Size @(d, ERn) Mnemonic BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BNOT #xx:3, Rd Operation (#xx:3 of Rd8) ← 1 (#xx:3 of @ERd) ← 1 (#xx:3 of @aa:8) ← 1 (Rn8 of Rd8) ← 1 (Rn8 of @ERd) ← 1 (Rn8 of @aa:8) ← 1 (#xx:3 of Rd8) ← 0 (#xx:3 of @ERd) ← 0 (#xx:3 of @aa:8) ← 0 (Rn8 of Rd8) ← 0 (Rn8 of @ERd) ← 0 (Rn8 of @aa:8) ← 0 (#xx:3 of Rd8) ← ¬ (#xx:3 of Rd8) (#xx:3 of @ERd) ← ¬ (#xx:3 of @ERd) (#xx:3 of @aa:8) ← ¬ (#xx:3 of @aa:8) (Rn8 of Rd8) ← ¬ (Rn8 of Rd8) (Rn8 of @ERd) ← ¬ (Rn8 of @ERd) (Rn8 of @aa:8) ← ¬ (Rn8 of @aa:8) (#xx:3 of Rd8) → Z (#xx:3 of @ERd) → Z (#xx:3 of @aa:8) → Z (Rn8 of @Rd8) → Z (Rn8 of @ERd) → Z (Rn8 of @aa:8) → Z (#xx:3 of Rd8) → C @aa Condition Code I HN Z V C B B B B B B B B B B B B B 2 4 4 2 4 4 2 4 4 2 4 4 2 —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— 2 8 8 2 8 8 2 8 8 2 8 8 2 BNOT #xx:3, @ERd B 4 —————— 8 BNOT #xx:3, @aa:8 B 4 —————— 8 BNOT Rn, Rd B 2 —————— 2 BNOT Rn, @ERd B 4 —————— 8 BNOT Rn, @aa:8 B 4 —————— ——— ¤ —— 8 BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BLD #xx:3, Rd B B B B B B B 2 4 4 2 4 4 2 2 6 6 2 6 6 2 ——— ¤ —— ——— ¤ —— ——— ¤ —— ——— ¤ —— ——— ¤ —— ————— ¤ 562 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Table A-1 Instruction Set (cont) Addressing Mode and Instruction Length (bytes) @–ERn/@ERn+ No. of States *1 Operand Size @(d, ERn) @ERn Mnemonic BLD #xx:3, @ERd BLD #xx:3, @aa:8 BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8 BST #xx:3, Rd BST #xx:3, @REd BST #xx:3, @aa:8 BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 BLAND #xx:3, Rd BLAND #xx:3, @ERd BLAND #xx:3, @aa:8 BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BIOR #xx:3, Rd BIOR #xx:3, @ERd BIOR #xx:3, @aa:8 BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 Operation (#xx:3 of @ERd) → C (#xx:3 of @aa:8) → C ¬ (#xx:3 of Rd8) → C ¬ (#xx:3 of @ERd) → C ¬ (#xx:3 of @aa:8) → C C → (#xx:3 of Rd8) C → (#xx:3 of @ERd) C → (#xx:3 of @aa:8) C → (#xx:3 of Rd8) C → (#xx:3 of @ERd24) C → (#xx:3 of @aa:8) C∧(#xx:3 of Rd8) → C C∧(#xx:3 of @ERd24) → C C∧(#xx:3 of @aa:8) → C C∧(#xx:3 of Rd8) → C C∧(#xx:3 of @ERd24) → C C∧(#xx:3 of @aa:8) → C C∨(#xx:3 of Rd8) → C C∨(#xx:3 of @ERd24) → C C∨(#xx:3 of @aa:8) → C C∨(#xx:3 of Rd8) → C C∨(#xx:3 of @ERd24) → C C∨(#xx:3 of @aa:8) → C C⊕(#xx:3 of Rd8) → C C⊕(#xx:3 of @ERd24) → C C⊕(#xx:3 of @aa:8) → C C⊕(#xx:3 of Rd8) → C C⊕(#xx:3 of @ERd24) → C C⊕(#xx:3 of @aa:8) → C @aa Condition Code I HN Z V C B B B B B B B B B B B B B B B B B B B B B B B B B B B B B 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 ————— ¤ ————— ¤ ————— ¤ ————— ¤ ————— ¤ —————— —————— —————— —————— —————— —————— ————— ¤ ————— ¤ ————— ¤ ————— ¤ ————— ¤ ————— ¤ ————— ¤ ————— ¤ ————— ¤ ————— ¤ ————— ¤ ————— ¤ ————— ¤ ————— ¤ ————— ¤ ————— ¤ ————— ¤ ————— ¤ 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 563 Advanced @(d, PC) Implied Normal @@aa #xx Rn Table A-1 Instruction Set (cont) 6. Branching instructions Addressing Mode and Instruction Length (bytes) @–ERn/@ERn+ No. of States *1 Operand Size @(d, ERn) Mnemonic BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 Operation If condition is true then PC ← PC+d else Never next; Always @aa Condition Code I HN Z V C — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 2 4 2 4 2 4 —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 C∨Z=0 C∨Z=1 2 4 C=0 2 4 C=1 2 4 Z=0 2 4 Z=1 2 4 V=0 2 4 V=1 2 4 N=0 2 4 N=1 2 4 N⊕V = 0 2 4 N⊕V = 1 Z ∨ (N⊕V) =0 2 4 2 4 564 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Table A-1 Instruction Set (cont) Addressing Mode and Instruction Length (bytes) @–ERn/@ERn+ No. of States *1 Operand Size @(d, ERn) Mnemonic BLE d:8 BLE d:16 Operation If condition is true then PC ← PC+d else next; Z ∨ (N⊕V) =1 @aa Condition Code I HN Z V C — — 2 4 —————— —————— 4 6 JMP @ERn JMP @aa:24 JMP @@aa:8 BSR d:8 — PC ← ERn — PC ← aa:24 — PC ← @aa:8 — PC → @–SP PC ← PC+d:8 — PC → @–SP PC ← PC+d:16 — PC → @–SP PC ← @ERn — PC → @–SP PC ← @aa:24 — PC → @–SP PC ← @aa:8 — PC ← @SP+ 2 4 2 2 —————— —————— —————— —————— 8 6 4 6 10 8 BSR d:16 4 —————— 8 10 JSR @ERn 2 —————— 6 JSR @aa:24 4 —————— 8 10 JSR @@aa:8 2 —————— 8 12 RTS 2 —————— 8 10 565 Advanced 8 @(d, PC) Implied Normal @@aa @ERn #xx Rn Table A-1 Instruction Set (cont) 7. System control instructions Addressing Mode and Instruction Length (bytes) @–ERn/@ERn+ No. of States *1 Operand Size @(d, ERn) Mnemonic TRAPA #x:2 Operation @aa Condition Code I HN Z V C — PC → @–SP CCR → @–SP → PC — CCR ← @SP+ PC ← @SP+ — Transition to powerdown state B B #xx:8 → CCR Rs8 → CCR 2 2 4 6 2 —————— 14 16 RTE ¤ ¤ ¤ ¤ ¤ ¤ 10 SLEEP —————— ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ 2 LDC #xx:8, CCR LDC Rs, CCR LDC @ERs, CCR LDC @(d:16, ERs), CCR LDC @(d:24, ERs), CCR LDC @ERs+, CCR 2 2 6 8 W @ERs → CCR W @(d:16, ERs) → CCR W @(d:24, ERs) → CCR W @ERs → CCR ERs32+2 → ERs32 W @aa:16 → CCR W @aa:24 → CCR B CCR → Rd8 2 10 12 4 8 LDC @aa:16, CCR LDC @aa:24, CCR STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16, ERd) STC CCR, @(d:24, ERd) STC CCR, @–ERd 6 8 8 10 2 6 8 —————— 4 6 —————— —————— W CCR → @ERd W CCR → @(d:16, ERd) W CCR → @(d:24, ERd) W ERd32–2 → ERd32 CCR → @ERd W CCR → @aa:16 W CCR → @aa:24 B B B CCR∧#xx:8 → CCR CCR∨#xx:8 → CCR CCR⊕#xx:8 → CCR 2 2 2 10 —————— 12 4 —————— 8 STC CCR, @aa:16 STC CCR, @aa:24 ANDC #xx:8, CCR ORC #xx:8, CCR XORC #xx:8, CCR NOP 6 8 —————— —————— ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ 8 10 2 2 2 2 — PC ← PC+2 2 —————— 566 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Table A-1 Instruction Set (cont) 8. Block transfer instructions Addressing Mode and Instruction Length (bytes) @–ERn/@ERn+ No. of States *1 Operand Size @(d, ERn) Mnemonic EEPMOV. B Operation @aa Condition Code I HN Z V C — if R4L ≠ 0 then repeat @R5 → @R6 R5+1 → R5 R6+1 → R6 R4L–1 → R4L until R4L=0 else next — if R4 ≠ 0 then repeat @R5 → @R6 R5+1 → R5 R6+1 → R6 R4L–1 → R4 until R4=0 else next 4 —————— 8+ 4n*2 EEPMOV. W 4 —————— 8+ 4n*2 Notes: 1. The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. For other cases see section A.3, Number of States Required for Execution. 2. n is the value set in register R4L or R4. 1 Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. 2 Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. 3 Retains its previous value when the result is zero; otherwise cleared to 0. 4 Set to 1 when the adjustment produces a carry; otherwise retains its previous value. 5 The number of states required for execution of an instruction that transfers data in synchronization with the E clock is variable. 6 Set to 1 when the divisor is negative; otherwise cleared to 0. 7 Set to 1 when the divisor is zero; otherwise cleared to 0. 8 Set to 1 when the quotient is negative; otherwise cleared to 0. 567 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn A.2 Operation Code Map (1) 1st byte 2nd byte AH AL BH BL Instruction when most significant bit of BH is 0. Instruction when most significant bit of BH is 1. 4 ORG ADD SUB Table A.2 Table A.2 (2) (2) CMP MOV OR.B XOR.B AND.B Table A.2 (2) XORC ANDC LDC Table A.2 Table A.2 (2) (2) ADDX SUBX 5 6 7 8 9 A B C D E F Table A.2 (2) Table A.2 (2) 1 Table A.2 (2) STC LDC 2 3 Instruction code: AL 0 NOP Table A.2 Table A.2 Table A.2 Table A.2 (2) (2) (2) (2) AH 0 1 2 3 BRA BVS JMP MOV Table A.2 Table A.2 EEPMOV (2) (2) Table A.2 (3) MULXU.B DIVXU.B MULXU.W DIVXU.W BST OR.W BSET BOR MOV.B/W BIOR ADD ADDX CMP SUBX OR XOR AND MOV BIXOR BIAND BILD BXOR BAND BNOT BCLR BTST BIST BLD XOR.W AND.W MOV.B RTS BSR RTE TRAPA Table A.2 (2) BRN BHI BLS BCC BCS BNE BEQ BVC BPL BMI BGE BSR BLT BGT JSR BLE 4 5 6 7 8 9 A B C D E F 568 Operation Code Map (2) 1st byte 2nd byte AH AL BH BL 1 LDC/STC SLEEP ADD INC ADDS MOV SHLL SHAL SHAR ROTL ROTR EXTU EXTU NEG SHLR ROTXL ROTXR NOT DEC SUBS DEC DAS BRA BRN ADD ADD CMP SUB OR CMP SUB OR XOR XOR BLS BCS MOV MOV BHI BCC BNE AND AND BEQ BVC BVS BPL DEC SUB CMP.L BMI BGE BLT BGT BLE NOT ROTXR ROTXL SHLR SHLL SHAL SHAR ROTL ROTR NEG SUB DEC DEC EXTS EXTS INC INC INC Table A.2 Table A.2 (3) (3) 2 3 4 5 6 7 8 9 A B C D E F Table A.2 (3) Instruction code: BH AH AL 0 MOV INC ADDS DAA 01 0A 0B 0F 10 11 12 13 17 1A 1B 1F 58 79 7A 569 Operation Code Map (3) 1st byte 2nd byte 3rd byte 4th byte AH AL BH BL CH CL DH DL Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. Instruction code: C 0 1 2 3 4 5 6 7 8 9 A B C D E F AH ALBH BLCH LDC STC STC STC MULXS DIVXS OR BTST BOR BTST BIOR BSET BIST BSET BTST BOR BTST BIOR BSET BSET BNOT BCLR BNOT BCLR BIST BIXOR BIAND BILD BST BXOR BAND BLD BNOT BCLR BNOT BCLR BIXOR BIAND BILD BST BXOR BAND BLD XOR AND DIVXS MULXS LBC LDC 01406 LDC STC 01C05 01D05 01F06 7Cr06 * 1 7Cr07 * 1 7Dr06 * 1 7Dr07 * 1 7Eaa6 * 2 7Eaa7 * 2 7Faa6 * 2 7Faa7 * 2 Notes: 1. r is the register designation field. 2. aa is the absolute address field. 570 A.3 Number of States Required for Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8/300H CPU. Table A-3 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A-2 indicates the number of states required per cycle according to the bus size. The number of states required for execution of an instruction can be calculated from these two tables as follows: Number of states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN Examples of Calculation of Number of States Required for Execution Examples: Advanced mode, stack located in external address space, on-chip supporting modules accessed with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. BSET #0, @FFFFC7:8 From table A-3, I = L = 2 and J = K = M = N = 0 From table A-2, SI = 4 and SL = 3 Number of states = 2 × 4 + 2 × 3 = 14 JSR @@30 From table A-3, I = J = K = 2 and L = M = N = 0 From table A-2, SI = SJ = SK = 4 Number of states = 2 × 4 + 2 × 4 + 2 × 4 = 24 571 Table A-2 Number of States per Cycle Access Conditions On-Chip Supporting Module Cycle Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation SI SJ SK SL SM SN 1 3 6 2 4 3+m 6 + 2m On-Chip Memory 2 8-Bit Bus 6 16-Bit Bus 3 External Device 8-Bit Bus 16-Bit Bus 2-State 3-State 2-State 3-State Access Access Access Access 4 6 + 2m 2 3+m Legend m: Number of wait states inserted into external device access 572 Table A-3 Number of Cycles per Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 Instruction Mnemonic ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS #1/2/4, ERd ADDX #xx:8, Rd ADDX Rs, Rd AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 ADDS ADDX AND ANDC BAND Bcc 573 Table A-3 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 2 2 1 1 1 1 1 1 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Instruction Mnemonic Bcc BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BIAND #xx:3, Rd BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8 BIOR #xx:8, Rd BIOR #xx:8, @ERd BIOR #xx:8, @aa:8 BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 BLD #xx:3, Rd BLD #xx:3, @ERd BLD #xx:3, @aa:8 BCLR BIAND BILD BIOR BIST BIXOR BLD 574 Table A-3 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 1 2 1 3 1 1 1 1 2 1 2 2 2 1 1 1 1 1 1 2 2 2 2 2 2 1 1 2 2 2 2 Instruction Mnemonic BNOT BNOT #xx:3, Rd BNOT #xx:3, @ERd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @ERd BNOT Rn, @aa:8 BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BSR d:8 Normal*1 Advanced BSR d:16 Normal*1 Advanced BST BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8 BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd DAA Rd DAS Rd BOR BSET BSR BTST BXOR CMP DAA DAS 575 Table A-3 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 1 1 1 2 2 1 1 2 2 1 1 1 1 1 1 1 2 2 1 2 1 2 1 2 1 2 1 2 2 2 2 2 2 2n + 2*2 2n + 2*2 12 20 12 20 Instruction Mnemonic DEC DEC.B Rd DEC.W #1/2, Rd DEC.L #1/2, ERd DIVXS.B Rs, Rd DIVXS.W Rs, ERd DIVXU.B Rs, Rd DIVXU.W Rs, ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd INC.W #1/2, Rd INC.L #1/2, ERd JMP @ERn JMP @aa:24 DIVXS DIVXU EEPMOV EXTS EXTU INC JMP JMP @@aa:8 Normal*1 2 Advanced 2 JSR JSR @ERn Normal*1 2 Advanced 2 JSR @aa:24 Normal*1 2 Advanced 2 JSR @@aa:8 Normal*1 2 Advanced 2 LDC LDC #xx:8, CCR LDC Rs, CCR LDC @ERs, CCR LDC @(d:16, ERs), CCR LDC @(d:24, ERs), CCR LDC @ERs+, CCR LDC @aa:16, CCR LDC @aa:24, CCR 1 1 2 3 5 2 3 4 1 1 1 1 1 1 2 576 Table A-3 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 Instruction Mnemonic MOV MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @ERd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @–ERd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd MOV.W @(d:16, ERs), Rd MOV.W @(d:24, ERs), Rd MOV.W @ERs+, Rd MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd MOV.W Rs, @(d:16, ERd) MOV.W Rs, @(d:24, ERd) MOV.W Rs, @–ERd MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, ERd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16, ERs), ERd MOV.L @(d:24, ERs), ERd MOV.L @ERs+, ERd MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs, @ERd MOV.L ERs, @(d:16, ERd) MOV.L ERs, @(d:24, ERd) MOV.L ERs, @–ERd MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 577 Table A-3 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 1*3 1*3 12 20 12 20 Instruction Mnemonic MOVFPE MOVTPE MULXS MULXU NEG MOVFPE @aa:16, Rd*3 2 MOVTPE Rs, @aa:16*3 2 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 3 2 1 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 2 2 MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU.B Rs, Rd MULXU.W Rs, ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd ORC #xx:8, CCR POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR.B Rd ROTR.W Rd ROTR.L ERd ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd RTE NOP NOT OR ORC POP PUSH ROTL 1 2 1 2 2 2 2 2 ROTR ROTXL ROTXR RTE 2 578 Table A-3 Number of Cycles per Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N Normal*1 2 1 2 2 2 Instruction Mnemonic RTS RTS Advanced 2 SHAL SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR.B Rd SHLR.W Rd SHLR.L ERd SLEEP 1 1 1 1 1 1 1 1 1 1 1 1 1 SHAR SHLL SHLR SLEEP STC STC CCR, Rd 1 STC CCR, @ERd 2 STC CCR, @(d:16, ERd) 3 STC CCR, @(d:24, ERd) 5 STC CCR, @–ERd 2 STC CCR, @aa:16 3 STC CCR, @aa:24 4 SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd SUB.L ERs, ERd SUBS #1/2/4, ERd SUBX #xx:8, Rd SUBX Rs, Rd TRAPA #x:2 Normal*1 1 2 1 3 1 1 1 1 2 1 2 2 2 1 1 1 1 1 1 2 SUB SUBS SUBX TRAPA 4 4 Advanced 2 XOR XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd XORC #xx:8, CCR 1 1 2 1 3 2 1 XORC Notes: 1. n is the value set in register R4L or R4. The source and destination are accessed n + 1 times each. 2. For the number of states required for data access, refer to the relevant hardware manual. 3. Not available in the H8/3003. 579 Appendix B Register Field B.1 Register Addresses and Bit Names Data Bus Width Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Address Register (low) Name H'1C H'1D H'1E H'1F H'20 H'21 H'22 H'23 H'24 H'25 H'26 H'27 MAR0AR MAR0AE MAR0AH MAR0AL 8 8 8 8 DMAC channel 0A ETCR0AH 8 ETCR0AL IOAR0A DTCR0A 8 8 8 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short address mode Full address mode DMAC channel 0B DTE DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A H'28 H'29 H'2A H'2B H'2C H'2D H'2E H'2F MAR0BR MAR0BE MAR0BH MAR0BL 8 8 8 8 ETCR0BH 8 ETCR0BL IOAR0B DTCR0B 8 8 8 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short address mode Full address mode DTME — DAID DAIDE TMS DTS2B DTS1B DTS0B Legend DMAC: DMA controller (Continued on next page) 580 (Continued from preceding page) Data Bus Width 8 8 8 8 Address Register (low) Name H'30 H'31 H'32 H'33 H'34 H'35 H'36 H'37 MAR1AR MAR1AE MAR1AH MAR1AL Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name DMAC channel 1A ETCR1AH 8 ETCR1AL IOAR1A DTCR1A 8 8 8 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short address mode Full address mode DMAC channel 1B DTE DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A H'38 H'39 H'3A H'3B H'3C H'3D H'3E H'3F MAR1BR MAR1BE MAR1BH MAR1BL 8 8 8 8 ETCR1BH 8 ETCR1BL IOAR1B DTCR1B 8 8 8 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short address mode Full address mode DMAC channel 2A DTME — DAID DAIDE TMS DTS2B DTS1B DTS0B H'40 H'41 H'42 H'43 H'44 H'45 H'46 H'47 MAR2AR MAR2AE MAR2AH MAR2AL 8 8 8 8 ETCR2AH 8 ETCR2AL IOAR2A DTCR2A 8 8 8 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short address mode Full address mode DTE DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A Legend DMAC: DMA controller (Continued on next page) 581 (Continued from preceding page) Data Bus Width 8 8 8 8 Address Register (low) Name H'48 H'49 H'4A H'4B H'4C H'4D H'4E H'4F MAR2BR MAR2BE MAR2BH MAR2BL Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name DMAC channel 2B ETCR2BH 8 ETCR2BL IOAR2B DTCR2B 8 8 8 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short address mode Full address mode DMAC channel 3A DTME — DAID DAIDE TMS DTS2B DTS1B DTS0B H'50 H'51 H'52 H'53 H'54 H'55 H'56 H'57 MAR3AR MAR3AE MAR3AH MAR3AL 8 8 8 8 ETCR3AH 8 ETCR3AL IOAR3A DTCR3A 8 8 8 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short address mode Full address mode DMAC channel 3B DTE DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A H'58 H'59 H'5A H'5B H'5C H'5D H'5E H'5F MAR3BR MAR3BE MAR3BH MAR3BL 8 8 8 8 ETCR3BH 8 ETCR3BL IOAR3B DTCR3B 8 8 8 DTE DTSZ DTID RPE DTIE DTS2 DTS1 DTS0 Short address mode Full address mode DTME — DAID DAIDE TMS DTS2B DTS1B DTS0B Legend DMAC: DMA controller (Continued on next page) 582 (Continued from preceding page) Data Bus Width 8 8 8 8 8 8 8 8 16 — — — — — Address Register (low) Name H'60 H'61 H'62 H'63 H'64 H'65 H'66 H'67 H'68 H'69 H'6A H'6B H'6C H'6D H'6E H'6F H'70 H'71 H'72 H'73 H'74 H'75 H'76 H'77 H'78 H'79 H'7A H'7B H'7C H'7D H'7E H'7F H'80 H'81 TSTR TSNC TMDR TFCR TCR0 TIOR0 TIER0 TSR0 TCNT0H TCNT0L GRA0H GRA0L GRB0H GRB0L TCR1 TIOR1 TIER1 TSR1 TCNT1H TCNT1L GRA1H GRA1L GRB1H GRB1L TCR2 TIOR2 TIER2 TSR2 TCNT2H TCNT2L GRA2H GRA2L GRB2H GRB2L Bit Names Bit 7 — — Bit 6 — — MDF — CCLR1 IOB2 — — Bit 5 — — FDIR CMD1 CCLR0 IOB1 — — Bit 4 STR4 Bit 3 STR3 Bit 2 STR2 Bit 1 STR1 Bit 0 STR0 Module Name ITU (all channels) SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 PWM4 CMD0 PWM3 BFB4 PWM2 BFA4 PWM1 BFB3 TPSC1 IOA1 IMIEB IMFB PWM0 BFA3 TPSC0 IOA0 IMIEA IMFA CKEG1 CKEG0 TPSC2 IOB0 — — — — — IOA2 OVIE OVF ITU channel 0 16 16 8 8 8 8 16 — — — — CCLR1 IOB2 — — CCLR0 IOB1 — — CKEG1 CKEG0 TPSC2 IOB0 — — — — — IOA2 OVIE OVF TPSC1 IOA1 IMIEB IMFB TPSC0 IOA0 IMIEA IMFA ITU channel 1 16 16 8 8 8 8 16 — — — — CCLR1 IOB2 — — CCLR0 IOB1 — — CKEG1 CKEG0 TPSC2 IOB0 — — — — — IOA2 OVIE OVF TPSC1 IOA1 IMIEB IMFB TPSC0 IOA0 IMIEA IMFA ITU channel 2 16 16 Legend ITU: 16-bit integrated timer unit (Continued on next page) 583 (Continued from preceding page) Data Bus Width 8 8 8 8 16 Address Register (low) Name H'82 H'83 H'84 H'85 H'86 H'87 H'88 H'89 H'8A H'8B H'8C H'8D H'8E H'8F H'90 H'91 H'92 H'93 H'94 H'95 H'96 H'97 H'98 H'99 H'9A H'9B H'9C H'9D H'9E H'9F TCR3 TIOR3 TIER3 TSR3 TCNT3H TCNT3L GRA3H GRA3L GRB3H GRB3L BRA3H BRA3L BRB3H BRB3L TOER TOCR TCR4 TIOR4 TIER4 TSR4 TCNT4H TCNT4L GRA4H GRA4L GRB4H GRB4L BRA4H BRA4L BRB4H BRB4L Bit Names Bit 7 — — — — Bit 6 CCLR1 IOB2 — — Bit 5 CCLR0 IOB1 — — Bit 4 Bit 3 Bit 2 Bit 1 TPSC1 IOA1 IMIEB IMFB Bit 0 TPSC0 IOA0 IMIEA IMFA Module Name ITU channel 3 CKEG1 CKEG0 TPSC2 IOB0 — — — — — IOA2 OVIE OVF 16 16 16 16 8 8 8 8 8 8 16 — — — — — — — — CCLR1 IOB2 — — EXB4 — CCLR0 IOB1 — — EXA4 XTGD IOB0 — — EB3 — EB4 — EA4 OLS4 TPSC1 IOA1 IMIEB IMFB EA3 OLS3 TPSC0 IOA0 IMIEA IMFA ITU (all channels) ITU channel 4 CKEG1 CKEG0 TPSC2 — — — IOA2 OVIE OVF 16 16 16 16 Legend ITU: 16-bit integrated timer unit (Continued on next page) 584 (Continued from preceding page) Data Bus Width 8 8 8 8 8 8 H'A5 NDRA*1 NDRB*1 NDRA*1 TCSR*2 TCNT*2 — RSTCSR*3 8 RFSHCR RTMCSR RTCNT RTCOR SMR BRR SCR TDR SSR RDR — — 8 8 8 8 8 8 8 8 8 8 — — — — — — — — — — — — — — — — TDRE RDRF ORER FER PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 C/A CHR PE O/E STOP MP CKS1 CKS0 SCI channel 0 8 8 H'A6 8 8 H'A7 8 8 H'A8 H'A9 H'AA H'AB H'AC H'AD H'AE H'AF H'B0 H'B1 H'B2 H'B3 H'B4 H'B5 H'B6 H'B7 8 8 — WRST — — — — — — — — — — — — RCYCE — Refresh controller Address Register (low) Name H'A0 H'A1 H'A2 H'A3 H'A4 TPMR TPCR NDERB NDERA NDRB*1 Bit Names Bit 7 — Bit 6 — Bit 5 — Bit 4 — Bit 3 Bit 2 Bit 1 Bit 0 Module Name TPC G3NOV G2NOV G1NOV G0NOV G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 NDR15 NDR15 NDR7 NDR7 — — — — OVF NDR14 NDR14 NDR6 NDR6 — — — — WT/IT NDR13 NDR13 NDR5 NDR5 — — — — TME NDR12 NDR12 NDR4 NDR4 — — — — — NDR11 — NDR3 — — NDR11 — NDR3 — NDR10 — NDR2 — — NDR10 — NDR2 CKS2 NDR9 — NDR1 — — NDR9 — NDR1 CKS1 NDR8 — NDR0 — — NDR8 — NDR0 CKS0 WDT RSTOE — SRFMD PSRAME DRAME CAS/WE M9/M8 CMF CMIE CKS2 CKS1 CKS0 PFSHE — — — Notes: 1. The address depends on the output trigger setting. 2. For write access to TCSR and TCNT, see section 12.2.4, Notes on Register Access. 3. For write access to RSTCSR, see section 12.2.4, Notes on Register Access. Legend TPC: Programmable timing pattern controller WDT: Watchdog timer SCI: Serial communication interface (Continued on next page) 585 (Continued from preceding page) Data Bus Width 8 8 8 8 8 8 — — — — — — — 8 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Port 4 TDRE RDRF ORER FER PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 Address Register (low) Name H'B8 H'B9 H'BA H'BB H'BC H'BD H'BE H'BF H'C0 H'C1 H'C2 H'C3 H'C4 H'C5 H'C6 H'C7 H'C8 H'C9 H'CA H'CB H'CC H'CD H'CE H'CF H'D0 H'D1 H'D2 H'D3 H'D4 H'D5 H'D6 H'D7 SMR BRR SCR TDR SSR RDR — — — — — — — P4DDR — P4DR P5DDR P6DDR P5DR P6DR — P8DDR P7DR P8DR P9DDR PADDR P9DR PADR PBDDR PCDDR PBDR PCDR Bit Names Bit 7 C/A Bit 6 CHR Bit 5 PE Bit 4 O/E Bit 3 STOP Bit 2 MP Bit 1 CKS1 Bit 0 CKS0 Module Name SCI channel 1 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR — — P46 — P45 — P44 — P43 — P42 — P41 — P40 P47 — P57 — — 8 8 8 8 8 Port 4 Port 5 Port 6 Port 5 Port 6 P57DDR P56DDR P55DDR P54DDR P53DDR P52DDR P51DDR P50DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR P56 P66 — — P76 — — P55 P65 — — P75 — P54 P64 — P53 P63 — P52 P62 — P51 P61 — P50 P60 — 8 8 8 8 8 8 8 8 8 8 8 — P77 — — P84DDR P83DDR P82DDR P81DDR P80DDR P74 P84 P73 P83 P72 P82 P71 P81 P70 P80 Port 8 Port 7 Port 8 Port 9 Port A Port 9 Port A Port B P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR P95 PA5 P94 PA4 P93 PA3 P92 PA2 P91 PA1 P90 PA0 PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR — PA7 — PA6 PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR PB7 PC7 PB6 PC6 PB5 PC5 PB4 PC4 PB3 PC3 PB2 PC2 PB1 PC1 PB0 PC0 PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Port C Port B Port C Legend SCI: Serial communication interface (Continued on next page) 586 (Continued from preceding page) Data Bus Width Address Register (low) Name H'D8 H'D9 H'DA H'DB H'DC H'DD H'DE H'DF H'E0 H'E1 H'E2 H'E3 H'E4 H'E5 H'E6 H'E7 H'E8 H'E9 H'EA H'EB H'EC H'ED H'EE H'EF — — P4PCR P5PCR — — — — ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR — — ABWCR ASTCR WCR WCER Bit Names Bit 7 — — Bit 6 — — Bit 5 — — Bit 4 — — Bit 3 — — Bit 2 — — Bit 1 — — Bit 0 — — Port 4 Port 5 Module Name 8 8 P47PCR P46PCR P45PCR P44PCR P43PCR P42PCR P41PCR P40PCR P57PCR P56PCR P55PCR P54PCR P53PCR P52PCR P51PCR P50PCR — — — — — — — — AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE — — — ABW6 AST6 — WCE6 — — — — AD7 — AD7 — AD7 — AD7 — ADST — — — ABW5 AST5 — WCE5 — — — — AD6 — AD6 — AD6 — AD6 — SCAN — — — ABW4 AST4 — WCE4 — — — — AD5 — AD5 — AD5 — AD5 — CKS — — — ABW3 AST3 WMS1 WCE3 — — — — AD4 — AD4 — AD4 — AD4 — CH2 — — — ABW2 AST2 WMS0 WCE2 — — — — AD3 — AD3 — AD3 — AD3 — CH1 — — — ABW1 AST1 WC1 WCE1 — — — — AD2 — AD2 — AD2 — AD2 — CH0 — — — ABW0 AST0 WC0 WCE0 8 8 8 8 8 8 8 8 8 8 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGE — — A/D 8 8 8 8 ABW7 AST7 — WCE7 Bus controller Legend A/D: A/D converter (Continued on next page) 587 (Continued from preceding page) Data Bus Width Address Register (low) Name H'F0 H'F1 H'F2 H'F3 H'F4 H'F5 H'F6 H'F7 H'F8 H'F9 H'FA H'FB H'FC H'FD H'FE H'FF — MDCR SYSCR BRCR ISCR IER ISR — IPRA IPRB — — — — — — Bit Names Bit 7 — Bit 6 — — STS2 — Bit 5 — — STS1 — Bit 4 — — STS0 — Bit 3 — — UE — Bit 2 — MDS2 NMIEG — Bit 1 — MDS1 — — Bit 0 — MDS0 RAME BRLE Bus controller I Interrupt controller System control Module Name 8 8 8 8 8 8 — SSBY — IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC IRQ7E IRQ7F — IRQ6E IRQ6F — IPRA6 IPRB6 — — — — — — IRQ5E IRQ5F — IPRA5 IPRB5 — — — — — — IRQ4E IRQ4F — IPRA4 IPRB4 — — — — — — IRQ3E IRQ3F — IPRA3 IPRB3 — — — — — — IRQ2E IRQ2F — IPRA2 IPRB2 — — — — — — IRQ1E IRQ1F — IPRA1 IPRB1 — — — — — — IRQ0E IRQ0F — IPRA0 — — — — — — — 8 8 IPRA7 IPRB7 — — — — — — Interrupt controller 588 B.2 Register Descriptions Register acronym Register name Address to which the register is mapped Name of on-chip supporting module TSTR Timer Start Register H'60 ITU (all channels) Bit numbers Bit 7 — Initial value Read/Write 1 — 6 — 1 — 5 — 1 — 4 STR4 0 R/W 3 STR3 0 R/W 2 STR2 0 R/W 1 STR1 0 R/W 0 STR0 0 R/W Initial bit values Names of the bits. Dashes (—) indicate reserved bits. Possible types of access R W Read only Write only Counter start 0 0 TCNT0 is halted 1 TCNT0 is counting Counter start 1 0 TCNT1 is halted 1 TCNT1 is counting Counter start 2 0 TCNT2 is halted 1 TCNT2 is counting Counter start 3 0 TCNT3 is halted 1 TCNT3 is counting Counter start 4 0 TCNT4 is halted 1 TCNT4 is counting R/W Read and write Full name of bit Descriptions of bit settings 589 MAR0A R/E/H/L—Memory Address Register 0A R/E/H/L H'20, H'21, H'22, H'23 22 21 20 19 18 DMAC0 Bit Initial value Read/Write 31 1 — 30 1 — 29 1 — 28 1 — 27 1 — 26 1 — 25 1 — 24 1 23 17 16 Undetermined — R/W R/W R/W R/W R/W R/W R/W R/W MAR0AE MAR0AR Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR0AH Source or destination address MAR0AL 590 ETCR0A H/L—Execute Transfer Count Register 0A H/L • Short address mode H'24, H'25 DMAC0 I/O mode and idle mode Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter Repeat mode Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCR0AH Transfer counter Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCR0AL Initial count 591 ETCR0A H/L—Execute Transfer Count Register 0A H/L (cont) • Full address mode H'24, H'25 DMAC0 Normal mode Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter Block transfer mode Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCR0AH Block size counter Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCR0AL Initial block size 592 IOAR0A—I/O Address Register 0A Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 H'26 2 1 DMAC0 0 Undetermined R/W R/W R/W R/W R/W Short address mode: source or destination address Full address mode: not used 593 DTCR0A—Data Transfer Control Register 0A • Bit Initial value Read/Write H'27 DMAC0 Short address mode 7 DTE 0 R/W 6 DTSZ 0 R/W 5 DTID 0 R/W 4 RPE 0 R/W 3 DTIE 0 R/W 2 DTS2 0 R/W 1 DTS1 0 R/W 0 DTS0 0 R/W Data transfer select Bit 2 Bit 1 Bit 0 DTS2 DTS1 DTS0 0 0 0 1 0 1 1 0 0 1 1 1 * Data Transfer Activation Source Compare match/input capture A interrupt from ITU channel 0 Compare match/input capture A interrupt from ITU channel 1 Compare match/input capture A interrupt from ITU channel 2 Compare match/input capture A interrupt from ITU channel 3 SCI transmit-data-empty interrupt SCI receive-data-full interrupt Transfer in full address mode Data transfer interrupt enable 0 Interrupt requested by DTE bit is disabled 1 Interrupt requested by DTE bit is enabled Repeat enable RPE DTIE Description 0 0 I/O mode 1 0 1 Repeat mode 1 Idle mode Data transfer increment/decrement 0 Incremented: If DTSZ = 0, MAR is incremented by 1 after each transfer If DTSZ = 1, MAR is incremented by 2 after each transfer 1 Decremented: If DTSZ = 0, MAR is decremented by 1 after each transfer If DTSZ = 1, MAR is decremented by 2 after each transfer Data transfer size 0 Byte-size transfer 1 Word-size transfer Data transfer enable 0 Data transfer is disabled 1 Data transfer is enabled 594 DTCR0A—Data Transfer Control Register 0A (cont) • Bit Initial value Read/Write H'27 DMAC0 Full address mode 7 DTE 0 R/W 6 DTSZ 0 R/W 5 SAID 0 R/W 4 SAIDE 0 R/W 3 DTIE 0 R/W 2 DTS2A 0 R/W 1 DTS1A 0 R/W 0 DTS0A 0 R/W Data transfer select 0A 0 Normal mode 1 Block transfer mode Data transfer select 2A and 1A Set both bits to 1 Data transfer interrupt enable 0 Interrupt request by DTE bit is disabled 1 Interrupt request by DTE bit is enabled Source address increment/decrement Bit 5 Bit 4 SAID SAIDE Increment/Decrement Enable 0 0 MARA is held fixed 1 Incremented: If DTSZ = 0, MARA is incremented by 1 after each transfer If DTSZ = 1, MARA is incremented by 2 after each transfer 1 0 MARA is held fixed 1 Decremented: If DTSZ = 0, MARA is decremented by 1 after each transfer If DTSZ = 1, MARA is decremented by 2 after each transfer Data transfer size 0 Byte-size transfer 1 Word-size transfer Data transfer enable 0 Data transfer is disabled 1 Data transfer is enabled 595 MAR0B R/E/H/L—Memory Address Register 0B R/E/H/L H'28, H'29, H'2A, H'2B 22 21 20 19 18 DMAC0 Bit Initial value Read/Write 31 1 — 30 1 — 29 1 — 28 1 — 27 1 — 26 1 — 25 1 — 24 1 23 17 16 Undetermined — R/W R/W R/W R/W R/W R/W R/W R/W MAR0BE MAR0BR Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR0BH Source or destination address MAR0BL 596 ETCR0B H/L—Execute Transfer Count Register 0B H/L • Short address mode H'2C, H'2D DMAC0 I/O mode and idle mode Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter Repeat mode Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCR0BH Transfer counter Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCR0BL Initial count 597 ETCR0B H/L—Execute Transfer Count Register 0B H/L (cont) • Full address mode H'2C, H'2D DMAC0 Normal mode Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Not used Block transfer mode Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Block transfer counter IOAR0B—I/O Address Register 0B Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 H'2E 2 1 DMAC0 0 Undetermined R/W R/W R/W R/W R/W Short address mode: source or destination address Full address mode: not used 598 DTCR0B—Data Transfer Control Register 0B • Bit Initial value Read/Write H'2F DMAC0 Short address mode 7 DTE 0 R/W 6 DTSZ 0 R/W 5 DTID 0 R/W 4 RPE 0 R/W 3 DTIE 0 R/W 2 DTS2 0 R/W 1 DTS1 0 R/W 0 DTS0 0 R/W Data transfer select Bit 2 Bit 1 Bit 0 DTS2 DTS1 DTS0 0 0 0 1 0 1 1 0 0 1 1 0 1 1 Data Transfer Activation Source Compare match/input capture A interrupt from ITU channel 0 Compare match/input capture A interrupt from ITU channel 1 Compare match/input capture A interrupt from ITU channel 2 Compare match/input capture A interrupt from ITU channel 3 SCI transmit-data-empty interrupt SCI receive-data-full interrupt Falling edge of DREQ input Low level of DREQ input Data transfer interrupt enable 0 Interrupt requested by DTE bit is disabled 1 Interrupt requested by DTE bit is enabled CPU interrupt requested when DTE = 0 Repeat enable RPE DTIE Description 0 0 I/O mode 1 0 1 Repeat mode 1 Idle mode Data transfer increment/decrement 0 Incremented: If DTSZ = 0, MAR is incremented by 1 after each transfer If DTSZ = 1, MAR is incremented by 2 after each transfer 1 Decremented: If DTSZ = 0, MAR is decremented by 1 after each transfer If DTSZ = 1, MAR is decremented by 2 after each transfer Data transfer size 0 Byte-size transfer 1 Word-size transfer Data transfer enable 0 Data transfer is disabled 1 Data transfer is enabled 599 DTCR0B—Data Transfer Control Register 0B • Bit Initial value Read/Write H'2F DMAC0 Full address mode 7 DTME 0 R/W 6 — 0 R/W 5 DAID 0 R/W 4 DAIDE 0 R/W 3 TMS 0 R/W 2 DTS2B 0 R/W 1 DTS1B 0 R/W 0 DTS0B 0 R/W Data transfer select 2B to 0B Bit 2 Bit 1 Bit 0 Data Transfer Activation Source DTS2B DTS1B DTS0B Normal Mode Block Transfer Mode 0 0 0 Auto-request Compare match/input capture (burst mode) A from ITU channel 0 1 Not available Compare match/input capture A from ITU channel 1 Compare match/input capture 1 0 Auto-request A from ITU channel 2 (cycle-steal mode) Compare match/input capture Not available 1 A from ITU channel 3 Not available 1 0 Not available 0 Not available Not available 1 Falling edge of DREQ Falling edge of DREQ 1 0 1 Low level input at DREQ Not available Transfer mode select 0 Destination is the block area in block transfer mode 1 Source is the block area in block transfer mode Destination address increment/decrement Bit 5 Bit 4 DAID DAIDE Increment/Decrement Enable 0 0 MARB is held fixed 1 Incremented: If DTSZ = 0, MARB is incremented by 1 after each transfer If DTSZ = 1, MARB is incremented by 2 after each transfer 1 0 MARB is held fixed 1 Decremented: If DTSZ = 0, MARB is decremented by 1 after each transfer If DTSZ = 1, MARB is decremented by 2 after each transfer Data transfer master enable 0 Data transfer is disabled 1 Data transfer is enabled 600 MAR1A R/E/H/L—Memory Address Register 1A R/E/H/L H'30, H'31, H'32, H'33 22 21 20 19 18 DMAC1 Bit Initial value Read/Write 31 1 — 30 1 — 29 1 — 28 1 — 27 1 — 26 1 — 25 1 — 24 1 23 17 16 Undetermined — R/W R/W R/W R/W R/W R/W R/W R/W MAR1AE MAR1AR Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR1AH MAR1AL Note: Bit functions are the same as for DMAC0. 601 ETCR1A H/L—Execute Transfer Count Register 1A H/L Bit Initial value Read/Write Bit Initial value Read/Write R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 H'34, H'35 5 4 3 2 DMAC1 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCR1AH Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCR1AL Note: Bit functions are the same as for DMAC0. IOAR1A—I/O Address Register 1A Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 H'36 2 1 DMAC1 0 Undetermined R/W R/W R/W R/W R/W Note: Bit functions are the same as for DMAC0. 602 DTCR1A—Data Transfer Control Register 1A • Short address mode Bit Initial value Read/Write 7 DTE 0 R/W 6 DTSZ 0 R/W 5 DTID 0 R/W 4 RPE 0 R/W 3 DTIE 0 R/W H'37 DMAC1 2 DTS2 0 R/W 1 DTS1 0 R/W 0 DTS0 0 R/W • Full address mode Bit Initial value Read/Write 7 DTE 0 R/W 6 DTSZ 0 R/W 5 SAID 0 R/W 4 SAIDE 0 R/W 3 DTIE 0 R/W 2 DTS2A 0 R/W 1 DTS1A 0 R/W 0 DTS0A 0 R/W Note: Bit functions are the same as for DMAC0. MAR1B R/E/H/L—Memory Address Register 1B R/E/H/L H'38, H'39, H'3A, H'3B 22 21 20 19 18 DMAC1 Bit Initial value Read/Write 31 1 — 30 1 — 29 1 — 28 1 — 27 1 — 26 1 — 25 1 — 24 1 23 17 16 Undetermined — R/W R/W R/W R/W R/W R/W R/W R/W MAR1BE MAR1BR Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR1BH MAR1BL Note: Bit functions are the same as for DMAC0. 603 ETCR1B H/L—Execute Transfer Count Register 1B H/L Bit Initial value Read/Write Bit Initial value Read/Write R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 H'3C, H'3D 5 4 3 2 DMAC1 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCR1BH Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCR1BL Note: Bit functions are the same as for DMAC0. IOAR1B—I/O Address Register 1B Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 H'3E 2 1 DMAC1 0 Undetermined R/W R/W R/W R/W R/W Note: Bit functions are the same as for DMAC0. 604 DTCR1B—Data Transfer Control Register 1B • Short address mode Bit Initial value Read/Write 7 DTE 0 R/W 6 DTSZ 0 R/W 5 DTID 0 R/W 4 RPE 0 R/W 3 DTIE 0 R/W H'3F DMAC1 2 DTS2 0 R/W 1 DTS1 0 R/W 0 DTS0 0 R/W • Full address mode Bit Initial value Read/Write 7 DTME 0 R/W 6 — 0 R/W 5 DAID 0 R/W 4 DAIDE 0 R/W 3 TMS 0 R/W 2 DTS2B 0 R/W 1 DTS1B 0 R/W 0 DTS0B 0 R/W Note: Bit functions are the same as for DMAC0. MAR2A R/E/H/L—Memory Address Register 2A R/E/H/L H'40, H'41, H'42, H'43 22 21 20 19 18 DMAC2 Bit Initial value Read/Write 31 1 — 30 1 — 29 1 — 28 1 — 27 1 — 26 1 — 25 1 — 24 1 23 17 16 Undetermined — R/W R/W R/W R/W R/W R/W R/W R/W MAR2AE MAR2AR Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR2AH MAR2AL Note: Bit functions are the same as for DMAC0. 605 ETCR2A H/L—Execute Transfer Count Register 2A H/L Bit Initial value Read/Write Bit Initial value Read/Write R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 H'44, H'45 5 4 3 2 DMAC2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCR2AH Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCR2AL Note: Bit functions are the same as for DMAC0. IOAR2A—I/O Address Register 2A Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 H'46 2 1 DMAC2 0 Undetermined R/W R/W R/W R/W R/W Note: Bit functions are the same as for DMAC0. 606 DTCR2A—Data Transfer Control Register 2A • Short address mode Bit Initial value Read/Write 7 DTE 0 R/W 6 DTSZ 0 R/W 5 DTID 0 R/W 4 RPE 0 R/W 3 DTIE 0 R/W H'47 DMAC2 2 DTS2 0 R/W 1 DTS1 0 R/W 0 DTS0 0 R/W • Full address mode Bit Initial value Read/Write 7 DTE 0 R/W 6 DTSZ 0 R/W 5 SAID 0 R/W 4 SAIDE 0 R/W 3 DTIE 0 R/W 2 DTS2A 0 R/W 1 DTS1A 0 R/W 0 DTS0A 0 R/W Note: Bit functions are the same as for DMAC0. MAR2B R/E/H/L—Memory Address Register 2B R/E/H/L H'48, H'49, H'4A, H'4B 22 21 20 19 18 DMAC2 Bit Initial value Read/Write 31 1 — 30 1 — 29 1 — 28 1 — 27 1 — 26 1 — 25 1 — 24 1 23 17 16 Undetermined — R/W R/W R/W R/W R/W R/W R/W R/W MAR2BE MAR2BR Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR2BH MAR2BL Note: Bit functions are the same as for DMAC0. 607 ETCR2B H/L—Execute Transfer Count Register 2B H/L Bit Initial value Read/Write Bit Initial value Read/Write R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 H'4C, H'4D 5 4 3 2 DMAC2 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCR2BH Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCR2BL Note: Bit functions are the same as for DMAC0. IOAR2B—I/O Address Register 2B Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 H'4E 2 1 DMAC2 0 Undetermined R/W R/W R/W R/W R/W Note: Bit functions are the same as for DMAC0. 608 DTCR2B—Data Transfer Control Register 2B • Short address mode Bit Initial value Read/Write 7 DTE 0 R/W 6 DTSZ 0 R/W 5 DTID 0 R/W 4 RPE 0 R/W 3 DTIE 0 R/W H'4F DMAC2 2 DTS2 0 R/W 1 DTS1 0 R/W 0 DTS0 0 R/W • Full address mode Bit Initial value Read/Write 7 DTME 0 R/W 6 — 0 R/W 5 DAID 0 R/W 4 DAIDE 0 R/W 3 TMS 0 R/W 2 DTS2B 0 R/W 1 DTS1B 0 R/W 0 DTS0B 0 R/W Note: Bit functions are the same as for DMAC0. MAR3A R/E/H/L—Memory Address Register 3A R/E/H/L H'50, H'51, H'52, H'53 22 21 20 19 18 DMAC3 Bit Initial value Read/Write 31 1 — 30 1 — 29 1 — 28 1 — 27 1 — 26 1 — 25 1 — 24 1 23 17 16 Undetermined — R/W R/W R/W R/W R/W R/W R/W R/W MAR3AE MAR3AR Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR3AH MAR3AL Note: Bit functions are the same as for DMAC0. 609 ETCR3A H/L—Execute Transfer Count Register 3A H/L Bit Initial value Read/Write Bit Initial value Read/Write R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 H'54, H'55 5 4 3 2 DMAC3 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCR3AH Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCR3AL Note: Bit functions are the same as for DMAC0. IOAR3A—I/O Address Register 3A Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 H'56 2 1 DMAC3 0 Undetermined R/W R/W R/W R/W R/W Note: Bit functions are the same as for DMAC0. 610 DTCR3A—Data Transfer Control Register 3A • Short address mode Bit Initial value Read/Write 7 DTE 0 R/W 6 DTSZ 0 R/W 5 DTID 0 R/W 4 RPE 0 R/W 3 DTIE 0 R/W H'57 DMAC3 2 DTS2 0 R/W 1 DTS1 0 R/W 0 DTS0 0 R/W • Full address mode Bit Initial value Read/Write 7 DTE 0 R/W 6 DTSZ 0 R/W 5 SAID 0 R/W 4 SAIDE 0 R/W 3 DTIE 0 R/W 2 DTS2A 0 R/W 1 DTS1A 0 R/W 0 DTS0A 0 R/W Note: Bit functions are the same as for DMAC0. MAR3B R/E/H/L—Memory Address Register 3B R/E/H/L H'58, H'59, H'5A, H'5B 22 21 20 19 18 DMAC3 Bit Initial value Read/Write 31 1 — 30 1 — 29 1 — 28 1 — 27 1 — 26 1 — 25 1 — 24 1 23 17 16 Undetermined — R/W R/W R/W R/W R/W R/W R/W R/W MAR3BE MAR3BR Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undetermined Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MAR3BH MAR3BL Note: Bit functions are the same as for DMAC0. 611 ETCR3B H/L—Execute Transfer Count Register 3B H/L Bit Initial value Read/Write Bit Initial value Read/Write R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 H'5C, H'5D 5 4 3 2 DMAC3 1 0 Undetermined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCR3BH Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 2 1 0 Undetermined R/W R/W R/W R/W R/W ETCR3BL Note: Bit functions are the same as for DMAC0. IOAR3B—I/O Address Register 3B Bit Initial value Read/Write R/W R/W R/W 7 6 5 4 3 H'5E 2 1 DMAC3 0 Undetermined R/W R/W R/W R/W R/W Note: Bit functions are the same as for DMAC0. 612 DTCR3B—Data Transfer Control Register 3B • Short address mode Bit Initial value Read/Write 7 DTE 0 R/W 6 DTSZ 0 R/W 5 DTID 0 R/W 4 RPE 0 R/W 3 DTIE 0 R/W H'5F DMAC3 2 DTS2 0 R/W 1 DTS1 0 R/W 0 DTS0 0 R/W • Full address mode Bit Initial value Read/Write 7 DTME 0 R/W 6 — 0 R/W 5 DAID 0 R/W 4 DAIDE 0 R/W 3 TMS 0 R/W 2 DTS2B 0 R/W 1 DTS1B 0 R/W 0 DTS0B 0 R/W Note: Bit functions are the same as for DMAC0. 613 TSTR—Timer Start Register Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 STR4 0 R/W 3 STR3 0 R/W H'60 2 STR2 0 R/W ITU (all channels) 1 STR1 0 R/W 0 STR0 0 R/W Counter start 0 0 TCNT0 is halted 1 TCNT0 is counting Counter start 1 0 TCNT1 is halted 1 TCNT1 is counting Counter start 2 0 TCNT2 is halted 1 TCNT2 is counting Counter start 3 0 TCNT3 is halted 1 TCNT3 is counting Counter start 4 0 TCNT4 is halted 1 TCNT4 is counting 614 TSNC—Timer Synchro Register Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 SYNC4 0 R/W 3 SYNC3 0 R/W H'61 2 SYNC2 0 R/W ITU (all channels) 1 SYNC1 0 R/W 0 SYNC0 0 R/W Timer sync 0 0 TCNT0 operates independently 1 TCNT0 is synchronized Timer sync 1 0 TCNT1 operates independently 1 TCNT1 is synchronized Timer sync 2 0 TCNT2 operates independently 1 TCNT2 is synchronized Timer sync 3 0 TCNT3 operates independently 1 TCNT3 is synchronized Timer sync 4 0 TCNT4 operates independently 1 TCNT4 is synchronized 615 TMDR—Timer Mode Register Bit Initial value Read/Write 7 — 1 — 6 MDF 0 R/W 5 FDIR 0 R/W 4 PWM4 0 R/W 3 PWM3 0 R/W H'62 2 PWM2 0 R/W ITU (all channels) 1 PWM1 0 R/W 0 PWM0 0 R/W PWM mode 0 0 Channel 0 operates normally 1 Channel 0 operates in PWM mode PWM mode 1 0 Channel 1 operates normally 1 Channel 1 operates in PWM mode PWM mode 2 0 Channel 2 operates normally 1 Channel 2 operates in PWM mode PWM mode 3 0 Channel 3 operates normally 1 Channel 3 operates in PWM mode PWM mode 4 0 Channel 4 operates normally 1 Channel 4 operates in PWM mode Flag direction 0 OVF is set to 1 in TSR2 when TCNT2 overflows or underflows 1 OVF is set to 1 in TSR2 when TCNT2 overflows Phase counting mode flag 0 Channel 2 operates normally 1 Channel 2 operates in phase counting mode 616 TFCR—Timer Function Control Register Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 CMD1 0 R/W 4 CMD0 0 R/W 3 BFB4 0 R/W H'63 2 BFA4 0 R/W ITU (all channels) 1 BFB3 0 R/W 0 BFA3 0 R/W Buffer mode A3 0 GRA3 operates normally 1 GRA3 is buffered by BRA3 Buffer mode B3 0 GRB3 operates normally 1 GRB3 is buffered by BRB3 Buffer mode A4 0 GRA4 operates normally 1 GRA4 is buffered by BRA4 Buffer mode B4 0 GRB4 operates normally 1 GRB4 is buffered by BRB4 Combination mode 1 and 0 Bit 5 Bit 4 CMD1 CMD0 Operating Mode of Channels 3 and 4 0 0 Channels 3 and 4 operate normally 1 0 1 Channels 3 and 4 operate together in complementary PWM mode 1 Channels 3 and 4 operate together in reset-synchronized PWM mode 617 TCR0—Timer Control Register 0 Bit Initial value Read/Write 7 — 1 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W H'64 2 TPSC2 0 R/W 1 TPSC1 0 R/W ITU0 0 TPSC0 0 R/W CKEG1 CKEG0 Timer prescaler 2 to 0 Bit 2 Bit 0 Bit 1 TPSC2 TPSC1 TPSC0 0 0 0 1 0 1 1 0 0 1 1 0 1 1 Clock edge 1 and 0 Bit 4 Bit 3 CKEG1 CKEG0 0 0 1 1 — Counted Edges of External Clock Rising edges counted Falling edges counted Both edges counted TCNT Clock Source Internal clock: ø Internal clock: ø/2 Internal clock: ø/4 Internal clock: ø/8 External clock A: TCLKA input External clock B: TCLKB input External clock C: TCLKC input External clock D: TCLKD input Counter clear 1 and 0 Bit 6 Bit 5 CCLR1 CCLR0 TCNT Clear Source 0 0 TCNT is not cleared 1 TCNT is cleared by GRA compare match or input capture 1 0 TCNT is cleared by GRB compare match or input capture 1 Synchronous clear: TCNT is cleared in synchronization with other synchronized timers 618 TIOR0—Timer I/O Control Register 0 Bit Initial value Read/Write 7 — 1 — 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 — 1 — H'65 2 IOA2 0 R/W 1 IOA1 0 R/W ITU0 0 IOA0 0 R/W I/O control A2 to A0 Bit 2 Bit 1 Bit 0 IOA2 IOA1 IOA0 0 0 0 1 0 1 1 0 0 1 1 0 1 1 I/O control B2 to B0 Bit 6 Bit 5 Bit 4 IOB2 IOB1 IOB0 0 0 0 1 0 1 1 0 0 1 1 0 1 1 GRA Function GRA is an output compare register GRA is an input capture register No output at compare match 0 output at GRA compare match 1 output at GRA compare match Output toggles at GRA compare match GRA captures rising edge of input GRA captures falling edge of input GRA captures both edges of input GRB Function GRB is an output compare register GRB is an input capture register No output at compare match 0 output at GRB compare match 1 output at GRB compare match Output toggles at GRB compare match GRB captures rising edge of input GRB captures falling edge of input GRB captures both edges of input 619 TIER0—Timer Interrupt Enable Register 0 Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — H'66 2 OVIE 0 R/W 1 IMIEB 0 R/W ITU0 0 IMIEA 0 R/W Input capture/compare match interrupt enable A 0 IMIA interrupt requested by IMFA is disabled 1 IMIA interrupt requested by IMFA is enabled Input capture/compare match interrupt enable B 0 IMIB interrupt requested by IMFB is disabled 1 IMIB interrupt requested by IMFB is enabled Overflow interrupt enable 0 OVI interrupt requested by OVF is disabled 1 OVI interrupt requested by OVF is enabled 620 TSR0—Timer Status Register 0 Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — H'67 2 OVF 0 R/(W)* 1 IMFB 0 R/(W)* ITU0 0 IMFA 0 R/(W)* Input capture/compare match flag A 0 [Clearing condition] Read IMFA when IMFA = 1, then write 0 in IMFA 1 [Setting conditions] TCNT = GRA when GRA functions as a compare match register. TCNT value is transferred to GRA by an input capture signal, when GRA functions as an input capture register. Input capture/compare match flag B 0 [Clearing condition] Read IMFB when IMFB = 1, then write 0 in IMFB 1 [Setting conditions] TCNT = GRB when GRB functions as a compare match register. TCNT value is transferred to GRB by an input capture signal, when GRB functions as an input capture register. Overflow flag 0 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 1 [Setting condition] TCNT overflowed from H'FFFF to H'0000 Note: * Only 0 can be written, to clear the flag. 621 TCNT0 H/L—Timer Counter 0 H/L Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 H'68, H'69 5 0 4 0 3 0 2 0 1 0 ITU0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter GRA0 H/L—General Register A0 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 H'6A, H'6B 5 1 4 1 3 1 2 1 1 1 ITU0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Output compare or input capture register GRB0 H/L—General Register B0 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 H'6C, H'6D 5 1 4 1 3 1 2 1 1 1 ITU0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Output compare or input capture register TCR1—Timer Control Register 1 Bit Initial value Read/Write 7 — 1 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W H'6E 2 TPSC2 0 R/W 1 TPSC1 0 R/W ITU1 0 TPSC0 0 R/W CKEG1 CKEG0 Note: Bit functions are the same as for ITU0. 622 TIOR1—Timer I/O Control Register 1 Bit Initial value Read/Write 7 — 1 — 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 — 1 — H'6F 2 IOA2 0 R/W 1 IOA1 0 R/W ITU1 0 IOA0 0 R/W Note: Bit functions are the same as for ITU0. TIER1—Timer Interrupt Enable Register 1 Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — H'70 2 OVIE 0 R/W 1 IMIEB 0 R/W ITU1 0 IMIEA 0 R/W Note: Bit functions are the same as for ITU0. TSR1—Timer Status Register 1 Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — H'71 2 OVF 0 R/(W)* 1 IMFB 0 R/(W)* ITU1 0 IMFA 0 R/(W)* Notes: Bit functions are the same as for ITU0. * Only 0 can be written, to clear the flag. TCNT1 H/L—Timer Counter 1 H/L Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 H'72, H'73 5 0 4 0 3 0 2 0 1 0 ITU1 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for ITU0. 623 GRA1 H/L—General Register A1 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 H'74, H'75 5 1 4 1 3 1 2 1 1 1 ITU1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for ITU0. GRB1 H/L—General Register B1 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 H'76, H'77 5 1 4 1 3 1 2 1 1 1 ITU1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for ITU0. TCR2—Timer Control Register 2 Bit Initial value Read/Write 7 — 1 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W H'78 2 TPSC2 0 R/W 1 TPSC1 0 R/W ITU2 0 TPSC0 0 R/W CKEG1 CKEG0 Notes: 1. Bit functions are the same as for ITU0. 2. When channel 2 is used in phase counting mode, the counter clock source selection by bits TPSC2 to TPSC0 is ignored. 624 TIOR2—Timer I/O Control Register 2 Bit Initial value Read/Write 7 — 1 — 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 — 1 — H'79 2 IOA2 0 R/W 1 IOA1 0 R/W ITU2 0 IOA0 0 R/W Note: Bit functions are the same as for ITU0. 625 TIER2—Timer Interrupt Enable Register 2 Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — H'7A 2 OVIE 0 R/W 1 IMIEB 0 R/W ITU2 0 IMIEA 0 R/W Note: Bit functions are the same as for ITU0. TSR2—Timer Status Register 2 Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — H'7B 2 OVF 0 R/(W)* 1 IMFB 0 R/(W)* ITU2 0 IMFA 0 R/(W)* Overflow flag Bit functions are the same as for ITU0. 0 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 1 [Setting condition] TCNT overflowed from H'FFFF to H'0000 or underflowed from H'0000 to H'FFFF Note: * Only 0 can be written, to clear the flag. TCNT2 H/L—Timer Counter 2 H/L Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 H'7C, H'7D 5 0 4 0 3 0 2 0 1 0 ITU2 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Phase counting mode: up/down counter Other modes: up-counter 626 GRA2 H/L—General Register A2 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 H'7E, H'7F 5 1 4 1 3 1 2 1 1 1 ITU2 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for ITU0. GRB2 H/L—General Register B2 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 H'80, H'81 5 1 4 1 3 1 2 1 1 1 ITU2 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for ITU0. TCR3—Timer Control Register 3 Bit Initial value Read/Write 7 — 1 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 CLEG0 0 R/W H'82 2 TPSC2 0 R/W 1 TPSC1 0 R/W ITU3 0 TPSC0 0 R/W Note: Bit functions are the same as for ITU0. TIOR3—Timer I/O Control Register 3 Bit Initial value Read/Write 7 — 1 — 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 — 1 — H'83 2 IOA2 0 R/W 1 IOA1 0 R/W ITU3 0 IOA0 0 R/W Note: Bit functions are the same as for ITU0. 627 TIER3—Timer Interrupt Enable Register 3 Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — H'84 2 OVIE 0 R/W 1 IMIEB 0 R/W ITU3 0 IMIEA 0 R/W Note: Bit functions are the same as for ITU0. TSR3—Timer Status Register 3 Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — H'85 2 OVF 0 R/(W)* 1 IMFB 0 R/(W)* ITU3 0 IMFA 0 R/(W)* Overflow flag Bit functions are the same as for ITU0 0 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 1 [Setting condition] TCNT overflowed from H'FFFF to H'0000 or underflowed from H'0000 to H'FFFF Note: * Only 0 can be written, to clear the flag. TCNT3 H/L—Timer Counter 3 H/L Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 H'86, H'87 5 0 4 0 3 0 2 0 1 0 ITU3 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Complementary PWM mode: up/down counter Other modes: up-counter 628 GRA3 H/L—General Register A3 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 H'88, H'89 5 1 4 1 3 1 2 1 1 1 ITU3 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Output compare or input capture register (can be buffered) GRB3 H/L—General Register B3 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 H'8A, H'8B 5 1 4 1 3 1 2 1 1 1 ITU3 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Output compare or input capture register (can be buffered) BRA3 H/L—Buffer Register A3 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 H'8C, H'8D 5 1 4 1 3 1 2 1 1 1 ITU3 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Used to buffer GRA BRB3 H/L—Buffer Register B3 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 H'8E, H'8F 5 1 4 1 3 1 2 1 1 1 ITU3 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Used to buffer GRB 629 TOER—Timer Output Enable Register Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 EXB4 1 R/W 4 EXA4 1 R/W 3 EB3 1 R/W H'90 2 EB4 1 R/W ITU (all channels) 1 EA4 1 R/W 0 EA3 1 R/W Master enable TIOCA3 0 TIOCA 3 output is disabled regardless of TIOR3, TMDR, and TFCR settings 1 TIOCA 3 is enabled for output according to TIOR3, TMDR, and TFCR settings Master enable TIOCA4 0 TIOCA 4 output is disabled regardless of TIOR4, TMDR, and TFCR settings 1 TIOCA 4 is enabled for output according to TIOR4, TMDR, and TFCR settings Master enable TIOCB4 0 TIOCB4 output is disabled regardless of TIOR4 and TFCR settings 1 TIOCB4 is enabled for output according to TIOR4 and TFCR settings Master enable TIOCB3 0 TIOCB 3 output is disabled regardless of TIOR3 and TFCR settings 1 TIOCB 3 is enabled for output according to TIOR3 and TFCR settings Master enable TOCXA4 0 TOCXA 4 output is disabled regardless of TFCR settings 1 TOCXA 4 is enabled for output according to TFCR settings Master enable TOCXB4 0 TOCXB4 output is disabled regardless of TFCR settings 1 TOCXB4 is enabled for output according to TFCR settings 630 TOCR—Timer Output Control Register Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 XTGD 1 R/W 3 — 1 — H'91 2 — 1 — ITU (all channels) 1 OLS4 1 R/W 0 OLS3 1 R/W Output level select 3 0 TIOCB 3 , TOCXA 4 , and TOCXB 4 outputs are inverted 1 TIOCB 3 , TOCXA 4 , and TOCXB 4 outputs are not inverted Output level select 4 0 TIOCA 3 , TIOCA 4, and TIOCB4 outputs are inverted 1 TIOCA 3 , TIOCA 4, and TIOCB4 outputs are not inverted External trigger disable 0 Input capture A in channel 1 is used as an external trigger signal in reset-synchronized PWM mode and complementary PWM mode * 1 External triggering is disabled Note: * When an external trigger occurs, bits 5 to 0 in TOER are cleared to 0, disabling ITU output. 631 TCR4—Timer Control Register 4 Bit Initial value Read/Write 7 — 1 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W H'92 2 TPSC2 0 R/W 1 TPSC1 0 R/W ITU4 0 TPSC0 0 R/W CKEG1 CKEG0 Note: Bit functions are the same as for ITU0. TIOR4—Timer I/O Control Register 4 Bit Initial value Read/Write 7 — 1 — 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 — 1 — H'93 2 IOA2 0 R/W 1 IOA1 0 R/W ITU4 0 IOA0 0 R/W Note: Bit functions are the same as for ITU0. TIER4—Timer Interrupt Enable Register 4 Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — H'94 2 OVIE 0 R/W 1 IMIEB 0 R/W ITU4 0 IMIEA 0 R/W Note: Bit functions are the same as for ITU0. TSR4—Timer Status Register 4 Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — H'95 2 OVF 0 R/(W)* 1 IMFB 0 R/(W)* ITU4 0 IMFA 0 R/(W)* Notes: Bit functions are the same as for ITU0. * Only 0 can be written, to clear the flag. 632 TCNT4 H/L—Timer Counter 4 H/L Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 H'96, H'97 5 0 4 0 3 0 2 0 1 0 ITU4 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for ITU3. GRA4 H/L—General Register A4 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 H'98, H'99 5 1 4 1 3 1 2 1 1 1 ITU4 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for ITU3. GRB4 H/L—General Register B4 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 H'9A, H'9B 5 1 4 1 3 1 2 1 1 1 ITU4 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for ITU3. BRA4 H/L—Buffer Register A4 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 H'9C, H'9D 5 1 4 1 3 1 2 1 1 1 ITU4 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for ITU3. 633 BRB4 H/L—Buffer Register B4 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 H'9E, H'9F 5 1 4 1 3 1 2 1 1 1 ITU4 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for ITU3. TPMR—TPC Output Mode Register Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 0 R/W H'A0 2 0 R/W 1 0 R/W 0 0 TPC G3NOV G2NOV G1NOV G0NOV R/W Group 0 non-overlap 0 Normal TPC output in group 0. Output values change at compare match A in the selected ITU channel. 1 Non-overlapping TPC output in group 0, controlled by compare match A and B in the selected ITU channel Group 1 non-overlap 0 Normal TPC output in group 1. Output values change at compare match A in the selected ITU channel. 1 Non-overlapping TPC output in group 1, controlled by compare match A and B in the selected ITU channel Group 2 non-overlap 0 Normal TPC output in group 2. Output values change at compare match A in the selected ITU channel. 1 Non-overlapping TPC output in group 2, controlled by compare match A and B in the selected ITU channel Group 3 non-overlap 0 Normal TPC output in group 3. Output values change at compare match A in the selected ITU channel. 1 Non-overlapping TPC output in group 3, controlled by compare match A and B in the selected ITU channel 634 TPCR—TPC Output Control Register Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'A1 2 1 R/W 1 1 R/W 0 1 TPC G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 R/W Group 0 compare match select 1 and 0 Bit 1 Bit 0 G0CMS1 G0CMS0 0 0 1 1 0 1 ITU Channel Selected as Output Trigger TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 0 TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 1 TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 2 TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 3 Group 1 compare match select 1 and 0 Bit 3 Bit 2 G1CMS1 G1CMS0 0 0 1 1 0 1 ITU Channel Selected as Output Trigger TPC output group 1 (TP7 to TP4 ) is triggered by compare match in ITU channel 0 TPC output group 1 (TP7 to TP4 ) is triggered by compare match in ITU channel 1 TPC output group 1 (TP7 to TP4 ) is triggered by compare match in ITU channel 2 TPC output group 1 (TP7 to TP4 ) is triggered by compare match in ITU channel 3 Group 2 compare match select 1 and 0 Bit 5 Bit 4 G2CMS1 G2CMS0 0 0 1 1 0 1 ITU Channel Selected as Output Trigger TPC output group 2 (TP11 to TP8 ) is triggered by compare match in ITU channel 0 TPC output group 2 (TP11 to TP8 ) is triggered by compare match in ITU channel 1 TPC output group 2 (TP11 to TP8 ) is triggered by compare match in ITU channel 2 TPC output group 2 (TP11 to TP8 ) is triggered by compare match in ITU channel 3 Group 3 compare match select 1 and 0 Bit 7 Bit 6 G3CMS1 G3CMS0 0 0 1 1 0 1 ITU Channel Selected as Output Trigger TPC output group 3 (TP15 to TP12) is triggered by compare match in ITU channel 0 TPC output group 3 (TP15 to TP12) is triggered by compare match in ITU channel 1 TPC output group 3 (TP15 to TP12) is triggered by compare match in ITU channel 2 TPC output group 3 (TP15 to TP12) is triggered by compare match in ITU channel 3 635 NDERB—Next Data Enable Register B Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'A2 2 0 R/W 1 0 R/W TPC 0 NDER8 0 R/W NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 Next data enable 15 to 8 Bits 7 to 0 NDER15 to NDER8 Description 0 TPC outputs TP15 to TP8 are disabled (NDR15 to NDR8 are not transferred to PB 7 to PB 0 ) TPC outputs TP15 to TP8 are enabled 1 (NDR15 to NDR8 are transferred to PB 7 to PB 0 ) NDERA—Next Data Enable Register A Bit Initial value Read/Write 7 NDER7 0 R/W 6 NDER6 0 R/W 5 NDER5 0 R/W 4 0 R/W 3 0 R/W H'A3 2 NDER2 0 R/W 1 NDER1 0 R/W TPC 0 NDER0 0 R/W NDER4 NDER3 Next data enable 7 to 0 Bits 7 to 0 NDER7 to NDER0 Description 0 TPC outputs TP 7 to TP0 are disabled (NDR7 to NDR0 are not transferred to PA 7 to PA 0) TPC outputs TP 7 to TP0 are enabled 1 (NDR7 to NDR0 are transferred to PA 7 to PA 0) 636 NDRB—Next Data Register B • Same output trigger for TPC output groups 2 and 3 H'A4/H'A6 TPC Address H'FFA4 Bit Initial value Read/Write 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Next output data for TPC output group 3 Next output data for TPC output group 2 Address H'FFA6 Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — • Different output triggers for TPC output groups 2 and 3 Address H'FFA4 Bit Initial value Read/Write 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Next output data for TPC output group 3 Address H'FFA6 Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Next output data for TPC output group 2 637 NDRA—Next Data Register A • Same output trigger for TPC output groups 0 and 1 H'A5/H'A7 TPC Address H'FFA5 Bit Initial value Read/Write 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Next output data for TPC output group 1 Next output data for TPC output group 0 Address H'FFA7 Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — • Different output triggers for TPC output groups 0 and 1 Address H'FFA5 Bit Initial value Read/Write 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Next output data for TPC output group 1 Address H'FFA7 Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Next output data for TPC output group 0 638 TCSR—Timer Control/Status Register Bit Initial value Read/Write 7 OVF 0 R/(W)* 6 WT/ IT 0 R/W 5 TME 0 R/W 4 — 1 — 3 — 1 — H'A8 2 CKS2 0 R/W 1 CKS1 0 R/W WDT 0 CKS0 0 R/W Timer enable 0 Timer disabled • TCNT is initialized to H'00 and halted 1 Timer enabled • TCNT is counting • CPU interrupt requests are enabled Timer mode select 0 Interval timer: requests interval timer interrupts 1 Watchdog timer: generates a reset signal Overflow flag 0 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 1 [Setting condition] TCNT changes from H'FF to H'00 Clock select 2 to 0 0 0 0 1 0 1 1 0 0 1 1 0 1 1 ø/2 ø/32 ø/64 ø/128 ø/256 ø/512 ø/2048 ø/4096 Note: * Only 0 can be written, to clear the flag. 639 TCNT—Timer Counter H'A9 (read), H'A8 (write) 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W WDT Bit Initial value Read/Write 7 0 R/W 0 0 R/W Count value RSTCSR—Reset Control/Status Register H'AB (read), H'AA (write) 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — WDT Bit Initial value Read/Write 7 WRST 0 R/(W)* 6 RSTOE 0 R/W 5 — 1 — 0 — 1 — Reset output enable 0 Reset signal is not output externally 1 Reset signal is output externally Watchdog timer reset 0 [Clearing condition] Reset signal input at RES pin, or 0 written by software 1 [Setting condition] TCNT overflow generates a reset signal Note: * Only 0 can be written in bit 7, to clear the flag. 640 RFSHCR—Refresh Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 M9/M8 0 R/W H'AC 2 RFSHE 0 R/W Refresh controller 1 — 1 — 0 RCYCE 0 R/W SRFMD PSRAME DRAME CAS/WE Refresh cycle enable 0 Refresh cycles are disabled 1 Refresh cycles are enabled for area 3 Refresh pin enable 0 Refresh signal output at the RFSH pin is disabled 1 Refresh signal output at the RFSH pin is enabled Address multiplex mode select 0 8-bit column address mode 1 9-bit column address mode Strobe mode select 0 2 WE mode 1 2 CAS mode PSRAM enable, DRAM enable Bit 6 Bit 5 PSRAME DRAME RAM Interface 0 0 Can be used as an interval timer 1 DRAM can be connected 1 0 PSRAM can be connected 1 Illegal setting Self-refresh mode 0 DRAM or PSRAM self-refresh is disabled in software standby mode 1 DRAM or PSRAM self-refresh is enabled in software standby mode 641 RTMCSR—Refresh Timer Control/Status Register Bit Initial value Read/Write 7 CMF 0 R/(W)* 6 CMIE 0 R/W 5 CKS2 0 R/W 4 CKS1 0 R/W 3 CKS0 0 R/W H'AD 2 — 1 — Refresh controller 1 — 1 — 0 — 1 — Clock select 2 to 0 Bit 5 Bit 4 Bit 3 CKS2 CKS1 CKS0 0 0 0 1 0 1 1 0 0 1 1 0 1 1 Counter Clock Source Clock input is disabled ø/2 ø/8 ø/32 ø/128 ø/512 ø/2048 ø/4096 Compare match interrupt enable 0 The CMI interrupt requested by CMF is disabled 1 The CMI interrupt requested by CMF is enabled Compare match flag 0 [Clearing condition] Read CMF when CMF = 1, then write 0 in CMF 1 [Setting condition] RTCNT = RTCOR Note: * Only 0 can be written, to clear the flag. 642 RTCNT—Refresh Timer Counter Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'AE 2 0 R/W Refresh controller 1 0 R/W 0 0 R/W Count value RTCOR—Refresh Time Constant Register Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'AF 2 1 R/W Refresh controller 1 1 R/W 0 1 R/W Interval at which RTCNT is cleared 643 SMR—Serial Mode Register Bit Initial value Read/Write 7 C/ A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 7 O/ E 0 R/W 3 STOP 0 R/W H'B0 2 MP 0 R/W 1 CKS1 0 R/W 0 SCI0 CKS0 0 R/W Multiprocessor mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop bit length 0 One stop bit 1 Two stop bits Parity mode 0 Even parity 1 Odd parity Parity enable 0 Parity bit is not added or checked 1 Parity bit is added and checked Character length 0 8-bit data 1 7-bit data Communication mode 0 Asynchronous mode 1 Synchronous mode Clock select 1 and 0 Bit 1 Bit 0 CKS1 CKS0 Clock Source 0 0 ø clock 1 ø/4 clock 0 1 ø/16 clock 1 ø/64 clock 644 BRR—Bit Rate Register Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'B1 2 1 R/W 1 1 R/W SCI0 0 1 R/W Serial communication bit rate setting 645 SCR—Serial Control Register Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W H'B2 2 TEIE 0 R/W 1 CKE1 0 R/W 0 SCI0 CKE0 0 R/W Clock enable 1 and 0 Bit 1 Bit 0 CKE1 CKE0 Clock Selection and Output 0 Asynchronous mode Internal clock, SCK pin available for generic input 0 output Synchronous mode Internal clock, SCK pin used for serial clock output Asynchronous mode Internal clock, SCK pin used for clock output 1 Synchronous mode Internal clock, SCK pin used for serial clock output Asynchronous mode External clock, SCK pin used for clock input 1 0 Synchronous mode External clock, SCK pin used for serial clock input Asynchronous mode External clock, SCK pin used for clock input 1 Synchronous mode External clock, SCK pin used for serial clock input Transmit-end interrupt enable 0 Transmit-end interrupt requests (TEI) are disabled 1 Transmit-end interrupt requests (TEI) are enabled Multiprocessor interrupt enable 0 Multiprocessor interrupts are disabled (normal receive operation) 1 Multiprocessor interrupts are enabled Transmit enable 0 Transmitting is disabled 1 Transmitting is enabled Receive enable 0 Transmitting is disabled 1 Transmitting is enabled Receive interrupt enable 0 Receive-end (RXI) and receive-error (ERI) interrupt requests are disabled 1 Receive-end (RXI) and receive-error (ERI) interrupt requests are enabled Transmit interrupt enable 0 Transmit-data-empty interrupt request (TXI) is disabled 1 Transmit-data-empty interrupt request (TXI) is enabled 646 TDR—Transmit Data Register Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'B3 2 1 R/W 1 1 R/W SCI0 0 1 R/W Serial transmit data 647 SSR—Serial Status Register Bit Initial value Read/Write 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* H'B4 2 TEND 1 R 1 MPB 0 R SCI0 0 MPBT 0 R/W Multiprocessor bit 0 Multiprocessor bit value in receive data is 0 1 Transmit end 0 Multiprocessor bit value in receive data is 1 Multiprocessor bit transfer 0 Multiprocessor bit value in transmit data is 0 1 Multiprocessor bit value in transmit data is 1 [Clearing conditions] Read TDRE when TDRE = 1, then write 0 in TDRE. The DMAC writes data in TDR. [Setting conditions] Reset or transition to standby mode. TE is cleared to 0 in SCR. TDRE is 1 when last bit of serial character is transmitted. Parity error 0 [Clearing conditions] Reset or transition to standby mode. Read PER when PER = 1, then write 0 in PER. [Setting condition] Parity error: (parity of receive data does not match parity setting of O/ E in SMR) [Clearing conditions] Reset or transition to standby mode. Read ORER when ORER = 1, then write 0 in ORER. [Setting condition] Overrun error (reception of next serial data ends when RDRF = 1) 1 Framing error 0 [Clearing conditions] Reset or transition to standby mode. Read FER when FER = 1, then write 0 in FER. [Setting condition] Framing error (stop bit is 0) 1 1 Overrun error Receive data register full 0 [Clearing conditions] Reset or transition to standby mode. Read RDRF when RDRF = 1, then write 0 in RDRF. The DMAC reads data from RDR. [Setting condition] Serial data is received normally and transferred from RSR to RDR 0 1 1 Transmit data register empty 0 [Clearing conditions] Read TDRE when TDRE = 1, then write 0 in TDRE. The DMAC writes data in TDR. [Setting conditions] Reset or transition to standby mode. TE is 0 in SCR Data is transferred from TDR to TSR, enabling new data to be written in TDR. 1 Note: * Only 0 can be written, to clear the flag. 648 RDR—Receive Data Register Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R H'B5 2 0 R 1 0 R SCI0 0 0 R Serial receive data SMR—Serial Mode Register Bit Initial value Read/Write 7 C/ A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/ E 0 R/W 3 STOP 0 R/W H'B8 2 MP 0 R/W 1 CKS1 0 R/W SCI1 0 CKS0 0 R/W Note: Bit functions are the same as for SCI0. BRR—Bit Rate Register Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'B9 2 1 R/W 1 1 R/W SCI1 0 1 R/W Note: Bit functions are the same as for SCI0. SCR—Serial Control Register Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W H'BA 2 TEIE 0 R/W 1 CKE1 0 R/W SCI1 0 CKE0 0 R/W Note: Bit functions are the same as for SCI0. 649 TDR—Transmit Data Register Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'BB 2 1 R/W 1 1 R/W SCI1 0 1 R/W Note: Bit functions are the same as for SCI0. SSR—Serial Status Register Bit Initial value Read/Write 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* H'BC 2 TEND 1 R 1 MPB 0 R SCI1 0 MPBT 0 R/W Notes: Bit functions are the same as for SCI0. * Only 0 can be written, to clear the flag. RDR—Receive Data Register Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R H'BD 2 0 R 1 0 R SCI1 0 0 R Note: Bit functions are the same as for SCI0. 650 P4DDR—Port 4 Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W H'C5 2 0 W 1 0 W Port 4 0 0 W P4 7 DDR P4 6 DDR P4 5 DDR P4 4 DDR P4 3 DDR P4 2 DDR P4 1 DDR P4 0 DDR Port 4 input/output select 0 Generic input pin 1 Generic output pin P4DR—Port 4 Data Register Bit Initial value Read/Write 7 P4 7 0 R/W 6 P4 6 0 R/W 5 P4 5 0 R/W 4 P4 4 0 R/W 3 P4 3 0 R/W H'C7 2 P4 2 0 R/W 1 P4 1 0 R/W Port 4 0 P4 0 0 R/W Data for port 4 pins P5DDR—Port 5 Data Direction Register Bit Mode Initial value 1, 2 Read/Write Mode Initial value 3, 4 Read/Write 7 0 W 1 — 6 0 W 1 — 5 0 W 1 — 4 0 W 1 — 3 1 — 1 — H'C8 2 1 — 1 — 1 1 — 1 — Port 5 0 1 — 1 — P5 7 DDR P5 6 DDR P5 5 DDR P5 4 DDR P5 3 DDR P5 2 DDR P5 1 DDR P5 0 DDR Port 5 input/output select 0 Generic input 1 Generic output 651 P6DDR—Port 6 Data Direction Register Bit Initial value Read/Write 7 — 1 — 6 0 W 5 0 W 4 0 W 3 0 W H'C9 2 0 W 1 0 W Port 6 0 0 W P6 6 DDR P6 5 DDR P6 4 DDR P6 3 DDR P6 2 DDR P6 1 DDR P6 0 DDR Port 6 input/output select 0 Generic input 1 Generic output P5DR—Port 5 Data Register Bit Initial value Read/Write 7 P5 7 0 R/W 6 P5 6 0 R/W 5 P5 5 0 R/W 4 P5 4 0 R/W 3 P5 3 0 R/W H'CA 2 P5 2 0 R/W 1 P5 1 0 R/W Port 5 0 P5 0 0 R/W Data for port 5 pins P6DR—Port 6 Data Register Bit Initial value Read/Write 7 — 1 — 6 P6 6 0 R/W 5 P6 5 0 R/W 4 P6 4 0 R/W 3 P6 3 0 R/W H'CB 2 P6 2 0 R/W 1 P6 1 0 R/W Port 6 0 P6 0 0 R/W Data for port 6 pins 652 P8DDR—Port 8 Data Direction Register Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 1 W 3 0 W H'CD 2 0 W 1 0 W Port 8 0 0 W P8 4 DDR P8 3 DDR P8 2 DDR P8 1 DDR P8 0 DDR Port 8 input/output select 0 Generic input 1 CS output Port 8 input/output select 0 Generic input 1 Generic output P7DR—Port 7 Data Register Bit Initial value Read/Write 7 P77 —* R 6 P76 —* R 5 P75 —* R 4 P74 —* R 3 P73 —* R H'CE 2 P72 —* R 1 P71 —* R Port 7 0 P70 —* R Data for port 7 pins Note: * Determined by pins P7 7 to P7 0 . P8DR—Port 8 Data Register Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 P8 4 0 R/W 3 P8 3 0 R/W H'CF 2 P8 2 0 R/W 1 P8 1 0 R/W Port 8 0 P8 0 0 R/W Data for port 8 pins 653 P9DDR—Port 9 Data Direction Register Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 0 W 4 0 W 3 0 W H'D0 2 0 W 1 0 W Port 9 0 0 W P9 5 DDR P9 4 DDR P9 3 DDR P9 2 DDR P9 1 DDR P9 0 DDR Port 9 input/output select 0 Generic input 1 Generic output PADDR—Port A Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W H'D1 2 0 W 1 0 W Port A 0 0 W PA7 DDR PA6 DDR PA5 DDR PA4 DDR PA3 DDR PA2 DDR PA1 DDR PA0 DDR Port A input/output select 0 Generic input 1 Generic output P9DR—Port 9 Data Register Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 P9 5 0 R/W 4 P9 4 0 R/W 3 P9 3 0 R/W H'D2 2 P9 2 0 R/W 1 P9 1 0 R/W Port 9 0 P9 0 0 R/W Data for port 9 pins 654 PADR—Port A Data Register Bit Initial value Read/Write 7 PA 7 0 R/W 6 PA 6 0 R/W 5 PA 5 0 R/W 4 PA 4 0 R/W 3 PA 3 0 R/W H'D3 2 PA 2 0 R/W 1 PA 1 0 R/W Port A 0 PA 0 0 R/W Data for port A pins PBDDR—Port B Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W H'D4 2 0 W 1 0 W Port B 0 0 W PB7 DDR PB6 DDR PB5 DDR PB4 DDR PB3 DDR PB2 DDR PB1 DDR PB0 DDR Port B input/output select 0 Generic input 1 Generic output PCDDR—Port C Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W H'D5 2 0 W 1 0 W Port C 0 0 W PC7 DDR PC6 DDR PC5 DDR PC4 DDR PC3 DDR PC2 DDR PC1 DDR PC0 DDR Port C input/output select 0 Generic input 1 CS output Port C input/output select 0 Generic input 1 Generic output 655 PBDR—Port B Data Register Bit Initial value Read/Write 7 PB 7 0 R/W 6 PB 6 0 R/W 5 PB 5 0 R/W 4 PB 4 0 R/W 3 PB 3 0 R/W H'D6 2 PB 2 0 R/W 1 PB 1 0 R/W Port B 0 PB 0 0 R/W Data for port B pins PCDR—Port C Data Register Bit Initial value Read/Write 7 PC 7 0 R/W 6 PC 6 0 R/W 5 PC 5 0 R/W 4 PC 4 0 R/W 3 PC 3 0 R/W H'D7 2 PC 2 0 R/W 1 PC 1 0 R/W Port C 0 PC 0 0 R/W Data for port C pins P4PCR—Port 4 Input Pull-Up Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'DA 2 0 R/W 1 0 R/W Port 4 0 0 R/W P4 7 PCR P4 6 PCR P4 5 PCR P4 4 PCR P4 3 PCR P4 2 PCR P4 1 PCR P4 0 PCR Port 4 input pull-up control 7 to 0 0 Input pull-up transistor is off 1 Input pull-up transistor is on Note: Valid when the corresponding P4DDR bit is cleared to 0 (designating generic input). 656 P5PCR—Port 5 Input Pull-Up Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'DB 2 0 R/W 1 0 R/W Port 5 0 0 R/W P5 7 PCR P5 6 PCR P5 5 PCR P5 4 PCR P5 3 PCR P5 2 PCR P5 1 PCR P5 0 PCR Port 5 input pull-up control 7 to 4 0 Input pull-up transistor is off 1 Input pull-up transistor is on Note: Valid when the corresponding P5DDR bit is cleared to 0 (designating generic input). ADDRA H/L—A/D Data Register A H/L Bit Initial value Read/Write 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R H'E0, H'E1 5 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R A/D 0 — 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — ADDRAH A/D conversion data 10-bit data giving an A/D conversion result ADDRAL Reserved bits 657 ADDRB H/L—A/D Data Register B H/L Bit Initial value Read/Write 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R H'E2, H'E3 5 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R A/D 0 — 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — ADDRBH A/D conversion data 10-bit data giving an A/D conversion result ADDRBL Reserved bits ADDRC H/L—A/D Data Register C H/L Bit Initial value Read/Write 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R H'E4, H'E5 5 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R A/D 0 — 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — ADDRCH A/D conversion data 10-bit data giving an A/D conversion result ADDRCL Reserved bits ADDRD H/L—A/D Data Register D H/L Bit Initial value Read/Write 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R H'E6, H'E7 5 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R A/D 0 — 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — ADDRDH A/D conversion data 10-bit data giving an A/D conversion result ADDRDL Reserved bits 658 ADCR—A/D Control Register Bit Initial value Read/Write 7 TRGE 0 R/W 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — H'E9 2 — 1 — 1 — 1 — 0 — 1 — A/D Trigger enable 0 A/D conversion cannot be externally triggered 1 A/D conversion starts at the fall of the external trigger signal (ADTRG ) 659 ADCSR—A/D Control/Status Register Bit Initial value Read/Write 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W H'E8 2 CH2 0 R/W 1 CH1 0 R/W 0 A/D CH0 0 R/W Clock select 0 Conversion time = 266 states (maximum) 1 Conversion time = 134 states (maximum) Channel select 2 to 0 Channel Group Selection Selection CH2 CH1 CH0 0 0 0 1 0 1 1 0 0 1 1 0 1 1 Scan mode 0 Single mode 1 Scan mode Description Single Mode Scan Mode AN 0 AN 0 AN 1 AN 0, AN 1 AN 2 AN 0 to AN 2 AN 3 AN 0 to AN 3 AN 4 AN 4 AN 5 AN 4, AN 5 AN 6 AN 4 to AN 6 AN 7 AN 4 to AN 7 A/D start 0 A/D conversion is stopped 1 Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends Scan mode: A/D conversion starts and continues, cycling among the selected channels, until ADST is cleared to 0 by software, by a reset, or by a transition to standby mode A/D interrupt enable 0 A/D end interrupt request is disabled 1 A/D end interrupt request is enabled A/D end flag 0 [Clearing condition] Read ADF while ADF = 1, then write 0 in ADF 1 [Setting conditions] Single mode: A/D conversion ends Scan mode: A/D conversion ends in all selected channels Note: * Only 0 can be written, to clear flag. 660 ABWCR—Bus Width Control Register Bit Initial Mode 1, 3 value Mode 2, 4 Read/Write 7 ABW7 1 0 R/W 6 ABW6 1 0 R/W 5 ABW5 1 0 R/W 4 ABW4 1 0 R/W 3 ABW3 1 0 R/W H'EC 2 ABW2 1 0 R/W Bus controller 1 ABW1 1 0 R/W 0 ABW0 1 0 R/W Area 7 to 0 bus width control Bits 7 to 0 AWB7 to AWB0 Bus Width of Access Area 0 Areas 7 to 0 are 16-bit access areas Areas 7 to 0 are 8-bit access areas 1 ASTCR—Access State Control Register Bit Initial value Read/Write 7 AST7 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W 3 AST3 1 R/W H'ED 2 AST2 1 R/W 1 Bus controller 0 AST0 1 R/W AST1 1 R/W Area 7 to 0 access state control Bits 7 to 0 AST7 to AST0 Number of States in Access Cycle 0 Areas 7 to 0 are two-state access areas Areas 7 to 0 are three-state access areas 1 661 WCR—Wait Control Register H'EE Bus controller Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 WMS1 0 R/W 2 WMS0 0 R/W 1 WC1 1 R/W 0 WC0 1 R/W Wait mode select 1 and 0 Bit 3 Bit 2 WMS1 WMS0 Wait Mode 0 0 Programmable wait mode 1 No wait states inserted by wait-state controller 1 0 1 Pin wait mode Pin auto-wait mode Wait count 1 and 0 Bit 1 Bit 0 WC1 WC0 Number of Wait States 0 0 No wait states inserted by wait-state controller 1 1 0 1 1 state inserted 2 states inserted 3 states inserted WCER—Wait Controller Enable Register Bit Initial value Read/Write 7 WCE7 1 R/W 6 WCE6 1 R/W 5 WCE5 1 R/W 4 WCE4 1 R/W 3 WCE3 1 R/W H'EF 2 WCE2 1 R/W Bus controller 1 WCE1 1 R/W 0 WCE0 1 R/W Wait state controller enable 7 to 0 0 Wait-state control is disabled (pin wait mode 0) 1 Wait-state control is enabled 662 MDCR—Mode Control Register Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 0 — 4 — 0 — 3 — 0 — H'F1 2 MDS2 —* R System control 1 MDS1 —* R 0 MDS0 —* R Mode select 2 to 0 Bit 2 Bit 1 Bit 0 MD2 MD1 MD0 0 0 0 1 0 1 1 0 0 1 1 0 1 1 Operating mode — Mode 1 Mode 2 Mode 3 Mode 4 — — — Note: * Determined by the state of the mode pins (MD 2 to MD0 ). 663 SYSCR—System Control Register Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W H'F2 2 NMIEG 0 R/W 1 System control 0 RAME 1 R/W — 1 — RAM enable 0 On-chip RAM is disabled 1 On-chip RAM is enabled NMI edge select 0 An interrupt is requested at the falling edge of NMI 1 An interrupt is requested at the rising edge of NMI User bit enable 0 CCR bit 6 (UI) is used as an interrupt mask bit 1 CCR bit 6 (UI) is used as a user bit Standby timer select 2 to 0 Bit 6 Bit 5 Bit 4 STS2 STS1 STS0 Standby Timer 0 0 0 Waiting time = 8192 states 1 Waiting time = 16384 states 0 Waiting time = 32768 states 1 1 Waiting time = 65536 states Waiting time = 131072 states 0 — 1 — Waiting time = 4 states 1 Software standby 0 SLEEP instruction causes transition to sleep mode 1 SLEEP instruction causes transition to software standby mode 664 BRCR—Bus Release Control Register Bit Initial value Read/Write 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — H'F3 2 — 1 — Bus controller 1 — 1 — 0 BRLE 0 R/W Bus release enable 0 The bus cannot be released to an external device 1 The bus can be released to an external device ISCR—IRQ Sense Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'F4 2 0 R/W Interrupt controller 1 0 R/W 0 0 R/W IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC IRQ 7 to IRQ 0 sense control 0 Interrupts are requested when IRQ 7 to IRQ 0 inputs are low 1 Interrupts are requested by falling-edge input at IRQ 7 to IRQ0 IER—IRQ Enable Register Bit Initial value Read/Write 7 IRQ7E 0 R/(W) 6 IRQ6E 0 R/(W) 5 IRQ5E 0 R/(W) 4 IRQ4E 0 R/(W) 3 IRQ3E 0 R/(W) H'F5 2 IRQ2E 0 R/(W) Interrupt controller 1 IRQ1E 0 R/(W) 0 IRQ0E 0 R/(W) IRQ7 to IRQ 0 enable 0 IRQ 7 to IRQ 0 interrupts are disabled 1 IRQ 7 to IRQ 0 interrupts are enabled 665 ISR—IRQ Status Register Bit Initial value Read/Write 7 IRQ7F 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* H'F6 2 IRQ2F 0 R/(W)* Interrupt controller 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* IRQ 7 to IRQ 0 flags Bits 7 to 0 IRQ7F to IRQ0F 0 Setting and Clearing Conditions [Clearing conditions] Read IRQnF when IRQnF = 1, then write 0 in IRQnF. IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out. IRQnSC = 1 and IRQn interrupt exception handling is carried out. [Setting conditions] IRQnSC = 0 and IRQn input is low. IRQnSC = 1 and IRQn input changes from high to low. (n = 7 to 0) Note: * Only 0 can be written, to clear the flag. 1 666 IPRA—Interrupt Priority Register A Bit Initial value Read/Write 7 IPRA7 0 R/W 6 IPRA6 0 R/W 5 IPRA5 0 R/W 4 IPRA4 0 R/W 3 IPRA3 0 R/W H'F8 2 IPRA2 0 R/W Interrupt controller 1 IPRA1 0 R/W 0 IPRA0 0 R/W Priority level A7 to A0 0 Priority level 0 (low priority) 1 Priority level 1 (high priority) • Interrupt sources controlled by each bit Bit 7 IPRA7 Interrupt source IRQ0 Bit 6 IPRA6 IRQ1 Bit 5 IPRA5 IRQ2, IRQ3 Bit 4 IPRA4 IRQ4 to IRQ7 Bit 3 IPRA3 Bit 2 IPRA2 Bit 1 IPRA1 ITU channel 1 Bit 0 IPRA0 ITU channel 2 WDT, ITU Refresh chanConnel 0 troller IPRB—Interrupt Priority Register B Bit Initial value Read/Write 7 IPRB7 0 R/W 6 IPRB6 0 R/W 5 IPRB5 0 R/W 4 IPRB4 0 R/W 3 IPRB3 0 R/W H'F9 2 IPRB2 0 R/W Interrupt controller 1 IPRB1 0 R/W 0 IPRB0 0 R/W Reserved bit Priority level B7 to B0 0 Priority level 0 (low priority) 1 Priority level 1 (high priority) • Interrupt sources controlled by each bit Bit 7 IPRB7 Interrupt source ITU channel 3 Bit 6 IPRB6 ITU channel 4 Bit 5 IPRB5 DMAC group 0 Bit 4 IPRB4 DMAC group 1 Bit 3 IPRB3 SCI channel 0 Bit 2 IPRB2 SCI channel 1 Bit 1 IPRB1 A/D converter Bit 0 — — 667 Appendix C I/O Port Block Diagrams C.1 Port 4 Block Diagram 8-bit bus mode 16-bit bus mode Reset Internal data bus (upper) Internal data bus (lower) R Q P4 n PCR RP4P C WP4P Reset R Write to external address Q P4 n DDR C WP4D Reset R D D P4 n Q P4n DR C WP4 D RP4 Read external address WP4P: Write to P4PCR RP4P: Read P4PCR WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 n = 0 to 7 Figure C-1 Port 4 Block Diagram 668 C.2 Port 5 Block Diagram Reset Internal data bus (upper) R Q P5 n PCR External bus Software released standby Mode 3/4 Hardware standby RP5P C WP5P Mode 3/4 Reset Reset S Q R D * D Internal data bus (lower) P5 n DDR C Mode 1/2 Q WP5D Reset R P5 n P5n DR C D Mode 3/4 WP5 RP5 WP5P: Write to P5PCR RP5P: Read P5PCR WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 n = 4 to 7 Note: * Set priority Figure C-2 Port 5 Block Diagram 669 C.3 Port 6 Block Diagrams Reset Internal data bus Bus controller WAIT input R Q P60 DDR C WP6D Reset R P6 0 Q P60 DR C WP6 D D RP6 WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C-3 (a) Port 6 Block Diagram (Pin P60) 670 Reset Internal data bus R Q P6 1 DDR C WP6D Reset R P6 1 Q P61 DR C WP6 D D Bus controller Bus release enable RP6 BREQ input WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C-3 (b) Port 6 Block Diagram (Pin P61) 671 Reset R Q P6 2 DDR C WP6D Reset R P6 2 Q P62 DR C WP6 D Bus controller Bus release enable BACK output D Internal data bus RP6 WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C-3 (c) Port 6 Block Diagram (Pin P62) 672 C.4 Port 7 Block Diagram RP7 P7n Internal data bus A/D converter module Analog input RP7: Read port 7 n = 0 to 7 Input enable Figure C-4 Port 7 Block Diagram (Pin P7n) 673 C.5 Port 8 Block Diagrams Reset R Q P8 0 DDR C WP8D Reset R P8 0 Q P80 DR C WP8 D Refresh controller Output enable RFSH output D Internal data bus Interrupt controller WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 IRQ 0 input RP8 Figure C-5 (a) Port 8 Block Diagram (Pin P80) 674 Reset R Q P8 n DDR C P8 n WP8D Reset R Q P8n DR C WP8 D D Internal data bus Bus controller CS 1 CS 2 CS 3 output RP8 Interrupt controller IRQ 1 IRQ 2 IRQ 3 input WP8D Write to P8DDR WP8: Write to port 8 RP8: Read port 8 n = 1 to 3 Figure C-5 (b) Port 8 Block Diagram (Pins P81, P82, P83) 675 Reset S Q P8 4 DDR C P8 4 WP8D Reset R Q P84 DR C WP8 D D Internal data bus Bus controller CS 0 output RP8 WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C-5 (c) Port 8 Block Diagram (Pin P84) 676 C.6 Port 9 Block Diagrams Reset R Q P9 n DDR C WP9D Reset R P9 n Q P9n DR C WP9 D SCI Output enable Serial transmit data D Internal data bus RP9 WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 n = 0 and 1 Figure C-6 (a) Port 9 Block Diagram (Pins P90, P91) 677 Reset R Q P9 n DDR C WP9D Reset R P9 n Q P9n DR C WP9 D D Internal data bus SCI Input enable RP9 Serial receive data WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 n = 2 and 3 Figure C-6 (b) Port 9 Block Diagram (Pins P92, P93) 678 Reset R Q P9 n DDR C WP9D Reset R P9 n Q P9n DR C WP9 Clock output enable Clock output D D Internal data bus SCI module Clock input enable RP9 Clock input WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 n = 4 and 5 Interrupt controller IRQ 4 or IRQ 5 input Figure C-6 (c) Port 9 Block Diagram (Pins P94, P95) 679 C.7 Port A Block Diagrams Reset R Q PA n DDR C WPAD Reset R PAn Q PA n DR C D D Internal data bus WPA Output trigger DMA controller Output enable Transfer end output TPC TPC output enable Next data ITU RPA Counter clock input WPAD: Write to PADDR WPA: Write to port A RPA: Read port A n = 0 and 1 Figure C-7 (a) Port A Block Diagram (Pins PA0, PA1) 680 Reset R Q PA n DDR C WPAD Reset R PAn Q PAn DR C D D Internal data bus WPA Output trigger ITU Output enable Compare match output TPC TPC output enable Next data RPA Input capture Counter clock input WPAD: Write to PADDR WPA: Write to port A RPA: Read port A n = 2 and 3 Figure C-7 (b) Port A Block Diagram (Pins PA2, PA3) 681 Reset R Q PA n DDR C WPAD Reset R PAn Q PA n DR C D Next data D Internal data bus WPA Output trigger ITU Output enable Compare match output TPC TPC output enable RPA ITU Input capture WPAD: Write to PADDR WPA: Write to port A RPA: Read port A n = 4 to 7 Figure C-7 (c) Port A Block Diagram (Pins PA4 to PA7) 682 C.8 Port B Block Diagrams Reset Internal data bus WPB Output trigger ITU Output enable Compare match output R Q PB n DDR C WPBD Reset R PBn Q PB n DR C D Next data D TPC TPC output enable RPB Input capture WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B n = 0 to 3 Figure C-8 (a) Port B Block Diagram (Pins PB0 to PB3) 683 R Q PB n DDR C WPBD Reset R PBn Q PB n DR C D D Internal data bus WPB Reset TPC TPC output enable Next data Output trigger ITU Output enable Compare match output RPB WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B n = 4 and 5 Figure C-8 (b) Port B Block Diagram (Pins PB4, PB5) 684 R Q PB 6 DDR C WPBD Reset R PB6 Q PB6 DR C D D Internal data bus WPB Reset TPC TPC output enable Next data Output trigger DMAC RPB WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B DREQ 0 input Figure C-8 (c) Port B Block Diagram (Pin PB6) 685 R Q PB 7 DDR C WPBD Reset R PB7 Q PB7 DR C D D Internal data bus WPB Reset TPC TPC output enable Next data Output trigger DMAC RPB WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B DREQ 1 input A/D converter ADTRG input Figure C-8 (d) Port B Block Diagram (Pin PB7) 686 C.9 Port C Block Diagrams Reset Internal data bus R Q PCn DDR C WPCD Reset R PCn Q PCn DR C WPC D D RPC WPCD: Write to PCDDR WPC: Write to port C RPC: Read port C n = 0 and 1 Figure C-9 (a) Port C Block Diagram (Pins PC0, PC1) 687 Reset R Q PCn DDR C WPCD PCn D Internal data bus Bus controller CS 4 CS 6 output DMAC Output enable Reset R Q PCn DR C WPC D Transfer end output RPC WPCD: Write to PCDDR WPC: Write to port C RPC: Read port C n = 2 and 4 Figure C-9 (b) Port C Block Diagram (Pins PC2, PC4) 688 Reset Internal data bus R Q PCn DDR C PCn WPCD Reset R Q PC n DR C WPC D D Bus controller CS5 CS7 output RPC DMAC DMA request input WPCD: Write to PCDDR WPC: Write to port C RPC: Read port C n = 3 and 5 Figure C-9 (c) Port C Block Diagram (Pins PC3, PC5) 689 Reset R Q PCn DDR C WPCD Reset R PCn Q PCn DR C WPC D D Internal data bus Interrupt controller WPCD: Write to PCDDR WPC: Write to port C RPC: Read port C n = 6 and 7 IRQ 6 IRQ 7 input RPC Figure C-9 (d) Port C Block Diagram (Pins PC6, PC7) 690 Appendix D Pin States D.1 Port States in Each Mode Table D-1 Port States Pin Name ø A19 to A0 D15 to D8 AS, RD, HWR, LWR P47 to P40 D7 to D0 P57 to P54 A23 to A20 P60 P61 1, 2 3, 4 1 to 4 1 to 4 Reset State Hardware Software Standby Standby Mode Mode H T T T keep T T L T T T T T T keep T keep BusReleased Mode Program Execution Sleep Mode Mode — 1 to 4 1 to 4 1 to 4 1 to 4 8-bit bus 16-bit bus Clock output T L T H T T T T T Clock output Clock output T T T keep T keep T keep A19 to A0 D15 to D0 AS, RD, HWR, LWR I/O port D7 to D0 I/O port A23 to A20 I/O port*1 WAIT I/O port BREQ (BRLE = 0) T keep (BRLE = 1) T (BRLE = 0) keep L (BRLE = 1) H T T P62 1 to 4 T T I/O port (BRLE = 0) or BACK (BRLE = 1) Input port P77 to P70 1 to 4 T T Note: * Do not set the DDR bit to 1. Legend H: High L: Low T: High-impedance state keep: Input pins are in the high-impedance state; output pins maintain their previous state. DDR: Data direction register bit 691 Table D-1 Port States (cont) Pin Name P80 Reset State T Hardware Software Standby Standby Mode Mode T (RFSHE = 0) keep (RFSHE = 1) RFSH (DDR = 0) T (DDR = 1) H (DDR = 0) T (DDR = 1) L keep keep keep keep (DDR = 0) keep (DDR = 1) H BusReleased Mode (RFSHE = 0) keep (RFSHE = 1) H keep Program Execution Sleep Mode I/O port (RFSHE = 0) or RFSH (RFSHE = 1) Input port (DDR = 0) or CS3 to CS1 (DDR = 1) Input port (DDR = 0) or CS0 (DDR = 1) I/O port I/O port I/O port I/O port Input port (DDR = 0) or CS7 to CS4 (DDR = 1) Mode 1 to 4 P83 to P81 1 to 4 T T P84 1 to 4 L T keep P95 to P90 PA7 to PA0 PB7 to PB0 PC7, PC6 PC1, PC0 PC5 to PC2 1 to 4 1 to 4 1 to 4 1 to 4 1 to 4 T T T T T T T T T T keep keep keep keep keep Legend H: High L: Low T: High-impedance state keep: Input pins are in the high-impedance state; output pins maintain their previous state. DDR: Data direction register bit 692 D.2 Pin States at Reset Reset in T1 State: Figure D-1 is a timing diagram for the case in which RES goes low during the T1 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state. AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance state. The address bus is initialized to the low output level 0.5 state after the low level of RES is sampled. Sampling of RES takes place at the fall of the system clock (ø). Access to external address T1 ø T2 T3 RES Internal reset signal Address bus H'000000 CS 0 High impedance CS 7 to CS1 AS High RD (read access) High HWR, LWR (write access) Data bus (write access) I/O port High High impedance High impedance Figure D-1 Reset during Memory Access (Reset during T1 State) 693 Reset in T2 State: Figure D-2 is a timing diagram for the case in which RES goes low during the T2 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state. AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance state. The address bus is initialized to the low output level 0.5 state after the low level of RES is sampled. The same timing applies when a reset occurs during a wait state (TW). Access to external address T1 ø T2 T3 RES Internal reset signal Address bus H'000000 CS 0 High impedance CS 7 to CS1 AS RD (read access) HWR, LWR (write access) Data bus (write access) I/O port High impedance High impedance Figure D-2 Reset during Memory Access (Reset during T2 State) 694 Reset in T3 State: Figure D-3 is a timing diagram for the case in which RES goes low during the T3 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state. AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance state. The address bus outputs are held during the T3 state.The same timing applies when a reset occurs in the T2 state of an access cycle to a two-state-access area. Access to external address T1 ø T2 T3 RES Internal reset signal Address bus H'000000 CS 0 High impedance CS 7 to CS1 AS RD (read access) HWR, LWR (write access) Data bus (write access) I/O port High impedance High impedance Figure D-3 Reset during Memory Access (Reset during T3 State) 695 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below. RES must remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns). STBY t1 ≥ 10tcyc RES t2 ≥ 0 ns (2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, RES does not have to be driven low as in (1). Timing of Recovery from Hardware Standby Mode: Drive the RES signal low approximately 100 ns before STBY goes high. STBY t = 100 ns RES tOSC 696 Appendix F Package Dimensions Figure E-1 shows the QFP-112 package dimensions of the H8/3003. Unit: mm Figure F-1 Package Dimensions (QFP-112) 697