H8S-2643

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H8S-2643 - 16-Bit Single-Chip Microcomputer - Renesas Technology Corp

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H8S-2643 数据手册

REJ09B0186-0300O The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 H8S/2643 Group, H8S/2643F-ZTAT Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series Rev. 3.00 Revision Date: Jan 11, 2005 Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 3.00 Jan 11, 2005 page ii of liv General Precautions on the Handling of Products 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product’s state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Address Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these address. Do not access these registers: the system’s operation is not guaranteed if they are accessed. Rev. 3.00 Jan 11, 2005 page iii of liv Configuration of this Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. Precautions in Relation to this Product Configuration of this Manual Overview Table of Contents Summary Description of Functional Modules • CPU and System-Control Modules • On-chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Features ii) I/O pins iii) Description of Registers iv) Description of Operation v) Usage: Points for Caution When designing an application system that includes this LSI, take the points for caution into account. Each section includes points for caution in relation to the descriptions given, and points for caution in usage are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix • Product-type codes and external dimensions • Major revisions or addenda in this version of the manual (only for revised versions) The history of revisions is a summary of sections that have been revised and sections that have been added to earlier versions. This does not include all of the revised contents. For details, confirm by referring to the main description of this manual. 10. Appendix/Appendices Rev. 3.00 Jan 11, 2005 page iv of liv Preface The H8S/2643 Group is a group of high-performance microcontrollers with a 32-bit H8S/2600 CPU core, and a set of on-chip supporting functions required for system configuration. The H8S/2600 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit general registers with a 32-bit internal configuration, and a concise and optimized instruction set. The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based on the high-level language C can also be run efficiently. The address space is divided into eight areas. The data bus width and access states can be selected for each of these areas, and various kinds of memory can be connected fast and easily. Single-power-supply flash memory (F-ZTAT™*) and masked ROM versions are available, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently changing specifications. On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse generator (PPG), 8-bit timer, 14-bit PWM timer (PWM), watchdog timer (WDT), serial communication interface (SCI, IrDA), A/D converter, D/A converter, and I/O ports. It is also possible to incorporate an on-chip PC bus interface (IIC) as an option. In addition, DMA controller (DMAC) and data transfer controller (DTC) are provided, enabling high-speed data transfer without CPU intervention. Use of the H8S/2643 Group enables easy implementation of compact, high-performance systems capable of processing large volumes of data. This manual describes the hardware of the H8S/2643 Group. Refer to the H8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of the instruction set. Note: * F-ZTAT (Flexible-ZTAT) is a trademark of Renesas Technology, Corp. Rev. 3.00 Jan 11, 2005 page v of liv Rev. 3.00 Jan 11, 2005 page vi of liv Main Revisions for this Edition Item 1.1 Overview Table 1.1 Overview Page 4 Revisions (See Manual for Details) Specification amended Memory • Flash memory or masked ROM • High-speed static RAM 5 Package • 144-pin plastic QFP (FP-144J) • 144-pin plastic TQFP (TFP-144) Specification amended and note deleted Product lineup Model Name Masked ROM Version F-ZTAT Version HD6432643 HD6432642 HD6432641 HD64F2643 — — ROM/RAM (Bytes) 256 k/16 k 192 k/12 k 128 k/8 k Packages FP-144J TFP-144 FP-144J TFP-144 FP-144J TFP-144 1.2 Internal Block Diagram Figure 1.1 Internal Block Diagram 6 Figure 1.1 amended P77/TxD3 P76/RxD3 P75/TMO3/SCK3 P74/TMO2/MRES P73/TMO1/CS7 P72/TMO0/CS6 P71/TMRI23/TMCI23/CS5 P70/TMRI01/TMCI01/CS4 Port 7 Rev. 3.00 Jan 11, 2005 page vii of liv Item 1.3.1 Pin Arrangement Figure 1.2 Pin Arrangement (FP144J, TFP-144: Top View) Page 7 Revisions (See Manual for Details) Figure 1.2 amended DA3/AN15/P97 AVSS TEST1 A20/PA4 A21/PA5 A22/PA6 A23/PA7 CS4/TMCI01/TMRI01/P70 CS5/TMCI23/TMRI23/P71 CS6/TMO0/P72 CS7/TMO1/P73 MRES/TMO2/P74 SCK3/TMO3/P75 RxD3/P76 TxD3/P77 MD0 MD1 MD2 NC 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Top view (FP-144J) (TFP-144) 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 1.3.2 Pin Functions 8 in Each Operating Mode Table 1.2 Pin Functions in Each Operating Mode Table 1.2 amended Pin Name Pin No. 15 16 17 18 19 20 21 22 23 27 Mode 4 PB0/A8 PVCC PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 Mode 5 PB0/A8 PVCC PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 Rev. 3.00 Jan 11, 2005 page viii of liv A0/PC0 A1/PC1 A2/PC2 A3/PC3 VSS A4/PC4 VCC A5/PC5 PWM0/A6/PC6 PWM1/A7/PC7 TIOCA3/PO0/P20 TIOCB3/PO1/P21 TIOCC3/PO2/P22 VSS A8/PB0 PVCC A9/PB1 A10/PB2 A11/PB3 A12/PB4 A13/PB5 A14/PB6 A15/PB7 TIOCD3/PO3/P23 TIOCA4/PO4/P24 TIOCB4/PO5/P25 A16/PA0 A17/PA1 A18/PA2 A19/PA3 VSS TIOCA0/PO8/P10 TIOCB0/PO9/P11 TCLKA/TIOCC0/PO10/P12 TCLKB/TIOCD0/PO11/P13 IRQ0/TIOCA1/PO12/P14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PD2/D10 PD1/D9 PVCC PD0/D8 VSS PE7/D7 PE6/D6 PE5/D5 PE4/D4 P50/TxD2 P27/PO7/TIOCB5 P26/PO6/TIOCA5 PE3/D3 PE2/D2 PE1/D1 PE0/D0 P17/PO15/TIOCB2/TCLKD/PWM3 P16/PO14/TIOCA2/PWM2/IRQ1 P15/PO13/TIOCB1/TCLKC Note: * FWE is used only in the flash memory version. Item Page Revisions (See Manual for Details) Pin Name Pin No. 28 29 30 40 41 42 43 47 48 49 50 Mode 4 PA1/A17 PA2/A18 PA3/A19 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 PE7/D7 Mode 5 PA1/A17 PA2/A18 PA3/A19 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PE5/D5 PE6/D6 PE7/D7 Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 1.3.2 Pin Functions 9 in Each Operating Mode Table 1.2 Pin Functions in Each Operating Mode 11 89 102 103 104 105 FEW * RD HWR LWR/ADTRG/IRQ3 2 FWE* RD HWR 2 FWE* RD HWR 2 FWE* PF6 PF5 PF4 2 AS/LCAS AS/LCAS AS/LCAS PF3/LWR/ADTRG/ IRQ3 PF3/LWR/ADTRG/ IRQ3 PF3/ADTRG/IRQ3 12 Pin No. Mode 4 Mode 5 Pin Name Mode 6 Mode 7 129 130 131 132 135 144 PA4/A20 PA5/A21 PA6/A22 PA7/A23 P72/TMO0/CS6 NC* 1 PA4/A20 PA5/A21 PA6/A22 PA7/A23 P72/TMO0/CS6 NC* 1 PA4/A20 PA5/A21 PA6/A22 PA7/A23 P72/TMO0/CS6 NC* 1 PA4 PA5 PA6 PA7 P72/TMO0 NC* 1 Rev. 3.00 Jan 11, 2005 page ix of liv Item Table 1.3 Pin Functions Page Revisions (See Manual for Details) Name and function amended XTAL, EXTAL Crystal: Connects to a crystal oscillator. … 1.3.3 Pin Functions 13 17 TxD4, TxD3, TxD2, TxD1, TxD0 Transmit data (channel 0 to 4) RxD4, RxD3, RxD2, RxD1, RxD0 Receive data (channel 0 to 4) SCK4, SCK3, SCK2, SCK1, SCK0 Serial clock (channel 0 to 4): Clock I/O pins. AVCC Analog power supply: A/D converter and D/A converter power supply pins. … 18 AVSS Analog ground: Analog circuit ground and reference voltage. … Vref Analog reference power supply: A/D converter and D/A converter reference voltage input pins. … PA7 to PA0 Port A: 8-bit I/O port. … 2.6.1 Overview Table 2.1 Instruction Classification 38 Table 2.1 amended Function Data transfer Instructions MOV POP*1, PUSH*1 LDM*5, STM*5 MOVFPE*3, MOVTPE*3 Note added Note: 5. Only register ER0 to ER6 should be used when using the STM/LDM instruction. Rev. 3.00 Jan 11, 2005 page x of liv Item 2.6.2 Instructions and Addressing Modes Table 2.2 Combinations of Instructions and Addressing Modes Page 39 Revisions (See Manual for Details) Table 2.2 amended Function Instruction Data transfer MOV POP, PUSH LDM*3, STM*3 MOVEPE*1, MOVTPE*1 40 Note added Note: 3. Only register ER0 to ER6 should be used when using the STM/LDM instruction. 42 2.6.3 Table of Instructions Classified by Function Table 2.3 Instructions Classified by Function 47 Table 2.3 amended Type Data transfer Instruction LDM*3 STM* 3 Size*1 L L Table 2.3 amended Type Block data transfer instruction Instruction EEPMOV.B Size* — 1 Function if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 EEPMOV.W — 48 Note added Note: 3. Only register ER0 to ER6 should be used when using the STM/LDM instruction. 2.10.2 STM/LDM Instruction 2.10.3 Bit Manipulation Instructions 3.3.1 Mode 4 3.3.2 Mode 5 3.3.3 Mode 6 67 2.10.2 added 2.10.3 added 76 Description amended … Port A, B, and C, function as … Rev. 3.00 Jan 11, 2005 page xi of liv Item Page Revisions (See Manual for Details) Description amended The pin functions of ports A to G vary depending on the operating mode. … Table 3.3 amended Port Port A Mode 4 PA7 to PA5 P*/A PA4 to PA0 P/A* Mode 5 P*/A P/A* Mode 6 P*/A P*/A Mode 7 P P 3.4 Pin Functions in 75 Each Operating Mode Table 3.3 Pin Functions in Each Mode 77 3.5 Address Map in Each Operating Mode 5.5.5 IRQ Interrupt 5.5.6 NMI Interrupt Usage Notes 10.1 Overview Table 10.1 Port Functions 341 119 Description amended The Address space is 16 Mbytes in modes 4 to 7 (advanced mode). 5.5.5 added 5.5.6 added Table 10.1 amended Port Port 7 Description 8-bit I/O port Pins P77/TxD3 P76/RxD3 P75/TMO3/SCK3 P74/TMO2/MRES P73/TMO1/CS7 P72/TMO0/CS6 P71/TMRI23/TMCI23/ CS5 P70/TMRI01/TMCI01/ CS4 Mode 4 Mode 5 Mode 6 Mode 7 8-bit I/O port also functioning as 8-bit timer I/O pins (TMRI01, TMCI01, TMRI23, TMCI23, TMO0, TMO1, TMO2, TMO3), SCI I/O pins (SCK3, RxD3, TxD3), and the manual reset input pin (MRES) 8-bit I/O port also functioning as 8-bit timer I/O pins (TMRI01, TMCI01, TMRI23, TMCI23, TMO0, TMO1, TMO2, TMO3), bus control output pins (CS4 to CS7), SCI I/O pins (SCK3, RxD3, TxD3), and the manual reset input pin (MRES) 10.2.1 Overview 10.2.2 Register Configuration 345 346 Description amended ... Port 1 functions are the same in all operation modes. ... (1) Port 1 Data Direction Register (P1DDR) Description amended … Because PPG and TPU are initialized at a manual reset, … Rev. 3.00 Jan 11, 2005 page xii of liv Item Page Revisions (See Manual for Details) Description amended … TOPCA2, and TIOCB2), external interrupt input pins (IRQ0 and IRQ1), and 14-bit PWM output pins (PWM2 and PWM3). … 10.2.3 Pin Functions 348 Table 10.3 Port 1 Pin Functions 352 Table 10.3 amended Pin P13/PO11/ TIOCD0/TCLKB Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, bit NDER11 in NDERH, and bit P13DDR. TPU Channel 0 Setting P13DDR NDER11 Pin function Table Below (1) — — TIOCD0 output 0 — P13 input Table Below (2) 1 0 P13 output TIOCD0 input * TCLKB input * 2 1 1 1 PO11 output 353 Pin P12/PO10/ TIOCC0/TCLKA Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR5, bit NDER10 in NDERH, and bit P12DDR. TPU Channel 0 Setting P12DDR NDER10 Pin function Table Below (1) — — TIOCC0 output 0 — P12 input Table Below (2) 1 0 P12 output TIOCC0 input * TCLKA input * 2 1 1 1 PO10 output 354 Pin Selection Method and Pin Functions P11/PO9/TIOCB0 The pin function is switched as shown below according to the combination of the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, and bits IOB3 to IOB0 in TIOR0H), bit NDER9 in NDERH, and bit P11DDR. TPU Channel 0 Setting P11DDR NDER9 Pin function Table Below (1) — — TIOCB0 output 0 — P11 input Table Below (2) 1 0 P11 output TIOCB0 input * 1 1 PO9 output 355 Pin Selection Method and Pin Functions P10/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bit NDER8 in NDERH, and bit P10DDR. TPU Channel 0 Setting P10DDR NDER8 Pin function Table Below (1) — — TIOCA0 output 0 — P10 input Table Below (2) 1 0 P10 output TIOCA0 input * 1 1 1 PO8 output Rev. 3.00 Jan 11, 2005 page xiii of liv Item 10.3.2 Register Configuration Page 357 Revisions (See Manual for Details) (1) Port 2 Data Direction Register (P2DDR) Description amended ... and in software standby mode. PPG and TPU are initialized by a manual reset, so the pin states are determined by the specification of P2DDR and P2DR. 10.4.2 Register Configuration 368 (1) Port 3 Data Direction Register (P3DDR) Description amended … SCI and IIC are initialized by a manual reset, so the pin states are determined by the specification of P3DDR and P3DR. 10.4.3 Pin Functions 370 Description amended The port 3 pins double as SCI I/O input pins (TxD0, RxD0, SCK0, IrTxD, IrRxD, TxD1, RxD1, SCK1, TxD4, RxD4, SCK4), external interrupt input pins ( , ) and IIC I/O pins (SCL0, SDA0, SCL1, SDA1). … 10.6.2 Register Configuration 376 (1) Port 5 Data Direction Register (P5DDR) Description amended … P5DDR is initialized to H'0 (bits 2 to 0) by a power-on reset and in hardware standby mode. ... and in software standby mode. As the SCI is initialized by a manual reset, the pin states are determined by the P5DDR and P5DR specifications. (2) Port 5 Data Register (P5DR) Description amended … P5DR is initialized to H'0 (bits 2 to 0) by a power-on reset and in hardware standby mode. … Rev. 3.00 Jan 11, 2005 page xiv of liv 5QRI 4QRI Item 10.7.1 Overview Page 379 Revisions (See Manual for Details) Description amended ), SCI I/O pins (SCK3, … bus control output pins ( to RxD3, TxD3) and manual reset input pin ( ). … SERM SERM 7SC 7SC 4SC 4SC Figure 10.6 Port 7 Pin Functions Figure 10.6 amended Port 7 pins P77 / TxD3 P76 / RxD3 P75 / TMO3 SCK3 Port 7 P74 / TMO2 / MRES P73 / TMO1 / CS7 P72 / TMO0 / CS6 P71 / TMRI23 / TMCI23 / CS5 P70 / TMRI01 / TMCI01 / CS4 Pins Functions for Modes 4 to 6 P77 (I/O) / TxD3 (output) P76 (I/O) / RxD3 (input) P75 (I/O) / TMO3 (output) / SCK3 (I/O) P74 (I/O) / TMO2 (output) / MRES (input) P73 (I/O) / TMO1 (output) / CS7 (output) P72 (I/O) / TMO0 (output) / CS6 (output) P71 (I/O) / TMRI23 (input) / TMCI23 (input) / CS5 (output) P70 (I/O) / TMRI01 (input) / TMCI01 (input) / CS4 (output) Modes 7 Pin Functions P77 (I/O) / TxD3 (output) P76 (I/O) / RxD3 (input) P75 (I/O) / TMO3 (output) / SCK3 (I/O) P74 (I/O) / TMO2 (output) / MRES (input) P73 (I/O) / TMO1 (output) P72 (I/O) / TMO0 (output) P71 (I/O) / TMRI23 (input) / TMCI23 (input) P70 (I/O) / TMRI01 (input) / TMCI01 (input) 10.7.2 Register Configuration 380 (1) Port 7 Data Direction register (P7DDR) Description amended ... and in software standby mode. The 8-bit timer and SCI are initialized by a manual reset so the pin states are determined by the specification of P7DDR and P7DR. 10.7.3 Pin Functions 382 Description amended … bus control output pins ( to ), SCI I/O pins (SCK3, RxD3, TxD3) and manual reset input pin ( ). … Table 10.12 Port 7 Pin Function 383 Table 10.12 amended Pin P72/TMO0/ CS6 Selection Method and Pin Functions Switches as follows according to combinations of operating mode and OS3 to OS0 bits of 8-bit timer TCSR0, and the P72DDR bit. Operating Mode OS3 to OS0 P72DDR Pin function 0 Modes 4 to 6 All 0 1 P72 input CS6 pin output pin Any is 1 — TMO0 output 0 Mode 7 All 0 1 P72 input P72 output pin pin Any is 1 — TMO0 output Rev. 3.00 Jan 11, 2005 page xv of liv Item 10.8.2 Register Configuration Page 386 Revisions (See Manual for Details) (1) Port 8 Data Direction Register (P8DDR) Description amended ... and in software standby mode. DMAC is initialized by a manual reset, so the pin states are determined by the specification of P8DDR and P8DR. 10.10.2 Register Configuration 393 (1) Port A Data Direction Register (PADDR) Description amended … PADDR is initialized to H'00 by a power-on reset, and in hardware standby mode. … when a transition is made to software standby mode. See section 24.2.1, Standby Control Register (SBYCR), for details. • Modes 4 to 6 … irrespective of the value of PADDR. When pins are not used as address outputs, … 394 (2) Port A Data Register (PADR) Description amended … PADR is initialized to H'00 by a power-on reset, and in hardware standby mode. … 395 (4) Port A MOS Pill-Up Control Register (PAPCR) Description amended …In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pill-up for than pin. In mode 7, if a pin is in the input state in accordance with the settings in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pill-up for than pin. PAPCR is initialized by a manual reset or to H'00 by a power-on reset, and in hardware standby mode. … (5) Port A Open Drain Control Register (PAODR) Description amended … PAODR is initialized to H'00 by a power-on reset, and in hardware standby mode. … 10.11.1 Overview 398 Description amended Port B is n 8-bit I/O port. Port B pins also function as address bus outputs; ... Rev. 3.00 Jan 11, 2005 page xvi of liv Item 10.12.1 Overview Figure 10.15 Port C Pin Functions Page 404 Revisions (See Manual for Details) Figure 10.15 amended Port C pins PC7/A7/PWM1 PC6/A6/PWM0 PC5/A5 Port C PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 Pin functions in modes 4 and 5 A7 (output) A6 (output) A5 (output) A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Pin functions in mode 6 When PCDDR = 1 When PCDDR = 0 A7 A6 A5 A4 A3 A2 A1 A0 (output) (output) (output) (output) (output) (output) (output) (output) PC7 (input) / PWM1 (output) PC6 (input) / PWM0 (output) PC5 (input) PC4 (input) PC3 (input) PC2 (input) PC1 (input) PC0 (input) Pin functions in mode 7 PC7 (I/O) / PWM1 (output) PC6 (I/O) / PWM0 (output) PC5 (I/O) PC4 (I/O) PC3 (I/O) PC2 (I/O) PC1 (I/O) PC0 (I/O) 10.15.1 Overview Figure 10.25 Port F Pin Functions 423 Figure 10.25 amended Port F pins PF7 / φ PF6 / AS/ L C AS PF5 / RD Port F PF4 / HWR PF3 / LWR/ADTRG/IRQ3 PF2 / LCAS/ WAIT / BREQO PF1 / BACK/ BUZZ PF0 / BREQ/IRQ2 10.16.2 Register Configuration 429 (1) Port G Data Direction Register (PGDDR) Description amended … In modes 4 and 5, the PGDDR are initialized to H'10 (bits 4 to 0) … Rev. 3.00 Jan 11, 2005 page xvii of liv Item 11.2.9 Timer Synchro Register (TSYR) 15.1.2 Block Diagram Figure 15.1 (a) Block Diagram of WDT0 Page 472 Revisions (See Manual for Details) Description amended TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 5 TCNT counters. 598 Figure 15.1 (a) amended Overflow WOVI 0 (interrupt request signal) Interrupt control Clock Clock select φ/2*2 φ/64*2 φ/128*2 φ/512*2 φ/2048*2 φ/8192*2 φ/32768*2 φ/131072*2 Internal clock sources WDTOVF Internal reset signal*1 Reset control RSTCSR TCNT TSCR Module bus Bus interface WDT Legend: Timer control/status register TCSR: Timer counter TCNT: RSTCSR: Reset control/status register Notes: 1. The type of internal reset signal depends on a register setting. There are two alternative types of reset, namely power-on reset and manual reset. 2. The φ in the subactive and subsleep modes is φSUB. 15.2.2 Timer Control/Status Register (TCSR) 605 WDT1 Input Clock Select Note *2 added Notes: 1. An overflow period is the time interval between the start of counting up from H’00 on the TCNT and the occurrence of a TCNT overview. 2. The φ in the subactive and subsleep modes is φSUB. Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): Table amended (Before) C/A, GM → (After) C/ , GM Description amended ... Where: N = Value set in BRR (0 ≤ N ≤ 255) ... ... N is an integer, 0 ≤ N ≤ 255, and the smaller error is specified. A 17.2.4 Serial Control 708 Register (SCR) 17.3.5 Clock 715 716 Rev. 3.00 Jan 11, 2005 page xviii of liv Internal bus Item Page Revisions (See Manual for Details) (2) Serial Data Transmission Description amended … For details, see (6), Interrupt Operation (Except Block Transfer Mode), and (7), Data Transfer Operation by DMAC or DTC. 17.3.6 Data Transfer 718 Operations 722 (3) Serial Data Reception (Except Block Transfer Mode) Description amended … For details, see (6), Interrupt Operation (Except Block Transfer Mode), and (7), Data Transfer Operation by DMAC or DTC. 18.2.2 Slave Address Register (SAR) 739 Bit 0  Format Select (FS): Description amended Bit 0  Format Select (FS): Used together with the FSX bit in SARX to select the communication format. 740 Bit table amended SAR Bit 0 0 SARX Bit 0 0 1 1 0 1 I2C bus format • SAR and SARX slave addresses recognized I2C bus format (Initial value) • SAR slave address recognized • SARX slave address ignored I2C bus format • SAR slave address ignored • SARX slave address recognized Synchronous serial format • SAR and SARX slave addresses ignored 18.2.3 Second Slave Address Register (SARX) Bit 0  Format Select X (FSX): Description amended Used together with the FS bit in SAR to select the communication format. Rev. 3.00 Jan 11, 2005 page xix of liv Item 2 Page Revisions (See Manual for Details) Bits 5 to 3  Serial Clock Select (CKS2 to CKS0): Note * added to bit table SCRX Bit 5 or 6 Bit 5 IICX 0 Bit 4 Bit 3 φ= 8 MHz 286 kHz 200 kHz 167 kHz Transfer Rate φ= 10 MHz φ= 16 MHz φ= 20 MHz φ= 25 MHz 18.2.4 I C Bus Mode 743 Register (ICMR) φ= CKS2 CKS1 CKS0 Clock 5 MHz 0 0 1 0 1 0 1 /28 /40 /48 /64 179 kHz 125 kHz 104 kHz 357 kHz 571 kHz* 714 kHz* 893 kHz* 250 kHz 400 kHz 500 kHz* 625 kHz* 208 kHz 333 kHz 417 kHz* 521 kHz* 156 kHz 250 kHz 313 kHz 391 kHz 78.1 kHz 125 kHz Note: * Outside the allowable range for the I2C bus interface standard (normal mode: max. 100 kHz, high-speed mode: max. 400 kHz). 18.2.5 I2C Bus Control Register (ICCR) 18.2.6 I2C Bus Status Register (ICSR) 746 Bit 4  Transmit/Receive Select (TRS) No.4 description deleted from clearing conditions 757 Bit 0  Acknowledge Bit (ACKB) Description added ... the value set by internal software is read. In addition, writing to this bit overwrites the setting for acknowledge data sent when receiving data, regardless of the TRS value. In this case the value loaded from the receive device is maintained unchanged, so caution is necessary when using instructions that manipulate the bits in this register. 18.3.5 Slave Transmit Operation Figure 18.11 Example of Slave Transmit Mode Operation Timing (MLS = 0) 771 Figure 18.11 amended Slave receive mode SCL (master output) SCL (slave output) 8 9 SDA (slave output) A Rev. 3.00 Jan 11, 2005 page xx of liv Item Page Revisions (See Manual for Details) Table 18.7 amended Time Indication I C Bus Specification φ = (Max.) 5 MHz Standard mode 2 18.4 Usage Notes 782 Table 18.7 Permissible SCL Rise Time (tSr) Values tcyc IICX Indication 0 7.5 tcyc φ= 8 MHz φ= φ= φ= φ= φ= 10 MHz 16 MHz 20 MHz 25 MHz 28 MHz 750 ns 468 ns 375 ns 300 ns 300 ns 300 ns     1000 ns 1000 ns 937 ns 300 ns 300 ns High-speed 300 ns mode 1 17.5 tcyc Standard mode 1000 ns 1000 ns 1000 ns 1000 ns 1000 ns875 ns 300 ns 300 ns 300 ns 300 ns 300 ns 700 ns 624 ns 300 ns 300 ns High-speed 300 ns mode Note added Note:When 7.5 tcyc is selected as the transfer rate, the actual transfer rate may be extended if φ exceeds 20 MHz. 788 to 792 (10) Notes on IRIC Flag Clearance when Using Wait Function (11) Notes on ICDR Reads and ICCR Access in Slave Transmit Mode (12) Notes on TRS Bit Setting in Slave Mode (13) Notes on ICDR Reads in Transmit Mode and ICDR Writes in Receive Mode (14) Notes on ACKE Bit and TRS Bit in Slave Mode (15) Notes on Arbitration Lost in Master Mode Description added 19.2.2 A/D Control/Status Register (ADCSR) 798 Bit 7—A/D End Flag (ADF): Description amended [Clearing conditions] • W hen 0 is written to the ADF flag after reading ADF = 1 • W hen the DMAC or DTC is activated by an ADI interrupt and ADDR is read 19.4.3 Input Sampling and A/D Conversion Time 19.6 Usage Notes 808 Description amended ... at least 10 µs when AVCC ≥ 4.5V, and at least 16 µs when AVCC < 4.5V. 811 (1) Setting Range of Analog Power Supply and Other Pins: (a) Analog input voltage range Description amended The voltage applied to analog input pin ANn during A/D conversion should be in the range AVSS ANn Vref. Table 19.7 Analog Pin Specifications 812 Table 19.7 amended Unit (Before) k → (After) kΩ Rev. 3.00 Jan 11, 2005 page xxi of liv Unit of permissible signal source impedance ≤ ≤ Item 20.1.4 Register Configuration Table 20.2 D/A Converter Registers Page 819 Revisions (See Manual for Details) Table 20.2 amended Channel All Name Module stop control register A Module stop control register C Abbreviation MSTPCRA MSTPCRC R/W R/W R/W Initial Value H'3F H'FF Address* H'FDE8 H'FDEA 22.11.1 Socket 874 Adapter and Memory Map 891 22.14 Note on Switching from FZTAT Version to Masked ROM Version Table 22.27 Registers Present in F-ZTAT Version but Absent in Masked ROM Version 23.2.2 Low-Power Control Register (LPWRCR) 896 22.11.1 replaced Table 22.27 amended Abbreviation FLMCR1 FLMCR2 EBR1 EBR2 RAMER Address H'FFA8 H'FFA9 H'FFAA H'FFAB H'FEDB Bits 1 and 0  Frequency Multiplication Factor (STC1, STC0): Note description added Note: …in section 25, Electrical Characteristics. Current consumption and noise can be reduced by using this function’s PLL ×4 setting and lowering the external clock frequency. 23.3.2 External Clock 900 Input Table 23.4 External Clock Input Conditions 24.12 φ Clock Output Disabling Function 931 (2) External Clock Clock low pulse width level and Clock high pulse width level test conditions amended (Before) φ 5MHz → (After) φ ≥ 5 MHz Description added ... in each processing state. Using the on-chip PLL circuit to lower the oscillator frequency or prohibiting external φ clock output also have the effect of reducing unwanted electromagnetic interference*. Therefore, consideration should be given to these options when deciding on system board settings. Note: * Electromagnetic interference: EMI (Electro Magnetic Interference) Rev. 3.00 Jan 11, 2005 page xxii of liv Item 25.2 DC Characteristics Table 25.2 DC Characteristics (1) Page 934 Revisions (See Manual for Details) Table 25.2 (1) amended Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = PLLVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide1 range specifications)* Item Input leakage current RES, FWE* 5 Symbol | Iin | STBY, NMI, MD2 to MD0 Ports 4, 9 Min. — — — Typ. — — — — Max. 1.0 1.0 1.0 1.0 Unit µA µA µA µA Test Conditions Vin = 0.5 to PVCC – 0.5 V Vin = 0.5 to AVCC – 0.5 V Vin = 0.5 to PVCC – 0.5 V Ta ≤ 50 °C 50˚C < Ta Three-state leakage current (off state) Current 2 dissipation* Ports 1, 2, 3, 5, 7, 8, A to G ITSI — Standby mode — — 1.0 — Typ. — 5.0 20 Max. — µA 936 Item RAM standby voltage* 3 Symbol VRAM Min. 2.0 Unit V Test Conditions Notes amended Notes: 1. ... Set Vref ≤ AVCC. 4. The values are for VRAM ≤ VCC < 3.0 V, ... Table 25.2 DC Characteristics (2) 937 Table 25.2 (2) amended  Preliminary  deleted Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V*7, Vref = 3.6 V to AVCC*8, VSS = AVSS = PLLVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)*1 Item Input leakage current RES, FWE* 6 Symbol | Iin | Min. — — — Typ. — — — Max. 1.0 1.0 1.0 Unit µA µA µA Test Conditions Vin = 0.5 to PVCC – 0.5 V Vin = 0.5 to AVCC – 0.5 V Test Conditions Vin = 0.5 to PVCC – 0.5 V STBY, NMI, MD2 to MD0 Ports 4, 9 938 Item Three-state leakage current (off state) Current 3 dissipation* Symbol Min. Ports 1, 2, 3, | ITSI | 5, 7, 8, A to G — Typ. — Max. 1.0 Unit µA Standby mode — — 1.0 — 5.0 20 µA Ta ≤ 50˚C 50˚C < Ta Rev. 3.00 Jan 11, 2005 page xxiii of liv Item 25.2 DC Characteristics Table 25.2 DC Characteristics (2) Page 939 Revisions (See Manual for Details) Table 25.2 (2) amended Item Port power supply current* 3 Symbol Min Operating Subclock operation Standby Watch mode PICC — — — — VRAM 2.0 Typ Max Unit mA µA Test Conditions 10 16 PVCC = 5.0 V — 0.5 — — 50 5.0 20 — Ta ≤ 50 °C 50 °C < Ta V RAM standby voltage* 4 Notes amended Notes: 1. …Set Vref ≤ AVCC. 4. The values are for VRAM ≤ VCC < 3.0 V, ... 7. AVCC = 3.3 V to 5.5 V if the A/D and D/A converters are not used (used as I/O ports). 8. Vref = 3.3 V to AVCC if the A/D and D/A converters are not used (used as I/O ports). Table 25.3 Permissible Output Currents 940 Table 25.3 conditions amended Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V*1, Vref = 3.6 V to AVCC*2, VSS = AVSS = PLLVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)*1 Notes added Notes:1. 2. 941 Table 25.4 Bus Drive Characteristics AVCC = 3.3 V to 5.5 V if the A/D and D/A converters are not used (used as I/O ports). Vref = 3.3 V to AVCC if the A/D and D/A converters are not used (used as I/O ports). Table 25.4 conditions amended (Before) VSS = AVSS = 0 V → (After) VSS = AVSS = PLLVSS = 0 V Rev. 3.00 Jan 11, 2005 page xxiv of liv Item Table 25.5 Clock Timing to 25.3.4 DMAC Timing Table 25.8 DMAC Timing Page Revisions (See Manual for Details) Condition A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V*1, Vref = 3.6 V to AVCC*2, VSS = AVSS = PLLVSS = 0 V, φ = 32.768 kHz, 2 to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = PLLVSS = 0 V, φ = 32.768 kHz, 2 to 25 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Notes added Notes: 1. AVCC = 3.3 V to 5.5 V if the A/D and D/A converters are not used (used as I/O ports). 2. Vref = 3.3 V to AVCC if the A/D and D/A converters are not used (used as I/O ports). 25.3.1 Clock Timing 943 to 957 Table 25.5 to 25.8 conditions amended 25.3.5 Timing of On- 961, 962 Chip Supporting Modules Table 25.9 Timing of On-Chip Supporting Modules Table 25.9 conditions amended Condition A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V*2, Vref = 3.6 V to 3 AVCC* , VSS = AVSS = PLLVSS = 0 V, φ = 32.768 kHz*1, 2 to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = PLLVSS = 0 V, φ = 32.768 kHz*1, 2 to 25 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Notes 2 and 3 added Notes: 1. Only available I/O port, TMR, WDT0, and WDT1. 2. AVCC = 3.3 V to 5.5 V if the A/D and D/A converters are not used (used as I/O ports). 3. Vref = 3.3 V to AVCC if the A/D and D/A converters are not used (used as I/O ports). Rev. 3.00 Jan 11, 2005 page xxv of liv Item Page Revisions (See Manual for Details) Table 25.10 conditions replaced Notes 2 and 3 added Notes: 1. 17.5 tcyc can be set …. 2. AVCC = 3.3 V to 5.5 V if the A/D and D/A converters are not used (used as I/O ports). 3. Vref = 3.3 V to AVCC if the A/D and D/A converters are not used (used as I/O ports). 25.3.5 Timing of On- 967 Chip Supporting Modules Table 25.10 I2C Bus Timing 25.4 A/D Conversion 969, 970 Characteristics Table 25.11 A/D Conversion Characteristics 25.5 D/A Conversion Characteristics Table 25.12 D/A Conversion Characteristics Table 25.11 and 25.12 conditions amended Condition A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V*1, Vref = 3.6 V to AVCC*2, VSS = AVSS = PLLVSS = 0 V, φ = 2 to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = PLLVSS = 0 V, φ = 2 to 25 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Notes added Notes: 1. AVCC = 3.3 V to 5.5 V if the A/D and D/A converters are not used (used as I/O ports). 2. Vref = 3.3 V to AVCC if the A/D and D/A converters are not used (used as I/O ports). 25.6 Flash Memory 971 Characteristics Table 25.13 Flash Memory Characteristics A.2 Instruction Codes 1005 Table 25.13 conditions amended Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = PLLVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Table A.2 amended and note *3 added LDM*3 MOV.L #xx:32,ERd STM*3 Notes: … 3. Only register ER0 to ER6 should be used when using the STM/LDM instruction. Table A.2 Instruction 1006 Codes 1010 1011 Rev. 3.00 Jan 11, 2005 page xxvi of liv Item Page Revisions (See Manual for Details) Note *5 added to table A.5 5 LDM* 1024 A.4 Number of States Required for Instruction Execution Table A.5 Number of Cycles in Instruction Execution 1028 1029 A.5 Bus States during Instruction Execution Table A.6 Instruction Execution Cycles 1042 1037 STM*5 Notes: … 5. Only register ER0 to ER6 should be used when using the STM/LDM instruction. Note *9 added to table A.6 LDM.L @Sp+, (ERn-ERn+1)* 9 LDM.L @Sp+, (ERn-ERn+2)*9 LDM.L @Sp+, (ERn-ERn+3)*9 STM.L (ERn-ERn+1) @-Sp*9 STM.L (ERn-ERn+2) @-Sp*9 STM.L (ERn-ERn+3) @-Sp*9 1043 Notes: … 9. Only register ER0 to ER6 should be used when using the STM/LDM instruction. Table amended Register Address Name H'FFB9 PORTA Bit 7 PA7 Bit 6 PA6 Bit 5 PA5 Bit 4 PA4 Bit 3 PA3 Bit 2 PA2 Bit 1 PA1 Bit 0 PA0 Module Name Port Data Bus Width (bits) 8 B.1 Addreses 1060 B.2 Functions 1062 SCRX—Serial Control Register X H'FDB4 IIC Figure amended Bit : 7 — Initial value : R/W : 0 R/W 6 IICX1 0 R/W 5 IICX0 0 R/W 4 IICE 0 R/W 3 FLSHE 0 R/W 2 — 0 R/W 1 — 0 R/W 0 — 0 R/W Flash memory control register enable 0 1 Flash control registers deselected in area H'FFFFA8 to H'FFFFAC Flash control registers selected in area H'FFFFA8 to H'FFFFAC I2C master enable 0 1 Disables CPU access of I2C bus interface data register and control register Enables CPU access of I C bus interface data register and control register 2 I2C transfer rate select 1, 0 The master mode transfer rate is selected in combination with CKS2 to CKS0 in ICMR. For details, see the section on the I2C bus mode register. Rev. 3.00 Jan 11, 2005 page xxvii of liv Item B.2 Functions Page 1075 Revisions (See Manual for Details) SSR0  Serial Status Register 0 H'FF7C SCI0 SSR1  Serial Status Register 1 H'FF84 SCI1 SSR2  Serial Status Register 2 H'FF8C SCI2 SSR3  Serial Status Register 3 H'FFD4 SCI3 SSR4  Serial Status Register 4 H'FFDC SCI4 Figure amended Bit : 7 TDRE Initial value : R/W : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor bit transfer (MPBT) 0 1 Transfer data “multiprocessor bit = 0” Transfer data “multiprocessor bit = 1” Multiprocessor bit (MPB) 0 1 [Clearing condition]* • When data “multiprocessor bit = 0” is received [Setting condition] • When data “multiprocessor bit = 1” is received Note: * The existing status is continued when, in multiprocessor format, the SCR RE bit is cleared to 0. Transmit end (TEND) 0 [Clearing conditions] • Writing 0 to TDRE flag after reading TDRE=1 • When data is written to TDR by DMAC or DTC by TXI interrupt request [Setting conditions] • When SCR TE bit=0 • When TDRE=1 at transfer of last bit of any byte of serial transmit character 1 Parity error (PER) 0 1 [Clearing condition]*1 • Writing 0 to PER after reading PER=1 [Setting condition] • When receiving, when the number of 1s in receive data plus parity bit does not match the even or odd parity specified in the SMR O/E bit *2 Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. Framing error (FER) 0 1 [Clearing condition] *1 • Writing 0 to FER after reading FER=1 [Setting condition] • When SCI checks if the stop bit at the end of receive data is 1 on completion of receiving, the stop bit is found to be 0 Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. Overrun error (ORER) 0 1 [Clearing condition]*1 • Writing 0 to ORER after reading ORER=1 [Setting condition] • On completion of next serial receive operation when RDRF=1 *2 Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. Receive data register full (RDRF) 0 [Clearing conditions] • Writing 0 to RDRF after reading RDRF=1 • After reading RDR data by DMAC or DTC by RXI interrupt request [Setting condition] • When receive data is sent from RSR to RDR on normal completion of serial receive operation 1 Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Transmit data register empty (TDRE) 0 [Clearing conditions] • Writing 0 to TDRE after reading TDRE=1 • When data written to TDR by DMAC or DTC by TXI interrupt request [Setting conditions] • When SCR TE bit=0 • When data is sent from TDR to TSR and data can be written to TDR 1 Note: * Only 0 can be written to these bits (to clear these flags). Rev. 3.00 Jan 11, 2005 page xxviii of liv Item B.2 Functions Page 1078 Revisions (See Manual for Details) SYSCRSystem Control Register H'FDE5 System Figure amended Bit : 7 MACS Initial value : R/W : 0 R/W 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W 3 0 R/W 2 0 R/W 1 — 0 — 0 RAME 1 R/W NMIEG MRESE RAM Enable 0 1 Internal RAM disabled Internal RAM enabled Manual reset select bit 0 Manual reset disabled Pins P74/TMO2/MRES can be used as P74/TMO2 I/O pins Manual reset enabled Pins P74/TMO2/MRES can be used as MRES input pins Pin RES 0 1 1 NMI edge select 0 1 Interrupt control mode 1, 0 INTM1 0 1 INTM0 0 1 0 1 MAC saturation 0 1 Non-saturating calculation for MAC instruction Saturating calculation for MAC instruction Interrupt control mode 1 MRES 1 0 1 Reset Type Power-on reset Manual reset Operation state Interrupt request issued on falling edge of NMI input Interrupt request issued on rising edge of NMI input Description Interrupt controlled by bit I Do not set Interrupt controlled by bits I2 to I0 and IPR Do not set 0 — 2 — 1080 Figure amended MDCR—Mode Control Register H'FDE7 System Bit : 7 — Initial value : R/W : 1 R/W 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 MDS2 —* R 1 MDS1 —* R 0 MDS0 —* R Note: * Determined by pins MD2 to MD0. Mode select 2 to 0 * Input level determined by mode pins. Rev. 3.00 Jan 11, 2005 page xxix of liv Item B.2 Functions Page 1080 Revisions (See Manual for Details) MSTPCRA—Module Stop Control Register AH'FDE8 System Bit : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : Module stop 0 1 Module stop mode is cleared Module stop mode is set MSTPCRB—Module Stop Control Register BH'FDE9 System Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : R/W : Module stop 0 1 Module stop mode canceled Module stop mode enabled 1081 MSTPCRC—Module Stop Control Register C H'FDEA System Figure amended Bit : 7 1 R/W 6 1 R/W Module stop 0 1 Module stop mode canceled Module stop mode enabled 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : R/W : 1083 LPWRCR—Low-Power Control Register H'FDEC System Figure amended 1 STC1 0 R/W 0 STC0 0 R/W Frequency multiplier STC1 0 1 STC0 0 1 0 1 Description ×1 ×2 ×4 Do not set Note: A system clock frequency multiplied by the multiplication factor (STC1 and STC0) should not exceed the maximum operating frequency defined in section 25, Electrical Characteristics. Current consumption and noise can be reduced by using this function's PLL × 4 setting and lowering the external clock frequency. Rev. 3.00 Jan 11, 2005 page xxx of liv Item B.2 Functions Page 1094 Revisions (See Manual for Details) NDRH—Next Data Register H H'FE2C, H'FE2E PPG Figure amended Same trigger for pulse output groups: Address: H'FE2C Bit : 7 NDR15 Initial value : R/W : 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Address: H'FE2E Bit : 7 — Initial value : R/W : 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Different triggers for pulse output groups: Address: H'FE2C Bit : 7 NDR15 Initial value : R/W : 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Address: H'FE2E Bit : 7 — Initial value : R/W : 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Rev. 3.00 Jan 11, 2005 page xxxi of liv Item B.2 Functions Page 1095 Revisions (See Manual for Details) NDRL—Next Data Register L H'FE2D, H'FE2F PPG Figure amended Same trigger for pulse output groups: Address: H'FE2D Bit : 7 NDR7 Initial value : R/W : 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Address: H'FE2F Bit : 7 — Initial value : R/W : 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Different triggers for pulse output groups: Address: H'FE2D Bit : 7 NDR7 Initial value : R/W : 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Address: H'FE2F Bit : 7 — Initial value : R/W : 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W 1114 Subtitle amended TCNT0—Timer Counter 0 (up-counter) TCNT0—Timer Counter 1 (up/down-counter*) TCNT0—Timer Counter 2 (up/down-counter*) TCNT0—Timer Counter 3 (up-counter) TCNT0—Timer Counter 4 (up/down-counter*) TCNT0—Timer Counter 5 (up/down-counter*) Rev. 3.00 Jan 11, 2005 page xxxii of liv Item B.2 Functions Page 1155 Revisions (See Manual for Details) TCSR1—Timer Control/Status Register 1 H'FFA2 (W), H'FFA2 (R) WDT1 4 PSS 0 R/W Prescaler select 0 TCNT counts the divided clock output by the φ-based prescaler (PSM) 1 TCNT counts the divided clock output by the φSUB-based prescaler (PSS) C.6 Port 7 Block Diagrams Figure C.6 (b) Port 7 Block Diagram (Pin P72) 1183 Figure C.6 (b) amended RDR7 8-bit timer Timer output TMO0 Timer output enable RPOR7 Note amended Note: * Priority order: (Mode 7) 8-bit timer output > DR output (Modes 4 to 6) Chip select output > 8-bit timer output > DR output Note amended Note: * Priority order: (Mode 7) 8-bit timer output > DR output (Modes 4 to 6) Chip select output > 8-bit timer output > DR output Figure C.9 amended Figure C.6 (c) Port 7 1184 Block Diagram (Pin P73) C.9 Port A Block Diagrams Figure C.9 Port A Block Diagram (Pins PA0 to PA7) 1194 PAn  Figures of “Port A Block Diagram (Pin PA1)” to “Port A Block Diagram (Pins PA4 to PA7)” deleted Rev. 3.00 Jan 11, 2005 page xxxiii of liv Item F. Product Code Lineup Table F.1 H8S/2643 Group Product Code Lineup Page 1217 Revisions (See Manual for Details) Table F.1 amended Product Code Package (Package Code) 144-pin QFP (FP-144J) 144-pin TQFP (TFP-144) 144-pin QFP (FP-144J) 144-pin TQFP (TFP-144) 144-pin QFP (FP-144J) 144-pin TQFP (TFP-144) 144-pin QFP (FP-144J) 144-pin TQFP (TFP-144) Product Type H8S/2643 F-ZTAT Mark Code HD64F2643 HD64F2643FC HD64F2643TF Masked ROM HD6432643 HD6432643FC HD6432643TF H8S/2642 HD6432642 HD6432642FC HD6432642TF H8S/2641 HD6432641 HD6432641FC HD6432641TF G. Package Dimensions  Figure G.1 FP-144F package dimensions deleted Figure G.1 added Figure G.2 added Figure G.1 FP-144J 1218 Package Dimensions Figure G.2 TFP144J Package Dimensions 1219 Rev. 3.00 Jan 11, 2005 page xxxiv of liv Contents Section 1 Overview ............................................................................................................. 1.1 1.2 1.3 1 Overview........................................................................................................................... 1 Internal Block Diagram..................................................................................................... 6 Pin Description ................................................................................................................. 7 1.3.1 Pin Arrangement.................................................................................................. 7 1.3.2 Pin Functions in Each Operating Mode ............................................................... 8 1.3.3 Pin Functions ....................................................................................................... 13 Section 2 CPU ...................................................................................................................... 21 2.1 Overview........................................................................................................................... 2.1.1 Features................................................................................................................ 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 2.1.3 Differences from H8/300 CPU ............................................................................ 2.1.4 Differences from H8/300H CPU ......................................................................... CPU Operating Modes...................................................................................................... Address Space................................................................................................................... Register Configuration...................................................................................................... 2.4.1 Overview.............................................................................................................. 2.4.2 General Registers................................................................................................. 2.4.3 Control Registers ................................................................................................. 2.4.4 Initial Register Values ......................................................................................... Data Formats..................................................................................................................... 2.5.1 General Register Data Formats............................................................................ 2.5.2 Memory Data Formats ......................................................................................... Instruction Set................................................................................................................... 2.6.1 Overview.............................................................................................................. 2.6.2 Instructions and Addressing Modes..................................................................... 2.6.3 Table of Instructions Classified by Function ....................................................... 2.6.4 Basic Instruction Formats .................................................................................... Addressing Modes and Effective Address Calculation..................................................... 2.7.1 Addressing Mode................................................................................................. 2.7.2 Effective Address Calculation ............................................................................. Processing States............................................................................................................... 2.8.1 Overview.............................................................................................................. 2.8.2 Reset State ........................................................................................................... 2.8.3 Exception-Handling State .................................................................................... 2.8.4 Program Execution State ..................................................................................... 21 21 22 23 23 24 29 30 30 31 32 34 35 35 37 38 38 39 41 48 50 50 53 57 57 58 59 62 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Rev. 3.00 Jan 11, 2005 page xxxv of liv 2.8.5 Bus-Released State............................................................................................... 2.8.6 Power-Down State ............................................................................................... 2.9 Basic Timing ..................................................................................................................... 2.9.1 Overview.............................................................................................................. 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 2.9.3 On-Chip Supporting Module Access Timing....................................................... 2.9.4 External Address Space Access Timing............................................................... 2.10 Usage Note........................................................................................................................ 2.10.1 TAS Instruction.................................................................................................... 2.10.2 STM/LDM Instruction ......................................................................................... 2.10.3 Bit Manipulation Instructions............................................................................... 62 62 63 63 63 65 66 66 66 67 67 Section 3 MCU Operating Modes................................................................................... 69 3.1 Overview........................................................................................................................... 3.1.1 Operating Mode Selection.................................................................................... 3.1.2 Register Configuration ......................................................................................... Register Descriptions ........................................................................................................ 3.2.1 Mode Control Register (MDCR).......................................................................... 3.2.2 System Control Register (SYSCR) ...................................................................... 3.2.3 Pin Function Control Register (PFCR) ................................................................ Operating Mode Descriptions ........................................................................................... 3.3.1 Mode 4 ................................................................................................................. 3.3.2 Mode 5 ................................................................................................................. 3.3.3 Mode 6 ................................................................................................................. 3.3.4 Mode 7 ................................................................................................................. Pin Functions in Each Operating Mode ............................................................................ Address Map in Each Operating Mode ............................................................................. 69 69 70 70 70 71 73 76 76 76 76 76 77 77 3.2 3.3 3.4 3.5 Section 4 Exception Handling.......................................................................................... 81 4.1 Overview........................................................................................................................... 4.1.1 Exception Handling Types and Priority ............................................................... 4.1.2 Exception Handling Operation............................................................................. 4.1.3 Exception Vector Table........................................................................................ Reset ................................................................................................................................. 4.2.1 Overview.............................................................................................................. 4.2.2 Types of Reset...................................................................................................... 4.2.3 Reset Sequence .................................................................................................... 4.2.4 Interrupts after Reset ............................................................................................ 4.2.5 State of On-Chip Supporting Modules after Reset Release ................................. Traces ................................................................................................................................ Interrupts ........................................................................................................................... 81 81 82 82 84 84 84 85 87 87 88 89 4.2 4.3 4.4 Rev. 3.00 Jan 11, 2005 page xxxvi of liv 4.5 4.6 4.7 Trap Instruction................................................................................................................. 90 Stack Status after Exception Handling.............................................................................. 91 Notes on Use of the Stack................................................................................................. 92 Section 5 Interrupt Controller .......................................................................................... 93 5.1 Overview........................................................................................................................... 5.1.1 Features................................................................................................................ 5.1.2 Block Diagram..................................................................................................... 5.1.3 Pin Configuration................................................................................................. 5.1.4 Register Configuration......................................................................................... Register Descriptions........................................................................................................ 5.2.1 System Control Register (SYSCR) ...................................................................... 5.2.2 Interrupt Priority Registers A to L, O (IPRA to IPRL, IPRO)............................. 5.2.3 IRQ Enable Register (IER) .................................................................................. 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 5.2.5 IRQ Status Register (ISR).................................................................................... Interrupt Sources............................................................................................................... 5.3.1 External Interrupts ............................................................................................... 5.3.2 Internal Interrupts ................................................................................................ 5.3.3 Interrupt Exception Handling Vector Table......................................................... Interrupt Operation ........................................................................................................... 5.4.1 Interrupt Control Modes and Interrupt Operation................................................ 5.4.2 Interrupt Control Mode 0..................................................................................... 5.4.3 Interrupt Control Mode 2..................................................................................... 5.4.4 Interrupt Exception Handling Sequence .............................................................. 5.4.5 Interrupt Response Times .................................................................................... Usage Notes ...................................................................................................................... 5.5.1 Contention between Interrupt Generation and Disabling..................................... 5.5.2 Instructions that Disable Interrupts...................................................................... 5.5.3 Times when Interrupts are Disabled .................................................................... 5.5.4 Interrupts during Execution of EEPMOV Instruction ......................................... 5.5.5 IRQ Interrupt ....................................................................................................... 5.5.6 NMI Interrupt Usage Notes ................................................................................. DTC and DMAC Activation by Interrupt ......................................................................... 5.6.1 Overview.............................................................................................................. 5.6.2 Block Diagram..................................................................................................... 5.6.3 Operation ............................................................................................................. 93 93 94 95 95 96 96 97 98 99 100 101 101 102 103 108 108 111 113 115 116 117 117 118 118 119 119 119 120 120 120 121 5.2 5.3 5.4 5.5 5.6 Section 6 PC Break Controller (PBC) ........................................................................... 123 6.1 Overview........................................................................................................................... 123 6.1.1 Features................................................................................................................ 123 Rev. 3.00 Jan 11, 2005 page xxxvii of liv 6.2 6.3 6.1.2 Block Diagram ..................................................................................................... 6.1.3 Register Configuration ......................................................................................... Register Descriptions ........................................................................................................ 6.2.1 Break Address Register A (BARA) ..................................................................... 6.2.2 Break Address Register B (BARB)...................................................................... 6.2.3 Break Control Register A (BCRA) ...................................................................... 6.2.4 Break Control Register B (BCRB)....................................................................... 6.2.5 Module Stop Control Register C (MSTPCRC).................................................... Operation........................................................................................................................... 6.3.1 PC Break Interrupt Due to Instruction Fetch........................................................ 6.3.2 PC Break Interrupt Due to Data Access............................................................... 6.3.3 Notes on PC Break Interrupt Handling ................................................................ 6.3.4 Operation in Transitions to Power-Down Modes................................................. 6.3.5 PC Break Operation in Continuous Data Transfer ............................................... 6.3.6 When Instruction Execution is Delayed by One State ......................................... 6.3.7 Additional Notes .................................................................................................. 124 125 125 125 126 126 128 128 128 128 129 130 130 131 131 132 Section 7 Bus Controller .................................................................................................... 133 7.1 Overview........................................................................................................................... 7.1.1 Features ................................................................................................................ 7.1.2 Block Diagram ..................................................................................................... 7.1.3 Pin Configuration................................................................................................. 7.1.4 Register Configuration ......................................................................................... Register Descriptions ........................................................................................................ 7.2.1 Bus Width Control Register (ABWCR) ............................................................... 7.2.2 Access State Control Register (ASTCR).............................................................. 7.2.3 Wait Control Registers H and L (WCRH, WCRL) .............................................. 7.2.4 Bus Control Register H (BCRH).......................................................................... 7.2.5 Bus Control Register L (BCRL)........................................................................... 7.2.6 Pin Function Control Register (PFCR) ................................................................ 7.2.7 Memory Control Register (MCR) ........................................................................ 7.2.8 DRAM Control Register (DRAMCR) ................................................................. 7.2.9 Refresh Timer Counter (RTCNT) ........................................................................ 7.2.10 Refresh Time Constant Register (RTCOR).......................................................... Overview of Bus Control .................................................................................................. 7.3.1 Area Partitioning .................................................................................................. 7.3.2 Bus Specifications................................................................................................ 7.3.3 Memory Interfaces ............................................................................................... 7.3.4 Interface Specifications for Each Area................................................................. 7.3.5 Chip Select Signals .............................................................................................. Basic Bus Interface ........................................................................................................... 133 133 135 136 137 138 138 139 140 144 146 148 151 153 155 156 157 157 158 159 160 161 162 7.2 7.3 7.4 Rev. 3.00 Jan 11, 2005 page xxxviii of liv 7.4.1 Overview.............................................................................................................. 7.4.2 Data Size and Data Alignment............................................................................. 7.4.3 Valid Strobes ....................................................................................................... 7.4.4 Basic Timing........................................................................................................ 7.4.5 Wait Control ........................................................................................................ 7.5 DRAM Interface ............................................................................................................... 7.5.1 Overview.............................................................................................................. 7.5.2 Setting Up DRAM Space..................................................................................... 7.5.3 Address Multiplexing .......................................................................................... 7.5.4 Data Bus .............................................................................................................. 7.5.5 DRAM Interface Pins .......................................................................................... 7.5.6 Basic Timing........................................................................................................ 7.5.7 Precharge State Control ....................................................................................... 7.5.8 Wait Control ........................................................................................................ 7.5.9 Byte Access Control ............................................................................................ 7.5.10 Burst Operation.................................................................................................... 7.5.11 Refresh Control.................................................................................................... 7.6 DMAC Single Address Mode and DRAM Interface ........................................................ 7.6.1 DDS = 1 ............................................................................................................... 7.6.2 DDS = 0 ............................................................................................................... 7.7 Burst ROM Interface ........................................................................................................ 7.7.1 Overview.............................................................................................................. 7.7.2 Basic Timing........................................................................................................ 7.7.3 Wait Control ........................................................................................................ 7.8 Idle Cycle.......................................................................................................................... 7.8.1 Operation ............................................................................................................. 7.8.2 Pin States in Idle Cycle........................................................................................ 7.9 Write Data Buffer Function .............................................................................................. 7.10 Bus Release....................................................................................................................... 7.10.1 Overview.............................................................................................................. 7.10.2 Operation ............................................................................................................. 7.10.3 Pin States in External Bus Released State ........................................................... 7.10.4 Transition Timing ................................................................................................ 7.10.5 Notes.................................................................................................................... 7.11 Bus Arbitration ................................................................................................................. 7.11.1 Overview.............................................................................................................. 7.11.2 Operation ............................................................................................................. 7.11.3 Bus Transfer Timing............................................................................................ 7.12 Resets and the Bus Controller........................................................................................... 162 162 164 165 173 175 175 175 176 176 177 177 179 180 184 186 190 194 194 196 198 198 198 200 201 201 205 206 207 207 207 208 209 210 211 211 211 212 213 Rev. 3.00 Jan 11, 2005 page xxxix of liv Section 8 DMA Controller ................................................................................................ 215 8.1 Overview........................................................................................................................... 8.1.1 Features ................................................................................................................ 8.1.2 Block Diagram ..................................................................................................... 8.1.3 Overview of Functions......................................................................................... 8.1.4 Pin Configuration................................................................................................. 8.1.5 Register Configuration ......................................................................................... Register Descriptions (1) (Short Address Mode) .............................................................. 8.2.1 Memory Address Register (MAR) ....................................................................... 8.2.2 I/O Address Register (IOAR)............................................................................... 8.2.3 Execute Transfer Count Register (ETCR)............................................................ 8.2.4 DMA Control Register (DMACR)....................................................................... 8.2.5 DMA Band Control Register (DMABCR)........................................................... Register Descriptions (2) (Full Address Mode) ................................................................ 8.3.1 Memory Address Register (MAR) ....................................................................... 8.3.2 I/O Address Register (IOAR)............................................................................... 8.3.3 Execute Transfer Count Register (ETCR)............................................................ 8.3.4 DMA Control Register (DMACR)....................................................................... 8.3.5 DMA Band Control Register (DMABCR)........................................................... Register Descriptions (3)................................................................................................... 8.4.1 DMA Write Enable Register (DMAWER) .......................................................... 8.4.2 DMA Terminal Control Register (DMATCR)..................................................... 8.4.3 Module Stop Control Register (MSTPCR) .......................................................... Operation........................................................................................................................... 8.5.1 Transfer Modes .................................................................................................... 8.5.2 Sequential Mode .................................................................................................. 8.5.3 Idle Mode ............................................................................................................. 8.5.4 Repeat Mode ........................................................................................................ 8.5.5 Single Address Mode ........................................................................................... 8.5.6 Normal Mode ....................................................................................................... 8.5.7 Block Transfer Mode ........................................................................................... 8.5.8 DMAC Activation Sources .................................................................................. 8.5.9 Basic DMAC Bus Cycles..................................................................................... 8.5.10 DMAC Bus Cycles (Dual Address Mode) ........................................................... 8.5.11 DMAC Bus Cycles (Single Address Mode)......................................................... 8.5.12 Write Data Buffer Function.................................................................................. 8.5.13 DMAC Multi-Channel Operation ........................................................................ 8.5.14 Relation between External Bus Requests, Refresh Cycles, the DTC, and the DMAC ..................................................................................................... 8.5.15 NMI Interrupts and DMAC.................................................................................. 8.5.16 Forced Termination of DMAC Operation............................................................ 215 215 216 217 219 220 221 222 223 223 224 229 234 234 235 235 237 241 246 246 249 250 251 251 253 257 260 264 267 270 276 279 280 288 294 295 297 298 299 8.2 8.3 8.4 8.5 Rev. 3.00 Jan 11, 2005 page xl of liv 8.6 8.7 8.5.17 Clearing Full Address Mode................................................................................ 300 Interrupts........................................................................................................................... 301 Usage Notes ...................................................................................................................... 302 Section 9 Data Transfer Controller (DTC)................................................................... 307 9.1 Overview........................................................................................................................... 9.1.1 Features................................................................................................................ 9.1.2 Block Diagram..................................................................................................... 9.1.3 Register Configuration......................................................................................... Register Descriptions........................................................................................................ 9.2.1 DTC Mode Register A (MRA) ............................................................................ 9.2.2 DTC Mode Register B (MRB)............................................................................. 9.2.3 DTC Source Address Register (SAR).................................................................. 9.2.4 DTC Destination Address Register (DAR).......................................................... 9.2.5 DTC Transfer Count Register A (CRA) .............................................................. 9.2.6 DTC Transfer Count Register B (CRB)............................................................... 9.2.7 DTC Enable Register (DTCER) .......................................................................... 9.2.8 DTC Vector Register (DTVECR)........................................................................ 9.2.9 Module Stop Control Register A (MSTPCRA) ................................................... Operation .......................................................................................................................... 9.3.1 Overview.............................................................................................................. 9.3.2 Activation Sources............................................................................................... 9.3.3 DTC Vector Table ............................................................................................... 9.3.4 Location of Register Information in Address Space ............................................ 9.3.5 Normal Mode....................................................................................................... 9.3.6 Repeat Mode........................................................................................................ 9.3.7 Block Transfer Mode ........................................................................................... 9.3.8 Chain Transfer ..................................................................................................... 9.3.9 Operation Timing................................................................................................. 9.3.10 Number of DTC Execution States ....................................................................... 9.3.11 Procedures for Using DTC .................................................................................. 9.3.12 Examples of Use of the DTC ............................................................................... Interrupts........................................................................................................................... Usage Notes ...................................................................................................................... 307 307 308 309 310 310 312 313 313 313 314 314 315 316 318 318 320 321 326 327 328 329 331 332 333 334 335 338 338 9.2 9.3 9.4 9.5 Section 10 I/O Ports ............................................................................................................ 339 10.1 Overview........................................................................................................................... 339 10.2 Port 1................................................................................................................................. 345 10.2.1 Overview.............................................................................................................. 345 10.2.2 Register Configuration......................................................................................... 346 10.2.3 Pin Functions ....................................................................................................... 348 Rev. 3.00 Jan 11, 2005 page xli of liv 10.3 Port 2 ................................................................................................................................. 10.3.1 Overview.............................................................................................................. 10.3.2 Register Configuration ......................................................................................... 10.3.3 Pin Functions........................................................................................................ 10.4 Port 3 ................................................................................................................................. 10.4.1 Overview.............................................................................................................. 10.4.2 Register Configuration ......................................................................................... 10.4.3 Pin Functions........................................................................................................ 10.5 Port 4 ................................................................................................................................. 10.5.1 Overview.............................................................................................................. 10.5.2 Register Configuration ......................................................................................... 10.5.3 Pin Functions........................................................................................................ 10.6 Port 5 ................................................................................................................................. 10.6.1 Overview.............................................................................................................. 10.6.2 Register Configuration ......................................................................................... 10.6.3 Pin Functions........................................................................................................ 10.7 Port 7 ................................................................................................................................. 10.7.1 Overview.............................................................................................................. 10.7.2 Register Configuration ......................................................................................... 10.7.3 Pin Functions........................................................................................................ 10.8 Port 8 ................................................................................................................................. 10.8.1 Overview.............................................................................................................. 10.8.2 Register Configuration ......................................................................................... 10.8.3 Pin Functions........................................................................................................ 10.9 Port 9 ................................................................................................................................. 10.9.1 Overview.............................................................................................................. 10.9.2 Register Configuration ......................................................................................... 10.9.3 Pin Functions........................................................................................................ 10.10 Port A ................................................................................................................................ 10.10.1 Overview.............................................................................................................. 10.10.2 Register Configuration ......................................................................................... 10.10.3 Pin Functions........................................................................................................ 10.10.4 MOS Input Pull-Up Function............................................................................... 10.11 Port B ................................................................................................................................ 10.11.1 Overview.............................................................................................................. 10.11.2 Register Configuration ......................................................................................... 10.11.3 Pin Functions........................................................................................................ 10.11.4 MOS Input Pull-Up Function............................................................................... 10.12 Port C ................................................................................................................................ 10.12.1 Overview.............................................................................................................. 10.12.2 Register Configuration ......................................................................................... Rev. 3.00 Jan 11, 2005 page xlii of liv 356 356 356 359 367 367 367 370 373 373 374 374 375 375 375 378 379 379 380 382 385 385 385 388 390 390 391 391 392 392 393 396 397 398 398 399 402 403 404 404 405 10.13 10.14 10.15 10.16 10.12.3 Pin Functions for Each Mode .............................................................................. 10.12.4 MOS Input Pull-Up Function............................................................................... Port D................................................................................................................................ 10.13.1 Overview.............................................................................................................. 10.13.2 Register Configuration......................................................................................... 10.13.3 Pin Functions ....................................................................................................... 10.13.4 MOS Input Pull-Up Function............................................................................... Port E ................................................................................................................................ 10.14.1 Overview.............................................................................................................. 10.14.2 Register Configuration......................................................................................... 10.14.3 Pin Functions ....................................................................................................... 10.14.4 MOS Input Pull-Up Function............................................................................... Port F ................................................................................................................................ 10.15.1 Overview.............................................................................................................. 10.15.2 Register Configuration......................................................................................... 10.15.3 Pin Functions ....................................................................................................... Port G................................................................................................................................ 10.16.1 Overview.............................................................................................................. 10.16.2 Register Configuration......................................................................................... 10.16.3 Pin Functions ....................................................................................................... 408 410 411 411 412 414 415 417 417 418 420 422 423 423 424 426 428 428 429 431 Section 11 16-Bit Timer Pulse Unit (TPU).................................................................. 433 11.1 Overview........................................................................................................................... 11.1.1 Features................................................................................................................ 11.1.2 Block Diagram..................................................................................................... 11.1.3 Pin Configuration................................................................................................. 11.1.4 Register Configuration......................................................................................... 11.2 Register Descriptions........................................................................................................ 11.2.1 Timer Control Register (TCR)............................................................................. 11.2.2 Timer Mode Register (TMDR)............................................................................ 11.2.3 Timer I/O Control Register (TIOR)..................................................................... 11.2.4 Timer Interrupt Enable Register (TIER).............................................................. 11.2.5 Timer Status Register (TSR)................................................................................ 11.2.6 Timer Counter (TCNT)........................................................................................ 11.2.7 Timer General Register (TGR) ............................................................................ 11.2.8 Timer Start Register (TSTR) ............................................................................... 11.2.9 Timer Synchro Register (TSYR) ......................................................................... 11.2.10 Module Stop Control Register A (MSTPCRA) ................................................... 11.3 Interface to Bus Master..................................................................................................... 11.3.1 16-Bit Registers ................................................................................................... 11.3.2 8-Bit Registers ..................................................................................................... 433 433 437 438 440 442 442 447 449 462 465 469 470 471 472 473 474 474 474 Rev. 3.00 Jan 11, 2005 page xliii of liv 11.4 Operation........................................................................................................................... 11.4.1 Overview.............................................................................................................. 11.4.2 Basic Functions .................................................................................................... 11.4.3 Synchronous Operation........................................................................................ 11.4.4 Buffer Operation .................................................................................................. 11.4.5 Cascaded Operation ............................................................................................. 11.4.6 PWM Modes ........................................................................................................ 11.4.7 Phase Counting Mode .......................................................................................... 11.5 Interrupts ........................................................................................................................... 11.5.1 Interrupt Sources and Priorities............................................................................ 11.5.2 DTC/DMAC Activation....................................................................................... 11.5.3 A/D Converter Activation .................................................................................... 11.6 Operation Timing .............................................................................................................. 11.6.1 Input/Output Timing ............................................................................................ 11.6.2 Interrupt Signal Timing........................................................................................ 11.7 Usage Notes ...................................................................................................................... 476 476 478 484 487 491 493 499 506 506 508 508 509 509 514 519 Section 12 Programmable Pulse Generator (PPG) ..................................................... 529 12.1 Overview........................................................................................................................... 12.1.1 Features ................................................................................................................ 12.1.2 Block Diagram ..................................................................................................... 12.1.3 Pin Configuration................................................................................................. 12.1.4 Registers............................................................................................................... 12.2 Register Descriptions ........................................................................................................ 12.2.1 Next Data Enable Registers H and L (NDERH, NDERL) ................................... 12.2.2 Output Data Registers H and L (PODRH, PODRL) ............................................ 12.2.3 Next Data Registers H and L (NDRH, NDRL) .................................................... 12.2.4 Notes on NDR Access.......................................................................................... 12.2.5 PPG Output Control Register (PCR).................................................................... 12.2.6 PPG Output Mode Register (PMR)...................................................................... 12.2.7 Port 1 Data Direction Register (P1DDR) ............................................................. 12.2.8 Port 2 Data Direction Register (P1DDR) ............................................................. 12.2.9 Module Stop Control Register A (MSTPCRA).................................................... 12.3 Operation........................................................................................................................... 12.3.1 Overview.............................................................................................................. 12.3.2 Output Timing...................................................................................................... 12.3.3 Normal Pulse Output............................................................................................ 12.3.4 Non-Overlapping Pulse Output............................................................................ 12.3.5 Inverted Pulse Output........................................................................................... 12.3.6 Pulse Output Triggered by Input Capture ............................................................ 12.4 Usage Notes ...................................................................................................................... Rev. 3.00 Jan 11, 2005 page xliv of liv 529 529 530 531 532 533 533 534 535 535 537 539 542 542 543 544 544 545 546 548 551 552 553 Section 13 8-Bit Timers (TMR) ...................................................................................... 555 13.1 Overview........................................................................................................................... 13.1.1 Features................................................................................................................ 13.1.2 Block Diagram..................................................................................................... 13.1.3 Pin Configuration................................................................................................. 13.1.4 Register Configuration......................................................................................... 13.2 Register Descriptions........................................................................................................ 13.2.1 Timer Counters 0 to 3 (TCNT0 to TCNT3)......................................................... 13.2.2 Time Constant Registers A0 to A3 (TCORA0 to TCORA3)............................... 13.2.3 Time Constant Registers B0 to B3 (TCORB0 to TCORB3) ............................... 13.2.4 Timer Control Registers 0 to 3 (TCR0 to TCR3) ................................................ 13.2.5 Timer Control/Status Registers 0 to 3 (TCSR0 to TCSR3) ................................. 13.2.6 Module Stop Control Register A (MSTPCRA) ................................................... 13.3 Operation .......................................................................................................................... 13.3.1 TCNT Incrementation Timing ............................................................................. 13.3.2 Compare Match Timing....................................................................................... 13.3.3 Timing of External RESET on TCNT ................................................................. 13.3.4 Timing of Overflow Flag (OVF) Setting ............................................................. 13.3.5 Operation with Cascaded Connection.................................................................. 13.4 Interrupts........................................................................................................................... 13.4.1 Interrupt Sources and DTC Activation ................................................................ 13.4.2 A/D Converter Activation.................................................................................... 13.5 Sample Application........................................................................................................... 13.6 Usage Notes ...................................................................................................................... 13.6.1 Contention between TCNT Write and Clear........................................................ 13.6.2 Contention between TCNT Write and Increment ................................................ 13.6.3 Contention between TCOR Write and Compare Match ...................................... 13.6.4 Contention between Compare Matches A and B ................................................. 13.6.5 Switching of Internal Clocks and TCNT Operation ........................................... 13.6.6 Interrupts and Module Stop Mode ....................................................................... 555 555 556 557 558 559 559 559 560 560 563 566 567 567 568 570 570 571 572 572 573 573 574 574 575 576 577 577 579 Section 14 14-Bit PWM D/A ........................................................................................... 581 14.1 Overview........................................................................................................................... 14.1.1 Features................................................................................................................ 14.1.2 Block Diagram..................................................................................................... 14.1.3 Pin Configuration................................................................................................. 14.1.4 Register Configuration......................................................................................... 14.2 Register Descriptions........................................................................................................ 14.2.1 PWM D/A Counter (DACNT)............................................................................. 14.2.2 PWM D/A Data Registers A and B (DADRA and DADRB) .............................. 14.2.3 PWM D/A Control Register (DACR).................................................................. 581 581 582 583 583 584 584 585 586 Rev. 3.00 Jan 11, 2005 page xlv of liv 14.2.4 Module Stop Control Register B (MSTPCRB).................................................... 588 14.3 Bus Master Interface ......................................................................................................... 589 14.4 Operation........................................................................................................................... 592 Section 15 Watchdog Timer ............................................................................................. 597 15.1 Overview........................................................................................................................... 15.1.1 Features ................................................................................................................ 15.1.2 Block Diagram ..................................................................................................... 15.1.3 Pin Configuration................................................................................................. 15.1.4 Register Configuration ......................................................................................... 15.2 Register Descriptions ........................................................................................................ 15.2.1 Timer Counter (TCNT) ........................................................................................ 15.2.2 Timer Control/Status Register (TCSR) ................................................................ 15.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 15.2.4 Pin Function Control Register (PFCR) ................................................................ 15.2.5 Notes on Register Access..................................................................................... 15.3 Operation........................................................................................................................... 15.3.1 Watchdog Timer Operation.................................................................................. 15.3.2 Interval Timer Operation...................................................................................... 15.3.3 Timing of Setting Overflow Flag (OVF).............................................................. 15.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF).......................... 15.4 Interrupts ........................................................................................................................... 15.5 Usage Notes ...................................................................................................................... 15.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 15.5.2 Changing Value of PSS and CKS2 to CKS0........................................................ 15.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode ................ 15.5.4 System Reset by Signal ...................................................................... 15.5.5 Internal Reset in Watchdog Timer Mode ............................................................. 15.5.6 OVF Flag Clearing in Interval Timer Mode ........................................................ 597 597 598 600 600 601 601 601 606 607 608 610 610 613 613 614 615 615 615 616 616 616 616 617 Section 16 Serial Communication Interface (SCI, IrDA) ........................................ 619 16.1 Overview........................................................................................................................... 16.1.1 Features ................................................................................................................ 16.1.2 Block Diagram ..................................................................................................... 16.1.3 Pin Configuration................................................................................................. 16.1.4 Register Configuration ......................................................................................... 16.2 Register Descriptions ........................................................................................................ 16.2.1 Receive Shift Register (RSR)............................................................................... 16.2.2 Receive Data Register (RDR) .............................................................................. 16.2.3 Transmit Shift Register (TSR) ............................................................................. 16.2.4 Transmit Data Register (TDR)............................................................................. Rev. 3.00 Jan 11, 2005 page xlvi of liv FVOTDW 619 619 621 622 623 625 625 625 626 626 16.2.5 Serial Mode Register (SMR) ............................................................................... 16.2.6 Serial Control Register (SCR) ............................................................................. 16.2.7 Serial Status Register (SSR) ................................................................................ 16.2.8 Bit Rate Register (BRR) ...................................................................................... 16.2.9 Smart Card Mode Register (SCMR).................................................................... 16.2.10 IrDA Control Register (IrCR).............................................................................. 16.2.11 Module Stop Control Registers B and C (MSTPCRB, MSTPCRC) ................... 16.3 Operation .......................................................................................................................... 16.3.1 Overview.............................................................................................................. 16.3.2 Operation in Asynchronous Mode ....................................................................... 16.3.3 Multiprocessor Communication Function ........................................................... 16.3.4 Operation in Clocked Synchronous Mode ........................................................... 16.3.5 IrDA Operation.................................................................................................... 16.4 SCI Interrupts.................................................................................................................... 16.5 Usage Notes ...................................................................................................................... 627 630 634 638 647 648 650 652 652 654 665 673 682 685 687 Section 17 Smart Card Interface ..................................................................................... 697 17.1 Overview........................................................................................................................... 17.1.1 Features................................................................................................................ 17.1.2 Block Diagram..................................................................................................... 17.1.3 Pin Configuration................................................................................................. 17.1.4 Register Configuration......................................................................................... 17.2 Register Descriptions........................................................................................................ 17.2.1 Smart Card Mode Register (SCMR).................................................................... 17.2.2 Serial Status Register (SSR) ................................................................................ 17.2.3 Serial Mode Register (SMR) ............................................................................... 17.2.4 Serial Control Register (SCR) ............................................................................. 17.3 Operation .......................................................................................................................... 17.3.1 Overview.............................................................................................................. 17.3.2 Pin Connections ................................................................................................... 17.3.3 Data Format ......................................................................................................... 17.3.4 Register Settings .................................................................................................. 17.3.5 Clock.................................................................................................................... 17.3.6 Data Transfer Operations..................................................................................... 17.3.7 Operation in GSM Mode ..................................................................................... 17.3.8 Operation in Block Transfer Mode ...................................................................... 17.4 Usage Notes ...................................................................................................................... 697 697 698 699 700 702 702 704 706 708 709 709 709 711 713 715 717 724 725 727 Section 18 I2C Bus Interface [Option] .......................................................................... 731 18.1 Overview........................................................................................................................... 731 18.1.1 Features................................................................................................................ 731 Rev. 3.00 Jan 11, 2005 page xlvii of liv 18.1.2 Block Diagram ..................................................................................................... 18.1.3 Input/Output Pins ................................................................................................. 18.1.4 Register Configuration ......................................................................................... 18.2 Register Descriptions ........................................................................................................ 18.2.1 I2C Bus Data Register (ICDR) ............................................................................. 18.2.2 Slave Address Register (SAR) ............................................................................. 18.2.3 Second Slave Address Register (SARX).............................................................. 18.2.4 I2C Bus Mode Register (ICMR)........................................................................... 18.2.5 I2C Bus Control Register (ICCR)......................................................................... 18.2.6 I2C Bus Status Register (ICSR)............................................................................ 18.2.7 Serial Control Register X (SCRX) ....................................................................... 18.2.8 DDC Switch Register (DDCSWR) ...................................................................... 18.2.9 Module Stop Control Register B (MSTPCRB).................................................... 18.3 Operation........................................................................................................................... 18.3.1 I2C Bus Data Format ............................................................................................ 18.3.2 Master Transmit Operation .................................................................................. 18.3.3 Master Receive Operation.................................................................................... 18.3.4 Slave Receive Operation ...................................................................................... 18.3.5 Slave Transmit Operation .................................................................................... 18.3.6 IRIC Setting Timing and SCL Control................................................................. 18.3.7 Operation Using the DTC .................................................................................... 18.3.8 Noise Canceler ..................................................................................................... 18.3.9 Sample Flowcharts ............................................................................................... 18.3.10 Initialization of Internal State............................................................................... 18.4 Usage Notes ...................................................................................................................... 732 734 734 736 736 739 740 741 744 752 757 758 760 761 761 762 765 767 769 772 773 774 774 778 780 Section 19 A/D Converter ................................................................................................. 793 19.1 Overview........................................................................................................................... 19.1.1 Features ................................................................................................................ 19.1.2 Block Diagram ..................................................................................................... 19.1.3 Pin Configuration................................................................................................. 19.1.4 Register Configuration ......................................................................................... 19.2 Register Descriptions ........................................................................................................ 19.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 19.2.2 A/D Control/Status Register (ADCSR)................................................................ 19.2.3 A/D Control Register (ADCR)............................................................................. 19.2.4 Module Stop Control Register A (MSTPCRA).................................................... 19.3 Interface to Bus Master ..................................................................................................... 19.4 Operation........................................................................................................................... 19.4.1 Single Mode (SCAN = 0)..................................................................................... 19.4.2 Scan Mode (SCAN = 1) ....................................................................................... Rev. 3.00 Jan 11, 2005 page xlviii of liv 793 793 794 795 796 797 797 798 801 802 803 804 804 806 19.4.3 Input Sampling and A/D Conversion Time ......................................................... 19.4.4 External Trigger Input Timing............................................................................. 19.5 Interrupts........................................................................................................................... 19.6 Usage Notes ...................................................................................................................... 808 810 810 811 Section 20 D/A Converter ................................................................................................. 817 20.1 Overview........................................................................................................................... 20.1.1 Features................................................................................................................ 20.1.2 Block Diagram..................................................................................................... 20.1.3 Input and Output Pins .......................................................................................... 20.1.4 Register Configuration......................................................................................... 20.2 Register Descriptions........................................................................................................ 20.2.1 D/A Data Registers 0 to 3 (DADR0 to DADR3)................................................. 20.2.2 D/A Control Registers 01 and 23 (DACR01 and DACR23) ............................... 20.2.3 Module Stop Control Registers A and C (MSTPCRA and MSTPCRC) ............. 20.3 Operation .......................................................................................................................... 817 817 817 819 819 820 820 820 822 823 Section 21 RAM .................................................................................................................. 825 21.1 Overview........................................................................................................................... 21.1.1 Block Diagram..................................................................................................... 21.1.2 Register Configuration......................................................................................... 21.2 Register Descriptions........................................................................................................ 21.2.1 System Control Register (SYSCR) ...................................................................... 21.3 Operation .......................................................................................................................... 21.4 Usage Notes ...................................................................................................................... 825 825 826 826 826 827 827 Section 22 ROM .................................................................................................................. 829 22.1 Overview........................................................................................................................... 22.1.1 Block Diagram..................................................................................................... 22.1.2 Register Configuration......................................................................................... 22.2 Register Descriptions........................................................................................................ 22.2.1 Mode Control Register (MDCR) ......................................................................... 22.3 Operation .......................................................................................................................... 22.4 Flash Memory Overview .................................................................................................. 22.4.1 Features................................................................................................................ 22.4.2 Overview.............................................................................................................. 22.4.3 Flash Memory Operating Modes ......................................................................... 22.4.4 On-Board Programming Modes........................................................................... 22.4.5 Flash Memory Emulation in RAM ...................................................................... 22.4.6 Differences between Boot Mode and User Program Mode ................................. 22.4.7 Block Configuration ............................................................................................ 829 829 829 830 830 830 833 833 834 835 836 838 839 840 Rev. 3.00 Jan 11, 2005 page xlix of liv 22.5 22.6 22.7 22.8 22.9 22.10 22.11 22.12 22.13 22.14 22.4.8 Pin Configuration................................................................................................. 22.4.9 Register Configuration ......................................................................................... Register Descriptions ........................................................................................................ 22.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 22.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 22.5.3 Erase Block Register 1 (EBR1)............................................................................ 22.5.4 Erase Block Register 2 (EBR2)............................................................................ 22.5.5 RAM Emulation Register (RAMER) ................................................................... 22.5.6 Flash Memory Power Control Register (FLPWCR) ............................................ 22.5.7 Serial Control Register X (SCRX) ....................................................................... On-Board Programming Modes ........................................................................................ 22.6.1 Boot Mode ........................................................................................................... 22.6.2 User Program Mode ............................................................................................. Programming/Erasing Flash Memory ............................................................................... 22.7.1 Program Mode...................................................................................................... 22.7.2 Program-Verify Mode.......................................................................................... 22.7.3 Erase Mode .......................................................................................................... 22.7.4 Erase-Verify Mode............................................................................................... Protection .......................................................................................................................... 22.8.1 Hardware Protection............................................................................................. 22.8.2 Software Protection.............................................................................................. 22.8.3 Error Protection.................................................................................................... Flash Memory Emulation in RAM.................................................................................... Interrupt Handling when Programming/Erasing Flash Memory ....................................... Flash Memory Programmer Mode .................................................................................... 22.11.1 Socket Adapter and Memory Map ....................................................................... 22.11.2 Programmer Mode Operation............................................................................... 22.11.3 Memory Read Mode ............................................................................................ 22.11.4 Auto-Program Mode ............................................................................................ 22.11.5 Auto-Erase Mode ................................................................................................. 22.11.6 Status Read Mode ................................................................................................ 22.11.7 Status Polling ....................................................................................................... 22.11.8 Programmer Mode Transition Time..................................................................... 22.11.9 Notes on Memory Programming.......................................................................... Flash Memory and Power-Down States ............................................................................ 22.12.1 Note on Power-Down States ................................................................................ Flash Memory Programming and Erasing Precautions ..................................................... Note on Switching from F-ZTAT Version to Masked ROM Version............................... 841 842 842 842 846 847 847 848 850 850 851 852 856 858 859 860 864 864 866 866 867 868 870 872 872 873 874 875 878 880 882 883 883 884 885 885 886 891 Section 23 Clock Pulse Generator .................................................................................. 893 23.1 Overview........................................................................................................................... 893 Rev. 3.00 Jan 11, 2005 page l of liv 23.2 23.3 23.4 23.5 23.6 23.7 23.8 23.9 23.1.1 Block Diagram..................................................................................................... 23.1.2 Register Configuration......................................................................................... Register Descriptions........................................................................................................ 23.2.1 System Clock Control Register (SCKCR) ........................................................... 23.2.2 Low-Power Control Register (LPWRCR) ........................................................... Oscillator........................................................................................................................... 23.3.1 Connecting a Crystal Resonator........................................................................... 23.3.2 External Clock Input............................................................................................ PLL Circuit ....................................................................................................................... Medium-Speed Clock Divider .......................................................................................... Bus Master Clock Selection Circuit.................................................................................. Subclock Oscillator........................................................................................................... Subclock Waveform Shaping Circuit................................................................................ Note on Crystal Resonator ................................................................................................ 893 894 894 894 895 896 896 899 901 902 902 902 903 904 Section 24 Power-Down Modes...................................................................................... 905 24.1 Overview........................................................................................................................... 24.1.1 Register Configuration......................................................................................... 24.2 Register Descriptions........................................................................................................ 24.2.1 Standby Control Register (SBYCR) .................................................................... 24.2.2 System Clock Control Register (SCKCR) ........................................................... 24.2.3 Low-Power Control Register (LPWRCR) ........................................................... 24.2.4 Timer Control/Status Register (TCSR)................................................................ 24.2.5 Module Stop Control Register (MSTPCR).......................................................... 24.3 Medium-Speed Mode ....................................................................................................... 24.4 Sleep Mode ....................................................................................................................... 24.4.1 Sleep Mode .......................................................................................................... 24.4.2 Exiting Sleep Mode ............................................................................................. 24.5 Module Stop Mode ........................................................................................................... 24.5.1 Module Stop Mode .............................................................................................. 24.5.2 Usage Notes ......................................................................................................... 24.6 Software Standby Mode.................................................................................................... 24.6.1 Software Standby Mode....................................................................................... 24.6.2 Exiting Software Standby Mode.......................................................................... 24.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode... 24.6.4 Software Standby Mode Application Example.................................................... 24.6.5 Usage Notes ......................................................................................................... 24.7 Hardware Standby Mode .................................................................................................. 24.7.1 Hardware Standby Mode ..................................................................................... 24.7.2 Hardware Standby Mode Timing......................................................................... 24.8 Watch Mode...................................................................................................................... 905 909 910 910 912 913 916 917 918 919 919 919 920 920 922 922 922 922 923 924 926 926 926 927 927 Rev. 3.00 Jan 11, 2005 page li of liv 24.9 24.10 24.11 24.12 24.8.1 Watch Mode......................................................................................................... 24.8.2 Exiting Watch Mode ............................................................................................ 24.8.3 Notes .................................................................................................................... Sub-Sleep Mode ................................................................................................................ 24.9.1 Sub-Sleep Mode................................................................................................... 24.9.2 Exiting Sub-Sleep Mode ...................................................................................... Sub-Active Mode .............................................................................................................. 24.10.1 Sub-Active Mode ................................................................................................. 24.10.2 Exiting Sub-Active Mode .................................................................................... Direct Transitions.............................................................................................................. 24.11.1 Overview of Direct Transitions............................................................................ φ Clock Output Disabling Function................................................................................... 927 928 928 929 929 929 930 930 930 931 931 931 Section 25 Electrical Characteristics .............................................................................. 933 25.1 Absolute Maximum Ratings.............................................................................................. 25.2 DC Characteristics ............................................................................................................ 25.3 AC Characteristics ............................................................................................................ 25.3.1 Clock Timing ....................................................................................................... 25.3.2 Control Signal Timing.......................................................................................... 25.3.3 Bus Timing........................................................................................................... 25.3.4 DMAC Timing ..................................................................................................... 25.3.5 Timing of On-Chip Supporting Modules ............................................................. 25.4 A/D Conversion Characteristics........................................................................................ 25.5 D/A Conversion Characteristics........................................................................................ 25.6 Flash Memory Characteristics........................................................................................... 25.7 Usage Note........................................................................................................................ 933 934 942 943 945 947 957 961 969 970 971 972 Appendix A Instruction Set .............................................................................................. 973 A.1 A.2 A.3 A.4 A.5 A.6 Instruction List .................................................................................................................. 973 Instruction Codes .............................................................................................................. 997 Operation Code Map ........................................................................................................1012 Number of States Required for Instruction Execution .....................................................1016 Bus States during Instruction Execution ..........................................................................1030 Condition Code Modification...........................................................................................1044 Appendix B Internal I/O Register ..................................................................................1050 B.1 B.2 Addresses .........................................................................................................................1050 Functions..........................................................................................................................1061 Appendix C I/O Port Block Diagrams ..........................................................................1163 C.1 Port 1 Block Diagrams .....................................................................................................1163 Rev. 3.00 Jan 11, 2005 page lii of liv C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.11 C.12 C.13 C.14 C.15 Port 2 Block Diagram ...................................................................................................... 1169 Port 3 Block Diagrams..................................................................................................... 1170 Port 4 Block Diagrams..................................................................................................... 1178 Port 5 Block Diagrams..................................................................................................... 1179 Port 7 Block Diagrams..................................................................................................... 1182 Port 8 Block Diagrams..................................................................................................... 1189 Port 9 Block Diagrams..................................................................................................... 1193 Port A Block Diagrams.................................................................................................... 1194 Port B Block Diagram...................................................................................................... 1195 Port C Block Diagrams .................................................................................................... 1196 Port D Block Diagram ..................................................................................................... 1198 Port E Block Diagram...................................................................................................... 1199 Port F Block Diagrams..................................................................................................... 1200 Port G Block Diagrams.................................................................................................... 1208 Appendix D Pin States ...................................................................................................... 1212 D.1 Port States in Each Mode................................................................................................. 1212 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode............................................................... 1216 Appendix F Product Code Lineup ................................................................................. 1217 Appendix G Package Dimensions ................................................................................. 1218 Rev. 3.00 Jan 11, 2005 page liii of liv Rev. 3.00 Jan 11, 2005 page liv of liv Section 1 Overview Section 1 Overview 1.1 Overview The H8S/2643 Group is a group of microcomputers (MCUs: microcomputer units), built around the H8S/2600 CPU, employing Renesas' proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. On-chip peripheral functions required for system configuration include DMA controller (DMAC), data transfer controller (DTC) bus masters, ROM and RAM memory, a 16-bit timer-pulse unit (TPU), programmable pulse generator (PPG), 8-bit timer, 14-bit PWM timer (PWM) watchdog timer (WDT), serial communication interface (SCI, IrDA), A/D converter, D/A converter, and I/O ports. It is also possible to incorporate an on-chip PC bus interface (IIC) as an option. On-chip ROM is available as 256-kbyte flash memory (F-ZTAT™ version)* or as 256-, 128-, or 64-kbyte mask ROM. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching has been speeded up, and processing speed increased. Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or external expansion mode. The features of the H8S/2643 Group are shown in table 1.1. Note: * F-ZTAT is a trademark of Renesas Technology, Corp. Rev. 3.00 Jan 11, 2005 page 1 of 1220 REJ09B0186-0300O Section 1 Overview Table 1.1 Item CPU Overview Specification • General-register machine  Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control  Maximum clock rate: 25 MHz  High-speed arithmetic operations 8/16/32-bit register-register add/subtract 16 × 16-bit register-register multiply 16 × 16 + 42-bit multiply and accumulate 32 ÷ 16-bit register-register divide •  Sixty-nine basic instructions  8/16/32-bit move/arithmetic and logic instructions  Unsigned/signed multiply and divide instructions  Multiply-and accumulate instruction  Powerful bit-manipulation instructions • Two CPU operating modes  Normal mode: 64-kbyte address space (cannot be used in the H8S/2643 Group)  Advanced mode: 16-Mbyte address space : 40 ns : 160 ns : 160 ns : 800 ns Instruction set suitable for high-speed operation Bus controller • • • • • • • Address space divided into 8 areas, with bus specifications settable independently for each area Choice of 8-bit or 16-bit access space for each area 2-state or 3-state access space can be designated for each area Number of program wait states can be set for each area Burst ROM directly connectable Possible to connect a maximum of 8 MB of DRAM (alternatively, it is also possible to use an interval timer) External bus release function Supports debugging functions by means of PC break interrupts Two break channels PC break controller • • Rev. 3.00 Jan 11, 2005 page 2 of 1220 REJ09B0186-0300O Section 1 Overview Item DMA controller (DMAC) Specification • • • • Data transfer controller (DTC) • • • • 16-bit timer-pulse unit (TPU) • • • Programmable pulse generator (PPG) • • • • 8-bit timer 4 channels • • • Watchdog timer (WDT) 2 channels 14-bit PWM timer (PWM) • • • • • Serial communication interface (SCI) 5 channels (SCI0 to SCI4) • • • Short address mode and full address mode selectable Short address mode: 4 channels Full address mode: 2 channels Transfer possible in repeat mode/block transfer mode Transfer possible in single address mode Activation by internal interrupt possible Can be activated by internal interrupt or software Multiple transfers or multiple types of transfer possible for one activation source Transfer possible in repeat mode, block transfer mode, etc. Request can be sent to CPU for interrupt that activated DTC 6-channel 16-bit timer on-chip Pulse I/O processing capability for up to 16 pins' Automatic 2-phase encoder count capability Maximum 16-bit pulse output possible with TPU as time base Output trigger selectable in 4-bit groups Non-overlap margin can be set Direct output or inverse output setting possible 8-bit up counter (external event count possible) Time constant register × 2 2 channel connection possible W atchdog timer or interval timer selectable Operation using sub-clock supported (WDT1 only) Maximum of 4 outputs Resolution: 1/16384 Maximum carrier frequency: 390.6 kHz (operating at 25 MHz) Asynchronous mode or synchronous mode selectable Multiprocessor communication function Smart card interface function Rev. 3.00 Jan 11, 2005 page 3 of 1220 REJ09B0186-0300O Section 1 Overview Item IrDA-equipped SCI 1 channel (SCI0) Specification • • • • • A/D converter • • • • • • D/A converter I/O ports Memory • • • • • Supports IrDA standard version 1.0 TxD and RxD encoding/decoding in IrDA format Start/stop synchronization mode or clock synchronization mode selectable Multiprocessor communications function Smart card interface function Resolution: 10 bits Input: 16 channels High-speed conversion: 10.72 µs minimum conversion time (at 25 MHz operation) Single or scan mode selectable Sample and hold circuit A/D conversion can be activated by external trigger or timer trigger Resolution: 8 bits Output: 4 channels 95 I/O pins, 16 input-only pins Flash memory or masked ROM High-speed static RAM ROM 256 kbytes 192 kbytes 128 kbytes 7QRI Product Name H8S/2643 H8S/2642 H8S/2641 Interrupt controller • • • Power-down state • • • • • • RAM 16 kbytes 12 kbytes 8 kbytes to ) 0QRI Nine external interrupt pins (NMI, Eight priority levels settable Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode 72 internal interrupt sources (including options) Sub-clock operation (sub-active mode, sub-sleep mode, watch mode) Rev. 3.00 Jan 11, 2005 page 4 of 1220 REJ09B0186-0300O Section 1 Overview Item Operating modes Specification Four MCU operating modes CPU Operating Mode Mode Description 4 5 6 7 Clock pulse generator Package I C bus interface (IIC) 2 channels (optional) 2 External Data Bus On-Chip ROM Disabled Disabled Enabled Enabled Initial Value 16 bits 8 bits 8 bits — Maximu m Value 16 bits 16 bits 16 bits — Advanced On-chip ROM disabled expansion mode On-chip ROM disabled expansion mode On-chip ROM enabled expansion mode Single-chip mode • • • • • • • • On-chip PLL circuit (×1, ×2, ×4) Input clock frequency: 2 to 25 MHz 144-pin plastic QFP (FP-144J) 144-pin plastic TQFP (TFP-144) 2 Conforms to I C bus interface type advocated by Philips Single master mode/slave mode Possible to determine arbitration lost conditions Supports two slave addresses Model Name ROM/RAM (Bytes) 256 k/16 k 192 k/12 k 128 k/8 k Packages FP-144J TFP-144 FP-144J TFP-144 FP-144J TFP-144 Product lineup Masked ROM Version F-ZTAT Version HD6432643 HD6432642 HD6432641 HD64F2643 — — Rev. 3.00 Jan 11, 2005 page 5 of 1220 REJ09B0186-0300O Section 1 Overview 1.2 Internal Block Diagram Figure 1.1 shows an internal block diagram. MD2 MD1 MD0 OSC2 OSC1 EXTAL XTAL PLLVCC PLLCAP PLLVSS STBY RES WDTOVF NMI TEST1 FWE*2 PF7/ ø PF6/ AS/ LCAS PF5/ RD PF4/ HWR PF3/ LWR/ADTRG/IRQ3 PF2/ LCAS / WAIT / BREQO PF1/ BACK/BUZZ PF0/ BREQ/IRQ2 PG4/ CS0 PG3/ CS1 PG2/ CS2 PG1/ CS3/OE/IRQ7 PG0/ CAS /IRQ6 P86 P85/ DACK1 P84/ DACK0 P83/ TEND1 P82/ TEND0 P81/ DREQ1 P80/ DREQ0 P77/TxD3 P76/RxD3 P75/TMO3/SCK3 P74/TMO2/MRES P73/TMO1/CS7 P72/TMO0/CS6 P71/TMRI23/TMCI23/CS5 P70/TMRI01/TMCI01/CS4 PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 PVCC PVCC PVCC PVCC VCC VCC VSS VSS VSS VSS VSS VSS VSS Port D P L L Port E Port 5 P52/SCK2 P51/RxD2 P50/TxD2 PA7/A23 PA6/A22 PA5/A21 PA4/A20 PA3/A19 PA2/A18 PA1/A17 PA0/A16 PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3 / A11 PB2/A10 PB1/A9 PB0/A8 PC7/A7/PWM1 PC6/A6/PWM0 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 P37/TxD4 P36/RxD4 P35/SCK1/SCK4/SCL0/IRQ5 P34/RxD1/SDA0 P33/TxD1/SCL1 P32/SCK0/SDA1/IRQ4 P31/RxD0/IrRxD P30/TxD0/IrTxD P97/AN15/DA3 P96/AN14/DA2 P95/AN13 P94/AN12 P93/AN11 P92/AN10 P91/AN9 P90/AN8 H8S/2600 CPU Internal data bus Internal address bus Clock pulse generator Bus controller Port F DTC PC break controller Port G DMAC ROM (Masked ROM, flash memory*1) WDT × 2 channels Peripheral data bus Peripheral address bus Interrupt controller Port 8 RAM 8 bit timer × 4 channels SCI × 5 channels (IrDA × 1 channel) I2C bus interface [option] TPU Port 7 14-bit PWM timer D/A converter PPG A/D converter Port 1 P17 / PO8/ TIOCA0 P16 / PO9/ TIOCB0 P15 / PO10/ TIOCC0 / TCLKA P14 / PO11/ TIOCD0 / TCLKB P13 / PO12/ TIOCA1/IRQ0 P12 / PO13/ TIOCB1 / TCLKC P11 / PO14/ TIOCA2/PWM2/IRQ1 P10 / PO15/ TIOCB2 /PWM3/ TCLKD Port 2 Vref AVCC AVSS Port 4 P47 / AN7/ DA1 P46 / AN6/ DA0 P45 / AN5 P44 / AN4 P43 / AN3 P42 / AN2 P41 / AN1 P40 / AN0 Notes: 1. 2. Applies to the H8S/2643 only. The FWE pin is used only in the flash memory version. Figure 1.1 Internal Block Diagram Rev. 3.00 Jan 11, 2005 page 6 of 1220 REJ09B0186-0300O P27 / PO0/ TIOCA3 P26 / PO1/ TIOCB3 P25 / PO2/ TIOCC3 P24 / PO3/ TIOCD3 P23 / PO4/ TIOCA4 P22 / PO5/ TIOCB4 P21 / PO6/ TIOCA5 P20 / PO7/ TIOCB5 Port 9 Port 3 Port C Port B Port A Section 1 Overview 1.3 1.3.1 Pin Description Pin Arrangement Figure 1.2 shows the pin arrangement of the H8S/2643 Group. PF0/BREQ/IRQ2 PF1/BACK/BUZZ PF2/LCAS/WAIT/BREQO PF3/LWR/ADTRG/IRQ3 PF4/HWR PF5/RD PF6/AS/LCAS P86 P85/DACK1 P84/DACK0 VSS PF7/ø PVCC OSC2 OSC1 VSS EXTAL VCC XTAL FWE* STBY NMI RES PLLVSS PLLCAP PLLVCC WDTOVF P83/TEND1 P82/TEND0 P81/DREQ1 PG4/CS0 PG3/CS1 PG2/CS2 PG1/CS3/OE/IRQ7 PG0/CAS/IRQ6 P37/TxD4 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 Top view (FP-144J) (TFP-144) Figure 1.2 Pin Arrangement (FP-144J, TFP-144: Top View) A0/PC0 A1/PC1 A2/PC2 A3/PC3 VSS A4/PC4 VCC A5/PC5 PWM0/A6/PC6 PWM1/A7/PC7 TIOCA3/PO0/P20 TIOCB3/PO1/P21 TIOCC3/PO2/P22 VSS A8/PB0 PVCC A9/PB1 A10/PB2 A11/PB3 A12/PB4 A13/PB5 A14/PB6 A15/PB7 TIOCD3/PO3/P23 TIOCA4/PO4/P24 TIOCB4/PO5/P25 A16/PA0 A17/PA1 A18/PA2 A19/PA3 VSS TIOCA0/PO8/P10 TIOCB0/PO9/P11 TCLKA/TIOCC0/PO10/P12 TCLKB/TIOCD0/PO11/P13 IRQ0/TIOCA1/PO12/P14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 AVCC VREF AN0/P40 AN1/P41 AN2/P42 AN3/P43 AN4/P44 AN5/P45 DA0/AN6/P46 DA1/AN7/P47 AN8/P90 AN9/P91 AN10/P92 AN11/P93 AN12/P94 AN13/P95 DA2/AN14/P96 DA3/AN15/P97 AVSS TEST1 A20/PA4 A21/PA5 A22/PA6 A23/PA7 CS4/TMCI01/TMRI01/P70 CS5/TMCI23/TMRI23/P71 CS6/TMO0/P72 CS7/TMO1/P73 MRES/TMO2/P74 SCK3/TMO3/P75 RxD3/P76 TxD3/P77 MD0 MD1 MD2 NC 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 P36/RxD4 P35/SCK1/SCK4/SCL0/IRQ5 P34/RxD1/SDA0 P33/TxD1/SCL1 VSS P32/SCK0/SDA1/IRQ4 PVCC P31/RxD0/IrRxD P30/TxD0/IrTxD P80/DREQ0 P52/SCK2 P51/RxD2 PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PVCC PD0/D8 VSS PE7/D7 PE6/D6 PE5/D5 PE4/D4 P50/TxD2 P27/PO7/TIOCB5 P26/PO6/TIOCA5 PE3/D3 PE2/D2 PE1/D1 PE0/D0 P17/PO15/TIOCB2/TCLKD/PWM3 P16/PO14/TIOCA2/PWM2/IRQ1 P15/PO13/TIOCB1/TCLKC Note: * FWE is used only in the flash memory version. Rev. 3.00 Jan 11, 2005 page 7 of 1220 REJ09B0186-0300O Section 1 Overview 1.3.2 Pin Functions in Each Operating Mode Table 1.2 shows the pin functions of the H8S/2643 Group in each of the operating modes. Table 1.2 Pin Functions in Each Operating Mode Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 A0 A1 A2 A3 VSS A4 VCC A5 A6 A7 P20/PO0/TIOCA3 P21/PO1/TIOCB3 P22/PO2/TIOCC3 VSS PB0/A8 PVCC PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 P23/PO3/TIOCD3 P24/PO4/TIOCA4 P25/PO5/TIOCB4 PA0/A16 A0 A1 A2 A3 VSS A4 VCC A5 A6 A7 P20/PO0/TIOCA3 P21/PO1/TIOCB3 P22/PO2/TIOCC3 VSS PB0/A8 PVCC PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 P23/PO3/TIOCD3 P24/PO4/TIOCA4 P25/PO5/TIOCB4 PA0/A16 PC0/A0 PC1/A1 PC2/A2 PC3/A3 VSS PC4/A4 VCC PC5/A5 PC6/A6/PWM0 PC7/A7/PWM1 P20/PO0/TIOCA3 P21/PO1/TIOCB3 P22/PO2/TIOCC3 VSS PB0/A8 PVCC PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 P23/PO3/TIOCD3 P24/PO4/TIOCA4 P25/PO5/TIOCB4 PA0/A16 PC0 PC1 PC2 PC3 VSS PC4 VCC PC5 PC6/PWM0 PC7/PWM1 P20/PO0/TIOCA3 P21/PO1/TIOCB3 P22/PO2/TIOCC3 VSS PB0 PVCC PB1 PB2 PB3 PB4 PB5 PB6 PB7 P23/PO3/TIOCD3 P24/PO4/TIOCA4 P25/PO5/TIOCB4 PA0 Rev. 3.00 Jan 11, 2005 page 8 of 1220 REJ09B0186-0300O Section 1 Overview Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 PA1/A17 PA2/A18 PA3/A19 VSS P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/TIOCC0/ TCLKA P13/PO11/TIOCD0/ TCLKB P14/PO12/TIOCA1/ 0QRI PA1/A17 PA2/A18 PA3/A19 VSS P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/TIOCC0/ TCLKA P13/PO11/TIOCD0/ TCLKB P14/PO12/TIOCA1/ 0QRI PA1/A17 PA2/A18 PA3/A19 VSS P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/TIOCC0/ TCLKA P13/PO11/TIOCD0/ TCLKB P14/PO12/TIOCA1/ 0QRI PA1 PA2 PA3 VSS P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/TIOCC0/ TCLKA P13/PO11/TIOCD0/ TCLKB P14/PO12/TIOCA1/ 0QRI P15/PO13/TIOCB1/ TCLKC P16/PO14/TIOCA2/ PWM2/ P17/PO15/TIOCB2/ TCLKD/PWM3 PE0/D0 PE1/D1 PE2/D2 PE3/D3 P26/PO6/TIOCA5 P27/PO7/TIOCB5 P50/TxD2 PE4/D4 PE5/D5 PE6/D6 PE7/D7 VSS D8 PVCC D9 D10 1QRI P15/PO13/TIOCB1/ TCLKC P16/PO14/TIOCA2/ PWM2/ P17/PO15/TIOCB2/ TCLKD/PWM3 PE0/D0 PE1/D1 PE2/D2 PE3/D3 P26/PO6/TIOCA5 P27/PO7/TIOCB5 P50/TxD2 PE4/D4 PE5/D5 PE6/D6 PE7/D7 VSS D8 PVCC D9 D10 1QRI P15/PO13/TIOCB1/ TCLKC P16/PO14/TIOCA2/ PWM2/ P17/PO15/TIOCB2/ TCLKD/PWM3 PE0/D0 PE1/D1 PE2/D2 PE3/D3 P26/PO6/TIOCA5 P27/PO7/TIOCB5 P50/TxD2 PE4/D4 PE5/D5 PE6/D6 PE7/D7 VSS D8 PVCC D9 D10 1QRI P15/PO13/TIOCB1/ TCLKC P16/PO14/TIOCA2/ PWM2/ P17/PO15/TIOCB2/ TCLKD/PWM3 PE0 PE1 PE2 PE3 P26/PO6/TIOCA5 P27/PO7/TIOCB5 P50/TxD2 PE4 PE5 PE6 PE7 VSS PD0 PVCC PD1 PD2 1QRI Rev. 3.00 Jan 11, 2005 page 9 of 1220 REJ09B0186-0300O Section 1 Overview Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 D11 D12 D13 D14 D15 P51/RxD2 P52/SCK2 P30/TxD0/IrTxD P31/RxD0/IrRxD PVCC P32/SCK0/SDA1/ 4QRI 0QERD D11 D12 D13 D14 D15 P51/RxD2 P52/SCK2 P30/TxD0/IrTxD P31/RxD0/IrRxD PVCC P32/SCK0/SDA1/ VSS P33/TxD1/SCL1 P34/RxD1/SDA0 P35/SCK1/SCK4/ SCL0/ P36/RxD4 P37/TxD4 / PG1/ PG2/ PG3/ PG4/ P81/ P82/ P83/ 6QRI SAC 5QRI 4QRI 0QERD D11 D12 D13 D14 D15 P51/RxD2 P52/SCK2 P30/TxD0/IrTxD P31/RxD0/IrRxD PVCC P32/SCK0/SDA1/ 4QRI 0QERD PD3 PD4 PD5 PD6 PD7 P51/RxD2 P52/SCK2 P30/TxD0/IrTxD P31/RxD0/IrRxD PVCC P32/SCK0/SDA1/ 4QRI 0QERD 1QERD 0DNET 1DNET 5QRI 7QRI 6QRI P80/ P80/ P80/ P80/ VSS P33/TxD1/SCL1 P34/RxD1/SDA0 P35/SCK1/SCK4/ SCL0/ P36/RxD4 P37/TxD4 PG1/ PG2/ PG3/ PG4/ P81/ P82/ P83/ 6QRI SAC 5QRI VSS P33/TxD1/SCL1 P34/RxD1/SDA0 P35/SCK1/SCK4/ SCL0/ P36/RxD4 P37/TxD4 / PG1/ PG2/ PG3/ PG4/ P81/ P82/ P83/ 6QRI SAC 5QRI VSS P33/TxD1/SCL1 P34/RxD1/SDA0 P35/SCK1/SCK4/ SCL0/ P36/RxD4 P37/TxD4 PG0/ PG1/ PG2 PG3 PG4 P81/ P82/ P83/ / PG0/ / PG0/ / PG0/ / WDTOVF PLLVCC PLLCAP PLLVSS WDTOVF PLLVCC PLLCAP PLLVSS WDTOVF PLLVCC PLLCAP PLLVSS Rev. 3.00 Jan 11, 2005 page 10 of 1220 REJ09B0186-0300O 7QRI EO 3SC 2SC 1SC 0SC 1QERD 0DNET 1DNET 7QRI EO 3SC 2SC 1SC 0SC 1QERD 0DNET 1DNET 7QRI EO 3SC 2SC 1SC 0SC / / / 1QERD 0DNET 1DNET WDTOVF PLLVCC PLLCAP PLLVSS Section 1 Overview Pin Name Pin No. Mode 4 SER Mode 5 SER Mode 6 SER Mode 7 SER 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 FEW *2 XTAL VCC EXTAL VSS OSC1 OSC2 PVCC PF7/φ VSS P85/ P86 SACL SA 0KCAD FWE*2 XTAL VCC EXTAL VSS OSC1 OSC2 PVCC PF7/φ VSS P85/ P86 SACL SA 0KCAD FWE*2 XTAL VCC EXTAL VSS OSC1 OSC2 PVCC PF7/φ VSS P85/ P86 SACL SA 0KCAD FWE*2 XTAL VCC EXTAL VSS OSC1 OSC2 PVCC PF7/φ VSS P85/ P86 PF6 PF5 PF4 3QRI GRTDA 0KCAD P84/ P84/ P84/ P84/ / / / AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 Rev. 3.00 Jan 11, 2005 page 11 of 1220 REJ09B0186-0300O 2QRI 2QRI QERB 2QRI QERB 2QRI QERB PF0/ / PF0/ / PF0/ KCAB KCAB KCAB PF1/ /BUZZ PF1/ /BUZZ PF1/ TIAW SACL OQERB TIAW SACL OQERB TIAW SACL PF2/ / / PF2/ / / PF2/ GRTDA 3QRI GRTDA 3QRI 3QRI GRTDA RWL / / PF3/LWR/ / PF3/LWR/ / PF3/ PF2 / / /BUZZ / PF1/BUZZ PF0/ 1KCAD YBTS IMN 1KCAD YBTS RWH DR IMN 1KCAD YBTS RWH DR IMN 1KCAD OQERB YBTS RWH DR IMN / Section 1 Overview Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 P46/AN6/DA0 P47/AN7/DA1 P90/AN8 P91/AN9 P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14/DA2 P97/AN15/DA3 AVSS 1TSET P46/AN6/DA0 P47/AN7/DA1 P90/AN8 P91/AN9 P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14/DA2 P97/AN15/DA3 AVSS PA4/A20 PA5/A21 PA6/A22 PA7/A23 P70/TMRI01/ TMCI01/ P71/TMRI23/ TMCI23/ P73/TMO1/ P74/TMO2/ P76/RxD3 P77/TxD3 MD0 MD1 MD2 NC* 1 6SC 4SC 1TSET P46/AN6/DA0 P47/AN7/DA1 P90/AN8 P91/AN9 P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14/DA2 P97/AN15/DA3 AVSS PA4/A20 PA5/A21 PA6/A22 PA7/A23 P70/TMRI01/ TMCI01/ P71/TMRI23/ TMCI23/ P73/TMO1/ P74/TMO2/ P76/RxD3 P77/TxD3 MD0 MD1 MD2 NC* 1 6SC 4SC 1TSET P46/AN6/DA0 P47/AN7/DA1 P90/AN8 P91/AN9 P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14/DA2 P97/AN15/DA3 AVSS PA4 PA5 PA6 PA7 P70/TMRI01/TMCI01 P71/TMRI23/TMCI23 P72/TMO0 P73/TMO1 P75/TMO3/SCK3 P76/RxD3 P77/TxD3 MD0 MD1 MD2 NC*1 SERM 1TSET PA4/A20 PA5/A21 PA6/A22 PA7/A23 P70/TMRI01/ TMCI01/ P71/TMRI23/ TMCI23/ P73/TMO1/ P74/TMO2/ P76/RxD3 P77/TxD3 MD0 MD1 MD2 NC* 1 6SC 4SC 5SC P72/TMO0/ P72/TMO0/ P72/TMO0/ P75/TMO3/SCK3 P75/TMO3/SCK3 P75/TMO3/SCK3 Notes: 1. NC pins should be left open. 2. FWE is used only in the flash memory version. Leave open in the mask ROM. Rev. 3.00 Jan 11, 2005 page 12 of 1220 REJ09B0186-0300O SERM 7SC 5SC SERM 7SC 5SC SERM 7SC P74/TMO2/ Section 1 Overview 1.3.3 Pin Functions Table 1.3 outlines the pin functions of the H8S/2643 Group. Table 1.3 Type Power Pin Functions Symbol VCC I/O Input Name and Function Power supply: For connection to the power supply. All VCC pins should be connected to the system power supply. Port power supply: Connect all pins to the port power supply. Ground: For connection to ground (0 V). All VSS pins should be connected to the system power supply (0 V). PLL power supply: Power supply for on-chip PLL oscillator. PLL ground: Ground for on-chip PLL oscillator. PLL capacitance: External capacitance pin for on-chip PLL oscillator. Crystal: Connects to a crystal oscillator. See section 23, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. Crystal: Connects to a crystal oscillator. The EXTAL pin can also input an external clock. See section 23, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. Sub clock: Connects to a 32.768 kHz crystal oscillator. See section 23, Clock Pulse Generator, for examples of connections to a crystal oscillator. Sub clock: Connects to a 32.768 kHz crystal oscillator. See section 23, Clock Pulse Generator, for examples of connections to a crystal oscillator. System clock: Supplies the system clock to an external device. PVCC VSS Clock PLLVCC PLLVSS PLLCAP XTAL Input Input Input Input Input Input EXTAL Input OSC1 Input OSC2 Input φ Output Rev. 3.00 Jan 11, 2005 page 13 of 1220 REJ09B0186-0300O Section 1 Overview Type Operating mode control Symbol MD2 to MD0 I/O Input Name and Function Mode pins: These pins set the operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the H8S/2643 Group is operating. MD2 0 MD1 0 1 1 0 1 MD0 0 1 0 1 0 1 0 1 System control Input Input Input Input Output Operating Mode — — — — Mode 4 Mode 5 Mode 6 Mode 7 Reset input: When this pin is driven low, the chip is reset. Manual reset: When this pin is driven low, a transmission is made to manual reset mode. Standby: When this pin is driven low, a transition is made to hardware standby mode. Bus request: Used by an external bus master to issue a bus request to the H8S/2643 Group. Bus request output: The external bus request signal used when an internal bus master accesses external space in the external bus-released state. Bus request acknowledge: Indicates that the bus has been released to an external bus master. Flash write enable: Pin for flash memory use (in planning stage). Test pin: Used for testing. Input PVCC. Rev. 3.00 Jan 11, 2005 page 14 of 1220 REJ09B0186-0300O OQERB 1TSET SERM QERB KCAB YBTS SER Output Input Input FWE Section 1 Overview Type Interrupts Symbol NMI I/O Input Name and Function Nonmaskable interrupt: Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high. Interrupt request: These pins request a maskable interrupt. Address bus: These pins output an address. Data bus: These pins constitute a bidirectional data bus. Chip select: Selection signal for areas 0 to 7. Address strobe: When this pin is low, it indicates that address output on the address bus is enabled. Read: When this pin is low, it indicates that the external address space can be read. High write/write enable/upper write enable: A strobe signal that writes to external space and indicates that the upper half (D15 to D8) of the data bus is enabled. The 2CAS type DRAM write enable signal. The 2WE type DRAM upper write enable signal. Low write/lower column address strobe/lower write enable: A strobe signal that writes to external space and indicates that the lower half (D7 to D0) of the data bus is enabled. The 2CAS type (LCASS = 1) DRAM lower column address strobe signal. The 2WE type DRAM lower write enable signal. Upper column address strobe/column address strobe: The 2CAS type DRAM upper column address strobe signal. Lower column address strobe: The 2CAS type DRAM lower column address strobe signal. Output enable: Output enable signal for DRAM space read access. Wait: Requests insertion of a wait state in the bus cycle when accessing external 3-state address space. Address bus Data bus Bus control A23 to A0 D15 to D0 to 0QRI to Input Output I/O Output Output Output Output 0SC SACL TIAW RWH 7QRI RWL SAC 7SC EO DR SA Output Output Output Output Input Rev. 3.00 Jan 11, 2005 page 15 of 1220 REJ09B0186-0300O Section 1 Overview Type DMA controller (DMAC) Symbol , 1QERD 0QERD 1KCAD 0KCAD 1DNET 0DNET I/O Input Output Output Input I/O Name and Function DMA request: Requests DMAC activation. DMA transfer completed 1,0: Indicates DMAC data transfer end. DMA transfer acknowledge 1,0: DMAC single address transfer acknowledge pin. Clock input D to A: These pins input an external clock. Input capture/output compare match A0 to D0: The TGR0A to TGR0D input capture input or output compare output, or PWM output pins. Input capture/output compare match A1 and B1: The TGR1A and TGR1B input capture input or output compare output, or PWM output pins. Input capture/output compare match A2 and B2: The TGR2A and TGR2B input capture input or output compare output, or PWM output pins. Input capture/output compare match A3 to D3: The TGR3A to TGR3D input capture input or output compare output, or PWM output pins. Input capture/output compare match A4 and B4: The TGR4A and TGR4B input capture input or output compare output, or PWM output pins. Input capture/output compare match A5 and B5: The TGR5A and TGR5B input capture input or output compare output, or PWM output pins. Pulse output: Pulse output pins. , , 16-bit timerpulse unit (TPU) TCLKD to TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4 TIOCA5, TIOCB5 I/O I/O I/O I/O I/O Programmable pulse generator (PPG) 8-bit timer PO15 to PO0 Output TMO0 to TMO3 TMCI01, TMCI23 TMRI01, TMRI23 Output Input Input Compare match output: The compare match output pins. Counter external clock input: Input pins for the external clock input to the counter. Counter external reset input: The counter reset input pins. Rev. 3.00 Jan 11, 2005 page 16 of 1220 REJ09B0186-0300O Section 1 Overview Type Symbol I/O Output Output Output Output Name and Function PWMX timer output: PWM D/A pulse output pins. Watchdog timer overflows: The counter overflows signal output pin in watchdog timer mode. BUZZ output: Output pins for the pulse divided by the watchdog timer. Transmit data (channel 0 to 4): Data output pins. 14-bit PWM timer PWM0 to (PWMX) PWM3 FVOTDW Watchdog timer (WDT) BUZZ Serial communication interface (SCI)/ Smart Card interface TxD4, TxD3, TxD2, TxD1, TxD0 RxD4, RxD3, RxD2, RxD1, RxD0 SCK4, SCK3, SCK2, SCK1, SCK0 IrDA-equipped SCI 1 channel (SCI0) IrTxD IrRxD Input Receive data (channel 0 to 4): Data input pins. I/O Serial clock (channel 0 to 4): Clock I/O pins. Output/ Input I/O IrDA transmission data/receive data: Input/output pins for the data encoded for the IrDA. I2C clock input (channel 1, 0): I2C clock input/output pins. These functions have a bus driving function. SCL0's output format is an NMOS open drain. I2C data input/output (channel 1, 0): I2C clock input/output pins. These functions have a bus driving function. SCL0's output format is an NMOS open drain. Analog input: Analog input pins. A/D conversion external trigger input: Pin for input of an external trigger to start A/D conversion. Analog output: Analog output pins for D/A converter. Analog power supply: A/D converter and D/A converter power supply pin. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+5 V). Rev. 3.00 Jan 11, 2005 page 17 of 1220 REJ09B0186-0300O I2C bus interface SCL0 (IIC) (optional) SCL1 SDA0 SDA1 I/O A/D converter AN15 to AN0 Input Input Output Input GRTDA D/A converter A/D converter, D/A converter DA3 to DA0 AVCC Section 1 Overview Type A/D converter, D/A converter Symbol AVSS I/O Input Name and Function Analog ground: Analog circuit ground and reference voltage. A/D converter and D/A converter ground and reference voltage. Connect to system power supply (0 V). Analog reference power supply: A/D converter and D/A converter reference voltage input pin. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+5 V). I/O ports P17 to P10 I/O Port 1: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 1 data direction register (P1DDR). Port 2: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 2 data direction register (P2DDR). Port 3: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 3 data direction register (P3DDR). Port 4: An 8-bit input port. Port 5: A 3-bit I/O port. Input or output can be designated for each bit by means of the port 5 data direction register (P5DDR). Port 7: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 7 data direction register (P7DDR). Port 8: A 7-bit I/O port. Input or output can be designated for each bit by means of the port 8 data direction register (P8DDR). Port 9: An 8-bit input port. Port A: A 8-bit I/O port. Input or output can be designated for each bit by means of the port A data direction register (PADDR). Port B: An 8-bit I/O port. Input or output can be designated for each bit by means of the port B data direction register (PBDDR). Port C: An 8-bit I/O port. Input or output can be designated for each bit by means of the port C data direction register (PCDDR). Port D: An 8-bit I/O port. Input or output can be designated for each bit by means of the port D data direction register (PDDDR). Vref Input P27 to P20 I/O P37 to P30 I/O P47 to P40 P52 to P50 Input I/O P77 to P70 I/O P86 to P80 I/O P97 to P90 PA7 to PA0 Input I/O PB7 to PB0 I/O PC7 to PC0 I/O PD7 to PD0 I/O Rev. 3.00 Jan 11, 2005 page 18 of 1220 REJ09B0186-0300O Section 1 Overview Type I/O ports Symbol PE7 to PE0 I/O I/O Name and Function Port E: An 8-bit I/O port. Input or output can be designated for each bit by means of the port E data direction register (PEDDR). Port F: An 8-bit I/O port. Input or output can be designated for each bit by means of the port F data direction register (PFDDR). Port G: A 5-bit I/O port. Input or output can be designated for each bit by means of the port G data direction register (PGDDR). PF7 to PF0 I/O PG4 to PG0 I/O Rev. 3.00 Jan 11, 2005 page 19 of 1220 REJ09B0186-0300O Section 1 Overview Rev. 3.00 Jan 11, 2005 page 20 of 1220 REJ09B0186-0300O Section 2 CPU Section 2 CPU 2.1 Overview The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2600 CPU has the following features. • Upward-compatible with H8/300 and H8/300H CPUs  Can execute H8/300 and H8/300H object programs • General-register architecture  Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • Sixty-nine basic instructions  8/16/32-bit arithmetic and logic instructions  Multiply and divide instructions  Powerful bit-manipulation instructions  Multiply-and-accumulate instructions • Eight addressing modes  Register direct [Rn]  Register indirect [@ERn]  Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]  Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]  Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]  Immediate [#xx:8, #xx:16, or #xx:32]  Program-counter relative [@(d:8,PC) or @(d:16,PC)]  Memory indirect [@@aa:8] • 16-Mbyte address space  Program: 16 Mbytes  Data: 16 Mbytes (4 Gbytes architecturally) Rev. 3.00 Jan 11, 2005 page 21 of 1220 REJ09B0186-0300O Section 2 CPU • High-speed operation  All frequently-used instructions execute in one or two states  Maximum clock rate : 25 MHz  8/16/32-bit register-register add/subtract : 40 ns  8 × 8-bit register-register multiply : 120 ns  16 ÷ 8-bit register-register divide : 480 ns  16 × 16-bit register-register multiply : 160 ns  32 ÷ 16-bit register-register divide : 800 ns • Two CPU operating modes  Normal mode*  Advanced mode Note: * Not available in the H8S/2643 Group. • Power-down state  Transition to power-down state by SLEEP instruction  CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. • Register configuration  The MAC register is supported only by the H8S/2600 CPU. • Basic instructions  The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. • Number of execution states  The number of execution states of the MULXU and MULXS instructions is different in each CPU. Execution States Instruction MULXU MULXS Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21 Rev. 3.00 Jan 11, 2005 page 22 of 1220 REJ09B0186-0300O Section 2 CPU In addition, there are differences in address space, CCR and EXR register functions, power-down modes, etc., depending on the model. 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements. • More general registers and control registers  Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added. • Expanded address space  Normal mode* supports the same 64-kbyte address space as the H8/300 CPU.  Advanced mode supports a maximum 16-Mbyte address space. Note: * Not available in the H8S/2643 Group. • Enhanced addressing  The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. • Enhanced instructions  Addressing modes of bit-manipulation instructions have been enhanced.  Signed multiply and divide instructions have been added.  A multiply-and-accumulate instruction has been added.  Two-bit shift instructions have been added.  Instructions for saving and restoring multiple registers have been added.  A test and set instruction has been added. • Higher speed  Basic instructions execute twice as fast. 2.1.4 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements. • Additional control register  One 8-bit and two 32-bit control registers have been added. • Enhanced instructions  Addressing modes of bit-manipulation instructions have been enhanced.  A multiply-and-accumulate instruction has been added.  Two-bit shift instructions have been added. Rev. 3.00 Jan 11, 2005 page 23 of 1220 REJ09B0186-0300O Section 2 CPU  Instructions for saving and restoring multiple registers have been added.  A test and set instruction has been added. • Higher speed  Basic instructions execute twice as fast. 2.2 CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode* supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data areas combined). The mode is selected by the mode pins of the microcontroller. Note: * Not available in the H8S/2643 Group. Maximum 64 kbytes, program and data areas combined Normal mode* CPU operating modes Advanced mode Maximum 16-Mbytes for program and data areas combined Note: * Not available in the H8S/2643 Group. Figure 2.1 CPU Operating Modes (1) Normal Mode (Not Available in the H8S/2643 Group) The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@–Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. Rev. 3.00 Jan 11, 2005 page 24 of 1220 REJ09B0186-0300O Section 2 CPU Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits (figure 2.2). The exception vector table differs depending on the microcontroller. For details of the exception vector table, see section 4, Exception Handling. H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Power-on reset exception vector Manual reset exception vector (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.2 Exception Vector Table (Normal Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. Rev. 3.00 Jan 11, 2005 page 25 of 1220 REJ09B0186-0300O Section 2 CPU Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. SP PC (16 bits) SP *2 (SP ) EXR*1 Reserved*1*3 CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. Figure 2.3 Stack Structure in Normal Mode (2) Advanced Mode Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program and data areas combined). Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. Instruction Set: All instructions and addressing modes can be used. Rev. 3.00 Jan 11, 2005 page 26 of 1220 REJ09B0186-0300O Section 2 CPU Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Power-on reset exception vector H'00000003 H'00000004 Reserved Manual reset exception vector H'00000007 H'00000008 Exception vector table H'0000000B H'0000000C (Reserved for system use) H'00000010 Reserved Exception vector 1 Figure 2.4 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table. Rev. 3.00 Jan 11, 2005 page 27 of 1220 REJ09B0186-0300O Section 2 CPU Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. SP SP Reserved PC (24 bits) *2 (SP ) EXR*1 Reserved*1*3 CCR PC (24 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. Figure 2.5 Stack Structure in Advanced Mode Rev. 3.00 Jan 11, 2005 page 28 of 1220 REJ09B0186-0300O Section 2 CPU 2.3 Address Space Figure 2.6 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF Data area Cannot be used by the H8S/2643 Group H'FFFFFFFF (a) Normal Mode* Note: * Not available in the H8S/2643 Group. (b) Advanced Mode Figure 2.6 Memory Map Rev. 3.00 Jan 11, 2005 page 29 of 1220 REJ09B0186-0300O Section 2 CPU 2.4 2.4.1 Register Configuration Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) Control Registers (CR) 23 PC 76543210 EXR T — — — — I2 I1 I0 76543210 CCR I UI H U N Z V C 63 MAC 31 Legend: SP: PC: EXR: T: I2 to I0: CCR: I: UI: Sign extension MACL 0 41 MACH 32 0 E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit* H: U: N: Z: V: C: MAC: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Multiply-accumulate register Note: * Cannot be used as an interrupt mask bit in the H8S/2643 Group. Figure 2.7 CPU Registers Rev. 3.00 Jan 11, 2005 page 30 of 1220 REJ09B0186-0300O Section 2 CPU 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2.8 illustrates the usage of the general registers. The usage of each register can be selected independently. • Address registers • 32-bit registers • 16-bit registers E registers (extended registers) (E0 to E7) • 8-bit registers ER registers (ER0 to ER7) R registers (R0 to R7) RH registers (R0H to R7H) RL registers (R0L to R7L) Figure 2.8 Usage of General Registers Rev. 3.00 Jan 11, 2005 page 31 of 1220 REJ09B0186-0300O Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the stack. Free area SP (ER7) Stack area Figure 2.9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), and 64-bit multiply-accumulate register (MAC). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) (2) Extended Control Register (EXR) This 8-bit register contains the trace bit (T) and three interrupt mask bits (I2 to I0). Bit 7—Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is executed. Bits 6 to 3—Reserved: They are always read as 1. Rev. 3.00 Jan 11, 2005 page 32 of 1220 REJ09B0186-0300O Section 2 CPU Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. All interrupts, including NMI, are disabled for three states after one of these instructions is executed, except for STC. (3) Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller. Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details, refer to section 5, Interrupt Controller. Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data. Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: • Add instructions, to indicate a carry • Subtract instructions, to indicate a borrow • Shift and rotate instructions, to store the value shifted out of the end bit Rev. 3.00 Jan 11, 2005 page 33 of 1220 REJ09B0186-0300O Section 2 CPU The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to Appendix A.1, List of Instructions. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. (4) Multiply-Accumulate Register (MAC) This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are a sign extension. 2.4.4 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. Rev. 3.00 Jan 11, 2005 page 34 of 1220 REJ09B0186-0300O Section 2 CPU 2.5 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.10 shows the data formats in general registers. Data Type Register Number Data Format 1-bit data RnH 7 0 76543210 Don’t care 1-bit data RnL Don’t care 7 0 76543210 4-bit BCD data RnH 7 Upper 43 Lower 0 Don’t care 4-bit BCD data RnL Don’t care 7 Upper 43 Lower 0 Byte data RnH 7 MSB 0 Don’t care LSB 7 Don’t care Byte data RnL 0 LSB MSB Figure 2.10 General Register Data Formats (1) Rev. 3.00 Jan 11, 2005 page 35 of 1220 REJ09B0186-0300O Section 2 CPU Data Type Register Number Data Format Word data Rn 15 MSB 0 LSB Word data 15 MSB Longword data 31 MSB En 0 LSB ERn 16 15 En Rn 0 LSB Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.10 General Register Data Formats (2) Rev. 3.00 Jan 11, 2005 page 36 of 1220 REJ09B0186-0300O Section 2 CPU 2.5.2 Memory Data Formats Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 0 0 Data Format Byte data Address L MSB LSB Word data Address 2M MSB Address 2M + 1 LSB Longword data Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB Figure 2.11 Memory Data Formats When ER7 is used as an address register to access the stack, the operand size should be word size or longword size. Rev. 3.00 Jan 11, 2005 page 37 of 1220 REJ09B0186-0300O Section 2 CPU 2.6 2.6.1 Instruction Set Overview The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Function Data transfer Instruction Classification Instructions MOV POP* , PUSH* LDM* , STM* 3 5 5 3 1 1 Size BWL WL L B BWL B BWL L BW WL B — BWL B — — Types 5 MOVFPE* , MOVTPE* Arithmetic operations ADD, SUB, CMP, NEG 23 ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS*4 MAC, LDMAC, STMAC, CLRMAC Logic operations Shift Bit manipulation Branch System control Legend: AND, OR, XOR, NOT BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc*2, JMP, BSR, JSR, RTS 4 8 14 5 9 1 SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — Block data transfer EEPMOV Notes: 1. 2. 3. 4. 5. B: byte size W: word size L: longword size POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. Bcc is the general name for conditional branch instructions. Not available in the H8S/2643 Group. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Only register ER0 to ER6 should be used when using the STM/LDM instruction. Rev. 3.00 Jan 11, 2005 page 38 of 1220 REJ09B0186-0300O 2.6.2 Addressing Modes Table 2.2 Function Instruction #xx Rn @ERn @(d:16,ERn) @(d:32,ERn) @–ERn/@ERn+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,PC) @(d:16,PC) @@aa:8 Data transfer POP, PUSH LDM*3, STM*3 — — BWL WL B — — — — — — — — — — — L — — — — — — — — — — — — — — — — — B — — — — — — — — WL — — — — — — BWL — — — — — — — — — — — — BW — — — — — — — — — — — — — — BW — — — — — — — — B — — — — — — — — BWL — — — — — — — — — — — — — — — — — — L — — — — — — — — — B — — — — — — — — — BWL — — — — — — — — — — — — — — — — — — — — — — BWL — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — B — — — — — — — — — — — — — — — — — L — — — — — — — — — — — — — MOVEPE*1, MOVTPE*1 Arithmetic operations SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, DIVXU MULXS, DIVXS NEG EXTU, EXTS TAS*2 MAC CLRMAC LDMAC, STMAC ADD, CMP — — — — — — — — — — — — — WL Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Combinations of Instructions and Addressing Modes MOV BWL BWL BWL BWL BWL BWL B BWL — BWL — — — — — Rev. 3.00 Jan 11, 2005 page 39 of 1220 REJ09B0186-0300O Section 2 CPU Addressing Modes Function Instruction #xx Rn @ERn @(d:16,ERn) @(d:32,ERn) @–ERn/@ERn+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,PC) @(d:16,PC) @@aa:8 — Section 2 CPU Logic operations AND, OR, XOR NOT Shift Bit manipulation — — — — — — — B — B — — — — — — — — — — — — — — — — — B W W W W B W W W W — — — — — — — — — — — — — — — — — — — W W — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — B B — — — B B — Branch JMP, JSR RTS System control RTE SLEEP LDC STC ANDC, ORC, XORC NOP Block data transfer Legend: B: Byte W: Word L: Longword Notes: 1. Not available in the H8S/2643 Group. 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 3. Only register ER0 to ER6 should be used when using the STM/LDM instruction. BWL — — B — — — — — — W W — — — — — — — — — — — — — BWL — — — — — — — — BWL — — — — — — — — — — — BWL — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Bcc, BSR Rev. 3.00 Jan 11, 2005 page 40 of 1220 REJ09B0186-0300O TRAPA — — — BW Section 2 CPU 2.6.3 Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + – × ÷ ∧ ∨ ⊕ → ¬ :8/:16/:24/:32 General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 3.00 Jan 11, 2005 page 41 of 1220 REJ09B0186-0300O Section 2 CPU Table 2.3 Type Data transfer Instructions Classified by Function Instruction MOV Size*1 B/W/L Function (EAs) → Rd, Rs → (Ead) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Cannot be used in the H8S/2643 Group. Cannot be used in the H8S/2643 Group. @SP+ → Rn Pops a register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn → @–SP Pushes a register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP. @SP+ → Rn (register list) Pops two or more general registers from the stack. Rn (register list) → @–SP Pushes two or more general registers onto the stack. Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. Rd ± 1 → Rd, Rd ± 2 → Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust → Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. MOVFPE MOVTPE POP B B W/L PUSH W/L LDM*3 STM*3 Arithmetic operations ADD SUB L L B/W/L ADDX SUBX B INC DEC B/W/L ADDS SUBS DAA DAS L B Rev. 3.00 Jan 11, 2005 page 42 of 1220 REJ09B0186-0300O Section 2 CPU Type Arithmetic operations Instruction MULXU Size*1 B/W Function Rd × Rs → Rd Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. Rd × Rs → Rd Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. Rd ÷ Rs → Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder. Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder. Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 – Rd → Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. @ERd – 0, 1 → ( of @ERd)*2 Tests memory contents, and sets the most significant bit (bit 7) to 1. (EAs) × (EAd) + MAC → MAC Performs signed multiplication on memory contents and adds the result to the multiply-accumulate register. The following operations can be performed: 16 bits × 16 bits + 32 bits → 32 bits, saturating 16 bits × 16 bits + 42 bits → 42 bits, non-saturating Rev. 3.00 Jan 11, 2005 page 43 of 1220 REJ09B0186-0300O MULXS B/W DIVXU B/W DIVXS B/W CMP B/W/L NEG B/W/L EXTU W/L EXTS W/L TAS B MAC — Section 2 CPU Type Arithmetic operations Instruction CLRMAC LDMAC STMAC Size*1 — L Function 0 → MAC Clears the multiply-accumulate register to zero. Rs → MAC, MAC → Rd Transfers data between a general register and a multiply-accumulate register. Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. ¬ (Rd) → (Rd) Takes the one's complement of general register contents. Rd (shift) → Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. Rd (shift) → Rd Performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. Rd (rotate) → Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. Rd (rotate) → Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. Logic operations AND B/W/L OR B/W/L XOR B/W/L NOT B/W/L Shift operations SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR B/W/L B/W/L B/W/L B/W/L Bitmanipulation instructions BSET B BCLR B Rev. 3.00 Jan 11, 2005 page 44 of 1220 REJ09B0186-0300O Section 2 CPU Type Bitmanipulation instructions Instruction BNOT Size*1 B Function ¬ ( of ) → ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ¬ ( of ) → Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. C ∧ ( of ) → C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ∧ ¬ ( of ) → C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ∨ ( of ) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ∨ ¬ ( of ) → C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ⊕ ( of ) → C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕ ¬ ( of ) → C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. ( of ) → C Transfers a specified bit in a general register or memory operand to the carry flag. ¬ ( of ) → C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. Rev. 3.00 Jan 11, 2005 page 45 of 1220 REJ09B0186-0300O BTST B BAND B BIAND B BOR B BIOR B BXOR B BIXOR B BLD B BILD B Section 2 CPU Type Bitmanipulation instructions Instruction BST Size*1 B Function C → ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. ¬ C → ( of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE JMP BSR JSR RTS System control TRAPA instructions RTE SLEEP — — — — — — — Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never C∨Z=0 C∨Z=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 N⊕V=0 N⊕V=1 Z ∨ (N ⊕ V) = 0 Z ∨ (N ⊕ V) = 1 BIST B Branch instructions Bcc — Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. Rev. 3.00 Jan 11, 2005 page 46 of 1220 REJ09B0186-0300O Section 2 CPU Type Instruction Size*1 B/W Function (EAs) → CCR, (EAs) → EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR → (EAd), EXR → (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR Logically ANDs the CCR or EXR contents with immediate data. CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR Logically ORs the CCR or EXR contents with immediate data. CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 → PC Only increments the program counter. if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6. R4L or R4: size of block (bytes) ER5: starting source address ER6: starting destination address Execution of the next instruction begins as soon as the transfer is completed. Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword Rev. 3.00 Jan 11, 2005 page 47 of 1220 REJ09B0186-0300O System control LDC instructions STC B/W ANDC B ORC B XORC B NOP Block data transfer instruction EEPMOV.B — — EEPMOV.W — Section 2 CPU 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 3. Only register ER0 to ER6 should be used when using the STM/LDM instruction. 2.6.4 Basic Instruction Formats The H8S/2643 Group instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). (1) Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. (2) Register Field Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. (3) Effective Address Extension Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. (4) Condition Field Specifies the branching condition of Bcc instructions. Rev. 3.00 Jan 11, 2005 page 48 of 1220 REJ09B0186-0300O Section 2 CPU Figure 2.12 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc rn rm MOV.B @(d:16, Rn), Rm, etc. Figure 2.12 Instruction Formats (Examples) Rev. 3.00 Jan 11, 2005 page 49 of 1220 REJ09B0186-0300O Section 2 CPU 2.7 2.7.1 Addressing Modes and Effective Address Calculation Addressing Mode The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.4 No. 1 2 3 4 5 6 7 8 Addressing Modes Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @–ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 (1) Register Direct—Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. (2) Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). Rev. 3.00 Jan 11, 2005 page 50 of 1220 REJ09B0186-0300O Section 2 CPU (3) Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. (4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. • Register indirect with pre-decrement—@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. (5) Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.5 indicates the accessible absolute address ranges. Rev. 3.00 Jan 11, 2005 page 51 of 1220 REJ09B0186-0300O Section 2 CPU Table 2.5 Absolute Address Access Ranges Normal Mode* 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF Absolute Address Data address Program instruction address 24 bits (@aa:24) Note: * Not available in the H8S/2643 Group. (6) Immediate—#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) Program-Counter Relative—@(d:8, PC) or @(d:16, PC) This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an even number. (8) Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode* the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Rev. 3.00 Jan 11, 2005 page 52 of 1220 REJ09B0186-0300O Section 2 CPU Note: * Not available in the H8S/2643 Group. Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode* Note: * Not available in the H8S/2643 Group. (b) Advanced Mode Figure 2.13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation Table 2.6 indicates how effective addresses are calculated in each addressing mode. In normal mode* the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: * Not available in the H8S/2643 Group. Rev. 3.00 Jan 11, 2005 page 53 of 1220 REJ09B0186-0300O No. Effective Address Calculation 1 op 2 31 31 Don’t care 24 23 General register contents op r 0 Register indirect (@ERn) rm rn Operand is general register contents. Register direct (Rn) Table 2.6 Section 2 CPU Addressing Mode and Instruction Format Effective Address (EA) 0 3 31 General register contents 31 op disp 31 Sign extension disp 0 r 0 Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) 24 23 Don’t care Rev. 3.00 Jan 11, 2005 page 54 of 1220 REJ09B0186-0300O 0 4 31 General register contents op r 1, 2, or 4 • Register indirect with pre-decrement @–ERn 31 General register contents 31 op r Operand Size Value added Byte Word Longword 1 2 4 1, 2, or 4 24 23 Don’t care 0 0 Register indirect with post-increment or pre-decrement • Register indirect with post-increment @ERn+ 0 31 24 23 Don’t care 0 Effective Address Calculation No. Effective Address Calculation 5 @aa:8 31 24 23 H'FFFF abs Don’t care Addressing Mode and Instruction Format Absolute address 87 Effective Address (EA) 0 op @aa:16 31 op abs 24 23 16 15 0 Don’t care Sign extension @aa:24 op abs 31 24 23 Don’t care 0 @aa:32 op abs 31 24 23 Don’t care 0 6 op IMM Immediate #xx:8/#xx:16/#xx:32 Operand is immediate data. Rev. 3.00 Jan 11, 2005 page 55 of 1220 REJ09B0186-0300O Section 2 CPU No. Effective Address Calculation 23 PC contents @(d:8, PC)/@(d:16, PC) 0 7 Program-counter relative Section 2 CPU Addressing Mode and Instruction Format Effective Address (EA) op 23 Sign extension disp 31 Don’t care disp 0 24 23 0 8 Memory indirect @@aa:8 • Normal mode* op 31 H'000000 87 abs abs 0 Rev. 3.00 Jan 11, 2005 page 56 of 1220 REJ09B0186-0300O 31 24 23 Don’t care 16 15 H'00 0 15 Memory contents • Advanced mode op abs 31 H'000000 31 Memory contents 87 abs 0 0 0 31 24 23 Don’t care 0 Note: * Not available in the H8S/2643 Group. Section 2 CPU 2.8 2.8.1 Processing States Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, interrupt, or trap instruction. Processing states Program execution state The CPU executes program instructions in sequence. Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU. Sleep mode Power-down state CPU operation is stopped to conserve power.* Software standby mode Hardware standby mode Note: * The power-down state also includes a medium-speed mode, module stop mode, subactive mode, subsleep mode, and watch mode. Figure 2.14 Processing States Rev. 3.00 Jan 11, 2005 page 57 of 1220 REJ09B0186-0300O Section 2 CPU End of bus request Bus request Program execution state SLEEP instruction with SSBY = 0 xc ep Bus-released state tio n ha s bu t of t es d ues qu En req re s Bu nd lin g Sleep mode En d o ha f ex nd ce lin pti g on Re qu es tf or e Inte rru pt r eq t ues SLEEP instruction with SSBY = 1 Exception handling state External interrupt request Software standby mode MRES= High RES= High STBY= High, RES= Low Manual reset state *1 Power-on reset state *1 Hardware standby mode*2 Reset state *1 Power-down state*3 Notes: 1. From any state except hardware standby mode, a transition to the power-on reset state occurs whenever RES goes low. From any state except hardware standby mode and power-on reset mode, a transition to the manual reset state occurs whenever MRES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. 3. Apart from these states, there are also the watch mode, subactive mode, and the subsleep mode. See section 24, Power-Down Modes. Figure 2.15 State Transitions 2.8.2 Reset State pin goes low, or when the pin goes low while The CPU enters the reset state when the manual resets are enabled by the MRESE bit. In the reset state, currently executing processing is halted and all interrupts are disabled. For details of MRESE bit setting, see section 3.2.2, System Control Register (SYSCR). The reset state can also be entered in the event of watchdog timer overflow. For details see section 15, Watchdog Timer. Rev. 3.00 Jan 11, 2005 page 58 of 1220 REJ09B0186-0300O SERM Note: * pin in the case of a manual reset. SERM SER Reset exception handling starts when the or pin* changes from low to high. SERM SER Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2.7 indicates the types of exception handling and their priority. Trap instruction exception handling is always accepted, in the program execution state. Exception handling and the stack structure depend on the interrupt control mode set in SYSCR. Table 2.7 Priority High Exception Handling Types and Priority Type of Exception Reset Detection Timing Synchronized with clock Start of Exception Handling Exception handling starts immediately after a low-to-high transition at the pin, or when the watchdog timer overflows. When the trace (T) bit is set to 1, the trace starts at the end of the current instruction or current exception-handling sequence When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Exception handling starts when a trap (TRAPA) instruction is executed*3 Trace End of instruction execution or end of exception-handling sequence*1 End of instruction execution or end of exception-handling sequence*2 When TRAPA instruction is executed Interrupt Trap instruction Low Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not executed at the end of the RTE instruction. 2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. 3. Trap instruction exception handling is always accepted, in the program execution state. Rev. 3.00 Jan 11, 2005 page 59 of 1220 REJ09B0186-0300O SER Section 2 CPU (2) Reset Exception Handling pin has gone low and the reset state has been entered, when pin goes high After the again, reset exception handling starts. After the reset state has been entered by driving the pin low while manual resets are enabled by the MRESE bit, reset exception handling starts when pin is driven high again. The CPU enters the power-on reset state when the pin is low, pin is low. When reset exception handling starts and enters the manual reset state when the the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. (3) Traces Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR is set to 1. When trace mode is established, trace exception handling starts at the end of each instruction. At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode is cleared. Interrupt masks are not affected. The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to return from the trace exception-handling routine, trace mode is entered again. Trace exceptionhandling is not executed at the end of the RTE instruction. Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit. (4) Interrupt Exception Handling and Trap Instruction Exception Handling When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution starts from that start address. Figure 2.16 shows the stack after exception handling ends. Rev. 3.00 Jan 11, 2005 page 60 of 1220 REJ09B0186-0300O SERM SER SER SERM SER SERM Section 2 CPU Normal mode*2 SP SP CCR CCR*1 PC (16 bits) EXR Reserved*1 CCR CCR*1 PC (16 bits) (a) Interrupt control mode 0 (b) Interrupt control mode 2 Advanced mode SP SP CCR PC (24 bits) EXR Reserved*1 CCR PC (24 bits) (c) Interrupt control mode 0 Notes: 1. Ignored when returning. 2. Not available in the H8S/2643 Group. (d) Interrupt control mode 2 Figure 2.16 Stack Structure after Exception Handling (Examples) Rev. 3.00 Jan 11, 2005 page 61 of 1220 REJ09B0186-0300O Section 2 CPU 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. Bus masters other than the CPU are DMA controller (DMAC) and data transfer controller (DTC). For further details, refer to section 7, Bus Controller. 2.8.6 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode, software standby mode, hardware standby mode, subsleep mode, and watch mode. There are also three other power-down modes: medium-speed mode, module stop mode, and subactive mode. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. Subactive mode, subsleep mode, and watch mode are power-down states using subclock input. For details, refer to section 24, Power-Down Modes. (1) Sleep Mode A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) in the standby control register (SBYCR) is cleared to 0. In sleep mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU registers are retained. (2) Software Standby Mode A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1. In software standby mode, the CPU and clock halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of CPU registers and onchip RAM are retained. The I/O ports also remain in their existing states. Rev. 3.00 Jan 11, 2005 page 62 of 1220 REJ09B0186-0300O Section 2 CPU (3) Hardware Standby Mode pin goes low. In hardware A transition to hardware standby mode is made when the standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. 2.9 2.9.1 Basic Timing Overview The H8S/2600 CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge of φ to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 On-Chip Memory (ROM, RAM) On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 2.17 shows the on-chip memory access cycle. Figure 2.18 shows the pin states. Bus cycle T1 φ Internal address bus Internal read signal Internal data bus Internal write signal Write access Internal data bus Write data Read data Address Read access Figure 2.17 On-Chip Memory Access Cycle Rev. 3.00 Jan 11, 2005 page 63 of 1220 REJ09B0186-0300O YBTS Section 2 CPU Bus cycle T1 φ Address bus AS RD HWR, LWR Data bus Unchanged High High High High-impedance state Figure 2.18 Pin States during On-Chip Memory Access Rev. 3.00 Jan 11, 2005 page 64 of 1220 REJ09B0186-0300O Section 2 CPU 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the access timing for the on-chip supporting modules. Figure 2.20 shows the pin states. Bus cycle T1 φ T2 Internal address bus Address Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Write data Read data Figure 2.19 On-Chip Supporting Module Access Cycle Rev. 3.00 Jan 11, 2005 page 65 of 1220 REJ09B0186-0300O Section 2 CPU Bus cycle T1 T2 φ Unchanged Address bus AS RD HWR, LWR High High High Data bus High-impedance state Figure 2.20 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 7, Bus Controller. 2.10 2.10.1 Usage Note TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas H8S and H8/300 series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used. Rev. 3.00 Jan 11, 2005 page 66 of 1220 REJ09B0186-0300O Section 2 CPU 2.10.2 STM/LDM Instruction With the STM or LDM instruction, the ER7 register is used as the stack pointer, and thus cannot be used as a register that allows save (STM) or restore (LDM) operation. With a single STM or LDM instruction, two to four registers can be saved or restored. The available registers are as follows: For two registers: ER0 and ER1, ER2 and ER3, or ER4 and ER5 For three registers: ER0 to ER2, or ER4 to ER6 For four registers: ER0 to ER3 For the Renesas H8S or H8/300 Series C/C++ Compiler, the STM/LDM instruction including ER7 is not created. 2.10.3 Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in byte-wise, operate the data in bit-wise, and write the result of the bit-wise operation in bit-wise again. Therefore, special care is necessary to use these instructions for the registers and the ports that include writeonly bit. The BCLR instruction can be used to clear to 0 the flags in the internal I/O registers. In this time, if it is obvious that the flag has been set to 1 in the interrupt handler, there is no need to read the flag beforehand. Rev. 3.00 Jan 11, 2005 page 67 of 1220 REJ09B0186-0300O Section 2 CPU Rev. 3.00 Jan 11, 2005 page 68 of 1220 REJ09B0186-0300O Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 3.1.1 Overview Operating Mode Selection The H8S/2643 Group has four operating modes (modes 4 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD2 to MD0). Table 3.1 lists the MCU operating modes. Table 3.1 MCU Operating Mode Selection External Data Bus On-Chip Initial ROM Width — — Max. Width MCU CPU Operating Operating Mode MD2 MD1 MD0 Mode Description 0* 1* 2* 3* 4 5 6 7 1 1 0 1 0 0 0 1 0 1 0 1 0 1 On-chip ROM enabled, expanded mode Single-chip mode Advanced On-chip ROM disabled, expanded mode — — — Disabled 16 bits 8 bits Enabled 8 bits — 16 bits 16 bits 16 bits Note: * Not available in the H8S/2643 Group. The CPU’s architecture allows for 4 Gbytes of address space, but the H8S/2643 Group actually accesses a maximum of 16 Mbytes. Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8bit access is selected for all areas, 8-bit bus mode is set. Rev. 3.00 Jan 11, 2005 page 69 of 1220 REJ09B0186-0300O Section 3 MCU Operating Modes Note that the functions of each pin depend on the operating mode. The H8S/2643 Group can be used only in modes 4 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.2 Register Configuration The H8S/2643 Group has a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) that controls the operation of the H8S/2643 Group. Table 3.2 summarizes these registers. Table 3.2 Name Mode control register System control register Pin function control register MCU Registers Abbreviation MDCR SYSCR PFCR R/W R/W R/W R/W Initial Value Undetermined H'01 H'0D/H'00 Address* H'FDE7 H'FDE5 H'FDEB Note: * Lower 16 bits of the address. 3.2 3.2.1 Bit Register Descriptions Mode Control Register (MDCR) : 7 — 1 R/W 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 MDS2 —* R 1 MDS1 —* R 0 MDS0 —* R Initial value : R/W : Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit register that indicates the current operating mode of the H8S/2643 Group. Bit 7—Reserved: Only 1 should be written to this bit. Bits 6 to 3—Reserved: These bits always read as 0 and cannot be modified. Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are read-only bits-they cannot be written to. The mode pin (MD2 to MD0) input Rev. 3.00 Jan 11, 2005 page 70 of 1220 REJ09B0186-0300O Section 3 MCU Operating Modes levels are latched into these bits when MDCR is read. These latches are cancelled by a power-on reset, but maintained by a manual reset. 3.2.2 Bit System Control Register (SYSCR) : 7 MACS 0 R/W 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 MRESE 0 R/W 1 — 0 — 0 RAME 1 R/W Initial value : R/W : SYSCR is an 8-bit readable-writable register that selects saturating or non-saturating calculation for the MAC instruction, selects the interrupt control mode, selects the detected edge for NMI, pin input, and enables or disenables on-chip RAM. enables or disenables SYSCR is initialized to H'01 by a power-on reset and in hardware standby mode. MACS, INTM1, INTM0, NMIEG, and RAME bits are initialized in manual reset mode, but the MRESE bit is not initialized. SYSCR is not initialized in software standby mode. Bit 7—MAC Saturation (MACS): Selects either saturating or non-saturating calculation for the MAC instruction. Bit 7 MACS 0 1 Description Non-saturating calculation for MAC instruction Saturating calculation for MAC instruction (Initial value) Bit 6—Reserved: This bit always read as 0 and cannot be modified. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and Interrupt Operation. Bit 5 INTM1 0 1 Bit 4 INTM0 0 1 0 1 Interrupt Control Mode 0 — 2 — SERM Description Control of interrupts by I bit Setting prohibited Control of interrupts by I2 to I0 bits and IPR Setting prohibited (Initial value) Rev. 3.00 Jan 11, 2005 page 71 of 1220 REJ09B0186-0300O Section 3 MCU Operating Modes Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input. Bit 3 NMIEG 0 1 Description An interrupt is requested at the falling edge of NMI input An interrupt is requested at the rising edge of NMI input (Initial value) Bit 2—Manual Reset Selection Bit (MRESE): Enables or disenables manual reset input. It is pin to the manual reset input ( ). possible to set the P74/TM02/ Bit 2 MRESE 0 1 Description Disenables manual reset. Enables manual reset. Possible to use P74/TM02/ Possible to use P74/TM02/ Table 3.3 Relationship Between Power-On Reset and Manual Reset Pin Reset Type Power-on reset Manual reset Operation state *: Don’t care (Initial state) 0 1 1 * 0 1 Bit 1—Reserved: This bit always read as 0 and cannot be modified. Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset status is released. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) Note: When the DTC is used, the RAME bit must be set to 1. Rev. 3.00 Jan 11, 2005 page 72 of 1220 REJ09B0186-0300O SERM SERM pin as Table 3.3 shows the relationship between the pin power-on reset and manual reset. pin as P74/TM02 input pin. input pin. SERM SERM SERM SERM (Initial value) SERM SER Section 3 MCU Operating Modes 3.2.3 Bit Pin Function Control Register (PFCR) : 7 CSS07 0 R/W 6 CSS36 0 R/W 5 BUZZE 0 R/W 4 LCASS 0 R/W 3 AE3 1/0 R/W 2 AE2 1/0 R/W 1 AE1 0 R/W 0 AE0 1/0 R/W Initial value : R/W : PFCR is an 8-bit readable-writable register that carries out CS selection control for PG4 and PG1 pins, LCAS selection control for PF2 and PF6 pins, and address output control during extension modes with ROM. PFCR is initialized by H'0D/H'00 by a power-on reset or a hardware standby mode. The immediately previous state is maintained in manual reset or software standby mode. / Select (CSS07): Selects the CS output content for PG4 pin. In modes 4 to 6, the Bit 7— selected CS is output by setting the corresponding DDR to 1. Bit 7 CSS07 0 1 Description Select Bit 6— / Select (CSS36): Selects the CS output content for PG1 pin. In modes 4 to 6, the selected CS is output by setting the corresponding DDR to 1. Bit 6 CSS36 0 1 Description Select SC 3SC Select 7SC 0SC 7SC 0SC 6SC 3SC Select (Initial value) (Initial value) Rev. 3.00 Jan 11, 2005 page 73 of 1220 REJ09B0186-0300O Section 3 MCU Operating Modes Bit 5—BUZZ Output Enable (BUZZE): Disenables/enables BUZZ output of PF1 pin. Input clock of WDT1 selected by PSS, CKS2 to CKS0 bits is output as a BUZZ signal. Bit 5 BUZZE 0 1 Description Functions as PF1 input pin Functions as BUZZ output pin (Initial value) Bit 4—LCAS Output Pin Selection Bit (LCASS): Selects the LCAS signal output pin. Bit 4 LCASS 0 1 Description Outputs LCAS signal from PF2 Outputs LCAS signal from PF6 (Initial Value) Bits 3 to 0—Address Output Enable 3 to 0 (AE3 to AE0): These bits select enabling or disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is enabled for address output, the address is output regardless of the corresponding DDR setting. When a pin is disabled for address output, it becomes an output port when the corresponding DDR bit is set to 1. Rev. 3.00 Jan 11, 2005 page 74 of 1220 REJ09B0186-0300O Section 3 MCU Operating Modes Bit 3 AE3 0 Bit 2 AE2 0 Bit 1 AE1 0 1 Bit 0 AE0 0 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Description A8 to A23 address output disabled (Initial value*) A8 address output enabled; A9 to A23 address output disabled A8, A9 address output enabled; A10 to A23 address output disabled A8 to A10 address output enabled; A11 to A23 address output disabled A8 to A11 address output enabled; A12 to A23 address output disabled A8 to A12 address output enabled; A13 to A23 address output disabled A8 to A13 address output enabled; A14 to A23 address output disabled A8 to A14 address output enabled; A15 to A23 address output disabled A8 to A15 address output enabled; A16 to A23 address output disabled A8 to A16 address output enabled; A17 to A23 address output disabled A8 to A17 address output enabled; A18 to A23 address output disabled A8 to A18 address output enabled; A19 to A23 address output disabled A8 to A19 address output enabled; A20 to A23 address output disabled A8 to A20 address output enabled; A21 to A23 address output disabled (Initial value*) A8 to A21 address output enabled; A22, A23 address output disabled A8 to A23 address output enabled Note: * In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000. In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101. Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to 1. Rev. 3.00 Jan 11, 2005 page 75 of 1220 REJ09B0186-0300O Section 3 MCU Operating Modes 3.3 3.3.1 Operating Mode Descriptions Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B, and C, function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. 3.3.2 Mode 5 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B, and C, function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.3 Mode 6 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Ports A, B, and C, function as input port pins immediately after a reset. Address output can be performed by setting the corresponding DDR (data direction register) bits to 1. Port D function as a data bus, and part of port F carries data bus signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.4 Mode 7 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. Rev. 3.00 Jan 11, 2005 page 76 of 1220 REJ09B0186-0300O Section 3 MCU Operating Modes 3.4 Pin Functions in Each Operating Mode The pin functions of ports A to G vary depending on the operating mode. Table 3.3 shows their functions in each operating mode. Table 3.3 Port Port A Port B Port C Port D Port E Port F PF7 PF6 to PF4 PF3 PF2 to PF0 Port G PG4 PG3 to PG0 Legend: P: I/O port A: Address bus output D: Data bus I/O C: Control signals, clock I/O *: After reset PA7 to PA5 PA4 to PA0 Pin Functions in Each Mode Mode 4 P*/A P/A* P/A* A D P/D* P/C* C P/C* P*/C C P*/C Mode 5 P*/A P/A* P/A* A D P*/D P/C* C P*/C P*/C C P*/C Mode 6 P*/A P*/A P*/A P*/A D P*/D P/C* C P*/C P*/C P*/C P*/C P Mode 7 P P P P P P P*/C P 3.5 Address Map in Each Operating Mode An address map of the H8S/2643 is shown in figure 3.1, an address map of the H8S/2642 in figure 3.2, and an address map of the H8S/2641 in figure 3.3. The address space is 16 Mbytes in modes 4 to 7 (advanced mode). The address space is divided into eight areas for modes 4 to 7. For details, see section 7, Bus Controller. Rev. 3.00 Jan 11, 2005 page 77 of 1220 REJ09B0186-0300O Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) Mode 7 (advanced single-chip mode) H'000000 H'000000 External address space On-chip ROM On-chip ROM H'03FFFF H'040000 H'FFB000 On-chip RAM*1 H'FFEFC0 H'FFF800 Internal I/O registers*2 H'FFFF40 H'FFFF60 H'FFFFC0 H'FFFFFF Notes: 1. 2. External address space Internal I/O registers On-chip RAM*1 H'FFFF40 H'FFFF60 H'FFFFC0 H'FFFFFF H'FFEFC0 H'FFF800 Internal I/O registers*2 H'FFFF3F External address space Internal I/O registers On-chip RAM*1 H'FFFF60 H'FFFFC0 H'FFFFFF Internal I/O registers On-chip RAM H'FFB000 On-chip RAM*1 H'FFEFBF External address space External address space H'FFF800 Internal I/O registers*2 External address space H'FFB000 On-chip RAM External addresses can be accessed by clearing th RAME bit in SYSCR to 0. Area H'FFF800 to H'FFFDAB is reserved, and must not be accessed. Figure 3.1 Memory Map in Each Operating Mode in the H8S/2643 Rev. 3.00 Jan 11, 2005 page 78 of 1220 REJ09B0186-0300O Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) Mode 6 (advanced expanded mode with on-chip ROM enabled) Mode 7 (advanced single-chip mode) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM External address space H'02FFFF H'030000 Reserved area H'040000 H'FFB000 H'FFC000 Reserved area On-chip RAM*1 H'FFEFC0 H'FFF800 Internal I/O registers*2 H'FFFF40 H'FFFF60 H'FFFFC0 H'FFFFFF Notes: 1. 2. External address space Internal I/O registers On-chip RAM*1 H'FFFF40 H'FFFF60 H'FFFFC0 H'FFFFFF External address space H'FFEFC0 H'FFF800 H'FFB000 H'FFC000 External address space Reserved area H'FFC000 On-chip RAM*1 H'FFEFBF External address space H'FFF800 Internal I/O registers*2 H'FFFF3F External address space Internal I/O registers On-chip RAM*1 H'FFFF60 H'FFFFC0 H'FFFFFF Internal I/O registers On-chip RAM Internal I/O registers*2 On-chip RAM External addresses can be accessed by clearing th RAME bit in SYSCR to 0. Area H'FFF800 to H'FFFDAB is reserved, and must not be accessed. Figure 3.2 Memory Map in Each Operating Mode in the H8S/2642 Rev. 3.00 Jan 11, 2005 page 79 of 1220 REJ09B0186-0300O Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) Mode 6 (advanced expanded mode with on-chip ROM enabled) Mode 7 (advanced single-chip mode) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM H'020000 External address space H'01FFFF Reserved area H'040000 H'FFB000 H'FFD000 Reserved area On-chip RAM*1 H'FFEFC0 H'FFF800 Internal I/O registers*2 H'FFFF40 H'FFFF60 H'FFFFC0 H'FFFFFF Notes: 1. 2. External address space Internal I/O registers On-chip RAM*1 H'FFFF40 H'FFFF60 H'FFFFC0 H'FFFFFF External address space H'FFEFC0 H'FFF800 H'FFB000 H'FFD000 External address space Reserved area H'FFD000 On-chip RAM*1 H'FFEFBF External address space H'FFF800 Internal I/O registers*2 H'FFFF3F External address space Internal I/O registers On-chip RAM*1 H'FFFF60 H'FFFFC0 H'FFFFFF Internal I/O registers On-chip RAM Internal I/O registers*2 On-chip RAM External addresses can be accessed by clearing th RAME bit in SYSCR to 0. Area H'FFF800 to H'FFFDAB is reserved, and must not be accessed. Figure 3.3 Memory Map in Each Operating Mode in the H8S/2641 Rev. 3.00 Jan 11, 2005 page 80 of 1220 REJ09B0186-0300O Section 4 Exception Handling Section 4 Exception Handling 4.1 4.1.1 Overview Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, direct transition, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times, in the program execution state. Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR. Table 4.1 Priority High Exception Types and Priority Exception Type Reset Start of Exception Handling Starts immediately after a low-to-high transition at the pin or pin, or when the watchdog overflows. The CPU enters the power-on reset state when the pin is low, and the manual reset state when the pin is low. Starts when execution of the current instruction or exception handling ends, if the trace (T) bit is set to 1 Starts when a direct transition occurs due to execution of a SLEEP instruction. Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued*2 Trace*1 Direct transition Interrupt Low Trap instruction (TRAPA)*3 Started by execution of a trap instruction (TRAPA) Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in program execution state. Rev. 3.00 Jan 11, 2005 page 81 of 1220 REJ09B0186-0300O SER SERM SER SERM Section 4 Exception Handling 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out. 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Reset Power-on reset Manual reset Trace Exception sources Interrupts External interrupts: NMI, IRQ7 to IRQ0 Internal interrupts: 72 interrupt sources in on-chip supporting modules Trap instruction Figure 4.1 Exception Sources Rev. 3.00 Jan 11, 2005 page 82 of 1220 REJ09B0186-0300O Section 4 Exception Handling Table 4.2 Exception Vector Table Vector Address*1 Exception Source Power-on reset Manual reset* 3 Vector Number 0 1 2 3 4 Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063 H'01FC to H'01FF  Reserved for system use Trace Direct transition* 3 5 6 NMI 7 8 9 10 11 External interrupt Trap instruction (4 sources) Reserved for system use 12 13 14 15 External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 16 17 18 19 20 21 22 23 24 127  Internal interrupt* 2 Notes: 1. Lower 16 bits of the address. 2. For details of internal interrupt vectors, see section 5.3.3, Interrupt Exception Handling Vector Table. 3. See section 24.11, Direct Transitions for details on direct transition. Rev. 3.00 Jan 11, 2005 page 83 of 1220 REJ09B0186-0300O Section 4 Exception Handling 4.2 4.2.1 Reset Overview A reset has the highest exception handling priority. There are two kinds of reset: a power-on reset pin, and a manual reset executed via the pin. executed via the or pin* goes low, currently executing processing is halted and the chip When the enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. The reset state can also be entered in the event of watchdog timer overflow. For details see section 15, Watchdog Timer. 4.2.2 There are two types of reset: power-on reset and manual reset. Table 4.3 shows the types of reset. When turning power on, do so as a power-on reset. Both power-on reset and manual reset initialize the internal state of the CPU. In a power-on reset, all of the registers of the built-in vicinity modules are initialized, while in a manual reset, the registers of the built-in vicinity models except for bus controllers and I/O ports are initialized. The states of the bus controllers and I/O ports are maintained. During a manual reset built-in vicinity modules are initialized, and ports used as input pins for built-in vicinity modules switch to the input ports controlled by DDR and DR. If using manual reset, set the MRESE bit to 1 beforehand, thereby enabling manual resets. See section 3.2.2, System Control Register (SYSCR) for settings of the MRESE bit. There are also power-on resets and manual resets as the two types of reset carried out by the watchdog timer. Rev. 3.00 Jan 11, 2005 page 84 of 1220 REJ09B0186-0300O SERM Note: * pin in the case of a manual reset. Types of Reset SERM SER Reset exception handling starts when the or pin* changes from low to high. SERM SERM SER SER Section 4 Exception Handling Table 4.3 Types of Reset Conditions for Transition to Reset Internal State CPU Built-in vicinity module Power-on reset * Manual reset Low High 4.2.3 Reset Sequence When the pin or the pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows. 1. The internal state of the CPU and the registers of the on-chip supporting modules are initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4.2 and 4.3 show examples of the reset sequence. SERM SER To ensure that this LSI is reset, hold the pin or the during operation, hold the pin low for at least 20 ms at power-up. To reset pin low for at least 20 states. SERM SER This LSI enters reset state when the SER Low SERM SER SERM Type Initialization Initialization Initialization Initialization except for bus controller and I/O port *: Don't Care pin or pin goes low. SER Rev. 3.00 Jan 11, 2005 page 85 of 1220 REJ09B0186-0300O Section 4 Exception Handling Vector fetch Internal processing Prefetch of first program instruction * * * φ RES, MRES Address bus (1) (3) (5) RD HWR, LWR High D15 to D0 (2) (4) (6) (1) (3) Reset exception handling vector address (when power-on reset, (1) = H'000000*, (3) = H'000002; when manual reset, (1)= H'000004, (3)= H'000006) (2) (4) Start address (contents of reset exception handling vector address) (5) Start address ((5) = (2) (4)) (6) First program instruction Note: * Three program wait states are inserted. Figure 4.2 Reset Sequence (Modes 4 and 5) Rev. 3.00 Jan 11, 2005 page 86 of 1220 REJ09B0186-0300O Section 4 Exception Handling Prefetch of Internal first program processing instruction Vector fetch φ RES, MRES Internal address bus (1) (3) (5) Internal read signal Internal write signal Internal data bus (2) High (4) (6) (1) (3) Reset exception handling vector address (when power-on reset, (1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) (5) Start address ((5) = (2) (4)) (6) First program instruction Figure 4.3 Reset Sequence (Modes 6 and 7) 4.2.4 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 4.2.5 State of On-Chip Supporting Modules after Reset Release After reset release, MSTPCRA to MSTPCRC are initialized to H'3F, H'FF, and H'FF, respectively, and all modules except the DMAC and DTC, enter module stop mode. Consequently, on-chip supporting module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited. Rev. 3.00 Jan 11, 2005 page 87 of 1220 REJ09B0186-0300O Section 4 Exception Handling 4.3 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking. Table 4.4 shows the state of CCR and EXR after execution of trace exception handling. Interrupts are accepted even within the trace exception handling routine. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Table 4.4 Status of CCR and EXR after Trace Exception Handling CCR Interrupt Control Mode 0 2 1 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution. I UI I2 to I0 EXR T Trace exception handling cannot be used. — — 0 Rev. 3.00 Jan 11, 2005 page 88 of 1220 REJ09B0186-0300O Section 4 Exception Handling 4.4 Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 72 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), 16-bit timer-pulse unit (TPU), 8-bit timer, serial communication interface (SCI), data transfer controller (DTC), DMA controller (DMAC), PC break controller (PBC), A/D converter, and I2C bus interface (IIC). Each interrupt source has a separate vector address. NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. For details of interrupts, see section 5, Interrupt Controller. External interrupts NMI (1) IRQ7 to IRQ0 (8) Interrupts Internal interrupts WDT*1 (2) Refresh timer*2 (1) TPU (26) 8-bit timer (12) SCI (20) DTC (1) DMAC (4) PBC (1) A/D converter (1) IIC(4) (Option) Notes: Numbers in parentheses are the numbers of interrupt sources. 1. When the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. 2. When refresh timer is used as an interval time, an interrupt request is generated by compare match. Figure 4.4 Interrupt Sources and Number of Interrupts Rev. 3.00 Jan 11, 2005 page 89 of 1220 REJ09B0186-0300O Section 4 Exception Handling 4.5 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.5 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.5 Status of CCR and EXR after Trap Instruction Exception Handling CCR Interrupt Control Mode 0 2 I 1 1 UI — — I2 to I0 — — EXR T — 0 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution. Rev. 3.00 Jan 11, 2005 page 90 of 1220 REJ09B0186-0300O Section 4 Exception Handling 4.6 Stack Status after Exception Handling Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP SP CCR CCR* PC (16 bits) EXR Reserved* CCR CCR* PC (16 bits) (a) Interrupt control mode 0 Note: * Ignored on return. (b) Interrupt control mode 2 Figure 4.5 (a) Stack Status after Exception Handling (Normal Modes: Not Available in the H8S/2643 Group) SP SP CCR PC (24 bits) EXR Reserved* CCR PC (24 bits) (a) Interrupt control mode 0 Note: * Ignored on return. (b) Interrupt control mode 2 Figure 4.5 (b) Stack Status after Exception Handling (Advanced Modes) Rev. 3.00 Jan 11, 2005 page 91 of 1220 REJ09B0186-0300O Section 4 Exception Handling 4.7 Notes on Use of the Stack When accessing word data or longword data, the H8S/2643 Group assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.6 shows an example of what happens when the SP value is odd. CCR SP PC SP R1L PC H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFF SP TRAP instruction executed MOV.B R1L, @–ER7 SP set to H'FFFEFF Data saved above SP Contents of CCR lost Legend: CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4.6 Operation when SP Value is Odd Rev. 3.00 Jan 11, 2005 page 92 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 5.1.1 Overview Features The H8S/2643 Group controls interrupts by means of an interrupt controller. The interrupt controller has the following features. • Two interrupt control modes  Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with IPR  An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI.  NMI is assigned the highest priority level of 8, and can be accepted at all times. • Independent vector addresses  All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. • Nine external interrupts  NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI.  Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ7 to IRQ0. • DTC and DMAC control  DTC and DMAC activation is performed by means of interrupts. Rev. 3.00 Jan 11, 2005 page 93 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5.1. INTM1, INTM0 SYSCR NMIEG NMI input IRQ input NMI input unit IRQ input unit ISR ISCR IER Priority determination I I2 to I0 Interrupt request Vector number CPU Internal interrupt request SWDTEND to TEI4 IPR Interrupt controller CCR EXR Legend: ISCR: IER: ISR: IPR: SYSCR: IRQ sense control register IRQ enable register IRQ status register Interrupt priority register System control register Figure 5.1 Block Diagram of Interrupt Controller Rev. 3.00 Jan 11, 2005 page 94 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller 5.1.3 Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Name Nonmaskable interrupt External interrupt requests 7 to 0 Interrupt Controller Pins Symbol NMI 0QRI I/O Input Function Nonmaskable external interrupt; rising or falling edge can be selected Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected to Input 5.1.4 Register Configuration Table 5.2 summarizes the registers of the interrupt controller. Table 5.2 Name System control register IRQ sense control register H IRQ sense control register L IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt priority register I Interrupt priority register J Interrupt priority register K Interrupt priority register L Interrupt priority register O Interrupt Controller Registers Abbreviation SYSCR ISCRH ISCRL IER ISR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK IPRL IPRO R/W R/W R/W R/W R/W R/(W)*2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'01 H'00 H'00 H'00 H'00 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 Address*1 H'FDE5 H'FE12 H'FE13 H'FE14 H'FE15 H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECE Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. Rev. 3.00 Jan 11, 2005 page 95 of 1220 REJ09B0186-0300O 7QRI Section 5 Interrupt Controller 5.2 5.2.1 Bit Register Descriptions System Control Register (SYSCR) : 7 MACS 0 R/W 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 MRESE 0 R/W 1 — 0 — 0 RAME 1 R/W Initial value : R/W : SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control Register (SYSCR). SYSCR is initialized to H'01 by a power-on reset, manual reset, and in hardware standby mode. SYSCR is not initialized in software standby mode. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes for the interrupt controller. Bit 5 INTM1 0 1 Bit 4 INTM0 0 1 0 1 Interrupt Control Mode 0 — 2 — Description Interrupts are controlled by I bit Setting prohibited Interrupts are controlled by bits I2 to I0, and IPR Setting prohibited (Initial value) Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. Bit 3 NMIEG 0 1 Description Interrupt request generated at falling edge of NMI input Interrupt request generated at rising edge of NMI input (Initial value) Rev. 3.00 Jan 11, 2005 page 96 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller 5.2.2 Bit Interrupt Priority Registers A to L, O (IPRA to IPRL, IPRO) : 7 — 0 — 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W 3 — 0 — 2 IPR2 1 R/W 1 IPR1 1 R/W 0 IPR0 1 R/W Initial value : R/W : The IPR registers are thirteen 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between IPR settings and interrupt sources is shown in table 5.3. The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI. The IPR registers are initialized to H'77 by a reset and in hardware standby mode. Bits 7 and 3—Reserved: These bits are always read as 0 and cannot be modified. Table 5.3 Correspondence between Interrupt Sources and IPR Settings Bits Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK IPRL IPRO 6 to 4 IRQ0 IRQ2 IRQ3 IRQ6 IRQ7 Watchdog timer 0 PC break TPU channel 0 TPU channel 2 TPU channel 4 8-bit timer channel 0 DMAC SCI channel 1 8-bit timer 2, 3 SCI channel 3 2 to 0 IRQ1 IRQ4 IRQ5 DTC Refresh timer A/D converter, watchdog timer 1 TPU channel 1 TPU channel 3 TPU channel 5 8-bit timer channel 1 SCI channel 0 SCI channel 2 IIC (Option) SCI channel 4 Rev. 3.00 Jan 11, 2005 page 97 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority level, level 7, by setting H'7. When interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to the CPU. 5.2.3 Bit IRQ Enable Register (IER) : 7 IRQ7E 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W Initial value : R/W : IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ7 to IRQ0. IER is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to IRQ0 are enabled or disabled. Bit n IRQnE 0 1 Description IRQn interrupts disabled IRQn interrupts enabled (n = 7 to 0) (Initial value) Rev. 3.00 Jan 11, 2005 page 98 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller 5.2.4 ISCRH Bit IRQ Sense Control Registers H and L (ISCRH, ISCRL) : 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : R/W : ISCRL Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : R/W : The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or to . both edge detection, or level sensing, for the input at pins The ISCR registers are initialized to H'0000 by a reset and in hardware standby mode. They are not initialized in software standby mode. Bits 15 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB) Bits 15 to 0 IRQ7SCB to IRQ0SCB 0 IRQ7SCA to IRQ0SCA 0 1 1 0 1 Description 0QRI 7QRI Interrupt request generated at Interrupt request generated at both falling and rising edges of to input 0QRI 7QRI Rev. 3.00 Jan 11, 2005 page 99 of 1220 REJ09B0186-0300O 0QRI 7QRI Interrupt request generated at rising edge of to 0QRI 7QRI Interrupt request generated at falling edge of 0QRI 7QRI to input low level (initial value) to input input Section 5 Interrupt Controller 5.2.5 Bit IRQ Status Register (ISR) : 7 IRQ7F 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* Initial value : R/W : Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0—IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests. Bit n IRQnF 0 Description [Clearing conditions] • • • • 1 (Initial value) Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag W hen interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and input is high W hen IRQn interrupt exception handling is executed when falling, rising, or bothedge detection is set (IRQnSCB = 1 or IRQnSCA = 1) W hen the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 W hen 0) input goes low when low-level detection is set (IRQnSCB = IRQnSCA = input when falling edge detection is set input when rising edge detection is set input when both-edge detection is set (n = 5 to 0) nQRI [Setting conditions] nQRI • • • • Rev. 3.00 Jan 11, 2005 page 100 of 1220 REJ09B0186-0300O nQRI W hen a falling or rising edge occurs in (IRQnSCB = IRQnSCA = 1) nQRI W hen a rising edge occurs in (IRQnSCB = 1, IRQnSCA = 0) nQRI W hen a falling edge occurs in (IRQnSCB = 0, IRQnSCA = 1) Section 5 Interrupt Controller 5.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (72 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ7 to IRQ0 can be used to restore the H8S/2643 Group from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. The vector number for NMI interrupt exception handling is 7. 7QRI IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins to . Interrupts IRQ5 to IRQ0 have the following features: 0QRI • Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling to . edge, rising edge, or both edges, at pins • Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER. • The interrupt priority level can be set with IPR. • The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.2. 0QRI 7QRI Rev. 3.00 Jan 11, 2005 page 101 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input Clear signal Note: n = 7 to 0 IRQn interrupt S R Q request Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0 Figure 5.3 shows the timing of setting IRQnF. φ IRQn input pin IRQnF Figure 5.3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as an I/O pin for another function. 5.3.2 Internal Interrupts There are 72 sources for internal interrupts from on-chip supporting modules. • For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. Rev. 3.00 Jan 11, 2005 page 102 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller • The interrupt priority level can be set by means of IPR. • The DMAC and DTC can be activated by a TPU, 8-bit timer, SCI, or other interrupt request. When the DMAC and DTC are activated by an interrupt, the interrupt control mode and interrupt mask bits are not affected. 5.3.3 Interrupt Exception Handling Vector Table Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of the IPR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5.4. Rev. 3.00 Jan 11, 2005 page 103 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address* Vector Number 7 16 17 18 19 20 21 22 23 DTC Watchdog timer 0 Refresh timer PC break A/D Watchdog timer 1 — TPU channel 0 24 25 26 27 28 29 30 31 32 33 34 35 36 — 37 38 39 Advanced Mode H'001C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C H'0060 H'0064 H'0068 H'006C H'0070 H'0074 H'0078 H'007C H'0080 H'0084 H'0088 H'008C H'0090 H'0094 H'0098 H'009C IPRF6 to 4 IPRA6 to 4 IPRA2 to 0 IPRB6 to 4 IPRB2 to 0 IPRC6 to 4 IPRC2 to 0 IPRD6 to 4 IPRD2 to 0 IPRE6 to 4 IPRE2 to 0 IPR Priority High Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 SWDTEND (software activation interrupt end) WOVI0 (interval timer) CMI PC break ADI (A/D conversion end) WOVI1 (interval timer) Reserved TGI0A (TGR0A input capture/compare match) TGI0B (TGR0B input capture/compare match) TGI0C (TGR0C input capture/compare match) TGI0D (TGR0D input capture/compare match) TCI0V (overflow 0) Reserved Origin of Interrupt Source External pin Low Rev. 3.00 Jan 11, 2005 page 104 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller Vector Address* Vector Number 40 41 42 43 TPU channel 2 44 45 46 47 TPU channel 3 48 49 50 51 52 — 53 54 55 56 57 58 59 TPU channel 5 60 61 62 63 Advanced Mode H'00A0 H'00A4 H'00A8 H'00AC H'00B0 H'00B4 H'00B8 H'00BC H'00C0 H'00C4 H'00C8 H'00CC H'00D0 H'00D4 H'00D8 H'00DC H'00E0 H'00E4 H'00E8 H'00EC H'00F0 H'00F4 H'00F8 H'00FC IPRH2 to 0 IPRH6 to 4 IPRG2 to 0 IPRG6 to 4 IPR IPRF2 to 0 Priority High Interrupt Source TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow 2) TCI2U (underflow 2) TGI3A (TGR3A input capture/compare match) TGI3B (TGR3B input capture/compare match) TGI3C (TGR3C input capture/compare match) TGI3D (TGR3D input capture/compare match) TCI3V (overflow 3) Reserved Origin of Interrupt Source TPU channel 1 TGI4A (TGR4A input capture/compare match) TGI4B (TGR4B input capture/compare match) TCI4V (overflow 4) TCI4U (underflow 4) TGI5A (TGR5A input capture/compare match) TGI5B (TGR5B input capture/compare match) TCI5V (overflow 5) TCI5U (underflow 5) TPU channel 4 Low Rev. 3.00 Jan 11, 2005 page 105 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller Vector Address* Vector Number 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Advanced Mode H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011C H'0120 H'0124 H'0128 H'012C H'0130 H'0134 H'0138 H'013C H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C IPRJ2 to 0 IPRI2 to 0 IPR IPRI6 to 4 Priority High Interrupt Source CMIA0 (compare match A0) CMIB0 (compare match B0) OVI0 (overflow 0) Reserved CMIA1 (compare match A1) CMIB1 (compare match B1) OVI1 (overflow 1) Origin of Interrupt Source 8-bit timer channel 0 — 8-bit timer channel 1 Reserved — DED0A (channel 0/channel 0A DMAC transfer end) DEND0B (channel 0B transfer end) DEND1A (channel 1/channel 1A transfer end) DEND1B (channel 1B transfer end) Reserved — IPRJ6 to 4 ERI0 (receive error 0) RXI0 (reception completed 0) TXI0 (transmit data empty 0) TEI0 (transmission end 0) ERI1 (receive error 1) RXI1 (reception completed 1) TXI1 (transmit data empty 1) TEI1 (transmission end 1) ERI2 (receive error 2) RXI2 (reception completed 2) TXI2 (transmit data empty 2) TEI2 (transmission end 2) SCI channel 0 SCI channel 1 IPRK6 to 4 SCI channel 2 IPRK2 to 0 Low Rev. 3.00 Jan 11, 2005 page 106 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller Vector Address* Vector Number 92 93 94 95 96 97 98 99 Advanced Mode H'0170 H'0174 H'0178 H'017C H'0180 H'0184 H'0188 H'018C H'0190 H'0194 H'0198 H'019C H'01A0 H'01A4 H'01A8 H'01AC H'01B0 H'01B4 H'01B8 H'01BC H'01C0 H'01C4 H'01C8 H'01CC H'01D0 H'01D4 H'01D8 H'01DC H'01E0 H'01E4 H'01E8 H'01EC H'01F0 H'01F4 H'01F8 H'01FC IPRM6 to 4 IPRL2 to 0 IPR IPRL6 to 4 Priority High Interrupt Source CMIA0 (compare match A2) CMIB0 (compare match B2) OVI0 (overflow 2) Reserved CMIA1 (compare match A3) CMIB1 (compare match B3) OVI1 (overflow 3) Reserved IICI0 (1 byte transmission/reception completed) DDCSW1 (format switch) IICI1 (1 byte transmission/reception completed) Reserved Reserved Origin of Interrupt Source 8 bit timer channel 2 — 8 bit timer channel 3 — IIC channel 100 0 (optional) 101 IIC channel 102 1 (optional) 103 — 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 Reserved — IPRM2 to 0 Reserved — IPRN6 to 4 Reserved — IPRN2 to 0 ERI3 (reception error 3) RXI3 (reception completed 3) TXI3 (transmission data empty 3) TEI3 (transmission end 3) ERI4 (reception error 4) RXI4 (reception completed 4) TXI4 (transmission data empty 4) TEI4 (transmission end 4) SCI channel 3 IPRO6 to 4 SCI channel 4 IPRO2 to 0 Low Note: * Lower 16 bits of the start address. Rev. 3.00 Jan 11, 2005 page 107 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller 5.4 5.4.1 Interrupt Operation Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2643 Group differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 5.5 shows the interrupt control modes. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated by the I and UI bits in the CPU’s CCR, and bits I2 to I0 in EXR. Table 5.5 Interrupt Control Modes Interrupt Mask Bits Description I — I2 to I0 Interrupt mask control is performed by the I bit. Setting prohibited 8-level interrupt mask control is performed by bits I2 to I0. 8 priority levels can be set with IPR. Setting prohibited SYSCR Interrupt Priority Setting Control Mode INTM1 INTM0 Registers 0 — 2 1 0 0 1 0 — — IPR — 1 — — Rev. 3.00 Jan 11, 2005 page 108 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller Figure 5.4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 I Interrupt acceptance control Interrupt source Default priority determination 8-level mask control Vector number IPR I2 to I0 Interrupt control mode 2 Figure 5.4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5.6 shows the interrupts selected in each interrupt control mode. Table 5.6 Interrupts Selected in Each Interrupt Control Mode (1) Interrupt Mask Bits Interrupt Control Mode 0 2 I 0 1 * Selected Interrupts All interrupts NMI interrupts All interrupts *: Don't care Rev. 3.00 Jan 11, 2005 page 109 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller (2) 8-Level Control In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level. Table 5.7 Interrupts Selected in Each Interrupt Control Mode (2) Selected Interrupts All interrupts Highest-priority-level (IPR) interrupt whose priority level is greater than the mask level (IPR > I2 to I0). Interrupt Control Mode 0 2 (3) Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Rev. 3.00 Jan 11, 2005 page 110 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller Table 5.8 shows operations and control signal functions in each interrupt control mode. Table 5.8 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Acceptance Control I 8-Level Control I2 to I0 IPR 2 Interrupt Control Setting Mode INTM1 INTM0 Default Priority Determination T (Trace) 0 2 Legend: O: 0 1 0 0 O X IM —* 1 X — —* PR O O — T O IM Interrupt operation control performed. X: No operation (All interrupts enabled). IM: Used as interrupt mask bit PR: Sets priority. —: Not used. Notes: 1. Set to 1 when interrupt is accepted. 2. Keep the initial setting. 5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. [3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. Rev. 3.00 Jan 11, 2005 page 111 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller Program execution status Interrupt generated? Yes Yes No NMI No No I=0 Yes Hold pending No IRQ0 Yes No IRQ1 Yes TEI4 Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 3.00 Jan 11, 2005 page 112 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller 5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5.6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.4 is selected. [3] Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. Rev. 3.00 Jan 11, 2005 page 113 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller Program execution status Interrupt generated? Yes Yes NMI No No No Level 7 interrupt? Yes Mask level 6 or below? Yes Level 6 interrupt? No Yes Mask level 5 or below? Yes No Level 1 interrupt? No Yes No Mask level 0? Yes No Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev. 3.00 Jan 11, 2005 page 114 of 1220 REJ09B0186-0300O 5.4.4 Interrupt acceptance Interrupt level determination Wait for end of instruction Stack Vector fetch Internal operation Instruction prefetch Internal operation Interrupt service routine instruction prefetch φ Interrupt request signal Internal address bus (1) (7) (9) (3) (5) (11) (13) Interrupt Exception Handling Sequence Internal read signal Internal write signal Internal data us (2) (4) (6) (8) (10) (12) (14) Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Figure 5.7 Interrupt Exception Handling (1) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address) (2) (4) Instruction code (Not executed) (3) Instruction prefetch address (Not executed) (5) SP-2 (7) SP-4 Section 5 Interrupt Controller Rev. 3.00 Jan 11, 2005 page 115 of 1220 REJ09B0186-0300O (6) (8) Saved PC and saved CCR (9) (11) Vector address (10) (12) Interrupt handling routine start address (vector address contents) (13) Interrupt handling routine start address ((13) = (10) (12)) (14) First instruction of interrupt handling routine Section 5 Interrupt Controller 5.4.5 Interrupt Response Times The H8S/2643 Group is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling highspeed processing. Table 5.9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.9 are explained in table 5.10. Table 5.9 Interrupt Response Times Normal Mode*5 No. 1 2 3 4 5 6 Execution Status Interrupt priority determination* 1 Advanced Mode INTM1 = 0 3 1 to (19 + 2·SI) 2·SK 2·SI 2·SI 2 12 to 32 INTM1 = 1 3 1 to (19 + 2·SI) 3·SK 2·SI 2·SI 2 13 to 33 INTM1 = 0 3 INTM1 = 1 3 1 to (19 + 2·SI) 3·SK SI 2·SI 2 12 to 32 Number of wait states until executing 1 to instruction ends*2 (19 + 2·SI) PC, CCR, EXR stack save Vector fetch Instruction fetch* 3 4 2·SK SI 2·SI 2 11 to 31 Internal processing* Total (using on-chip memory) Notes: 1. 2. 3. 4. 5. Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Not available in the H8S/2643 Group. Rev. 3.00 Jan 11, 2005 page 116 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller Table 5.10 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8 Bit Bus Symbol Instruction fetch Branch address read Stack manipulation SI SJ SK Internal Memory 1 2-State Access 4 3-State Access 6 + 2m 16 Bit Bus 2-State Access 2 3-State Access 3+m Legend: m: Number of wait states in an external device access. 5.5 5.5.1 Usage Notes Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.8 shows an example in which the CMIEA bit in the TMR’s TCR register is cleared to 0. Rev. 3.00 Jan 11, 2005 page 117 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller TCR write cycle by CPU CMIA exception handling φ Internal address bus TCR address Internal write signal CMIEA CMFA CMIA interrupt signal Figure 5.8 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 5.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.5.3 Times when Interrupts are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. Rev. 3.00 Jan 11, 2005 page 118 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller 5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 5.5.5 IRQ Interrupt When operating by clock input, acceptance of input to an IRQ is synchronized with the clock. In software standby mode, the input is accepted asynchronously. For details on the input conditions, see section 25.3.2, Control Signal Timing. 5.5.6 NMI Interrupt Usage Notes The NMI interrupt is part of the exception processing performed cooperatively by the LSI’s internal interrupt controller and the CPU when the system is operating normally under the specified electrical conditions. No operations, including NMI interrupts, are guaranteed when operation is not normal (runaway status) due to software problems or abnormal input to the LSI’s pins. In such cases, the LSI may be restored to the normal program execution state by applying an external reset. Rev. 3.00 Jan 11, 2005 page 119 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller 5.6 5.6.1 DTC and DMAC Activation by Interrupt Overview The DTC and DMAC can be activated by an interrupt. In this case, the following options are available: • • • • Interrupt request to CPU Activation request to DTC Activation request to DMAC Selection of a number of the above For details of interrupt requests that can be used with to activate the DTC and DMAC, see section 9, Data Transfer Controller and section 8, DMA Controller. 5.6.2 Block Diagram Figure 5.9 shows a block diagram of the DTC interrupt controller. DMAC Clear signal Disenable signal Interrupt request IRQ interrupt Interrupt source clear signal Selection circuit Select signal Clear signal DTCER DTC activation request vector number Control logic Clear signal DTC On-chip supporting module DTVECR SWDTE clear signal Determination of priority Interrupt controller CPU interrupt request vector number CPU I, I2 to I0 Figure 5.9 Interrupt Control for DTC and DMAC Rev. 3.00 Jan 11, 2005 page 120 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller 5.6.3 Operation The interrupt controller has three main functions in DTC and DMAC control. (1) Selection of Interrupt Source DMAC inputs activation factor directly to each channel. The activation factors for each channel of DMAC are selected by DTF3 to DTF0 bits of DMACR. The DTA bit of DMABCR can be used to select whether the selected activation factors are managed by DMAC. By setting the DTA bit to 1, the interrupt factor which were the activation factor for that DMAC do not act as the DTC activation factor or the CPU interrupt factor. Interrupt factors other than the interrupts managed by the DMAC are selected as DTC activation request or CPU interrupt request by the DTCERA to DTCERF of DTC and the DTCE bit of DTCERI. By specifying the DISEL bit of the DTC's MRB, it is possible to clear the DTCE bit to 0 after DTC data transfer, and request a CPU interrupt. If DTC carries out the designate number of data transfers and the transfer counter reads 0, after DTC data transfer, the DTCE bit is also cleared to 0, and a CPU interrupt requested. (2) Determination of Priority The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See sections 8.6, Interrupts and 9.3.3, DTC Vector Table for the respective priority. (3) Operation Order If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. If the same interrupt is selected as the DMAC activation factor and as the DTC activation factor or CPU interrupt factor, these operate independently. They operate in accordance with the respective operating states and bus priorities. Table 5.11 shows the interrupt factor clear control and selection of interrupt factors by specification of the DTA bit of DMAC's DMABCR, DTC's DTCERA to DTCERF, DTCERI's DTCE bits, and the DISEL bit of DTC's MRB. Rev. 3.00 Jan 11, 2005 page 121 of 1220 REJ09B0186-0300O Section 5 Interrupt Controller Table 5.11 Interrupt Source Selection and Clearing Control Settings DMAC DTA 0 DTCE 0 1 DTC DISEL * 0 1 1 * * Interrupt Source Selection/Clearing Control DMAC O O O DTC × CPU ∆ × ∆ O × ∆ × ∆ Legend: ∆ : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) O : The relevant interrupt is used. The interrupt source is not cleared. × : The relevant bit cannot be used. * : Don’t care (4) Notes on Use SCI and A/D converter interrupt sources are cleared when the DMAC or DTC reads or writes to the prescribed register, and are not dependent upon the DTA, DTCE, and DISEL bits. Rev. 3.00 Jan 11, 2005 page 122 of 1220 REJ09B0186-0300O Section 6 PC Break Controller (PBC) Section 6 PC Break Controller (PBC) 6.1 Overview The PC break controller (PBC) provides functions that simplify program debugging. Using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. Four break conditions can be set in the PBC: instruction fetch, data read, data write, and data read/write. 6.1.1 Features The PC break controller has the following features. • Two break channels (A and B) • The following can be set as break compare conditions  24 address bits Bit masking possible  Bus cycle Instruction fetch Data access: data read, data write, data read/write  Bus master Either CPU or CPU/DTC can be selected • The timing of PC break exception handling after the occurrence of a break condition is as follows  Immediately before execution of the instruction fetched at the set address (instruction fetch)  Immediately after execution of the instruction that accesses data at the set address (data access) • Module stop mode can be set  The initial setting is for PBC operation to be halted. Register access is enabled by clearing module stop mode. Rev. 3.00 Jan 11, 2005 page 123 of 1220 REJ09B0186-0300O Section 6 PC Break Controller (PBC) 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the PC break controller. BARA BCRA Mask control Comparator Match signal Internal address Access status Control logic Output control PC break interrupt Comparator Match signal Control logic Mask control BARB BCRB Figure 6.1 Block Diagram of PC Break Controller Rev. 3.00 Jan 11, 2005 page 124 of 1220 REJ09B0186-0300O Output control Section 6 PC Break Controller (PBC) 6.1.3 Register Configuration Table 6.1 shows the PC break controller registers. Table 6.1 PC Break Controller Registers Initial Value Name Break address register A Break address register B Break control register A Break control register B Module stop control register C Abbreviation BARA BARB BCRA BCRB MSTPCRC R/W R/W R/W R/(W)* R/(W)* R/W 2 2 Power-On Reset Manual Reset Address*1 H'FE00 H'FE04 H'FE08 H'FE09 H'FDEA H'XX000000 Retained H'XX000000 Retained H'00 H'00 H'FF Retained Retained Retained Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written, for flag clearing. 6.2 6.2.1 Bit Register Descriptions Break Address Register A (BARA) : 31 — ••• 24 23 22 21 20 19 18 17 16 ••• 7 6 5 4 3 2 1 0 ••• BAA BAA BAA BAA BAA BAA BAA BAA — 23 22 21 20 19 18 17 16 Unde- 0 0 0 0 0 0 0 0 fined — R/W R/W R/W R/W R/W R/W R/W R/W ••• BAA BAA BAA BAA BAA BAA BAA BAA 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Initial value : Undefined R/W :— ••• ••• ••• ••• R/W R/W R/W R/W R/W R/W R/W R/W BARA is a 32-bit readable/writable register that specifies the channel A break address. BAA23 to BAA0 are initialized to H'000000 by a power-on reset and in hardware standby mode. Bits 31 to 24—Reserved: These bits return an undefined value if read, and cannot be modified. Bits 23 to 0—Break Address A23 to A0 (BAA23 to BAA0): These bits hold the channel A PC break address. Rev. 3.00 Jan 11, 2005 page 125 of 1220 REJ09B0186-0300O Section 6 PC Break Controller (PBC) 6.2.2 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 6.2.3 Bit Break Control Register A (BCRA) : 7 CMFA 6 CDA 0 R/W 5 4 3 2 1 0 BIEA 0 R/W BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value : R/W 0 : R/(W)* Note: * Only 0 can be written, for flag clearing. BCRA is an 8-bit readable/writable register that controls channel A PC breaks. BCRA (1) selects the break condition bus master, (2) specifies bits subject to address comparison masking, and (3) specifies whether the break condition is applied to an instruction fetch or a data access. It also contains a condition match flag. BCRA is initialized to H'00 by a power-on reset and in hardware standby mode. Bit 7—Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is satisfied. This flag is not cleared to 0. Bit 7 CMFA 0 1 Description [Clearing condition] • • W hen 0 is written to CMFA after reading CMFA = 1 W hen a condition set for channel A is satisfied (Initial value) [Setting condition] Bit 6—CPU Cycle/DTC Cycle Select A (CDA): Selects the channel A break condition bus master. Bit 6 CDA 0 1 Description PC break is performed when CPU is bus master PC break is performed when CPU or DTC is bus master (Initial value) Rev. 3.00 Jan 11, 2005 page 126 of 1220 REJ09B0186-0300O Section 6 PC Break Controller (PBC) Bits 5 to 3—Break Address Mask Register A2 to A0 (BAMRA2 to BAMRA0): These bits specify which bits of the break address (BAA23 to BAA0) set in BARA are to be masked. Bit 5 Bit 4 Bit 3 BAMRA2 BAMRA1 BAMRA0 Description 0 0 0 1 1 0 1 1 0 0 1 1 0 1 All BARA bits are unmasked and included in break conditions (Initial value) BAA0 (lowest bit) is masked, and not included in break conditions BAA1 to 0 (lower 2 bits) are masked, and not included in break conditions BAA2 to 0 (lower 3 bits) are masked, and not included in break conditions BAA3 to 0 (lower 4 bits) are masked, and not included in break conditions BAA7 to 0 (lower 8 bits) are masked, and not included in break conditions BAA11 to 0 (lower 12 bits) are masked, and not included in break conditions BAA15 to 0 (lower 16 bits) are masked, and not included in break conditions Bits 2 and 1—Break Condition Select A (CSELA1, CSELA0): These bits selection an instruction fetch, data read, data write, or data read/write cycle as the channel A break condition. Bit 2 CSELA1 0 1 Bit 1 CSELA0 0 1 0 1 Description Instruction fetch is used as break condition Data read cycle is used as break condition Data write cycle is used as break condition Data read/write cycle is used as break condition (Initial value) Bit 0—Break Interrupt Enable A (BIEA): Enables or disables channel A PC break interrupts. Bit 0 BIEA 0 1 Description PC break interrupts are disabled PC break interrupts are enabled Rev. 3.00 Jan 11, 2005 page 127 of 1220 REJ09B0186-0300O (Initial value) Section 6 PC Break Controller (PBC) 6.2.4 Break Control Register B (BCRB) BCRB is the channel B break control register. The bit configuration is the same as for BCRA. 6.2.5 Bit Module Stop Control Register C (MSTPCRC) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : R/W : MSTPCRC is an 8-bit readable/writable register that performs module stop mode control. When the MSTPC4 bit is set to 1, PC break controller operation is stopped at the end of the bus cycle, and module stop mode is entered. Register read/write accesses are not possible in module stop mode. For details, see section 24.5, Module Stop Mode. MSTPCRC is initialized to H'FF by a power on reset and in hardware standby mode. It is not initialized by a manual reset and in software standby mode. Bit 4—Module Stop (MSTPC4): Specifies the PC break controller module stop mode. Bit 4 MSTPC4 0 1 Description PC break controller module stop mode is cleared PC break controller module stop mode is set (Initial value) 6.3 Operation The operation flow from break condition setting to PC break interrupt exception handling is shown in sections 6.3.1, PC Break Interrupt Due to Instruction Fetch, and 6.3.2, PC Break Interrupt Due to Data Access, taking the example of channel A. 6.3.1 PC Break Interrupt Due to Instruction Fetch (1) Initial settings  Set the break address in BARA. For a PC break caused by an instruction fetch, set the address of the first instruction byte as the break address. Rev. 3.00 Jan 11, 2005 page 128 of 1220 REJ09B0186-0300O Section 6 PC Break Controller (PBC)  Set the break conditions in BCRA. BCRA bit 6 (CDA): With a PC break caused by an instruction fetch, the bus master must be the CPU. Set 0 to select the CPU. BCRA bits 5 to 3 (BAMA2 to 0): Set the address bits to be masked. BCRA bits 2 and 1 (CSELA1 and 0): Set 00 to specify an instruction fetch as the break condition. BCRA bit 0 (BIEA): Set to 1 to enable break interrupts. (2) Satisfaction of break condition  When the instruction at the set address is fetched, a PC break request is generated immediately before execution of the fetched instruction, and the condition match flag (CMFA) is set. (3) Interrupt handling  After priority determination by the interrupt controller, PC break interrupt exception handling is started. 6.3.2 PC Break Interrupt Due to Data Access (1) Initial settings  Set the break address in BARA. For a PC break caused by a data access, set the target ROM, RAM, I/O, or external address space address as the break address. Stack operations and branch address reads are included in data accesses.  Set the break conditions in BCRA. BCRA bit 6 (CDA): Select the bus master. BCRA bits 5 to 3 (BAMA2 to 0): Set the address bits to be masked. BCRA bits 2 and 1 (CSELA1 and 0): Set 01, 10, or 11 to specify data access as the break condition. BCRA bit 0 (BIEA): Set to 1 to enable break interrupts. (2) Satisfaction of break condition  After execution of the instruction that performs a data access on the set address, a PC break request is generated and the condition match flag (CMFA) is set. (3) Interrupt handling  After priority determination by the interrupt controller, PC break interrupt exception handling is started. Rev. 3.00 Jan 11, 2005 page 129 of 1220 REJ09B0186-0300O Section 6 PC Break Controller (PBC) 6.3.3 Notes on PC Break Interrupt Handling (1) The PC break interrupt is shared by channels A and B. The channel from which the request was issued must be determined by the interrupt handler. (2) The CMFA and CMFB flags are not cleared to 0, so 0 must be written to CMFA or CMFB after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt will be requested after interrupt handling ends. (3) A PC break interrupt generated when the DTC is the bus master is accepted after the bus has been transferred to the CPU by the bus controller. 6.3.4 Operation in Transitions to Power-Down Modes The operation when a PC break interrupt is set for an instruction fetch at the address after a SLEEP instruction is shown below. (1) When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to sleep mode, or from subactive mode to subsleep mode After execution of the SLEEP instruction, a transition is not made to sleep mode or subsleep mode, and PC break interrupt handling is executed. After execution of PC break interrupt handling, the instruction at the address after the SLEEP instruction is executed (figure 6.2 (A)). (2) When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to subactive mode After execution of the SLEEP instruction, a transition is made to subactive mode via direct transition exception handling. After the transition, PC break interrupt handling is executed, then the instruction at the address after the SLEEP instruction is executed (figure 6.2 (B)). (3) When the SLEEP instruction causes a transition from subactive mode to high-speed (mediumspeed) mode After execution of the SLEEP instruction, and following the clock oscillation settling time, a transition is made to high-speed (medium-speed) mode via direct transition exception handling. After the transition, PC break interrupt handling is executed, then the instruction at the address after the SLEEP instruction is executed (figure 6.2 (C)). (4) When the SLEEP instruction causes a transition to software standby mode or watch mode After execution of the SLEEP instruction, a transition is made to the respective mode, and PC break interrupt handling is not executed. However, the CMFA or CMFB flag is set (figure 6.2 (D)). Rev. 3.00 Jan 11, 2005 page 130 of 1220 REJ09B0186-0300O Section 6 PC Break Controller (PBC) SLEEP instruction execution SLEEP instruction execution SLEEP instruction execution SLEEP instruction execution PC break exception handling System clock → subclock Subclock → system clock, oscillation settling time Transition to respective mode (D) Execution of instruction after sleep instruction (A) Direct transition exception handling Subactive mode Direct transition exception handling High-speed (medium-speed) mode PC break exception handling PC break exception handling Execution of instruction after sleep instruction (B ) Execution of instruction after sleep instruction (C ) Figure 6.2 Operation in Power-Down Mode Transitions 6.3.5 PC Break Operation in Continuous Data Transfer If a PC break interrupt is generated when the following operations are being performed, exception handling is executed on completion of the specified transfer. (1) When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction PC break exception handling is executed after all data transfers have been completed and the EEPMOV.B instruction has ended. (2) When a PC break interrupt is generated at a DTC transfer address PC break exception handling is executed after the DTC has completed the specified number of data transfers, or after data for which the DISEL bit is set to 1 has been transferred. 6.3.6 When Instruction Execution is Delayed by One State Caution is required in the following cases, as instruction execution is one state later than usual. (1) When the PBC is enabled (i.e. when the break interrupt enable bit is set to 1), execution of a one-word branch instruction (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, or RTS) located in onchip ROM or RAM is always delayed by one state. (2) When break interruption by instruction fetch is set, the set address indicates on-chip ROM or RAM space, and that address is used for data access, the instruction that executes the data access is one state later than in normal operation. Rev. 3.00 Jan 11, 2005 page 131 of 1220 REJ09B0186-0300O Section 6 PC Break Controller (PBC) (3) When break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction has one of the addressing modes shown below, and that address indicates on-chip ROM or RAM, and that address is used for data access, the instruction will be one state later than in normal operation. @ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24, @aa:32, @(d:8,PC), @(d:16,PC), @@aa:8 (4) When break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction is NOP or SLEEP, or has #xx,Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the instruction will be one state later than in normal operation. 6.3.7 Additional Notes (1) When a PC break is set for an instruction fetch at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the instruction fetch at the next address. (2) When the I bit is set by an LDC, ANDC, ORC, or XORC instruction A PC break interrupt becomes valid two states after the end of the executing instruction. If a PC break interrupt is set for the instruction following one of these instructions, since interrupts, including NMI, are disabled for a 3-state period in the case of LDC, ANDC, ORC, and XORC, the next instruction is always executed. For details, see section 5, Interrupt Controller. (3) When a PC break is set for an instruction fetch at the address following a Bcc instruction A PC break interrupt is generated if the instruction at the next address is executed in accordance with the branch condition, but is not generated if the instruction at the next address is not executed. (4) When a PC break is set for an instruction fetch at the branch destination address of a Bcc instruction A PC break interrupt is generated if the instruction at the branch destination is executed in accordance with the branch condition, but is not generated if the instruction at the branch destination is not executed. Rev. 3.00 Jan 11, 2005 page 132 of 1220 REJ09B0186-0300O Section 7 Bus Controller Section 7 Bus Controller 7.1 Overview The H8S/2643 Group has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU, DMA controller (DMAC), and data transfer controller (DTC). 7.1.1 Features The features of the bus controller are listed below. • Manages external address space in area units  Manages the external space as 8 areas of 2-Mbytes  Bus specifications can be set independently for each area  DRAM/Burst ROM interface can be set • Basic bus interface to ) can be output for areas 0 to 7  Chip selects (  8-bit access or 16-bit access can be selected for each area  2-state access or 3-state access can be selected for each area  Program wait states can be inserted for each area • DRAM interface  DRAM interface can be set for areas 2 to 5 (in advanced mode)  Multiplexed output of row and column addresses (8/9/10-bit)  2 CAS method  Burst operation (in high-speed mode)  Insertion of TP cycle to secure RAS precharge time  Selection of CAS-before-RAS refresh and self refresh • Burst ROM interface  Burst ROM interface can be set for area 0  Choice of 1- or 2-state burst access 7SC 0SC Rev. 3.00 Jan 11, 2005 page 133 of 1220 REJ09B0186-0300O Section 7 Bus Controller • Idle cycle insertion  An idle cycle can be inserted in case of an external read cycle between different areas  An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle • Write buffer functions  External write cycle and internal access can be executed in parallel  DMAC single-address mode and internal access can be executed in parallel • Bus arbitration function  Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC and DTC • Other features  Refresh counter (refresh timer) can be used as an interval timer  External bus release function Rev. 3.00 Jan 11, 2005 page 134 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.1.2 Block Diagram Figure 7.1 shows a block diagram of the bus controller. CS0 to CS7 Area decoder Internal address bus ABWCR External bus control signals ASTCR BCRH BCRL BREQ BACK BREQO Bus controller Internal data bus Internal control signals Bus mode signal WAIT Wait controller WCRH WCRL DRAM controller MCR External DRAM control signal DRAMCR RTCNT RTCOR CPU bus request signal DTC bus request signal Bus arbiter DMAC bus request signal CPU bus acknowledge signal DTC bus acknowledge signal DMAC bus acknowledge signal Legend: ABWCR: ASTCR: BCRH: BCRL: WCRH: WCRL: Bus width control register Access state control register Bus control register H Bus control register L Wait control register H Wait control register L MCR: Memory control register DRAMCR: DRAM control register RTCNT: Refresh timer counter RTCOR: Refresh time constand register Figure 7.1 Block Diagram of Bus Controller Rev. 3.00 Jan 11, 2005 page 135 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.1.3 Pin Configuration Table 7.1 summarizes the pins of the bus controller. Table 7.1 Name Address strobe Read High write/ write enable Low write Bus Controller Pins Symbol I/O Output Output Output Function Strobe signal indicating that address output on address bus is enabled. Strobe signal indicating that external space is being read. Strobe signal indicating that external space is to be written, and upper half (D15 to D8) of data bus is enabled. Strobe signal indicating that external space is to be written, and lower half (D7 to D0) of data bus is enabled. Strobe signal showing selection of area 0 Strobe signal showing selection of area 1 Strobe signal showing selection of area 2. When area 2 is allocated to DRAM space, this is the row address strobe signal for DRAM. When areas 2 to 5 are contiguous DRAM space, this is the row address strobe signal for DRAM. Strobe signal showing selection of area 3. When area 3 is allocated to DRAM space, this is the row address strobe signal for DRAM. When only area 2 is allocated to DRAM space, or when areas 2 to 5 are contiguous DRAM space, this is output enable signal. Strobe signal showing selection of area 4. When area 4 is allocated to DRAM space, this is the row address strobe signal for DRAM. Strobe signal showing selection of area 5. When area 5 is allocated to DRAM space, this is the row address strobe signal for DRAM. Strobe signal showing selection of area 6. Strobe signal showing selection of area 7. 2 CAS method DRAM upper column address strobe signal DRAM lower column address strobe signal Chip select 1 Chip select 2/row address strobe 2 Chip select 7 Upper column address strobe Lower column strobe Rev. 3.00 Jan 11, 2005 page 136 of 1220 REJ09B0186-0300O SACL SAC 7SC 6SC Chip select 6 5SC Chip select 5/row address strobe 5 4SC Chip select 4/row address strobe 4 EO 3SC Chip select 3/row address strobe 3 2SC 1SC 0SC Chip select 0 RWH RWL DR / SA Output Output Output Output Output Output Output Output Output Output Output Section 7 Bus Controller Name Wait Bus request Bus request acknowledge Bus request output Symbol I/O Input Input Output Output Function Wait request signal when accessing external 3-state access space. Request signal that releases bus to external device. Acknowledge signal indicating that bus has been released. External bus request signal used when internal bus master accesses external space when external bus is released. 7.1.4 Register Configuration Table 7.2 summarizes the registers of the bus controller. Table 7.2 Bus Controller Registers Initial Value Name Bus width control register Access state control register Wait control register H Wait control register L Bus control register H Bus control register L Pin function control register Memory control register DRAM control register Refresh timer counter Refresh time constant register Abbreviation ABWCR ASTCR WCRH WCRL BCRH BCRL PFCR MCR DRAMCR RTCNT RTCOR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Power-On Reset H'FF/H'00*2 H'FF H'FF H'FF H'D0 H'08 H'0D/H'00 H'00 H'00 H'00 H'FF Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Address*1 H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FDEB H'FED6 H'FED7 H'FED8 H'FED9 Notes: 1. Lower 16 bits of the address. 2. Determined by the MCU operating mode. OQERB KCAB QERB TIAW Rev. 3.00 Jan 11, 2005 page 137 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.2 7.2.1 Bit Register Descriptions Bus Width Control Register (ABWCR) : 7 ABW7 6 ABW6 1 R/W 0 R/W 5 ABW5 1 R/W 0 R/W 4 ABW4 1 R/W 0 R/W 3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W 1 ABW1 1 R/W 0 R/W 0 ABW0 1 R/W 0 R/W Modes 5 to 7 Initial value : RW Mode 4 Initial value : RW : : 1 R/W 0 R/W ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. ABWCR sets the data bus width for the external memory space. The bus width for on-chip memory and internal I/O registers is fixed regardless of the settings in ABWCR. In normal mode, the settings of bits ABW7 to ABW1 have no effect on operation. After a power-on reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 5 to 7, and to H'00 in mode 4. It is not initialized by a manual reset or in software standby mode. Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the corresponding area is to be designated for 8-bit access or 16-bit access. Bit n ABWn 0 1 Description Area n is designated for 16-bit access Area n is designated for 8-bit access (n = 7 to 0) Rev. 3.00 Jan 11, 2005 page 138 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.2.2 Bit Access State Control Register (ASTCR) : 7 AST7 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W 3 AST3 1 R/W 2 AST2 1 R/W 1 AST1 1 R/W 0 AST0 1 R/W Initial value : R/W : ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR. In normal mode, the settings of bits AST7 to AST1 have no effect on operation. ASTCR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is to be designated as a 2-state access space or a 3-state access space. Wait state insertion is enabled or disabled at the same time. Bit n ASTn 0 1 Description Area n is designated for 2-state access Wait state insertion in area n external space is disabled Area n is designated for 3-state access Wait state insertion in area n external space is enabled (Initial value) (n = 7 to 0) Rev. 3.00 Jan 11, 2005 page 139 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a power-on reset and in hardware standby mode. They are not initialized by a manual reset or in software standby mode. (1) WCRH Bit : 7 W71 Initial value : R/W : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3 W51 1 R/W 2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1. Bit 7 W71 0 1 Bit 6 W70 0 1 0 1 Description Program wait not inserted when external space area 7 is accessed 1 program wait state inserted when external space area 7 is accessed 2 program wait states inserted when external space area 7 is accessed 3 program wait states inserted when external space area 7 is accessed (Initial value) Rev. 3.00 Jan 11, 2005 page 140 of 1220 REJ09B0186-0300O Section 7 Bus Controller Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit 5 W61 0 1 Bit 4 W60 0 1 0 1 Description Program wait not inserted when external space area 6 is accessed 1 program wait state inserted when external space area 6 is accessed 2 program wait states inserted when external space area 6 is accessed 3 program wait states inserted when external space area 6 is accessed (Initial value) Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 W51 0 1 Bit 2 W50 0 1 0 1 Description Program wait not inserted when external space area 5 is accessed 1 program wait state inserted when external space area 5 is accessed 2 program wait states inserted when external space area 5 is accessed 3 program wait states inserted when external space area 5 is accessed (Initial value) Bits 1 and 0—Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1. Bit 1 W41 0 1 Bit 0 W40 0 1 0 1 Description Program wait not inserted when external space area 4 is accessed 1 program wait state inserted when external space area 4 is accessed 2 program wait states inserted when external space area 4 is accessed 3 program wait states inserted when external space area 4 is accessed (Initial value) Rev. 3.00 Jan 11, 2005 page 141 of 1220 REJ09B0186-0300O Section 7 Bus Controller (2) WCRL Bit : 7 W31 Initial value : R/W : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3 W11 1 R/W 2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1. Bit 7 W31 0 1 Bit 6 W30 0 1 0 1 Description Program wait not inserted when external space area 3 is accessed 1 program wait state inserted when external space area 3 is accessed 2 program wait states inserted when external space area 3 is accessed 3 program wait states inserted when external space area 3 is accessed (Initial value) Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1. Bit 5 W21 0 1 Bit 4 W20 0 1 0 1 Description Program wait not inserted when external space area 2 is accessed 1 program wait state inserted when external space area 2 is accessed 2 program wait states inserted when external space area 2 is accessed 3 program wait states inserted when external space area 2 is accessed (Initial value) Rev. 3.00 Jan 11, 2005 page 142 of 1220 REJ09B0186-0300O Section 7 Bus Controller Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 W11 0 1 Bit 2 W10 0 1 0 1 Description Program wait not inserted when external space area 1 is accessed 1 program wait state inserted when external space area 1 is accessed 2 program wait states inserted when external space area 1 is accessed 3 program wait states inserted when external space area 1 is accessed (Initial value) Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1. Bit 1 W01 0 1 Bit 0 W00 0 1 0 1 Description Program wait not inserted when external space area 0 is accessed 1 program wait state inserted when external space area 0 is accessed 2 program wait states inserted when external space area 0 is accessed 3 program wait states inserted when external space area 0 is accessed (Initial value) Rev. 3.00 Jan 11, 2005 page 143 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.2.4 Bit Bus Control Register H (BCRH) : 7 ICIS1 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W 3 0 R/W 2 0 R/W 1 RMTS1 0 R/W 0 RMTS0 0 R/W BRSTRM BRSTS1 BRSTS0 RMTS2 Initial value : R/W : BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1 0 1 Description Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas (Initial value) Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed. Bit 6 ICIS0 0 1 Description Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles (Initial value) Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface. Bit 5 BRSTRM 0 1 Description Area 0 is basic bus interface Area 0 is burst ROM interface (Initial value) Rev. 3.00 Jan 11, 2005 page 144 of 1220 REJ09B0186-0300O Section 7 Bus Controller Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 0 1 Description Burst cycle comprises 1 state Burst cycle comprises 2 states (Initial value) Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 0 1 Description Max. 4 words in burst access Max. 8 words in burst access (Initial value) Bits 2 to 0—RAM Type Select (RMTS2 to RMTS0): In advanced mode, these bits select the memory interface for areas 2 to 5. When DRAM space is selected, the appropriate area becomes the DRAM interface. Bit 2 RMTS2 0 Bit 1 RMTS1 0 1 1 1 Bit 0 RMTS0 0 1 0 1 1 Area 5 Normal space Normal space Normal space DRAM space Contiguous DRAM space DRAM space DRAM space Area 4 Description Area 3 Area 2 Note: When all areas selected in DRAM are 8-bit space, the PF2 pin can be used as an I/O port and for and . When contiguous RAM is selected set the appropriate bus width and number of access states (the number of programmable waits) to the same values for all of areas 2 to 5. Do not set other than the above combinations. TIAW OQERB Rev. 3.00 Jan 11, 2005 page 145 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.2.5 Bit Bus Control Register L (BCRL) : 7 BRLE 0 R/W 6 BREQOE 0 R/W 5 — 0 — 4 OES 0 R/W 3 DDS 1 R/W 2 RCTS 0 R/W 1 WDBE 0 R/W 0 WAITE 0 R/W Initial value : R/W : BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of pin input. 1 External bus release is enabled Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request signal ( ) in the external bus release state, when an internal bus master performs an external space access, or when a refresh request is generated. Bit 6 BREQOE 0 1 Description output enabled Bit 5—Reserved: This bit cannot be modified and is always read as 0. Rev. 3.00 Jan 11, 2005 page 146 of 1220 REJ09B0186-0300O OQERB output disabled. can be used as I/O port OQERB KCAB QERB QERB OQERB OQERB TIAW Bit 7 BRLE 0 BCRL is initialized to H'08 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release. Description External bus release is disabled. , and can be used as I/O ports (Initial value) (Initial value) Section 7 Bus Controller Bit 4 OES 0 1 Description When only area 2 is set for DRAM, or when areas 2 to 5 are set as contiguous DRAM space, the pin is used as the pin Bit 3—DACK Timing Select (DDS): When using the DRAM interface, this bit selects the DMAC single address transfer bus timing. Bit 3 DDS 0 1 Description When performing DMAC single address transfers to DRAM, always execute full access. The signal is output as a low-level signal from the Tr or T1 cycle Burst access is also possible when performing DMAC single address tranfers to DRAM. The signal is output as a low-level signal from the TC1 or T2 cycle Bit 2 RCTS 0 1 Description signal output timing is same when reading and writing signal is asserted half cycle earlier than when writing (Initial value) Bit 1—Write Data Buffer Enable (WDBE): This bit selects whether or not to use the write buffer function in the external write cycle or the DMAC single address cycle. Bit 1 WDBE 0 1 Description Write data buffer function not used Write data buffer function used (Initial value) SAC When reading, SAC Bit 2—Read CAS Timing Select (RCTS): Selects the signal output timing. Rev. 3.00 Jan 11, 2005 page 147 of 1220 REJ09B0186-0300O EO 3SC 3SC KCAD KCAD 3SC Uses the pin as the port or as signal output EO 3SC Bit 4—OE Select (OES): Selects the pin as the pin. (Initial value) (Initial value) SAC Section 7 Bus Controller Bit 0 WAITE 0 1 Description Wait input by pin enabled 7.2.6 Bit Pin Function Control Register (PFCR) : 7 CSS07 0 R/W 6 CSS36 0 R/W 5 BUZZE 0 R/W 4 LCASS 0 R/W 3 AE3 1/0 R/W 2 AE2 1/0 R/W 1 AE1 0 R/W 0 AE0 1/0 R/W Initial value : R/W : PFCR is an 8-bit read/write register that controls the CS selection of pins PG4 and PG1, controls LCAS selection of pins PF2 and PF6, and controls the address output in expanded mode with ROM. PFCR is initialized to H'0D/H'00 by a power-on reset and in hardware standby mode. It retains its previous state by a manual reset or in software standby mode. / Select (CSS07): This bit selects the contents of CS output via the PG4 pin. In Bit 7— modes 4, 5, and 6, setting the corresponding DDR to 1 outputs the selected CS. Bit 7 CSS07 0 1 Description Selects Bit 6— / Select (CSS36): This bit selects the contents of CS output via the PG1 pin. In modes 4, 5, and 6, setting the corresponding DDR to 1 outputs the selected CS. Bit 6 CSS36 0 1 Description Selects Rev. 3.00 Jan 11, 2005 page 148 of 1220 REJ09B0186-0300O 6SC 3SC Selects 7SC 0SC Selects TIAW TIAW TIAW Wait input by pin disabled. pin can be used as I/O port (Initial value) (Initial value) (Initial value) TIAW Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the pin. 7SC 0SC 6SC 3SC Section 7 Bus Controller Bit 5—BUZZ Output Enable (BUZZE): This bit enables/disables BUZZ output via the PF1 pin. The WDT1 input clock, selected with PSS and CKS2 to CKS0, is output as the BUZZ signal. See Section 15.2.4, Pin Function Control Register (PFCR) for details of BUZZ output. Bit 5 BUZZE 0 1 Description Functions as PF1 input pin Functions as BUZZ output pin (Initial value) Bit 4—LCAS Output Pin Select Bit (LCASS): Selects output pin for LCAS signal. Bit 4 LCASS 0 1 Description Outputs LCAS signal from PF2 Outputs LCAS signal from PF6 (Initial value) Rev. 3.00 Jan 11, 2005 page 149 of 1220 REJ09B0186-0300O Section 7 Bus Controller Bits 3 to 0—Address Output Enable 3 to 0 (AE3 to AE0): These bits select enabling or disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is enabled for address output, the address is output regardless of the corresponding DDR setting. When a pin is disabled for address output, it becomes an output port when the corresponding DDR bit is set to 1. Bit 3 AE3 0 Bit 2 AE2 0 Bit 1 AE1 0 1 Bit 0 AE0 0 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Description A8 to A23 address output disabled (Initial value*) A8 address output enabled; A9 to A23 address output disabled A8, A9 address output enabled; A10 to A23 address output disabled A8 to A10 address output enabled; A11 to A23 address output disabled A8 to A11 address output enabled; A12 to A23 address output disabled A8 to A12 address output enabled; A13 to A23 address output disabled A8 to A13 address output enabled; A14 to A23 address output disabled A8 to A14 address output enabled; A15 to A23 address output disabled A8 to A15 address output enabled; A16 to A23 address output disabled A8 to A16 address output enabled; A17 to A23 address output disabled A8 to A17 address output enabled; A18 to A23 address output disabled A8 to A18 address output enabled; A19 to A23 address output disabled A8 to A19 address output enabled; A20 to A23 address output disabled A8 to A20 address output enabled; A21 to A23 address output disabled (Initial value*) A8 to A21 address output enabled; A22, A23 address output disabled A8 to A23 address output enabled Note: * In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000. In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101. Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to 1. Rev. 3.00 Jan 11, 2005 page 150 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.2.7 Bit Memory Control Register (MCR) : 7 TPC 0 R/W 6 BE 0 R/W 5 RCDM 0 R/W 4 CW2 0 R/W 3 MXC1 0 R/W 2 MXC0 0 R/W 1 RLW1 0 R/W 0 RLW0 0 R/W Initial value : R/W : The MCR is an 8-bit read/write register that, when areas 2 to 5 are set as the DRAM interface, controls the DRAM strobe method, number of precharge cycles, access mode, address multiplex shift amount, and number of wait states to be inserted when a refresh is performed. The MCR is initialized to H'00 at a power-on reset and in hardware standby mode. It is not initialized at a manual reset or in software standby mode. Bit 7—TP Cycle Control (TPC): When accessing areas 2 to 5, allocated to DRAM, this bit selects whether the precharge cycle (TP) is 1 state or 2 states. Bit 7 TPC 0 1 Description Insert 1 precharge cycle Insert 2 precharge cycles (Initial value) Bit 6—Burst Access Enable (BE): This bit enables/disables burst access of areas 2 to 5, allocated as DRAM space. DRAM space burst access is in high-speed page mode. When using EDO type in this case, either select OE output or RAS up mode. Bit 6 BE 0 1 Description Burst disabled (always full access) Access DRAM space in high-speed page mode (Initial value) Rev. 3.00 Jan 11, 2005 page 151 of 1220 REJ09B0186-0300O Section 7 Bus Controller Bit 5—RAS Down Mode (RCDM): When areas 2 to 5 are allocated to DRAM space, this bit selects whether the signal level remains Low while waiting for the next DRAM access (RAS down mode) or the signal level returns to High (RAS up mode), when DRAM access is discontinued. Bit 5 RCDM 0 1 Description DRAM interface: selects RAS up mode DRAM interface: selects RAS down mode (Initial value) Bit 4—Reserved (CW2): Only write 0 to this bit. Bits 3 and 2—Multiplex shift counts 1 and 0 (MXC1, MXC0): These bits select the shift amount to the low side of the row address of the multiplexed row/column address in DRAM interface mode. They also select the row address to be compared in burst operation of the DRAM interface. Bit 3 MXC1 0 Bit 2 MXC0 0 Description 8-bit shift (Initial value) 1 1 0 1 Rev. 3.00 Jan 11, 2005 page 152 of 1220 REJ09B0186-0300O SAR SAR — (1) 8-bit access space: target row addresses for comparison are A23 to A8 (2) 16-bit access space: target row addresses for comparison are A23 to A9 9-bit shift (1) 8-bit access space: target row addresses for comparison are A23 to A9 (2) 16-bit access space: target row addresses for comparison are A23 to A10 10-bit shift (1) 8-bit access space: target row addresses for comparison are A23 to A10 (2) 16-bit access space: target row addresses for comparison are A23 to A11 Section 7 Bus Controller Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1, RLW0): These bits select the number of wait states to be inserted in the CAS-before-RAS refresh cycle of the DRAM interface. The selected number of wait states is applied to all areas set as DRAM space. Wait input via the pin is disabled. TIAW Bit 1 RLW1 0 1 Bit 0 RLW0 0 1 0 1 Description Do not insert wait state Insert 1 wait state Insert 2 wait states Insert 3 wait states (Initial value) 7.2.8 Bit DRAM Control Register (DRAMCR) : 7 RFSHE 0 R/W 6 CBRM 0 R/W 5 RMODE 0 R/W 4 CMF 0 R/W 3 CMIE 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : The DRAMCR is an 8-bit read/write register that selects DRAM refresh mode, the refresh counter clock, and sets the refresh timer control. The DRAMCR is initialized to H'00 at a power-on reset and in hardware standby mode. It is not initialized at a manual reset or in software standby mode. Bit 7—Refresh Control (RFSHE): This bit selects whether or not to perform refresh control. When not performing refresh control, the refresh timer can be used as an interval timer. Bit 7 RFSHE 0 1 Description Do not perform refresh control Perform refresh control (Initial value) Rev. 3.00 Jan 11, 2005 page 153 of 1220 REJ09B0186-0300O Section 7 Bus Controller Bit 6—CBR Refresh Mode (CBRM): This bit selects whether CBR refresh is performed in parallel with other external access, or only CBR refresh is performed. Bit 6 CBRM 0 1 Description Enables external access during CAS-before-RAS refresh Disables external access during CAS-before-RAS refresh (Initial value) Bit 5—Refresh Mode (RMODE): This bit selects whether or not to perform a self refresh in software standby mode when performing refresh control (RFSHE = 1). Bit 5 RMODE 0 1 Description Do not perform self-refresh in software standby mode Perform self-refresh in software standby mode (Initial value) Bit 4—Compare Match Flag (CMF): This status flag shows a match between RTCNT and RTCOR values. When performing refresh control (RFSHE = 1), write 1 to CMF when writing to the DRAMCR. Bit 4 CMF 0 1 Description [Clearing condition] • • W hen CMF = 1, read the CMF flag, then clear the CMF flag to 0 CMF is set when RTCNT = RTCOR (Initial value) [Setting condition] Bit 3—Compare Match Interrupt Enable (CMIE): This bit enables/disables the CMF flag interrupt request (CMI) when the DRAMCR CMF flag is set to 1. CMIE is always 0 when performing a self-refresh. Bit 3 CMIE 0 1 Description Disables CMF flag interrupt requests (CMI) Enables CMF flag interrupt requests (CMI) (Initial value) Rev. 3.00 Jan 11, 2005 page 154 of 1220 REJ09B0186-0300O Section 7 Bus Controller Bits 2 to 0—Refresh Counter Clock Select (CKS2 to CKS0): These bits select from the seven internal clocks derived by dividing the system clock (φ) to be input to RTCNT. The RTCNT count up starts when CKS2 to CKS0 are set to select the input clock. Bit 2 CKS2 0 Bit 1 CKS1 0 1 1 0 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 Description Stops count Counts on φ/2 Counts on φ/8 Counts on φ/32 Counts on φ/128 Counts on φ/512 Counts on φ/2048 Counts on φ/4096 (Initial value) 7.2.9 Bit Refresh Timer Counter (RTCNT) : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value : R/W : RTCNT is an 8-bit read/write up-counter. RTCNT counts up using the internal clock selected by the DRAMCR CKS2 to CKS0 bits. When RTCNT matches the value in RTCOR (compare match), the DRAMCR CMF flag is set to 1 and RTCNT is cleared to H'00. If, at this point, DRAMCR RFSHE is set to 1, the refresh cycle starts. When the DRAMCR CMIE bit is set to 1, a compare match interrupt (CMI) is also generated. RTCNT is initialized to H'00 at a power-on reset and in hardware standby mode. It is not initialized at a manual reset or in software standby mode. Rev. 3.00 Jan 11, 2005 page 155 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.2.10 Bit Refresh Time Constant Register (RTCOR) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : R/W : RTCOR is an 8-bit read/write register that sets theRTCNT compare match cycle. The values of RTCOR and RTCNT are constantly compared and, when both value match, the DRAMCR CMF flag is set to 1 and RTCNT is cleared to H'00. RTCOR is initialized to H'FF at a power-on reset and in hardware standby mode. It is not initialized at a manual reset or in software standby mode. Rev. 3.00 Jan 11, 2005 page 156 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.3 7.3.1 Overview of Bus Control Area Partitioning In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. A chip select signal ( to ) can be output for each area. In normal mode*, it controls a 64-kbyte address space comprising part of area 0. Figure 7.2 shows an outline of the memory map. Note: * Not available in the H8S/2643 Group. 7SC 0SC H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) H'FFFFFF (1) Advanced mode H'0000 H'FFFF (2) Normal mode* Note: * Not available in the H8S/2643 Group. Figure 7.2 Overview of Area Partitioning Rev. 3.00 Jan 11, 2005 page 157 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. (1) Bus Width A bus width of 8 or 16 bits can be selected with ADWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is always set. (2) Number of Access States Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a 3-state access space. With the DRAM interface or the burst ROM interface, the number of access states may be determined without regard to ASTCR. When 2-state access space is designated, wait insertion is disabled. (3) Number of Program Wait States When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected. Table 7.3 shows the bus specifications for each basic bus interface area. Rev. 3.00 Jan 11, 2005 page 158 of 1220 REJ09B0186-0300O Section 7 Bus Controller Table 7.3 ABWCR ABWn 0 Bus Specifications for Each Area (Basic Bus Interface) ASTCR ASTn 0 1 WCRH, WCRL Wn1 — 0 1 Wn0 — 0 1 0 1 — 0 1 1 0 1 8 2 3 Bus Specifications (Basic Bus Interface) Bus Width 16 Program Wait Access States States 2 3 0 0 1 2 3 0 0 1 2 3 1 0 1 — 0 7.3.3 Memory Interfaces The H8S/2643 Group memory interfaces comprise a basic bus interface that allows direct connection or ROM, SRAM, and so on, DRAM interface with direct DRAM connection and a burst ROM interface that allows direct connection of burst ROM. The memory interface can be selected independently for each area. An area for which the basic bus interface is designated functions as normal space, and areas set for DRAM interface are DRAM spaces an area for which the burst ROM interface is designated functions as burst ROM space. Rev. 3.00 Jan 11, 2005 page 159 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.3.4 Interface Specifications for Each Area The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (sections 7.4, Basic Bus Interface, 7.5, DRAM Interface, and 7.7, Burst ROM Interface) should be referred to for further details. (1) Area 0 Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external space. Either basic bus interface or burst ROM interface can be selected for area 0. (2) Areas 1 and 6 In external expansion mode, all of areas 1 and 6 is external space. Only the basic bus interface can be used for areas 1 and 6. (3) Areas 2 to 5 In external expansion mode, all of areas 2 to 5 is external space. (4) Area 7 Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space. Only the basic bus interface can be used for the area 7. Rev. 3.00 Jan 11, 2005 page 160 of 1220 REJ09B0186-0300O 7SC A signal can be output when accessing area 7 external space. SAR 5SC 2SC 5SC 2SC to The standard bus interface or DRAM interface can be selected for areas 2 to 5. In DRAM interface to are used as signals. mode, signals 6SC 0SC A signal can be output when accessing area 0 external space. and pin signals can be output when accessing the area 1 and 6 external space. 1SC signals can be output when accessing area 2 to 5 external space. Section 7 Bus Controller 7.3.5 Chip Select Signals This LSI allows chip select signals ( to ) to be output for each of areas 0 to 7. The level of these signals is set Low when accessing the external space of the respective area. signal can be enabled or disabled by the data direction register (DDR) of The output of the pin. the port of the corresponding pin is set for output after a power-on reset. The to In ROM-disabled expanded mode, the pins are set for input after a power-on reset, so the corresponding DDR must be set to 1 to to signals. allow the output of to are set for input after a power-on reset, In ROM-disabled expanded mode, all of pins to signals. so the corresponding DDR must be set to 1 to allow the output of See section 10, I/O Ports for details. Bus cycle T1 φ T2 T3 Address bus Area n external address CSn nSC Figure 7.3 Signal Output Timing (where n=0 to 7) Rev. 3.00 Jan 11, 2005 page 161 of 1220 REJ09B0186-0300O SAR 5SC 2SC When areas 2 to 5 are set as DRAM space, to outputs are used as signals. 1SC 7SC 0SC 7SC 0SC 0SC nSC 7SC 1SC nSC Figure 7.3 shows example (where n = 0 to 7) signal output timing. 7SC 0SC nSC 7SC Section 7 Bus Controller 7.4 7.4.1 Basic Bus Interface Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 7.3). 7.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. (1) 8-Bit Access Space Figure 7.4 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses. Upper data bus Lower data bus D15 D8 D7 D0 Byte size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Word size Figure 7.4 Access Sizes and Data Alignment Control (8-Bit Access Space) Rev. 3.00 Jan 11, 2005 page 162 of 1220 REJ09B0186-0300O Section 7 Bus Controller (2) 16-Bit Access Space Figure 7.5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Lower data bus Upper data bus D15 D8 D7 D0 Byte size Byte size Word size Longword size 1st bus cycle 2nd bus cycle • Even address • Odd address Figure 7.5 Access Sizes and Data Alignment Control (16-Bit Access Space) Rev. 3.00 Jan 11, 2005 page 163 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.4.3 Valid Strobes Table 7.4 shows the data buses used and valid strobes for the access spaces. Table 7.4 Area 8-bit access space Data Buses Used and Valid Strobes Access Read/ Size Write Byte Read Write Read Write Word Read Write Address — — Even Odd Even Odd — — Valid Strobe Upper Data Bus (D15 to D8) Valid Valid Invalid Valid Hi-Z Valid Valid Lower data bus (D7 to D0) Invalid Hi-Z Invalid Valid Hi-Z Valid Valid Valid 16-bit access Byte space , Notes: Hi-Z: High impedance. Invalid: Input state; input value is ignored. Rev. 3.00 Jan 11, 2005 page 164 of 1220 REJ09B0186-0300O RWL RWL RWH DR RWL RWH DR RWH DR RWH In a write, the lower half. DR In a read, the data bus. signal is valid without discrimination between the upper and lower halves of the signal is valid for the upper half of the data bus, and the signal for the Section 7 Bus Controller 7.4.4 Basic Timing (1) 8-Bit 2-State Access Space Figure 7.6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. RWL The pin is fixed high. Wait states cannot be inserted. Bus cycle T1 φ T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Note: n = 0 to 7 Figure 7.6 Bus Timing for 8-Bit 2-State Access Space Rev. 3.00 Jan 11, 2005 page 165 of 1220 REJ09B0186-0300O Section 7 Bus Controller (2) 8-Bit 3-State Access Space Figure 7.7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Rev. 3.00 Jan 11, 2005 page 166 of 1220 REJ09B0186-0300O RWL The pin is fixed high. Wait states can be inserted. Bus cycle T1 φ T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 Valid High impedance D7 to D0 Note: n = 0 to 7 Figure 7.7 Bus Timing for 8-Bit 3-State Access Space Section 7 Bus Controller (3) 16-Bit 2-State Access Space Figures 7.8 to 7.10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted. Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Note: n = 0 to 7 Figure 7.8 Bus Timing for 16-Bit 2-State Access Space (Even Address Byte Access) Rev. 3.00 Jan 11, 2005 page 167 of 1220 REJ09B0186-0300O Section 7 Bus Controller Bus cycle T1 φ T2 Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Valid Note: n = 0 to 7 Figure 7.9 Bus Timing for 16-Bit 2-State Access Space (Odd Address Byte Access) Rev. 3.00 Jan 11, 2005 page 168 of 1220 REJ09B0186-0300O Section 7 Bus Controller Bus cycle T1 φ T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 7 Figure 7.10 Bus Timing for 16-Bit 2-State Access Space (Word Access) Rev. 3.00 Jan 11, 2005 page 169 of 1220 REJ09B0186-0300O Section 7 Bus Controller (4) 16-Bit 3-State Access Space Figures 7.11 to 7.13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted. Bus cycle T1 φ T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 Valid High impedance D7 to D0 Note: n = 0 to 7 Figure 7.11 Bus Timing for 16-Bit 3-State Access Space (Even Address Byte Access) Rev. 3.00 Jan 11, 2005 page 170 of 1220 REJ09B0186-0300O Section 7 Bus Controller Bus cycle T1 φ T2 T3 Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Note: n = 0 to 7 Valid Figure 7.12 Bus Timing for 16-Bit 3-State Access Space (Odd Address Byte Access) Rev. 3.00 Jan 11, 2005 page 171 of 1220 REJ09B0186-0300O Section 7 Bus Controller Bus cycle T1 φ T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Note: n = 0 to 7 Valid Figure 7.13 Bus Timing for 16-Bit 3-State Access Space (Word Access) Rev. 3.00 Jan 11, 2005 page 172 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.4.5 Wait Control When accessing external space, the H8S/2643 Group can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin pin. wait insertion using the (1) Program Wait Insertion From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings of WCRH and WCRL. (2) Pin Wait Insertion pin. Program Setting the WAITE bit in BCRL to 1 enables wait insertion by means of the wait insertion is first carried out according to the settings in WCRH and WCRL. Then, if the pin is low at the falling edge of φ in the last T2 or Tw state, a Tw state is inserted. If the pin is held low, Tw states are inserted until it goes high. This is useful when inserting four or more Tw states, or when changing the number of Tw states for different external devices. The WAITE bit setting applies to all areas. Rev. 3.00 Jan 11, 2005 page 173 of 1220 REJ09B0186-0300O TIAW TIAW TIAW TIAW Section 7 Bus Controller Figure 7.14 shows an example of wait state insertion timing. By program wait T1 T2 Tw By WAIT pin Tw Tw T3 φ WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Note: indicates the timing of WAIT pin sampling. Figure 7.14 Example of Wait State Insertion Timing The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT input disabled. At a manual reset, the bus control register values are retained and wait control continues as before the reset. Rev. 3.00 Jan 11, 2005 page 174 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.5 7.5.1 DRAM Interface Overview This LSI allows area 2 to 5 external space to be set as DRAM space and DRAM interfacing to be performed. With the DRAM interface, DRAM can be directly connected to the LSI. BCRH RMTS2 to RMTS0 allow the setting up of 2-, 4-, or 8-Mbyte DRAM space. Burst operation is possible using high-speed page mode. 7.5.2 Setting Up DRAM Space To set up areas 2 to 5 as DRAM space, set the RMTS2 to RMTS0 bits of BCRH. Table 7.5 shows the relationship between the settings of the RMTS2 to RMTS0 bits and DRAM space. You can select (1) one area (area 2), (2) two areas (areas 2 and 3), or (3) four areas (areas 2 to 5). Using ×16 bits 64-M DRAMs requires a 4-M word (8-Mbyte) contiguous space. Setting RMTS2 to RMTS0 to 1 allows areas 2 to 5 to be configured as one contiguous DRAM space. The RAS pin, and to can be used as input ports. In this signal can be output from the configuration, the bus widths are the same for areas 2 to 5. Table 7.5 RMTS2 0 RMTS2 to RMTS0 Settings vs DRAM Space RMTS1 0 1 RMTS0 1 0 1 1 Area 5 Normal space Normal space DRAM space Contiguous DRAM space DRAM space Area 4 Area 3 Area 2 DRAM space 1 1 5SC 3SC 2SC Rev. 3.00 Jan 11, 2005 page 175 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.5.3 Address Multiplexing In the case of DRAM space, the row address and column address are multiplexed. With address multiplexing, the MXC1 and MXC0 bits of the MCR select the amount of shift in the row address. Table 7.6 shows the relationship between MXC1 and MXC0 settings and the shift amount. Table 7.6 MXC1 and MXC0 Settings vs Address Multiplexing Address Pin A23 to A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 MCR Shift MXC1 MXC0 Amount Row 0 address 1 0 1 0 1 Column — address — 8 bits 9 bits 10 bits Setting prohibited — A23 to A13 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A23 to A13 A12 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A23 to A13 A12 A11 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 — — — — — — A8 — A7 — A6 — A5 — A4 — A3 — A2 — A1 — A0 A23 to A13 A12 A11 A10 A9 7.5.4 Data Bus Setting the ABWCR bit of an area set as DRAM space to 1 sets the corresponding area as 8-bit DRAM space. Clearing the ABWCR bit to 0 sets the area as 16-bit DRAM. 16-bit DRAMs can be directly connected in the case of 16-bit DRAM space. With 8-bit DRAM space, the high data bus byte (D15 to D8) is valid. With 16-bit DRAM space, the high and low data bus bytes (D15 to D0) are valid. The access size and data alignment are the same as for the standard bus interface. See section 7.4.2, Data Size and Data Alignment for details. Rev. 3.00 Jan 11, 2005 page 176 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.5.5 DRAM Interface Pins Table 7.7 shows the pins used for the DRAM interface, and their functions. Table 7.7 Pin DRAM Interface Pin Configuration In DRAM Mode Name Write enable Direction Output Function Write enable when accessing DRAM space in 2 CAS mode. Lower column address strobe signal when accessing 16-bit DRAM space. Row address strobe when area 2 set as DRAM space. Row address strobe when area 3 set as DRAM space. Row address strobe when area 4 set as DRAM space. Row address strobe when area 5 set as DRAM space. Upper column address strobe when accessing DRAM space. Wait request signal Multiplexed output of row address and column address. Output enable signal when accessing DRAM space in read mode. A12 to A0 D15 to D0 A12 to A0 D15 to D0 * Note: * Valid when OES bit set to 1. 7.5.6 Basic Timing Figure 7.15 shows the basic access timing for DRAM space. There are four basic DRAM timing states. In contrast to the standard bus interface, the corresponding ASTCR bit only controls the enabling/disabling of wait insertion and has no effect on the number of access states. When the corresponding ASTCR bit is cleared to 0, no wait states can be inserted in the DRAM access cycle. Rev. 3.00 Jan 11, 2005 page 177 of 1220 REJ09B0186-0300O SACU SACL 2SAR 3SAR 4SAR 5SAR TIAW EO EW SACL TIAW SAC 2SC 3SC 4SC 5SC EO RWH Lower column address Output strobe Row address strobe 2 Output Row address strobe 3 Output Row address strobe 4 Output Row address strobe 5 Output Upper column address Output strobe Wait Address pin Data pin Output enable pin Input Output Input/output Data input/output pin. Output Section 7 Bus Controller The four basic timing states are as follows: TP (precharge cycle) 1 state, Tr (row address output cycle) 1 state, Tc1 and Tc2 (column address output cycle) two states. A23 to A0 AS CSn (RAS) RCTS = 0 CAS, LCAS RCTS = 1 HWR (WE) Read RD D15 toD0 CAS, LCAS HWR (WE) Write RD D15 to D0 Note: n = 2 to 5 Rev. 3.00 Jan 11, 2005 page 178 of 1220 REJ09B0186-0300O SAC φ When RCTS is set to 1, the cycle earlier when reading. signal timing differs when reading and writing, being asserted Ω Tp Tr Tc1 Tc2 row column Figure 7.15 Basic Access Timing Section 7 Bus Controller 7.5.7 Precharge State Control When accessing DRAM, it is essential to secure a time for RAS precharging. In this LSI, it is therefore necessary to insert 1 TP state when accessing DRAM space. By setting the TPC bit of the MCR to 1, TP can be changed from 1 state to 2 states. Set the appropriate number of TP cycles according to the type of DRAM connected and the operation frequency of the LSI. Figure 7.16 shows the timing when TP is set for 2 states. Setting the TPC bit to 1 also sets the refresh cycle TP to 2 states. Tp1 φ Tp2 Tr Tc1 Tc2 A23 to A0 row column CSn (RAS) RCTS = 0 CAS, LCAS RCTS = 1 Read HWR (WE) D15 to D0 CAS, LCAS Write HWR (WE) D15 to D0 Note: n = 2 to 5 Figure 7.16 Timing With Two Precharge Cycles Rev. 3.00 Jan 11, 2005 page 179 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.5.8 Wait Control There are two methods of inserting wait states in DRAM access: (1) insertion of program wait states, and (2) insertion of pin waits via pin. (1) Insertion of Program Wait States Setting the ASTCR bit of an area set for DRAM to 1 automatically inserts from 0 to 3 wait states, as set by WCRH and WCRL, between the Tc1 state and Tc2 state. Rev. 3.00 Jan 11, 2005 page 180 of 1220 REJ09B0186-0300O SAC When a program wait is inserted, the write wait function is activated and only the output only during the Tc2 state when writing. TIAW signal is Section 7 Bus Controller Figure 7.17 shows example timing for the insertion of program waits. Program waits Tp Tr Tc1 Tw Tw Tc2 φ Address bus AS CSn (RAS) RCTS = 0 CAS, LCAS RCTS = 1 Read RD Data bus Read data CAS, LCAS Write HWR (WE) Data bus Note: ↓ shows timing for WAIT pin sampling. n = 2 to 5 Write data Figure 7.17 Example Program Wait Insertion Timing (Wait 2 State Insertion) Rev. 3.00 Jan 11, 2005 page 181 of 1220 REJ09B0186-0300O Section 7 Bus Controller (2) Insertion of Pin Waits pin is valid regardless of the When the WAITE bit of BCRH is set to 1, wait input via the ASTCR AST bit. In this state, a program wait is inserted when the DRAM space is accessed. If the pin level is Low at the fall in φ in the final Tc1 or Tw state, a further Tw is inserted. If the pin is kept Low, Tw is inserted until the level of the pin changes to High. level of the Rev. 3.00 Jan 11, 2005 page 182 of 1220 REJ09B0186-0300O SAC TIAW When wait states are inserted via the pin, the when writing is output after the Tw state. TIAW TIAW TIAW TIAW Section 7 Bus Controller Tp Tr Program waits Tc1 Tw WAIT pin wait states Tw φ Address bus AS CSn (RAS) RCTS = 0 CAS, LCAS RCTS = 1 Read RD Data bus CAS, LCAS Write HWR (WE) Data bus Note: ↓ shows timing for /WAIT pin sampling. n = 2 to 5 Write data Rev. 3.00 Jan 11, 2005 page 183 of 1220 REJ09B0186-0300O TIAW Figure 7.18 Example Timing for Insertion of Wait States via TIAW Figure 7.18 shows example timing for the insertion of wait states via the pin. Tc2 Read data Pin Section 7 Bus Controller 7.5.9 Byte Access Control When 16-bit DRAMs are connected, the 2 CAS method can be used as the control signal required for byte access. Figure 7.19 shows the 2 CAS method control timing. Figure 7.20 shows an example of connecting DRAM in high-speed page mode. Tp φ A23 to A0 Tr Tc1 row CSn (RAS) CAS Byte control LCAS HWR (WE) Note: n = 2 to 5 Figure 7.19 2 CAS Method Control Timing (For High Byte Write Access) to control the read data or, as shown in figure When using DRAM EDO page mode, either use 7.20, select RAS up mode. Figure 7.21 is an example of DRAM connection in EDO page mode when OES = 1. Rev. 3.00 Jan 11, 2005 page 184 of 1220 REJ09B0186-0300O SACL When all areas selected as DRAM space are set as 8-bit space, the port. pin functions as an I/O Tc2 column EO Section 7 Bus Controller This LSI (address shift set to 9 bits) 2CAS 4-Mbit DRAM 256 kbytes × 16-bit configuration 9-bit column address RAS UCAS LCAS WE A8 A7 A6 A4 A3 A2 A1 A0 D15 to D0 Row address input: A8 to A0 CS (RAS) CAS LCAS HWR (WE) A9 A8 A7 A6 A5 A4 A3 A2 A1 D15 to D0 A5 Column address input: A8 to A0 OE Figure 7.20 High-speed Page Mode DRAM Rev. 3.00 Jan 11, 2005 page 185 of 1220 REJ09B0186-0300O Section 7 Bus Controller This LSI (address shift set to 10 bits) 2CAS 16-Mbit DRAM 1 Mbyte × 16-bit configuration 10-bit column address RAS UCAS LCAS WE A9 A8 A7 A6 A4 A3 A2 A1 A0 D15 to D0 OE Row address input: A9 to A0 CS2 (RAS) CAS LCAS HWR (WE) A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 CS3 (OE) D15 to D0 A5 Column address input: A9 to A0 Figure 7.21 Example Connection of EDO Page Mode DRAM (OES = 1) 7.5.10 Burst Operation In addition to full DRAM access (normal DRAM access), in which the row address is output each time the data in DRAM is accessed, there is also a high-speed page mode that allows high-speed access (burst access). In this method, if the same row address is accessed successively, the row address is output once and then only the column address is changed. Burst access is selected by setting the BE bit of the MCR to 1. Rev. 3.00 Jan 11, 2005 page 186 of 1220 REJ09B0186-0300O Section 7 Bus Controller (1) Operation Timing for Burst Access (High-Speed Page Mode) Figure 7.22 shows the operation timing for burst access. When the DRAM space is successively signal and column address output cycle (2 state) are continued as long as the accessed, the row address is the same in the preceding and succeeding access cycles. The MXC1 and MXC0 bits of the MCR specify which row address is compared. Read OE* D15 to D0 Write OE D15 to D0 Notes: n = 2 to 5 * OE is enabled when OES = 1. The bus cycle can also be extended in burst access by inserting wait states. The method and timing of inserting the wait states is the same as in full access. For details, see section 7.5.8, Wait Control. SAC Tp Tr Tc1 Tc2 Tc1 Tc2 φ A23 to A0 row column1 column2 AS CSn (RAS) RCTS = 0 CAS, LCAS RCTS = 1 HWR (WE) CAS, LCAS HWR (WE) Figure 7.22 Operating Timing in High-Speed Page Mode Rev. 3.00 Jan 11, 2005 page 187 of 1220 REJ09B0186-0300O Section 7 Bus Controller (2) RAS Down Mode and RAS Up Mode Even when burst operation is selected, DRAM access may not be continuous, but may be interrupted by accessing another area. In this case, burst operation can be continued by keeping the signal level Low while the other area is accessed and then accessing the same row address in the DRAM space. • RAS down mode To select RAS down mode, set the RCDM bit of the MCR to 1. When DRAM access is signal level is kept Low and, if the row address interrupted and another area accessed, the is the same as previously when the DRAM space is again accessed, burst access is continued. Figure 7.23 shows example RAS down mode timing. Note that if the refresh operation occurs when RAS is down, the signal level changes to High. DRAM read access Tp φ Tr Tc1 Tc2 External space read access T1 T2 A23 to A0 RD HWR (WE) CSn (RAS) RCTS = 0 CAS, LCAS RCTS = 1 OE* D15 to D0 Notes: n = 2 to 5 * OE is enabled when OES = 1. Figure 7.23 Example Operation Timing in RAS Down Mode Rev. 3.00 Jan 11, 2005 page 188 of 1220 REJ09B0186-0300O SAR SAR SAR DRAM write access Tc1 Tc2 Section 7 Bus Controller • RAS up mode To select RAS up mode, clear the RCDM bit of the MCR to 0. If DRAM access is interrupted to access another area, the signal level returns to High. Burst operation is only possible when the DRAM space is contiguous. Figure 7.24 shows example timing in RAS up mode. Note that the signal level does not return to High in burst ROM space access. Tp φ A23 to A0 RD HWR (WE) CSn (RAS) CAS, LCAS D15 to D0 Note: n = 2 to 5 Figure 7.24 Example Operation Timing in RAS Up Mode SAR SAR DRAM write access Tr Tc1 Tc2 DRAM read access Tc1 Tc2 External space write access T1 T2 Rev. 3.00 Jan 11, 2005 page 189 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.5.11 Refresh Control This LSI has a DRAM refresh control function. There are two refresh methods: (1) CAS-beforeRAS (CBR), and (2) self refresh. (1) CAS-Before-RAS (CBR) Refresh To select CBR refresh, set the RFSHE bit of DRAMCR to 1 and clear the RMODE bit to 0. In CBR refresh, the input clock selected with the CKS2 to CKS0 bits of DRAMCR are used for the RTCNT count-up. Refresh control is performed when the count reaches the value set in RTCOR (compare match). The RTCNT is then reset and the count again started from H'00. That is, the refresh is repeated at the set interval determined by RTCOR and CKS2 to CKS0. Set RTCOR and CKS2 to CKS0 to satisfy the refresh cycle for the DRAM being used. The RTCNT count up starts when the CKS2 to CKS0 bits are set. The RTCNT and RTCOR values should therefore be set before setting CKS2 to CKS0. When a value is set in RTCOR, RTCNT is cleared. When RTCNT is set at the same time that it is reset by a compare match, the value written to RTCNT takes precedence. When performing refresh control (RFSHE = 1), do not clear the CMF flag. Figure 7.25 shows RTCNT operation. Figure 7.26 shows compare match timing. And figure 7.27 shows CBR refresh timing. signal to be changed during the refresh cycle. In this Some types of DRAM do not allow the case, set CBRM to 1. Figure 7.28 shows the timing. The signal is not controlled and a Low level is output when an access request occurs. Note that other normal spaces are accessed during the CBR refresh cycle. RTCNT RTCOR H'00 Refresh request Figure 7.25 RTCNT Operation Rev. 3.00 Jan 11, 2005 page 190 of 1220 REJ09B0186-0300O SC EW Section 7 Bus Controller φ RTCNT N H'00 RTCOR N Refresh request signal and CMF bit setting signal Figure 7.26 Compare Match Timing Read access of normal space Write access of normal space φ A23 to A0 CS AS RD HWR (WE) Refresh cycle RAS CAS Figure 7.27 Example CBR Refresh Timing (CBRM = 0) Rev. 3.00 Jan 11, 2005 page 191 of 1220 REJ09B0186-0300O Section 7 Bus Controller Normal space access request φ A23 to A0 CS AS RD HWR (WE) Refresh cycle RAS CAS Figure 7.28 Example CBR Refresh Timing (CBRM = 1) Rev. 3.00 Jan 11, 2005 page 192 of 1220 REJ09B0186-0300O Section 7 Bus Controller (2) Self-Refresh One of the DRAM standby modes is the self-refresh mode (battery backup mode), in which the DRAM generates its own refresh timing and refresh address. To select self-refresh, set the RFSHE bit and RMODE bits of the DRAMCR to 1. Next, execute a SLEEP instruction to make a transition to software standby mode. As shown in figure 7.29, the and signals are output and the DRAM enters self-refresh mode. When you exit software standby mode, the RMODE bit is cleared to 0 and self-refresh mode is exited. When making a transition to software standby mode, self-refresh mode starts after a CBR refresh, providing there is a CBR refresh request. CBR refresh requests occurring immediately before entering software standby mode are cleared on completion of the self-refresh when the software standby mode is exited. Software standby TRp φ TRcr TRc3 CSn (RAS) CAS, LCAS HWR (WE) Note: n = 2 to 5 SAR SAC High level Figure 7.29 Self-Refresh Timing Rev. 3.00 Jan 11, 2005 page 193 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.6 DMAC Single Address Mode and DRAM Interface When burst mode is set for the DRAM interface, the DDS bit selects the output timing for the signal. It also selects whether or not to perform burst access when accessing the DRAM space in DMAC single address mode. 7.6.1 Burst access is performed on the basis of the address only, regardless of the bus master. The output level changes to Low afer the Tc1 state in the case of the DRAM interface. Rev. 3.00 Jan 11, 2005 page 194 of 1220 REJ09B0186-0300O KCAD Figure 7.30 shows the KCAD KCAD DDS = 1 output timing for the DRAM interface when DDS = 1. Section 7 Bus Controller Tp φ Tr Tc1 Tc2 A23 to A0 row column CSn (RAS) CAS (UCAS) LCAS (LCAS) Read HWR (WE) RCTS = 0 RCTS = 1 D15 to D0 CAS (UCAS) LCAS (LCAS) Write HWR (WE) D15 to D0 DACK Note: n = 2 to 5 KCAD Figure 7.30 Output Timing when DDS = 1 (Example Showing DRAM Access) Rev. 3.00 Jan 11, 2005 page 195 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.6.2 DDS = 0 When the DRAM space is accessed in DMAC single address mode, always perform full access (normal access). The output level changes to Low afer the Tr state in the case of the DRAM interface. In other than DMAC signle address mode, burst access is possible when the DRAM space is accessed. Rev. 3.00 Jan 11, 2005 page 196 of 1220 REJ09B0186-0300O KCAD Figure 7.31 shows the KCAD output timing for the DRAM interface when DDS = 0. Section 7 Bus Controller Tp φ Tr Tc1 Tc2 A23 to A0 row column CSn (RAS) CAS (UCAS) LCAS (LCAS) RCTS = 1 RCTS = 0 Read HWR (WE) D15 to D0 CAS (UCAS) LCAS (LCAS) Write HWR (WE) D15 to D0 DACK Note: n = 2 to 5 KCAD Figure 7.31 Output Timing when DDS = 0 (Example Showing DRAM Access) Rev. 3.00 Jan 11, 2005 page 197 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.7 7.7.1 Burst ROM Interface Overview In this LSI, the area 0 external space can be set as burst ROM space and burst ROM interfacing performed. Burst ROM space interfacing allows 16-bit ROM capable of burst access to be accessed at high-speed. The BRSTRM bit of BCRH sets area 0 as burst ROM space. CPU instruction fetches (only) can be performed using a maximum of 4-word or 8-word continuous burst access. 1 state or 2 states can be selected in the case of burst access. 7.7.2 Basic Timing The AST0 bit of ASTCR sets the number of access states in the initial cycle (full access) of the burst ROM interface. Wait states can be inserted when the AST0 bit is set to 1. The burst cycle can be set for 1 state or 2 sttes by setting the BRSTS1 bit of BCRH. Wait states cannot be inserted. When area 0 is set as burst ROM space, area 0 is a 16-bit access space regardless of the ABW0 bit of ABWCR. When the BRSTS0 bit of BCRH is cleared to 0, 4-word max. burst access is performed. When the BRSTS0 bit is set to 1, 8-word max. burst access is performed. Figure 7.32 (a) and (b) shows the basic access timing for the burst ROM space. Figure 7.32 (a) is an example when both the AST0 and BRSTS1 bits are set to 1. Figure 7.32 (b) is an example when both the AST0 and BRSTS1 bits are set to 0. Rev. 3.00 Jan 11, 2005 page 198 of 1220 REJ09B0186-0300O Section 7 Bus Controller Full access T1 φ T2 T3 T1 Burst access T2 T1 T2 Address bus Low address only changes CS0 AS RD Data bus Read data Read data Read data Figure 7.32 (a) Example Burst ROM Access Timing (AST0 = BRSTS1 = 1) Rev. 3.00 Jan 11, 2005 page 199 of 1220 REJ09B0186-0300O Section 7 Bus Controller Full access T1 φ T2 Burst access T1 T1 Address bus Low address only changes CS0 AS RD Data bus Read data Read data Read data Figure 7.32 (b) Example Burst ROM Access Timing (AST0 = BRSTS1 = 0) 7.7.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the pin can be used in the initial cycle (full access) of the burst ROM interface. See section 7.4.5, Wait Control. Wait states cannot be inserted in the burst cycle. Rev. 3.00 Jan 11, 2005 page 200 of 1220 REJ09B0186-0300O TIAW Section 7 Bus Controller 7.8 7.8.1 Idle Cycle Operation When the H8S/2643 Group accesses external space, it can insert a 1-state idle cycle (TI) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on. (1) Consecutive Reads between Different Areas If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read cycle. Figure 7.33 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A φ Address bus CS (area A) CS (area B) RD Data bus Data collision (b) Idle cycle inserted (Initial value ICIS1 = 1) T1 T2 T3 Bus cycle B T1 T2 φ Address bus CS (area A) CS (area B) RD Data bus Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Long output floating time (a) Idle cycle not inserted (ICIS1 = 0) Figure 7.33 Example of Idle Cycle Operation (1) Rev. 3.00 Jan 11, 2005 page 201 of 1220 REJ09B0186-0300O Section 7 Bus Controller (2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 7.34 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A φ Address bus CS (area A) CS (area B) RD T1 T2 T3 Bus cycle B T1 T2 φ Address bus CS (area A) CS (area B) RD Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Possibility of overlap between CS (area B) and RD (a) Idle cycle not inserted (ICIS1 = 0) (b) Idle cycle inserted (Initial value ICIS1 = 1) Figure 7.34 Example of Idle Cycle Operation (2) Rev. 3.00 Jan 11, 2005 page 202 of 1220 REJ09B0186-0300O Section 7 Bus Controller In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap signal and the bus cycle B signal. between the bus cycle A In the initial state after reset release, idle cycle insertion (b) is set. Bus cycle A φ Address bus CS (area A) CS (area B) RD HWR Data bus Data collision (b) Idle cycle inserted (Initial value ICIS1 = 1) T1 T2 T3 Bus cycle B T1 T2 φ Address bus CS (area A) CS (area B) RD HWR Data bus Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Long output floating time (a) Idle cycle not inserted (ICIS1 = 0) Rev. 3.00 Jan 11, 2005 page 203 of 1220 REJ09B0186-0300O DR SC Figure 7.35 Relationship between Chip Select ( ) and Read ( ) SC DR Setting idle cycle insertion, as in (b), however, will prevent any overlap between the signals. SC SC DR Depending on the system’s load conditions, the example is shown in figure 7.35. signal may lag behind the DR SC (3) Relationship between Chip Select ( ) Signal and Read ( ) Signal signal. An DR and Section 7 Bus Controller (4) Notes The setting of the ICIS0 and ICIS1 bits is invalid when accessing the DRAM space. For example, if the 2nd of successive reads of different areas is a DRAM access, only the TP cycle is inserted, not the T1 cycle. Figure 7.36 shows the timing. Note, however, that ICIS0 and ICIS1 settings are valid in burst access in RAS down mode, and an idle cycle is inserted. Figure 7.37 (a) and (b) shows the timing. External read T1 φ DRAM space read Tp Tr Tc1 Tc2 T2 T3 Address bus RD Data bus Figure 7.36 Example of DRAM Access after External Read DRAM space read Tp EXTAL Address RD RAS CAS, LCAS Data bus Tr Tc1 Tc2 T1 External read T1 T2 T3 DRAM space read Tc1 Tc1 Tc2 Idle cycle Figure 7.37 (a) Example Idle Cycle Operation in RAS Down Mode (ICIS1 = 1) Rev. 3.00 Jan 11, 2005 page 204 of 1220 REJ09B0186-0300O Section 7 Bus Controller DRAM space read Tp EXTAL Address RD HWR RAS CAS, LCAS Data bus Tr Tc1 Tc2 T1 External read T1 T2 T3 DRAM space read Tc1 Tc1 Tc2 Idle cycle Figure 7.37 (b) Example Idle Cycle Operation in RAS Down Mode (ICIS0 = 1) 7.8.2 Pin States in Idle Cycle Table 7.8 shows pin states in an idle cycle. Table 7.8 Pins A23 to A0 D15 to D0 Pin States in Idle Cycle Pin State Contents of next bus cycle High impedance High* High High High High High High Note: * Remains low in DRAM space RAS down mode or a refresh cycle. nKCAD RWL RWH DR SA SAC nSC Rev. 3.00 Jan 11, 2005 page 205 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.9 Write Data Buffer Function The H8S/2643 Group has a write data buffer function in the external data bus. Using the write data buffer function enables external writes and DMA single address mode transmission to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit in BCRL to 1. Figure 7.38 shows an example of the timing when the write data buffer function is used. When this function is used, if an external write and DMA single address mode transmission continues for 2 states or longer, and there is an internal access next, only an external write is executed in the first state, but from the next state onward an internal access (on-chip memory or internal I/O register read/write) is executed in parallel with the external write rather than waiting until it ends. On-chip memory read Internal I/O register read External write cycle T1 T2 TW TW T3 Internal address bus Internal memory Internal read signal Internal I/O register address A23 to A0 External address External space write CSn HWR, LWR D15 to D0 Figure 7.38 Example of Timing when Write Data Buffer Function Is Used Rev. 3.00 Jan 11, 2005 page 206 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.10 7.10.1 Bus Release Overview The H8S/2643 Group can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. If an internal bus master wants to make an external access and when a refresh request occurs in the external bus released state, it can issue a bus request off-chip. 7.10.2 Operation In external expansion mode, the bus can be released to an external device by setting the BRLE bit pin low issues an external bus request to the H8S/2643 Group. in BCRL to 1. Driving the When the pin is sampled, at the prescribed timing the pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus-released state. In the external bus released state, an internal bus master can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request from the external bus master to be dropped. Also, when a refresh request occurs in the external bus released state, refresh control is deferred until the external bus master drops the bus request. If the BREQOE bit in BCRL is set to 1, when an internal bus master wants to make an external pin is access and when a refresh request occurs in the external bus released state, the driven low and a request can be made off-chip to drop the bus request. The following shows the order of priority when an external bus release request, refresh request, and external access by the internal bus master occur simultaneously: When CBRM = 1 (High) Refresh > External bus release > External access by internal bus master (Low) When CBRM = 0 (High) Refresh > External bus release (Low) (High) External bus release > External access by internal bus master (Low) Rev. 3.00 Jan 11, 2005 page 207 of 1220 REJ09B0186-0300O KCAB pin is driven high, the When the external bus released state is terminated. pin is driven high at the prescribed timing and the OQERB KCAB QERB QERB QERB Section 7 Bus Controller Note: A refresh can be executed at the same time as external access by the internal bus master. 7.10.3 Pin States in External Bus Released State Table 7.9 shows pin states in the external bus released state. Table 7.9 Pins A23 to A0 D15 to D0 Pin States in Bus Released State Pin State High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High Rev. 3.00 Jan 11, 2005 page 208 of 1220 REJ09B0186-0300O nKCAD RWL RWH DR SA SAC nSC Section 7 Bus Controller 7.10.4 Transition Timing Figure 7.39 shows the timing for transition to the bus-released state. CPU cycle CPU cycle T0 T1 T2 External bus released state φ High impedance Address bus Address High impedance High impedance Data bus CSn AS High impedance High impedance RD HWR, LWR High impedance BREQ BACK BREQO* Minimum 1 state [1] [1] [2] [3] [4] [5] [6] [2] [3] [4] [5] [6] Low level of BREQ pin is sampled at rise of T2 state. BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master. BREQ pin state is still sampled in external bus released state. High level of BREQ pin is sampled. BACK pin is driven high, ending bus release cycle. BREQO signal goes high 1.5 clocks after BACK signal goes high. Note: * Output only when BREQOE is set to 1. Figure 7.39 Bus-Released State Transition Timing Rev. 3.00 Jan 11, 2005 page 209 of 1220 REJ09B0186-0300O Section 7 Bus Controller DRAM space read access External bus released φ A23 to A0 CS AS RD RAS CAS BREQ BACK Figure 7.40 Example Bus Release Transition Timing After DRAM Access (Reading DRAM) 7.10.5 Notes The external bus release function is deactivated when MSTPCR is set to H'FFFFFF or H'EFFFFF and a transition is made to sleep mode. To use the external bus release function in sleep mode, do not set MSTPCR to H'FFFFFF and H'EFFFFF. = 1 width greater When the CBRM bit is set to 1 to use the CBR refresh function, set the than the number of the slowest external access states. Otherwise, CBR refresh requests from the refresh timer may not be performed. Rev. 3.00 Jan 11, 2005 page 210 of 1220 REJ09B0186-0300O QERB Section 7 Bus Controller 7.11 7.11.1 Bus Arbitration Overview The H8S/2643 Group has a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU, DTC, and DMAC which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. 7.11.2 Operation The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) DMAC > DTC > CPU (Low) An internal bus access by an internal bus master, external bus release, and refresh can be executed in parallel. In the event of simultaneous external bus release request, refresh request, and internal bus master external access request generation, the order of priority is as follows: When CBRM = 1 (High) Refresh > External bus release > External access by internal bus master (Low) When CBRM = 0 (High) Refresh > External bus release (Low) (High) External bus release > External access by internal bus master (Low) Rev. 3.00 Jan 11, 2005 page 211 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.11.3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. (1) CPU The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: • The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. See appendix A.5, Bus States During Instruction Execution, for timings at which the bus is not transferred. • If the CPU is in sleep mode, it transfers the bus immediately. (2) DTC The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). (3) DMAC When a start request occurs, the DMAC requests the bus arbiter for bus privileges. The DMAC releases bus privileges on completion of one transmission in short address mode, normal mode external requests, and cycle steal mode. The DMAC releases the bus on completion of the transmission of one block in block transmission mode, or after a transmission in burst mode. Rev. 3.00 Jan 11, 2005 page 212 of 1220 REJ09B0186-0300O Section 7 Bus Controller 7.12 Resets and the Bus Controller In a power-on reset, the H8S/2643 Group, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. The bus controller registers and internal states are retained at a manual reset. The current external input is ignored. Write data is not retained. Also, bus cycle is executed to completion. The and outputs are disabled and because the DMAC is initialized at a manual reset, function as I/O ports controlled by DDR and DR. Rev. 3.00 Jan 11, 2005 page 213 of 1220 REJ09B0186-0300O DNET KCAD TIAW Section 7 Bus Controller Rev. 3.00 Jan 11, 2005 page 214 of 1220 REJ09B0186-0300O Section 8 DMA Controller Section 8 DMA Controller 8.1 Overview The H8S/2643 Group has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4 channels. 8.1.1 Features The features of the DMAC are listed below. • Choice of short address mode or full address mode Short address mode  Maximum of 4 channels can be used  Choice of dual address mode or single address mode  In dual address mode, one of the two addresses, transfer source and transfer destination, is specified as 24 bits and the other as16 bits  In single address mode, transfer source or transfer destination address only is specified as 24 bits  In single address mode, transfer can be performed in one bus cycle  Choice of sequential mode, idle mode, or repeat mode for dual address mode and single address mode Full address mode  Maximum of 2 channels can be used  Transfer source and transfer destination address specified as 24 bits  Choice of normal mode or block transfer mode • 16-Mbyte address space can be specified directly • Byte or word can be set as the transfer unit • Activation sources: internal interrupt, external request, auto-request (depending on transfer mode)  Six 16-bit timer-pulse unit (TPU) compare match/input capture interrupts  Serial communication interface (SCI0, SCI1) transmit-data-empty interrupt, reception complete interrupt  A/D converter conversion end interrupt  External request  Auto-request Rev. 3.00 Jan 11, 2005 page 215 of 1220 REJ09B0186-0300O Section 8 DMA Controller • Module stop mode can be set  The initial setting enables DMAC registers to be accessed. DMAC operation is halted by setting module stop mode 8.1.2 Block Diagram A block diagram of the DMAC is shown in figure 8.1. Internal address bus Internal interrupts TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A TXI0 RXI0 TXI1 RXI1 ADI External pins DREQ0 DREQ1 TEND0 TEND1 DACK0 DACK1 Interrupt signals DEND0A DEND0B DEND1A DEND1B Address buffer Processor Channel 1B Channel 1A Channel 0B Channel 0A MAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B Module data bus Control logic DMAWER DMATCR DMACR0A DMACR0B DMACR1A DMACR1B DMABCR Data buffer Channel 1 Internal data bus Legend: DMAWER: DMATCR: DMABCR: DMACR: MAR: IOAR: ETCR: DMA write enable register DMA terminal control register DMA band control register (for all channels) DMA control register Memory address register I/O address register Executive transfer counter register Figure 8.1 Block Diagram of DMAC Rev. 3.00 Jan 11, 2005 page 216 of 1220 REJ09B0186-0300O Channel 0 IOAR0A Section 8 DMA Controller 8.1.3 Overview of Functions Tables 8.1 (a) and (b) summarize DMAC functions in short address mode and full address mode, respectively. Table 8.1 (a) Overview of DMAC Functions (Short Address Mode) Address Register Bit Length Transfer Mode Dual address mode Transfer Source • Source Destination 16/24 • Sequential mode  1-byte or 1-word transfer executed for one transfer request  Memory address incremented/decremented by 1 or 2  1 to 65536 transfers • Idle mode  1-byte or 1-word transfer executed for one transfer request  Memory address fixed  1 to 65536 transfers • Repeat mode  1-byte or 1-word transfer executed for one transfer request  Memory address incremented/ decremented by 1 or 2  After specified number of transfers (1 to 256), initial state is restored and operation continues • • • TPU channel 0 to 24/16 5 compare match/input capture A interrupt SCI transmit-dataempty interrupt SCI reception complete interrupt A/D converter conversion end interrupt External request • • • • 1-byte or 1-word transfer executed for one transfer request Transfer in 1 bus cycle using pin in place of address specifying I/O Specifiable for sequential, idle, and repeat modes Rev. 3.00 Jan 11, 2005 page 217 of 1220 REJ09B0186-0300O KCAD KCAD Single address mode • External request 24/ /24 KCAD Section 8 DMA Controller Table 8.1 (b) Overview of DMAC Functions (Full Address Mode) Address Register Bit Length Transfer Mode • Normal mode Auto-request  Transfer request retained internally  Transfers continue for the specified number of times (1 to 65536)  Choice of burst or cycle steal transfer External request  1-byte or 1-word transfer executed for one transfer request  1 to 65536 transfers • Block transfer mode  Specified block size transfer executed for one transfer request  1 to 65536 transfers  Either source or destination specifiable as block area  Block size: 1 to 256 bytes or words • • • • • TPU channel 0 to 24 5 compare match/input capture A interrupt SCI transmit-dataempty interrupt SCI reception complete interrupt External request A/D converter conversion end interrupt 24 • External request Transfer Source • Auto-request Source 24 Destination 24 Rev. 3.00 Jan 11, 2005 page 218 of 1220 REJ09B0186-0300O Section 8 DMA Controller 8.1.4 Pin Configuration Table 8.2 summarizes the DMAC pins. In short address mode, external request transfer, single address transfer, and transfer end output are not performed for channel A. The DMA transfer acknowledge function is used in channel B single address mode in short address mode. pins, setting single address transfer automatically sets the corresponding With regard to the pin. port to output, functioning as a Table 8.2 Channel 0 DMAC Pins Pin Name DMA request 0 DMA transfer acknowledge 0 DMA transfer end 0 Symbol I/O Input Output Output Input Output Output Function DMAC channel 0 external request DMAC channel 0 single address transfer acknowledge DMAC channel 0 transfer end DMAC channel 1 external request DMAC channel 1 single address transfer acknowledge DMAC channel 1 transfer end 1 DMA request 1 DMA transfer acknowledge 1 DMA transfer end 1 Rev. 3.00 Jan 11, 2005 page 219 of 1220 REJ09B0186-0300O DNET pins, whether or not the corresponding port is used as a With regard to the be specified by means of a register setting. 0QERD 1QERD 0DNET 0KCAD 1KCAD 1DNET KCAD KCAD DNET QERD When the pin is used, do not designate the corresponding port for output. pin can Section 8 DMA Controller 8.1.5 Register Configuration Table 8.3 summarizes the DMAC registers. Table 8.3 DMAC Registers Initial Value Bus Address* Width 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 8 bits 8 bits 16 bits 16 bits 16 bits 16 bits 16 bits 8 bits Channel Name 0 Memory address register 0A I/O address register 0A Transfer count register 0A Memory address register 0B I/O address register 0B Transfer count register 0B 1 Memory address register 1A I/O address register 1A Transfer count register 1A Memory address register 1B I/O address register 1B Transfer count register 1B 0, 1 DMA write enable register DMA control register 0A DMA control register 0B DMA control register 1A DMA control register 1B DMA band control register Note: * Lower 16 bits of the address. Abbreviation R/W MAR0A IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B DMAWER DMACR0A DMACR0B DMACR1A DMACR1B DMABCR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Undefined H'FEE0 Undefined H'FEE4 Undefined H'FEE6 Undefined H'FEE8 Undefined H'FEEC Undefined H'FEEE Undefined H'FEF0 Undefined H'FEF4 Undefined H'FEF6 Undefined H'FEF8 Undefined H'FEFC Undefined H'FEFE H'00 H'00 H'00 H'00 H'00 H'00 H'0000 H'3F H'FF60 H'FF61 H'FF62 H'FF63 H'FF64 H'FF65 H'FF66 H'FDE8 DMA terminal control register DMATCR Module stop control register A MSTPCRA Rev. 3.00 Jan 11, 2005 page 220 of 1220 REJ09B0186-0300O Section 8 DMA Controller 8.2 Register Descriptions (1) (Short Address Mode) Short address mode transfer can be performed for channels A and B independently. Short address mode transfer is specified for each channel by clearing the FAE bit in DMABCR to 0, as shown in table 8.4. Short address mode or full address mode can be selected for channels 1 and 0 independently by means of bits FAE1 and FAE0. Table 8.4 FAE0 0 Short Address Mode and Full Address Mode (For 1 Channel: Example of Channel 0) Description Short address mode specified (channels A and B operate independently) Channel 0A MAR0A IOAR0A ETCR0A DMACR0A MAR0B IOAR0B ETCR0B DMACR0B Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source, etc. Channel 0B Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source, etc. 1 Full address mode specified (channels A and B operate in combination) MAR0A MAR0B Channel 0 Specifies transfer source address Specifies transfer destination address Not used Not used Specifies number of transfers Specifies number of transfers (used in block transfer mode only) Specifies transfer size, mode, activation source, etc. IOAR0A IOAR0B ETCR0A ETCR0B DMACR0A DMACR0B Rev. 3.00 Jan 11, 2005 page 221 of 1220 REJ09B0186-0300O Section 8 DMA Controller 8.2.1 Bit MAR R/W Bit MAR R/W Memory Address Register (MAR) : : : : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined 31 — 0 — 15 30 — 0 — 14 29 — 0 — 13 28 — 0 — 12 27 — 0 — 11 26 — 0 — 10 25 — 0 — 9 24 — 0 * * * * * * * * — R/W R/W R/W R/W R/W R/W R/W R/W 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 Initial value : Initial value : MAR is a 32-bit readable/writable register that specifies the transfer source address or destination address. The upper 8 bits of MAR are reserved: they are always read as 0, and cannot be modified. Whether MAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. MAR is incremented or decremented each time a byte or word transfer is executed, so that the address specified by MAR is constantly updated. For details, see section 8.2.4, DMA Control Register (DMACR). MAR is not initialized by a reset or in standby mode. Rev. 3.00 Jan 11, 2005 page 222 of 1220 REJ09B0186-0300O Section 8 DMA Controller 8.2.2 Bit IOAR R/W I/O Address Register (IOAR) : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer source address or destination address. The upper 8 bits of the transfer address are automatically set to H'FF. Whether IOAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. IOAR is invalid in single address mode. IOAR is not incremented or decremented each time a transfer is executed, so that the address specified by IOAR is fixed. IOAR is not initialized by a reset or in standby mode. 8.2.3 Execute Transfer Count Register (ETCR) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of this register is different for sequential mode and idle mode on the one hand, and for repeat mode on the other. (1) Sequential Mode and Idle Mode Transfer Counter Bit ETCR R/W : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : Rev. 3.00 Jan 11, 2005 page 223 of 1220 REJ09B0186-0300O Section 8 DMA Controller In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter (with a count range of 1 to 65,536). ETCR is decremented by 1 each time a transfer is performed, and when the count reaches H'0000, the DTE bit in DMABCR is cleared, and transfer ends. (2) Repeat Mode Transfer Number Storage Bit ETCRH R/W : : * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W : 15 14 13 12 11 10 9 8 Initial value : Transfer Counter Bit ETCRL R/W : : * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W *: Undefined : 7 6 5 4 3 2 1 0 Initial value : In repeat mode, ETCR functions as transfer counter ETCRL (with a count range of 1 to 256) and transfer number storage register ETCRH. ETCRL is decremented by 1 each time a transfer is performed, and when the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this point, MAR is automatically restored to the value it had when the count was started. The DTE bit in DMABCR is not cleared, and so transfers can be performed repeatedly until the DTE bit is cleared by the user. ETCR is not initialized by a reset or in standby mode. 8.2.4 Bit DMACR R/W DMA Control Register (DMACR) : : : 7 DTSZ 0 R/W 6 DTID 0 R/W 5 RPE 0 R/W 4 DTDIR 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W Initial value : DMACR is an 8.bit readable/writable register that controls the operation of each DMAC channel. DMACR is initialized to H'00 by a reset, and in standby mode. Rev. 3.00 Jan 11, 2005 page 224 of 1220 REJ09B0186-0300O Section 8 DMA Controller Bit 7—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time. Bit 7 DTSZ 0 1 Description Byte-size transfer Word-size transfer (Initial value) Bit 6—Data Transfer Increment/Decrement (DTID): Selects incrementing or decrementing of MAR every data transfer in sequential mode or repeat mode. In idle mode, MAR is neither incremented nor decremented. Bit 6 DTID 0 Description MAR is incremented after a data transfer • • 1 • • W hen DTSZ = 0, MAR is incremented by 1 after a transfer W hen DTSZ = 1, MAR is incremented by 2 after a transfer W hen DTSZ = 0, MAR is decremented by 1 after a transfer W hen DTSZ = 1, MAR is decremented by 2 after a transfer (Initial value) MAR is decremented after a data transfer Bit 5—Repeat Enable (RPE): Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed. Bit 5 RPE 0 1 DMABCR DTIE 0 1 0 1 Description Transfer in sequential mode (no transfer end interrupt) Transfer in sequential mode (with transfer end interrupt) Transfer in repeat mode (no transfer end interrupt) Transfer in idle mode (with transfer end interrupt) (Initial value) For details of operation in sequential, idle, and repeat mode, see section 8.5.2, Sequential Mode, section 8.5.3, Idle Mode, and section 8.5.4, Repeat Mode. Rev. 3.00 Jan 11, 2005 page 225 of 1220 REJ09B0186-0300O Section 8 DMA Controller Bit 4—Data Transfer Direction (DTDIR): Used in combination with the SAE bit in DMABCR to specify the data transfer direction (source or destination). The function of this bit is therefore different in dual address mode and single address mode. DMABCR SAE 0 Bit 4 DTDIR 0 1 1 0 1 Description Transfer with MAR as source address and IOAR as destination address (Initial value) Transfer with IOAR as source address and MAR as destination address Transfer with pin as read strobe and MAR as destination address Transfer with MAR as source address and pin as write strobe Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source). There are some differences in activation sources for channel A and for channel B. Rev. 3.00 Jan 11, 2005 page 226 of 1220 REJ09B0186-0300O KCAD KCAD Section 8 DMA Controller Channel A Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 1 1 0 1 1 0 0 Bit 0 DTF0 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 0 1 1 0 1 Description — — — Activated by SCI channel 0 transmit-data-empty interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmit-data-empty interrupt Activated by SCI channel 1 reception complete interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt — — (Initial value) Activated by A/D converter conversion end interrupt Rev. 3.00 Jan 11, 2005 page 227 of 1220 REJ09B0186-0300O Section 8 DMA Controller Channel B Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 1 1 0 1 1 0 0 Bit 0 DTF0 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 0 1 1 0 1 Description — Activated by Activated by pin falling edge input* pin low-level input (Initial value) Activated by A/D converter conversion end interrupt Activated by SCI channel 0 transmit-data-empty interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmit-data-empty interrupt Activated by SCI channel 1 reception complete interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt — — Note: * Detected as a low level in the first transfer after transfer is enabled. The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 8.5.13, DMAC Multi-Channel Operation. Rev. 3.00 Jan 11, 2005 page 228 of 1220 REJ09B0186-0300O QERD QERD Section 8 DMA Controller 8.2.5 Bit DMA Band Control Register (DMABCR) : 15 FAE1 0 R/W 7 DTE1B 0 R/W 14 FAE0 0 R/W 6 DTE1A 0 R/W 13 SAE1 0 R/W 5 DTE0B 0 R/W 12 SAE0 0 R/W 4 DTE0A 0 R/W 11 DTA1B 0 R/W 3 DTIE1B 0 R/W 10 DTA1A 0 R/W 2 DTIE1A 0 R/W 9 DTA0B 0 R/W 1 DTIE0B 0 R/W 8 DTA0A 0 R/W 0 DTIE0A 0 R/W DMABCRH : Initial value : R/W Bit : : DMABCRL : Initial value : R/W : DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel. DMABCR is initialized to H'0000 by a reset, and in standby mode. Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short address mode or full address mode. In short address mode, channels 1A and 1B are used as independent channels. Bit 15 FAE1 0 1 Description Short address mode Full address mode (Initial value) Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short address mode or full address mode. In short address mode, channels 0A and 0B are used as independent channels. Bit 14 FAE0 0 1 Description Short address mode Full address mode (Initial value) Rev. 3.00 Jan 11, 2005 page 229 of 1220 REJ09B0186-0300O Section 8 DMA Controller Bit 13—Single Address Enable 1 (SAE1): Specifies whether channel 1B is to be used for transfer in dual address mode or single address mode. Bit 13 SAE1 0 1 Description Transfer in dual address mode Transfer in single address mode (Initial value) This bit is invalid in full address mode. Bit 12—Single Address Enable 0 (SAE0): Specifies whether channel 0B is to be used for transfer in dual address mode or single address mode. Bit 12 SAE0 0 1 Description Transfer in dual address mode Transfer in single address mode (Initial value) This bit is invalid in full address mode. Bits 11 to 8—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the CPU or DTC. When DTE = 1 and DTA = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the CPU or DTC regardless of the DTA bit setting. Bit 11—Data Transfer Acknowledge 1B (DTA1B): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1B data transfer factor setting. Rev. 3.00 Jan 11, 2005 page 230 of 1220 REJ09B0186-0300O Section 8 DMA Controller Bit 11 DTA1B 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bit 10—Data Transfer Acknowledge 1A (DTA1A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1A data transfer factor setting. Bit 10 DTA1A 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bit 9—Data Transfer Acknowledge 0B (DTA0B): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0B data transfer factor setting. Bit 9 DTA0B 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bit 8—Data Transfer Acknowledge 0A (DTA0A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0A data transfer factor setting. Bit 8 DTA0A 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bits 7 to 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is Rev. 3.00 Jan 11, 2005 page 231 of 1220 REJ09B0186-0300O Section 8 DMA Controller an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. The conditions for the DTE bit being cleared to 0 are as follows: • When initialization is performed • When the specified number of transfers have been completed in a transfer mode other than repeat mode • When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason When DTE = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the data transfer factor setting. When a request is issued by the activation source, DMA transfer is executed. The condition for the DTE bit being set to 1 is as follows: • When 1 is written to the DTE bit after the DTE bit is read as 0 Bit 7—Data Transfer Enable 1B (DTE1B): Enables or disables data transfer on channel 1B. Bit 7 DTE1B 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bit 6—Data Transfer Enable 1A (DTE1A): Enables or disables data transfer on channel 1A. Bit 6 DTE1A 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bit 5—Data Transfer Enable 0B (DTE0B): Enables or disables data transfer on channel 0B. Bit 5 DTE0B 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Rev. 3.00 Jan 11, 2005 page 232 of 1220 REJ09B0186-0300O Section 8 DMA Controller Bit 4—Data Transfer Enable 0A (DTE0A): Enables or disables data transfer on channel 0A. Bit 4 DTE0A 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bits 3 to 0—Data Transfer End Interrupt Enable (DTIE): These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIE bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE bit to 1. Bit 3—Data Transfer End Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1B transfer end interrupt. Bit 3 DTIE1B 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Bit 2—Data Transfer End Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1A transfer end interrupt. Bit 2 DTIE1A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Rev. 3.00 Jan 11, 2005 page 233 of 1220 REJ09B0186-0300O Section 8 DMA Controller Bit 1—Data Transfer End Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0B transfer end interrupt. Bit 1 DTIE0B 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Bit 0—Data Transfer End Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0A transfer end interrupt. Bit 0 DTIE0A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) 8.3 Register Descriptions (2) (Full Address Mode) Full address mode transfer is performed with channels A and B together. For details of full address mode setting, see table 8.4. 8.3.1 Bit MAR R/W Bit MAR R/W Memory Address Register (MAR) : : : : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined 31 — 0 — 15 30 — 0 — 14 29 — 0 — 13 28 — 0 — 12 27 — 0 — 11 26 — 0 — 10 25 — 0 — 9 24 — 0 * * * * * * * * — R/W R/W R/W R/W R/W R/W R/W R/W 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 Initial value : Initial value : MAR is a 32-bit readable/writable register; MARA functions as the transfer source address register, and MARB as the destination address register. Rev. 3.00 Jan 11, 2005 page 234 of 1220 REJ09B0186-0300O Section 8 DMA Controller MAR is composed of two 16-bit registers, MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and cannot be modified. MAR is incremented or decremented each time a byte or word transfer is executed, so that the source or destination memory address can be updated automatically. For details, see section 8.3.4, DMA Control Register (DMACR). MAR is not initialized by a reset or in standby mode. 8.3.2 I/O Address Register (IOAR) IOAR is not used in full address transfer. 8.3.3 Execute Transfer Count Register (ETCR) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The function of this register is different in normal mode and in block transfer mode. ETCR is not initialized by a reset or in standby mode. (1) Normal Mode ETCRA Transfer Counter Bit ETCR R/W : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each time a transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not used at this time. ETCRB ETCRB is not used in normal mode. Rev. 3.00 Jan 11, 2005 page 235 of 1220 REJ09B0186-0300O Section 8 DMA Controller (2) Block Transfer Mode ETCRA Holds block size Bit ETCRAH R/W : : * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W : 15 14 13 12 11 10 9 8 Initial value : Block size counter Bit ETCRAL R/W : : * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W *: Undefined : 7 6 5 4 3 2 1 0 Initial value : ETCRB Block Transfer Counter Bit ETCRB R/W : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH holds the block size. ETCRAL is decremented each time a 1-byte or 1-word transfer is performed, and when the count reaches H'00, ETCRAL is loaded with the value in ETCRAH. So by setting the block size in ETCRAH and ETCRAL, it is possible to repeatedly transfer blocks consisting of any desired number of bytes or words. ETCRB functions in block transfer mode, as a 16-bit block transfer counter. ETCRB is decremented by 1 each time a block is transferred, and transfer ends when the count reaches H'0000. Rev. 3.00 Jan 11, 2005 page 236 of 1220 REJ09B0186-0300O Section 8 DMA Controller 8.3.4 DMA Control Register (DMACR) DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel. In full address mode, DMACRA and DMACRB have different functions. DMACR is initialized to H'0000 by a reset, and in standby mode. DMACRA Bit : 15 DTSZ 0 R/W 14 SAID 0 R/W 13 SAIDE 0 R/W 12 BLKDIR 0 R/W 11 BLKE 0 R/W 10 — 0 R/W 9 — 0 R/W 8 — 0 R/W DMACRA : Initial value : R/W : DMACRB Bit : 7 — 0 R/W 6 DAID 0 R/W 5 DAIDE 0 R/W 4 — 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W DMACRB : Initial value : R/W : Bit 15—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time. Bit 15 DTSZ 0 1 Description Byte-size transfer Word-size transfer (Initial value) Bit 14—Source Address Increment/Decrement (SAID) Bit 13—Source Address Increment/Decrement Enable (SAIDE): These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data transfer is performed. Rev. 3.00 Jan 11, 2005 page 237 of 1220 REJ09B0186-0300O Section 8 DMA Controller Bit 14 SAID 0 Bit 13 SAIDE 0 1 Description MARA is fixed MARA is incremented after a data transfer • • 1 0 1 W hen DTSZ = 0, MARA is incremented by 1 after a transfer W hen DTSZ = 1, MARA is incremented by 2 after a transfer (Initial value) MARA is fixed MARA is decremented after a data transfer • • W hen DTSZ = 0, MARA is decremented by 1 after a transfer W hen DTSZ = 1, MARA is decremented by 2 after a transfer Bit 12—Block Direction (BLKDIR) Bit 11—Block Enable (BLKE): These bits specify whether normal mode or block transfer mode is to be used. If block transfer mode is specified, the BLKDIR bit specifies whether the source side or the destination side is to be the block area. Bit 12 BLKDIR 0 1 Bit 11 BLKE 0 1 0 1 Description Transfer in normal mode Transfer in normal mode Transfer in block transfer mode, source side is block area (Initial value) Transfer in block transfer mode, destination side is block area For operation in normal mode and block transfer mode, see section 8.5, Operation. Rev. 3.00 Jan 11, 2005 page 238 of 1220 REJ09B0186-0300O Section 8 DMA Controller Bits 10 to 7—Reserved: Can be read or written to. Bit 6—Destination Address Increment/Decrement (DAID) Bit 5—Destination Address Increment/Decrement Enable (DAIDE): These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed. Bit 6 DAID 0 Bit 5 DAIDE 0 1 Description MARB is fixed MARB is incremented after a data transfer • • 1 0 1 W hen DTSZ = 0, MARB is incremented by 1 after a transfer W hen DTSZ = 1, MARB is incremented by 2 after a transfer (Initial value) MARB is fixed MARB is decremented after a data transfer • • W hen DTSZ = 0, MARB is decremented by 1 after a transfer W hen DTSZ = 1, MARB is decremented by 2 after a transfer Bit 4—Reserved: Can be read or written to. Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source). The factors that can be specified differ between normal mode and block transfer mode. • Normal Mode Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 1 1 0 1 1 Bit 0 DTF0 0 1 0 1 * 0 1 * * * Description — — Activated by — Activated by pin falling edge input pin low-level input (Initial value) Auto-request (cycle steal) Auto-request (burst) — *: Don't care Rev. 3.00 Jan 11, 2005 page 239 of 1220 REJ09B0186-0300O QERD QERD Section 8 DMA Controller • Block Transfer Mode Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 1 1 0 1 1 0 0 Bit 0 DTF0 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 0 1 1 0 1 Description — Activated by Activated by pin falling edge input* pin low-level input (Initial value) Activated by A/D converter conversion end interrupt Activated by SCI channel 0 transmit-data-empty interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmit-data-empty interrupt Activated by SCI channel 1 reception complete interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt — — Note: * Detected as a low level in the first transfer after transfer is enabled. The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 8.5.13, DMAC Multi-Channel Operation. Rev. 3.00 Jan 11, 2005 page 240 of 1220 REJ09B0186-0300O QERD QERD Section 8 DMA Controller 8.3.5 Bit DMA Band Control Register (DMABCR) : 15 FAE1 0 R/W 7 DTME1 0 R/W 14 FAE0 0 R/W 6 DTE1 0 R/W 13 — 0 R/W 5 DTME0 0 R/W 12 — 0 R/W 4 DTE0 0 R/W 11 DTA1 0 R/W 3 DTIE1B 0 R/W 10 — 0 R/W 2 DTIE1A 0 R/W 9 DTA0 0 R/W 1 DTIE0B 0 R/W 8 — 0 R/W 0 DTIE0A 0 R/W DMABCRH : Initial value : R/W Bit : : DMABCRL : Initial value : R/W : DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel. DMABCR is initialized to H'0000 by a reset, and in standby mode. Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short address mode or full address mode. In full address mode, channels 1A and 1B are used together as a single channel. Bit 15 FAE1 0 1 Description Short address mode Full address mode (Initial value) Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short address mode or full address mode. In full address mode, channels 0A and 0B are used together as a single channel. Bit 14 FAE0 0 1 Description Short address mode Full address mode (Initial value) Rev. 3.00 Jan 11, 2005 page 241 of 1220 REJ09B0186-0300O Section 8 DMA Controller Bits 13 and 12—Reserved: Can be read or written to. Bits 11 and 9—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the CPU or DTC. When the DTE = 1 and the DTA = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When the DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the CPU or DTC regardless of the DTA bit setting. The state of the DTME bit does not affect the above operations. Bit 11—Data Transfer Acknowledge 1 (DTA1): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1 data transfer factor setting. Bit 11 DTA1 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bit 9—Data Transfer Acknowledge 0 (DTA0): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0 data transfer factor setting. Bit 9 DTA0 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Rev. 3.00 Jan 11, 2005 page 242 of 1220 REJ09B0186-0300O Section 8 DMA Controller Bits 10 and 8—Reserved: Can be read or written to. Bits 7 and 5—Data Transfer Master Enable (DTME): Together with the DTE bit, these bits control enabling or disabling of data transfer on the relevant channel. When both the DTME bit and the DTE bit are set to 1, transfer is enabled for the channel. If the relevant channel is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU. When the DTME bit is subsequently set to 1 again, the interrupted transfer is resumed. In block transfer mode, however, the DTME bit is not cleared by an NMI interrupt, and transfer is not interrupted. The conditions for the DTME bit being cleared to 0 are as follows: • When initialization is performed • When NMI is input in burst mode • When 0 is written to the DTME bit The condition for DTME being set to 1 is as follows: • When 1 is written to DTME after DTME is read as 0 Bit 7—Data Transfer Master Enable 1 (DTME1): Enables or disables data transfer on channel 1. Bit 7 DTME1 0 1 Description Data transfer disabled. In burst mode, cleared to 0 by an NMI interrupt Data transfer enabled (Initial value) Bit 5—Data Transfer Master Enable 0 (DTME0): Enables or disables data transfer on channel 0. Bit 5 DTME0 0 1 Description Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt (Initial value) Data transfer enabled Rev. 3.00 Jan 11, 2005 page 243 of 1220 REJ09B0186-0300O Section 8 DMA Controller Bits 6 and 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU. The conditions for the DTE bit being cleared to 0 are as follows: • When initialization is performed • When the specified number of transfers have been completed • When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason When DTE = 1 and DTME = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the data transfer factor setting. When a request is issued by the activation source, DMA transfer is executed. The condition for the DTE bit being set to 1 is as follows: • When 1 is written to the DTE bit after the DTE bit is read as 0 Bit 6—Data Transfer Enable 1 (DTE1): Enables or disables data transfer on channel 1. Bit 6 DTE1 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bit 4—Data Transfer Enable 0 (DTE0): Enables or disables data transfer on channel 0. Bit 4 DTE0 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bits 3 and 1—Data Transfer Interrupt Enable B (DTIEB): These bits enable or disable an interrupt to the CPU or DTC when transfer is interrupted. If the DTIEB bit is set to 1 when DTME = 0, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC. A transfer break interrupt can be canceled either by clearing the DTIEB bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the DTME bit to 1. Rev. 3.00 Jan 11, 2005 page 244 of 1220 REJ09B0186-0300O Section 8 DMA Controller Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1 transfer break interrupt. Bit 3 DTIE1B 0 1 Description Transfer break interrupt disabled Transfer break interrupt enabled (Initial value) Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0 transfer break interrupt. Bit 1 DTIE0B 0 1 Description Transfer break interrupt disabled Transfer break interrupt enabled (Initial value) Bits 2 and 0—Data Transfer End Interrupt Enable A (DTIEA): These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If DTIEA bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIEA bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE bit to 1. Bit 2—Data Transfer End Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1 transfer end interrupt. Bit 2 DTIE1A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Rev. 3.00 Jan 11, 2005 page 245 of 1220 REJ09B0186-0300O Section 8 DMA Controller Bit 0—Data Transfer End Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0 transfer end interrupt. Bit 0 DTIE0A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) 8.4 8.4.1 Register Descriptions (3) DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions so that only specific bits of DMACR for the specific channel and also DMATCR and DMABCR can be changed to prevent inadvertent changes being made to registers other than those for the channel concerned. The restrictions applied by DMAWER are valid for the DTC. Figure 8.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt, and reactivating channel 0A. The address register and count register area is re-set by the first DTC transfer, then the control register area is re-set by the second DTC chain transfer. When re-setting the control register area, perform masking by setting bits in DMAWER to prevent modification of the contents of the other channels. Rev. 3.00 Jan 11, 2005 page 246 of 1220 REJ09B0186-0300O Section 8 DMA Controller First transfer area MAR0A IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A DTC IOAR1A ETCR1A MAR1B IOAR1B ETCR1B DMAWER DMACR0A DMACR1A Second transfer area using chain transfer DMATCR DMACR0B DMACR1B DMABCR Figure 8.2 Areas for Register Re-Setting by DTC (Example: Channel 0A) Bit : 7 — 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 WE1B 0 R/W 2 WE1A 0 R/W 1 WE0B 0 R/W 0 WE0A 0 R/W DMAWER : Initial value : R/W : DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to the DMACR, DMABCR, and DMATCR by the DTC. DMAWER is initialized to H'00 by a reset, and in standby mode. Bits 7 to 4—Reserved: These bits are always read as 0 and cannot be modified. Rev. 3.00 Jan 11, 2005 page 247 of 1220 REJ09B0186-0300O Section 8 DMA Controller Bit 3—Write Enable 1B (WE1B): Enables or disables writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR by the DTC. Bit 3 WE1B 0 1 Description Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are disabled (Initial value) Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are enabled Bit 2—Write Enable 1A (WE1A): Enables or disables writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR by the DTC. Bit 2 WE1A 0 1 Description Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are disabled (Initial value) Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are enabled Bit 1—Write Enable 0B (WE0B): Enables or disables writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR. Bit 1 WE0B 0 1 Description Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are disabled (Initial value) Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are enabled Bit 0—Write Enable 0A (WE0A): Enables or disables writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR. Bit 0 WE0A 0 1 Description Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled (Initial value) Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled Rev. 3.00 Jan 11, 2005 page 248 of 1220 REJ09B0186-0300O Section 8 DMA Controller Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the DMAWER settings. These bits should be changed, if necessary, by CPU processing. In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0. To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable B for the channel to be reactivated. MAR, IOAR, and ETCR are always write-enabled regardless of the DMAWER settings. When modifying these registers, the channel for which the modification is to be made should be halted. 8.4.2 Bit DMA Terminal Control Register (DMATCR) : 7 — 0 — 6 — 0 — 5 TEE1 0 R/W 4 TEE0 0 R/W 3 — 0 — 2 — 0 — 1 — 0 — 0 — 0 — DMATCR : Initial value : R/W : DMATCR is an 8-bit readable/writable register that controls enabling or disabling of DMAC transfer end pin output. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. DMATCR is initialized to H'00 by a reset, and in standby mode. Bits 7 and 6—Reserved: These bits are always read as 0 and cannot be modified. Bit 5 TEE1 0 1 Description pin output disabled pin output enabled (Initial value) Bit 4 TEE0 0 1 Description pin output disabled pin output enabled (Initial value) Rev. 3.00 Jan 11, 2005 page 249 of 1220 REJ09B0186-0300O 0DNET Bit 4—Transfer End Enable 0 (TEE0): Enables or disables transfer end pin 0 ( 1DNET Bit 5—Transfer End Enable 1 (TEE1): Enables or disables transfer end pin 1 ( ) output. 1DNET 1DNET 0DNET 0DNET ) output. Section 8 DMA Controller The transfer end signal indicates the transfer cycle in which the transfer counter reached 0, regardless of the transfer source. An exception is block transfer mode, in which the transfer end signal indicates the transfer cycle in which the block counter reached 0. Bits 3 to 0—Reserved: These bits are always read as 0 and cannot be modified. 8.4.3 Bit Initial value : R/W : MSTPCRA is an 8-bit readable/writable register that performs module stop mode control. When the MSTPA7 bit in MSTPCR is set to 1, the DMAC operation stops at the end of the bus cycle and a transition is made to module stop mode. For details, see section 24.5, Module Stop Mode. MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized by a manual reset and in software standby mode. Bit 7—Module Stop (MSTP7): Specifies the DMAC module stop mode. Bits 7 MSTPA7 0 1 Description DMAC module stop mode cleared DMAC module stop mode set (Initial value) Rev. 3.00 Jan 11, 2005 page 250 of 1220 REJ09B0186-0300O DNET The pins are assigned only to channel B in short address mode. Module Stop Control Register (MSTPCR) : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Section 8 DMA Controller 8.5 8.5.1 Operation Transfer Modes Table 8.5 lists the DMAC modes. Table 8.5 DMAC Transfer Modes Transfer Source TPU channel 0 to 5 compare match/input capture A interrupt SCI transmit-dataempty interrupt SCI reception complete • interrupt A/D converter conversion end interrupt External request • Remarks • • Up to 4 channels can operate independently External request applies to channel B only Single address mode applies to channel B only Modes (1), (2), and (3) can also be specified for single address mode Transfer Mode Short address mode Dual (1) Sequential mode • address mode (2) Idle mode (3) Repeat mode • • • • (4) Single address mode Full address mode (5) Normal mode (6) Block transfer mode • • • External request Auto-request TPU channel 0 to 5 compare match/input capture A interrupt SCI transmit-dataempty interrupt SCI reception complete interrupt A/D converter conversion end interrupt External request • Max. 2-channel operation, combining channels A and B With auto-request, burst mode transfer or cycle steal transfer can be selected • • • • • Rev. 3.00 Jan 11, 2005 page 251 of 1220 REJ09B0186-0300O Section 8 DMA Controller Operation in each mode is summarized below. (1) Sequential Mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. One address is specified as 24 bits, and the other as 16 bits. The transfer direction is programmable. (2) Idle Mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. One address is specified as 24 bits, and the other as 16 bits. The transfer source address and transfer destination address are fixed. The transfer direction is programmable. (3) Repeat Mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. When the specified number of transfers have been completed, the addresses and transfer counter are restored to their original settings, and operation is continued. No interrupt request is sent to the CPU or DTC. One address is specified as 24 bits, and the other as 16 bits. The transfer direction is programmable. (4) Single Address Mode In response to a single transfer request, the specified number of transfers are carried out between external memory and an external device, one byte or one word at a time. Unlike dual address mode, source and destination accesses are performed in parallel. Therefore, either the source or the destination is an external device which can be accessed with a strobe alone, using pin. One address is specified as 24 bits, and for the other, the pin is set the automatically. The transfer direction is programmable. Modes (1), (2) and (3) can also be specified for single address mode. (5) Normal Mode • Auto-request By means of register settings only, the DMAC is activated, and transfer continues until the specified number of transfers have been completed. An interrupt request can be sent to the CPU or DTC when transfer is completed. Both addresses are specified as 24 bits.  Cycle steal mode: The bus is released to another bus master every byte or word transfer. Rev. 3.00 Jan 11, 2005 page 252 of 1220 REJ09B0186-0300O KCAD Section 8 DMA Controller  Burst mode: The bus is held and transfer continued until the specified number of transfers have been completed. • External request In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. Both addresses are specified as 24 bits. (6) Block Transfer Mode In response to a single transfer request, a block transfer of the specified block size is carried out. This is repeated the specified number of times, once each time there is a transfer request. At the end of each single block transfer, one address is restored to its original setting. An interrupt request can be sent to the CPU or DTC when the specified number of block transfers have been completed. Both addresses are specified as 24 bits. 8.5.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 8.6 summarizes register functions in sequential mode. Rev. 3.00 Jan 11, 2005 page 253 of 1220 REJ09B0186-0300O Section 8 DMA Controller Table 8.6 Register Functions in Sequential Mode Function Register 23 MAR 23 H'FF 15 ETCR DTDIR = 0 DTDIR = 1 Initial Setting 0 Source Operation address register IOAR Destination Start address of Incremented/ address transfer destination decremented every register or transfer source transfer address register Fixed Start address of transfer source or transfer destination Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 15 0 Destination Source address register 0 Transfer counter Legend: MAR: IOAR: ETCR: DTDIR: Memory address register I/O address register Transfer count register Data transfer direction bit MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. Rev. 3.00 Jan 11, 2005 page 254 of 1220 REJ09B0186-0300O Section 8 DMA Controller Figure 8.3 illustrates operation in sequential mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N–1)) Where : L = Value set in MAR N = Value set in ETCR Figure 8.3 Operation in Sequential Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536. Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can be set for channel B only. Figure 8.4 shows an example of the setting procedure for sequential mode. Rev. 3.00 Jan 11, 2005 page 255 of 1220 REJ09B0186-0300O Section 8 DMA Controller [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set transfer source and transfer destination addresses [2] [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Clear the RPE bit to 0 to select sequential mode. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts with the DTIE bit. • Set the DTE bit to 1 to enable transfer. Sequential mode setting Set DMABCRH Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Sequential mode Figure 8.4 Example of Sequential Mode Setting Procedure Rev. 3.00 Jan 11, 2005 page 256 of 1220 REJ09B0186-0300O Section 8 DMA Controller 8.5.3 Idle Mode Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 8.7 summarizes register functions in idle mode. Table 8.7 Register Functions in Idle Mode Function Register 23 MAR 23 H'FF 15 ETCR 15 IOAR DTDIR = 0 DTDIR = 1 Initial Setting 0 Source Operation address register address register Destination Start address of Fixed address transfer destination register or transfer source address register Start address of Fixed transfer source or transfer destination Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 0 Destination Source 0 Transfer counter Legend: MAR: IOAR: ETCR: DTDIR: Memory address register I/O address register Transfer count register Data transfer direction bit MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is neither incremented nor decremented each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. Rev. 3.00 Jan 11, 2005 page 257 of 1220 REJ09B0186-0300O Section 8 DMA Controller Figure 8.5 illustrates operation in idle mode. MAR Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Figure 8.5 Operation in Idle Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536. Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can be set for channel B only. When the DMAC is used in single address mode, only channel B can be set. Rev. 3.00 Jan 11, 2005 page 258 of 1220 REJ09B0186-0300O Section 8 DMA Controller Figure 8.6 shows an example of the setting procedure for idle mode. Idle mode setting [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set DMABCRH Set transfer source and transfer destination addresses [2] Set number of transfers [3] [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Set the RPE bit to 1. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. • Set the DTIE bit to 1. • Set the DTE bit to 1 to enable transfer. Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Idle mode Figure 8.6 Example of Idle Mode Setting Procedure Rev. 3.00 Jan 11, 2005 page 259 of 1220 REJ09B0186-0300O Section 8 DMA Controller 8.5.4 Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 8.8 summarizes register functions in repeat mode. Table 8.8 Register Functions in Repeat Mode Function Register 23 MAR DTDIR = 0 DTDIR = 1 Initial Setting 0 Source Operation address register Destination Start address of Incremented/ address transfer destination decremented every register or transfer source transfer. Initial setting is restored when value reaches H'0000 address register Fixed Start address of transfer source or transfer destination Number of transfers Fixed 23 H'FF 15 IOAR 0 Destination Source address register transfers 7 ETCRH 0 Holds number of 7 ETCRL 0 Transfer counter Number of transfers Decremented every transfer. Loaded with ETCRH value when count reaches H'00 Legend: MAR: IOAR: ETCR: DTDIR: Memory address register I/O address register Transfer count register Data transfer direction bit Rev. 3.00 Jan 11, 2005 page 260 of 1220 REJ09B0186-0300O Section 8 DMA Controller MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. The number of transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when H'00 is set in both ETCRH and ETCRL, is 256. In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number of transfers. ETCRL is decremented by 1 each time a transfer is executed, and when its value reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR restoration operation is as shown below. MAR = MAR – (–1)DTID · 2DTSZ · ETCRH The same value should be set in ETCRH and ETCRL. In repeat mode, operation continues until the DTE bit is cleared. To end the transfer operation, therefore, you should clear the DTE bit to 0. A transfer end interrupt request is not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the transfer after that terminated when the DTE bit was cleared. Rev. 3.00 Jan 11, 2005 page 261 of 1220 REJ09B0186-0300O Section 8 DMA Controller Figure 8.7 illustrates operation in repeat mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N–1)) Where : L = Value set in MAR N = Value set in ETCR Figure 8.7 Operation in Repeat mode Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can be set for channel B only. Rev. 3.00 Jan 11, 2005 page 262 of 1220 REJ09B0186-0300O Section 8 DMA Controller Figure 8.8 shows an example of the setting procedure for repeat mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in both ETCRH and ETCRL. [2] [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Set the RPE bit to 1. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. • Clear the DTIE bit to 0. • Set the DTE bit to 1 to enable transfer. Repeat mode setting Set DMABCRH Set transfer source and transfer destination addresses Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Repeat mode Figure 8.8 Example of Repeat Mode Setting Procedure Rev. 3.00 Jan 11, 2005 page 263 of 1220 REJ09B0186-0300O Section 8 DMA Controller 8.5.5 Single Address Mode Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCR to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer ). The transfer direction can be specified by the DTDIR in DMACR. acknowledge pin ( Table 8.9 summarizes register functions in single address mode. Table 8.9 Register Functions in Single Address Mode Function Register 23 MAR pin 15 ETCR Legend: MAR: IOAR: ETCR: DTDIR: : Memory address register I/O address register Transfer count register Data transfer direction bit Data transfer acknowledge Note: * See the operation descriptions in sections 8.5.2, Sequential Mode, 8.5.3, Idle Mode, and 8.5.4, Repeat Mode. MAR specifies the start address of the transfer source or transfer destination as 24 bits. Rev. 3.00 Jan 11, 2005 page 264 of 1220 REJ09B0186-0300O KCAD IOAR is invalid; in its place the strobe for external devices ( KCAD DTDIR = 0 DTDIR = 1 Initial Setting 0 Source Operation address register Write strobe Destination Start address of * address transfer destination register or transfer source Read strobe (Set automatically Strobe for external by SAE bit; IOAR is device invalid) Number of transfers * KCAD KCAD 0 Transfer counter ) is output. Section 8 DMA Controller Figure 8.9 illustrates operation in single address mode (when sequential mode is specified). Address T Transfer DACK 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N–1)) Where : L = Value set in MAR N = Value set in ETCR Figure 8.9 Operation in Single Address Mode (When Sequential Mode is Specified) Rev. 3.00 Jan 11, 2005 page 265 of 1220 REJ09B0186-0300O Section 8 DMA Controller Figure 8.10 shows an example of the setting procedure for single address mode (when sequential mode is specified). [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Set the SAE bit to 1 to select single address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [2] Set the transfer source address/transfer destination address in MAR. [2] [3] Set the number of transfers in ETCR. [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Clear the RPE bit to 0 to select sequential mode. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. Read DMABCRL [5] [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts with the DTIE bit. • Set the DTE bit to 1 to enable transfer. Single address mode setting Set DMABCRH [1] Set transfer source and transfer destination addresses Set number of transfers [3] Set DMACR [4] Set DMABCRL [6] Single address mode Figure 8.10 Example of Single Address Mode Setting Procedure (When Sequential Mode is Specified) Rev. 3.00 Jan 11, 2005 page 266 of 1220 REJ09B0186-0300O Section 8 DMA Controller 8.5.6 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB. Table 8.10 summarizes register functions in normal mode. Table 8.10 Register Functions in Normal Mode Register 23 MARA 23 MARB Function 0 Source address Initial Setting Start address of transfer source Operation Incremented/decremented every transfer, or fixed register 0 Destination address register 0 Transfer counter Start address of Incremented/decremented transfer destination every transfer, or fixed Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 15 ETCRA Legend: MARA: Memory address register A MARB: Memory address register B ETCRA: Transfer count register A MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented each time a transfer is performed, and when its value reaches H'0000 the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536. Rev. 3.00 Jan 11, 2005 page 267 of 1220 REJ09B0186-0300O Section 8 DMA Controller Figure 8.11 illustrates operation in normal mode. Address TA Transfer Address TB Address BA Legend: Address Address Address Address Where : Address BB TA TB BA BB LA LB N = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (N–1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRA Figure 8.11 Operation in Normal Mode Transfer requests (activation sources) are external requests and auto-requests. With auto-request, the DMAC is only activated by register setting, and the specified number of transfers are performed automatically. With auto-request, cycle steal mode or burst mode can be selected. In cycle steal mode, the bus is released to another bus master each time a transfer is performed. In burst mode, the bus is held continuously until transfer ends. Rev. 3.00 Jan 11, 2005 page 268 of 1220 REJ09B0186-0300O Section 8 DMA Controller For setting details, see section 8.3.4, DMA Controller Register (DMACR). Figure 8.12 shows an example of the setting procedure for normal mode. [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the number of transfers in ETCRA. Set transfer source and transfer destination addresses [2] [4] Set each bit in DMACRA and DMACRB. • Set the transfer data size with the DTSZ bit. • Specify whether MARA is to be incremented, decremented, or fixed, with the SAID and SAIDE bits. • Clear the BLKE bit to 0 to select normal mode. • Specify whether MARB is to be incremented, decremented, or fixed, with the DAID and DAIDE bits. • Select the activation source with bits DTF3 to DTF0. [5] Read DTE = 0 and DTME = 0 in DMABCRL. Read DMABCRL [5] [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts with the DTIE bit. • Set both the DTME bit and the DTE bit to 1 to enable transfer. Normal mode setting Set DMABCRH Set number of transfers [3] Set DMACR [4] Set DMABCRL [6] Normal mode Figure 8.12 Example of Normal Mode Setting Procedure Rev. 3.00 Jan 11, 2005 page 269 of 1220 REJ09B0186-0300O Section 8 DMA Controller 8.5.7 Block Transfer Mode In block transfer mode, transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in DMACRA to 1. In block transfer mode, a transfer of the specified block size is carried out in response to a single transfer request, and this is executed the specified number of times. The transfer source is specified by MARA, and the transfer destination by MARB. Either the transfer source or the transfer destination can be selected as a block area (an area composed of a number of bytes or words). Table 8.11 summarizes register functions in block transfer mode. Table 8.11 Register Functions in Block Transfer Mode Register 23 MARA 23 MARB 0 0 Function Source address register Destination address register Initial Setting Start address of transfer source Operation Incremented/decremented every transfer, or fixed Start address of Incremented/decremented transfer destination every transfer, or fixed Block size Fixed 7 0 Holds block ETCRAH size Block size Block size Decremented every transfer; ETCRH value copied when count reaches H'00 Decremented every block transfer; transfer ends when count reaches H'0000 7 ETCRAL 15 ETCRB 0 counter 0 Block transfer counter Number of block transfers Legend: MARA: Memory address register A MARB: Memory address register B ETCRA: Transfer count register A ETCRB: Transfer count register B MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Rev. 3.00 Jan 11, 2005 page 270 of 1220 REJ09B0186-0300O Section 8 DMA Controller Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in DMACRA. To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL, and N in ETCRB. Figure 8.13 illustrates operation in block transfer mode when MARB is designated as a block area. Address TA 1st block Transfer Block area Address TB 2nd block Consecutive transfer of M bytes or words is performed in response to one request Address BB Nth block Address BA Legend: Address Address Address Address Where : TA TB BA BB LA LB N M = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (M·N–1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 8.13 Operation in Block Transfer Mode (BLKDIR = 0) Rev. 3.00 Jan 11, 2005 page 271 of 1220 REJ09B0186-0300O Section 8 DMA Controller Figure 8.14 illustrates operation in block transfer mode when MARA is designated as a block area. Address TA Block area Address BA Address TB Transfer Consecutive transfer of M bytes or words is performed in response to one request 2nd block 1st block Nth block Address BB Legend: Address Address Address Address Where : TA TB BA BB LA LB N M = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (N–1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (M·N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 8.14 Operation in Block Transfer Mode (BLKDIR = 1) Rev. 3.00 Jan 11, 2005 page 272 of 1220 REJ09B0186-0300O Section 8 DMA Controller ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA is restored in accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR. ETCRB is decremented by 1 every block transfer, and when the count reaches H'0000 the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this point, an interrupt request is sent to the CPU or DTC. Figure 8.15 shows the operation flow in block transfer mode. Rev. 3.00 Jan 11, 2005 page 273 of 1220 REJ09B0186-0300O Section 8 DMA Controller Start (DTE = DTME = 1) No Transfer request? Yes Acquire bus Read address specified by MARA MARA = MARA + SAIDE · (–1)SAID · 2DTSZ Write to address specified by MARB MARB = MARB + DAIDE · (–1)DAID · 2DTSZ ETCRAL = ETCRAL – 1 No ETCRAL = H'00 Yes Release bus ETCRAL = ETCRAH BLKDIR = 0 Yes No MARB = MARB – DAIDE · (–1)DAID · 2DTSZ · ETCRAH MARA = MARA – SAIDE · (–1)SAID · 2DTSZ · ETCRAH ETCRB = ETCRB – 1 No ETCRB = H'0000 Yes Clear DTE bit to 0 to end transfer Figure 8.15 Operation Flow in Block Transfer Mode Rev. 3.00 Jan 11, 2005 page 274 of 1220 REJ09B0186-0300O Section 8 DMA Controller Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. For details, see section 8.3.4, DMA Control Register (DMACR). Figure 8.16 shows an example of the setting procedure for block transfer mode. [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the block size in both ETCRAH and ETCRAL. Set the number of transfers in ETCRB. [4] Set each bit in DMACRA and DMACRB. • Set the transfer data size with the DTSZ bit. • Specify whether MARA is to be incremented, decremented, or fixed, with the SAID and SAIDE bits. • Set the BLKE bit to 1 to select block transfer mode. • Specify whether the transfer source or the transfer destination is a block area with the BLKDIR bit. • Specify whether MARB is to be incremented, decremented, or fixed, with the DAID and DAIDE bits. • Select the activation source with bits DTF3 to DTF0. [5] Read DTE = 0 and DTME = 0 in DMABCRL. Set DMABCRL [6] [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts to the CPU with the DTIE bit. • Set both the DTME bit and the DTE bit to 1 to enable transfer. Block transfer mode setting Set DMABCRH Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Block transfer mode Figure 8.16 Example of Block Transfer Mode Setting Procedure Rev. 3.00 Jan 11, 2005 page 275 of 1220 REJ09B0186-0300O Section 8 DMA Controller 8.5.8 DMAC Activation Sources DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The activation sources that can be specified depend on the transfer mode and the channel, as shown in table 8.12. Table 8.12 DMAC Activation Sources Short Address Mode Channels 0A and 1A O O O O O O O O O O O pin falling edge input pin low-level input × × × Channels 0B and 1B O O O O O O O O O O O O O × Full Address Mode Normal Mode × × × × × × × × × × × O O O Block Transfer Mode O O O O O O O O O O O O O × Activation Source Internal Interrupts ADI TXI0 RXI0 TXI1 RXI1 TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A External Requests Auto-request Legend: O : Can be specified × : Cannot be specified (1) Activation by Internal Interrupt An interrupt request selected as a DMAC activation source can be sent simultaneously to the CPU and DTC. For details, see section 5, Interrupt Controller. With activation by an internal interrupt, the DMAC accepts the request independently of the interrupt controller. Consequently, interrupt controller priority settings are not accepted. Rev. 3.00 Jan 11, 2005 page 276 of 1220 REJ09B0186-0300O QERD QERD Section 8 DMA Controller If the DMAC is activated by a CPU interrupt source or an interrupt source that is not used as a DTC activation source (DTA = 1), the interrupt source flag is cleared automatically by the DMA transfer. With ADI, TXI, and RXI interrupts, however, the interrupt source flag is not cleared unless the prescribed register is accessed in a DMA transfer. If the same interrupt is used as an activation source for more than one channel, the interrupt request flag is cleared when the highestpriority channel is activated first. Transfer requests for other channels are held pending in the DMAC, and activation is carried out in order of priority. When DTE = 0, such as after completion of a transfer, a request from the selected activation source is not sent to the DMAC, regardless of the DTA bit. In this case, the relevant interrupt request is sent to the CPU or DTC. In case of overlap with a CPU interrupt source or DTC activation source (DTA = 0), the interrupt request flag is not cleared by the DMAC. (2) Activation by External Request pin) is specified as an activation source, the relevant port should be If an external request ( set to input mode in advance. Level sensing or edge sensing can be used for external requests. External request operation in normal mode (short address mode or full address mode) is described below. When edge sensing is selected, a 1-byte or 1-word transfer is executed each time a high-to-low pin. The next transfer may not be performed if the next edge is transition is detected on the input before transfer is completed. pin is When level sensing is selected, the DMAC stands by for a transfer request while the held high. While the pin is held low, transfers continue in succession, with the bus being pin goes high in the middle of a released each time a byte or word is transferred. If the transfer, the transfer is interrupted and the DMAC stands by for a transfer request. (3) Activation by Auto-Request Auto-request activation is performed by register setting only, and transfer continues to the end. With auto-request activation, cycle steal mode or burst mode can be selected. In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is transferred. DMA and CPU cycles usually alternate. Rev. 3.00 Jan 11, 2005 page 277 of 1220 REJ09B0186-0300O QERD QERD QERD QERD QERD Section 8 DMA Controller In burst mode, the DMAC keeps possession of the bus until the end of the transfer, and transfer is performed continuously. (4) Single Address Mode The DMAC can operate in dual address mode in which read cycles and write cycles are separate cycles, or single address mode in which read and write cycles are executed in parallel. In dual address mode, transfer is performed with the source address and destination address specified separately. In single address mode, on the other hand, transfer is performed between external space in which either the transfer source or the transfer destination is specified by an address, and an external strobe, without regard to the device for which selection is performed by means of the address. Figure 8.17 shows the data bus in single address mode. RD HWR, LWR A23 to A0 Address bus (Read) External memory D15 to D0 (high impedance) Data bus H8S/2643 (Write) DACK Figure 8.17 Data Bus in Single Address Mode When using the DMAC for single address mode reading, transfer is performed from external memory to the external device, and the pin functions as a write strobe for the external device. When using the DMAC for single address mode writing, transfer is performed from the external device to external memory, and the pin functions as a read strobe for the external device. Since there is no directional control for the external device, one or other of the above single directions should be used. Rev. 3.00 Jan 11, 2005 page 278 of 1220 REJ09B0186-0300O KCAD External device KCAD KCAD Section 8 DMA Controller Bus cycles in single address mode are in accordance with the settings of the bus controller for the external memory area. On the external device side, is output in synchronization with the address strobe. For details of bus cycles, see section 8.5.11, DMAC Bus Cycles (Single Address Mode). Do not specify internal space for transfer addresses in single address mode. 8.5.9 Basic DMAC Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 8.18. In this example, wordsize transfer is performed from 16-bit , 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations. As with CPU cycles, DMA cycles conform to the bus controller settings. CPU cycle T1 φ Source address Address bus RD HWR LWR Destination address DMAC cycle (1-word transfer) T2 T1 T2 T3 T1 T2 T3 CPU cycle Figure 8.18 Example of DMA Transfer Bus Timing The address is not output to the external address bus in an access to on-chip memory or an internal I/O register. KCAD Rev. 3.00 Jan 11, 2005 page 279 of 1220 REJ09B0186-0300O Section 8 DMA Controller 8.5.10 DMAC Bus Cycles (Dual Address Mode) (1) Short Address Mode output is enabled and byte-size short Figure 8.19 shows a transfer example in which address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space. DMA read DMA write DMA read φ Address bus RD HWR LWR TEND Bus release Bus release Figure 8.19 Example of Short Address Mode Transfer A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released one or more bus cycles are inserted by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. Rev. 3.00 Jan 11, 2005 page 280 of 1220 REJ09B0186-0300O DNET output is enabled, In repeat mode, when which the transfer counter reaches 0. DNET DMA write DMA read DMA write DMA dead Bus release Last transfer cycle Bus release output goes low in the transfer cycle in DNET Section 8 DMA Controller (2) Full Address Mode (Cycle Steal Mode) output is enabled and word-size full address Figure 8.20 shows a transfer example in which mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. DMA read DMA write DMA read φ Address bus RD HWR LWR TEND Bus release Bus release Figure 8.20 Example of Full Address Mode (Cycle Steal) Transfer A one-byte or one-word transfer is performed, and after the transfer the bus is released. While the bus is released one bus cycle is inserted by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. DNET DMA write DMA read DMA write DMA dead Bus release Last transfer cycle Bus release Rev. 3.00 Jan 11, 2005 page 281 of 1220 REJ09B0186-0300O Section 8 DMA Controller (3) Full Address Mode (Burst Mode) output is enabled and word-size full address Figure 8.21 shows a transfer example in which mode transfer (burst mode) is performed from external 16-bit, 2-state access space to external 16bit, 2-state access space. DMA read φ Address bus RD HWR LWR TEND Bus release Burst transfer Last transfer cycle Bus release DMA write DMA read Figure 8.21 Example of Full Address Mode (Burst Mode) Transfer In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. If a request from another higher-priority channel is generated after burst transfer starts, that channel has to wait until the burst transfer ends. If an NMI is generated while a channel designated for burst transfer is in the transfer enabled state, the DTME bit is cleared and the channel is placed in the transfer disabled state. If burst transfer has already been activated inside the DMAC, the bus is released on completion of a one-byte or one-word transfer within the burst transfer, and burst transfer is suspended. If the last transfer cycle of the burst transfer has already been activated inside the DMAC, execution continues to the end of the transfer even if the DTME bit is cleared. Rev. 3.00 Jan 11, 2005 page 282 of 1220 REJ09B0186-0300O DNET DMA write DMA read DMA write DMA dead Section 8 DMA Controller (4) Full Address Mode (Block Transfer Mode) output is enabled and word-size full address Figure 8.22 shows a transfer example in which mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space. DMA read DMA write DMA read DMA write φ Address bus RD HWR LWR TEND Bus release Block transfer Bus release Last block transfer Bus release Figure 8.22 Example of Full Address Mode (Block Transfer Mode) Transfer A one-block transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released, one or more bus cycles are inserted by the CPU or DTC. In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a onestate DMA dead cycle is inserted after the DMA write cycle. One block is transmitted without interruption. NMI generation does not affect block transfer operation. DNET DMA dead DMA read DMA write DMA read DMA write DMA dead Rev. 3.00 Jan 11, 2005 page 283 of 1220 REJ09B0186-0300O Section 8 DMA Controller Bus release φ DREQ Address bus DMA control Channel Idle Request Transfer source Transfer destination Transfer source Transfer destination Read Minimum of 2 cycles [1] [2] [3] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the write cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. pin low level is sampled while acceptance by means of the pin is When the possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and pin high level sampling for edge detection is started. If pin high level sampling has been completed by the time the DMA write cycle ends, acceptance pin low level sampling is performed again, and resumes after the end of the write cycle, this operation is repeated until the transfer ends. Rev. 3.00 Jan 11, 2005 page 284 of 1220 REJ09B0186-0300O QERD QERD QERD QERD Figure 8.23 Example of QERD Figure 8.23 shows an example of pin falling edge activated normal mode transfer. DMA write Bus release DMA read DMA write Bus release DMA read Write Request clear period Acceptance resumes Pin Falling Edge Activated Normal Mode Transfer QERD Idle Set the DTA bit for the channel for which the QERD QERD QERD (5) Pin Falling Edge Activation Timing pin is selected to 1. Read Request Write Idle Request clear period Minimum of 2 cycles [4] [5] [6] [7] Acceptance resumes QERD Section 8 DMA Controller Bus release φ DREQ Address bus DMA control Channel Idle Request Transfer source Transfer destination Transfer source Transfer destination Read Request clear period Minimun of 2 cycles [1] [2] [3] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. pin low level is sampled while acceptance by means of the pin is When the possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the pin high level sampling for edge detection is started. If pin request is cleared, and high level sampling has been completed by the time the DMA dead cycle ends, acceptance resumes after the end of the dead cycle, pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev. 3.00 Jan 11, 2005 page 285 of 1220 REJ09B0186-0300O QERD QERD QERD QERD Figure 8.24 Example of QERD DMA read Write Figure 8.24 shows an example of pin falling edge activated block transfer mode transfer. 1 block transfer DMA write DMA Bus dead release 1 block transfer DMA read DMA write DMA dead Bus release Dead Idle Read Request Write Dead Idle Request clear period Minimun of 2 cycles [4] [5] [6] [7] Acceptance resumes Acceptance resumes Pin Falling Edge Activated Block Transfer Mode Transfer QERD QERD QERD Section 8 DMA Controller Bus release φ DREQ Address bus DMA control Channel Idle Request Transfer source Transfer destination Transfer source Transfer destination Read Request clear period Minimum of 2 cycles [1] [2] [3] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMA cycle is started. [4] [7] Acceptance is resumed after the write cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. pin low level is sampled while acceptance by means of the pin is When the possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the write cycle, acceptance resumes, pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev. 3.00 Jan 11, 2005 page 286 of 1220 REJ09B0186-0300O QERD QERD QERD Figure 8.25 Example of QERD Figure 8.25 shows an example of level activated normal mode transfer. DMA write Bus release DMA read DMA write Bus release DMA read Write Idle Request Acceptance resumes Level Activated Normal Mode Transfer QERD [4] Set the DTA bit for the channel for which the QERD QERD (6) Level Activation Timing (Normal Mode) pin is selected to 1. Read Write Idle Request clear period Minimum of 2 cycles [5] [6] [7] Acceptance resumes QERD Section 8 DMA Controller Bus release φ DREQ Address bus DMA control Channel Idle Request Transfer source Transfer destination Transfer source Transfer destination Read Request clear period Minimum of 2 cycles [1] [2] [3] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMA cycle is started. [4] [7] Acceptance is resumed after the dead cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. pin low level is sampled while acceptance by means of the pin is When the possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the pin low level request is cleared. After the end of the dead cycle, acceptance resumes, sampling is performed again, and this operation is repeated until the transfer ends. Rev. 3.00 Jan 11, 2005 page 287 of 1220 REJ09B0186-0300O QERD QERD QERD Figure 8.26 Example of QERD DMA read Write Figure 8.26 shows an example of level activated block transfer mode transfer. 1 block transfer DMA Bus dead release DMA read DMA right DMA dead Bus release 1 block transfer DMA right Dead Idle Read Request Write Dead Idle Request clear period Minimum of 2 cycles [4] [5] [6] [7] Acceptance resumes Acceptance resumes Level Activated Block Transfer Mode Transfer QERD QERD Section 8 DMA Controller 8.5.11 DMAC Bus Cycles (Single Address Mode) (1) Single Address Mode (Read) output is enabled and byte-size single Figure 8.27 shows a transfer example in which address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read φ Address bus RD DACK TEND DMA read Bus release Bus release Figure 8.27 Example of Single Address Mode (Byte Read) Transfer Rev. 3.00 Jan 11, 2005 page 288 of 1220 REJ09B0186-0300O DNET DMA read DMA DMA read dead Bus release Bus Last transfer cycle release Bus release Section 8 DMA Controller Figure 8.28 shows a transfer example in which output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read φ Address bus RD DACK TEND Bus release Bus release Figure 8.28 Example of Single Address Mode (Word Read) Transfer A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released, one or more bus cycles are inserted by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. DNET DMA read DMA read DMA dead Bus release Last transfer cycle Bus release Rev. 3.00 Jan 11, 2005 page 289 of 1220 REJ09B0186-0300O Section 8 DMA Controller (2) Single Address Mode (Write) output is enabled and byte-size single Figure 8.29 shows a transfer example in which address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write φ Address bus HWR LWR DACK TEND DMA write Bus release Bus release Figure 8.29 Example of Single Address Mode (Byte Write) Transfer Rev. 3.00 Jan 11, 2005 page 290 of 1220 REJ09B0186-0300O DNET DMA write DMA DMA write dead Bus release Bus Last transfer release cycle Bus release Section 8 DMA Controller Figure 8.30 shows a transfer example in which output is enabled and word-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write φ Address bus HWR LWR DACK TEND Bus release Bus release Figure 8.30 Example of Single Address Mode (Word Write) Transfer A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released one or more bus cycles are inserted by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. DNET DMA write DMA write DMA dead Bus release Last transfer cycle Bus release Rev. 3.00 Jan 11, 2005 page 291 of 1220 REJ09B0186-0300O Section 8 DMA Controller Bus release φ DREQ Address bus DACK DMA control Transfer source/ destination Transfer source/ destination Idle Channel Request Minimum of 2 cycles [1] [2] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the single cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. pin low level is sampled while acceptance by means of the pin is When the possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and pin high level sampling for edge detection is started. If pin high level sampling has been completed by the time the DMA single cycle ends, acceptance pin low level sampling is performed again, and resumes after the end of the single cycle, this operation is repeated until the transfer ends. Rev. 3.00 Jan 11, 2005 page 292 of 1220 REJ09B0186-0300O QERD QERD QERD QERD Figure 8.31 Example of QERD Figure 8.31 shows an example of pin falling edge activated single address mode transfer. DMA single Bus release DMA single Bus release Single Request clear period [3] Acceptance resumes Pin Falling Edge Activated Single Address Mode Transfer QERD Idle Set the DTA bit for the channel for which the QERD QERD QERD (3) Pin Falling Edge Activation Timing pin is selected to 1. Single Idle Request Minimum of 2 cycles Request clear period [4] [5] [6] [7] Acceptance resumes QERD Section 8 DMA Controller Bus release φ DREQ Address bus DACK DMA control Idle Channel Request Minimum of 2 cycles [1] [2] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMAC cycle is started. [4] [7] Acceptance is resumed after the single cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. pin low level is sampled while acceptance by means of the pin is When the possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the single cycle, acceptance resumes, pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev. 3.00 Jan 11, 2005 page 293 of 1220 REJ09B0186-0300O QERD QERD QERD Figure 8.32 Example of QERD Figure 8.32 shows an example of pin low level activated single address mode transfer. Bus release DMA single Transfer source/ destination Single Idle Request clear period [3] Acceptance resumes Pin Low Level Activated Single Address Mode Transfer QERD [4] Set the DTA bit for the channel for which the QERD QERD (4) Pin Low Level Activation Timing pin is selected to 1. Bus release DMA single Transfer source/ destination Single Idle Request Minimum of 2 cycles Request clear period [5] [6] [7] Acceptance resumes QERD Section 8 DMA Controller 8.5.12 Write Data Buffer Function DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved. When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel. Internal accesses are independent of the bus master, and DMAC dead cycles are regarded as internal accesses. pin if the bus cycle in which a low level is to be A low level can always be output from the output is an external bus cycle. However, a low level is not output from the pin if the bus cycle in which a low level is to be output from the pin is an internal bus cycle, and an external write cycle is executed in parallel with this cycle. Figure 8.33 shows an example of burst mode transfer from on-chip RAM to external memory using the write data buffer function. DMA read DMA write DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Internal address Internal read signal External address HWR, LWR TEND Figure 8.33 Example of Dual Address Transfer Using Write Data Buffer Function Figure 8.34 shows an example of single address transfer using the write data buffer function. In this example, the CPU program area is in on-chip memory. Rev. 3.00 Jan 11, 2005 page 294 of 1220 REJ09B0186-0300O DNET DNET DNET Section 8 DMA Controller DMA read DMA single CPU read DMA single CPU read φ Internal address Internal read signal External address RD DACK Figure 8.34 Example of Single Address Transfer Using Write Data Buffer Function When the write data buffer function is activated, the DMAC recognizes that the bus cycle pin sampling is started one concerned has ended, and starts the next operation. Therefore, state after the start of the DMA write cycle or single address transfer. 8.5.13 DMAC Multi-Channel Operation The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table 8.13 summarizes the priority order for DMAC channels. Table 8.13 DMAC Channel Priority Order Short Address Mode Channel 0A Channel 0B Channel 1A Channel 1B Channel 1 Low Full Address Mode Channel 0 Priority High Rev. 3.00 Jan 11, 2005 page 295 of 1220 REJ09B0186-0300O QERD Section 8 DMA Controller If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released the DMAC selects the highest-priority channel from among those issuing a request according to the priority order shown in table 8.13. During burst transfer, or when one block is being transferred in block transfer, the channel will not be changed until the end of the transfer. Figure 8.35 shows a transfer example in which transfer requests are issued simultaneously for channels 0A, 0B, and 1. DMA DMA write read DMA read φ Address bus RD HWR LWR DMA control Idle Read Channel 0A Channel 0B Channel 1 Bus release Write DMA write DMA read DMA write DMA read Idle Read Write Idle Read Write Read Request clear Request hold Request hold Selection Nonselection Request clear Request hold Bus release Selection Request clear Bus release Channel 1 transfer Channel 0A transfer Channel 0B transfer Figure 8.35 Example of Multi-Channel Transfer Rev. 3.00 Jan 11, 2005 page 296 of 1220 REJ09B0186-0300O Section 8 DMA Controller 8.5.14 Relation between External Bus Requests, Refresh Cycles, the DTC, and the DMAC There can be no break between a DMA cycle read and a DMA cycle write. This means that a refresh cycle, external bus release cycle, or DTC cycle is not generated between the external read and external write in a DMA cycle. In the case of successive read and write cycles, such as in burst transfer or block transfer, a refresh or external bus released state may be inserted after a write cycle. Since the DTC has a lower priority than the DMAC, the DTC does not operate until the DMAC releases the bus. When DMA cycle reads or writes are accesses to on-chip memory or internal I/O registers, these DMA cycles can be executed at the same time as refresh cycles or external bus release. However, simultaneous operation may not be possible when a write buffer is used. Rev. 3.00 Jan 11, 2005 page 297 of 1220 REJ09B0186-0300O Section 8 DMA Controller 8.5.15 NMI Interrupts and DMAC When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and the DTME bit are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested. If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the CPU. The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again. Figure 8.36 shows the procedure for continuing transfer when it has been interrupted by an NMI interrupt on a channel designated for burst mode transfer. Resumption of transfer on interrupted channel [1] [2] [1] No Check that DTE = 1 and DTME = 0 in DMABCRL. Write 1 to the DTME bit. DTE = 1 DTME = 0 Yes Set DTME bit to 1 [2] Transfer continues Transfer ends Figure 8.36 Example of Procedure for Continuing Transfer on Channel Interrupted by NMI Interrupt Rev. 3.00 Jan 11, 2005 page 298 of 1220 REJ09B0186-0300O Section 8 DMA Controller 8.5.16 Forced Termination of DMAC Operation If the DTE bit for the channel currently operating is cleared to 0, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit. Figure 8.37 shows the procedure for forcibly terminating DMAC operation by software. [1] Clear the DTE bit in DMABCRL to 0. If you want to prevent interrupt generation after forced termination of DMAC operation, clear the DTIE bit to 0 at the same time. Forced termination of DMAC Clear DTE bit to 0 [1] Forced termination Figure 8.37 Example of Procedure for Forcibly Terminating DMAC Operation Rev. 3.00 Jan 11, 2005 page 299 of 1220 REJ09B0186-0300O Section 8 DMA Controller 8.5.17 Clearing Full Address Mode Figure 8.38 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. [1] Clear both the DTE bit and the DTME bit in DMABCRL to 0; or wait until the transfer ends and the DTE bit is cleared to 0, then clear the DTME bit to 0. Also clear the corresponding DTIE bit to 0 at the same time. [2] Clear all bits in DMACRA and DMACRB to 0. [3] Clear the FAE bit in DMABCRH to 0. Initialize DMACR [2] Clearing full address mode Stop the channel [1] Clear FAE bit to 0 [3] Initialization; operation halted Figure 8.38 Example of Procedure for Clearing Full Address Mode Rev. 3.00 Jan 11, 2005 page 300 of 1220 REJ09B0186-0300O Section 8 DMA Controller 8.6 Interrupts The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 8.14 shows the interrupt sources and their priority order. Table 8.14 Interrupt Source Priority Order Interrupt Name DEND0A DEND0B DEND1A DEND1B Interrupt Source Short Address Mode Interrupt due to end of transfer on channel 0A Interrupt due to end of transfer on channel 0B Interrupt due to end of transfer on channel 1A Interrupt due to end of transfer on channel 1B Full Address Mode Interrupt due to end of transfer on channel 0 Interrupt due to break in transfer on channel 0 Interrupt due to end of transfer on channel 1 Interrupt due to break in transfer on channel 1 Low Interrupt Priority Order High Enabling or disabling of each interrupt source is set by means of the DTIE bit for the corresponding channel in DMABCR, and interrupts from each source are sent to the interrupt controller independently. The relative priority of transfer end interrupts on each channel is decided by the interrupt controller, as shown in table 8.14. Figure 8.39 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is always generated when the DTIE bit is set to 1 while DTE bit is cleared to 0. DTE/ DTME Transfer end/transfer break interrupt DTIE Figure 8.39 Block Diagram of Transfer End/Transfer Break Interrupt In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to 0 while DTIEB bit is set to 1. In both short address mode and full address mode, DMABCR should be set so as to prevent the occurrence of a combination that constitutes a condition for interrupt generation during setting. Rev. 3.00 Jan 11, 2005 page 301 of 1220 REJ09B0186-0300O Section 8 DMA Controller 8.7 Usage Notes (1) DMAC Register Access during Operation Except for forced termination, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, the DMAC register should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below. (a) DMAC control starts one cycle before the bus cycle, with output of the internal address. Consequently, MAR is updated in the bus cycle before DMAC transfer. Figure 8.40 shows an example of the update timing for DMAC registers in dual address transfer mode. DMA transfer cycle DMA last transfer cycle DMA dead DMA read φ DMA Internal address DMA control DMA register operation Idle Transfer destination Write DMA write DMA read DMA write Transfer source Read Transfer source Idle Read Transfer destination Write Dead Idle [1] [2] [1] [2]' [3] [1] Transfer source address register MAR operation (incremented/decremented/fixed) Transfer counter ETCR operation (decremented) Block size counter ETCR operation (decremented in block transfer mode) [2] Transfer destination address register MAR operation (incremented/decremented/fixed) [2'] Transfer destination address register MAR operation (incremented/decremented/fixed) Block transfer counter ETCR operation (decremented, in last transfer cycle of a block in block transfer mode) [3] Transfer address register MAR restore operation (in block or repeat transfer mode) Transfer counter ETCR restore (in repeat transfer mode) Block size counter ETCR restore (in block transfer mode) Notes: 1. In single address transfer mode, the update timing is the same as [1]. 2. The MAR operation is post-incrementing/decrementing of the DMA internal address value. Figure 8.40 DMAC Register Update Timing Rev. 3.00 Jan 11, 2005 page 302 of 1220 REJ09B0186-0300O Section 8 DMA Controller (b) If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC register is read as shown in figure 8.41. CPU longword read MAR upper word read φ DMA internal address DMA control DMA register operation Idle Transfe source Read Transfer destination Write MAR lower word read DMA transfer cycle DMA read DMA write Idle [1] [2] Note: The lower word of MAR is the updated value after the operation in [1]. Figure 8.41 Contention between DMAC Register Update and CPU Read (2) Module Stop When the MSTPA7 bit in MSTPCR is set to 1, the DMAC clock stops, and the module stop state is entered. However, 1 cannot be written to the MSTPA7 bit if any of the DMAC channels is enabled. This setting should therefore be made when DMAC operation is stopped. When the DMAC clock stops, DMAC register accesses can no longer be made. Since the following DMAC register settings are valid even in the module stop state, they should be invalidated, if necessary, before a module stop. • Transfer end/suspend interrupt (DTE = 0 and DTIE = 1) pin enable (TEE = 1) • • pin enable (FAE = 0 and SAE = 1) (3) Medium-Speed Mode When the DTA bit is 0, internal interrupt signals specified as DMAC transfer sources are edgedetected. In medium-speed mode, the DMAC operates on a medium-speed clock, while on-chip supporting modules operate on a high-speed clock. Consequently, if the period in which the relevant interrupt source is cleared by the CPU, DTC, or another DMAC channel, and the next interrupt is generated, is less than one state with respect to the DMAC clock (bus master clock), edge detection may not be possible and the interrupt may be ignored. Rev. 3.00 Jan 11, 2005 page 303 of 1220 REJ09B0186-0300O KCAD DNET Section 8 DMA Controller (4) Write Data Buffer Function When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel. (a) Write Data Buffer Function and DMAC Register Setting If the setting of is changed during execution of an external access by means of the write data buffer function, the external access may not be performed normally. The register that controls external accesses should only be manipulated when external reads, etc., are used with DMAC operation disabled, and the operation is not performed in parallel with external access. (b) Write Data Buffer Function and DMAC Operation Timing The DMAC can start its next operation during external access using the write data buffer function. pin sampling timing, output timing, etc., are different from the Consequently, the case in which the write data buffer function is disabled. Also, internal bus cycles maybe hidden, and not visible. pin if the bus cycle in which a low level is to be output A low level is not output from the from the pin is an internal bus cycle, and an external write cycle is executed in parallel with pin if the write this cycle. Note, for example, that a low level may not be output from the data buffer function is used when data transfer is performed between an internal I/O register and on-chip memory. If at least one of the DMAC transfer addresses is an external address, a low level is output from pin. the Rev. 3.00 Jan 11, 2005 page 304 of 1220 REJ09B0186-0300O DNET DNET (c) Write Data Buffer Function and Output DNET DNET QERD Also, in medium-speed mode, speed clock. pin sampling is performed on the rising edge of the medium- QERD DNET DNET Section 8 DMA Controller DMA read φ Internal address Internal read signal Internal write signal External address HWR, LWR TEND Not output External write by CPU, etc. pin falling edge detection is performed in synchronization with DMAC internal operations. The operation is as follows: pin, and [1] Activation request wait state: Waits for detection of a low level on the switches to [2]. [2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3]. [3] Activation request disabled state: Waits for detection of a high level on the pin, and switches to [1]. After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is enabled is performed by detection of a low level. (6) Activation Source Acceptance pin falling edge At the start of activation source acceptance, a low level is detected in both sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is Rev. 3.00 Jan 11, 2005 page 305 of 1220 REJ09B0186-0300O QERD QERD QERD QERD (5) Activation by Falling Edge on Pin DNET Figure 8.42 Example in Which Low Level is Not Output at DNET DMA write Figure 8.42 shows an example in which a low level is not output at the pin. Pin QERD Section 8 DMA Controller (7) Internal Interrupt after End of Transfer When the DTE bit is cleared to 0 by the end of transfer or an abort, the selected internal interrupt request will be sent to the CPU or DTC even if DTA is set to 1. Also, if internal DMAC activation has already been initiated when operation is aborted, the transfer is executed but flag clearing is not performed for the selected internal interrupt even if DTA is set to 1. An internal interrupt request following the end of transfer or an abort should be handled by the CPU as necessary. (8) Channel Re-Setting To reactivate a number of channels when multiple channels are enabled, use exclusive handling of transfer end interrupts, and perform DMABCR control bit operations exclusively. Note, in particular, that in cases where multiple interrupts are generated between reading and writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the DMABCR write data in the original interrupt handling routine will be incorrect, and the write may invalidate the results of the operations by the multiple interrupts. Ensure that overlapping DMABCR operations are not performed by multiple interrupts, and that there is no separation between read and write operations by the use of a bit-manipulation instruction. Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must first be read while cleared to 0 before the CPU can write a 1 to them. Rev. 3.00 Jan 11, 2005 page 306 of 1220 REJ09B0186-0300O QERD When the DMAC is activated, take any necessary steps to prevent an internal interrupt or pin low level remaining from the end of the previous transfer, etc. QERD detected. Therefore, a request is accepted from an internal interrupt or occurs before execution of the DMABCRL write to enable transfer. pin low level that Section 9 Data Transfer Controller (DTC) Section 9 Data Transfer Controller (DTC) 9.1 Overview The H8S/2643 Group includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 9.1.1 Features The features of the DTC are: • Transfer possible over any number of channels  Transfer information is stored in memory  One activation source can trigger a number of data transfers (chain transfer) • Wide range of transfer modes  Normal, repeat, and block transfer modes available  Incrementing, decrementing, and fixing of source and destination addresses can be selected • Direct specification of 16-Mbyte address space possible  24-bit transfer source and destination addresses can be specified • Transfer can be set in byte or word units • A CPU interrupt can be requested for the interrupt that activated the DTC  An interrupt request can be issued to the CPU after one data transfer ends  An interrupt request can be issued to the CPU after the specified data transfers have completely ended • Activation by software is possible • Module stop mode can be set  The initial setting enables DTC registers to be accessed. DTC operation is halted by setting module stop mode. Rev. 3.00 Jan 11, 2005 page 307 of 1220 REJ09B0186-0300O Section 9 Data Transfer Controller (DTC) 9.1.2 Block Diagram Figure 9.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1. Internal address bus Interrupt controller DTC On-chip RAM CPU interrupt request Legend: MRA, MRB: CRA, CRB: SAR: DAR DTCERA to DTCERF, DTCERI: DTVECR: DTC service request DTC mode registers A and B DTC transfer count registers A and B DTC source address register DTC destination address register DTC enable registers A to F and I DTC vector register Figure 9.1 Block Diagram of DTC Rev. 3.00 Jan 11, 2005 page 308 of 1220 REJ09B0186-0300O MRA MRB CRA CRB DAR SAR Interrupt request Internal data bus Register information DTCERA to DTCERF, DTCERI Control logic DTVECR Section 9 Data Transfer Controller (DTC) 9.1.3 Register Configuration Table 9.1 summarizes the DTC registers. Table 9.1 Name DTC mode register A DTC mode register B DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B DTC enable registers DTC vector register Module stop control register DTC Registers Abbreviation MRA MRB SAR DAR CRA CRB DTCER DTVECR MSTPCRA R/W —*2 —*2 —*2 —* 2 Initial Value Undefined Undefined Undefined Undefined Undefined Undefined H'00 H'00 H'3F Address*1 —*3 —*3 —*3 —*3 —*3 —*3 H'FE16 to H'FE1E H'FE1F H'FDE8 —*2 —*2 R/W R/W R/W Notes: 1. Lower 16 bits of the address. 2. Registers within the DTC cannot be read or written to directly. 3. Register information is located in on-chip RAM addresses H'EBC0 to H'EFBF. It cannot be located in external memory space. When the DTC is used, do not clear the RAME bit in SYSCR to 0. Rev. 3.00 Jan 11, 2005 page 309 of 1220 REJ09B0186-0300O Section 9 Data Transfer Controller (DTC) 9.2 9.2.1 Bit Register Descriptions DTC Mode Register A (MRA) : 7 SM1 Undefined — 6 SM0 Undefined — 5 DM1 Undefined — 4 DM0 Undefined — 3 MD1 Undefined — 2 MD0 Undefined — 1 DTS Undefined — 0 Sz Undefined — Initial value : R/W : MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer. Bit 7 SM1 0 1 Bit 6 SM0 — 0 1 Description SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented, decremented, or left fixed after a data transfer. Bit 5 DM1 0 1 Bit 4 DM0 — 0 1 Description DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) Rev. 3.00 Jan 11, 2005 page 310 of 1220 REJ09B0186-0300O Section 9 Data Transfer Controller (DTC) Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 MD1 0 1 Bit 2 MD0 0 1 0 1 Description Normal mode Repeat mode Block transfer mode — Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. Bit 1 DTS 0 1 Description Destination side is repeat area or block area Source side is repeat area or block area Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred. Bit 0 Sz 0 1 Description Byte-size transfer Word-size transfer Rev. 3.00 Jan 11, 2005 page 311 of 1220 REJ09B0186-0300O Section 9 Data Transfer Controller (DTC) 9.2.2 Bit DTC Mode Register B (MRB) : 7 CHNE Undefined — 6 DISEL Undefined — 5 — Undefined — 4 — Undefined — 3 — Undefined — 2 — Undefined — 1 — Undefined — 0 — Undefined — Initial value: R/W : MRB is an 8-bit register that controls the DTC operating mode. Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER is not performed. Bit 7 CHNE 0 1 Description End of DTC data transfer (activation waiting state is entered) DTC chain transfer (new register information is read, then data is transferred) Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are disabled or enabled after a data transfer. Bit 6 DISEL 0 1 Description After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 (the DTC clears the interrupt source flag of the activating interrupt to 0) After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the interrupt source flag of the activating interrupt to 0) Bits 5 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2643 Group, and should always be written with 0. Rev. 3.00 Jan 11, 2005 page 312 of 1220 REJ09B0186-0300O Section 9 Data Transfer Controller (DTC) 9.2.3 Bit DTC Source Address Register (SAR) : 23 22 21 20 19 4 3 2 1 0 Initial value: R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ————— Unde- Unde- Unde- Unde- Undefined fined fined fined fined ————— SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 9.2.4 Bit DTC Destination Address Register (DAR) : 23 22 21 20 19 4 3 2 1 0 Initial value : R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ————— Unde- Unde- Unde- Unde- Undefined fined fined fined fined ————— DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. 9.2.5 Bit DTC Transfer Count Register A (CRA) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined ———————————————— CRAH CRAL CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is Rev. 3.00 Jan 11, 2005 page 313 of 1220 REJ09B0186-0300O Section 9 Data Transfer Controller (DTC) transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is repeated. 9.2.6 Bit DTC Transfer Count Register B (CRB) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined ———————————————— CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. 9.2.7 Bit DTC Enable Register (DTCER) : 7 DTCE7 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTCE0 0 R/W Initial value: R/W : The DTC enable register comprises seven 8-bit readable/writable registers, DTCERA to DTCERF and DTCERI, with bits corresponding to the interrupt sources that can control enabling and disabling of DTC activation. These bits enable or disable DTC service for the corresponding interrupt sources. The DTC enable register is initialized to H'00 by a reset and in hardware standby mode. Rev. 3.00 Jan 11, 2005 page 314 of 1220 REJ09B0186-0300O Section 9 Data Transfer Controller (DTC) Bit n—DTC Activation Enable (DTCEn) Bit n DTCEn 0 Description DTC activation by this interrupt is disabled [Clearing conditions] • • 1 W hen the DISEL bit is 1 and the data transfer has ended W hen the specified number of transfers have ended (Initial value) DTC activation by this interrupt is enabled [Holding condition] • W hen the DISEL bit is 0 and the specified number of transfers have not ended (n = 7 to 0) A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources and DTCE bits is shown in table 9.4, together with the vector number generated for each interrupt controller. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. 9.2.8 Bit DTC Vector Register (DTVECR) : 7 0 R/(W)*1 6 0 R/W*2 5 0 R/W*2 4 0 R/W*2 3 0 R/W*2 2 0 R/W*2 1 0 R/W*2 0 0 R/W*2 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value: R/W : Notes: 1. Only 1 can be written to the SWDTE bit. 2. Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0. DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. DTVECR is initialized to H'00 by a reset and in hardware standby mode. Rev. 3.00 Jan 11, 2005 page 315 of 1220 REJ09B0186-0300O Section 9 Data Transfer Controller (DTC) Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. Bit 7 SWDTE 0 Description DTC software activation is disabled [Clearing conditions] • • 1 W hen the DISEL bit is 0 and the specified number of transfers have not ended W hen 0s written to the DISEL bit after a software-activated data transfer end interrupt (SWDTEND) request has been sent to the CPU (Initial value) DTC software activation is enabled [Holding conditions] • • • W hen the DISEL bit is 1 and data transfer has ended W hen the specified number of transfers have ended During data transfer due to software activation Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + ((vector number) 4 clocks. Figure 16.24 Example of Clocked Synchronous Transmission by DTC (8) Operation in Case of Mode Transition • Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. TSR, TDR, and SSR are reset. The output pin states in module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and becomes high-level output after the relevant mode is cleared. If a transition is made during transmission, the data being transmitted will be undefined. When transmitting without changing the transmit mode after the relevant mode is cleared, transmission can be started by setting TE to 1 again, and performing the following sequence: SSR read -> TDR write -> TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode, the procedure must be started again from initialization. Figure 16.25 shows a sample flowchart for mode transition during transmission. Port pin states are shown in figures 16.26 and 16.27. Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a transition from transmission by DTC transfer to module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. To perform transmission with the DTC after the relevant mode is cleared, setting TE and TIE to 1 will set the TXI flag and start DTC transmission. Rev. 3.00 Jan 11, 2005 page 690 of 1220 REJ09B0186-0300O Section 16 Serial Communication Interface (SCI, IrDA) • Reception Receive operation should be stopped (by clearing RE to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. RSR, RDR, and SSR are reset. If a transition is made without stopping operation, the data being received will be invalid. To continue receiving without changing the reception mode after the relevant mode is cleared, set RE to 1 before starting reception. To receive with a different receive mode, the procedure must be started again from initialization. Figure 16.28 shows a sample flowchart for mode transition during reception. Rev. 3.00 Jan 11, 2005 page 691 of 1220 REJ09B0186-0300O Section 16 Serial Communication Interface (SCI, IrDA) All data transmitted? Yes Read TEND flag in SSR No [1] TEND = 1 Yes TE = 0 [2] No [1] Data being transmitted is interrupted. After exiting software standby mode, etc., normal CPU transmission is possible by setting TE to 1, reading SSR, writing TDR, and clearing TDRE to 0, but note that if the DTC has been activated, the remaining data in DTCRAM will be transmitted when TE and TIE are set to 1. [2] If TIE and TEIE are set to 1, clear them to 0 in the same way. Transition to software standby mode, etc. Exit from software standby mode, etc. Change operating mode? Yes Initialization [3] [3] Includes module stop mode, watch mode, subactive mode, and subsleep mode. No TE = 1 Figure 16.25 Sample Flowchart for Mode Transition during Transmission Rev. 3.00 Jan 11, 2005 page 692 of 1220 REJ09B0186-0300O Section 16 Serial Communication Interface (SCI, IrDA) Transition to software standby Exit from software standby Start of transmission End of transmission TE bit SCK output pin Port input/output TxD output pin Port input/output Port High output Start SCI TxD output Stop Port input/output Port High output SCI TxD output Figure 16.26 Asynchronous Transmission Using Internal Clock Transition to software standby Exit from software standby Start of transmission End of transmission TE bit SCK output pin Port input/output TxD output pin Port input/output Port Marking output SCI TxD output Last TxD bit held Port input/output Port High output* SCI TxD output Note: * Initialized by software standby. Figure 16.27 Synchronous Transmission Using Internal Clock Rev. 3.00 Jan 11, 2005 page 693 of 1220 REJ09B0186-0300O Section 16 Serial Communication Interface (SCI, IrDA) Read RDRF flag in SSR No [1] [1] Receive data being received becomes invalid. RDRF = 1 Yes Read receive data in RDR RE = 0 Transition to software standby mode, etc. Exit from software standby mode, etc. Change operating mode? Yes Initialization [2] [2] Includes module stop mode, watch mode, subactive mode, and subsleep mode. No RE = 1 Figure 16.28 Sample Flowchart for Mode Transition during Reception Rev. 3.00 Jan 11, 2005 page 694 of 1220 REJ09B0186-0300O Section 16 Serial Communication Interface (SCI, IrDA) (9) Switching from SCK Pin Function to Port Pin Function: • Problem in Operation: When switching the SCK pin function to the output port function (highlevel output) by making the following settings while DDR = 1, DR = 1, C/ = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. End of serial data transmission 2. TE bit = 0 3. C/ bit = 0 ... switchover to port output 4. Occurrence of low-level output (see figure 16.29) Half-cycle low-level output SCK/port 1. End of transmission Data TE C/A CKE1 CKE0 Bit 6 Bit 7 2.TE = 0 4. Low-level output 3.C/A = 0 Figure 16.29 Operation when Switching from SCK Pin Function to Port Pin Function • Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/ = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown. 1. End of serial data transmission 2. TE bit = 0 3. CKE1 bit = 1 4. C/ bit = 0 ... switchover to port output 5. CKE1 bit = 0 Rev. 3.00 Jan 11, 2005 page 695 of 1220 REJ09B0186-0300O A A A A Section 16 Serial Communication Interface (SCI, IrDA) High-level outputTE SCK/port 1. End of transmission Data TE C/A 3.CKE1 = 1 CKE1 CKE0 5.CKE1 = 0 Bit 6 Bit 7 2.TE = 0 4.C/A = 0 Figure 16.30 Operation when Switching from SCK Pin Function to Port Pin Function (Example of Preventing Low-Level Output) Rev. 3.00 Jan 11, 2005 page 696 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface Section 17 Smart Card Interface 17.1 Overview SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 17.1.1 Features Features of the Smart Card interface supported by the H8S/2643 Group are as follows. • Asynchronous mode  Data length: 8 bits  Parity bit generation and checking  Transmission of error signal (parity error) in receive mode  Error signal detection and automatic data retransmission in transmit mode  Direct convention and inverse convention both supported • On-chip baud rate generator allows any bit rate to be selected • Three interrupt sources  Three interrupt sources (transmit data empty, receive data full, and transmit/receive error) that can issue requests independently  The transmit data empty interrupt and receive data full interrupt can activate the DMA controller (DMAC) or data transfer controller (DTC) to execute data transfer Rev. 3.00 Jan 11, 2005 page 697 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface 17.1.2 Block Diagram Figure 17.1 shows a block diagram of the Smart Card interface. Bus interface Module data bus Internal data bus RDR TDR RxD RSR TSR SCMR SSR SCR SMR Transmission/ reception control BRR φ Baud rate generator φ/4 φ/16 φ/64 Clock TxD Parity generation Parity check SCK TXI RXI ERI Legend: SCMR: RSR: RDR: TSR: TDR: SMR: SCR: SSR: BRR: Smart Card mode register Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Figure 17.1 Block Diagram of Smart Card Interface Rev. 3.00 Jan 11, 2005 page 698 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface 17.1.3 Pin Configuration Table 17.1 shows the Smart Card interface pin configuration. Table 17.1 Smart Card Interface Pins Channel 0 Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 1 Serial clock pin 1 Receive data pin 1 Transmit data pin 1 2 Serial clock pin 2 Receive data pin 2 Transmit data pin 2 3 Serial clock pin 3 Receive data pin 3 Transmit data pin 3 4 Serial clock pin 4 Receive data pin 4 Transmit data pin 4 Symbol SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 SCK2 RxD2 TxD2 SCK3 RxD3 TxD3 SCK4 RxD4 TxD4 I/O I/O Input Output I/O Input Output I/O Input Output I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output SCI3 clock input/output SCI3 receive data input SCI3 transmit data output SCI4 clock input/output SCI4 receive data input SCI4 transmit data output Rev. 3.00 Jan 11, 2005 page 699 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface 17.1.4 Register Configuration Table 17.2 shows the registers used by the Smart Card interface. Details of BRR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 16, Serial Communication Interface. Table 17.2 Smart Card Interface Registers Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Smart card mode register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Smart card mode register 1 2 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit data register 2 Serial status register 2 Receive data register 2 Smart card mode register 2 Abbreviation SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 SMR2 BRR2 SCR2 TDR2 SSR2 RDR2 SCMR2 R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R R/W 2 Initial Value H'00 H'FF H'00 H'FF H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'00 H'F2 Address*1 H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E R/(W)*2 H'84 R/(W)*2 H'84 Rev. 3.00 Jan 11, 2005 page 700 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface Channel 3 Name Serial mode register 3 Bit rate register 3 Serial control register 3 Transmit data register 3 Serial status register 3 Receive data register 3 Smart card mode register 3 4 Serial mode register 4 Bit rate register 4 Serial control register 4 Transmit data register 4 Serial status register 4 Receive data register 4 Smart card mode register 4 All Module stop control register B, C Abbreviation SMR3 BRR3 SCR3 TDR3 SSR3 RDR3 SCMR3 SMR4 BRR4 SCR4 TDR4 SSR4 RDR4 SCMR4 MSTPCRB MSTPCRC R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W 2 Initial Value H'00 H'FF H'00 H'FF H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'FF H'FF Address*1 H'FDD0 H'FDD1 H'FDD2 H'FDD3 H'FDD4 H'FDD5 H'FDD6 H'FDD8 H'FDD9 H'FDDA H'FDDB H'FDDC H'FDDD H'FDDE H'FDE9 H'FDEA R/(W)*2 H'84 Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. Rev. 3.00 Jan 11, 2005 page 701 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface 17.2 Register Descriptions Registers added with the Smart Card interface and bits for which the function changes are described here. 17.2.1 Bit Smart Card Mode Register (SCMR) : 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 SDIR 0 R/W 2 SINV 0 R/W 1 — 1 — 0 SMIF 0 R/W Initial value : R/W : SCMR is an 8-bit readable/writable register that selects the Smart Card interface function. SCMR is initialized to H'F2 by a reset and in standby mode. Bits 7 to 4—Reserved: These bits are always read as 1 and cannot be modified. Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3 SDIR 0 1 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) Rev. 3.00 Jan 11, 2005 page 702 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the SDIR bit for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 17.3.4, Register Settings. Bit 2 SINV 0 1 Description TDR contents are transmitted as they are Receive data is stored as it is in RDR TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR (Initial value) Bit 1—Reserved: This bit is always read as 1 and cannot be modified. Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the Smart Card interface function. Bit 0 SMIF 0 1 Description Smart Card interface function is disabled Smart Card interface function is enabled (Initial value) Rev. 3.00 Jan 11, 2005 page 703 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface 17.2.2 Bit Serial Status Register (SSR) : 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value : R/W : Note: * Only 0 can be written, to clear these flags. Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting conditions for bit 2, TEND, are also different. Bits 7 to 5—Operate in the same way as for the normal SCI. For details, see section 16.2.7, Serial Status Register (SSR). Bit 4—Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the error signal sent back from the receiving end in transmission. Framing errors are not detected in Smart Card interface mode. Bit 4 ERS 0 Description Normal reception, with no error signal [Clearing conditions] • • 1 Upon reset, and in standby mode or module stop mode W hen 0 is written to ERS after reading ERS = 1 (Initial value) Error signal sent from receiver indicating detection of parity error [Setting condition] • W hen the low level of the error signal is sampled Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state. Rev. 3.00 Jan 11, 2005 page 704 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 16.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit, are as shown below. Bit 2 TEND 0 Description Transmission is in progress [Clearing conditions] • • 1 W hen 0 is written to TDRE after reading TDRE = 1 W hen the DMAC or DTC is activated by a TXI interrupt and write data to TDR (Initial value) Transmission has ended [Setting conditions] • • • • • • Upon reset, and in standby mode or module stop mode W hen the TE bit in SCR is 0 and the ERS bit is also 0 W hen TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 0 W hen TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 1 W hen TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 0 W hen TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit) Rev. 3.00 Jan 11, 2005 page 705 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface 17.2.3 Bit Serial Mode Register (SMR) : 7 GM 0 R/W 6 BLK 0 R/W 5 PE 0 R/W 4 0 3 BCP1 0 R/W 2 BCP0 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : R/W Note: When the smart card interface is used, be sure to make the 1 setting shown for bit 5. The function of bits 7, 6, 3, and 2 of SMR changes in Smart Card interface mode. Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode. This bit is cleared to 0 when the normal smart card interface is used. In GSM mode, this bit is set to 1, the timing of setting of the TEND flag that indicates transmission completion is advanced and clock output control mode addition is performed. The contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control register (SCR). Bit 7 GM 0 Description Normal smart card interface mode operation • • 1 • • (Initial value) TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit Clock output ON/OFF control only TEND flag generation 11.0 etu after beginning of start bit High/low fixing control possible in addition to clock output ON/OFF control (set by SCR) GSM mode smart card interface mode operation Note: etu: Elementary time unit (time for transfer of 1 bit) Rev. 3.00 Jan 11, 2005 page 706 of 1220 REJ09B0186-0300O E O/ Section 17 Smart Card Interface Bit 6—Block Transfer Mode (BLK): Selects block transfer mode. Bit 6 BLK 0 Description Normal Smart Card interface mode operation • • • 1 • • • Error signal transmission/detection and automatic data retransmission performed TXI interrupt generated by TEND flag TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode) Error signal transmission/detection and automatic data retransmission not performed TXI interrupt generated by TDRE flag TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode) Block transfer mode operation Bits 3 and 2—Basic Clock Pulse 1 and 2 (BCP1, BCP0): These bits specify the number of basic clock periods in a 1-bit transfer interval on the Smart Card interface. Bit 3 BCP1 0 1 Bit 2 BCP0 1 0 1 0 Description 32 clock periods 64 clock periods 372 clock periods 256 clock periods (Initial value) Bits 5, 4, 1, and 0: Operate in the same way as for the normal SCI. For details, see section 16.2.5, Serial Mode Register (SMR). Rev. 3.00 Jan 11, 2005 page 707 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface 17.2.4 Bit Serial Control Register (SCR) : 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value : R/W : In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1. Bits 7 to 2—Operate in the same way as for the normal SCI. For details, see section 16.2.6, Serial Control Register (SCR). Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. In smart card interface mode, in addition to the normal switching between clock output enabling and disabling, the clock output can be specified as to be fixed high or low. SCMR SMIF 0 1 1 1 1 1 1 SMR C/ , GM See the SCI 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 Operates as port I/O pin Outputs clock as SCK output pin Operates as SCK output pin, with output fixed low Outputs clock as SCK output pin Operates as SCK output pin, with output fixed high Outputs clock as SCK output pin SCR Setting CKE1 CKE0 SCK Pin Function Rev. 3.00 Jan 11, 2005 page 708 of 1220 REJ09B0186-0300O A Section 17 Smart Card Interface 17.3 17.3.1 Operation Overview The main functions of the Smart Card interface are as follows. • One frame consists of 8-bit data plus a parity bit. • In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. • If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. • If the error signal is sampled during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. (except in block transfer mode). • Only asynchronous communication is supported; there is no clocked synchronous communication function. 17.3.2 Pin Connections Figure 17.2 shows a schematic diagram of Smart Card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected with the LSI pin. The data transmission line should be pulled up to the VCC power supply with a resistor. When the clock generated on the Smart Card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock. LSI port output is used as the reset signal. Other pins must normally be connected to the power supply or ground. Rev. 3.00 Jan 11, 2005 page 709 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface VCC TxD I/O RxD SCK Rx (port) H8S/2643 Group Connected equipment Data line Clock line Reset line CLK RST IC card Figure 17.2 Schematic Diagram of Smart Card Interface Pin Connections Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. Rev. 3.00 Jan 11, 2005 page 710 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface 17.3.3 Data Format (1) Normal Transfer Mode Figure 17.3 shows the normal Smart Card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. If an error signal is sampled during transmission, the same data is retransmitted. When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Transmitting station output Legend: Ds: D0 to D7: Dp: DE: Receiving station output Start bit Data bits Parity bit Error signal Figure 17.3 Normal Smart Card Interface Data Format Rev. 3.00 Jan 11, 2005 page 711 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the Smart Card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. [4] The receiving station carries out a parity check. If there is no parity error and the data is received normally, the receiving station waits for reception of the next data. If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. [5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. If it does receive an error signal, however, it returns to step [2] and retransmits the erroneous data. (2) Block Transfer Mode The operation sequence in block transfer mode is as follows. [1] When the data line in not in use it is in the high-impedance state, and is fixed high with a pullup resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the Smart Card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. [4] After reception, a parity error check is carried out, but an error signal is not output even if an error has occurred. When an error occurs reception cannot be continued, so the error flag should be cleared to 0 before the parity bit of the next frame is received. [5] The transmitting station proceeds to transmit the next data frame. Rev. 3.00 Jan 11, 2005 page 712 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface 17.3.4 Register Settings Table 17.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 17.3 Smart Card Interface Register Settings Bit Register SMR BRR SCR TDR SSR RDR SCMR Bit 7 GM BRR7 TIE TDR7 TDRE RDR7 — Bit 6 BLK BRR6 RIE TDR6 RDRF RDR6 — Bit 5 1 BRR5 TE TDR5 ORER RDR5 — Bit 4 Bit 3 BCP1 BRR3 0 TDR3 PER RDR3 SDIR Bit 2 BCP0 BRR2 0 TDR2 TEND RDR2 SINV Bit 1 CKS1 BRR1 CKE1* TDR1 0 RDR1 — Bit 0 CKS0 BRR0 CKE0 TDR0 0 RDR0 SMIF BRR4 RE TDR4 ERS RDR4 — Legend: —: Unused bit. *: The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0. (1) SMR Setting The GM bit is cleared to 0 in normal smart card interface mode, and set to 1 in GSM mode. The O/ bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. Bits BCP1 and BCP0 select the number of basic clock periods in a 1-bit transfer interval. For details, see section 17.3.5, Clock. The BLK bit is cleared to 0 in normal smart card interface mode, and set to 1 in block transfer mode. (2) BRR Setting BRR is used to set the bit rate. See section 17.3.5, Clock, for the method of calculating the value to be set. E O/ E Rev. 3.00 Jan 11, 2005 page 713 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface (3) SCR Setting The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI. For details, see section 16, Serial Communication Interface. Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in SMR is set to 1, clock output is performed. The clock output can also be fixed high or low. (4) Smart Card Mode Register (SCMR) Setting The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SMIF bit is set to 1 in the case of the Smart Card interface. Examples of register settings and the waveform of the start character are shown below for the two types of IC card (direct convention and inverse convention). • Direct convention (SDIR = SINV = O/ = 0) (Z) A Ds Z D0 Z D1 A D2 Z D3 With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. The parity bit is 1 since even parity is stipulated for the Smart Card. • Inverse convention (SDIR = SINV = O/ = 1) (Z) A Ds Z D7 Z D6 A D5 A D4 With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. The parity bit is 0, corresponding to state Z, since even parity is stipulated for the Smart Card. Rev. 3.00 Jan 11, 2005 page 714 of 1220 REJ09B0186-0300O E E Z D4 Z D5 A D6 A D7 Z Dp (Z) State A D3 A D2 A D1 A D0 Z Dp (Z) State Section 17 Smart Card Interface With the H8S/2643 Group, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/ bit in SMR is set to odd parity mode (the same applies to both transmission and reception). 17.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1, CKS0, BCP1 and BCP0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 17.5 shows some sample bit rates. If clock output is selected by setting CKE0 to 1, a clock is output from the SCK pin. The clock frequency is determined by the bit rate and the setting of bits BCP1 and BCP0. B= φ S×2 2n+1 × (N + 1) × 106 Where: N = Value set in BRR (0 ≤ N ≤ 255) B = Bit rate (bit/s) φ = Operating frequency (MHz) n = See table 17.4 S = Number of internal clocks in 1-bit period, set by BCP1 and BCP0 Table 17.4 Correspondence between n and CKS1, CKS0 n 0 1 2 3 1 CKS1 0 CKS0 0 1 0 1 E Rev. 3.00 Jan 11, 2005 page 715 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface Table 17.5 Examples of Bit Rate B (bit/s) for Various BRR Settings (When n = 0 and S = 372) φ (MHz) N 0 1 2 10.00 13441 6720 4480 10.714 14400 7200 4800 13.00 17473 8737 5824 14.285 19200 9600 6400 16.00 21505 10753 7168 18.00 24194 12097 8065 20.00 26882 13441 8961 25.00 33602 16801 11201 Note: Bit rates are rounded to the nearest whole number. The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 ≤ N ≤ 255, and the smaller error is specified. N= φ S×2 2n+1 ×B × 106 – 1 Table 17.6 Examples of BRR Settings for Bit Rate B (bit/s) (When n = 0 and S = 372) φ (MHz) 7.1424 bit/s 9600 N Error 0 0.00 10.00 N Error 1 30 10.7136 N Error 1 25 13.00 N Error 1 8.99 14.2848 N Error 1 0.00 16.00 N Error 1 12.01 18.00 N Error 2 15.99 20.00 N Error 2 6.60 25.00 N Error 3 12.49 Rev. 3.00 Jan 11, 2005 page 716 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372) φ (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 25.00 Maximum Bit Rate (bit/s) 9600 13441 14400 17473 19200 21505 24194 26882 33602 N 0 0 0 0 0 0 0 0 0 n 0 0 0 0 0 0 0 0 0 The bit rate error is given by the following formula: Error (%) = ( 17.3.6 φ S×2 2n+1 × B × (N + 1) × 106 – 1) × 100 Data Transfer Operations (1) Initialization Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0. [3] Set the GM, BLK, O/E, BCP1, BCP0, CKS1, CKS0 bits in SMR. Set the PE bit to 1. [4] Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. [5] Set the value corresponding to the bit rate in BRR. [6] Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. [7] Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. Rev. 3.00 Jan 11, 2005 page 717 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface (2) Serial Data Transmission As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 17.4 shows a flowchart for transmitting, and figure 17.5 shows the relation between a transmit operation and the internal registers. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ERS error flag in SSR is cleared to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the TEND flag in SSR is set to 1. [4] Write the transmit data to TDR, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. [5] When transmitting data continuously, go back to step [2]. [6] To end transmission, clear the TE bit to 0. With the above processing, interrupt servicing or data transfer by the DMAC or DTC is possible. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit data empty interrupt (TXI) request will be generated. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transfer error interrupt (ERI) request will be generated. The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag set timing is shown in figure 17.6. If the DMAC or DTC is activated by a TXI request, the number of bytes set in the DMAC or DTC can be transmitted automatically, including automatic retransmission. For details, see (6), Interrupt Operation (Except Block Transfer Mode), and (7), Data Transfer Operation by DMAC or DTC. Note: For block transfer mode, see section 16.3.2, Operation in Asynchronous Mode. Rev. 3.00 Jan 11, 2005 page 718 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface Start Initialization Start transmission ERS = 0? Yes No Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0 End Figure 17.4 Example of Transmission Processing Flow Rev. 3.00 Jan 11, 2005 page 719 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface TDR (1) Data write (2) Transfer from TDR to TSR (3) Serial data output Data 1 Data 1 Data 1 TSR (shift register) Data 1 ; Data remains in TDR Data 1 I/O signal line output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has been completed. Figure 17.5 Relation Between Transmit Operation and Internal Registers I/O data TXI (TEND interrupt) When GM = 0 Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Guard time 12.5etu When GM = 1 11.0etu Legend: Ds: D0 to D7: Dp: DE: Start bit Data bits Parity bit Error signal Figure 17.6 TEND Flag Generation Timing in Transmission Operation Rev. 3.00 Jan 11, 2005 page 720 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface (3) Serial Data Reception (Except Block Transfer Mode) Data reception in Smart Card mode uses the same processing procedure as for the normal SCI. Figure 17.7 shows an example of the transmission processing flow. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either is set, perform the appropriate receive error processing, then clear both the ORER and the PER flag to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the RDRF flag is set to 1. [4] Read the receive data from RDR. [5] When receiving data continuously, clear the RDRF flag to 0 and go back to step [2]. [6] To end reception, clear the RE bit to 0. Start Initialization Start reception ORER = 0 and PER = 0 Yes No Error processing No RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 17.7 Example of Reception Processing Flow Rev. 3.00 Jan 11, 2005 page 721 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface With the above processing, interrupt servicing or data transfer by the DMAC or DTC is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transfer error interrupt (ERI) request will be generated. If the DMAC or DTC is activated by an RXI request, the receive data in which the error occurred is skipped, and only the number of bytes of receive data set in the DMAC or DTC are transferred. For details, see (6), Interrupt Operation (Except Block Transfer Mode), and (7), Data Transfer Operation by DMAC or DTC. If a parity error occurs during reception and the PER is set to 1, the received data is still transferred to RDR, and therefore this data can be read. Note: For block transfer mode, see section 16.3.2, Operation in Asynchronous Mode. (4) Mode Switching Operation When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE bit to 0 and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE bit to 0 and setting RE bit to 1. The TEND flag can be used to check that the transmit operation has been completed. (5) Fixing Clock Output Level When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 17.8 shows the timing for fixing the clock output level. In this example, GM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled. Rev. 3.00 Jan 11, 2005 page 722 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface Specified pulse width Specified pulse width SCK SCR write (CKE0 = 0) SCR write (CKE0 = 1) Figure 17.8 Timing for Fixing Clock Output Level (6) Interrupt Operation (Except Block Transfer Mode) There are three interrupt sources in smart card interface mode: transmit data empty interrupt (TXI) requests, transfer error interrupt (ERI) requests, and receive data full interrupt (RXI) requests. The transmit end interrupt (TEI) request is not used in this mode. When the TEND flag in SSR is set to 1, a TXI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated. The relationship between the operating states and interrupt sources is shown in table 17.8. Note: For block transfer mode, see section 16.4, SCI Interrupts. Table 17.8 Smart Card Mode Operating States and Interrupt Sources Operating State Transmit Mode Receive Mode Normal operation Error Normal operation Error Flag TEND ERS RDRF PER, ORER Enable Bit TIE RIE RIE RIE Interrupt Source TXI ERI RXI ERI DMAC Activation Possible Not possible Possible Not possible DTC Activation Possible Not possible Possible Not possible (7) Data Transfer Operation by DMAC or DTC In smart card mode, as with the normal SCI, transfer can be carried out using the DMAC or DTC. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DMAC or DTC activation source, the DMAC or DTC will be activated by the TXI request, and transfer of the Rev. 3.00 Jan 11, 2005 page 723 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the DTC. In the event of an error, the SCI retransmits the same data automatically. During this period, TEND remains cleared to 0 and the DMAC is not activated. Therefore, the SCI and DMAC will automatically transmit the specified number of bytes, including retransmission in the event of an error. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. When performing transfer using the DMAC or DTC, it is essential to set and enable the DMAC or DTC before carrying out SCI setting. For details of the DMAC or DTC setting procedures, see section 8, DMA Controller (DMAC) and section 9, Data Transfer Controller (DTC). In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DMAC or DTC activation source, the DMAC or DTC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC or DTC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DMAC or DTC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared. Note: For block transfer mode, see section 16.4, SCI Interrupts. 17.3.7 Operation in GSM Mode (1) Switching the Mode When switching between smart card interface mode and software standby mode, the following switching procedure should be followed in order to maintain the clock duty. • When changing from smart card interface mode to software standby mode [1] Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. [2] Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. [3] Write 0 to the CKE0 bit in SCR to halt the clock. [4] Wait for one serial clock period. During this interval, clock output is fixed at the specified level, with the duty preserved. [5] Make the transition to the software standby state. Rev. 3.00 Jan 11, 2005 page 724 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface • When returning to smart card interface mode from software standby mode [6] Exit the software standby state. [7] Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the normal duty. Software standby Normal operation Normal operation [1] [2] [3] [4] [5] [6] [7] Figure 17.9 Clock Halt and Restart Procedure (2) Powering On To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. [2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR. [3] Set SMR and SCMR, and switch to smart card mode operation. [4] Set the CKE0 bit in SCR to 1 to start clock output. 17.3.8 Operation in Block Transfer Mode Operation in block transfer mode is the same as in SCI asynchronous mode, except for the following points. For details, see section 16.3.2, Operation in Asynchronous Mode. (1) Data Format The data format is 8 bits with parity. There is no stop bit, but there is a 2-bit (1-bit or more in reception) error guard time. Also, except during transmission (with start bit, data bits, and parity bit), the transmission pins go to the high-impedance state, so the signal lines must be fixed high with a pull-up resistor. Rev. 3.00 Jan 11, 2005 page 725 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface (2) Transmit/Receive Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock. The number of basic clock periods in a 1-bit transfer interval can be set to 32, 64, 372, or 256 with bits BCP1 and BCP0. For details, see section 17.3.5, Clock. (3) ERS (FER) Flag As with the normal Smart Card interface, the ERS flag indicates the error signal status, but since error signal transmission and reception is not performed, this flag is always cleared to 0. Rev. 3.00 Jan 11, 2005 page 726 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface 17.4 Usage Notes The following points should be noted when using the SCI as a Smart Card interface. (1) Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode In Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (as determined by bits BCP1 and BCP0). In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock. Figure 17.10 shows the receive data sampling timing when using a clock of 372 times the transfer rate. 372 clocks 186 clocks 0 185 371 0 185 371 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 17.10 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Transfer Rate) Rev. 3.00 Jan 11, 2005 page 727 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface Thus the reception margin in asynchronous mode is given by the following formula. Formula for reception margin in smart card interface mode M = (0.5 –  2N N Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, and 256) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin formula is as follows. When D = 0.5 and F = 0, M = (0.5 – 1/2 × 372) × 100% = 49.866% (2) Retransfer Operations (Except Block Transfer Mode) Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. • Retransfer operation when SCI is in receive mode Figure 17.11 illustrates the retransfer operation when the SCI is in receive mode. [1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [2] The RDRF bit in SSR is not set for a frame in which an error has occurred. [3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1. [4] If no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is generated. If DMAC or DTC data transfer by an RXI source is enabled, the contents of RDR can be read automatically. When the RDR data is read by the DMAC or DTC, the RDRF flag is automatically cleared to 0. [5] When a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission. Rev. 3.00 Jan 11, 2005 page 728 of 1220 REJ09B0186-0300O  ) – (L – 0.5) F –   1 D – 0.5 (1 + F) × 100% Section 17 Smart Card Interface nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1] Retransferred frame Transfer frame n+1 (DE) Ds D0 D1 D2 D3 D4 Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp [4] [3] Figure 17.11 Retransfer Operation in SCI Receive Mode • Retransfer operation when SCI is in transmit mode Figure 17.12 illustrates the retransfer operation when the SCI is in transmit mode. [6] If an error signal is sent back from the receiving end after transmission of one frame is completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality is received. [8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. [9] If an error signal is not sent back from the receiving end, transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt request is generated. If data transfer by the DMAC and DTC by means of the TXI source is enabled, the next data can be written to TDR automatically. When data is written to TDR by the DMAC or DTC, the TDRE bit is automatically cleared to 0. Transfer frame n+1 (DE) Ds D0 D1 D2 D3 D4 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE TDRE Transfer to TSR from TDR TEND [7] FER/ERS [6] Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transfer to TSR from TDR Transfer to TSR from TDR [9] [8] Figure 17.12 Retransfer Operation in SCI Transmit Mode Rev. 3.00 Jan 11, 2005 page 729 of 1220 REJ09B0186-0300O Section 17 Smart Card Interface Rev. 3.00 Jan 11, 2005 page 730 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Section 18 I2C Bus Interface [Option] A two-channel I2C bus interface is available as an option in the H8S/2643 Group. The I2C bus interface is not available for the H8S/2643 Group. Observe the following notes when using this option. For mask-ROM versions, a “W” is added to the part number in products in which this optional function is used. Examples: HD6432643WF 18.1 Overview A two-channel I2C bus interface is available for the H8S/2643 Group as an option. The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Each I2C bus interface channel uses only one data line (SDA) and one clock line (SCL) to transfer data, saving board and connector space. 18.1.1 Features • Selection of addressing format or non-addressing format  I2C bus format: addressing format with acknowledge bit, for master/slave operation • • • • • •  Serial format: non-addressing format without acknowledge bit, for master operation only Conforms to Philips I2C bus interface (I2C bus format) Two ways of setting slave address (I2C bus format) Start and stop conditions generated automatically in master mode (I2C bus format) Selection of acknowledge output levels when receiving (I2C bus format) Automatic loading of acknowledge bit when transmitting (I2C bus format) Wait function in master mode (I2C bus format)  A wait can be inserted by driving the SCL pin low after data transfer, excluding acknowledgement. The wait can be cleared by clearing the interrupt flag. Wait function in slave mode (I2C bus format)  A wait request can be generated by driving the SCL pin low after data transfer, excluding acknowledgement. The wait request is cleared when the next transfer becomes possible. • Rev. 3.00 Jan 11, 2005 page 731 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] • Three interrupt sources  Data transfer end (including transmission mode transition with I2C bus format and address reception after loss of master arbitration)  Address match: when any slave address matches or the general call address is received in slave receive mode (I2C bus format)  Stop condition detection • Selection of 16 internal clocks (in master mode) • Direct bus drive (with SCL and SDA pins)  Two pins—P35/SCL0 and P34/SDA0—(normally NMOS push-pull outputs) function as NMOS open-drain outputs when the bus drive function is selected.  Two pins—P33/SCL1 and P32/SDA1—(normally CMOS pins) function as NMOS-only outputs when the bus drive function is selected. 18.1.2 Block Diagram Figure 18.1 shows a block diagram of the I2C bus interface. Figure 18.2 shows an example of I/O pin connections to external circuits. Channel 0 I/O pins are NMOS open drains, and it is possible to apply voltages in excess of the power supply (PVCC) voltage for this LSI. Set the upper limit of voltage applied to the power supply (PVCC) power supply range + 0.3 V, i.e. 5.8 V. Channel 1 I/O pins are driven solely by NMOS, so in terms of appearance they carry out the same operations as an NMOS open drain. However, the voltage which can be applied to the I/O pins depends on the voltage of the power supply (PVCC) of this LSI. Rev. 3.00 Jan 11, 2005 page 732 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] φ SCL PS ICCR Clock control Noise canceler Bus state decision circuit Arbitration decision circuit ICMR ICSR ICDRT SDA Output data control circuit ICDRS ICDRR Noise canceler Address comparator SAR, SARX Legend: ICCR: I2C bus control register ICMR: I2C bus mode register ICSR: I2C bus status register ICDR: I2C bus data register SAR: Slave address register SARX: Second slave address register X Prescaler PS: Interrupt generator Interrupt request Figure 18.1 Block Diagram of I2C Bus Interface Rev. 3.00 Jan 11, 2005 page 733 of 1220 REJ09B0186-0300O Internal data bus Section 18 I2C Bus Interface [Option] VDD PVCC2 SCL SCL in SCL out SDA SCL SDA SDA in SDA out (Master) SCL SDA SCL in SCL out SCL in SCL out H8S/2643 Group chip SDA in SDA out (Slave 1) SDA in SDA out (Slave 2) Figure 18.2 I2C Bus Interface Connections (Example: H8S/2643 Group Chip as Master) 18.1.3 Input/Output Pins Table 18.1 summarizes the input/output pins used by the I2C bus interface. Table 18.1 I2C Bus Interface Pins Channel 0 1 Name Serial clock Serial data Serial clock Serial data Abbreviation SCL0 SDA0 SCL1 SDA1 I/O I/O I/O I/O I/O Function IIC0 serial clock input/output IIC0 serial data input/output IIC1 serial clock input/output IIC1 serial data input/output Note: In the text, the channel subscript is omitted, and only SCL and SDA are used. 18.1.4 Register Configuration Table 18.2 summarizes the registers of the I2C bus interface. Rev. 3.00 Jan 11, 2005 page 734 of 1220 REJ09B0186-0300O SCL SDA Section 18 I2C Bus Interface [Option] Table 18.2 Register Configuration Channel 0 Name I2C bus control register I2C bus status register I2C bus data register I C bus mode register Slave address register Second slave address register 1 I2C bus control register I C bus status register I2C bus data register I2C bus mode register Slave address register Second slave address register Common Serial control register X DDC switch register Module stop control register B 2 2 Abbreviation ICCR0 ICSR0 ICDR0 ICMR0 SAR0 SARX0 ICCR1 ICSR1 ICDR1 ICMR1 SAR1 SARX1 SCRX DDCSWR MSTPCRB R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'01 H'00 — H'00 H'00 H'01 H'01 H'00 — H'00 H'00 H'01 H'00 H'0F H'FF Address*1 H'FF78*3 H'FF79*3 H'FF7E*2*3 H'FF7F*2*3 H'FF7F*2*3 H'FF7E*2*3 H'FF80*3 H'FF81*3 H'FF86*2*3 H'FF87*2*3 H'FF87*2*3 H'FF86*2*3 H'FDB4 H'FDB5 H'FDE9 Notes: 1. Lower 16 bits of the address. 2. The register that can be written or read depends on the ICE bit in the I2C bus control 2 register. The slave address register can be accessed when ICE = 0, and the I C bus mode register can be accessed when ICE = 1. 3. The I2C bus interface registers are assigned to the same addresses as other registers. Register selection is performed by means of the IICE bit in the serial control register X (SCRX). Rev. 3.00 Jan 11, 2005 page 735 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] 18.2 18.2.1 Bit Register Descriptions I2C Bus Data Register (ICDR) : 7 ICDR7 — R/W 6 ICDR6 — R/W 5 ICDR5 — R/W 4 ICDR4 — R/W 3 ICDR3 — R/W 2 ICDR2 — R/W 1 ICDR1 — R/W 0 ICDR0 — R/W Initial value : R/W : • Bit ICDRR : 7 — R 6 — R 5 — R 4 — R 3 — R 2 — R 1 — R 0 — R ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0 Initial value : R/W : • Bit ICDRS : 7 — — 6 — — 5 — — 4 — — 3 — — 2 — — 1 — — 0 — — ICDRS7 ICDRS6 ICDRR5 ICDRS4 ICDRS3 ICDRS2 ICDRS1 ICDRS0 Initial value : R/W : • Bit ICDRT : 7 — W 6 — W 5 — W 4 — W 3 — W 2 — W 1 — W 0 — W ICDRT7 ICDRT6 ICDRT5 ICDRT4 ICDRT3 ICDRT2 ICDRT1 ICDRT0 Initial value : R/W : • Bit TDRE, RDRF (internal flags) : : : — TDRE Initial value R/W 0 — — RDRF 0 — ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is divided internally into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or Rev. 3.00 Jan 11, 2005 page 736 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] written by the CPU, ICDRR is read-only, and ICDRT is write-only. Data transfers among the three registers are performed automatically in coordination with changes in the bus state, and affect the status of internal flags such as TDRE and RDRF. If IIC is in transmit mode and the next data is in ICDRT (the TDRE flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred automatically from ICDRT to ICDRS. If IIC is in receive mode and no previous data remains in ICDRR (the RDRF flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred automatically from ICDRS to ICDRR. If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1. ICDR is assigned to the same address as SARX, and can be written and read only when the ICE bit is set to 1 in ICCR. The value of ICDR is undefined after a reset. The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the TDRE and RDRF flags affects the status of the interrupt flags. Rev. 3.00 Jan 11, 2005 page 737 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] TDRE 0 Description The next transmit data is in ICDR (ICDRT), or transmission cannot be started [Clearing conditions] • • • • W hen transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1) W hen a stop condition is detected in the bus line state after a stop condition is issued with the I2C bus format or serial format selected 2 W hen a stop condition is detected with the I C bus format selected (Initial value) In receive mode (TRS = 0) (A 0 write to TRS during transfer is valid after reception of a frame containing an acknowledge bit) 1 The next transmit data can be written in ICDR (ICDRT) [Setting conditions] • In transmit mode (TRS = 1), when a start condition is detected in the bus line state after a start condition is issued in master mode with the I2C bus format or serial format selected W hen using formatless mode in transmit mode (TRS = 1) W hen data is transferred from ICDRT to ICDRS (Data transfer from ICDRT to ICDRS when TRS = 1 and TDRE = 0, and ICDRS is empty) • W hen a switch is made from receive mode (TRS = 0) to transmit mode (TRS = 1 ) after detection of a start condition • • RDRF 0 Description The data in ICDR (ICDRR) is invalid [Clearing condition] • W hen ICDR (ICDRR) receive data is read in receive mode (Initial value) 1 The ICDR (ICDRR) receive data can be read [Setting condition] • W hen data is transferred from ICDRS to ICDRR (Data transfer from ICDRS to ICDRR in case of normal termination with TRS = 0 and RDRF = 0) Rev. 3.00 Jan 11, 2005 page 738 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] 18.2.2 Bit Slave Address Register (SAR) : 7 SVA6 0 R/W 6 SVA5 0 R/W 5 SVA4 0 R/W 4 SVA3 0 R/W 3 SVA2 0 R/W 2 SVA1 0 R/W 1 SVA0 0 R/W 0 FS 0 R/W Initial value : R/W : SAR is an 8-bit readable/writable register that stores the slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. SAR is assigned to the same address as ICMR, and can be written and read only when the ICE bit is cleared to 0 in ICCR. SAR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 1—Slave Address (SVA6 to SVA0): Set a unique address in bits SVA6 to SVA0, differing from the addresses of other slave devices connected to the I2C bus. Bit 0—Format Select (FS): Used together with the FSX bit in SARX to select the communication format. • I2C bus format: addressing format with acknowledge bit • Synchronous serial format: non-addressing format without acknowledge bit, for master mode only The FS bit also specifies whether or not SAR slave address recognition is performed in slave mode. Rev. 3.00 Jan 11, 2005 page 739 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] SAR Bit 0 FS 0 SARX Bit 0 FSX 0 1 Operating Mode I2C bus format • • • 1 0 • • 1 • SAR and SARX slave addresses recognized (Initial value) SAR slave address recognized SARX slave address ignored SAR slave address ignored SARX slave address recognized SAR and SARX slave addresses ignored I2C bus format I2C bus format Synchronous serial format 18.2.3 Bit Second Slave Address Register (SARX) : 7 SVAX6 0 R/W 6 SVAX5 0 R/W 5 SVAX4 0 R/W 4 SVAX3 0 R/W 3 SVAX2 0 R/W 2 SVAX1 0 R/W 1 SVAX0 0 R/W 0 FSX 1 R/W Initial value : R/W : SARX is an 8-bit readable/writable register that stores the second slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. SARX is assigned to the same address as ICDR, and can be written and read only when the ICE bit is cleared to 0 in ICCR. SARX is initialized to H'01 by a reset and in hardware standby mode. Bits 7 to 1—Second Slave Address (SVAX6 to SVAX0): Set a unique address in bits SVAX6 to SVAX0, differing from the addresses of other slave devices connected to the I2C bus. Bit 0—Format Select X (FSX): Used together with the FS bit in SAR to select the communication format. • I2C bus format: addressing format with acknowledge bit • Synchronous serial format: non-addressing format without acknowledge bit, for master mode only Rev. 3.00 Jan 11, 2005 page 740 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] The FSX bit also specifies whether or not SARX slave address recognition is performed in slave mode. For details, see the description of the FS bit in SAR. 18.2.4 Bit I2C Bus Mode Register (ICMR) : 7 MLS 0 R/W 6 WAIT 0 R/W 5 CKS2 0 R/W 4 CKS1 0 R/W 3 CKS0 0 R/W 2 BC2 0 R/W 1 BC1 0 R/W 0 BC0 0 R/W Initial value : R/W : ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the master mode transfer clock frequency and the transfer bit count. ICMR is assigned to the same address as SAR. ICMR can be written and read only when the ICE bit is set to 1 in ICCR. ICMR is initialized to H'00 by a reset and in hardware standby mode. Bit 7—MSB-First/LSB-First Select (MLS): Selects whether data is transferred MSB-first or LSB-first. If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1. Do not set this bit to 1 when the I2C bus format is used. Bit 7 MLS 0 1 Description MSB-first LSB-first (Initial value) Rev. 3.00 Jan 11, 2005 page 741 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Bit 6—Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data and the acknowledge bit, in master mode with the I2C bus format. When WAIT is set to 1, after the fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the acknowledge bit is transferred. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. The IRIC flag in ICCR is set to 1 on completion of the acknowledge bit transfer, regardless of the WAIT setting. The setting of this bit is invalid in slave mode. Bit 6 WAIT 0 1 Description Data and acknowledge bits transferred consecutively Wait inserted between data and acknowledge bits (Initial value) Rev. 3.00 Jan 11, 2005 page 742 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Bits 5 to 3—Serial Clock Select (CKS2 to CKS0): These bits, together with the IICX1 (channel 1) or IICX0 (channel 0) bit in the SCRX register, select the serial clock frequency in master mode. They should be set according to the required transfer rate. SCRX Bit 5 or 6 Bit 5 IICX 0 Bit 4 Bit 3 φ= 8 MHz 286 kHz 200 kHz 167 kHz Transfer Rate φ= 10 MHz φ= 16 MHz φ= 20 MHz φ= 25 MHz φ= CKS2 CKS1 CKS0 Clock 5 MHz 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 φ/28 φ/40 φ/48 φ/64 φ/80 179 kHz 125 kHz 104 kHz 357 kHz 571 kHz* 714 kHz* 893 kHz* 250 kHz 400 kHz 500 kHz* 625 kHz* 208 kHz 333 kHz 417 kHz* 521 kHz* 156 kHz 250 kHz 313 kHz 391 kHz 125 kHz 200 kHz 250 kHz 313 kHz 78.1 kHz 125 kHz 62.5 kHz 100 kHz φ/100 50.0 kHz 80.0 kHz 100 kHz 160 kHz 200 kHz 250 kHz φ/112 44.6 kHz 71.4 kHz 89.3 kHz 143 kHz 179 kHz 223 kHz φ/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz 195 kHz φ/56 φ/80 φ/96 89.3 kHz 143 kHz 62.5 kHz 100 kHz 179 kHz 286 kHz 357 kHz 446 kHz 125 kHz 200 kHz 250 kHz 313 kHz 1 0 0 52.1 kHz 83.3 kHz 104 kHz 167 kHz 208 kHz 260 kHz φ/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz 195 kHz φ/160 31.3 kHz 50.0 kHz 62.5 kHz 100 kHz 125 kHz 156 kHz φ/200 25.0 kHz 40.0 kHz 50.0 kHz 80.0 kHz 100 kHz 125 kHz φ/224 22.3 kHz 35.7 kHz 44.6 kHz 71.4 kHz 89.3 kHz 112 kHz φ/256 19.5 kHz 31.3 kHz 39.1 kHz 62.5 kHz 78.1 kHz 97.7 kHz Note: * Outside the allowable range for the I2C bus interface standard (normal mode: max. 100 kHz, high-speed mode: max. 400 kHz). Bits 2 to 0—Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to be transferred next. With the I2C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low. The bit counter is initialized to 000 by a reset and when a start condition is detected. The value returns to 000 at the end of a data transfer, including the acknowledge bit. Rev. 3.00 Jan 11, 2005 page 743 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Bit 2 BC2 0 Bit 1 BC1 0 1 1 0 1 Bit 0 BC0 0 1 0 1 0 1 0 1 Bits/Frame Synchronous Serial Format 8 1 2 3 4 5 6 7 I2C Bus Format 9 2 3 4 5 6 7 8 (Initial value) 18.2.5 Bit I2C Bus Control Register (ICCR) : 7 ICE 0 R/W 6 IEIC 0 R/W 5 MST 0 R/W 4 TRS 0 R/W 3 ACKE 0 R/W 2 BBSY 0 R/W 1 IRIC 0 R/(W)* 0 SCP 1 W Initial value : R/W : Note: * Only 0 can be written, for flag clearing. ICCR is an 8-bit readable/writable register that enables or disables the I2C bus interface, enables or disables interrupts, selects master or slave mode and transmission or reception, enables or disables acknowledgement, confirms the I2C bus interface bus status, issues start/stop conditions, and performs interrupt flag confirmation. ICCR is initialized to H'01 by a reset and in hardware standby mode. Bit 7—I2C Bus Interface Enable (ICE): Selects whether or not the I2C bus interface is to be used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer operations are enabled. When ICE is cleared to 0, the I2C bus interface module is halted and its internal states are cleared. The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers can be accessed when ICE is 1. Rev. 3.00 Jan 11, 2005 page 744 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Bit 7 ICE 0 Description I2C bus interface module disabled, with SCL and SDA signal pins set to port function I2C bus interface module internal states initialized SAR and SARX can be accessed 1 I2C bus interface module enabled for transfer operations (pins SCL and SDA are driving the bus) ICMR and ICDR can be accessed (Initial value) Bit 6—I2C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I2C bus interface to the CPU. Bit 6 IEIC 0 1 Description Interrupts disabled Interrupts enabled (Initial value) Bit 5—Master/Slave Select (MST) Bit 4—Transmit/Receive Select (TRS) MST selects whether the I2C bus interface operates in master mode or slave mode. TRS selects whether the I2C bus interface operates in transmit mode or receive mode. In master mode with the I2C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. In slave receive mode with the addressing format (FS = 0 or FSX = 0), hardware automatically selects transmit or receive mode according to the R/W bit in the first frame after a start condition. Modification of the TRS bit during transfer is deferred until transfer of the frame containing the acknowledge bit is completed, and the changeover is made after completion of the transfer. MST and TRS select the operating mode as follows. Rev. 3.00 Jan 11, 2005 page 745 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Bit 5 MST 0 1 Bit 4 TRS 0 1 0 1 Bit 5 MST 0 Description Slave mode [Clearing conditions] 1. When 0 is written by software 2. When bus arbitration is lost after transmission is started in I2C bus format master mode 1 Master mode [Setting conditions] 1. When 1 is written by software (in cases other than clearing condition 2) 2. When 1 is written in MST after reading MST = 0 (in case of clearing condition 2) Bit 4 TRS 0 Description Receive mode [Clearing conditions] 1. When 0 is written by software (in cases other than setting condition 3) 2. When 0 is written in TRS after reading TRS = 1 (in case of clearing condition 3) 2 3. When bus arbitration is lost after transmission is started in I C bus format master mode Operating Mode Slave receive mode Slave transmit mode Master receive mode Master transmit mode (Initial value) (Initial value) (Initial value) 1 Transmit mode [Setting conditions] 1. When 1 is written by software (in cases other than clearing condition 3) 2. When 1 is written in TRS after reading TRS = 0 (in case of clearing condition 3) 2 3. When a 1 is received as the R/W bit of the first frame in I C bus format slave mode Rev. 3.00 Jan 11, 2005 page 746 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Bit 3—Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the acknowledge bit returned from the receiving device when using the I2C bus format is to be ignored and continuous transfer is performed, or transfer is to be aborted and error handling, etc., performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received acknowledge bit is not indicated by the ACKB bit, which is always 0. In the H8S/2643 Group, the DTC can be used to perform continuous transfer. The DTC is activated when the IRTR interrupt flag is set to 1 (IRTR is one of two interrupt flags, the other being IRIC). When the ACKE bit is 0, the TDRE, IRIC, and IRTR flags are set on completion of data transmission, regardless of the value of the acknowledge bit. When the ACKE bit is 1, the TDRE, IRIC, and IRTR flags are set on completion of data transmission when the acknowledge bit is 0, and the IRIC flag alone is set on completion of data transmission when the acknowledge bit is 1. When the DTC is activated, the TDRE, IRIC, and IRTR flags are cleared to 0 after the specified number of data transfers have been executed. Consequently, interrupts are not generated during continuous data transfer, but if data transmission is completed with a 1 acknowledge bit when the ACKE bit is set to 1, the DTC is not activated and an interrupt is generated, if enabled. Depending on the receiving device, the acknowledge bit may be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance. Bit 3 ACKE 0 1 Description The value of the acknowledge bit is ignored, and continuous transfer is performed If the acknowledge bit is 1, continuous transfer is interrupted (Initial value) Bit 2—Bus Busy (BBSY): The BBSY flag can be read to check whether the I2C bus (SCL, SDA) is busy or free. In master mode, this bit is also used to issue start and stop conditions. A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting BBSY to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition, clearing BBSY to 0. To issue a start condition, use a MOV instruction to write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, use a MOV instruction to write 0 in BBSY and 0 in SCP. It is not possible to write to BBSY in slave mode; the I2C bus interface must be set to master transmit mode before issuing a start condition. MST and TRS should both be set to 1 before writing 1 in BBSY and 0 in SCP. Rev. 3.00 Jan 11, 2005 page 747 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Bit 2 BBSY 0 Description Bus is free [Clearing condition] • 1 W hen a stop condition is detected Bus is busy [Setting condition] • W hen a start condition is detected (Initial value) Bit 1—I2C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I2C bus interface has issued an interrupt request to the CPU. IRIC is set to 1 at the end of a data transfer, when a slave address or general call address is detected in slave receive mode, when bus arbitration is lost in master transmit mode, and when a stop condition is detected. IRIC is set at different times depending on the FS bit in SAR and the WAIT bit in ICMR. See section 18.3.6, IRIC Setting Timing and SCL Control. The conditions under which IRIC is set also differ depending on the setting of the ACKE bit in ICCR. IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 in IRIC. When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously without CPU intervention. Rev. 3.00 Jan 11, 2005 page 748 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Bit 1 IRIC 0 Description Waiting for transfer, or transfer in progress [Clearing conditions] • • W hen 0 is written in IRIC after reading IRIC = 1 W hen ICDR is written or read by the DTC (When the TDRE or RDRF flag is cleared to 0) (This is not always a clearing condition; see the description of DTC operation for details) Interrupt requested [Setting conditions] I2C bus format master mode • W hen a start condition is detected in the bus line state after a start condition is issued (when the TDRE flag is set to 1 because of first frame transmission) W hen a wait is inserted between the data and acknowledge bit when WAIT = 1 At the end of data transfer (at the rise of the 9th transmit/receive clock pulse, or at the fall of the 8th transmit/receive clock pulse when using wait insertion) W hen a slave address is received after bus arbitration is lost (when the AL flag is set to 1) W hen 1 is received as the acknowledge bit when the ACKE bit is 1 (when the ACKB bit is set to 1) W hen the slave address (SVA, SVAX) matches (when the AAS and AASX flags are set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the TDRE or RDRF flag is set to 1) W hen the general call address is detected (when FS = 0 and the ADZ flag is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the TDRE or RDRF flag is set to 1) W hen 1 is received as the acknowledge bit when the ACKE bit is 1 (when the ACKB bit is set to 1) W hen a stop condition is detected (when the STOP or ESTP flag is set to 1) Rev. 3.00 Jan 11, 2005 page 749 of 1220 REJ09B0186-0300O (Initial value) 1 • • • • 2 I C bus format slave mode • • • • Section 18 I2C Bus Interface [Option] Bit 1 IRIC 1 Description Synchronous serial format • • At the end of data transfer (when the TDRE or RDRF flag is set to 1) W hen a start condition is detected with serial format selected When any other condition arises in which the TDRE or RDRF flag is set to 1 When, with the I2C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set. The IRTR flag (the DTC start request flag) is not set at the end of a data transfer up to detection of a retransmission start condition or stop condition after a slave address (SVA) or general call address match in I2C bus format slave mode. Even when the IRIC flag and IRTR flag are set, the TDRE or RDRF internal flag may not be set. The IRIC and IRTR flags are not cleared at the end of the specified number of transfers in continuous transfer using the DTC. The TDRE or RDRF flag is cleared, however, since the specified number of ICDR reads or writes have been completed. Table 18.3 shows the relationship between the flags and the transfer states. Rev. 3.00 Jan 11, 2005 page 750 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Table 18.3 Flags and Transfer States MST TRS BBSY ESTP STOP IRTR AASX AL 1/0 1 1 1 1 0 0 0 0 0 1/0 1 1 1/0 1/0 0 0 0 0 1/0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1/0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 AAS 0 0 0 0 0 1/0 1 1 0 0 ADZ 0 0 0 0 0 1/0 0 1 0 0 ACKB State 0 0 0 0/1 0/1 0 0 0 0 0/1 Idle state (flag clearing required) Start condition issuance Start condition established Master mode wait Master mode transmit/receive end Arbitration lost SAR match by first frame in slave mode General call address match SARX match Slave mode transmit/receive end (except after SARX match) Slave mode transmit/receive end (after SARX match) Stop condition detected 0 0 0 1/0 1 1/0 1 1 0 0 0 1/0 0 0 1/0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0/1 Bit 0—Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored. Bit 0 SCP 0 1 Description Writing 0 issues a start or stop condition, in combination with the BBSY flag Reading always returns a value of 1 Writing is ignored (Initial value) Rev. 3.00 Jan 11, 2005 page 751 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] 18.2.6 Bit I2C Bus Status Register (ICSR) : 7 ESTP 0 R/(W)* 6 STOP 0 R/(W)* 5 IRTR 0 R/(W)* 4 AASX 0 R/(W)* 3 AL 0 R/(W)* 2 AAS 0 R/(W)* 1 ADZ 0 R/(W)* 0 ACKB 0 R/W Initial value : R/W : Note: * Only 0 can be written, for flag clearing. ICSR is an 8-bit readable/writable register that performs flag confirmation and acknowledge confirmation and control. ICSR is initialized to H'00 by a reset and in hardware standby mode. Bit 7—Error Stop Condition Detection Flag (ESTP): Indicates that a stop condition has been detected during frame transfer in I2C bus format slave mode. Bit 7 ESTP 0 Description No error stop condition [Clearing conditions] • • 1 • W hen 0 is written in ESTP after reading ESTP = 1 W hen the IRIC flag is cleared to 0 2 In I C bus format slave mode (Initial value) Error stop condition detected [Setting conditions] • • W hen a stop condition is detected during frame transfer In other modes No meaning Rev. 3.00 Jan 11, 2005 page 752 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Bit 6—Normal Stop Condition Detection Flag (STOP): Indicates that a stop condition has been detected after completion of frame transfer in I2C bus format slave mode. Bit 6 STOP 0 Description No normal stop condition [Clearing conditions] • • 1 • W hen 0 is written in STOP after reading STOP = 1 W hen the IRIC flag is cleared to 0 In I2C bus format slave mode Normal stop condition detected [Setting conditions] • • W hen a stop condition is detected after completion of frame transfer In other modes No meaning (Initial value) Bit 5—I2C Bus Interface Continuous Transmission/Reception Interrupt Request Flag (IRTR): Indicates that the I2C bus interface has issued an interrupt request to the CPU, and the source is completion of reception/transmission of one frame in continuous transmission/reception for which DTC activation is possible. When the IRTR flag is set to 1, the IRIC flag is also set to 1 at the same time. IRTR flag setting is performed when the TDRE or RDRF flag is set to 1. IRTR is cleared by reading IRTR after it has been set to 1, then writing 0 in IRTR. IRTR is also cleared automatically when the IRIC flag is cleared to 0. Rev. 3.00 Jan 11, 2005 page 753 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Bit 5 IRTR 0 Description Waiting for transfer, or transfer in progress [Clearing conditions] • • 1 W hen 0 is written in IRTR after reading IRTR = 1 W hen the IRIC flag is cleared to 0 (Initial value) Continuous transfer state [Setting conditions] • • In I2C bus interface slave mode When the TDRE or RDRF flag is set to 1 when AASX = 1 In other modes When the TDRE or RDRF flag is set to 1 Bit 4—Second Slave Address Recognition Flag (AASX): In I2C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX. AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is also cleared automatically when a start condition is detected. Bit 4 AASX 0 Description Second slave address not recognized [Clearing conditions] • • • 1 W hen 0 is written in AASX after reading AASX = 1 W hen a start condition is detected In master mode (Initial value) Second slave address recognized [Setting condition] • W hen the second slave address is detected in slave receive mode and FSX = 0 Rev. 3.00 Jan 11, 2005 page 754 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Bit 3—Arbitration Lost (AL): This flag indicates that arbitration was lost in master mode. The I2C bus interface monitors the bus. When two or more master devices attempt to seize the bus at nearly the same time, if the I2C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 3 AL 0 Description Bus arbitration won [Clearing conditions] • • 1 W hen ICDR data is written (transmit mode) or read (receive mode) W hen 0 is written in AL after reading AL = 1 (Initial value) Arbitration lost [Setting conditions] • • If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode If the internal SCL line is high at the fall of SCL in master transmit mode Bit 2—Slave Address Recognition Flag (AAS): In I2C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected. AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition, AAS is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Rev. 3.00 Jan 11, 2005 page 755 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Bit 2 AAS 0 Description Slave address or general call address not recognized [Clearing conditions] • • • 1 W hen ICDR data is written (transmit mode) or read (receive mode) W hen 0 is written in AAS after reading AAS = 1 In master mode (Initial value) Slave address or general call address recognized [Setting condition] • W hen the slave address or general call address is detected in slave receive mode and FS = 0 Bit 1—General Call Address Recognition Flag (ADZ): In I2C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (H'00). ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition, ADZ is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 1 ADZ 0 Description General call address not recognized [Clearing conditions] • • • 1 W hen ICDR data is written (transmit mode) or read (receive mode) W hen 0 is written in ADZ after reading ADZ = 1 In master mode (Initial value) General call address recognized [Setting condition] • W hen the general call address is detected in slave receive mode and (FSX = 0 or FS = 0) Bit 0—Acknowledge Bit (ACKB): Stores acknowledge data. In transmit mode, after the receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In receive mode, after data has been received, the acknowledge data set in this bit is sent to the transmitting device. Rev. 3.00 Jan 11, 2005 page 756 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] When this bit is read, in transmission (when TRS = 1), the value loaded from the bus line (returned by the receiving device) is read. In reception (when TRS = 0), the value set by internal software is read. In addition, writing to this bit overwrites the setting for acknowledge data sent when receiving data, regardless of the TRS value. In this case the value loaded from the receive device is maintained unchanged, so caution is necessary when using instructions that manipulate the bits in this register. Bit 0 ACKB 0 Description Receive mode: 0 is output at acknowledge output timing (Initial value) Transmit mode: Indicates that the receiving device has acknowledged the data (signal is 0) 1 Receive mode: 1 is output at acknowledge output timing Transmit mode: Indicates that the receiving device has not acknowledged the data (signal is 1) 18.2.7 Bit Serial Control Register X (SCRX) : 7 — 0 R/W 6 IICX1 0 R/W 5 IICX0 0 R/W 4 IICE 0 R/W 3 FLSHE 0 R/W 2 — 0 R/W 1 — 0 R/W 0 — 0 R/W Initial value : R/W : SCRX is an 8-bit readable/writable register that controls register access, the I2C interface operating mode (when the on-chip IIC option is included), and on-chip flash memory control (FZTAT versions). If a module controlled by SCRX is not used, do not write 1 to the corresponding bit. SCRX is initialized to H'00 by a reset and in hardware standby mode. Bit 7—Reserved: Do not set 1. Bit 6—I2C Transfer Select 1 (IICX1): This bit, together with bits CKS2 to CKS0 in ICMR of IIC1, selects the transfer rate in master mode. For details, see section 18.2.4, I2C Bus Mode Register (ICMR). Rev. 3.00 Jan 11, 2005 page 757 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Bit 5—I2C Transfer Select 0 (IICX0): This bit, together with bits CKS2 to CKS0 in ICMR of IIC0, selects the transfer rate in master mode. For details, see section 18.2.4, I2C Bus Mode Register (ICMR). Bit 4—I2C Master Enable (IICE): Controls CPU access to the I2C bus interface data and control registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR). Bit 4 IICE 0 1 Description CPU access to I2C bus interface data and control registers is disabled CPU access to I C bus interface data and control registers is enabled 2 (Initial value) Bit 3—Flash Memory Control Register Enable (FLSHE): Controls the operation of the flash memory in F-ZTAT versions. For details, see section 22, ROM. Bits 2 to 0—Reserved: Do not set 1. 18.2.8 Bit DDC Switch Register (DDCSWR) : 7 — 0 6 — 0 5 — 0 4 — 0 3 CLR3 1 W*2 2 CLR2 1 W*2 1 CLR1 1 W*2 0 CLR0 1 W*2 Initial value : R/W Notes: 1. 2. : R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 Should always be written with 0. Always read as 1. DDCSWR is an 8-bit readable/writable register that is used to initialize the IIC module. DDCSWR is initialized to H'0F by a reset and in hardware standby mode. Bits 7 to 4—Reserved: Should always be written with 0. Bits 3 to 0—IIC Clear 3 to 0 (CLR3 to CLR0): These bits control initialization of the internal state of IIC0 and IIC1. These bits can only be written to; if read they will always return a value of 1. When a write operation is performed on these bits, a clear signal is generated for the internal latch circuit of the corresponding module(s), and the internal state of the IIC module(s) is initialized. Rev. 3.00 Jan 11, 2005 page 758 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] The write data for these bits is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. When clearing is required again, all the bits must be written to in accordance with the setting. Bit 3 CLR3 0 Bit 2 CLR2 0 1 Bit 1 CLR1 — 0 1 1 — — Bit 0 CLR0 — 0 1 0 1 — Description Setting prohibited Setting prohibited IIC0 internal latch cleared IIC1 internal latch cleared IIC0 and IIC1 internal latches cleared Invalid setting Rev. 3.00 Jan 11, 2005 page 759 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] 18.2.9 Bit Module Stop Control Register B (MSTPCRB) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : R/W : MSTPCRB is an 8-bit readable/writable register that perform module stop mode control. When the MSTPB4 or MSTPB3 bit is set to 1, operation of the corresponding IIC channel is halted at the end of the bus cycle, and a transition is made to module stop mode. For details, see section 24.5, Module Stop Mode. MSTPCRB is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset and in software standby mode. Bit 4—Module Stop (MSTPB4): Specifies IIC channel 0 module stop mode. Bit 4 MSTPB4 0 1 Description IIC channel 0 module stop mode is cleared IIC channel 0 module stop mode is set (Initial value) Bit 3—Module Stop (MSTPB3): Specifies IIC channel 1 module stop mode. Bit 3 MSTPB3 0 1 Description IIC channel 1 module stop mode is cleared IIC channel 1 module stop mode is set (Initial value) Rev. 3.00 Jan 11, 2005 page 760 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] 18.3 18.3.1 Operation I2C Bus Data Format The I2C bus interface has serial and I2C bus formats. The I2C bus formats are addressing formats with an acknowledge bit. These are shown in figures 18.3. The first frame following a start condition always consists of 8 bits. The serial format is a non-addressing format with no acknowledge bit. Although start and stop conditions must be issued, this format can be used as a synchronous serial format. This is shown in figure 18.4. Figure 18.5 shows the I2C bus timing. The symbols used in figures 18.3 to 18.5 are explained in table 18.4. (a) I2C bus format (FS = 0 or FSX = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 n: transfer bit count (n = 1 to 8) m: transfer frame count (m ≥ 1) (b) I2C bus format (start condition retransmission, FS = 0 or FSX = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 A/A 1 P 1 n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 ≥ 1) Figure 18.3 I2C Bus Data Formats (I2C Bus Formats) Rev. 3.00 Jan 11, 2005 page 761 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] FS = 1 and FSX = 1 S 1 DATA 8 1 DATA n m P 1 n: transfer bit count (n = 1 to 8) m: transfer frame count (m ≥ 1) Figure 18.4 I2C Bus Data Format (Serial Format) SDA SCL S 1-7 SLA 8 R/W 9 A 1-7 DATA 8 9 A 1-7 DATA 8 9 A/A P Figure 18.5 I2C Bus Timing Table 18.4 I2C Bus Data Format Symbols Legend S SLA Start condition. The master device drives SDA from high to low while SCL is high Slave address, by which the master device selects a slave device Indicates the direction of data transfer: from the slave device to the master device when R/ is 1, or from the master device to the slave device when R/ is 0 Acknowledge. The receiving device (the slave in master transmit mode, or the master in master receive mode) drives SDA low to acknowledge a transfer Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first or LSB-first format is selected by bit MLS in ICMR Stop condition. The master device drives SDA from low to high while SCL is high A DATA P 18.3.2 Master Transmit Operation In I2C bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The transmission procedure and operations are described below. (1) Set the ICE bit in ICCR to 1. Set bits MLS, WAIT, and CKS2 to CKS0 in ICMR, and bit IICX in STCR, according to the operating mode. Rev. 3.00 Jan 11, 2005 page 762 of 1220 REJ09B0186-0300O W W W R/ Section 18 I2C Bus Interface [Option] (2) Read the BBSY flag in ICCR to confirm that the bus is free, then set bits MST and TRS to 1 in ICCR to select master transmit mode. Next, write 1 to BBSY and 0 to SCP. This changes SDA from high to low when SCL is high, and generates the start condition. The TDRE internal flag is then set to 1, and the IRIC and IRTR flags are also set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. (3) With the I2C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame data following the start condition indicates the 7-bit slave address and transmit/receive direction. Write the data (slave address + R/ ) to ICDR. The TDRE internal flag is then cleared to 0. The written address data is transferred to ICDRS, and the TDRE internal flag is set to 1 again. This is identified as indicating the end of the transfer, and so the IRIC flag is cleared to 0. The master device sequentially sends the transmit clock and the data written to ICDR using the timing shown in figure 18.6. The selected slave device (i.e. the slave device with the matching slave address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal. (4) When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. If the TDRE internal flag has been set to 1, after one frame has been transmitted SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. (5) To continue transfer, write the next data to be transmitted into ICDR. After the data has been transferred to ICDRS and the TDRE internal flag has been set to 1, clear the IRIC flag to 0. Transmission of the next frame is performed in synchronization with the internal clock. Data can be transmitted sequentially by repeating steps (4) and (5). To end transmission, after clearing the IRIC flag and transmitting the final data (with no more transmit data in ICDRT), write H'FF dummy data to ICDR, and then write 0 to BBSY and SCP in ICCR when the IRIC flag is set again. This changes SDA from low to high when SCL is high, and generates the stop condition. W Rev. 3.00 Jan 11, 2005 page 763 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Start condition issuance SCL (master output) 1 2 3 4 5 6 7 8 9 1 2 Slave address SDA (master output) SDA (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 [4] Slave address R/W A Data 1 TDRE IRIC Interrupt request generation Address + R/W Interrupt request generation ICDRT Data 1 ICDRS Address + R/W Data 1 User processing [3] ICDR write [2] Write BBSY = 1 and SCP = 0 (start condition issuance) [3] IRIC clearance [5] ICDR write [5] IRIC clearance Figure 18.6 Example of Master Transmit Mode Operation Timing (MLS = WAIT = 0) To transmit data continuously: (6) Before the rise of the 9th transmit clock pulse for the data being transmitted, clear the IRIC flag to 0 and then write the next transmit data to ICDR. (7) When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock pulse. At the same time, the next transmit data written into ICDR (ICDRT) is transferred to ICDRS, the TDRE internal flag is set to 1, and then the next frame is transmitted in synchronization with the internal clock. Data can be transmitted continuously by repeating steps (6) and (7). Rev. 3.00 Jan 11, 2005 page 764 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] SCL (master output) 1 2 3 4 5 6 7 8 9 1 2 3 SDA (master output) SDA (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Data 1 [7] A Data 2 TDRE IRIC Interrupt request generation Data 1 Data 2 [7] Data 3 ICDRT ICDRS Data 1 Data 2 User processing ICDR write [6] IRIC clearance [6] ICDR write [6] IRIC clearance [6] ICDR write Figure 18.7 Example of Master Transmit Mode Continuous Transmit Operation Timing (MLS = WAIT = 0) 18.3.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. The reception procedure and operations in master receive mode are described below. (1) Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Also clear the ACKB bit in ICSR to 0 (acknowledge data setting). (2) When ICDR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. In order to determine the end of reception, the IRIC flag in ICCR must be cleared beforehand. (3) The master device drives SDA at the 9th receive clock pulse to return an acknowledge signal. When one frame of data has been received, the IRIC flag in ICCR is set to 1 at the rise of the 9th receive clock pulse. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. If the RDRF internal flag has been cleared to 0, it is set to 1, and the receive operation continues. If reception of the next frame ends before the ICDR read/IRIC flag clearing in (4) is performed, SCL is automatically fixed low in synchronization with the internal clock. Rev. 3.00 Jan 11, 2005 page 765 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] (4) Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0. Data can be received continuously by repeating steps (3) and (4). As the RDRF internal flag is cleared to 0 when reception is started after initially switching from master transmit mode to master receive mode, reception of the next frame of data is started automatically. To halt reception, the TRS bit must be set to 1 before the rise of the receive clock for the next frame. To halt reception, set the TSR bit to 1, read ICDR, then write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Master transmit mode SCL (master output) Master receive mode 9 1 2 3 4 5 6 7 8 9 1 2 SDA (slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Data 1 Bit 3 Bit 2 Bit 1 Bit 0 [3] A Bit 7 Bit 6 Data 2 SDA (master output) RDRF IRIC Interrupt request generation Interrupt request generation ICDRS Data 1 ICDRR Data 1 User processing [1] TRS cleared to 0 [2] ICDR read [2] IRIC clearance (dummy read) [4] ICDR read [4] IRIC clearance Figure 18.8 Example of Master Receive Mode Operation Timing (MLS = WAIT = ACKB = 0) Rev. 3.00 Jan 11, 2005 page 766 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] 18.3.4 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The reception procedure and operations in slave receive mode are described below. (1) Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode. (2) When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1. (3) When the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. If the 8th data bit (R/ ) is 0, the TRS bit in ICCR remains cleared to 0, and slave receive operation is performed. (4) At the 9th clock pulse of the receive frame, the slave device drives SDA low and returns an acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. If the RDRF internal flag has been cleared to 0, it is set to 1, and the receive operation continues. If the RDRF internal flag has been set to 1, the slave device drives SCL low from the fall of the receive clock until data is read into ICDR. (5) Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0. Receive operations can be performed continuously by repeating steps (4) and (5). When SDA is changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in ICCR is cleared to 0. Rev. 3.00 Jan 11, 2005 page 767 of 1220 REJ09B0186-0300O W Section 18 I2C Bus Interface [Option] Start condition issuance SCL (master output) SCL (slave output) SDA (master output) SDA (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 1 2 3 4 5 6 7 8 9 1 2 Slave address R/W [4] A Data 1 RDRF IRIC Interrupt request generation Address + R/W ICDRS ICDRR Address + R/W User processing [5] ICDR read [5] IRIC clearance Figure 18.9 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0) Rev. 3.00 Jan 11, 2005 page 768 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] SCL (master output) SCL (slave output) SDA (master output) 7 8 9 1 2 3 4 5 6 7 8 9 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data 1 SDA (slave output) [4] Data 2 [4] A A RDRF IRIC Interrupt request generation Data 1 Data 2 Interrupt request generation ICDRS ICDRR Data 1 Data 2 User processing [5] ICDR read [5] IRIC clearance Figure 18.10 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0) 18.3.5 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. (1) Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode. (2) When the slave address matches in the first frame following detection of the start condition, the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. If the 8th data bit (R/ ) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave transmit mode automatically. The TDRF flag is set to 1. The slave device drives SCL low from the fall of the transmit clock until ICDR data is written. Rev. 3.00 Jan 11, 2005 page 769 of 1220 REJ09B0186-0300O W Section 18 I2C Bus Interface [Option] (3) After clearing the IRIC flag to 0, write data to ICDR. The TDRE internal flag is cleared to 0. The written data is transferred to ICDRS, and the TDRE internal flag and the IRIC and IRTR flags are set to 1 again. After clearing the IRIC flag to 0, write the next data to ICDR. The slave device sequentially sends the data written into ICDR in accordance with the clock output by the master device at the timing shown in figure 18.11. (4) When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock pulse. If the TDRE internal flag has been set to 1, this slave device drives SCL low from the fall of the transmit clock until data is written to ICDR. The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal. As this acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to determine whether the transfer operation was performed normally. When the TDRE internal flag is 0, the data written into ICDR is transferred to ICDRS, transmission is started, and the TDRE internal flag and the IRIC and IRTR flags are set to 1 again. (5) To continue transmission, clear the IRIC flag to 0, then write the next data to be transmitted into ICDR. The TDRE flag is cleared to 0. Transmit operations can be performed continuously by repeating steps (4) and (5). To end transmission, write H'FF to ICDR to release SDA on the slave side. When SDA is changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in ICCR is cleared to 0. Rev. 3.00 Jan 11, 2005 page 770 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Slave receive mode SCL (master output) SCL (slave output) Slave transmit mode 8 9 1 2 3 4 5 6 7 8 9 1 2 SDA (slave output) SDA (slave output) R/W A [2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Data 1 A Data 2 TDRE [3] IRIC Interrupt request generation Interrupt request generation Interrupt request generation ICDRT Data 1 Data 2 ICDRS Data 1 Data 2 User processing [3] IRIC clearance [3] ICDR write [3] ICDR write [5] IRIC clearance [3] ICDR write Figure 18.11 Example of Slave Transmit Mode Operation Timing (MLS = 0) Rev. 3.00 Jan 11, 2005 page 771 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] 18.3.6 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. Figure 18.12 shows the IRIC set timing and SCL control. (a) When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait) SCL 7 8 9 1 SDA IRIC 7 8 A 1 User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) (b) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted) SCL 8 9 1 SDA IRIC 8 A 1 User processing Clear IRIC Clear Write to ICDR (transmit) IRIC or read ICDR (receive) (c) When FS = 1 and FSX = 1 (synchronous serial format) SCL 7 8 1 SDA IRIC 7 8 1 User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) Figure 18.12 IRIC Setting Timing and SCL Control Rev. 3.00 Jan 11, 2005 page 772 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] 18.3.7 Operation Using the DTC The I2C bus format provides for selection of the slave device and transfer direction by means of the slave address and the R/ bit, confirmation of reception with the acknowledge bit, indication of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out in conjunction with CPU processing by means of interrupts. Table 18.5 shows some examples of processing using the DTC. These examples assume that the number of transfer data bytes is known in slave mode. Table 18.5 Examples of Operation Using the DTC Item Master Transmit Mode Master Receive Mode Transmission by CPU (ICDR write) Slave Transmit Mode Reception by CPU (ICDR read) Slave Receive Mode Reception by CPU (ICDR read) Slave address + Transmission by R/ bit DTC (ICDR write) transmission/ reception Dummy data read Actual data transmission/ reception Dummy data (H'FF) write Last frame processing Transfer request processing after last frame processing Setting of number of DTC transfer data frames — Transmission by DTC (ICDR write) — Not necessary 1st time: Clearing by CPU 2nd time: End condition issuance by CPU Transmission: Reception: Actual Actual data count data count + 1 (+1 equivalent to slave address + R/ bits) W W W Processing by CPU (ICDR read) Reception by DTC (ICDR read) — Reception by CPU (ICDR read) Not necessary — Transmission by DTC (ICDR write) Processing by DTC (ICDR write) Not necessary — Reception by DTC (ICDR read) — Reception by CPU (ICDR read) Automatic clearing Not necessary on detection of end condition during transmission of dummy data (H'FF) Transmission: Reception: Actual Actual data count data count + 1 (+1 equivalent to dummy data (H'FF)) Rev. 3.00 Jan 11, 2005 page 773 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] 18.3.8 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 18.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. Sampling clock C SCL or SDA input signal D Latch Q D C Q Latch Match detector Internal SCL or SDA signal System clock period Sampling clock Figure 18.13 Block Diagram of Noise Canceler 18.3.9 Sample Flowcharts Figures 18.14 to 18.17 show sample flowcharts for using the I2C bus interface in each mode. Rev. 3.00 Jan 11, 2005 page 774 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Start Initialize Read BBSY in ICCR No BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCR Write BBSY = 1 and SCP = 0 in ICCR Read IRIC in ICCR No IRIC = 1? Yes Write transmit data in ICDR Clear IRIC in ICCR Read IRIC in ICCR No IRIC = 1? Yes Read ACKB in ICSR ACKB = 0? Yes Transmit mode? Yes Write transmit data in ICDR Clear IRIC in ICCR Read IRIC in ICCR No IRIC = 1? Yes Read ACKB in ICSR No End of transmission (ACKB = 1)? Yes Clear IRIC in ICCR Write BBSY = 0 and SCP = 0 in ICCR End [12] Generate a stop condition. [11] Test for end of transfer. [9] Set transmit data for the second and subsequent bytes. (Perform ICDR write and IRIC flag clear operations consecutively.) No Master receive mode No [8] Test for acknowledgement by the designated slave device. [7] Wait for 1 byte to be transmitted. [6] Set first transmit data for the first byte (slave address + R/W). (ICDR write and IRIC flag clear operations consecutively.) [3] Select master transmit mode. [1] Initialize. [2] Test the status of the SCL and SDA lines. [4] Generate a start condition. [5] Wait for start condition to be generated. [10] Wait for 1 byte to be transmitted. Figure 18.14 Flowchart for Master Transmit Mode (Example) Rev. 3.00 Jan 11, 2005 page 775 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Master receive mode Set TRS = 0 in ICCR Set WAIT = 1 in ICMR Set ACKB = 0 in ICSR Read ICDR Clear IRIC in ICCR Read IRIC in ICCR No IRIC = 1? Yes Last receive? No Clear IRIC in ICCR Yes [2] Start receiving. The first read is a dummy read. (Perform ICDR write and IRIC flag clear operations consecutively.) [1] Select receive mode. [3] Wait for 1 byte to be received. [4] Clear IRIC flag (clear wait). Read IRIC in ICCR No IRIC = 1? Yes Read ICDR Clear IRIC in ICCR Read IRIC in ICCR No IRIC = 1? Yes Last receive? No Clear IRIC in ICCR Yes [5] Wait for 1 byte to be received. [6] Read the received data. [7] Clear IRIC flag. [8] Wait for second and subsequent receive data bytes. [9] Clear IRIC flag (clear wait). Set ACKB = 1 in ICSR Set TRS = 1 in ICCR Clear IRIC in ICCR Read IRIC in ICCR No IRIC = 1? Yes Set WAIT = 0 in ICMR Read ICDR Clear IRIC in ICCR Write BBSY = 0 and SCP = 0 in ICCR End [10] Set acknowledge data for the last receive. [11] Clear IRIC flag (clear wait). [12] Wait for 1 byte to be received. [13] Clear wait mode. Read receive data. Clear IRIC flag. (Perform IRIC flag clearing while WAIT = 0.) [14] Generate a stop condition. Figure 18.15 Flowchart for Master Receive Mode (Example) Rev. 3.00 Jan 11, 2005 page 776 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Start Initialize Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR Read IRIC in ICCR No [2] IRIC = 1? Yes [1] Read AAS and ADZ in ICSR AAS = 1 and ADZ = 0? Yes Read TRS in ICCR TRS = 0? Yes Last receive? No Read ICDR Clear IRIC in ICCR Yes No Slave transmit mode No General call address processing * Description omitted [3] [1] Select slave receive mode. [2] Wait for the first byte to be received (slave address). [3] Start receiving. The first read is a dummy read. [4] Read IRIC in ICCR No IRIC = 1? Yes [4] Wait for the transfer to end. [5] Set acknowledge data for the last receive. [6] Start the last receive. [7] Wait for the transfer to end. Set ACKB = 0 in ICSR Read ICDR Clear IRIC in ICCR [5] [6] [8] Read the last receive data. Read IRIC in ICCR No IRIC = 1? Yes Read ICDR Clear IRIC in ICCR End [7] [8] Figure 18.16 Flowchart for Slave Transmit Mode (Example) Rev. 3.00 Jan 11, 2005 page 777 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Slave transmit mode Clear IRIC in ICCR [1] Set transmit data for the second and subsequent bytes. [1] [2] Wait for 1 byte to be transmitted. [3] Test for end of transfer. Clear IRIC in ICCR [4] Select slave receive mode. [5] Dummy read (to release the SCL line). Read IRIC in ICCR No [2] IRIC = 1? Yes Read ACKB in ICSR End of transmission (ACKB = 1)? Yes Set TRS = 0 in ICCR Read ICDR Clear IRIC in ICCR [4] [3] Write transmit data in ICDR No [5] End Figure 18.17 Flowchart for Slave Receive Mode (Example) 18.3.10 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed by (1) setting bits CLR3 to CLR0 in the DDCSWR register or (2) clearing the ICE bit. For details of settings for bits CLR3 to CLR0, see section 18.2.8, DDC Switch Register (DDCSWR). Rev. 3.00 Jan 11, 2005 page 778 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] (1) Scope of Initialization The initialization executed by this function covers the following items: • TDRE and RDRF internal flags • Transmit/receive sequencer and internal operating clock counter • Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data output, etc.) The following items are not initialized: • Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, DDCSWR, STCR) • Internal latches used to retain register read information for setting/clearing flags in the ICMR, ICCR, ICSR, and DDCSWR registers • The value of the ICMR register bit counter (BC2 to BC0) • Generated interrupt sources (interrupt sources transferred to the interrupt controller) (2) Notes on Initialization • Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. • Basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary. • When initialization is performed by means of the DDCSWR register, the write data for bits CLR3 to CLR0 is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. Similarly, when clearing is required again, all the bits must be written to simultaneously in accordance with the setting. • If a flag clearing setting is made during transmission/reception, the IIC module will stop transmitting/receiving at that point and the SCL and SDA pins will be released. When transmission/reception is started again, register initialization, etc., must be carried out as necessary to enable correct communication as a system. The value of the BBSY bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the SCL and SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and flags may also have an effect. To prevent problems caused by these factors, the following procedure should be used when initializing the IIC state. Rev. 3.00 Jan 11, 2005 page 779 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] 1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0, or according to the ICE bit. 2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBST bit to 0, and wait for two transfer rate clock cycles. 3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0, or according to the ICE bit. 4. Initialize (re-set) the IIC registers. 18.4 Usage Notes (1) In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that SCL and SDA are both low, then issue the instruction that generates the stop condition. Note that SCL may not yet have gone low when BBSY is cleared to 0. (2) Either of the following two conditions will start the next transfer. Pay attention to these conditions when reading or writing to ICDR.  Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to ICDRS)  Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to ICDRR) (3) Table 18.6 shows the timing of SCL and SDA output in synchronization with the internal clock. Timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, series resistance, and parallel resistance. Rev. 3.00 Jan 11, 2005 page 780 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Table 18.6 I2C Bus Timing (SCL and SDA Output) Item SCL output cycle time SCL output high pulse width SCL output low pulse width SDA output bus free time Start condition output hold time Retransmission start condition output setup time Stop condition output setup time Data output setup time (master) Data output setup time (slave) Data output hold time tSDAHO Symbol tSCLO tSCLHO tSCLLO tBUFO tSTAHO tSTASO tSTOSO tSDASO Output Timing 28 tcyc to 256 tcyc 0.5 tSCLO 0.5 tSCLO 0.5 tSCLO – 1 tcyc 0.5 tSCLO – 1 tcyc 1 tSCLO 0.5 tSCLO + 2 tcyc 1 tSCLLO – 3 tcyc 1 tSCLL – 3 tcyc 3 tcyc ns Unit ns ns ns ns ns ns ns ns Notes Figure 25.33 (reference) (4) SCL and SDA input is sampled in synchronization with the internal clock. The AC timing therefore depends on the system clock cycle tcyc, as shown in table 25.11 in section 25, Electrical Characteristics. Note that the I2C bus interface AC timing specifications will not be met with a system clock frequency of less than 5 MHz. (5) The I2C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for highspeed mode). In master mode, the I2C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds the time determined by the input clock of the I2C bus interface, the high period of SCL is extended. The SCL rise time is determined by the pull-up resistance and load capacitance of the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the SCL rise time does not exceed the values given in the table below. Rev. 3.00 Jan 11, 2005 page 781 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Table 18.7 Permissible SCL Rise Time (tSr) Values Time Indication I C Bus Specification φ = (Max.) 5 MHz Standard mode 2 tcyc IICX Indication 0 7.5 tcyc φ= 8 MHz φ= φ= φ= φ= φ= 10 MHz 16 MHz 20 MHz 25 MHz 28 MHz 750 ns 468 ns 375 ns 300 ns 300 ns 300 ns     1000 ns 1000 ns 937 ns 300 ns 300 ns High-speed 300 ns mode 1 17.5 tcyc Standard mode 1000 ns 1000 ns 1000 ns 1000 ns 1000 ns875 ns 300 ns 300 ns 300 ns 300 ns 300 ns 700 ns 624 ns 300 ns 300 ns High-speed 300 ns mode Note: When 7.5 tcyc is selected as the transfer rate, the actual transfer rate may be extended if φ exceeds 20 MHz. (6) The I2C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns and 300 ns. The I2C bus interface SCL and SDA output timing is prescribed by tScyc and tcyc, as shown in table 18.6. However, because of the rise and fall times, the I2C bus interface specifications may not be satisfied at the maximum transfer rate. Table 18.8 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. tBUFO fails to meet the I2C bus interface specifications at any frequency. The solution is either (a) to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input timing permits this output timing for use as slave devices connected to the I2C bus. tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I2C bus interface specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input timing permits this output timing for use as slave devices connected to the I2C bus. Rev. 3.00 Jan 11, 2005 page 782 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Table 18.8 I2C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] I2C Bus tSr/tSf SpecifiInfluence cation (Max.) (Min.) Standard mode –1000 4000 600 4700 1300 4700 1300 4000 600 4700 600 4000 600 250 100 250 100 Item tSCLHO tcyc Indication 0.5 tSCLO (–tSr) φ= 5 MHz 4000 950 4750 1000*1 3800* 750*1 4550 800 9000 2200 4400 1350 3100 400 3100 400 1 φ= 8 MHz 4000 950 4750 φ= φ= φ= 10 MHz 16 MHz 20 MHz 4000 950 4750 4000 950 4750 4000 950 4750 φ= 25 MHz 4000 950 4750 1000*1 3960* 910*1 4710 960 9000 2200 4080 1030 3580 880 3580 880 1 High-speed –300 mode tSCLLO 0.5 tSCLO (–tSf ) Standard mode –250 High-speed –250 mode tBUFO 0.5 tSCLO – 1 tcyc ( –tSr ) Standard mode –1000 1000*1 1000*1 3875* 825*1 4625 875 9000 2200 4250 1200 3325 625 3325 625 1 1000*1 1000*1 3938* 888*1 4688 938 9000 2200 4125 1075 3513 813 3513 813 1 3900* 850*1 4650 900 9000 2200 4200 1150 3400 700 3400 700 1 3950* 900*1 4700 950 9000 2200 4100 1050 3550 850 3550 850 1 High-speed –300 mode Standard mode –250 tSTAHO 0.5 tSCLO – 1 tcyc (–tSf ) High-speed –250 mode Standard mode –1000 tSTASO 1 tSCLO (–tSr ) High-speed –300 mode tSTOSO 0.5 tSCLO + 2 tcyc (–tSr ) Standard mode –1000 High-speed –300 mode 1 tSCLLO*2 – Standard –1000 (master) 3 tcyc mode (–tSr ) High-speed –200 mode tSDASO 1 tSCLL*2 – 2 (slave) 3 tcyc* (–tSr ) tSDASO Standard mode –1000 High-speed –300 mode Rev. 3.00 Jan 11, 2005 page 783 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Time Indication (at Maximum Transfer Rate) [ns] I C Bus tSr/tSf SpecifiInfluence cation (Max.) (Min.) Standard mode 0 0 0 2 Item tSDAHO tcyc Indication 3 tcyc φ= 5 MHz 600 600 φ= 8 MHz 375 375 φ= φ= φ= φ= 10 MHz 16 MHz 20 MHz 25 MHz 300 300 188 188 150 150 120 120 High-speed 0 mode Notes: Does not meet the I2C bus interface specification. Remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. The values in the above table will vary depending on the settings of the IICX bit and bits CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the maximum transfer rate; therefore, whether or not the I2C bus interface specifications are met must be determined in accordance with the actual setting conditions. Calculated using the I2C bus specification values (standard mode: 4700 ns min.; high-speed mode: 1300 ns min.). (7) Note on ICDR Read at End of Master Reception To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. After this, receive data can be read by means of an ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to ICDR, and so it will not be possible to read the second byte of data. If it is necessary to read the second byte of data, issue the stop condition in master receive mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the BBSY bit in the ICCR register is cleared to 0, the stop condition has been generated, and the bus has been released, then read the ICDR register with TRS cleared to 0. Note that if the receive data (ICDR data) is read in the interval between execution of the instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the actual generation of the stop condition, the clock may not be output correctly in subsequent master transmission. Clearing of the MST bit after completion of master transmission/reception, or other modifications of IIC control bits to change the transmit/receive operating mode or settings, must be carried out during interval (a) in figure 18.18 (after confirming that the BBSY bit has been cleared to 0 in the ICCR register). Rev. 3.00 Jan 11, 2005 page 784 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Stop condition (a) SDA SCL Internal clock BBSY bit Master receive mode ICDR reading prohibited Bit 0 8 A 9 Start condition Execution of stop condition issuance instruction (0 written to BBSY and SCP) Confirmation of stop condition generation (0 read from BBSY) Start condition issuance Figure 18.18 Points for Attention Concerning Reading of Master Receive Data (8) Notes on Start Condition Issuance for Retransmission Figure 18.19 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to ICDR, together with the corresponding flowchart. Rev. 3.00 Jan 11, 2005 page 785 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] [1] Wait for end of 1-byte transfer IRIC = 1 ? Yes Clear IRIC in ICSR Start condition issuance? Yes Read SCL pin SCL = Low ? Yes Write BBSY = 1, SCP = 0 (ICSR) Read SCL pin SCL = High ? Yes Write transmit data to ICDR [5] No [4] [3] No [2] No Other processing [5] Set transmit data (slave address + R/W) Note: Program so that processing from [3] to [5] is executed continuously. No [1] [2] Determine whether SCL is low [3] Issue restart condition instruction for retransmission [4] Determine whether SCL is high SCL SDA ACK Start condition (retransmission) bit7 IRIC [1] IRIC determination [2] Determination of SCL = low [4] Determination of SCL = high [5] ICDR write [3] Start condition instruction issuance Figure 18.19 Flowchart and Timing of Start Condition Instruction Issuance for Retransmission Rev. 3.00 Jan 11, 2005 page 786 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] (9) Notes on I2C Bus Interface Stop Condition Instruction Issuance If the rise time of the 9th SCL acknowledge exceeds the specification because the bus load capacitance is large, or if there is a slave device of the type that drives SCL low to effect a wait, issue the stop condition instruction after reading SCL and determining it to be low, as shown below. 9th clock VIH High period secured SCL As waveform rise is late, SCL is detected as low SDA Stop condition IRIC [1] Determination of SCL = low [2] Stop condition instruction issuance Figure 18.20 Timing of Stop Condition Issuance Rev. 3.00 Jan 11, 2005 page 787 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] (10) Notes on IRIC Flag Clearance when Using Wait Function If the SCL rise time exceeds the designated duration or if the slave device is of the type that keeps SCL low and applies a wait state when the wait function is used in the master mode of the I2C bus interface, read SCL and clear the IRIC flag after determining that SCL has gone low, as shown below. Clearing the IRIC flag to 0 when WAIT is set to 1 and SCL is being held at high level can cause the SDA value to change before SCL goes low, resulting in a start condition or stop condition being generated erroneously. SCL = high duration maintained SCL VIH SCL = low detected SDA IRIC [1] Judgement that SCL = low [2] IRIC clearance Figure 18.21 IRIC Flag Clearance in WAIT = 1 Status Rev. 3.00 Jan 11, 2005 page 788 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] (11) Notes on ICDR Reads and ICCR Access in Slave Transmit Mode In a transmit operation in the slave mode of the I2C bus interface, do not read the ICDR register or read or write to the ICCR register during the period indicated by the shaded portion in figure 18.22. Normally, when interrupt processing is triggered in synchronization with the rising edge of the 9th clock cycle, the period in question has already elapsed when the transition to interrupt processing takes place, so there is no problem with reading the ICDR register or reading or writing to the ICCR register. To ensure that the interrupt processing is performed properly, one of the following two conditions should be applied. • Make sure that reading received data from the ICDR register, or reading or writing to the ICCR register, is completed before the next slave address receive operation starts. • Monitor the BC2 to BC0 counter in the ICMR register and, when the value of BC2 to BC0 is 000 (8th or 9th clock cycle), allow a waiting time of at least 2 transfer clock cycles in order to involve the problem period in question before reading from the ICDR register, or reading or writing to the ICCR register. Waveforms if problem occurs SDA SCL TRS R/W 8 Address received Period when ICDR reads and ICCR reads and writes are prohibited (6 system clock cycles) A 9 Data transmission ICDR write Bit 7 Detection of 9th clock cycle rising edge Figure 18.22 ICDR Read and ICCR Access Timing in Slave Transmit Mode Rev. 3.00 Jan 11, 2005 page 789 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] (12) Notes on TRS Bit Setting in Slave Mode From the detection of the rising edge of the 9th clock cycle or of a stop condition to when the rising edge of the next SCL pin signal is detected (the period indicated as (a) in figure 18.23) in the slave mode of the I2C bus interface, the value set in the TRS bit in the ICCR register is effective immediately. However, at other times (indicated as (b) in figure 18.23) the value set in the TRS bit is put on hold until the next rising edge of the 9th clock cycle or stop condition is detected, rather than taking effect immediately. This results in the actual internal value of the TRS bit remaining 1 (transmit mode) and no acknowledge bit being sent at the 9th clock cycle address receive completion in the case of an address receive operation following a restart condition input with no stop condition intervening. When receiving an address in the slave mode, clear the TRS bit to 0 during the period indicated as (a) in figure 18.23. To cancel the holding of the SCL bit low by the wait function in the slave mode, clear the TRS bit to 0 and then perform a dummy read of the ICDR register. Restart condition (a) SDA SCL TRS 8 9 1 2 3 4 5 6 7 8 (b) A 9 Data transmission Address reception TRS bit setting hold time ICDR dummy read TRS bit set Detection of 9th clock cycle rising edge Detection of 9th clock cycle rising edge Figure 18.23 TRS Bit Setting Timing in Slave Mode Rev. 3.00 Jan 11, 2005 page 790 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] (13) Notes on ICDR Reads in Transmit Mode and ICDR Writes in Receive Mode When attempting to read ICDR in the transmit mode (TRS = 1) or write to ICDR in the receive mode (TRS = 0) under certain conditions, the SCL pin may not be held low after the completion of the transmit or receive operation and a clock may not be output to the SCL bus line before the ICDR register access operation can take place properly. When accessing ICDR, always change the setting to the transmit mode before performing a read operation, and always change the setting to the receive mode before performing a write operation. (14) Notes on ACKE Bit and TRS Bit in Slave Mode When using the I2C bus interface, if an address is received in the slave mode immediately after 1 is received as an acknowledge bit (ACKB = 1) in the transmit mode (TRS = 1), an interrupt may be generated at the rising edge of the 9th clock cycle if the address does not match. When performing slave mode operations using the IIC bus interface module, make sure to do the following. When a 1 is received as an acknowledge bit for the final transmit data after completing a series of transmit operations, clear the ACKE bit in the ICCR register to 0 to initialize the ACKB bit to 0. • In the slave mode, change the setting to the receive mode (TRS = 0) before the start condition is input. To ensure that the switch from the slave transmit mode to the slave receive mode is accomplished properly, end the transmission as described in figure 18.17 in section 18.3.9, Sample Flowcharts. (15) Notes on Arbitration Lost in Master Mode The I2C bus interface recognizes the data in transmit/receive frame as an address when arbitration is lost in master mode and a transition to slave receive mode is automatically carried out. When arbitration is lost not in the first frame but in the second frame or subsequent frame, transmit/receive data that is not an address is compared with the value set in the SAR or SARX register as an address. If the receive data matches with the address in the SAR or SARX register, the I2C bus interface erroneously recognizes that the address call has occurred. (See figure 18.24.) In multi-master mode, a bus conflict could happen. When The I2C bus interface is operated in master mode, check the state of the AL bit in the ICSR register every time after one frame of data has been transmitted or received. When arbitration is lost during transmitting the second frame or subsequent frame, take avoidance measures. • Rev. 3.00 Jan 11, 2005 page 791 of 1220 REJ09B0186-0300O Section 18 I2C Bus Interface [Option] Arbitration is lost The AL flag in ICSR is set to 1 I2C bus interface (Master transmit mode) S SLA R/W A Transmit data match Transmit timing match DATA1 Transmit data does not match Other device (Master transmit mode) S SLA R/W A DATA2 A DATA3 A Data contention bus interface (Slave receive mode) I2C S SLA R/W A SLA R/W A DATA4 A Receive address is ignored Automatically transferred to slave receive mode Receive data is recognized as an address When the receive data matches to the address set in the SAR or SARX register, the I2C bus interface operates as a slave device. Figure 18.24 Diagram of Erroneous Operation when Arbitration is Lost Though it is prohibited in the normal I2C protocol, the same problem may occur when the MST bit is erroneously set to 1 and a transition to master mode is occurred during data transmission or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1 according to the order below. A. Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting the MST bit. B. Set the MST bit to 1. C. To confirm that the bus was not entered to the busy state while the MST bit is being set, check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been set. Rev. 3.00 Jan 11, 2005 page 792 of 1220 REJ09B0186-0300O Section 19 A/D Converter Section 19 A/D Converter 19.1 Overview The H8S/2643 Group incorporates a successive approximation type 10-bit A/D converter that allows up to sixteen analog input channels to be selected. 19.1.1 Features A/D converter features are listed below. • 10-bit resolution • Sixteen input channels • Settable analog conversion voltage range  Conversion of analog voltages with the reference voltage pin (Vref) as the analog reference voltage • High-speed conversion  Minimum conversion time: 10.64 µs per channel (at 25 MHz operation) • Choice of single mode or scan mode  Single mode: Single-channel A/D conversion  Scan mode: Continuous A/D conversion on 1 to 4 channels • Four data registers  Conversion results are held in a 16-bit data register for each channel • Sample and hold function • Three kinds of conversion start  Choice of software or timer conversion start trigger (TPU or 8-bit timer), or pin • A/D conversion end interrupt generation  A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion • Module stop mode can be set  As the initial setting, A/D converter operation is halted. Register access is enabled by exiting module stop mode. Rev. 3.00 Jan 11, 2005 page 793 of 1220 REJ09B0186-0300O GRTDA Section 19 A/D Converter 19.1.2 Block Diagram Figure 19.1 shows a block diagram of the A/D converter. Module data bus Bus interface Internal data bus AVCC Vref AVSS 10-bit D/A Successive approximations register A D D R A A D D R B A D D R C A D D R D A D C S R A D C R AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 + Multiplexer φ/2 φ/4 Control circuit φ/8 φ/16 – Comparator Sample-andhold circuit ADI interrupt Conversion start trigger from 8-bit timer or TPU A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D ADTRG Legend: ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: Figure 19.1 Block Diagram of A/D Converter Rev. 3.00 Jan 11, 2005 page 794 of 1220 REJ09B0186-0300O Section 19 A/D Converter 19.1.3 Pin Configuration Table 19.1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. The 16 analog input pins are divided into two channel sets and two groups, with analog input pins 0 to 7 (AN0 to AN7) comprising channel set 0, analog input pins 8 to 15 (AN8 to AN15) comprising channel set 1, analog input pins 0 to 3 and 8 to 11 (AN0 to AN3, AN8 to AN11) comprising group 0, and analog input pins 4 to 7 and 12 to 15 (AN4 to AN7, AN12 to AN15) comprising group 1. Table 19.1 A/D Converter Pins Pin Name Analog power supply pin Analog ground pin Reference voltage pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Analog input pin 8 Analog input pin 9 Analog input pin 10 Analog input pin 11 Analog input pin 12 Analog input pin 13 Analog input pin 14 Analog input pin 15 A/D external trigger input pin Symbol AVCC AVSS Vref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Channel set 1 (CH3 = 1) group 1 analog inputs Channel set 1 (CH3 = 1) group 0 analog inputs Channel set 0 (CH3 = 0) group 1 analog inputs Function Analog block power supply Analog block ground and reference voltage A/D conversion reference voltage Channel set 0 (CH3 = 0) group 0 analog inputs GRTDA Rev. 3.00 Jan 11, 2005 page 795 of 1220 REJ09B0186-0300O Section 19 A/D Converter 19.1.4 Register Configuration Table 19.2 summarizes the registers of the A/D converter. Table 19.2 A/D Converter Registers Name A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Module stop control register A Abbreviation ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR MSTPCRA R/W R R R R R R R R R/(W)* R/W R/W 2 Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'33 H'3F Address*1 H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FDE8 Notes: 1. Lower 16 bits of the address. 2. Bit 7 can only be written with 0 for flag clearing. Rev. 3.00 Jan 11, 2005 page 796 of 1220 REJ09B0186-0300O Section 19 A/D Converter 19.2 19.2.1 Bit Register Descriptions A/D Data Registers A to D (ADDRA to ADDRD) : 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R 0 — 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — Initial value : R/W : There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. Bits 5 to 0 are always read as 0. The correspondence between the analog input channels and ADDR registers is shown in table 19.3. ADDR can always be read by the CPU. The upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section 19.3, Interface to Bus Master. The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop mode. Table 19.3 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel Channel Set 0 (CH3 = 0) Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 Channel Set 1 (CH3 = 1) Group 0 AN8 AN9 AN10 AN11 Group 1 AN12 AN13 AN14 AN15 A/D Data Register ADDRA ADDRB ADDRC ADDRD Rev. 3.00 Jan 11, 2005 page 797 of 1220 REJ09B0186-0300O Section 19 A/D Converter 19.2.2 Bit A/D Control/Status Register (ADCSR) : 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CH3 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Initial value : R/W : Note: * Only 0 can be written to bit 7, to clear this flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations. ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode. Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion. Bit 7 ADF 0 Description [Clearing conditions] • • 1 • • W hen 0 is written to the ADF flag after reading ADF = 1 W hen the DMAC or DTC is activated by an ADI interrupt and ADDR is read Single mode: When A/D conversion ends Scan mode: When A/D conversion ends on all specified channels (Initial value) [Setting conditions] Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests at the end of A/D conversion. Bit 6 ADIE 0 1 Description A/D conversion end interrupt (ADI) request disabled A/D conversion end interrupt (ADI) request enabled (Initial value) Rev. 3.00 Jan 11, 2005 page 798 of 1220 REJ09B0186-0300O Section 19 A/D Converter Bit 5—A/D Start (ADST): Selects starting or stopping on A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external ). trigger input pin ( Bit 5 ADST 0 1 Description • • • A/D conversion stopped Single mode: Scan mode: (Initial value) Bit 4—Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating mode. See section 19.4, Operation, for single mode and scan mode operation. Only set the SCAN bit while conversion is stopped (ADST = 0). Bit 4 SCAN 0 1 Description Single mode Scan mode (Initial value) Bit 3—Channel Select 3 (CH3): Switches the analog input pins assigned to group 0 or group 1. Setting CH3 to 1 enables AN8 to AN15 to be used instead of AN0 to AN7. Bit 3 CH3 0 1 Description AN8 to AN11 are group 0 analog input pins, AN12 to AN15 are group 1 analog input pins AN0 to AN3 are group 0 analog input pins, AN4 to AN7 are group 1 analog input pins (Initial value) GRTDA A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. Rev. 3.00 Jan 11, 2005 page 799 of 1220 REJ09B0186-0300O Section 19 A/D Converter Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input channels. Only set the input channel while conversion is stopped (ADST = 0). Channel Selection CH3 0 CH2 0 CH1 0 1 1 0 1 1 0 0 1 1 0 1 CH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Single Mode (SCAN = 0) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 (Initial value) Description Scan Mode (SCAN = 1) AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 AN8 AN8, AN9 AN8 to AN10 AN8 to AN11 AN12 AN12, AN13 AN12 to AN14 AN12 to AN15 Rev. 3.00 Jan 11, 2005 page 800 of 1220 REJ09B0186-0300O Section 19 A/D Converter 19.2.3 Bit A/D Control Register (ADCR) : 7 TRGS1 0 R/W 6 TRGS0 0 R/W 5 — 1 — 4 — 1 — 3 CKS1 0 R/W 2 CKS0 0 R/W 1 — 1 — 0 — 1 — Initial value : R/W : ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations and sets the A/D conversion time. ADCR is initialized to H'33 by a reset, and in standby mode or module stop mode. Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): Select enabling or disabling of the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped (ADST = 0). Bit 7 TRGS1 0 1 Bit 6 TRGS0 0 1 0 1 Description A/D conversion start by software is enabled (Initial value) A/D conversion start by TPU conversion start trigger is enabled A/D conversion start by 8-bit timer conversion start trigger is enabled A/D conversion start by external trigger pin ( ) is enabled Bits 5, 4, 1, and 0—Reserved: They are always read as 1 and cannot be modified. Bits 3 and 2—Clock Select 1 and 0 (CKS1, CKS0): These bits select the A/D conversion time. The conversion time should be changed only when ADST = 0. Set bits CKS1 and CKS0 to give a conversion time of at least 10 µs when AVCC ≥ 4.5 V, and at least 16 µs when AVCC < 4.5 V. Bit 3 CKS1 0 1 Bit 2 CKS0 0 1 0 1 Description Conversion time = 530 states (max.) Conversion time = 266 states (max.) Conversion time = 134 states (max.) Conversion time = 68 states (max.) (Initial value) Rev. 3.00 Jan 11, 2005 page 801 of 1220 REJ09B0186-0300O GRTDA Section 19 A/D Converter 19.2.4 Bit Module Stop Control Register A (MSTPCRA) : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : MSTPCR is an 8-bit readable/writable register that performs module stop mode control. When the MSTPA1 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 24.5, Module Stop Mode. MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized by a manual reset and in software standby mode. Bit 1—Module Stop (MSTPA1): Specifies the A/D converter module stop mode. Bit 1 MSTPA1 0 1 Description A/D converter module stop mode cleared A/D converter module stop mode set (Initial value) Rev. 3.00 Jan 11, 2005 page 802 of 1220 REJ09B0186-0300O Section 19 A/D Converter 19.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading ADDR. always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 19.2 shows the data flow for ADDR access. Upper byte read Bus master (H'AA) Bus interface Module data bus TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Lower byte read Bus master (H'40) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Figure 19.2 ADDR Access Operation (Reading H'AA40) Rev. 3.00 Jan 11, 2005 page 803 of 1220 REJ09B0186-0300O Section 19 A/D Converter 19.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. 19.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1, according to the software or external trigger input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 19.3 shows a timing diagram for this example. [1] Single mode is selected (SCAN = 0), input channel AN1 is selected (CH3 = 0, CH2 = 0, CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). [2] When A/D conversion is completed, the result is transferred to ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. [3] Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. [4] The A/D interrupt handling routine starts. [5] The routine reads ADCSR, then writes 0 to the ADF flag. [6] The routine reads and processes the connection result (ADDRB). [7] Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps [2] to [7] are repeated. Rev. 3.00 Jan 11, 2005 page 804 of 1220 REJ09B0186-0300O Section 19 A/D Converter Set* ADIE ADST ADF State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Idle Idle Idle Idle A/D conversion 1 A/D conversion starts Set* Clear* Set* Clear* Idle A/D conversion 2 Idle ADDRA ADDRB ADDRC ADDRD Read conversion result A/D conversion result 1 Read conversion result A/D conversion result 2 Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 19.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Rev. 3.00 Jan 11, 2005 page 805 of 1220 REJ09B0186-0300O Section 19 A/D Converter 19.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by a software, timer or external trigger input, A/D conversion starts on the first channel in the group (AN0). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDR registers corresponding to the channels. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again from the first channel (AN0). The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described next. Figure 19.4 shows a timing diagram for this example. [1] Scan mode is selected (SCAN = 1), channel set 0 is selected (CH3 = 0), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1) [2] When A/D conversion of the first channel (AN0) is completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. [3] Conversion proceeds in the same way through the third channel (AN2). [4] When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. [5] Steps [2] to [4] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). Rev. 3.00 Jan 11, 2005 page 806 of 1220 REJ09B0186-0300O Section 19 A/D Converter Continuous A/D conversion execution Set*1 ADST ADF A/D conversion time State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Transfer ADDRA ADDRB ADDRC ADDRD Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. A/D conversion result 1 A/D conversion result 4 A/D conversion result 2 A/D conversion result 3 Idle Idle Idle A/D conversion 1 Clear*1 Clear*1 Idle A/D conversion 2 A/D conversion 4 Idle A/D conversion 5 *2 Idle A/D conversion 3 Idle Idle Idle Figure 19.4 Example of A/D Converter Operation (Scan Mode, 3 Channels AN0 to AN2 Selected) Rev. 3.00 Jan 11, 2005 page 807 of 1220 REJ09B0186-0300O Section 19 A/D Converter 19.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 19.5 shows the A/D conversion timing. Table 19.4 indicates the A/D conversion time. As indicated in figure 19.5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 19.4. In scan mode, the values given in table 19.4 apply to the first conversion time. The values given in table 19.5 apply to the second and subsequent conversions. In both cases, set bits CKS1 and CKS0 in ADCR to give a conversion time of at least 10 µs when AVCC ≥ 4.5 V, and at least 16 µs when AVCC < 4.5 V. (1) φ Address (2) Write signal Input sampling timing ADF tD t SPL t CONV Legend: (1): ADCSR write cycle (2): ADCSR address tD: A/D conversion start delay tSPL: Input sampling time tCONV: A/D conversion time Figure 19.5 A/D Conversion Timing Rev. 3.00 Jan 11, 2005 page 808 of 1220 REJ09B0186-0300O Section 19 A/D Converter Table 19.4 A/D Conversion Time (Single Mode) CKS1 = 0 CKS0 = 0 Item A/D conversion start delay Input sampling time A/D conversion time Symbol tD tSPL tCONV CKS0 = 1 CKS1 = 1 CKS0 = 0 CKS0 = 1 Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 18 — — 33 10 — — 63 17 — 266 6 — — 31 9 — 134 4 — 67 — 15 — 5 — 68 127 — 530 515 — 259 — 131 — Note: Values in the table are the number of states. Table 19.5 A/D Conversion Time (Scan Mode) CKS1 0 1 CKS0 0 1 0 1 Conversion Time (State) 512 (Fixed) 256 (Fixed) 128 (Fixed) 64 (Fixed) Rev. 3.00 Jan 11, 2005 page 809 of 1220 REJ09B0186-0300O Section 19 A/D Converter 19.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the pin. A falling edge at the pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit has been set to 1 by software. Figure 19.6 shows the timing. φ ADTRG Internal trigger signal ADST A/D conversion Figure 19.6 External Trigger Input Timing 19.5 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC and DMAC can be activated by an ADI interrupt. Having the converted data read by the DTC or DMAC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. The A/D converter interrupt source is shown in table 19.6. Table 19.6 A/D Converter Interrupt Source Interrupt Source ADI Description Interrupt due to end of conversion DTC, DMAC Activation Possible Rev. 3.00 Jan 11, 2005 page 810 of 1220 REJ09B0186-0300O GRTDA GRTDA Section 19 A/D Converter 19.6 Usage Notes The following points should be noted when using the A/D converter. (1) Setting Range of Analog Power Supply and Other Pins: (a) Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVSS ≤ ANn ≤ Vref. (b) Relation between AVCC, AVSS and VCC, VSS As the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS. If the A/D converter is not used, the AVCC and AVSS pins must on no account be left open. (c) Vref input range The analog reference voltage input at the Vref pin set in the range Vref ≤ AVCC. If conditions (a), (b), and (c) above are not met, the reliability of the device may be adversely affected. (2) Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN15), analog reference power supply (Vref), and analog power supply (AVCC) by the analog ground (AVSS). Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS) on the board. (3) Notes on Noise Countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN15) and analog reference power supply (Vref) should be connected between AVCC and AVSS as shown in figure 19.7. Also, the bypass capacitors connected to AVCC and Vref and the filter capacitor connected to AN0 to AN15 must be connected to AVSS. If a filter capacitor is connected as shown in figure 19.7, the input currents at the analog input pins (AN0 to AN15) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the Rev. 3.00 Jan 11, 2005 page 811 of 1220 REJ09B0186-0300O Section 19 A/D Converter sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC Vref Rin* 2 *1 *1 0.1 µF AVSS 100 AN0 to AN15 Notes: Values are reference values. 1. 10 µF 0.01 µF 2. Rin: Input impedance Figure 19.7 Example of Analog Input Protection Circuit Table 19.7 Analog Pin Specifications Item Analog input capacitance Permissible signal source impedance Min. — — Max. 20 5 Unit pF kΩ Rev. 3.00 Jan 11, 2005 page 812 of 1220 REJ09B0186-0300O Section 19 A/D Converter 10 kΩ AN0 to AN15 To A/D converter 20 pF Note: Values are reference values. Figure 19.8 Analog Input Pin Equivalent Circuit (4) A/D Conversion Precision Definitions H8S/2643 Group A/D conversion precision definitions are given below. • Resolution The number of A/D converter digital output codes • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'00) to B'0000000001 (H'01) (see figure 19.10). • Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3E) to B'1111111111 (H'3F) (see figure 19.10). • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 19.9). • Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error. • Absolute precision The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Rev. 3.00 Jan 11, 2005 page 813 of 1220 REJ09B0186-0300O Section 19 A/D Converter Digital output 111 110 101 100 011 010 001 000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 1024 1024 FS Analog input voltage Figure 19.9 A/D Conversion Precision Definitions (1) Rev. 3.00 Jan 11, 2005 page 814 of 1220 REJ09B0186-0300O Section 19 A/D Converter Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 19.10 A/D Conversion Precision Definitions (2) (5) Permissible Signal Source Impedance H8S/2643 Group analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the A/D converter’s sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 kΩ, charging may be insufficient and it may not be possible to guarantee the A/D conversion precision. However, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 kΩ, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/µs or greater). When converting a high-speed analog signal, a low-impedance buffer should be inserted. Rev. 3.00 Jan 11, 2005 page 815 of 1220 REJ09B0186-0300O Section 19 A/D Converter (6) Influences on Absolute Precision Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVSS. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. H8S/2643 Group Sensor output impedance to 5 kΩ Sensor input Low-pass filter C to 0.1 µF Cin = 15 pF A/D converter equivalent circuit 10 kΩ 20 pF Figure 19.11 Example of Analog Input Circuit Rev. 3.00 Jan 11, 2005 page 816 of 1220 REJ09B0186-0300O Section 20 D/A Converter Section 20 D/A Converter 20.1 Overview The H8S/2643 Group has an on-chip D/A converter module with four channels. 20.1.1 Features Features of the D/A converter module are listed below. • • • • • • Eight-bit resolution Four-channel output Maximum conversion time: 10 µs (with 20-pF load capacitance) Output voltage: 0 V to Vref D/A output retention in software standby mode Possible to set module stop mode  Operation of D/A converter is disenabled by initial values. It is possible to access the register by canceling module stop mode. Block Diagram 20.1.2 Figure 20.1 shows a block diagram of the D/A converter. Rev. 3.00 Jan 11, 2005 page 817 of 1220 REJ09B0186-0300O Section 20 D/A Converter Module data bus Bus interface Internal data bus Vref DADR0 (DADR2) AVCC DA1 (DA3) DA0 (DA2) AVSS 8-bit D/A DADR1 (DADR3) Control circuit Legend: DACR: D/A control register DADR0 to DADR3: D/A data register 0 to 3 Figure 20.1 Block Diagram of D/A Converter Rev. 3.00 Jan 11, 2005 page 818 of 1220 REJ09B0186-0300O DACR Section 20 D/A Converter 20.1.3 Input and Output Pins Table 20.1 lists the input and output pins used by the D/A converter module. Table 20.1 Input and Output Pins of D/A Converter Module Name Analog supply voltage Analog ground Analog output 0 Analog output 1 Analog output 2 Analog output 3 Reference voltage Abbreviation AVCC AVSS DA0 DA1 DA2 DA3 Vref I/O Input Input Output Output Output Output Input Function Power supply for analog circuits Ground and reference voltage for analog circuits Analog output channel 0 Analog output channel 1 Analog output channel 2 Analog output channel 3 Reference voltage of analog section 20.1.4 Register Configuration Table 20.2 lists the registers of the D/A converter module. Table 20.2 D/A Converter Registers Channel 0, 1 Name D/A data register 0 D/A data register 1 D/A control register 01 2, 3 D/A data register 2 D/A data register 3 D/A control register 23 All Module stop control register A Module stop control register C Note: * Lower 16 bits of the address. Abbreviation DADR0 DADR1 DACR01 DADR2 DADR3 DACR23 MSTPCRA MSTPCRC R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'1F H'00 H'00 H'1F H'3F H'FF Address* H'FFA4 H'FFA5 H'FFA6 H'FDAC H'FDAD H'FDAE H'FDE8 H'FDEA Rev. 3.00 Jan 11, 2005 page 819 of 1220 REJ09B0186-0300O Section 20 D/A Converter 20.2 20.2.1 Bit Register Descriptions D/A Data Registers 0 to 3 (DADR0 to DADR3) : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value : R/W : D/A data registers 0 to 3 (DADR0 to DADR3) are 8-bit readable/writable registers that store data to be converted. When analog output is enabled, the value in the D/A data register is converted and output continuously at the analog output pin. The D/A data registers are initialized to H'00 by a reset and in hardware standby mode. 20.2.2 Bit D/A Control Registers 01 and 23 (DACR01 and DACR23) : 7 DAOE1 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Initial value : R/W : DACR01 and DACR23 are an 8-bit readable/writable register that controls the operation of the D/A converter module. DACR01 and DACR23 are initialized to H'1F by a reset and in hardware standby mode. Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output. Bit 7 DAOE1 0 1 Description Analog output DA1 (DA3) is disabled (Initial value) D/A conversion is enabled on channel 1. Analog output DA1 (DA3) is enabled Rev. 3.00 Jan 11, 2005 page 820 of 1220 REJ09B0186-0300O Section 20 D/A Converter Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6 DAOE0 0 1 Description Analog output DA0 (DA2) is disabled (Initial value) D/A conversion is enabled on channel 0. Analog output DA0 (DA2) is enabled Bit 5—D/A Enable (DAE): Controls D/A conversion, in combination with bits DAOE0 and DAOE1. D/A conversion is controlled independently on channels 0 and 1 when DAE = 0. Channels 0 and 1 are controlled together when DAE = 1. Output of the converted results is always controlled independently by DAOE0 and DAOE1. Bit 7 DAOE1 0 Bit 6 DAOE0 0 1 Bit 5 DAE * 0 1 1 0 0 1 1 *: Don’t care * D/A conversion Disabled on channels 0 and 1 (channels 2 and 3) Enabled on channel 0 (channel 2) Disabled on channel 1 (channel 3) Enabled on channels 0 and 1 (channels 2 and 3) Disabled on channel 0 (channel 2) Enabled on channel 1 (channel 3) Enabled on channels 0 and 1 (channels 2 and 3) Enabled on channels 0 and 1 (channels 2 and 3) If the H8S/2643 Group chip enters software standby mode while D/A conversion is enabled, the D/A output is retained and the analog power supply current is the same as during D/A conversion. If it is necessary to reduce the analog power supply current in software standby mode, disable D/A output by clearing both the DAOE0 and DAOE1 bits to 0. Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1. Rev. 3.00 Jan 11, 2005 page 821 of 1220 REJ09B0186-0300O Section 20 D/A Converter 20.2.3 Module Stop Control Registers A and C (MSTPCRA and MSTPCRC) MSTPCRA Bit : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : MSTPCRC Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : R/W : MSTPCRA and MSTPCRC are 8-bit readable/writable registers that performs module stop mode control. When the MSTPA2 and MSTPC5 are set to 1, the D/A converter halts and enters module stop mode at the end of the bus cycle. Register read/write is disenabled in module stop mode. See section 24.5, Module Stop Mode, for details. MSTPCRA is initialized to H'3F by a power-on reset and in hardware standby mode. MSTPCRC is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset and in software standby mode. Rev. 3.00 Jan 11, 2005 page 822 of 1220 REJ09B0186-0300O Section 20 D/A Converter (1) Module Stop Control Register A (MSTPCRA) Bit 2—Module Stop (MSTPA2): Specifies D/A converter (channels 0 and 1) module stop mode. Bit 2 MSTPA2 0 1 Description D/A converter (channels 0 and 1) module stop mode is cleared D/A converter (channels 0 and 1) module stop mode is set (Initial value) (2) Module Stop Control Register C (MSTPCRC) Bit 5—Module Stop (MSTPC5): Specifies D/A converter (channels 2 and 3) module stop mode. Bit 5 MSTPC5 0 1 Description D/A converter (channels 2 and 3) module stop mode is cleared D/A converter (channels 2 and 3) module stop mode is set (Initial value) 20.3 Operation The D/A converter module has two built-in D/A converter circuits that can operate independently. D/A conversion is performed continuously whenever enabled by the D/A control register (DACR). When a new value is written in DADR0 or DADR1, conversion of the new value begins immediately. The converted result is output by setting the DAOE0 or DAOE1 bit to 1. An example of conversion on channel 0 is given next. Figure 20.2 shows the timing. • Software writes the data to be converted in DADR0. • D/A conversion begins when the DAOE0 bit in DACR is set to 1. After the elapse of the conversion time, analog output appears at the DA0 pin. The output value is Vref × (DADR0 value)/256. This output continues until a new value is written in DADR0 or the DAOE0 bit is cleared to 0. • If a new value is written in DADR0, conversion begins immediately. Output of the converted result begins after the conversion time. • When the DAOE0 bit is cleared to 0, DA0 becomes an input pin. Rev. 3.00 Jan 11, 2005 page 823 of 1220 REJ09B0186-0300O Section 20 D/A Converter DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle φ Address DADR0 Conversion data (1) Conversion data (2) DAOE0 DA0 High-impedance state Legend: t DCONV: D/A conversion time t DCONV Conversion result (1) Conversion result (2) t DCONV Figure 20.2 D/A Conversion (Example) Rev. 3.00 Jan 11, 2005 page 824 of 1220 REJ09B0186-0300O Section 21 RAM Section 21 RAM 21.1 Overview The H8S/2643 has 16 kbytes of on-chip high-speed static RAM, the H8S/2642 has 12 kbytes, and the H8S/2641 has 8 kbytes. The RAM is connected to the CPU by a 16-bit data bus, enabling onestate access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer. The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR). 21.1.1 Block Diagram Figure 21.1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FFB000 H'FFB002 H'FFB004 H'FFB001 H'FFB003 H'FFB005 H'FFEFBE H'FFFFC0 H'FFEFBF H'FFFFC1 H'FFFFFE H'FFFFFF Figure 21.1 Block Diagram of RAM (H8S/2643 Group) Rev. 3.00 Jan 11, 2005 page 825 of 1220 REJ09B0186-0300O Section 21 RAM 21.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 21.1 shows the address and initial value of SYSCR. Table 21.1 RAM Register Name System control register Abbreviation SYSCR R/W R/W Initial Value H'01 Address* H'FDE5 Note: * Lower 16 bits of the address. 21.2 21.2.1 Bit Register Descriptions System Control Register (SYSCR) : 7 MACS 0 R/W 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 MRESE 0 R/W 1 — 0 — 0 RAME 1 R/W Initial value : R/W : The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in SYSCR, see section 3.2.2, System Control Register (SYSCR). Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Note: When the DTC is used, the RAME bit must be set to 1. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) Rev. 3.00 Jan 11, 2005 page 826 of 1220 REJ09B0186-0300O Section 21 RAM 21.3 Operation When the RAME bit is set to 1, accesses to addresses H'FFB000 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in the H8S/2643, to addresses H'FFC000 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in the H8S/2642, and to addresses H'FFD000 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in the H8S/2641, are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or word units. Each type of access can be performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address. 21.4 Usage Notes (1) When Using the DTC DTC register information can be located in addresses H'FFEBC0 to H'FFEFBF. When the DTC is used, the RAME bit must not be cleared to 0. (2) Reserved Areas Addresses H'FFB000 to H'FFBFFF in the H8S/2642, and H'FFB000 to H'FFCFFF in the H8S/2641 are reserved areas that cannot be read or written to. When the RAME bit is cleared to 0, the off-chip address space is accessed. Rev. 3.00 Jan 11, 2005 page 827 of 1220 REJ09B0186-0300O Section 21 RAM Rev. 3.00 Jan 11, 2005 page 828 of 1220 REJ09B0186-0300O Section 22 ROM Section 22 ROM 22.1 Overview The H8/2643 Group has 256 kbytes of on-chip flash memory, or 256 , 192 , or 128 kbytes of onchip mask ROM. The ROM is connected to the bus master via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching is thus speeded up, and processing speed increased. The on-chip ROM is enabled and disabled by setting the mode pins (MD2 to MD0). The flash memory version can be erased and programmed on-board, as well as with a specialpurpose PROM programmer. 22.1.1 Block Diagram Figure 22.1 shows a block diagram of 256-kbyte ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000002 H'000001 H'000003 H'03FFFE H'03FFFF Figure 22.1 Block Diagram of ROM (256 Kbytes) 22.1.2 Register Configuration The H8/2643 Group operating mode is controlled by the mode pins and the BCRL register. The register configuration is shown in table 22.1. Rev. 3.00 Jan 11, 2005 page 829 of 1220 REJ09B0186-0300O Section 22 ROM Table 22.1 Register Configuration Register Name Mode control register Abbreviation MDCR R/W R/W Initial Value Undefined Address* H'FDE7 Note: * Lower 16 bits of the address. 22.2 22.2.1 Register Descriptions Mode Control Register (MDCR) Bit: Initial value: R/W: 7 — 1 R/W 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 MDS2 —* R 1 MDS1 —* R 0 MDS0 —* R Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit read-only register used to monitor the current H8/2643 Group operating mode. Bit 7—Reserved: Only 1 should be written to this bit. Bits 6 to 3—Reserved: Read-only bits, always read as 0. Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to MD0. MDS2 to MDS0 are read-only bits, and cannot be modified. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a power-on reset, but are retained in a manual reset. 22.3 Operation The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. Word data must start at an even address. The on-chip ROM is enabled and disabled by setting the mode pins (MD2 to MD0). These settings are shown in table 22.2. Rev. 3.00 Jan 11, 2005 page 830 of 1220 REJ09B0186-0300O Section 22 ROM Table 22.2 Operating Modes and ROM (F-ZTAT Version) Mode Pins Operating Mode Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Mode 8 Mode 9 Mode 10 Mode 11 Mode 12 Mode 13 Mode 14 User program mode (advanced expanded mode with on-chip ROM enabled)*1 User program mode (advanced singlechip mode)*2 1 Boot mode (advanced expanded mode 1 with on-chip ROM enabled)* Boot mode (advanced single-chip mode)*2 — 1 0 1 Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode — 1 0 0 1 1 0 1 — FWE 0 MD2 0 MD1 0 MD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Enabled (256 kbytes) Enabled (256 kbytes) Enabled (256 kbytes) Enabled (256 kbytes) — Enabled (256 kbytes) Enabled (256 kbytes) — Disabled On-Chip ROM — Mode 15 1 Notes: 1. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced expanded mode with on-chip ROM enabled. 2. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced single-chip mode. Rev. 3.00 Jan 11, 2005 page 831 of 1220 REJ09B0186-0300O Section 22 ROM Table 22.3 Operating Modes and ROM (Masked ROM Version) Mode Pins Operating Mode Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode 1 1 0 1 — MD2 0 MD1 0 MD0 0 1 0 1 0 1 0 1 Enabled (256 kbytes)* Enabled (256 kbytes)* Disabled On-Chip ROM — Note: * In the case of the H8S/2643. 192 kbytes are enabled in the H8S/2642, and 128 kbytes in the H8S/2641. Rev. 3.00 Jan 11, 2005 page 832 of 1220 REJ09B0186-0300O Section 22 ROM 22.4 22.4.1 Flash Memory Overview Features The H8S/2643 Group has 256 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode  Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time. Block erase (in single-block units) can be performed. To erase the entire flash memory, each block must be erased in turn. Block erasing can be performed as required on 4 kbytes, 32 kbytes, and 64 kbytes blocks. • Programming/erase times The flash memory programming time is 10 ms (typ.) for simultaneous 128-byte programming, equivalent to 78 µs (typ.) per byte, and the erase time is 100 ms (typ.). • Reprogramming capability The flash memory can be reprogrammed up to 100 times. • On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board:  Boot mode  User program mode • Automatic bit rate adjustment With data transfer in boot mode, the LSI’s bit rate can be automatically adjusted to match the transfer bit rate of the host. • Flash memory emulation in RAM Flash memory programming can be emulated in real time by overlapping a part of RAM onto flash memory. • Protect modes There are three protect modes, hardware, software, and error protection, which allow protected status to be designated for flash memory program/erase/verify operations. • Programmer mode Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode. Rev. 3.00 Jan 11, 2005 page 833 of 1220 REJ09B0186-0300O Section 22 ROM 22.4.2 Overview (1) Block Diagram Internal address bus Internal data bus (16 bits) Module bus FLMCR1 FLMCR2 EBR1 EBR2 RAMER FLPWCR Bus interface/controller Operating mode FWE pin Mode pin Flash memory (256 kbytes) Legend: FLMCR1: FLMCR2: EBR1: EBR2: RAMER: FLPWCR: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Flash memory power control register Figure 22.2 Block Diagram of Flash Memory Rev. 3.00 Jan 11, 2005 page 834 of 1220 REJ09B0186-0300O Section 22 ROM 22.4.3 Flash Memory Operating Modes (1) Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the microcomputer enters an operating mode as shown in figure 22.3. In user mode, flash memory can be read but not programmed or erased. The boot, user program and programmer modes are provided as modes to write and erase the flash memory. MD1 = 1, MD2 = 1, FWE = 0 *1 User mode (on-chip ROM enabled) RES = 0 Reset state RES = 0 MD1 = 1, MD2 = 1, FWE = 1 RES = 0 MD1 = 0, MD2 = 0, FWE = 1 RES = 0 Programmer mode *2 FWE = 1 FWE = 0 *1 User program mode Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. RAM emulation possible 2. MD0 = 0, MD1 = 0, MD2 = 0, P14 = 0, P16 = 0, PF0 = 1 Figure 22.3 Flash Memory State Transitions Rev. 3.00 Jan 11, 2005 page 835 of 1220 REJ09B0186-0300O Section 22 ROM 22.4.4 On-Board Programming Modes (1) Boot Mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the H8S/2643 (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Host Programming control program New application program New application program H8S/2643 Boot program Flash memory RAM SCI H8S/2643 Boot program Flash memory RAM Boot program area SCI Application program (old version) Application program (old version) Programming control program 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks. Host 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host New application program H8S/2643 Boot program Flash memory RAM Boot program area Flash memory preprogramming erase Programming control program H8S/2643 SCI Boot program Flash memory RAM Boot program area New application program Programming control program SCI Program execution state Rev. 3.00 Jan 11, 2005 page 836 of 1220 REJ09B0186-0300O Section 22 ROM (2) User Program Mode 1. Initial state The FWE assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. Host Programming/ erase control program New application program New application program 2. Programming/erase control program transfer When user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to RAM. Host H8S/2643 Boot program Flash memory FWE assessment program H8S/2643 SCI RAM Boot program Flash memory FWE assessment program SCI RAM Transfer program Transfer program Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. Host 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host New application program H8S/2643 Boot program Flash memory FWE assessment program H8S/2643 SCI RAM Boot program Flash memory FWE assessment program Transfer program Programming/ erase control program Programming/ erase control program SCI RAM Transfer program Flash memory erase New application program Program execution state Rev. 3.00 Jan 11, 2005 page 837 of 1220 REJ09B0186-0300O Section 22 ROM 22.4.5 Flash Memory Emulation in RAM Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. SCI Flash memory Emulation block RAM Overlap RAM (emulation is performed on data written in RAM) Application program Execution state Figure 22.4 Reading Overlap RAM Data in User Mode or User Program Mode When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten. Rev. 3.00 Jan 11, 2005 page 838 of 1220 REJ09B0186-0300O Section 22 ROM SCI Flash memory Programming data RAM Application program Overlap RAM (programming data) Programming control program execution state Figure 22.5 Writing Overlap RAM Data in User Program Mode 22.4.6 Differences between Boot Mode and User Program Mode Table 22.4 Differences between Boot Mode and User Program Mode Boot Mode Total erase Block erase Programming control program* Yes No Program/program-verify User Program Mode Yes Yes Erase/erase-verify Program/program-verify Emulation Note: * To be provided by the user, in accordance with the recommended algorithm. Rev. 3.00 Jan 11, 2005 page 839 of 1220 REJ09B0186-0300O Section 22 ROM 22.4.7 Block Configuration The flash memory is divided into three 64 kbytes blocks, one 32 kbytes block, and eight 4 kbytes blocks. Address H'00000 4 kbytes × 8 32 kbytes 256 kbytes 64 kbytes 64 kbytes 64 kbytes Address H'3FFFF Figure 22.6 Flash Memory Block Configuration Rev. 3.00 Jan 11, 2005 page 840 of 1220 REJ09B0186-0300O Section 22 ROM 22.4.8 Pin Configuration The flash memory is controlled by means of the pins shown in table 22.5. Table 22.5 Pin Configuration Pin Name Reset Flash write enable Mode 2 Mode 1 Mode 0 Port F0 Port 16 Port 14 Transmit data Receive data Abbreviation I/O Input Input Input Input Input Input Input Input Output Input Function Reset Flash memory program/erase protection by hardware Sets MCU operating mode Sets MCU operating mode Sets MCU operating mode Sets MCU operating mode in programmer mode Sets MCU operating mode in programmer mode Sets MCU operating mode in programmer mode Serial transmit data output Serial receive data input MD2 MD1 MD0 PF0 P16 P14 TxD2 RxD2 SER FWE Rev. 3.00 Jan 11, 2005 page 841 of 1220 REJ09B0186-0300O Section 22 ROM 22.4.9 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 22.6. In order to access these registers, the FLSHE bit in SCRX must be set to 1 (except for RAMER, SCRX). Table 22.6 Register Configuration Register Name Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Serial control register X Abbreviation FLMCR1*5 FLMCR2* EBR1* EBR2* 5 5 5 5 R/W R/W *2 R* 2 2 2 Initial Value H'00*3 H'00 H'00* H'00* H'00 H'00*4 H'00 4 4 Address*1 H'FFA8 H'FFA9 H'FFAA H'FFAB H'FEDB H'FFAC H'FDB4 R/W * R/W * R/W RAMER* SCRX Flash memory power control register FLPWCR*5 R/W *2 R/W Notes: 1. Lower 16 bits of the address. 2. To access these registers, set the FLSHE bit to 1 in serial control register X. Even if FLSHE is set to 1, if the chip is in a mode in which the on-chip flash memory is disabled, a read will return H'00 and writes are invalid. Writes are also invalid when the FWE bit in FLMCR1 is not set to 1. 3. When a high level is input to the FWE pin, the initial value is H'80. 4. When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in FLMCR1 is not set, these registers are initialized to H'00. 5. FLMCR1, FLMCR2, EBR1, and EBR2, RAMER, and FLPWCR are 8-bit registers. Use byte access on these registers. 22.5 22.5.1 Register Descriptions Flash Memory Control Register 1 (FLMCR1) FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'00000 to H'3FFFF is entered by setting SWE1 bit to 1 when FWE = 1, then setting the PV1 or EV1 bit. Program mode for addresses H'00000 to H'3FFFF is entered by setting SWE1 bit to 1 when FWE = 1, then setting the PSU1 bit, and finally setting the P1 bit. Erase mode for addresses H'00000 to H'3FFFF is entered by setting SWE1 bit to 1 when FWE = 1, then setting the ESU1 bit, and finally setting the E1 bit. FLMCR1 is initialized by a power-on reset, and in hardware standby mode and software standby mode. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Rev. 3.00 Jan 11, 2005 page 842 of 1220 REJ09B0186-0300O Section 22 ROM Writes are enabled only in the following cases: Writes to bit SWE1 of FLMCR1 enabled when FWE = 1, to bits ESU1, PSU1, EV1, and PV1 when FWE = 1 and SWE1 = 1, to bit E1 when FWE = 1, SWE1 = 1 and ESU1 = 1, and to bit P1 when FWE = 1, SWE1 = 1, and PSU1 = 1. Bit: Initial value: R/W: 7 FWE —* R 6 SWE1 0 R/W 5 ESU1 0 R/W 4 PSU1 0 R/W 3 EV1 0 R/W 2 PV1 0 R/W 1 E1 0 R/W 0 P1 0 R/W Note: * Determined by the state of the FWE pin. Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing. Bit 7 FWE 0 1 Description When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin Bit 6—Software Write Enable Bit 1 (SWE1): This bit selects write and erase valid/invalid of the flash memory. Set it when setting bits 5 to 0, bits 7 to 0 of EBR1, and bits 3 to 0 of EBR2. Bit 6 SWE1 0 1 Description Writes disabled Writes enabled [Setting condition] • W hen FWE = 1 (Initial value) Rev. 3.00 Jan 11, 2005 page 843 of 1220 REJ09B0186-0300O Section 22 ROM Bit 5—Erase Setup Bit 1 (ESU1): Prepares for a transition to erase mode. Set this bit to 1 before setting the E1 bit in FLMCR1 to 1. Do not set the SWE1, PSU1, EV1, PV1, E1, or P1 bit at the same time. Bit 5 ESU1 0 1 Description Erase setup cleared Erase setup [Setting condition] • W hen FWE = 1 and SWE1 = 1 (Initial value) Bit 4—Program Setup Bit 1 (PSU1): Prepares for a transition to program mode. Set this bit to 1 before setting the P1 bit in FLMCR1 to 1. Do not set the SWE1, ESU1, EV1, PV1, E1, or P1 bit at the same time. Bit 4 PSU1 0 1 Description Program setup cleared Program setup [Setting condition] • W hen FWE = 1 and SWE1 = 1 (Initial value) Bit 3—Erase-Verify 1 (EV1): Selects erase-verify mode transition or clearing. Do not set the SWE1, ESU1, PSU1, PV1, E1, or P1 bit at the same time. Bit 3 EV1 0 1 Description Erase-verify mode cleared Transition to erase-verify mode [Setting condition] • W hen FWE = 1 and SWE1 = 1 (Initial value) Rev. 3.00 Jan 11, 2005 page 844 of 1220 REJ09B0186-0300O Section 22 ROM Bit 2—Program-Verify 1 (PV1): Selects program-verify mode transition or clearing. Do not set the SWE1, ESU1, PSU1, EV1, E1, or P1 bit at the same time. Bit 2 PV1 0 1 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] • W hen FWE = 1 and SWE1 = 1 (Initial value) Bit 1—Erase 1 (E1): Selects erase mode transition or clearing. Do not set the SWE1, ESU1, PSU1, EV1, PV1, or P1 bit at the same time. Bit 1 E1 0 1 Description Erase mode cleared Transition to erase mode [Setting condition] • W hen FWE = 1, SWE1 = 1, and ESU1 = 1 (Initial value) Bit 0—Program 1 (P1): Selects program mode transition or clearing. Do not set the SWE1, PSU1, ESU1, EV1, PV1, or E1 bit at the same time. Bit 0 P1 0 1 Description Program mode cleared Transition to program mode [Setting condition] • W hen FWE = 1, SWE1 = 1, and PSU1 = 1 (Initial value) Rev. 3.00 Jan 11, 2005 page 845 of 1220 REJ09B0186-0300O Section 22 ROM 22.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is an 8-bit register used for flash memory operating mode control. FLMCR2 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00. Bit: Initial value: R/W: 7 FLER 0 R 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 — 0 — 1 — 0 — 0 — 0 — Note: FLMCR2 is a read-only register, and should not be written to. Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state. Bit 7 FLER 0 Description Flash memory is operating normally [Clearing condition] • 1 Power-on reset or hardware standby mode An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] • See section 22.8.3, Error Protection (Initial value) Flash memory program/erase protection (error protection) is disabled Bits 6 to 0—Reserved: These bits always read 0. Rev. 3.00 Jan 11, 2005 page 846 of 1220 REJ09B0186-0300O Section 22 ROM 22.5.3 Erase Block Register 1 (EBR1) EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE1 bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically cleared to 0. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory erase block configuration is shown in table 22.7. Bit: Initial value: R/W: 7 EB7 0 R/W 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W 0 EB0 0 R/W 22.5.4 Erase Block Register 2 (EBR2) EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin. Bit 0 will be initialized to 0 if bit SWE1 of FLMCR1 is not set, even though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically cleared to 0. Bits 7 to 4 are reserved and must only be written with 0. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory erase block configuration is shown in table 22.7. Bit: Initial value: R/W: 7 — 0 R/W 6 — 0 R/W 5 — 0 R/W 4 — 0 R/W 3 EB11 0 R/W 2 EB10 0 R/W 1 EB9 0 R/W 0 EB8 0 R/W Rev. 3.00 Jan 11, 2005 page 847 of 1220 REJ09B0186-0300O Section 22 ROM Table 22.7 Flash Memory Erase Blocks Block (Size) EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) EB8 (32 kbytes) EB9 (64 kbytes) EB10 (64 kbytes) EB11 (64 kbytes) Addresses H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF H'008000 to H'00FFFF H'010000 to H'01FFFF H'020000 to H'02FFFF H'030000 to H'03FFFF 22.5.5 RAM Emulation Register (RAMER) RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset and in software standby mode. RAMER settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 22.8. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bit: Initial value: R/W: 7 — 0 R 6 — 0 R 5 — 0 R/W 4 — 0 R/W 3 RAMS 0 R/W 2 RAM2 0 R/W 1 RAM1 0 R/W 0 RAM0 0 R/W Bits 7 and 6—Reserved: These bits always read 0. Bits 5 and 4—Reserved: Only 0 may be written to these bits. Rev. 3.00 Jan 11, 2005 page 848 of 1220 REJ09B0186-0300O Section 22 ROM Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory block are program/erase-protected. Bit 3 RAMS 0 1 Description Emulation not selected Program/erase-protection of all flash memory blocks is disabled Emulation selected Program/erase-protection of all flash memory blocks is enabled (Initial value) Bits 2 to 0—Flash Memory Area Selection: These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM. (See table 22.8.) Table 22.8 Flash Memory Area Divisions Addresses H'FFD000 to H'FFDFFF H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF Block Name RAM area 4 kbytes EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) RAMS 0 1 1 1 1 1 1 1 1 RAM1 * 0 0 0 0 1 1 1 1 RAM1 * 0 0 1 1 0 0 1 1 RAM0 * 0 1 0 1 0 1 0 1 *: Don't care Rev. 3.00 Jan 11, 2005 page 849 of 1220 REJ09B0186-0300O Section 22 ROM 22.5.6 Flash Memory Power Control Register (FLPWCR) Bit: Initial value: R/W: 7 PDWND 0 R/W 6 — 0 R 5 — 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R 0 — 0 R FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. Bit 7—Power-Down Disable (PDWND): Enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. Bit 7 PDWND 0 1 Description Transition to flash memory power-down mode enabled Transition to flash memory power-down mode disabled (Initial value) Bits 6 to 0—Reserved: These bits always read 0. 22.5.7 Serial Control Register X (SCRX) Bit: Initial value: R/W: 7 — 0 R/W 6 IICX1 0 R/W 5 IICX0 0 R/W 4 IICE 0 R/W 3 FLSHE 0 R/W 2 — 0 R/W 1 — 0 R/W 0 — 0 R/W SCRX is an 8-bit readable/writable register that controls on-chip flash memory. SCRX is initialized to H'00 by a reset and in hardware standby mode. Bit 7—Reserved: This bit should always be written with 0. Bits 6 and 5—I2C Transfer Rate Select (IICX1, IICX0): These bits, together with bits CKS2 to CKS0 in ICMR, select the transfer rate in master mode. For details of the transfer rate, see section 18.2.4, I2C Bus Mode Register (ICMR). Rev. 3.00 Jan 11, 2005 page 850 of 1220 REJ09B0186-0300O Section 22 ROM Bit 4—I2C Master Enable (IICE): Controls access to the I2C bus interface data registers and control registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR). For details of the control, see section 18.2.7, Serial Control Register X (SCRX). Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Setting the FLSHE bit to 1 enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash memory control register contents are retained. Bit 3 FLSHE 0 1 Description Flash control registers deselected in area H'FFFFA8 to H'FFFFAC Flash control registers selected in area H'FFFFA8 to H'FFFFAC (Initial value) Bits 2 to 0—Reserved: Should always be written with 0. 22.6 On-Board Programming Modes When pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 22.9. For a diagram of the transitions to the various flash memory modes, see figure 22.11. Table 22.9 Setting On-Board Programming Modes Mode Boot mode User program mode Expanded mode Single-chip mode Expanded mode Single-chip mode 1 FWE 1 MD2 0 0 1 1 MD1 1 1 1 1 MD0 0 1 0 1 Rev. 3.00 Jan 11, 2005 page 851 of 1220 REJ09B0186-0300O Section 22 ROM 22.6.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The SCI channel to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2643 Group’s pins have been set to boot mode, the boot program built into the H8S/2643 Group is started and the programming control program prepared in the host is serially transmitted to the H8S/2643 Group via the SCI. In the H8S/2643 Group, the programming control program received via the SCI is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 22.7, and the boot mode execution procedure in figure 22.8. H8S/2643 Group Flash memory Host Write data reception Verify data transmission RxD2 SCI2 TxD2 On-chip RAM Figure 22.7 System Configuration in Boot Mode Rev. 3.00 Jan 11, 2005 page 852 of 1220 REJ09B0186-0300O Section 22 ROM Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate H8S/2643 measures low period of H'00 data transmitted by host H8S/2643 calculates bit rate and sets value in bit rate register After bit rate adjustment, H8S/2643 transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, LSI transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte H8S/2643 transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units H8S/2643 transmits received programming control program to host as verify data (echo-back) Transfer received programming control program to on-chip RAM No Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, H8S/2643 transmits one H'AA data byte to host Execute programming control program transferred to on-chip RAM n+1→n n = N? Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Figure 22.8 Boot Mode Execution Procedure Rev. 3.00 Jan 11, 2005 page 853 of 1220 REJ09B0186-0300O Section 22 ROM (1) Automatic SCI Bit Rate Adjustment Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 22.9 Automatic SCI Bit Rate Adjustment When boot mode is initiated, the H8S/2643 Group measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The H8S/2643 Group calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the H8S/2643 Group. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host’s transmission bit rate and the H8S/2643 Group’ system clock frequency, there will be a discrepancy between the bit rates of the host and the H8S/2643 Group. Set the host transfer bit rate at 2,400, 4,800, 9,600 or 19,200 bps to operate the SCI properly. Table 22.10 shows host transfer bit rates and system clock frequencies for which automatic adjustment of the H8S/2643 Group bit rate is possible. The boot program should be executed within this system clock range. Table 22.10 System Clock Frequencies for which Automatic Adjustment of H8S/2643 Group Bit Rate is Possible Host Bit Rate 2,400 bps 4,800 bps 9,600 bps 19,200 bps System Clock Frequency for Which Automatic Adjustment of H8S/2643 Group Bit Rate is Possible 2 to 8 MHz 4 to 16 MHz 8 to 25 MHz 16 to 25 MHz Rev. 3.00 Jan 11, 2005 page 854 of 1220 REJ09B0186-0300O Section 22 ROM (2) On-Chip RAM Area Divisions in Boot Mode In boot mode, the RAM area is divided into an area used by the boot program and an area to which the programming control program is transferred via the SCI, as shown in figure 22.10. The boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host. H'FFC000 Programming control program area (8 kbytes) H'FFDFFF H'FFE000 Boot program area (4 kbytes) H'FFEFBF Note: The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note also that the boot program remains in this area of the on-chip RAM even after control branches to the programming control program. Figure 22.10 RAM Areas in Boot Mode (3) Notes on Use of Boot Mode • When the chip comes out of reset in boot mode, it measures the low-level period of the input at the SCI’s RxD2 pin. The reset should end with RxD2 high. After the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period of the RxD2 pin. • In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. • Interrupts cannot be used while the flash memory is being programmed or erased. • The RxD2 and TxD2 pins should be pulled up on the board. • Before branching to the programming control program (RAM area H'FFC000), the chip terminates transmit and receive operations by the on-chip SCI (channel 2) (by clearing the RE Rev. 3.00 Jan 11, 2005 page 855 of 1220 REJ09B0186-0300O Section 22 ROM and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD2, goes to the high-level output state (PA1DDR = 1, PA1DR = 1). The contents of the CPU’s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. The initial values of other on-chip registers are not changed. • Boot mode can be entered by making the pin settings shown in table 22.9 and executing a reset-start. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the FWE pin and mode pins, and executing reset release*1. Boot mode can also be cleared by a WDT overflow reset. Do not change the mode pin input levels in boot mode, and do not drive the FWE pin low while the boot program is being executed or while flash memory is being programmed or erased*2. • If the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins ( , , ) will change according to the change in the microcomputer’s operating mode*3. Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS = 4 states) with respect to the reset release timing. 2. For further information on FWE application and disconnection, see section 22.13, Flash Memory Programming and Erasing Precautions. 3. See appendix D, Pin States. 22.6.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary. To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7), and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7. Rev. 3.00 Jan 11, 2005 page 856 of 1220 REJ09B0186-0300O RWH DR SA Section 22 ROM The flash memory itself cannot be read while the SWE1 bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM or external memory. If the program is to be located in external memory, the instruction for writing to flash memory, and the following instruction, should be placed in on-chip RAM. Figure 22.11 shows the procedure for executing the program/erase control program when transferred to on-chip RAM. Write the FWE assessment program and transfer program (and the program/erase control program if necessary) beforehand MD2, MD1, MD0 = 110, 111 Reset-start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area FWE = high* Execute program/erase control program (flash memory rewriting) Clear FWE* Branch to flash memory application program Notes: Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only when the flash memory is programmed or erased. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * For further information on FWE application and disconnection, see section 22.13, Flash Memory Programming and Erasing Precautions. Figure 22.11 User Program Mode Execution Procedure Rev. 3.00 Jan 11, 2005 page 857 of 1220 REJ09B0186-0300O Section 22 ROM 22.7 Programming/Erasing Flash Memory A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes are made by setting the PSU1, ESU1, P1, E1, PV1, and EV1 bits in FLMCR1 for addresses H'000000 to H'03FFFF. The flash memory cannot be read while it is being written or erased. The flash memory cannot be read while being programmed or erased. Therefore, the program (user program) that controls flash memory programming/erasing should be located and executed in on-chip RAM or external memory. If the program is to be located in external memory, the instruction for writing to flash memory, and the following instruction, should be placed in on-chip RAM. Also ensure that the DTC and DMAC is not activated before or after execution of the flash memory write instruction. In the following operation descriptions, wait times after setting or clearing individual bits in FLMCR1 are given as parameters; for details of the wait times, see section 25.6, Flash Memory Characteristics. Notes: 1. Operation is not guaranteed if bits SWE1, ESU1, PSU1, EV1, PV1, E1, and P1 of FLMCR1 are set/reset by a program in flash memory in the corresponding address areas. 2. When programming or erasing, set FWE to 1 (programming/erasing will not be executed if FWE = 0). 3. Programming should be performed in the erased state. Do not perform additional programming on previously programmed addresses. Rev. 3.00 Jan 11, 2005 page 858 of 1220 REJ09B0186-0300O Section 22 ROM *3 E1 = 1 Erase setup state E1 = 0 Normal mode ESU1 = 1 ESU1 = 0 Erase-verify mode Erase mode *1 FWE = 1 FWE = 0 *2 EV1 = 1 EV1 = 0 PSU1 = 1 PSU1 = 0 On-board SWE1 = 1 Software programming mode programming Software programming enable disable state SWE1 = 0 state *4 P1 = 1 Program setup state P1 = 0 Program mode PV1 = 1 PV1 = 0 Program-verify mode Notes: In order to perform a normal read of flash memory, SWE must be cleared to 0. Also note that verify-reads can be performed during the programming/erasing process. 1. : Normal mode : On-board programming mode 2. Do not make a state transition by setting or clearing multiple bits simultaneously. 3. After a transition from erase mode to the erase setup state, do not enter erase mode without passing through the software programming enable state. 4. After a transition from program mode to the program setup state, do not enter program mode without passing through the software programming enable state. Figure 22.12 FLMCR1 Bit Settings and State Transitions 22.7.1 Program Mode When writing data or programs to flash memory, the program/program-verify flowchart shown in figure 22.13 should be followed. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a time. Rev. 3.00 Jan 11, 2005 page 859 of 1220 REJ09B0186-0300O Section 22 ROM The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N1 + N2) are shown in table 25.13 in section 25.6, Flash Memory Characteristics. Following the elapse of (x0) µs or more after the SWE1 bit is set to 1 in FLMCR1, 128-byte program data is stored in the program data area and reprogram data area, and the 128-byte data in the program data area in RAM is written consecutively to the program address (the lower 8 bits of the first address written to must be H'00 or H'80). 128 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than (y + z2 + α + β) ms as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU1 bit in FLMCR1, and after the elapse of (y) µs or more, the operating mode is switched to program mode by setting the P1 bit in FLMCR1. The time during which the P1 bit is set is the flash memory programming time. Refer to the table in figure 22.13 for the programming time. 22.7.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of the given programming time, clear the P1 bit in FLMCR1, then wait for at least (α) µs before clearing the PSU1 bit to exit program mode. After the elapse of at least (β) µs, the watchdog timer is cleared and the operating mode is switched to program-verify mode by setting the PV1 bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 22.13) and transferred to RAM. After verification of 128 bytes of data has been completed, exit program-verify mode, wait for at least (η) µs, then clear the SWE1 bit in FLMCR1. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. The maximum number of repetitions of the program/program-verify sequence is indicated by the maximum programming count (N1 + N2). However, ensure that the program/program-verify sequence is not repeated more than (N1 + N2) times on the same bits. Rev. 3.00 Jan 11, 2005 page 860 of 1220 REJ09B0186-0300O Section 22 ROM Notes on Program/Program-Verify Procedure (1) In order to perform 128-byte-unit programming, the lower 8 bits of the write start address must be H'00 or H'80. (2) When performing continuous writing of 128-byte data to flash memory, byte-unit transfer should be used. 128-byte data transfer is necessary even when writing fewer than 128 bytes of data. Write H'FF data to the extra addresses. (3) Verify data is read in word units. (4) The write pulse is applied and a flash memory write executed while the P1 bit in FLMCR1 is set. In the H8S/2643, write pulses should be applied as follows in the program/program-verify procedure to prevent voltage stress on the device and loss of write data reliability. a. After write pulse application, perform a verify-read in program-verify mode and apply a write pulse again for any bits read as 1 (reprogramming processing). When all the 0-write bits in the 128-byte write data are read as 0 in the verify-read operation, the program/program-verify procedure is completed. In the H8S/2643, the number of loops in reprogramming processing is guaranteed not to exceed the maximum value of the maximum programming count (N). b. After write pulse application, a verify-read is performed in program-verify mode, and programming is judged to have been completed for bits read as 0. c. If programming of other bits is incomplete in the 128 bytes, reprogramming processing should be executed. If a bit for which programming has been judged to be completed is read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit. (5) The period for which the P1 bit in FLMCR1 is set (the write pulse width) should be changed according to the degree of progress through the program/program-verify procedure. For detailed wait time specifications, see section 25.6, Flash Memory Characteristics. (6) The program/program-verify flowchart for the H8S/2643 is shown in figure 22.13. To cover the points noted above, bits on which reprogramming processing is to be executed, and bits on which additional programming is to be executed, must be determined as shown below. Since reprogram data and additional-programming data vary according to the progress of the programming procedure, it is recommended that the following data storage areas (128 bytes each) be provided in RAM. Rev. 3.00 Jan 11, 2005 page 861 of 1220 REJ09B0186-0300O Section 22 ROM Reprogram Data Computation Table Result of Verify-Read after Write Pulse (X) Application (V) Result of Operation 0 1 0 1 1 0 1 1 (D) 0 0 1 1 Comments Programming completed: reprogramming processing not to be executed Programming incomplete: reprogramming processing to be executed  Still in erased state: no action Legend: (D): Source data of bits on which programming is executed (X): Source data of bits on which reprogramming is executed Additional-Programming Data Computation Table Result of Verify-Read after Write Pulse (Y) (X') Application (V) Result of Operation 0 0 0 Comments Programming by write pulse application judged to be completed: additional programming processing to be executed Programming by write pulse application incomplete: additional programming processing not to be executed Programming already completed: additional programming processing not to be executed Still in erased state: no action 0 1 1 1 1 0 1 1 1 Legend: (Y): Data of bits on which additional programming is executed (X'): Data of bits on which reprogramming is executed in a certain reprogramming loop (7) It is necessary to execute additional programming processing during the course of the H8S/2643 program/program-verify procedure. However, once 128-byte-unit programming is finished, additional programming should not be carried out on the same address area. When executing reprogramming, an erase must be executed first. Note that normal operation of reads, etc., is not guaranteed if additional programming is performed on addresses for which a program/program-verify operation has finished. Rev. 3.00 Jan 11, 2005 page 862 of 1220 REJ09B0186-0300O Section 22 ROM Start of programming START Set SWE1 bit in FLMCR1 Write pulse application subroutine Sub-Routine Write Pulse Enable WDT Set PSU1 bit in FLMCR1 Wait (y) µs Set P1 bit in FLMCR1 tsp10 or tsp30 or tsp200: Wait (z0) µs or (z1) µs or (z2) µs Clear P1 bit in FLMCR1 Wait (α) µs Clear PSU1 bit in FLMCR1 Wait (β) µs Disable WDT End Sub Note: 6. Programming Time P1 Bit Set Time (µs) Additional Number of Writes Programming Programming 1 z0 z1 2 z0 z1 · · · · · · · · · Programming must be executed in the erased state. Do not perform additional programming on addresses that have already been programmed. Wait (× 0) µs Store 128 bytes of program data in program *4 data area and reprogram data area n=1 m=0 Successively write 128-byte reprogram data to flash memory Sub-Routine-Call *1 Write pulse application subroutine Set PV1 bit in FLMCR1 Wait (γ) µs H'FF dummy write to verify address Wait (ε) µs Read verify data Increment address Program data = verify data? OK N1 ≥ n? NG NG m=1 n←n+1 *2 OK Additional-programming data computation Transfer additional-programming data to additional-programming data area Reprogram data computation *4 *3 *4 N1 – 1 N1 N1 + 1 N1 + 2 N1 + 3 · · · z0 z0 z2 z2 z2 · · · z1 z1 — — — · · · Transfer reprogram data to reprogram data area 128-byte data verification completed? OK Clear PV1 bit in FLMCR1 tcpv: NG N1 + N2 – 2 N1 + N2 – 1 N1 + N2 z2 z2 z2 — — — Wait (η) µs N1 ≥ n? NG RAM Program data storage area (128 bytes) Successively write 128-byte data from additional- 1 * programming data area in RAM to flash memory Sub-Routine-Call Additional programming subroutine Reprogram data storage area (128 bytes) m=0? NG n (N1 + N2) ? NG Additional-programming data storage area (128 bytes) OK Clear SWE1 bit in FLMCR1 tcswe: OK Clear SWE1 bit in FLMCR1 Wait (×1) µs Programming failure Wait (×1) µs End of programming Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (word) units. 3. Even bits for which programming has been completed in the 128-byte programming loop will be subject to programming again if they fail the subsequent verify operation. 4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional-programming data must be provided in RAM. The reprogram and additional-programming data contents are modified as programming proceeds. 5. A write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See note 6 for details of the pulse widths. When writing of additional-programming data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied. Reprogram Data Computation Table Original Data (D) 0 0 1 1 Verify Data (V) 0 1 0 1 Reprogram Data (X) 1 0 1 1 Comments Programming complete Programming is incomplete: reprogramming should be performed Left in the erased state Additional-Programming Data Computation Table Reprogram Data (X') 0 0 1 1 Verify Data (V) 0 1 0 1 Additional-Programming Data (X) 0 1 1 1 Comments Additional programming should be performed Additional programming should not be performed Additional programming should not be performed Additional programming should not be performed Figure 22.13 Program/Program-Verify Flowchart Rev. 3.00 Jan 11, 2005 page 863 of 1220 REJ09B0186-0300O Section 22 ROM 22.7.3 Erase Mode When erasing flash memory, the single-block erase/erase-verify flowchart shown in figure 22.14 should be followed. To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in erase block register 1 and 2 (EBR1, EBR2) at least (x) µs after setting the SWE1 bit to 1 in FLMCR1. Next, the watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. Set a value greater than (y + z + α + β) ms as the WDT overflow period. Preparation for entering erase mode (erase setup) is performed next by setting the ESU1 bit in FLMCR1. The operating mode is then switched to erase mode by setting the E1 bit in FLMCR1 after the elapse of at least (y) µs. The time during which the E1 bit is set is the flash memory erase time. Ensure that the erase time does not exceed (z) ms. Note: With flash memory erasing, preprogramming (setting all memory data in the memory to be erased to all 0) is not necessary before starting the erase procedure. 22.7.4 Erase-Verify Mode In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the fixed erase time, clear the E1 bit in FLMCR1, then wait for at least (α) µs before clearing the ESU1 bit to exit erase mode. After exiting erase mode, the watchdog timer is cleared after the elapse of (β) µs or more. The operating mode is then switched to erase-verify mode by setting the EV1 bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data is unerased, set erase mode again and repeat the erase/erase-verify sequence in the same way. The maximum number of reoperations of the erase/erase-verify sequence is indicated by the maximum erase count (N). However, ensure that the erase/erase-verify sequence is not repeated more than (N) times. When verification is completed, exit erase-verify mode, and wait for at least (η) µs. If erasure has been completed on all the erase blocks, clear the SWE1 bit in FLMCR1. If there are any unerased blocks, make a 1 bit setting for the flash memory area to be erased, and repeat the erase/eraseverify sequence as before. Rev. 3.00 Jan 11, 2005 page 864 of 1220 REJ09B0186-0300O Section 22 ROM Start *1 Set SWE1 bit in FLMCR1 Wait (x) µs n=1 Set EBR1 and 2 Enable WDT Set ESU1 bit in FLMCR1 Wait (y) µs Set E1 bit in FLMCR1 Wait (z) ms Clear E1 bit in FLMCR1 Wait (α) µs Clear ESU1 bit in FLMCR1 Wait (β) µs Disable WDT Set EV1 bit in FLMCR1 Wait (γ) µs Set block start address to verify address n←n+1 Halt erase Start erase *3 H'FF dummy write to verify address Wait (ε) µs Increment address Read verify data Verify data = all "1"? OK NG Last address of block? OK Clear EV1 bit in FLMCR1 Wait (η) µs NG *4 *2 NG Clear EV1 bit in FLMCR1 Wait (η) µs NG End of erasing of all erase blocks? OK n ≥ (N)? OK Clear SWE1 bit in FLMCR1 Wait (× 1) µs Erase failure Clear SWE1 bit in FLMCR1 Wait (× 1) µs End of erasing Notes: 1. 2. 3. 4. Preprogramming (setting erase block data to all "0") is not necessary. Verify data is read in 16-bit (W) units. Set only one bit in EBR1 and 2. More than 2 bits cannot be set. Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn. Figure 22.14 Erase/Erase-Verify Flowchart Rev. 3.00 Jan 11, 2005 page 865 of 1220 REJ09B0186-0300O Section 22 ROM 22.8 Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 22.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2). The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained in the error-protected state. (See table 22.11.) Table 22.11 Hardware Protection Functions Item FWE pin protection Description • W hen a low level is input to the FWE pin, FLMCR1, FLMCR2, (except bit FLER) EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. Program Yes Erase Yes Reset/standby protection • In a power-on reset (including a WDT power- Yes on reset) and in standby mode, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. In a reset via the pin, the reset state is not entered unless the pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the pin low for the pulse width specified in the AC characteristics section. Yes Rev. 3.00 Jan 11, 2005 page 866 of 1220 REJ09B0186-0300O SER SER SER • SER Section 22 ROM 22.8.2 Software Protection Software protection can be implemented by setting the SWE1 bit in FLMCR1, erase block register 1 (EBR1), erase block register 2 (EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), does not cause a transition to program mode or erase mode. (See table 22.12.) Table 22.12 Software Protection Functions Item SWE bit protection Description • Program Erase Yes Setting bit SWE1 in FLMCR1 to 0 will place Yes area H'000000 to H'03FFFF in the program/erase-protected state. (Execute the program in the on-chip RAM, external memory) Erase protection can be set for individual blocks by settings in erase block register 1 (EBR1) and erase block register 2 (EBR2). Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state. Yes Setting the RAMS bit to 1 in the RAM emulation register (RAMER) places all blocks in the program/erase-protected state. — Block specification protection • Yes • Emulation protection • Yes Rev. 3.00 Jan 11, 2005 page 867 of 1220 REJ09B0186-0300O Section 22 ROM 22.8.3 Error Protection In error protection, an error is detected when H8S/2643 Group runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the H8S/2643 Group malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P1 or E1 bit. However, PV1 and EV1 bit setting is enabled, and a transition can be made to verify mode. FLER bit setting conditions are as follows: (1) When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) (2) Immediately after exception handling (excluding a reset) during programming/erasing (3) When a SLEEP instruction (including software standby) is executed during programming/erasing (4) When the CPU releases the bus to the DTC Error protection is released only by a power-on reset and in hardware standby mode. Rev. 3.00 Jan 11, 2005 page 868 of 1220 REJ09B0186-0300O Section 22 ROM Figure 22.15 shows the flash memory state transition diagram. Program mode Erase mode RD VF PR ER FLER = 0 RES = 0 or HSTBY = 0 Reset or standby (hardware protection) RD VF PR ER FLER = 0 Error occurrence (software standby) Error occurrence RES = 0 or HSTBY = 0 RES = 0 or HSTBY = 0 FLMCR1, FLMCR2, EBR1, EBR2 initialization state Error protection mode RD VF PR ER FLER = 1 Software standby mode Software standby mode release Error protection mode (software standby) RD VF PR ER FLER = 1 FLMCR1, FLMCR2, (except bit FLER) EBR1, EBR2 initialization state Legend: RD: Memory read possible VF: Verify-read possible PR: Programming possible ER: Erasing possible RD: VF: PR: ER: Memory read not possible Verify-read not possible Programming not possible Erasing not possible Figure 22.15 Flash Memory State Transitions Rev. 3.00 Jan 11, 2005 page 869 of 1220 REJ09B0186-0300O Section 22 ROM 22.9 Flash Memory Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses cannot be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 22.16 shows an example of emulation of real-time flash memory programming. Start of emulation program Set RAMER Write tuning data to overlap RAM Execute application program No Tuning OK? Yes Clear RAMER Write to flash memory emulation block End of emulation program Figure 22.16 Flowchart for Flash Memory Emulation in RAM Rev. 3.00 Jan 11, 2005 page 870 of 1220 REJ09B0186-0300O Section 22 ROM This area can be accessed from both the RAM area and flash memory area H'00000 EB0 H'01000 EB1 H'02000 EB2 H'03000 EB3 H'04000 EB4 H'05000 EB5 H'06000 EB6 H'07000 EB7 H'08000 H'FFD000 Flash memory EB8 to EB11 On-chip RAM H'FFEFBF H'3FFFF H'FFDFFF Figure 22.17 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB0 is Overlapped (1) Set bits RAMS, RAM2 to RAM0 in RAMER to 1, 0, 0, 0, to overlap part of RAM onto the area (EB0) for which real-time programming is required. (2) Real-time programming is performed using the overlapping RAM. (3) After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap. (4) The data written in the overlapping RAM is written into the flash memory space (EB0). Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of RAM2 to RAM0 (emulation protection). In this state, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), will not cause a transition to program mode or erase mode. When actually programming or erasing a flash memory area, the RAMS bit should be cleared to 0. 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 contains the vector table. When performing RAM emulation, the vector table is needed in the overlap RAM. Rev. 3.00 Jan 11, 2005 page 871 of 1220 REJ09B0186-0300O Section 22 ROM 22.10 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI interrupt is disabled when flash memory is being programmed or erased (when the P1 or E1 bit is set in FLMCR1), and while the boot program is executing in boot mode*1, to give priority to the program or erase operation. There are three reasons for this: (1) Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. (2) In the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly*2, possibly resulting in MCU runaway. (3) If interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, in on-board programming mode alone there are conditions for disabling interrupt, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All requests, including NMI interrupt, must therefore be restricted inside and outside the MCU when programming or erasing flash memory. NMI interrupt is also disabled in the error-protection state while the P1 or E1 bit remains set in FLMCR1. Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming control program has completed programming. 2. The vector may not be read correctly in this case for the following two reasons: • If flash memory is read while being programmed or erased (while the P1 or E1 bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned). • If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. 22.11 Flash Memory Programmer Mode Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, flash memory read mode, auto-program mode, autoerase mode, and status read mode are supported. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. In programmer mode, set the mode pins to programmer mode (see table 22.13) and input a 12 MHz input clock. Rev. 3.00 Jan 11, 2005 page 872 of 1220 REJ09B0186-0300O Section 22 ROM Table 22.13 shows the pin settings for programmer mode. Table 22.13 Programmer Mode Pin Settings Pin Names Mode pins: MD2, MD1, MD0 Mode setting pins: PF0, P16, P14 FWE pin pin Settings Low level input to MD2, MD1, and MD0. High level input to PF0, low level input to P16 and P14 High level input (in auto-program and auto-erase modes) Power-on reset circuit Oscillator circuit 22.11.1 Socket Adapter and Memory Map Memory read (verify), write, and flash memory initialize (erase all) are supported in the writer mode using a PROM writer. In this case a general purpose PROM writer is used with a custom socket adapter installed. Table 22.14 lists suitable socket adapter models. The socket adapter used with the write mode of the LSI must be one of the models listed in table 22.14. Table 22.14 Socket Adapter Models Product Model HD64F2643FC HD64F2643TF Package 144-pin QFP (FP-144J) 144-pin TQFP (TFP-144) Socket Adapter Model ME2643ESHF1H HF2643Q144D4001 ME2643ESNHH Manufacturer Minato Electronics Inc. Data-IO Japan Inc. Minato Electronics Inc. SER XTAL, EXTAL, PLLVCC, PLLCAP, PLLVSS pins Rev. 3.00 Jan 11, 2005 page 873 of 1220 REJ09B0186-0300O Section 22 ROM 22.11.2 Programmer Mode Operation Table 22.15 shows how the different operating modes are set when using programmer mode, and table 22.16 lists the commands used in programmer mode. Details of each mode are given below. (1) Memory Read Mode Memory read mode supports byte reads. (2) Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. (3) Auto-Erase Mode Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-programming. (4) Status Read Mode Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the I/O6 signal. In status read mode, error information is output if an error occurs. Table 22.15 Settings for Various Operating Modes In Programmer Mode Pin Names Read Output disable Command write Chip disable*1 H or L H or L H or L*3 H or L L L H L X L L H H H X H Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. Ain indicates that there is also address input in auto-program mode. 3. For command writes in auto-program and auto-erase modes, input a high level to the FWE pin. Rev. 3.00 Jan 11, 2005 page 874 of 1220 REJ09B0186-0300O EW EO EC Mode FWE I/O7 to I/O0 Data output Hi-Z Data input Hi-Z A18 to A0 Ain X Ain*2 X Section 22 ROM Table 22.16 Programmer Mode Commands Number of Cycles 1+n 129 2 2 1st Cycle Mode Write Write Write Write Address X X X X Data H'00 H'40 H'20 H'71 Mode Read Write Write Write 2nd Cycle Address RA WA X X Data Dout Din H'20 H'71 Command Name Memory read mode Auto-program mode Auto-erase mode Status read mode Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n). 22.11.3 Memory Read Mode (1) After completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. When reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. (2) In memory read mode, command writes can be performed in the same way as in the command wait state. (3) Once memory read mode has been entered, consecutive reads can be performed. (4) After powering on, memory read mode is entered. Table 22.17 AC Characteristics in Transition to Memory Read Mode (Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C) Item Command write cycle hold time setup time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 — — Max — — — — — — 30 30 Unit µs ns ns ns ns ns ns ns EW EW EC EC Data hold time Data setup time Write pulse width rise time fall time Rev. 3.00 Jan 11, 2005 page 875 of 1220 REJ09B0186-0300O Section 22 ROM Command write A18 to A0 tces CE tceh tnxtc Memory read mode Address stable OE tf WE twep tr tds I/O7 to I/O0 tdh Note: Data is latched on the rising edge of WE. Figure 22.18 Timing Waveforms for Memory Read after Memory Write Table 22.18 AC Characteristics in Transition from Memory Read Mode to Another Mode (Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C) Item Command write cycle hold time setup time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 — — Max — — — — — — 30 30 Unit µs ns ns ns ns ns ns ns EW EW EC EC Data hold time Data setup time Write pulse width rise time fall time Rev. 3.00 Jan 11, 2005 page 876 of 1220 REJ09B0186-0300O Section 22 ROM Memory read mode A18 to A0 Address stable tnxtc CE tces tceh Other mode command write OE tf WE twep tr tds I/O7 to I/O0 Note: Do not enable WE and OE at the same time. tdh Figure 22.19 Timing Waveforms in Transition from Memory Read Mode to Another Mode Table 22.19 AC Characteristics in Memory Read Mode (Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C) Item Access time output delay time output delay time Symbol tacc tce toe tdf toh Min — — — — 5 Max 20 150 150 100 — Unit µs ns ns ns ns EO EC Output disable delay time Data output hold time Rev. 3.00 Jan 11, 2005 page 877 of 1220 REJ09B0186-0300O Section 22 ROM A18 to A0 Address stable Address stable CE OE WE I/O7 to I/O0 VIL VIL VIH tacc toh tacc toh A18 to A0 CE Address stable tce toe OE WE VIH tacc toh I/O7 to I/O0 tdf tacc toh 22.11.4 Auto-Program Mode (1) In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. (2) A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. (3) The lower 7 bits of the transfer address must be low. If a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. (4) Memory address transfer is performed in the second cycle (figure 22.22). Do not perform transfer after the third cycle. (5) Do not perform a command write during a programming operation. Rev. 3.00 Jan 11, 2005 page 878 of 1220 REJ09B0186-0300O EO EC Figure 22.21 and EO EC Figure 22.20 and Enable State Read Timing Waveforms Address stable tce toe tdf Clock System Read Timing Waveforms Section 22 ROM (6) Perform one auto-program operation for a 128-byte block for each address. Two or more additional programming operations cannot be performed on a previously programmed address block. (7) Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-program operation end decision pin). (8) Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling and . Table 22.20 AC Characteristics in Auto-Program Mode (Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C) Item Command write cycle hold time setup time Symbol tnxtc tceh tces tdh tds twep twsts tspa tas tah twrite tpns tpnh tr tf Min 20 0 0 50 50 70 1 — 0 60 1 100 100 — — Max — — — — — — — 150 — — 3000 — — 30 30 Unit µs ns ns ns ns ns ms ns ns ns ms ns ns ns ns Data hold time Data setup time Write pulse width Status polling start time Status polling access time Address setup time Address hold time Memory write time Write setup time Write end setup time rise time fall time Rev. 3.00 Jan 11, 2005 page 879 of 1220 REJ09B0186-0300O EC EO EW EW EC EC Section 22 ROM FWE tpnh Address stable tpns tces tceh tnxtc tnxtc A18 to A0 CE OE tf twep tr tas tah Data transfer 1 to 128 bytes twsts tspa WE tds tdh twrite Write operation end decision signal I/O7 I/O6 I/O5 to I/O0 Write normal end decision signal H'40 H'00 Figure 22.22 Auto-Program Mode Timing Waveforms 22.11.5 Auto-Erase Mode (1) Auto-erase mode supports only entire memory erasing. (2) Do not perform a command write during auto-erasing. (3) Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin). (4) Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling and . Rev. 3.00 Jan 11, 2005 page 880 of 1220 REJ09B0186-0300O EC EO Section 22 ROM Table 22.21 AC Characteristics in Auto-Erase Mode (Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C) Item Command write cycle hold time setup time Symbol tnxtc tceh tces tdh tds twep tests tspa terase tens tenh tr tf Min 20 0 0 50 50 70 1 — 100 100 100 — — Max — — — — — — — 150 40000 — — 30 30 Unit µs ns ns ns ns ns ms ns ms ns ns ns ns EW EW EC EC Data hold time Data setup time Write pulse width Status polling start time Status polling access time Memory erase time Erase setup time Erase end setup time rise time fall time FWE tenh A18 to A0 tens tces tceh tnxtc tnxtc CE OE tf twep tr tests tspa WE tds tdh terase Erase end decision signal I/O7 I/O6 I/O5 to I/O0 Erase normal end decision signal H'20 H'20 H'00 Figure 22.23 Auto-Erase Mode Timing Waveforms Rev. 3.00 Jan 11, 2005 page 881 of 1220 REJ09B0186-0300O Section 22 ROM 22.11.6 Status Read Mode (1) Status read mode is provided to identify the kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. (2) The return code is retained until a command write other than a status read mode command write is executed. Table 22.22 AC Characteristics in Status Read Mode (Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C) Item Read time after command write hold time setup time Symbol tnxtc tceh tces tdh tds twep toe tdf tce tr tf Min 20 0 0 50 50 70 — — — — — Max — — — — — — 150 100 150 30 30 Unit µs ns ns ns ns ns ns ns ns ns ns Rev. 3.00 Jan 11, 2005 page 882 of 1220 REJ09B0186-0300O EW EW EC EO EC EC Data hold time Data setup time Write pulse width output delay time output delay time rise time fall time Disable delay time A18 to A0 tces tceh tnxtc tces tceh tnxtc tnxtc CE tce OE tf twep tr tf twep tr toe WE tds tdh H'71 tds H'71 tdh tdf I/O7 to I/O0 Note: I/O2 and I/O3 are undefined. Figure 22.24 Status Read Mode Timing Waveforms Section 22 ROM Table 22.23 Status Read Mode Return Commands Pin Name I/O7 Attribute Normal end decision I/O6 Command error I/O5 Programming error I/O4 Erase error I/O3 — I/O2 — I/O1 I/O0 ProgramEffective ming or address erase count error exceeded 0 0 Initial value 0 Indications Normal end: 0 Abnormal end: 1 0 Command error: 1 0 0 0 0 — ProgramErasing — error: 1 ming Otherwise: 0 error: 1 Otherwise: 0 Otherwise: 0 Count Effective exceeded: 1 address Otherwise: 0 error: 1 Otherwise: 0 Note: I/O2 and I/O3 are undefined. 22.11.7 Status Polling (1) The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode. (2) The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase mode. Table 22.24 Status Polling Output Truth Table Pin Name I/O7 I/O6 I/O0 to I/O5 During Internal Operation 0 0 0 Abnormal End 1 0 0 — 0 1 0 Normal End 1 1 0 22.11.8 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 22.25 Stipulated Transition Times to Command Wait State Item Standby release (oscillation stabilization time) Programmer mode setup time VCC hold time Symbol tosc1 tbmv tdwn Min 30 10 0 Max — — — Unit ms ms ms Rev. 3.00 Jan 11, 2005 page 883 of 1220 REJ09B0186-0300O Section 22 ROM Memory read mode Command Auto-program mode wait state Auto-erase mode tosc1 VCC tbmv Command wait state Normal/abnormal end decision tdwn RES FWE Note: When using other than the automatic write mode and automatic erase mode, drive the FWE input pin low. Figure 22.25 Oscillation Stabilization Time, Boot Program Transfer Time, and Power-Down Sequence 22.11.9 Notes on Memory Programming (1) When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. (2) When performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: The flash memory is initially in the erased state when the device is shipped by Renesas. For other chips for which the erasure history is unknown, it is recommended that autoerasing be executed to check and supplement the initialization (erase) level. Auto-programming should be performed once only on the same address block. Additional programming cannot be performed on previously programmed address blocks. Rev. 3.00 Jan 11, 2005 page 884 of 1220 REJ09B0186-0300O Section 22 ROM 22.12 Flash Memory and Power-Down States In addition to its normal operating state, the flash memory has power-down states in which power consumption is reduced by halting part or all of the internal power supply circuitry. There are three flash memory operating states: (1) Normal operating mode: The flash memory can be read and written to. (2) Power-down mode: Part of the power supply circuitry is halted, and the flash memory can be read when the H8S/2643 is operating on the subclock. (3) Standby mode: All flash memory circuits are halted, and the flash memory cannot be read or written to. States (2) and (3) are flash memory power-down states. Table 22.26 shows the correspondence between the operating states of the H8S/2643 and the flash memory. Table 22.26 Flash Memory Operating States LSI Operating State High-speed mode Medium-speed mode Sleep mode Subactive mode Subsleep mode Watch mode Software standby mode Hardware standby mode When PDWND = 0: Power-down mode (read-only) When PDWND = 1: Normal mode (read-only) Standby mode Flash Memory Operating State Normal mode (read/write) 22.12.1 Note on Power-Down States When the flash memory is in a power-down state, part or all of the internal power supply circuitry is halted. Therefore, a power supply circuit stabilization period must be provided when returning to normal operation. When the flash memory returns to its normal operating state from a powerdown state, bits STS2 to STS0 in SBYCR must be set to provide a wait time of at least 20 µs (power supply stabilization time), even if an oscillation stabilization period is not necessary. Rev. 3.00 Jan 11, 2005 page 885 of 1220 REJ09B0186-0300O Section 22 ROM 22.13 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode, the RAM emulation function, and programmer mode are summarized below. (1) Use the specified voltages and timing for programming and erasing Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas microcomputer device type with 256-kbyte on-chip flash memory (FZTAT256V3A). Do not select the HN27C4096 setting for the PROM programmer, and only use the specified socket adapter. Failure to observe these points may result in damage to the device. (2) Powering on and off (see figures 22.26 to 22.28) Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low before turning off VCC. When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. (3) FWE application/disconnection (see figures 22.26 to 22.28) FWE application should be carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection state. The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: • Apply FWE when the VCC voltage has stabilized within its rated voltage range. • Apply FWE when oscillation has stabilized (after the elapse of the oscillation stabilization time). • In boot mode, apply and disconnect FWE during a reset. • In user program mode, FWE can be switched between high and low level regardless of the reset state. FWE input can also be switched during execution of a program in flash memory. • Do not apply FWE if program runaway has occurred. • Disconnect FWE only when the SWE1, ESU1, PSU1, EV1, PV1, P1, and E1 bits in FLMCR1 are cleared. Rev. 3.00 Jan 11, 2005 page 886 of 1220 REJ09B0186-0300O Section 22 ROM Make sure that the SWE1, ESU1, PSU1, EV1, PV1, P1, and E1 bits are not set by mistake when applying or disconnecting FWE. (4) Do not apply a constant high level to the FWE pin Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. (5) Use the recommended algorithm when programming and erasing flash memory The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P1 or E1 bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. (6) Do not set or clear the SWE1 bit during execution of a program in flash memory Wait for at least 100 µs after clearing the SWE1 bit before executing a program or reading data in flash memory. When the SWE1 bit is set, data in flash memory can be rewritten, but when SWE1 = 1, flash memory can only be read in program-verify or erase-verify mode. Access flash memory only for verify operations (verification during programming/erasing). Also, do not clear the SWE1 bit during programming, erasing, or verifying. Similarly, when using the RAM emulation function while a high level is being input to the FWE pin, the SWE1 bit must be cleared before executing a program or reading data in flash memory. However, the RAM area overlapping flash memory space can be read and written to regardless of whether the SWE1 bit is set or cleared. (7) Do not use interrupts while flash memory is being programmed or erased All interrupt requests, including NMI, should be disabled during FWE application to give priority to program/erase operations. (8) Do not perform overwriting. Erase the memory before reprogramming In on-board programming, perform only one programming operation on a 128-byte programming unit block. In programmer mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. Rev. 3.00 Jan 11, 2005 page 887 of 1220 REJ09B0186-0300O Section 22 ROM (9) Before programming, check that the chip is correctly mounted in the PROM programmer Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. (10) Do not touch the socket adapter or chip during programming Touching either of these can cause contact faults and write errors. Programming/ erasing possible Wait time: 100 µs Wait time: x φ tOSC1 VCC Min 0 µs FWE tMDS*3 Min 0 µs MD2 to MD0*1 tMDS*3 RES SWE1 set SWE1 bit SWE1 cleared Period during which flash memory access is prohibited (x: Wait time after setting SWE1 bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off by pulling the pins up or down. 2. See section 25.6, Flash Memory Characteristics. 3. Mode programming setup time tMDS (min.) = 200 ns Figure 22.26 Power-On/Off Timing (Boot Mode) Rev. 3.00 Jan 11, 2005 page 888 of 1220 REJ09B0186-0300O Section 22 ROM Programming/ erasing possible Wait time: 100 µs Wait time: x φ tOSC1 VCC Min 0 µs FWE MD2 to MD0*1 tMDS*3 RES SWE1 set SWE1 bit SWE1 cleared Period during which flash memory access is prohibited (x: Wait time after setting SWE1 bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until power-off by pulling the pins up or down. 2. See section 25.6, Flash Memory Characteristics. 3. Mode programming setup time tMDS (min.) = 200 ns Figure 22.27 Power-On/Off Timing (User Program Mode) Rev. 3.00 Jan 11, 2005 page 889 of 1220 REJ09B0186-0300O Section 22 ROM Wait time: x Programming/erasing possible Wait time: x Programming/erasing possible Wait time: 100 µs Wait time: x Programming/erasing possible Wait time: 100 µs Programming/erasing possible Wait time: 100 µs φ tOSC1 VCC Min 0 µs FWE tMDS tMDS*2 MD2 to MD0 tMDS tRESW RES SWE1 set Mode change*1 Boot mode SWE1 cleared Mode User change*1 mode User program mode User mode User program mode SWE1 bit Period during which flash memory access is prohibited (x: Wait time after setting SWE1 bit)*3 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of RES input. The state of ports with multiplexed address functions and bus control output pins (AS, RD, WR) will change during this switchover interval (the interval during which the RES pin input is low), and therefore these pins should not be used as output signals during this time. 2. When making a transition from boot mode to another mode, a mode programming setup time tMDS (min.) of 200 ns is necessary with respect to RES clearance timing. 3. See section 25.6, Flash Memory Characteristics. Figure 22.28 Mode Transition Timing (Example: Boot Mode → User Mode ↔ User Program Mode) Rev. 3.00 Jan 11, 2005 page 890 of 1220 REJ09B0186-0300O Wait time: x Wait time: 100 µs Section 22 ROM 22.14 Note on Switching from F-ZTAT Version to Masked ROM Version The masked ROM version does not have the internal registers for flash memory control that are provided in the F-ZTAT version. Table 22.27 lists the registers that are present in the F-ZTAT version but not in the masked ROM version. If a register listed in table 22.27 is read in the masked ROM version, an undefined value will be returned. Therefore, if application software developed on the F-ZTAT version is switched to a masked ROM version product, it must be modified to ensure that the registers in table 22.27 have no effect. Table 22.27 Registers Present in F-ZTAT Version but Absent in Masked ROM Version Register Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Abbreviation FLMCR1 FLMCR2 EBR1 EBR2 RAMER Address H'FFA8 H'FFA9 H'FFAA H'FFAB H'FEDB Rev. 3.00 Jan 11, 2005 page 891 of 1220 REJ09B0186-0300O Section 22 ROM Rev. 3.00 Jan 11, 2005 page 892 of 1220 REJ09B0186-0300O Section 23 Clock Pulse Generator Section 23 Clock Pulse Generator 23.1 Overview The H8S/2643 Group has a built-in clock pulse generator (CPG) that generates the system clock (φ), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator, PLL (phase-locked loop) circuit, clock selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock oscillator, and waveform shaping circuit. The frequency can be changed by means of the PLL circuit in the CPG. Frequency changes are performed by software by means of settings in the system clock control register (SCKCR) and low-power control register (LPWRCR). 23.1.1 Block Diagram Figure 23.1 shows a block diagram of the clock pulse generator. LPWRCR STC1, STC0 SCKCR SCK2 to SCK0 EXTAL XTAL System clock oscillator PLL circuit (×1, ×2, ×4) Clock selection circuit φ SUB Mediumspeed clock divider φ/2 to φ/32 Bus master clock selection circuit φ OSC1 OSC2 Subclock oscillator Waveform shaping circuit System clock Internal clock to to φ pin supporting modules Bus master clock to CPU, DMAC and DTC WDT1 count clock Legend: LPWRCR: Low-power control register SCKCR: System clock control register Figure 23.1 Block Diagram of Clock Pulse Generator Rev. 3.00 Jan 11, 2005 page 893 of 1220 REJ09B0186-0300O Section 23 Clock Pulse Generator 23.1.2 Register Configuration The clock pulse generator is controlled by SCKCR and LPWRCR. Table 23.1 shows the register configuration. Table 23.1 Clock Pulse Generator Register Name System clock control register Low-power control register Abbreviation SCKCR LPWRCR R/W R/W R/W Initial Value H'00 H'00 Address* H'FDE6 H'FDEC Note:* Lower 16 bits of the address. 23.2 23.2.1 Bit Register Descriptions System Clock Control Register (SCKCR) : 7 PSTOP 0 R/W 6 — 0 — 5 — 0 — 4 — 0 — 3 STCS 0 R/W 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W Initial value: R/W : SCKCR is an 8-bit readable/writable register that performs φ clock output control, selection of operation when the PLL circuit frequency multiplication factor is changed, and medium-speed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—φ Clock Output Disable (PSTOP): Controls φ output. Description Bit 7 PSTOP 0 1 High-Speed Mode, Medium-Speed Mode, Sleep Mode, Sub-Active Mode Sub-Sleep Mode φ output (initial value) Fixed high φ output Fixed high Software Standby Mode, Watch Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance Bits 6 and 4—Reserved: These bits are always read as 0 and cannot be modified. Rev. 3.00 Jan 11, 2005 page 894 of 1220 REJ09B0186-0300O Section 23 Clock Pulse Generator Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation when the PLL circuit frequency multiplication factor is changed. Bit 3 STCS 0 1 Description Specified multiplication factor is valid after transition to software standby mode, watch mode, and subactive mode (Initial value) Specified multiplication factor is valid immediately after STC bits are rewritten Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master clock. Bit 2 SCK2 0 Bit 1 SCK1 0 1 1 0 1 Bit 0 SCK0 0 1 0 1 0 1 — Description Bus master is in high-speed mode Medium-speed clock is φ/2 Medium-speed clock is φ/4 Medium-speed clock is φ/8 Medium-speed clock is φ/16 Medium-speed clock is φ/32 — (Initial value) 23.2.2 Bit Low-Power Control Register (LPWRCR) : 7 DTON 0 R/W 6 LSON 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 — 0 R/W 1 STC1 0 R/W 0 STC0 0 R/W NESEL SUBSTP RFCUT Initial value : R/W : LPWRCR is an 8-bit readable/writable register that performs power-down mode control. The following pertains to bits 1 and 0. For details of the other bits, see section 24.2.3, Low-Power Control Register (LPWRCR). LPWRCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized in software standby mode. Rev. 3.00 Jan 11, 2005 page 895 of 1220 REJ09B0186-0300O Section 23 Clock Pulse Generator Bits 1 and 0—Frequency Multiplication Factor (STC1, STC0): The STC bits specify the frequency multiplication factor of the PLL circuit. Bit 1 STC1 0 1 Bit 0 STC0 0 1 0 1 Description ×1 ×2 ×4 Setting prohibited (Initial value) Notes: A system clock frequency multiplied by the multiplication factor (STC1 and STC0) should not exceed the maximum operating frequency defined in section 25, Electrical Characteristics. Current consumption and noise can be reduced by using this function’s PLL ×4 setting and lowering the external clock frequency. 23.3 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 23.3.1 Connecting a Crystal Resonator (1) Circuit Configuration A crystal resonator can be connected as shown in the example in figure 23.2. Select the damping resistance Rd according to table 23.2. An AT-cut parallel-resonance crystal should be used. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF Figure 23.2 Connection of Crystal Resonator (Example) Rev. 3.00 Jan 11, 2005 page 896 of 1220 REJ09B0186-0300O Section 23 Clock Pulse Generator Table 23.2 Damping Resistance Value Frequency (MHz) 2 Rd (Ω) 1k 4 500 8 200 12 0 16 0 20 0 25 0 (2) Crystal Resonator Figure 23.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 23.3. CL L XTAL Rs EXTAL AT-cut parallel-resonance type C0 Figure 23.3 Crystal Resonator Equivalent Circuit Table 23.3 Crystal Resonator Parameters Frequency (MHz) 2 RS max (Ω) C0 max (pF) 500 7 4 120 7 8 80 7 12 60 7 16 50 7 20 40 7 25 40 7 (3) Note on Board Design When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 23.4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Rev. 3.00 Jan 11, 2005 page 897 of 1220 REJ09B0186-0300O Section 23 Clock Pulse Generator Avoid CL2 Signal A Signal B H8S/2643 Group XTAL EXTAL CL1 Figure 23.4 Example of Incorrect Board Design External circuitry such as that shown below is recommended around the PLL. R1 PLLCAP Rp PLLVCC CPB* PLLVSS PVCC VCC CB* VSS C1 CB* Note: * CB and CPB are laminated ceramic capacitors. Recommended values: R1 = 3 kΩ Rp = 200 Ω C1 = 470 pF CB = CPB = 0.1 µF Figure 23.5 Points for Attention when Using PLL Oscillation Circuit Place oscillation stabilization capacitor C1 and resistor R1 close to the PLLCAP pin, and ensure that no other signal lines cross this line. Supply the C1 ground from PLLVSS. Separate PLLVCC and PLLVSS from the other VCC and VSS lines at the board power supply source, and be sure to insert bypass capacitors CPB and CB close to the pins. Rev. 3.00 Jan 11, 2005 page 898 of 1220 REJ09B0186-0300O Section 23 Clock Pulse Generator 23.3.2 External Clock Input (1) Circuit Configuration An external clock signal can be input as shown in the examples in figure 23.6. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode. EXTAL XTAL Open External clock input (a) XTAL pin left open EXTAL XTAL External clock input (b) Complementary clock input at XTAL pin Figure 23.6 External Clock Input (Examples) Rev. 3.00 Jan 11, 2005 page 899 of 1220 REJ09B0186-0300O Section 23 Clock Pulse Generator (2) External Clock Table 23.4 and figure 23.7 show the input conditions for the external clock. Table 23.4 External Clock Input Conditions VCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V Item Symbol Min. 20 20 — — 0.4 80 Clock high pulse width level tCH 0.4 80 Max. — — 10 10 0.6 — 0.6 — VCC = 3.0 V to 3.6 V PVCC = 5.0 V ±10% Min. 15 15 — — 0.4 80 0.4 80 Max. — — 5 5 0.6 — 0.6 — Unit ns ns ns ns tcyc ns tcyc ns φ ≥ 5 MHz φ < 5 MHz φ ≥ 5 MHz φ < 5 MHz Figure 25.2 Test Conditions Figure 23.7 External clock input low tEXL pulse width External clock input high pulse width External clock fall time Clock low pulse width level tEXH External clock rise time tEXr tEXf tCL tEXH tEXL EXTAL VCC × 0.5 tEXr tEXf Figure 23.7 External Clock Input Timing Rev. 3.00 Jan 11, 2005 page 900 of 1220 REJ09B0186-0300O Section 23 Clock Pulse Generator 23.4 PLL Circuit The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 1, 2, or 4. The multiplication factor is set with the STC bits in LPWRCR. The phase of the rising edge of the internal clock is controlled so as to match that at the EXTAL pin. When setting the multiplication factor, ensure that the clock frequency after multiplication does not exceed the maximum operating frequency of the chip. When the multiplication factor of the PLL circuit is changed, the operation varies according to the setting of the STCS bit in SCKCR. When STCS = 0 (initial value), the setting becomes valid after a transition to software standby mode, watch mode, or subactive mode. The transition time count is performed in accordance with the setting of bits STS2 to STS0 in SBYCR. [1] The initial PLL circuit multiplication factor is 1. [2] A value is set in bits STS2 to STS0 to give the specified transition time. [3] The target value is set in STC1 and STC0, and a transition is made to software standby mode, watch mode, or subactive mode. [4] The clock pulse generator stops and the value set in STC1 and STC0 becomes valid. [5] Software standby mode, watch mode, or subactive mode is cleared, and a transition time is secured in accordance with the setting in STS2 to STS0. [6] After the set transition time has elapsed, the LSI resumes operation using the target multiplication factor. If a PC break is set for the SLEEP instruction that causes a transition to software standby mode in [3], software standby mode is entered and break exception handling is executed after the oscillation stabilization time. In this case, the instruction following the SLEEP instruction is executed after execution of the RTE instruction. When STCS = 1, the LSI operates on the changed multiplication factor immediately after bits STC1 and STC0 are rewritten. Rev. 3.00 Jan 11, 2005 page 901 of 1220 REJ09B0186-0300O Section 23 Clock Pulse Generator 23.5 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32. 23.6 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed clocks (φ/2, φ/4, φ/8, φ/16, and φ/32) to be supplied to the bus master, according to the settings of the SCK2 to SCK0 bits in SCKCR. 23.7 Subclock Oscillator (1) Connecting 32.768 kHz Quartz Oscillator To supply a clock to the subclock oscillator, connect a 32.768 kHz quartz oscillator, as shown in figure 23.8. See (3), Note on Board Design in section 23.3.1, Connecting a Crystal Resonator, for points to be noted when connecting a crystal oscillator. C1 OSC1 C2 OSC2 C1 = C2 = 15 pF (typ.) Figure 23.8 Example Connection of 32.768 kHz Crystal Oscillator Rev. 3.00 Jan 11, 2005 page 902 of 1220 REJ09B0186-0300O Section 23 Clock Pulse Generator Figure 23.9 shows the equivalence circuit for a 32.768 kHz oscillator. Ls Cs Rs OSC1 Co Co = 1.5 pF (typ.) Rs = 14 kΩ (typ.) fw = 32.768 kHz OSC2 Figure 23.9 Equivalence Circuit for 32.768 kHz Oscillator (2) Handling pins when subclock not required If no subclock is required, connect the OSC1 pin to VCC and leave OSC2 open, as shown in figure 23.10. VCC OSC1 OSC2 Open Figure 23.10 Pin Handling When Subclock Not Required 23.8 Subclock Waveform Shaping Circuit To eliminate noise from the subclock input to OSC1, the subclock is sampled using the dividing clock φ. The sampling frequency is set using the NESEL bit of LPWRCR. For details, see section 24.2.3, Low Power Control Register (LPWRCR). No sampling is performed in sub-active mode, sub-sleep mode, or watch mode. Rev. 3.00 Jan 11, 2005 page 903 of 1220 REJ09B0186-0300O Section 23 Clock Pulse Generator 23.9 Note on Crystal Resonator Since various characteristics related to the crystal resonator are closely linked to the user’s board design, thorough evaluation is necessary on the user’s part, for both the mask versions and F-ZTAT versions, using the resonator connection examples shown in this section as a guide. As the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. Rev. 3.00 Jan 11, 2005 page 904 of 1220 REJ09B0186-0300O Section 24 Power-Down Modes Section 24 Power-Down Modes 24.1 Overview In addition to the normal program execution state, the H8S/2643 Group has eight power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. The H8S/2643 Group operating modes are as follows: (1) High-speed mode (2) Medium-speed mode (3) Subactive mode (4) Sleep mode (5) Subsleep mode (6) Watch mode (7) Module stop mode (8) Software standby mode (9) Hardware standby mode (2) to (9) are power down modes. Sleep mode and sub-sleep mode are CPU mode, medium-speed mode is a CPU and bus master mode, sub-active mode is a CPU and bus master and on-chip supporting module mode, and module stop mode is an on-chip supporting module mode (including bus masters other than the CPU) state. Some of these modes can be combined. After a reset, the LSI is in high-speed mode, with modules other than the DMAC and DTC in module stop mode. Table 24.1 shows the internal states of the LSI in the respective modes. Table 24.2 shows the conditions for shifting between the power-down modes. Figure 24.1 is a mode transition diagram. Rev. 3.00 Jan 11, 2005 page 905 of 1220 REJ09B0186-0300O Section 24 Power-Down Modes Table 24.1 LSI Internal States in Each Mode Function System clock pulse generator Subclock pulse generator CPU HighSpeed MediumSpeed Sleep Module Stop Watch Subactive Halted Software Hardware Subsleep Standby Standby Halted Halted Halted Function- Function- Function- Function- Halted ing ing ing ing Function- Function- Function- Function- Function- Function- Function- Function- Halted ing ing ing ing ing ing ing ing Instructions Function- Medium- Halted High/ Halted Subclock Halted Halted Halted Registers ing speed (retained) medium- (retained) operation (retained) (retained) (undefined) operation speed operation Function- Function- Function- Function- Function- Function- Function- Function- Halted External NMI ing ing ing ing ing ing ing ing interrupts IRQ0 to IRQ7 Peripheral WDT1 functions WDT0 TMR DMAC DTC TPU IIC0 IIC1 PCB PPG D/A0, 1 SCI0 SCI1 SCI2 SCI3 SCI4 PWM0, 1 A/D RAM I/O Function- Function- Function- Function- Retained Function- Retained Retained Retained ing ing ing ing (DTC) ing Function- Function- Function- Function- Retained Function- Retained Retained High ing ing ing ing ing* impedance Function- Function- Function- Halted ing ing ing (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) Function- Function- Function- Function- Subclock Subclock Subclock Halted Halted ing ing ing ing operation operation operation (retained) (reset) Function- Function- Function- Function- Halted Subclock Subclock Halted Halted ing ing ing ing (retained) operation operation (retained) (reset) Halted (retained) Function- Medium- Function- Halted Halted Halted Halted Halted Halted (retained) (retained) (retained) (retained) (retained) (reset) ing speed ing operation Halted Halted Halted Halted Halted Function- Function- Function- Halted (retained) (retained) (retained) (retained) (retained) (reset) ing ing ing Notes: “Halted (retained)” means that internal register values are retained. The internal state is “operation suspended.” “Halted (reset)” means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). Rev. 3.00 Jan 11, 2005 page 906 of 1220 REJ09B0186-0300O Section 24 Power-Down Modes * With the exception of ports D and E, an I/O port always returns a value of 1 when read in the H8S/2643F-ZTAT. Use as an output port is possible. Program-halted state STBY pin = Low Reset state STBY pin = High RES pin = Low Hardware standby mode RES pin = High Program execution state SLEEP command High-speed mode (main clock) Any interrupt SCK2 to SCK0 = 0 SCK2 to SCK0 0 SLEEP command SSBY = 1, PSS = 0, LSON = 0 Software standby mode SSBY = 0, LSON = 0 Sleep mode (main clock) Medium-speed mode (main clock) External interrupt *3 SLEEP command Interrupt *2 LSON bit = 0 SSBY = 1, PSS = 1, DTON = 0 Watch mode (subclock) SLEEP command SSBY = 1, PSS = 1 DTON = 1, LSON = 0 After the oscillation stabilization time (STS2 to 0), clock switching exception processing SLEEP command SSBY = 1, PSS = 1 DTON = 1, LSON = 1 Clock switching exception processing SLEEP command Interrupt *1 LSON bit = 1 SLEEP command Interrupt *2 SSBY = 0, PSS = 1, LSON = 1 Sub-sleep mode (subclock) Sub-active mode (subclock) : Transition after exception processing : Low power dissipation mode Notes: When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. From any state except hardware standby mode, a transition to the reset state occurs when RES is driven Low. From any state, a transition to hardware standby mode occurs when STBY is driven low. Always select high-speed mode before making a transition to watch mode or sub-active mode. 1. NMI, IRQ0 to IRQ7, and WDT1 interrupts 2. NMI, IRQ0 to IRQ7, IWDT0 interrupts, WDT1 interrupt, and TMR0 to TMR3 interrupts 3. NMI and IRQ0 to IRQ7 Figure 24.1 Mode Transition Diagram Rev. 3.00 Jan 11, 2005 page 907 of 1220 REJ09B0186-0300O Section 24 Power-Down Modes Table 24.2 Power-Down Mode Transition Conditions Status of Control Bit at Transition SSBY PSS * * 0 0 1 1 1 1 0 1 1 0 1 1 1 1 State After Transition State After Transition Back from Low Power Invoked by SLEEP Mode Invoked by Interrupt High-speed/Medium-speed — High-speed/Medium-speed — High-speed Sub-active — — — — Sub-active — High-speed Sub-active — — Pre-Transition State LSON DTON Command 0 1 0 1 0 1 0 1 * 0 1 * 0 1 0 1 * * * * 0 0 1 1 * * * * 0 0 1 1 Sleep — Software standby — Watch Watch — Sub-active — — Sub-sleep — Watch Watch High-speed — High-speed/ 0 Medium-speed 0 1 1 1 1 1 1 Sub-active 0 0 0 1 1 1 1 1 Legend: *: Don’t care —: Do not set Rev. 3.00 Jan 11, 2005 page 908 of 1220 REJ09B0186-0300O Section 24 Power-Down Modes 24.1.1 Register Configuration Power-down modes are controlled by the SBYCR, SCKCR, LPWRCR, TCSR (WDT1), and MSTPCR registers. Table 24.3 summarizes these registers. Table 24.3 Power-Down Mode Registers Name Standby control register System clock control register Low-power control register Timer control/status register Module stop control register A to C Abbreviation SBYCR SCKCR LPWRCR TCSR MSTPCRA MSTPCRB MSTPCRC Note: * Lower 16 bits of the address. R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'08 H'00 H'00 H'00 H'3F H'FF H'FF Address* H'FDE4 H'FDE6 H'FDEC H'FFA2 H'FDE8 H'FDE9 H'FDEA Rev. 3.00 Jan 11, 2005 page 909 of 1220 REJ09B0186-0300O Section 24 Power-Down Modes 24.2 24.2.1 Bit Register Descriptions Standby Control Register (SBYCR) : 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 OPE 1 R/W 2 — 0 — 1 — 0 — 0 — 0 — Initial value : R/W : SBYCR is an 8-bit readable/writable register that performs power-down mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Software Standby (SSBY): When making a low power dissipation mode transition by executing the SLEEP instruction, the operating mode is determined in combination with other control bits. Note that the value of the SSBY bit does not change even when shifting between modes using interrupts. Bit 7 SSBY 0 Description Shifts to sleep mode when the SLEEP instruction is executed in high-speed mode or medium-speed mode. Shifts to sub-sleep mode when the SLEEP instruction is executed in sub-active mode. (Initial value) Shifts to software standby mode, sub-active mode, and watch mode when the SLEEP instruction is executed in high-speed mode or medium-speed mode. Shifts to watch mode or high-speed mode when the SLEEP instruction is executed in sub-active mode. 1 Rev. 3.00 Jan 11, 2005 page 910 of 1220 REJ09B0186-0300O Section 24 Power-Down Modes Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the MCU wait time for clock stabilization when shifting to high-speed mode or medium-speed mode by using a specific interrupt or command to cancel software standby mode, watch mode, or sub-active mode. With a crystal oscillator (table 24.5), select a wait time of 8ms (oscillation stabilization time) or more, depending on the operating frequency. With an external clock, there are no specific wait requirements. Bit 6 STS2 0 Bit 5 STS1 0 1 1 0 1 Bit 4 STS0 0 1 0 1 0 1 0 1 Description Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states (Initial value) Bit 3—Output Port Enable (OPE): This bit specifies whether the output of the address bus and bus control signals ( to , , , , , , ) is retained or set to highimpedance state in the software standby mode, watch mode, and when making a direct transition. Bit 3 OPE 0 1 Description In software standby mode, watch mode, and when making a direct transition, address bus and bus control signals are high-impedance. In software standby mode, watch mode, and when making a direct transition, the output state of the address bus and bus control signals is retained. (Initial value) Bits 2 to 0—Reserved: These bits are always read as 0 and cannot be modified. EO SAC RWL RWH DR SA 7SC 0SC Rev. 3.00 Jan 11, 2005 page 911 of 1220 REJ09B0186-0300O Section 24 Power-Down Modes 24.2.2 Bit System Clock Control Register (SCKCR) : 7 PSTOP 0 R/W 6 — 0 — 5 — 0 — 4 — 0 — 3 STCS 0 R/W 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W Initial value : R/W : SCKCR is an 8-bit readable/writable register that performs φ clock output control, selection of operation when the PLL circuit frequency multiplication factor is changed, and medium-speed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—φ Clock Output Disable (PSTOP): In combination with the DDR of the applicable port, this bit controls φ output. See section 24.12, φ Clock Output Disabling Function for details. Description Bit 7 0 1 High-Speed Mode, Medium-Speed Mode, Sleep Mode, Software Standby PSTOP Sub-Active Mode Sub-Sleep Mode Mode, Watch Mode φ output (initial value) Fixed high φ output Fixed high Fixed high Fixed high Hardware Standby Mode High impedance High impedance Bits 6 and 4—Reserved: These bits are always read as 0 and cannot be modified. Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation when the PLL circuit frequency multiplication factor is changed. Bit 3 STCS 0 1 Description Specified multiplication factor is valid after transition to software standby mode, watch mode, or subactive mode (Initial value) Specified multiplication factor is valid immediately after STC bits are rewritten Rev. 3.00 Jan 11, 2005 page 912 of 1220 REJ09B0186-0300O Section 24 Power-Down Modes Bits 2 to 0—System clock select (SCK2 to SCK0): These bits select the bus master clock in high-speed mode, medium-speed mode, and sub-active mode. Set SCK2 to SCK0 all to 0 when shifting to operation in watch mode or sub-active mode. Bit 2 SCK2 0 Bit 1 SCK1 0 1 1 0 1 Bit 0 SCK0 0 1 0 1 0 1 — Description Bus master in high-speed mode Medium-speed clock is φ/2 Medium-speed clock is φ/4 Medium-speed clock is φ/8 Medium-speed clock is φ/16 Medium-speed clock is φ/32 — (Initial value) 24.2.3 Bit Low-Power Control Register (LPWRCR) : 7 DTON 0 R/W 6 LSON 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 — 0 R/W 1 STC1 0 R/W 0 STC0 0 R/W NESEL SUBSTP RFCUT Initial value : R/W : The LPWRCR is an 8-bit read/write register that controls the low power dissipation modes. The LPWRCR is initialized to H'00 at a power-on reset and when in hardware standby mode. It is not initialized at a manual reset or when in software standby mode. The following describes bits 7 to 2. For details of other bits, see section 23.2.2, Low-Power Control Register. Bit 7—Direct Transition ON Flag (DTON): When shifting to low power dissipation mode by executing the SLEEP instruction, this bit specifies whether or not to make a direct transition between high-speed mode or medium-speed mode and the sub-active modes. The selected operating mode after executing the SLEEP instruction is determined by the combination of other control bits. Rev. 3.00 Jan 11, 2005 page 913 of 1220 REJ09B0186-0300O Section 24 Power-Down Modes Bit 7 DTON 0 Description • • 1 • W hen the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode*. W hen the SLEEP instruction is executed in sub-active mode, operation shifts to sub-sleep mode or watch mode. (Initial value) W hen the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts directly to sub-active mode*, or shifts to sleep mode or software standby mode. W hen the SLEEP instruction is executed in sub-active mode, operation shifts directly to high-speed mode, or shifts to sub-sleep mode. • Note: * Always set high-speed mode when shifting to watch mode or sub-active mode. Bit 6—Low-Speed ON Flag (LSON): When shifting to low power dissipation mode by executing the SLEEP instruction, this bit specifies the operating mode, in combination with other control bits. This bit also controls whether to shift to high-speed mode or sub-active mode when watch mode is cancelled. Bit 6 LSON 0 Description • • • 1 • • • W hen the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode*. W hen the SLEEP instruction is executed in sub-active mode, operation shifts to watch mode or shifts directly to high-speed mode. Operation shifts to high-speed mode when watch mode is cancelled. (Initial value) W hen the SLEEP instruction is executed in high-speed mode, operation shifts to watch mode or sub-active mode. W hen the SLEEP instruction is executed in sub-active mode, operation shifts to subsleep mode or watch mode. Operation shifts to sub-active mode when watch mode is cancelled. Note: * Always set high-speed mode when shifting to watch mode or sub-active mode. Rev. 3.00 Jan 11, 2005 page 914 of 1220 REJ09B0186-0300O Section 24 Power-Down Modes Bit 5—Noise Elimination Sampling Frequency Select (NESEL): This bit selects the sampling frequency of the subclock (φSUB) generated by the subclock oscillator is sampled by the clock (φ) generated by the system clock oscillator. Set this bit to 0 when φ = 5MHz or more. Bit 5 NESEL 0 1 Description Sampling using 1/32 × φ Sampling using 1/4 × φ (Initial value) Bit 4—Subclock enable (SUBSTP): This bit enables/disables subclock generation. Bit 4 SUBSTP Description 0 1 Enables subclock generation Disables subclock generation (Initial value) Bit 3—Oscillation Circuit Feedback Resistance Control Bit (RFCUT): This bit turns the internal feedback resistance of the main clock oscillation circuit ON/OFF. Bit 3 RFCUT 0 1 Description When the main clock is oscillating, sets the feedback resistance ON. When the main clock is stopped, sets the feedback resistance OFF. (Initial value) Sets the feedback resistance OFF. Bit 2—Reserved: Should always be written with 0. Rev. 3.00 Jan 11, 2005 page 915 of 1220 REJ09B0186-0300O Section 24 Power-Down Modes 24.2.4 Timer Control/Status Register (TCSR) WDT1 TCSR Bit : 7 OVF Initial value : R/W : 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 PSS 0 R/W 3 RST/NMI 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Note: * Only write 0 to clear the flag. TCSR is an 8-bit read/write register that selects the clock input to WDT1 TCNT and the mode. The following describes bit 4. For details of the other bits in this register, see section 15.2.2, Timer Control/Status Register (TCSR). The TCSR is initialized to H'00 at a reset and when in hardware standby mode. It is not initialized in software standby mode. Bit 4—Prescaler select (PSS): This bit selects the clock source input to WDT1 TCNT. It also controls operation when shifting low power dissipation modes. The operating mode selected after the SLEEP instruction is executed is determined in combination with other control bits. For details, see the description for clock selection in section 15.2.2, Timer Control/Status Register (TCSR), and this section. Bit 4 PSS 0 Description • • 1 • • • TCNT counts the divided clock from the φ -based prescaler (PSM). W hen the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode or software standby mode. (Initial value) TCNT counts the divided clock from the φSUB-based prescaler (PSS). W hen the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, watch mode*, or sub-active mode*. W hen the SLEEP instruction is executed in sub-active mode, operation shifts to subsleep mode, watch mode, or high-speed mode. Note: * Always set high-speed mode when shifting to watch mode or sub-active mode. Rev. 3.00 Jan 11, 2005 page 916 of 1220 REJ09B0186-0300O Section 24 Power-Down Modes 24.2.5 Module Stop Control Register (MSTPCR) MSTPCRA Bit : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W MSTPCRB Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : R/W MSTPCRC Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : R/W : : : MSTPCR, comprising three 8-bit readable/writable registers, performs module stop mode control. MSTPCR is initialized to H'3FFFFF by a reset and in hardware standby mode. It is not initialized in software standby mode. MSTPCRA/MSTPCRB/MSTPCRC Bits 7 to 0—Module Stop (MSTPA7 to MSTPA0, MSTPB7 to MSTPB0, MSTPC7 to MSTPC0): These bits specify module stop mode. See table 24.3 for the method of selecting the on-chip peripheral functions. MSTPCRA/MSTPCRB/ MSTPCRC Bits 7 to 0 MSTPA7 to MSTPA0, MSTPB7 to MSTPB0, MSTPC7 to MSTPC0 0 1 Description Module stop mode is cleared (initial value of MSTPA7 and MSTPA6) Module stop mode is set (initial value of MSTPA5 to 0, MSTPB7 to 0, and MSTPC7 to 0) Rev. 3.00 Jan 11, 2005 page 917 of 1220 REJ09B0186-0300O Section 24 Power-Down Modes 24.3 Medium-Speed Mode In high-speed mode, when the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (the DMAC and DTC) also operate in medium-speed mode. On-chip supporting modules other than the bus masters always operate on the high-speed clock (φ). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and LSON bit in LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit = 1, LPWRCR LSON bit = 0, and TCSR (WDT1) PSS bit = 0, operation shifts to the software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. and pins are set Low and medium-speed mode is cancelled, operation shifts When the to the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer. Figure 24.2 shows the timing for transition to and clearance of medium-speed mode. Rev. 3.00 Jan 11, 2005 page 918 of 1220 REJ09B0186-0300O YBTS When the pin is driven low, a transition is made to hardware standby mode. SERM SER Section 24 Power-Down Modes Medium-speed mode φ, supporting module clock Bus master clock Internal address bus SBYCR SBYCR Internal write signal Figure 24.2 Medium-Speed Mode Transition and Clearance Timing 24.4 24.4.1 Sleep Mode Sleep Mode When the SLEEP instruction is executed when the SBYCR SSBY bit = 0 and the LPWRCR LSON bit = 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of the CPUís internal registers are retained. Other supporting modules do not stop. 24.4.2 Exiting Sleep Mode (1) Exiting Sleep Mode by Interrupts When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. YBTS When the pin level is driven low, a transition is made to hardware standby mode. Rev. 3.00 Jan 11, 2005 page 919 of 1220 REJ09B0186-0300O YBTS (3) Exiting Sleep Mode by SERM SER SERM SER Setting the or duration, driving the processing. pin level Low selects the reset state. After the stipulated reset input and pins High starts the CPU performing reset exception Pin SERM SER (2) Exiting Sleep Mode by or Pins YBTS SERM SER Sleep mode is exited by any interrupt, or signals at the , , or pins. Section 24 Power-Down Modes 24.5 24.5.1 Module Stop Mode Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 24.4 shows MSTP bits and the corresponding on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI, A/D converter and 14-bit PWM are retained. After reset clearance, all modules other than DMAC and DTC are in module stop mode. When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. Rev. 3.00 Jan 11, 2005 page 920 of 1220 REJ09B0186-0300O Section 24 Power-Down Modes Table 24.4 MSTP Bits and Corresponding On-Chip Supporting Modules Register MSTPCRA Bit MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 MSTPCRB MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0* MSTPCRC MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3* MSTPC2* MSTPC1* MSTPC0* Module DMA controller (DMAC) Data transfer controller (DTC) 16-bit timer pulse unit (TPU) 8-bit timer (TMR0, TMR1) Programmable pulse generator (PPG) D/A converter (channels 0, 1) A/D converter 8-bit timer (TMR2, TMR3) Serial communication interface 0 (SCI0) Serial communication interface 1 (SCI1) Serial communication interface 2 (SCI2) I2C bus interface 0 (IIC0) I2C bus interface 1 (IIC1) 14-bit PWM timer (PWM0) 14-bit PWM timer (PWM1) — Serial communication interface 3 (SCI3) Serial communication interface 4 (SCI4) D/A converter (channels 2, 3) PC break controller (PBC) — — — — Note: * Write 1 to bit MSTPB0 and bits MTSPC3 to MSTPC0. Rev. 3.00 Jan 11, 2005 page 921 of 1220 REJ09B0186-0300O Section 24 Power-Down Modes 24.5.2 Usage Notes (1) DMAC and DTC Module Stop Depending on the operating status of the DMAC and DTC, the MSTPA7 and MSTPA6 bits may not be set to 1. Setting of the DMAC or DTC module stop mode should be carried out only when the respective module is not activated. For details, refer to section 8, DMA Controller, and section 9, Data Transfer Controller (DTC). (2) On-Chip Supporting Module Interrupt Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC and DTC activation source. Interrupts should therefore be disabled before entering module stop mode. (3) Writing to MSTPCR MSTPCR should only be written to by the CPU. 24.6 24.6.1 Software Standby Mode Software Standby Mode A transition is made to software standby mode when the SLEEP instruction is executed when the SBYCR SSBY bit = 1 and the LPWRCR LSON bit = 0, and the TCSR (WDT1) PSS bit = 0. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than the SCI, A/D converter, and 14-bit PWM, and I/O ports, are retained. Whether the address bus and bus control signals are placed in the high-impedance state. In this mode the oscillator stops, and therefore power dissipation is significantly reduced. 24.6.2 Exiting Software Standby Mode Rev. 3.00 Jan 11, 2005 page 922 of 1220 REJ09B0186-0300O 7QRI 0QRI Software standby mode is cleared by an external interrupt (NMI pin, or pins pin, pin or pin. means of the to ), or by YBTS SERM SER Section 24 Power-Down Modes (1) Exiting Software Standby Mode with an Interrupt When an NMI or IRQ0 to IRQ7 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are supplied to the entire chip, software standby mode is exited, and interrupt exception handling is started. When exiting software standby mode with an IRQ0 to IRQ7 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ7 is generated. Software standby mode cannot be exited if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. pin or pin is driven low, clock oscillation is started. At the same time as When the clock oscillation starts, clocks are supplied to the entire chip. Note that the pin or pin pin or pin goes high, the must be held low until clock oscillation stabilizes. When the CPU begins reset exception handling. 24.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. (1) Using a Crystal Oscillator Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time). Table 24.5 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. YBTS When the pin is driven low, a transition is made to hardware standby mode. YBTS (3) Exiting Software Standby Mode by Pin Rev. 3.00 Jan 11, 2005 page 923 of 1220 REJ09B0186-0300O SERM SERM SER SER SERM SER (2) Exiting Software Standby Mode by or Pins SERM SER Section 24 Power-Down Modes Table 24.5 Oscillation Stabilization Time Settings Standby STS2 STS1 STS0 Time 0 0 0 1 1 0 1 1 0 0 1 1 0 1 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states 25 20 16 12 10 8 6 4 2 MHz MHz MHz MHz MHz MHz MHz MHz MHz Unit 0.32 0.65 1.3 2.6 5.2 10.4 0.41 0.82 1.6 3.3 6.6 0.51 1.0 2.0 4.1 8.2 0.65 1.3 2.7 5.5 10.9 21.8 — 1.3 0.8 1.6 3.3 6.6 1.0 2.0 4.1 8.2 1.3 2.7 5.5 2.0 4.1 8.2 4.1 8.2 16.4 32.8 65.5 131.2 — 8.0 µs ms 10.9 16.4 21.8 43.6 — 1.7 32.8 65.6 — 4.0 13.1 16.4 26.2 — 1.6 32.8 — 2.0 13.1 16.4 — 0.8 — 1.0 Reserved — 16 states* 0.6 : Recommended time setting Note: * Do not use this setting in the version with built-in flash memory. (2) Using an External Clock The PLL circuit requires a time for stabilization. Insert a wait of 2 ms min. 24.6.4 Software Standby Mode Application Example Figure 24.3 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin. Rev. 3.00 Jan 11, 2005 page 924 of 1220 REJ09B0186-0300O Section 24 Power-Down Modes Oscillator φ NMI NMIEG SSBY NMI exception Software standby mode handling (power-down mode) NMIEG = 1 SSBY = 1 SLEEP instruction Oscillation stabilization time tOSC2 NMI exception handling Figure 24.3 Software Standby Mode Application Example Rev. 3.00 Jan 11, 2005 page 925 of 1220 REJ09B0186-0300O Section 24 Power-Down Modes 24.6.5 Usage Notes (1) I/O Port Status In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus and bus control signal output is also retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. (2) Current Dissipation during Oscillation Stabilization Wait Period Current dissipation increases during the oscillation stabilization wait period. (3) Write Data Buffer Function The write data buffer function and software standby mode cannot be used at the same time. When the write data buffer function is used, the WDBE bit in BCRL should be cleared to 0 to cancel the write data buffer function before entering software standby mode. Also check that external writes have finished, by reading external addresses, etc., before executing a SLEEP instruction to enter software standby mode. See section 7.9, Write Data Buffer Function, for details of the write data buffer function. 24.7 24.7.1 When the Hardware Standby Mode Hardware Standby Mode pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before pin low. driving the Do not change the state of the mode pins (MD2 to MD0) while the H8S/2643 Group is in hardware standby mode. Hardware standby mode is cleared by means of the pin and the pin. When the pin is driven high while the pin is low, the reset state is set and clock oscillation is started. Ensure that the pin is held low until the clock oscillator stabilizes (at least 8 ms—the oscillation stabilization time—when using a crystal oscillator). When the pin is subsequently Rev. 3.00 Jan 11, 2005 page 926 of 1220 REJ09B0186-0300O YBTS SER SER YBTS SER SER YBTS YBTS Section 24 Power-Down Modes driven high, a transition is made to the program execution state via the reset exception handling state. 24.7.2 Hardware Standby Mode Timing Figure 24.4 shows an example of hardware standby mode timing. pin is driven low after the pin has been driven low, a transition is made to When the hardware standby mode. Hardware standby mode is cleared by driving the pin high, pin from low to high. waiting for the oscillation stabilization time, then changing the Oscillator RES STBY Oscillation stabilization time Figure 24.4 Hardware Standby Mode Timing 24.8 24.8.1 Watch Mode Watch Mode CPU operation makes a transition to watch mode when the SLEEP instruction is executed in highspeed mode or sub-active mode with SBYCR SSBY = 1, LPWRCR DTON = 0, and TCSR (WDT1) PSS = 1. In watch mode, the CPU is stopped and supporting modules other than WDT1 are also stopped. The contents of the CPU’s internal registers, the data in internal RAM, and the statuses of the internal supporting modules (excluding the SCI, ADC, and 14-bit PWM) and I/O ports are retained. Rev. 3.00 Jan 11, 2005 page 927 of 1220 REJ09B0186-0300O YBTS SER SER YBTS Reset exception handling Section 24 Power-Down Modes 24.8.2 Exiting Watch Mode (1) Exiting Watch Mode by Interrupts When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or medium-speed mode when the LPWRCR LSON bit = 0 or to sub-active mode when the LSON bit = 1. When a transition is made to high-speed mode, a stable clock is supplied to all LSI circuits and interrupt exception processing starts after the time set in SBYCR STS2 to STS0 has elapsed. In the case of IRQ0 to IRQ7 interrupts, no transition is made from watch mode if the corresponding enable bit has been cleared to 0, and, in the case of interrupts from the internal supporting modules, the interrupt enable register has been set to disable the reception of that interrupt, or is masked by the CPU. See section 24.6.3, Setting Oscillation Stabilization Time After Clearing Software Standby Mode for how to set the oscillation stabilization time when making a transition from watch mode to high-speed mode. or pins, see (2), Exiting Software Standby Mode by For exiting watch mode by the or pins in section 24.6.2, Exiting Software Standby Mode. 24.8.3 Notes (1) I/O Port Status The status of the I/O ports is retained in watch mode. Also, when the OPE bit is set to 1, the address bus and bus control signals continue to be output. Therefore, when a High level is output, the current consumption is not diminished by the amount of current to support the High level output. (2) Current Consumption when Waiting for Oscillation Stabilization The current consumption increases during stabilization of oscillation. Rev. 3.00 Jan 11, 2005 page 928 of 1220 REJ09B0186-0300O YBTS When the pin level is driven low, a transition is made to hardware standby mode. YBTS (3) Exiting Watch Mode by SERM SER Pin SERM SER (2) Exiting Watch Mode by or Pins 7QRI 0QRI Watch mode is exited by any interrupt (WOVI1 interrupt, NMI pin, or , , or pins. at the to ), or signals YBTS SERM SER SERM SER Section 24 Power-Down Modes 24.9 24.9.1 Sub-Sleep Mode Sub-Sleep Mode When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1, and TCSR (WDT1) PSS bit = 1, CPU operation shifts to sub-sleep mode. In sub-sleep mode, the CPU is stopped. Supporting modules other than TMR0 to TMR3, WDT0, and WDT1 are also stopped. The contents of the CPUís internal registers, the data in internal RAM, and the statuses of the internal supporting modules (excluding the SCI, ADC, and 14-bit PWM) and I/O ports are retained. 24.9.2 Exiting Sub-Sleep Mode Sub-sleep mode is exited by an interrupt (interrupts from internal supporting modules, NMI pin, or to ), or signals at the , , or pins. (1) Exiting Sub-Sleep Mode by Interrupts When an interrupt occurs, sub-sleep mode is exited and interrupt exception processing starts. In the case of IRQ0 to IRQ7 interrupts, sub-sleep mode is not cancelled if the corresponding enable bit has been cleared to 0, and, in the case of interrupts from the internal supporting modules, the interrupt enable register has been set to disable the reception of that interrupt, or is masked by the CPU. For exiting sub-sleep mode by the or pins, see (2), Exiting Software Standby Mode by or pins in section 24.6.2, Exiting Software Standby Mode. YBTS When the pin level is driven low, a transition is made to hardware standby mode. YBTS (3) Exiting Sub-Sleep Mode by Pin SERM SERM SER SER (2) Exiting Sub-Sleep Mode by or YBTS Pins SERM SER SERM 7QRI 0QRI SER Rev. 3.00 Jan 11, 2005 page 929 of 1220 REJ09B0186-0300O Section 24 Power-Down Modes 24.10 Sub-Active Mode 24.10.1 Sub-Active Mode When the SLEEP instruction is executed in high-speed mode with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 1, LSON bit = 1, and TCSR (WDT1) PSS bit = 1, CPU operation shifts to sub-active mode. When an interrupt occurs in watch mode, and if the LSON bit of LPWRCR is 1, a transition is made to sub-active mode. And if an interrupt occurs in sub-sleep mode, a transition is made to sub-active mode. In sub-active mode, the CPU operates at low speed on the subclock, and the program is executed step by step. Supporting modules other than TMR0 to TMR3, WDT0, and WDT1 are also stopped. When operating the CPU in sub-active mode, the SCKCR SCK2 to SCK0 bits must be set to 0. 24.10.2 Exiting Sub-Active Mode (1) Exiting Sub-Active Mode by SLEEP Instruction When the SLEEP instruction is executed with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 0, and TCSR (WDT1) PSS bit = 1, the CPU exits sub-active mode and a transition is made to watch mode. When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1, and TCSR (WDT1) PSS bit = 1, a transition is made to sub-sleep mode. Finally, when the SLEEP instruction is executed with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 1, LSON bit = 0, and TCSR (WDT1) PSS bit = 1, a direct transition is made to high-speed mode (SCK0 to SCK2 all 0). See section 24.11, Direct Transitions for details of direct transitions. For exiting sub-active mode by the or pins, see (2), Exiting Software Standby Mode or pins in section 24.6.2, Exiting Software Standby Mode. by Rev. 3.00 Jan 11, 2005 page 930 of 1220 REJ09B0186-0300O YBTS When the pin level is driven Low, a transition is made to hardware standby mode. YBTS (3) Exiting Sub-Active Mode by SERM SER Pin SERM SER (2) Exiting Sub-Active Mode by or Pins YBTS SERM SER Sub-active mode is exited by the SLEEP instruction or the , , or pins. SERM SER Section 24 Power-Down Modes 24.11 Direct Transitions 24.11.1 Overview of Direct Transitions There are three modes, high-speed, medium-speed, and sub-active, in which the CPU executes programs. When a direct transition is made, there is no interruption of program execution when shifting between high-speed and sub-active modes. Direct transitions are enabled by setting the LPWRCR DTON bit to 1, then executing the SLEEP instruction. After a transition, direct transition interrupt exception processing starts. (1) Direct Transitions from High-Speed Mode to Sub-Active Mode Execute the SLEEP instruction in high-speed mode when the SBYCR SSBY bit = 1, LPWRCR LSON bit = 1, and DTON bit = 1, and TSCR (WDT1) PSS bit = 1 to make a transition to subactive mode. (2) Direct Transitions from Sub-Active Mode to High-Speed Mode Execute the SLEEP instruction in sub-active mode when the SBYCR SSBY bit = 1, LPWRCR LSON bit = 0, and DTON bit = 1, and TSCR (WDT1) PSS bit = 1 to make a direct transition to high-speed mode after the time set in SBYCR STS2 to STS0 has elapsed. 24.12 φ Clock Output Disabling Function Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle, and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set. Table 24.6 shows the state of the φ pin in each processing state. Using the on-chip PLL circuit to lower the oscillator frequency or prohibiting external φ clock output also have the effect of reducing unwanted electromagnetic interference*. Therefore, consideration should be given to these options when deciding on system board settings. Note: * Electromagnetic interference: EMI (Electro Magnetic Interference) Rev. 3.00 Jan 11, 2005 page 931 of 1220 REJ09B0186-0300O Section 24 Power-Down Modes Table 24.6 φ Pin State in Each Processing State DDR PSTOP Hardware standby mode Software standby mode, watch mode, and direct transition Sleep mode and subsleep mode High-speed mode, medium-speed mode, and subactive mode 0 — High impedance High impedance High impedance High impedance 1 0 High impedance Fixed high φ output φ output 1 1 High impedance Fixed high Fixed high Fixed high Rev. 3.00 Jan 11, 2005 page 932 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics Section 25 Electrical Characteristics 25.1 Absolute Maximum Ratings Table 25.1 lists the absolute maximum ratings. Table 25.1 Absolute Maximum Ratings Item Power supply voltage Symbol VCC PLLVCC PVCC Input voltage (XTAL, EXTAL, OSC1, OSC2) Input voltage (ports 4 and 9) Input voltage (except XTAL, EXTAL, OSC1, OSC2, ports 4 and 9) Reference voltage Analog power supply voltage Analog input voltage Operating temperature Storage temperature Vin Vin Vin –0.3 to +7.0 –0.3 to VCC +0.3 –0.3 to AVCC +0.3 –0.3 to PVCC +0.3 V V V V Value –0.3 to +4.3 Unit V Vref AVCC VAN Topr Tstg –0.3 to AVCC +0.3 –0.3 to +7.0 –0.3 to AVCC +0.3 Regular specifications: –20 to +75 Wide-range specifications: –40 to +85 –55 to +125 V V V °C °C °C Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded. Rev. 3.00 Jan 11, 2005 page 933 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics 25.2 DC Characteristics Table 25.2 lists the DC characteristics. Table 25.3 lists the permissible output currents. Table 25.2 DC Characteristics (1) Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = PLLVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)*1 Item Port 2 , , NMI, FWE*5, MD2 to MD0 EXTAL, OSC1 Ports 1, 3, 5, 7, 8, A to G Ports 4, 9 YBTS SER YBTS SER 0QRI 7QRI Symbol to VT VT – + + – Min. 1.0 — 0.4 PVCC – 0.7 Typ. — — — — Max. — — Unit V V Test Conditions Schmitt trigger input voltage Input high voltage PVCC × 0.7 V PVCC + 0.3 V VT – VT VIH VCC × 0.8 — 2.2 AVCC × 0.7 VIL –0.3 — — — VCC + 0.3 V PVCC + 0.3 V AVCC + 0.3 V 0.5 V Input low voltage , , 5 NMI, FWE* , MD2 to MD0 EXTAL, OSC1 Ports 1, 3, 4, 5, 7, 8, 9, A to G –0.3 –0.3 — — VCC × 0.2 0.8 V V Output high voltage All output pins VOH except P34 and P35 P34, P35 All output pins except P34 and P35 PVCC –0.5 — — V IOH = –200 µA PVCC –2.5 3.5 IOH = –100 µA IOH = –1 mA Output low voltage All output pins VOL — — 0.4 V IOL = 1.6 mA Rev. 3.00 Jan 11, 2005 page 934 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics Test Conditions Vin = 0.5 to PVCC – 0.5 V Vin = 0.5 to AVCC – 0.5 V Vin = 0.5 to PVCC – 0.5 V Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25°C Item SER SER Symbol , FWE*5 | Iin | , NMI, MD2 to MD0 YBTS Min. — — — — Typ. — — — — Max. 1.0 1.0 1.0 1.0 Unit µA µA µA µA Input leakage current Ports 4, 9 Three-state leakage current (off state) Ports 1, 2, 3, ITSI 5, 7, 8, A to G MOS input Ports A to E pull-up current Input capacitance NMI All input pins except and NMI Current 2 dissipation* Normal operation Sleep mode All modules stopped SER –IP Cin 50 — — — — — — — 300 30 30 15 µA pF pF pF ICC*4 — — — 85 mA 72 VCC = 3.3 V VCC = 3.6 V 58 75 mA VCC = 3.3 V VCC = 3.6 V 50 — mA f = 25 MHz f = 25 MHz f = 25 MHz, VCC = 3.3 V (reference values) f = 25 MHz, VCC = 3.3 V (reference values) Using 32.768 kHz crystal resonator Using 32.768 kHz crystal resonator Using 32.768 kHz crystal resonator Ta ≤ 50°C 50°C < Ta Mediumspeed mode (φ/32) Subactive mode Subsleep mode Watch mode — 40 — mA — 200 120 VCC = 3.0 V Ta = 25°C 70 150 VCC = 3.0 V Ta = 25°C 50 20 VCC = 3.0 V Ta = 25°C 1.0 — 5.0 20 µA — µA — µA Standby mode — — µA Rev. 3.00 Jan 11, 2005 page 935 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics Item Port power supply 2 current* Operating Subclock operation Standby Watch mode Analog During A/D power supply and D/A current conversion Idle Reference During A/D power supply and D/A current conversion Idle RAM standby voltage*3 VRAM AlCC AlCC Symbol Min. PICC — — — — — Typ. Max. Unit mA µA Ta ≤ 50°C 50°C < Ta mA AVCC = 5.0 V Test Conditions 25 17 PVCC = 5.0 V — 0.5 — 0.6 50 5.0 20 2.0 — — 0.01 Ta = 25°C 4.0 5.0 5.0 µA mA AVref = 5.0 V — 2.0 0.01 Ta = 25°C — 5.0 — µA V Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pins open. Apply a voltage between 4.5 V and 5.5 V to the AVCC and Vref pins by connecting them to PVCC, for instance. Set Vref ≤ AVCC. 2. Current dissipation values are for VIH = VCC (EXTAL, OSC1), AVCC (ports 4 and 9), or PVCC (other), and VIL = 0 V, with all output pins unloaded and the on-chip MOS pull-up transistors in the off state. 3. The values are for VRAM ≤ VCC < 3.0 V, VIH (min.) = VCC – 0.1 V, and VIL (max.) = 0.1 V. 4. ICC depends on VCC and f as follows: ICC (max.) = 1.0 (mA) + 0.93 (mA/(MHz × V)) × VCC × f (normal operation) ICC (max.) = 1.0 (mA) + 0.77 (mA/(MHz × V)) × VCC × f (sleep mode) 5. FWE is used only in the flash memory version. Rev. 3.00 Jan 11, 2005 page 936 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics Table 25.2 DC Characteristics (2) Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V*7, Vref = 3.6 V to AVCC*8, VSS = AVSS = PLLVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)*1 Item Port 2 , , FWE*6, NMI, MD2 to MD0 EXTAL, OSC1 Ports 1, 3, 5, 7, 8, A to G Ports 4, 9 YBTS SER YBTS SER 0QRI 7QRI YBTS SER Symbol to VT VT – + + – Min. — Typ. — Max. — — Unit V V Test Conditions Schmitt trigger input voltage Input high voltage PVCC × 0.2 — PVCC × 0.05 — PVCC × 0.9 — PVCC × 0.7 V PVCC + 0.3 V VT – VT VIH VCC × 0.8 — VCC + 0.3 V PVCC × 0.8 — AVCC × 0.8 — VIL –0.3 — PVCC + 0.3 V AVCC + 0.3 V PVCC × 0.1 V Input low voltage , , NMI, FWE*6, MD2 to MD0 EXTAL, OSC1 Ports 1, 3, 5, 7, 8, A to G Ports 4 and 9 –0.3 –0.3 –0.3 PVCC –0.5 — — — — VCC × 0.2 V PVCC × 0.2 V AVCC × 0.2 V — V IOH = –200 µA Output high voltage All output pins VOH except P34 and P35 P34, P35 All output pins except P34 and P35 PVCC –2.5 PVCC –1.0 — — — IOH = –100 µA*2 IOH = –1mA Output low voltage Input leakage current All output pins VOL , FWE*6 | Iin | — — — — — — — — 0.4 1.0 1.0 1.0 V µA µA µA IOL = 1.6 mA Vin = 0.5 to PVCC – 0.5 V Vin = 0.5 to AVCC – 0.5 V , NMI, MD2 to MD0 Ports 4, 9 Rev. 3.00 Jan 11, 2005 page 937 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics Item Three-state leakage current (off state) Symbol Min. Ports 1, 2, 3, ITSI 5, 7, 8, A to G — Typ. — Max. 1.0 Unit µA Test Conditions Vin = 0.5 to PVCC – 0.5 V MOS input Ports A to E pull-up current SER –IP Cin 25 — — — — — — — 300 30 30 15 µA pF pF pF Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25°C Input capacitance NMI All input pins except and NMI Current dissipation*3 Normal operation Sleep mode All modules stopped Mediumspeed mode (φ/32) Subactive mode Subsleep mode Watch mode Standby mode Rev. 3.00 Jan 11, 2005 page 938 of 1220 REJ09B0186-0300O SER ICC*5 — — — 40 60 mA VCC = 3.3 V VCC = 3.6 V 45 mA 35 VCC = 3.3 V VCC = 3.6 V 30 — mA f = 16 MHz f = 16 MHz f = 16 MHz, VCC = 3.3 V (reference values) f = 16 MHz, VCC = 3.3 V (reference values) Using 32.768 kHz crystal resonator Using 32.768 kHz crystal resonator Using 32.768 kHz crystal resonator Ta ≤ 50°C 50°C < Ta — 25 — mA — 120 200 VCC = 3.0 V T a = 25 °C 70 150 VCC = 3.0 V T a = 25 °C 20 50 VCC = 3.0 V Ta = 25 °C 1.0 — 5.0 20 µA — µA — µA — — µA Section 25 Electrical Characteristics Item Port power supply 3 current* Operating Subclock operation Standby Watch mode Analog During A/D AlCC power supply and D/A current conversions Idle Reference current During A/D AlCC and D/A conversions Idle RAM standby voltage*4 VRAM Symbol Min. PICC — — — — — Typ. Max. Unit mA µA Ta ≤ 50°C 50°C < Ta mA AVCC = 5.0 V Test Conditions 16 10 PVCC = 5.0 V — 0.5 — 0.6 50 5.0 20 2.0 — — 0.01 Ta = 25°C 4.0 5.0 5.0 µA mA AVref = 5.0 V — 2.0 0.01 Ta = 25°C — 5.0 — µA V Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage between 3.3 V to 5.5 V to the AVCC and Vref pins by connecting them to PVCC, for instance. Set Vref ≤ AVCC. 2. When using P34 and P35 as output pins, set PVCC = 4.5 V to 5.5 V. 3. Current dissipation values are for VIH = VCC (EXTAL, OSC1), AVCC (ports 4 and 9), or PVCC (other), and VIL = 0 V, with all output pins unloaded and the on-chip MOS pull-up transistors in the off state. 4. The values are for VRAM ≤ VCC < 3.0 V, VIH (min.) = VCC – 0.1 V, and VIL (max.) = 0.1 V. 5. ICC depends on VCC and f as follows: ICC (max.) = 1.0 (mA) + 0.93 (mA/(MHz × V)) × VCC × f (normal operation) ICC (max.) = 1.0 (mA) + 0.77 (mA/(MHz × V)) × VCC × f (sleep mode) 6. FWE is used only in the flash memory version. 7. AVCC = 3.3 V to 5.5 V if the A/D and D/A converters are not used (used as I/O ports). 8. Vref = 3.3 V to AVCC if the A/D and D/A converters are not used (used as I/O ports). Rev. 3.00 Jan 11, 2005 page 939 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics Table 25.3 Permissible Output Currents Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V*1, Vref = 3.6 V to AVCC*2, VSS = AVSS = PLLVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)*1 Item Permissible output low current (per pin) Permissible output low current (total) All output pins Total of all output pins Symbol Min. PVCC = 3.0 to 5.5 V IOL PVCC = 3.0 to 5.5 V Σ IOL PVCC = 3.0 to 5.5 V –IOH PVCC = 3.0 to 5.5 V Σ –IOH — — — — Typ. — — — — Max. 10 120 2.0 40 Unit mA mA mA mA Permissible output All output high current (per pin) pins Permissible output high current (total) Total of all output pins Notes: To protect chip reliability, do not exceed the output current values in table 25.3. 1. AVCC = 3.3 V to 5.5 V if the A/D and D/A converters are not used (used as I/O ports). 2. Vref = 3.3 V to AVCC if the A/D and D/A converters are not used (used as I/O ports). Rev. 3.00 Jan 11, 2005 page 940 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics Table 25.4 Bus Drive Characteristics Conditions : VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.3 V to 5.5 V, Vref = 3.3 V to AVCC, VSS = AVSS = PLLVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Applicable Pins: SCL1 and 0, SDA1 and 0 Item Schmitt trigger input voltage Symbol VT VT + + - Min. PVCC × 0.3 — 0.4 0.2 PVCC × 0.7 - 0.5 — — — Typ. Max. — — — — — — — — — — — — PVCC × 0.7 — — PVCC + 0.5 PVCC × 0.3 0.7 0.4 0.4 20 1.0 Unit Test Conditions V PVCC = 4.5 V to 5.5 V PVCC = 3.0 V to 4.5 V V V IOL = 8 mA, PVCC = 4.5 V to 5.5 V IOL = 3 mA, PVCC = 4.5 V to 5.5 V IOL = 1.6 mA, PVCC = 3.0 V to 5.5 V pF µA Vin = 0 V, f = 1 MHz, Ta = 25°C Vin = 0.5 to VCC - 0.5 V VT - VT Input high voltage VIH Input low voltage VIL Output low voltage VOL Input capacitance Cin Three-state leakage current (off state) ITSI — — SCL, SDA, output tOf fall time 20 + 0.1 Cb — 250 ns Rev. 3.00 Jan 11, 2005 page 941 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics 25.3 AC Characteristics Figure 25.1 shows the test conditions for the AC characteristics. 5V RL LSI output pin C RH C = 50 pF: Ports 10 to 13, 70 to 73, A to G (In case of expansion bus control signal output pin setting) C = 30 pF: All ports RL = 2.4 kΩ RH = 12 kΩ Input/output timing measurement levels · Low level : 0.8 V · High level : 2.0 V Figure 25.1 Output Load Circuit Rev. 3.00 Jan 11, 2005 page 942 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics 25.3.1 Clock Timing Table 25.5 lists the clock timing Table 25.5 Clock Timing Condition A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V*1, Vref = 3.6 V to AVCC*2, VSS = AVSS = PLLVSS = 0 V, φ = 32.768 kHz, 2 to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = PLLVSS = 0 V, φ = 32.768 kHz, 2 to 25 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A 16MHz Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Clock oscillator settling time at reset (crystal) Clock oscillator settling time in software standby (crystal) External clock output stabilization delay time 32 kHz clock oscillation settling time Sub clock oscillator frequency Sub clock (φSUB) cycle time Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 Min. 62.5 18 18 — — 10 8 Max. 500 — — 12 12 — — Condition B 25MHz Min. 40 15 15 — — 10 5 Max. 500 — — 5 5 — — Unit ns ns ns ns ns ms ms Figure 25.3 Figure 24.3 Test Conditions Figure 25.2 tDEXT tOSC3 fSUB tSUB 2 — 32.768 30.5 — 2 2 — 32.768 30.5 — 2 ms s kHz µs Figure 25.3 Notes: 1. AVCC = 3.3 V to 5.5 V if the A/D and D/A converters are not used (used as I/O ports). 2. Vref = 3.3 V to AVCC if the A/D and D/A converters are not used (used as I/O ports). Rev. 3.00 Jan 11, 2005 page 943 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics tcyc tCH φ tCL tCr tCf Figure 25.2 System Clock Timing EXTAL tDEXT VCC tDEXT STBY tOSC1 RES tOSC1 φ Figure 25.3 Oscillator Settling Timing Rev. 3.00 Jan 11, 2005 page 944 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics 25.3.2 Control Signal Timing Table 25.6 lists the control signal timing. Table 25.6 Control Signal Timing Condition A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V*1, Vref = 3.6 V to AVCC*2, VSS = AVSS = PLLVSS = 0 V, φ = 32.768 kHz, 2 to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = PLLVSS = 0 V, φ = 32.768 kHz, 2 to 25 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Item setup time pulse width setup time pulse width SER Condition B Min. 200 20 250 20 150 10 200 150 10 200 Max. — — — — — — — — — — ns ns ns ns Unit ns tcyc ns tcyc ns Figure 25.5 Test Conditions Figure 25.4 Symbol tRESS tRESW tMRESS tMRESW tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW Min. 200 20 250 20 250 10 200 250 10 200 Max. — — — — — — — — — — SERM SERM QRI QRI QRI SER NMI setup time NMI hold time NMI pulse width (exiting software standby mode) setup time hold time pulse width (exiting software standby mode) Notes: 1. AVCC = 3.3 V to 5.5 V if the A/D and D/A converters are not used (used as I/O ports). 2. Vref = 3.3 V to AVCC if the A/D and D/A converters are not used (used as I/O ports). Rev. 3.00 Jan 11, 2005 page 945 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics φ tRESS RES tRESW tRESS tMRESS tMRESS MRES tMRESW Figure 25.4 Reset Input Timing φ tNMIS NMI tNMIW tNMIH IRQ tIRQW tIRQS IRQ Edge input tIRQS IRQ Level input tIRQH Figure 25.5 Interrupt Input Timing Rev. 3.00 Jan 11, 2005 page 946 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics 25.3.3 Bus Timing Table 25.7 lists the bus timing. Table 25.7 Bus Timing Condition A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V*1, Vref = 3.6 V to AVCC*2, VSS = AVSS = PLLVSS = 0 V, φ = 2 to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC*2, VSS = AVSS = PLLVSS = 0 V, φ = 2 to 25 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Item Address delay time Address setup time Address hold time delay time 1 delay time 2 delay time delay time 1 SC Condition B Min. — Max. 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol tAD tAS tAH tCSD1 tCSD2 tASD tRSD1 tRSD2 tRDS tRDH tACC1 tACC2 tACC3 tACC4 Min. — Max. 30 Test Conditions Figure 25.6 to Figure 25.11 — 0.5 × tcyc – 30 — 0.5 × tcyc – 20 — 30 — — — — 30 0 — — — — 30 30 30 30 — — 1.0 × tcyc – 35 1.5 × tcyc – 35 2.0 × tcyc – 35 2.5 × tcyc – 35 — 0.5 × tcyc – 15 0.5 × tcyc – 8 — — — — — 15 0 — — — — — 20 18 18 18 18 — — 1.0 × tcyc – 25 1.5 × tcyc – 25 2.0 × tcyc – 25 2.5 × tcyc – 25 DR DR SC SA delay time 2 Read data setup time Read data hold time Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Rev. 3.00 Jan 11, 2005 page 947 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics Condition A Item Read data access time 5 delay time 1 delay time 2 pulse width 1 pulse width 2 RW Condition B Min. — — — Max. Unit ns 3.0 × tcyc – 25 18 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol tACC5 tWRD1 tWRD2 tWSW1 tWSW2 Min. — — — 1.0 × tcyc – 30 1.5 × tcyc – 30 — 0.5 × tcyc – 27 0.5 × tcyc – 20 0.5 × tcyc – 15 0.5 × tcyc – 15 1.5 × tcyc – 30 1.0 × tcyc – 20 0.5 × tcyc – 20 — — — — 0.5 × tcyc – 25 40 10 60 — — — Max. 3.0 × tcyc – 35 30 30 — — 30 — — — — — — — 30 30 30 30 — — — — 30 60 40 Test Conditions Figure 25.6 to Figure 25.11 OQERB QERB KCAB TIAW TIAW SAR SAC SAC SAC SAC SAC RW RW RW RW RW EO EO 1.0 × — tcyc – 15 1.5 × — tcyc – 15 — 22 0.5 × — tcyc – 15 0.5 × tcyc – 8 — Write data delay time tWDD Write data setup time tWDS Write data hold time setup time hold time precharge time tWDH tWCS tWCH tPCH 0.5 × — tcyc – 10 0.5 × — tcyc – 10 1.5 × — tcyc – 15 1.0 × tcyc – 8 0.5 × tcyc – 8 — — — — 0.5 × tcyc – 8 25 5 30 — — — — — 20 18 18 18 — — — — 15 40 25 Figure 25.11 to Figure 25.13 precharge time 1 tCP1 precharge time 2 tCP2 delay time 1 delay time 2 tCASD1 tCASD2 tOED1 tOED2 tCSR tWTS tWTH tBRQS tBACD tBZD tBRQOD delay time 1 delay time 2 setup time setup time hold time setup time delay time delay time Figure 25.8 Figure 25.14 Bus-floating time Figure 25.15 Notes: 1. AVCC = 3.3 V to 5.5 V if the A/D and D/A converters are not used (used as I/O ports). 2. Vref = 3.3 V to AVCC if the A/D and D/A converters are not used (used as I/O ports). Rev. 3.00 Jan 11, 2005 page 948 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics T1 φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS tAH T2 tASD AS tASD tRSD1 RD (read) tACC2 tRSD2 tAS tACC3 tRDS tRDH D15 to D0 (read) tWRD2 WR (write) tAS tWDD D15 to D0 (write) tWSW1 tWRD2 tAH tWDH Figure 25.6 Basic Bus Timing (Two-State Access) Rev. 3.00 Jan 11, 2005 page 949 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics T1 φ T2 T3 tAD A23 to A0 tCSD1 CS7 to CS0 tASD AS tASD tAS tAH tRSD1 RD (read) tACC4 tRSD2 tAS tACC5 tRDS tRDH D15 to D0 (read) tWRD1 WR (write) tWDD tWDS D15 to D0 (write) tWSW2 tWRD2 tAH tWDH Figure 25.7 Basic Bus Timing (Three-State Access) Rev. 3.00 Jan 11, 2005 page 950 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics T1 φ T2 TW T3 A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) WR (write) D15 to D0 (write) tWTS tWTH WAIT tWTS tWTH Figure 25.8 Basic Bus Timing (Three-State Access with One Wait State) Rev. 3.00 Jan 11, 2005 page 951 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics T1 φ T2 or T3 T1 T2 tAD A23 to A0 tAS CS7 to CS0 tASD AS tASD tAH tRSD2 RD (read) tACC3 D15 to D0 (read) tRDS tRDH Figure 25.9 Burst ROM Access Timing (Two-State Access) Rev. 3.00 Jan 11, 2005 page 952 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics T1 φ T2 or T3 T1 tAD A23 to A0 CS7 to CS0 AS tRSD2 RD (read) tACC1 D15 to D0 (read) tRDS tRDH Figure 25.10 Burst ROM Access Timing (One-State Access) Rev. 3.00 Jan 11, 2005 page 953 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics Tp Tr TC1 TC2 φ tAD A23 to A0 tPCH CS5 to CS2 (RAS) tCSD2 CAL, LCAS (RCTS=0) tCASD2 CAL to LCAS (When RCTS is set to 1) (read) OE (When OES is set to 1) (read) tACC3 D15 to D0 (read) tWRD1 HWR, LWR (write) tWDD D15 to D0 (write) tWRD1 tRDS tRDH tACC2 tCASD1 tCP2 tCASD1 tACC1 tCASD1 tCP1 tAS tAH tACC4 tCSD tAD tOED2 tACC2 tOED1 tWCS tWDS tWCH tWDH Figure 25.11 DRAM Access Timing Rev. 3.00 Jan 11, 2005 page 954 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics TRp TRr TRC1 TRC2 φ tCSD2 tCSD1 CS5 to CS2 (RAS) tCASD1 tCSR tCASD1 CAS, LCAS Figure 25.12 DRAM CBR Refresh Timing TRp TRr TRC TRC φ tCSD2 CS5 to CS2 (RAS) tCASD1 CAS, LCAS tCSD2 tCSR tCASD1 Figure 25.13 DRAM Self-Refresh Timing Rev. 3.00 Jan 11, 2005 page 955 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics φ tBRQS BREQ tBRQS tBACD BACK tBZD A23 to A0 CS7 to CS0, AS, RD, HWR, LWR tBACD tBZD Figure 25.14 External Bus Release Timing φ tBRQOD BREQO tBRQOD Figure 25.15 External Bus Request Output Timing Rev. 3.00 Jan 11, 2005 page 956 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics 25.3.4 DMAC Timing Table 25.8 shows the DMAC timing. Table 25.8 DMAC Timing Condition A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V*1, Vref = 3.6 V to AVCC*2, VSS = AVSS = PLLVSS = 0 V, φ = 2 to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = PLLVSS = 0 V, φ = 2 to 25 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Item setup time hold time delay time delay time 1 delay time 2 QERD Condition B Min. 25 10 — — — Max. — — 20 18 18 ns Figure 25.18 Figure 25.16 Figure 25.17 Unit ns Test Conditions Figure 25.19 Symbol tDRQS tDRQH tTED tDACD1 tDACD2 Min. 40 10 — — — Max. — — 30 30 30 QERD KCAD KCAD DNET Notes: 1. AVCC = 3.3 V to 5.5 V if the A/D and D/A converters are not used (used as I/O ports). 2. Vref = 3.3 V to AVCC if the A/D and D/A converters are not used (used as I/O ports). Rev. 3.00 Jan 11, 2005 page 957 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics T1 T2 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR to LWR D15 to D0 (write) tDACD1 DACK0, DACK1 tDACD2 Figure 25.16 DMAC Single Address Transfer Timing/Two-State Access Rev. 3.00 Jan 11, 2005 page 958 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics T1 T2 T2 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR to LWR D15 to D0 (write) tDACD1 DACK0, DACK1 tDACD2 Figure 25.17 DMAC Single Address Transfer Timing/Three-State Access T1 T2 or T3 φ tTED TEND0, TEND1 tTED Figure 25.18 DMAC TEND Output Timing Rev. 3.00 Jan 11, 2005 page 959 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics φ tDRQS tDRQH DREQ0, DREQ1 Figure 25.19 DMAC DREQ Input Timing Rev. 3.00 Jan 11, 2005 page 960 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics 25.3.5 Timing of On-Chip Supporting Modules Table 25.9 lists the timing of on-chip supporting modules. Table 25.9 Timing of On-Chip Supporting Modules Condition A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V*2, Vref = 3.6 V to AVCC*3, VSS = AVSS = PLLVSS = 0 V, φ = 32.768 kHz*1, 2 to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (widerange specifications) Condition B: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = PLLVSS = 0 V, φ = 32.768 kHz*1, 2 to 25 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Item I/O port Output data delay time Input data setup time Input data hold time PPG TPU Symbol tPWD tPRS tPRH Min. — 40 40 — — 40 40 1.5 2.5 Max. 60 — — 60 60 — — — — Condition B Min. — 25 25 — — 25 25 1.5 2.5 Max. 40 — — 40 40 — — — — ns tcyc Figure 25.23 ns ns Figure 25.21 Figure 25.22 Unit ns Test Conditions Figure 25.20 Pulse output delay tPOD time Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges tTOCD tTICS tTCKS tTCKWH tTCKWL Rev. 3.00 Jan 11, 2005 page 961 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics Condition A Item TMR Symbol Timer output delay tTMOD time Timer reset input setup time Timer clock input setup time Timer clock pulse width WDT0 WDT1 PWM SCI Single edge Both edges tTMRS tTMCS tTMCWH tTMCWL tWOVD tBUZD Min. — 40 40 1.5 2.5 — — — 4 6 tSCKW tSCKr tSCKf tTXD 0.4 — — — 60 60 60 Max. 60 — — — — 60 60 60 — — 0.6 1.5 1.5 60 — — — Condition B Min. — 25 25 1.5 2.5 — — — 4 6 0.4 — — — 40 40 40 Max. 40 — — — — 40 40 40 — — 0.6 1.5 1.5 40 — — — ns Figure 25.32 ns Figure 25.31 tScyc tcyc ns ns ns tcyc Figure 25.27 Figure 25.28 Figure 25.29 Figure 25.30 Unit ns ns ns tcyc Test Conditions Figure 25.24 Figure 25.26 Figure 25.25 Overflow output delay time Buzz output delay time Pulse output delay tPWOD time Input clock cycle Asynchro- tScyc nous Synchronous Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup tRXS time (synchronous) Receive data hold tRXH time (synchronous) A/D Trigger input setup tTRGS converter time Notes: 1. Only available I/O port, TMR, WDT0, and WDT1. 2. AVCC = 3.3 V to 5.5 V if the A/D and D/A converters are not used (used as I/O ports). 3. Vref = 3.3 V to AVCC if the A/D and D/A converters are not used (used as I/O ports). Rev. 3.00 Jan 11, 2005 page 962 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics T1 φ T2 tPRS Ports 1, 3, 4, 7, 9 A to G (read) tPRH tPWD Ports 1, 3, 7 A to G (write) Figure 25.20 I/O Port Input/Output Timing φ tPOD PO15 to PO0 Figure 25.21 PPG Output Timing φ tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 25.22 TPU Input/Output Timing Rev. 3.00 Jan 11, 2005 page 963 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics φ tTCKS TCLKA to TCLKD tTCKWL tTCKWH tTCKS Figure 25.23 TPU Clock Input Timing φ tTMOD TMO0, TMO1 TMO2, TMO3 Figure 25.24 8-bit Timer Output Timing φ tTMCS TMCI01, TMCI23 tTMCWL tTMCWH tTMCS Figure 25.25 8-bit Timer Clock Input Timing φ tTMRS TMRI01, TMRI23 Figure 25.26 8-bit Timer Reset Input Timing Rev. 3.00 Jan 11, 2005 page 964 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics φ tWOVD WDTOVF tWOVD Figure 25.27 WDT0 Output Timing φ tBUZD BUZZ tBUZD Figure 25.28 WDT1 Output Timing φ tPWOD PWM3 toPWM0 Figure 25.29 PWM Output Timing tSCKW SCK0 to SCK4 tScyc tSCKr tSCKf Figure 25.30 SCK Clock Input Timing Rev. 3.00 Jan 11, 2005 page 965 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics SCK0 to SCK4 tTXD TxD0 to TxD4 (transit data) tRXS RxD0 to RxD4 (receive data) tRXH Figure 25.31 SCI Input/Output Timing (Clock Synchronous Mode) φ tTRGS ADTRG Figure 25.32 A/D Converter External Trigger Input Timing Rev. 3.00 Jan 11, 2005 page 966 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics Table 25.10 I2C Bus Timing Condition A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V*2, Vref = 3.6 V to AVCC*3, VSS = AVSS = PLLVSS = 0 V, φ = 5 MHz to maximum operating frequency, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = PLLVSS = 0 V, φ = 5 MHz to maximum operating frequency, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Ratings Item SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rise time SCL, SDA input fall time SCL, SDA input spike pulse elimination time SDA input bus free time Start condition input hold time Symbol tSCL tSCLH tSCLL tSr tSf tSP tBUF tSTAH Min. 12 tcyc 3 tcyc 5 tcyc — — — 5 tcyc 3 tcyc 3 tcyc 3 tcyc 0.5 tcyc 0 — Typ. — — — — — — — — — — — — — Max. — — — 7.5 tcyc* 300 1 tcyc — — — — — — 400 2 1 Unit ns ns ns ns ns ns ns ns ns ns ns ns pF Notes Figure 25.33 Retransmission start condition input tSTAS setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load tSTOS tSDAS tSDAH Cb Notes: 1. 17.5 tcyc can be set according to the clock selected for use by the I C module. For details, see section 18.4, Usage Notes. 2. AVCC = 3.3 V to 5.5 V if the A/D and D/A converters are not used (used as I/O ports). 3. Vref = 3.3 V to AVCC if the A/D and D/A converters are not used (used as I/O ports). Rev. 3.00 Jan 11, 2005 page 967 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics VIH SDA0 to SDA1 tBUF tSTAH VIL tSCLH tSTAS tSP tSTOS SCL0 to SCL1 P* S* tSf tSCLL tSCL tSr tSDAH Sr* tSDAS Note: * S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Retransmission start condition Figure 25.33 I2C Bus Inteface Input/Output Timing (Option) Rev. 3.00 Jan 11, 2005 page 968 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics 25.4 A/D Conversion Characteristics Table 25.11 lists the A/D conversion characteristics. Table 25.11 A/D Conversion Characteristics Condition A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V*1, Vref = 3.6 V to AVCC*2, VSS = AVSS = PLLVSS = 0 V, φ = 2 to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = PLLVSS = 0 V, φ = 2 to 25 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization Absolute accuracy Min. 10 16 — — — — — — — Typ. 10 — — — — — — ±0.5 — Max. 10 — 20 5 ±7.5 ±7.5 ±7.0 — ±8.0 Min. 10 10 — — — — — — — Condition B Typ. 10 — — — — — — ±0.5 — Max. 10 — 20 5 ±3.5 ±3.5 ±3.5 — ±4.0 Unit bits µs pF kΩ LSB LSB LSB LSB LSB Notes: 1. AVCC = 3.3 V to 5.5 V if the A/D and D/A converters are not used (used as I/O ports). 2. Vref = 3.3 V to AVCC if the A/D and D/A converters are not used (used as I/O ports). Rev. 3.00 Jan 11, 2005 page 969 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics 25.5 D/A Conversion Characteristics Table 25.12 shows the D/A conversion characteristics. Table 25.12 D/A Conversion Characteristics Condition A: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 3.0 V to 5.5 V, AVCC = 3.6 V to 5.5 V*1, Vref = 3.6 V to AVCC*2, VSS = AVSS = PLLVSS = 0 V, φ = 2 to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = PLLVSS = 0 V, φ = 2 to 25 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition A Item Resolution Conversion time Absolute accuracy Min. 8 — — — Typ. 8 — ± 2.0 — Max. 8 10 ± 3.0 ± 2.0 Condition B Min. 8 — — — Typ. Max. Unit 8 — 8 10 bits µs 20-pF capacitive load 2-MΩ resistive load 4-MΩ resistive load Test Conditions ± 1.5 ± 2.0 LSB — ± 1.5 LSB Notes: 1. AVCC = 3.3 V to 5.5 V if the A/D and D/A converters are not used (used as I/O ports). 2. Vref = 3.3 V to AVCC if the A/D and D/A converters are not used (used as I/O ports). Rev. 3.00 Jan 11, 2005 page 970 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics 25.6 Flash Memory Characteristics Table 25.13 Flash Memory Characteristics Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = PLLVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Symbol Min. 124 Item Programming time* * * Erase time*1*3*5 Number of rewrites Programming Wait time after SWE1 bit setting* Wait time after PSU1 bit setting* Wait time after P1 bit setting* * 14 1 1 Typ. 10 50 — — — — — — — — — — — — — — — — — — — — — — — Max. 200 1000 100 — — 30 10 200 — — — — — 6 994 — — — 10 — — — — — 100 Unit ms/128 bytes ms/block Times µs µs µs µs µs µs µs µs µs µs Times Times µs µs µs ms µs µs µs µs µs Times tP tE NWEC x0 y z0 z1 z2 — — — 1 50 — — — 5 5 4 2 2 — — 100 1 100 — 10 10 6 2 4 — Wait time after P1 bit clearing* 1 1 α β γ 1 Wait time after PSU1 bit clearing* Wait time after PV1 bit setting* 1 Wait time after H'FF dummy write* Wait time after PV1 bit clearing*1 Maximum number of writes* * Common Erasing 14 ε η N1 N2 Wait time after SWE1 bit clearing* Wait time after SWE1 bit setting* Wait time after E1 bit setting* * Wait time after E1 bit clearing* 15 1 1 1 x1 x y z α Wait time after ESU1 bit setting*1 Wait time after ESU1 bit clearing* Wait time after EV1 bit setting* 1 1 β γ ε η N Wait time after H'FF dummy write* Wait time after EV1 bit clearing*1 Maximum number of erases* * 15 1 Notes: 1. Follow the program/erase algorithms when making the time settings. Rev. 3.00 Jan 11, 2005 page 971 of 1220 REJ09B0186-0300O Section 25 Electrical Characteristics 2. Programming time per 128 bytes. (Indicates the total time during which the P1 bit is set in flash memory control register 1 (FLMCR1). Does not include the program-verify time.) 3. Time to erase one block. (Indicates the time during which the E1 bit is set in FLMCR1. Does not include the erase-verify time.) 4. Maximum programming time (tP(max.) = Wait time after P1 bit setting (z) × maximum number of writes (N)) (z0 + z1) × 6 + z2 × 994 5. Maximum erase time (tE(max.) = Wait time after E1 bit setting (z) × maximum number of erases (N)) 25.7 Usage Note Although both the F-ZTAT and masked ROM versions fully meet the electrical specifications listed in this manual, due to differences in the fabrication process, the on-chip ROM, and the layout patterns, there will be differences in the actual values of the electrical characteristics, the operating margins, the noise margins, and other aspects. Therefore, if a system is evaluated using the F-ZTAT version, a similar evaluation should also be performed using the masked ROM version. Rev. 3.00 Jan 11, 2005 page 972 of 1220 REJ09B0186-0300O Appendix A Instruction Set Appendix A Instruction Set A.1 Instruction List Operand Notation Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + – × ÷ ∧ ∨ ⊕ → ¬ ( ) :8/:16/:24/:32 General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-and-accumulate register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Add Subtract Multiply Divide Logical AND Logical OR Logical exclusive OR Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Logical NOT (logical complement) Contents of operand 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 3.00 Jan 11, 2005 page 973 of 1220 REJ09B0186-0300O Appendix A Instruction Set Condition Code Notation Symbol Changes according to the result of instruction * 0 1 — Undetermined (no guaranteed value) Always cleared to 0 Always set to 1 Not affected by execution of the instruction Rev. 3.00 Jan 11, 2005 page 974 of 1220 REJ09B0186-0300O Table A.1 Instruction Set (1) Data Transfer Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 IHNZVC —— —— —— —— —— —— —— 0— 0— 0— 0— 0— 0— 0— Advanced 1 1 2 3 5 3 2 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic MOV MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd B W4 W W 2 2 B B B B 8 2 2 4 6 B 4 B 2 B 6 B 4 B 2 B 2 B 8 B 4 B 2 @ERs→Rd8 @(d:16,ERs)→Rd8 @(d:32,ERs)→Rd8 B 2 Rs8→Rd8 MOV.B #xx:8,Rd B2 #xx:8→Rd8 Operation @ERs→Rd8,ERs32+1→ERs32 @aa:8→Rd8 @aa:16→Rd8 @aa:32→Rd8 Rs8→@ERd Rs8→@(d:16,ERd) Rs8→@(d:32,ERd) ERd32-1→ERd32,Rs8→@ERd Rs8→@aa:8 Rs8→@aa:16 Rs8→@aa:32 #xx:16→Rd16 Rs16→Rd16 @ERs→Rd16 —— —— —— —— —— —— —— —— —— —— —— —— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 3 4 2 3 5 3 2 3 4 2 1 2 ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 975 of 1220 REJ09B0186-0300O Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 0— 0— 0— 3 5 3 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic MOV MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd L L L L 10 4 6 8 L 6 L 4 L 2 L6 W 6 W 4 W 2 W 8 W 4 W 2 Rs16→@ERd Rs16→@(d:16,ERd) Rs16→@(d:32,ERd) W 6 @aa:32→Rd16 W 4 @aa:16→Rd16 W 2 W 8 @(d:32,ERs)→Rd16 MOV.W @(d:16,ERs),Rd W 4 @(d:16,ERs)→Rd16 —— —— Appendix A Instruction Set Operation IHNZVC @ERs→Rd16,ERs32+2→ERs32 — — —— —— —— —— —— 0— 0— 0— 0— 0— 0— —— —— 0— 0— 3 4 2 3 5 3 3 4 ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ERd32-2→ERd32,Rs16→@ERd — — Rs16→@aa:16 Rs16→@aa:32 #xx:32→ERd32 ERs32→ERd32 @ERs→ERd32 @(d:16,ERs)→ERd32 @(d:32,ERs)→ERd32 @ERs→ERd32,ERs32+4→@ERs32 @aa:16→ERd32 @aa:32→ERd32 —— —— —— —— —— —— —— —— ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ Rev. 3.00 Jan 11, 2005 page 976 of 1220 REJ09B0186-0300O 0— 0— 0— 0— 0— 0— 0— 0— 3 1 4 5 7 5 5 6 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 0— 0— 4 5 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic Operation ERs32→@ERd 6 10 4 6 8 2 4 2 4 4 ERs32→@aa:32 @SP→Rn16,SP+2→SP @SP→ERn32,SP+4→SP SP-2→SP,Rn16→@SP SP-4→SP,ERn32→@SP (@SP→ERn32,SP+4→SP) Repeated for each register restored STM STM (ERm-ERn),@-SP L 4 (SP-4→SP,ERn32→@SP) Repeated for each register saved MOVFPE MOVTPE MOVTPE Rs,@aa:16 MOVFPE @aa:16,Rd Cannot be used in the H8S/2643 Group Cannot be used in the H8S/2643 Group ERs32→@aa:16 ERs32→@(d:32,ERd) ERs32→@(d:16,ERd) —— —— —— MOV MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) L MOV.L ERs,@(d:32,ERd) L MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 POP POP.L ERn PUSH PUSH.L ERn LDM LDM @SP+,(ERm-ERn) L L PUSH.W Rn W L POP.W Rn W L L L L 4 IHNZVC 0— 0— —— —— —— —— —— —— 0— 0— 0— 0— 0— 0— —————— 7 5 5 6 3 5 3 5 7/9/11 [1] ↔↔↔↔↔↔↔↔↔↔ ERd32-4→ERd32,ERs32→@ERd — — —————— ↔↔↔↔↔↔↔↔↔↔ 7/9/11 [1] [2] [2] Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 977 of 1220 REJ09B0186-0300O (2) Arithmetic Instructions Addressing Mode/ Instruction Length (Bytes) Appendix A Instruction Set Condition Code No. of States*1 Advanced Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic ADD ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDX ADDX Rs,Rd ADDS ADDS #2,ERd ADDS #4,ERd INC INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd DAA SUB SUB.W #xx:16,Rd SUB.B Rs,Rd B W4 DAA Rd B L 2 2 2 L 2 W 2 W 2 INC.B Rd B 2 L 2 L 2 ADDS #1,ERd L 2 B 2 ADDX #xx:8,Rd B2 L 2 L6 W 2 Rd16+Rs16→Rd16 ERd32+#xx:32→ERd32 ERd32+ERs32→ERd32 Rd8+#xx:8+C→Rd8 Rd8+Rs8+C→Rd8 ERd32+1→ERd32 ERd32+2→ERd32 ERd32+4→ERd32 Rd8+1→Rd8 Rd16+1→Rd16 Rd16+2→Rd16 ERd32+1→ERd32 ERd32+2→ERd32 Rd8 decimal adjust→Rd8 Rd8-Rs8→Rd8 Rd16-#xx:16→Rd16 W4 Rd16+#xx:16→Rd16 B 2 Rd8+Rs8→Rd8 ADD.B #xx:8,Rd B2 Rd8+#xx:8→Rd8 Operation IHNZVC — — ↔ ↔ ↔ ↔ 1 1 — [3] 2 — [3] 1 — [4] 3 — [4] — — 1 [5] 1 [5] 1 —— — —— — —— — —— — —— — —— — —— — —— — —— — —— — —— — —* — * 1 1 1 1 1 1 1 1 1 1 — [3] 2 ↔↔ ↔ ↔↔↔↔↔↔↔ ↔↔↔↔↔ ↔↔↔↔↔↔↔ ↔ ↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔ ↔↔ ↔↔↔↔↔ ↔↔↔ ↔↔↔↔↔↔↔↔ Rev. 3.00 Jan 11, 2005 page 978 of 1220 REJ09B0186-0300O Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 1 3 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic SUB SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBX SUBX Rs,Rd SUBS SUBS #2,ERd SUBS #4,ERd DEC DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DAS MULXU MULXU.W Rs,ERd W 2 MULXU.B Rs,Rd B 2 DAS Rd B 2 L 2 L 2 W 2 W 2 DEC.B Rd B 2 L 2 Rd8-1→Rd8 Rd16-1→Rd16 Rd16-2→Rd16 ERd32-1→ERd32 ERd32-2→ERd32 Rd8 decimal adjust→Rd8 L 2 SUBS #1,ERd L 2 ERd32-1→ERd32 ERd32-2→ERd32 ERd32-4→ERd32 B 2 Rd8-Rs8-C→Rd8 SUBX #xx:8,Rd B2 Rd8-#xx:8-C→Rd8 L 2 ERd32-ERs32→ERd32 L6 ERd32-#xx:32→ERd32 W 2 Rd16-Rs16→Rd16 — [3] Operation IHNZVC — [4] — [4] — — 1 [5] [5] 1 1 —————— —————— —————— —— —— —— —— —— —* — — — — — *— 1 1 1 1 1 1 1 1 1 ↔↔↔↔↔ ↔↔↔↔↔↔ ↔↔↔↔↔↔ ↔↔↔↔↔ ↔↔ ↔↔↔↔↔ ↔↔↔ ↔↔↔↔↔ Rd8×Rs8→Rd16 (unsigned multiplication) — — — — — — Rd16×Rs16→ERd32 (unsigned multiplication) —————— 3 4 MULXS.W Rs,ERd W 4 Rd16×Rs16→ERd32 (signed multiplication) Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 979 of 1220 REJ09B0186-0300O MULXS MULXS.B Rs,Rd B 4 —— ↔↔ ↔↔ —— Rd8×Rs8→Rd16 (signed multiplication) —— —— 4 5 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 12 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic Operation DIVXU RdL: quotient) (unsigned division) DIVXU.W Rs,ERd W 2 DIVXU.B Rs,Rd B 2 IHNZVC Appendix A Instruction Set Rd16÷Rs8→Rd16 (RdH: remainder, — — [6] [7] — — ERd32÷Rs16→ERd32 (Ed: remainder, — — [6] [7] — — Rd: quotient) (unsigned division) 20 NEG.L ERd EXTU EXTU.L ERd L EXTU.W Rd W 2 2 L 2 0-ERd32→ERd32 0→( of Rd16) 0→( of ERd32) — ↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔ —— 0 ↔↔↔ ↔↔ ↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔ Rev. 3.00 Jan 11, 2005 page 980 of 1220 REJ09B0186-0300O DIVXS DIVXS.B Rs,Rd B 4 Rd16÷Rs8→Rd16 (RdH: remainder, — — [8] [7] — — RdL: quotient) (signed division) DIVXS.W Rs,ERd Rd8-#xx:8 2 Rd8-Rs8 Rd16-#xx:16 2 Rd16-Rs16 ERd32-#xx:32 2 2 2 ERd32-ERs32 0-Rd8→Rd8 0-Rd16→Rd16 W 4 ERd32÷Rs16→ERd32 (Ed: remainder, — — [8] [7] — — Rd: quotient) (signed division) CMP CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd NEG NEG.W Rd W NEG.B Rd B L L6 W W4 B CMP.B #xx:8,Rd B2 — — 1 1 — [3] 2 — [3] 1 — [4] 3 — [4] — — 1 1 1 1 —— 0 0— 0— 1 1 21 13 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic Operation ( of Rd16)→ ( of Rd16) —— EXTS EXTS.W Rd W 2 IHNZVC ( of ERd32) @ERd-0→CCR set, (1)→ ( of @ERd) MAC MAC @ERn+, @ERm+ — 4 @ERnx@ERm+MAC→MAC (signal multiplication) @ERn+2→ERn, ERm+2→ERm CLRMAC LDMAC LDMAC ERs,MACL STMAC STMAC MACL,ERd L 2 STMAC MACH,ERd L 2 L 2 LDMAC ERs,MACH L 2 CLRMAC — 2 0→MACH, MACL ERs→MACH ERs→MACL MACH→ERd MACL→ERd — —— — — — — —— — — — — —— — — — 2 [12] 2 [12] 2 [12] — —— — — — [11] [11] [11] 4 Rev. 3.00 Jan 11, 2005 page 981 of 1220 REJ09B0186-0300O —— ↔↔ ↔↔ ↔↔ —— ↔ ↔ TAS*3 TAS @ERd B 4 —— ↔ ↔ EXTS.L ERd L 2 ( of ERd32)→ —— ↔ ↔ 0— 1 0— 1 0— 4 — — 1 [12] 1 [12] Appendix A Instruction Set (3) Logical Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Appendix A Instruction Set Mnemonic AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd NOT NOT.B Rd NOT.W Rd NOT.L ERd L B W L L6 4 2 2 2 W 2 W4 B 2 B2 L 4 L6 W 2 W4 B 2 B2 L 4 Rd8⁄#xx:8→Rd8 Rd8⁄Rs8→Rd8 Rd16⁄#xx:16→Rd16 Rd16⁄Rs16→Rd16 ERd32⁄#xx:32→ERd32 ERd32⁄ERs32→ERd32 Rd8⊕#xx:8→Rd8 Rd8⊕Rs8→Rd8 Rd16⊕#xx:16→Rd16 Rd16⊕Rs16→Rd16 ERd32⊕#xx:32→ERd32 ERd32⊕ERs32→ERd32 ¬ Rd8→Rd8 ¬ Rd16→Rd16 ¬ ERd32→ERd32 L6 W 2 Rd16∧Rs16→Rd16 ERd32∧#xx:32→ERd32 ERd32∧ERs32→ERd32 W4 Rd16∧#xx:16→Rd16 B 2 Rd8∧Rs8→Rd8 B2 Rd8∧#xx:8→Rd8 Operation IHNZVC —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 1 1 2 1 3 2 1 1 2 1 3 2 1 1 2 1 3 2 1 1 1 ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ Rev. 3.00 Jan 11, 2005 page 982 of 1220 REJ09B0186-0300O (4) Shift Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd L L W 2 2 2 W 2 C MSB LSB B 2 0 B 2 L 2 L 2 W 2 W 2 MSB LSB C B 2 B 2 L 2 L 2 W 2 C MSB W 2 LSB B 2 0 B 2 Operation IHNZVC —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— —— 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 983 of 1220 REJ09B0186-0300O Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 0 0 1 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd ROTXL ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd L 2 L 2 W 2 W 2 B 2 B 2 L 2 L 2 — — — — — — MSB — — LSB C W 2 — C W 2 — MSB LSB B 2 — B 2 — L 2 — L 2 — W 2 — MSB LSB W 2 — 0 C B 2 — B 2 — Operation IHNZVC —— 0 Appendix A Instruction Set —— 0 —— 0 0 —— 0 0 —— 0 0 —— 0 —— —— —— —— —— —— —— —— —— —— —— —— 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ Rev. 3.00 Jan 11, 2005 page 984 of 1220 REJ09B0186-0300O Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 0 0 1 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd C MSB ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd L 2 L 2 W 2 — 1 W 2 — MSB LSB C B 2 — B 2 — L 2 L 2 W 2 W 2 LSB B 2 B 2 —— —— —— —— —— —— —— —— —— —— —— —— Operation IHNZVC 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 ↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔ Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 985 of 1220 REJ09B0186-0300O (5) Bit-Manipulation Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Appendix A Instruction Set Mnemonic BSET BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BCLR BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 B B B B 2 4 4 6 B B B 4 6 8 B 4 BCLR #xx:3,Rd B 2 B 8 B 6 B 4 B 4 B 2 (Rn8 of Rd8)←1 (Rn8 of @ERd)←1 (Rn8 of @aa:8)←1 (Rn8 of @aa:16)←1 (Rn8 of @aa:32)←1 (#xx:3 of Rd8)←0 (#xx:3 of @ERd)←0 (#xx:3 of @aa:8)←0 (#xx:3 of @aa:16)←0 (#xx:3 of @aa:32)←0 (Rn8 of Rd8)←0 (Rn8 of @ERd)←0 (Rn8 of @aa:8)←0 (Rn8 of @aa:16)←0 B 8 B 6 (#xx:3 of @aa:16)←1 (#xx:3 of @aa:32)←1 B 4 (#xx:3 of @aa:8)←1 B 4 (#xx:3 of @ERd)←1 BSET #xx:3,Rd B 2 (#xx:3 of Rd8)←1 Operation IHNZVC —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 Rev. 3.00 Jan 11, 2005 page 986 of 1220 REJ09B0186-0300O Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 6 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic BCLR BNOT BNOT #xx:3,@ERd [¬ (#xx:3 of @ERd)] BNOT #xx:3,@aa:8 [¬ (#xx:3 of @aa:8)] BNOT #xx:3,@aa:16 B 6 (#xx:3 of @aa:16)← [¬ (#xx:3 of @aa:16)] BNOT #xx:3,@aa:32 B 8 (#xx:3 of @aa:32)← [¬ (#xx:3 of @aa:32)] BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 B 6 B 4 B 4 B 2 (Rn8 of Rd8)←[¬ (Rn8 of Rd8)] B 4 (#xx:3 of @aa:8)← B 4 (#xx:3 of @ERd)← BNOT #xx:3,Rd B 2 BCLR Rn,@aa:32 B 8 (Rn8 of @aa:32)←0 Operation IHNZVC —————— (#xx:3 of Rd8)←[¬ (#xx:3 of Rd8)] — — — — — — —————— 4 —————— 4 —————— 5 —————— 6 —————— (Rn8 of @ERd)←[¬ (Rn8 of @ERd)] — — — — — — (Rn8 of @aa:8)←[¬ (Rn8 of @aa:8)] — — — — — — (Rn8 of @aa:16)← [¬ (Rn8 of @aa:16)] —————— 1 4 4 5 BNOT Rn,@aa:32 B 8 (Rn8 of @aa:32)← [¬ (Rn8 of @aa:32)] —————— 6 BTST BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 B B B BTST #xx:3,Rd B 2 4 4 6 ¬ (#xx:3 of Rd8)→Z ¬ (#xx:3 of @ERd)→Z ¬ (#xx:3 of @aa:8)→Z ¬ (#xx:3 of @aa:16)→Z ——— ——— ——— ——— —— —— —— —— 1 3 3 4 ↔↔↔↔ Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 987 of 1220 REJ09B0186-0300O Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced —— —— 5 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic BTST BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BLD BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BILD BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BST BST #xx:3,@ERd BST #xx:3,@aa:8 B B BST #xx:3,Rd B 2 4 4 B B B 4 6 8 B 4 BILD #xx:3,Rd B 2 B 8 B 6 B 4 B 4 BLD #xx:3,Rd B 2 (#xx:3 of Rd8)→C (#xx:3 of @ERd)→C (#xx:3 of @aa:8)→C (#xx:3 of @aa:16)→C (#xx:3 of @aa:32)→C ¬ (#xx:3 of Rd8)→C ¬ (#xx:3 of @ERd)→C ¬ (#xx:3 of @aa:8)→C ¬ (#xx:3 of @aa:16)→C ¬ (#xx:3 of @aa:32)→C C→(#xx:3 of Rd8) C→(#xx:3 of @ERd) C→(#xx:3 of @aa:8) B 8 B 6 ¬ (Rn8 of @aa:16)→Z ¬ (Rn8 of @aa:32)→Z B 4 ¬ (Rn8 of @aa:8)→Z B 4 ¬ (Rn8 of @ERd)→Z B 2 ¬ (Rn8 of Rd8)→Z B 8 ¬ (#xx:3 of @aa:32)→Z Operation IHNZVC ——— ——— ——— ——— ——— ——— Appendix A Instruction Set —— —— —— —— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— 3 3 4 5 1 3 3 4 5 1 3 3 4 5 —————— —————— —————— 1 4 4 ↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔ Rev. 3.00 Jan 11, 2005 page 988 of 1220 REJ09B0186-0300O Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 5 6 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic BST BST #xx:3,@aa:16 BST #xx:3,@aa:32 BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BAND BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BIAND BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BOR BOR #xx:3,@ERd B BOR #xx:3,Rd B B 2 4 B B B 4 4 6 8 BIAND #xx:3,Rd B 2 B 8 B 6 B 4 B 4 BAND #xx:3,Rd B 2 B 8 B 6 B 4 ¬ C→(#xx:3 of @aa:8) ¬ C→(#xx:3 of @aa:16) ¬ C→(#xx:3 of @aa:32) C∧(#xx:3 of Rd8)→C C∧(#xx:3 of @ERd)→C C∧(#xx:3 of @aa:8)→C C∧(#xx:3 of @aa:16)→C C∧(#xx:3 of @aa:32)→C C∧[¬ (#xx:3 of Rd8)]→C C∧[¬ (#xx:3 of @ERd)]→C C∧[¬ (#xx:3 of @aa:8)]→C C∧[¬ (#xx:3 of @aa:16)]→C C∧[¬ (#xx:3 of @aa:32)]→C C∨(#xx:3 of Rd8)→C C∨(#xx:3 of @ERd)→C B 4 ¬ C→(#xx:3 of @ERd) B 2 ¬ C→(#xx:3 of Rd8) B 8 C→(#xx:3 of @aa:32) B 6 C→(#xx:3 of @aa:16) Operation IHNZVC —————— —————— —————— —————— —————— —————— —————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— 1 4 4 5 6 1 3 3 4 5 1 3 3 4 5 1 3 ↔↔↔↔↔↔↔↔↔↔↔↔ Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 989 of 1220 REJ09B0186-0300O Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 3 4 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic Operation C∨(#xx:3 of @aa:8)→C C∨(#xx:3 of @aa:16)→C C∨(#xx:3 of @aa:32)→C C∨[¬ (#xx:3 of Rd8)]→C 4 4 6 8 2 4 4 6 8 2 4 4 6 8 C∨[¬ (#xx:3 of @ERd)]→C C∨[¬ (#xx:3 of @aa:8)]→C C∨[¬ (#xx:3 of @aa:16)]→C C∨[¬ (#xx:3 of @aa:32)]→C C⊕(#xx:3 of Rd8)→C C⊕(#xx:3 of @ERd)→C C⊕(#xx:3 of @aa:8)→C C⊕(#xx:3 of @aa:16)→C C⊕(#xx:3 of @aa:32)→C C⊕[¬ (#xx:3 of Rd8)]→C C⊕[¬ (#xx:3 of @ERd)]→C C⊕[¬ (#xx:3 of @aa:8)]→C C⊕[¬ (#xx:3 of @aa:16)]→C C⊕[¬ (#xx:3 of @aa:32)]→C BOR BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BIOR BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BXOR BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 BIXOR BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 B B B B BIXOR #xx:3,Rd B B B B B BXOR #xx:3,Rd B B B B B B 2 B 8 B 6 B 4 IHNZVC ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— Appendix A Instruction Set 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ Rev. 3.00 Jan 11, 2005 page 990 of 1220 REJ09B0186-0300O (6) Branch Instructions Addressing Mode/ Instruction Length (Bytes) Operation Condition Code Branching Condition No. of States*1 Advanced Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic Bcc BRA d:16(BT d:16) BRN d:8(BF d:8) BRN d:16(BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:B(BHS d:8) BCC d:16(BHS d:16) BCS d:8(BLO d:8) BCS d:16(BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 — — — — — — — 4 2 4 2 4 2 4 V=0 Z=1 Z=0 — 2 — 4 C=1 — 2 — 4 C=0 — 2 — 4 C∨Z=1 — 2 — 4 C∨Z=0 — 2 else next; — 4 PC←PC+d Never BRA d:8(BT d:8) — 2 if condition is true then Always IHNZVC —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 991 of 1220 REJ09B0186-0300O Addressing Mode/ Instruction Length (Bytes) Operation Condition Code Branching Condition No. of States*1 Advanced 2 3 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic Bcc BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 — — 2 4 — 4 — 2 — 4 — 2 — 4 N⊕V=1 — 2 — 4 N⊕V=0 — 2 — 4 N=1 — 2 N=0 — 4 BVS d:8 — 2 V=1 IHNZVC —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— Appendix A Instruction Set 2 3 2 3 2 3 2 3 Rev. 3.00 Jan 11, 2005 page 992 of 1220 REJ09B0186-0300O Z∨(N⊕V)=0 — — — — — — —————— Z∨(N⊕V)=1 — — — — — — —————— 2 3 2 3 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 2 3 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic JMP JMP @aa:24 JMP @@aa:8 BSR BSR d:16 JSR JSR @aa:24 JSR @@aa:8 RTS RTS — — 2 2 PC←@SP+ — 4 JSR @ERn — 2 — 4 PC→@-SP,PC←ERn PC→@-SP,PC←aa:24 PC→@-SP,PC←@aa:8 BSR d:8 — 2 PC→@-SP,PC←PC+d:8 PC→@-SP,PC←PC+d:16 — 2 PC←@aa:8 — 4 PC←aa:24 JMP @ERn — 2 PC←ERn Operation IHNZVC —————— —————— —————— —————— —————— —————— —————— —————— —————— 5 4 5 4 5 6 5 Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 993 of 1220 REJ09B0186-0300O (7) System Control Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 8 [9] Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Appendix A Instruction Set Mnemonic TRAPA EXR→@-SP,→PC EXR←@SP+,CCR←@SP+, PC←@SP+ SLEEP LDC LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR W W W W W W W 10 4 4 6 6 8 8 W 10 W 6 W 6 W 4 W 4 B 2 B 2 Rs8→CCR Rs8→EXR @ERs→CCR @ERs→EXR @(d:16,ERs)→CCR @(d:16,ERs)→EXR @(d:32,ERs)→CCR @(d:32,ERs)→EXR @ERs→CCR,ERs32+2→ERs32 @ERs→EXR,ERs32+2→ERs32 @aa:16→CCR @aa:16→EXR @aa:32→CCR @aa:32→EXR B4 #xx:8→EXR LDC #xx:8,CCR B2 #xx:8→CCR SLEEP — Transition to power-down state TRAPA #xx:2 — PC→@-SP,CCR→@-SP, Operation IHNZVC 1 ————— ↔ ↔ ↔ ↔ ↔ ↔ —————— ↔ ↔ ↔ ↔ ↔ ↔ —————— ↔ ↔ ↔ ↔ ↔ ↔ —————— ↔ ↔ ↔ ↔ ↔ ↔ —————— ↔ ↔ ↔ ↔ ↔ ↔ —————— ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Rev. 3.00 Jan 11, 2005 page 994 of 1220 REJ09B0186-0300O —————— ↔ ↔ ↔ RTE RTE — 5 [9] 2 1 2 1 1 3 3 4 4 6 6 4 —————— 4 4 —————— 4 5 —————— 5 Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States*1 Advanced 1 1 Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa — Mnemonic STC STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@-ERd STC EXR,@-ERd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 ANDC ANDC #xx:8,EXR ORC ORC #xx:8,EXR XORC XORC #xx:8,EXR NOP NOP XORC #xx:8,CCR B4 B2 B4 — ORC #xx:8,CCR B2 B4 ANDC #xx:8,CCR B2 W 8 W 8 W 6 W 6 W 4 W 4 W 10 W 10 W 6 EXR→@(d:16,ERd) CCR→@(d:32,ERd) EXR→@(d:32,ERd) W 6 CCR→@(d:16,ERd) W 4 EXR→@ERd W 4 CCR→@ERd B 2 EXR→Rd8 B 2 CCR→Rd8 Operation IHNZVC —————— —————— —————— —————— —————— —————— —————— —————— 3 3 4 4 6 6 4 —————— 4 ERd32-2→ERd32,CCR→@ERd — — — — — — ERd32-2→ERd32,EXR→@ERd CCR→@aa:16 EXR→@aa:16 CCR→@aa:32 EXR→@aa:32 CCR∧#xx:8→CCR EXR∧#xx:8→EXR CCR∨#xx:8→CCR EXR∨#xx:8→EXR CCR⊕#xx:8→CCR EXR⊕#xx:8→EXR 2 PC←PC+2 —————— —————— —————— —————— 4 4 5 5 ↔ ↔ ↔ ↔ ↔ ↔ 1 —————— 2 ↔ ↔ ↔ ↔ ↔ ↔ 1 —————— 2 ↔ ↔ ↔ ↔ ↔ ↔ 1 —————— —————— 2 1 Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 995 of 1220 REJ09B0186-0300O (8) Block Transfer Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code — No. of States*1 Advanced Operand Size #xx Rn @ERn @(d,ERn) @aa @–ERn/@ERn+ @(d,PC) @@aa Appendix A Instruction Set Mnemonic Operation EEPMOV EEPMOV.B — 4 if R4L 0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4L-1→R4L Until R4L=0 else next; 4 if R4 0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4-1→R4 Until R4=0 else next; IHNZVC —————— Rev. 3.00 Jan 11, 2005 page 996 of 1220 REJ09B0186-0300O EEPMOV.W — —————— 4+2n *2 4+2n *2 Notes: 1. The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. 2. n is the initial value of R4L or R4. 3. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. [1] Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. [2] Cannot be used in the H8S/2643 Group. [3] Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. [4] Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. [5] Retains its previous value when the result is zero; otherwise cleared to 0. [6] Set to 1 when the divisor is negative; otherwise cleared to 0. [7] Set to 1 when the divisor is zero; otherwise cleared to 0. [8] Set to 1 when the quotient is negative; otherwise cleared to 0. [9] One additional state is required for execution when EXR is valid. Appendix A Instruction Set A.2 Instruction Codes Table A.2 shows the instruction codes. Rev. 3.00 Jan 11, 2005 page 997 of 1220 REJ09B0186-0300O Table A.2 Instruction Codes Instruction Mnemonic Size 1st byte 8 IMM rs 1 IMM rs 1 0 erd IMM 1 ers 0 erd 0 0 erd 0 erd 0 erd IMM rs IMM rs 6 IMM rs 6 0 erd 0 IMM 4 0 IMM 0 erd abs 1 3 disp 0 disp 8 1 0 disp 0 disp 0 0 7 0 7 6 6 rd 0 IMM 0 IMM abs abs 0 0 7 6 0 IMM 0 7 6 0 IMM 0 1 0 6 IMM 6 6 0 ers 0 erd F IMM rd rd rd rd 8 9 rd rd rd 0 7 0 7 0 0 0 0 9 0 E 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4 5 1 8 0 A A E C 6 1 6 1 A 6 9 6 rd E rd B B B A A 9 9 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte B B W W L L L L L B B B B W W L L B B B B B B B — — — — ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS ADDS #2,ERd ADDS #4,ERd ADDX ADDX Rs,Rd AND AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC ANDC #xx:8,EXR BAND BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 Bcc BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) BRA d:8 (BT d:8) BAND #xx:3,Rd ANDC #xx:8,CCR AND.B #xx:8,Rd ADDX #xx:8,Rd ADDS #1,ERd ADD Instruction Format 9th byte 10th byte Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 998 of 1220 REJ09B0186-0300O Instruction Mnemonic Size 1st byte 4 5 0 disp 3 0 disp 4 0 disp 5 0 disp 6 0 disp 7 0 disp 8 0 disp 9 0 disp A 0 disp B 0 disp C 0 disp D 0 disp E disp F 8 0 disp 0 disp disp disp disp disp disp disp disp disp disp disp disp 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 F 8 E 8 D 8 C 8 B 8 A 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 disp 2 2 disp 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte — — — — — — — — — — — — — — — — — — — — — — — — — — — — BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 Bcc Instruction Format 10th byte Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 999 of 1220 REJ09B0186-0300O Instruction Mnemonic Size 1st byte 7 7 0 IMM 0 IMM abs 0 IMM 7 0 IMM 2 0 abs 7 2 0 0 7 abs 1 3 rn 0 erd abs 1 abs abs 6 3 1 IMM 0 erd 1 IMM 1 IMM abs abs 7 6 0 1 IMM 0 7 6 1 IMM 0 abs 1 3 1 IMM 0 erd 1 IMM 1 IMM abs abs 0 7 7 1 IMM 0 7 7 1 IMM 0 abs 1 3 1 IMM 0 erd abs 1 3 0 0 7 0 7 4 4 rd 1 IMM 1 IMM abs abs 0 0 7 4 1 IMM 0 7 4 1 IMM 0 0 0 7 7 0 7 7 0 rd 0 0 7 6 0 7 6 0 rd 8 8 6 2 rn 0 2 rn 0 6 2 rn 0 0 6 2 rn 0 rd 8 8 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 A A E C 4 A A E C 7 A A E C 6 A A F D 2 A A F 7 2 D 0 erd 0 7 2 0 2 0 IMM rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B B B B B B B B B B B BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BIOR #xx:3,Rd BILD #xx:3,Rd BIAND #xx:3,Rd BCLR Instruction Format 10th byte Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1000 of 1220 REJ09B0186-0300O Instruction Mnemonic Size 1st byte 6 1 IMM 0 erd abs 1 8 abs abs 6 7 1 IMM 1 IMM 8 rd 0 1 IMM 1 IMM abs abs 7 1 IMM 5 0 7 5 1 IMM 0 0 7 5 0 0 rd 0 0 IMM 0 IMM abs abs 7 7 0 0 IMM 0 7 7 0 IMM 0 7 7 0 0 rd 0 0 IMM 0 IMM abs abs 0 7 1 0 IMM 0 7 1 0 IMM 0 0 7 1 8 8 rd 0 6 8 8 6 1 1 abs abs rn rn 0 0 6 1 rn 0 6 1 rn 0 7 1 7 7 0 7 5 0 3 1 IMM 0 erd abs 1 3 0 IMM 0 erd abs 1 3 0 IMM 0 erd abs 1 3 rn 0 erd abs 1 3 6 7 0 0 6 7 1 IMM 0 0 1 IMM 6 7 0 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 A A F D 1 A A F D 1 A A E C 7 A A E C 5 A A F D 7 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B B B B B B B B B B B BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BNOT #xx:3,Rd BLD #xx:3,Rd BIXOR #xx:3,Rd BIST Instruction Format 10th byte Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1001 of 1220 REJ09B0186-0300O Instruction Mnemonic Size 1st byte 7 7 7 6 6 abs 7 7 7 6 abs abs 7 6 6 7 0 erd abs 1 abs abs 3 disp 0 disp 0 IMM 0 erd 0 IMM 0 IMM abs abs abs 1 3 0 IMM 0 erd abs 1 3 rn 0 erd 0 0 rd 0 C 6 3 rn 0 0 7 7 rd 3 3 0 IMM 0 IMM abs abs 0 0 7 3 0 IMM 0 7 3 0 IMM 0 8 8 6 7 0 6 7 0 0 6 7 0 IMM 0 6 7 0 IMM 0 rd 0 8 8 6 0 6 0 rn 0 rn 0 6 0 rn 0 7 6 6 5 5 6 7 7 6 6 7 7 7 6 6 6 7 3 A A E C 3 A A F D 7 C 5 A A F D 0 6 0 rn 0 0 rn rd A 3 8 A 0 IMM 1 8 7 0 0 0 0 IMM 0 F abs 0 IMM 7 0 0 D 0 erd 0 IMM 0 7 0 0 0 0 IMM rd A 0 IMM 3 0 7 4 0 A abs 0 IMM 1 0 7 4 0 E abs 0 IMM 7 4 0 C 0 erd 0 IMM 0 7 4 0 4 0 IMM rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B — — B B B B B B B B B B B B BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR BSR d:16 BST BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST #xx:3,Rd BST #xx:3,Rd BSR d:8 BSET #xx:3,Rd BOR Instruction Format 10th byte Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1002 of 1220 REJ09B0186-0300O Instruction Mnemonic Size 1st byte 7 6 abs abs 6 3 rn 0 6 7 7 7 abs 1 abs abs 7 5 0 IMM 3 A IMM rs 2 IMM rs 2 0 erd IMM 1 ers 0 erd 0 0 0 5 D 7 0 erd 0 erd 0 0 rd 0 erd C 5 D B 4 5 5 9 9 8 8 F F 5 5 1 3 rs rs rd 0 erd F D D rs rs rd rd rd rd rd rd rd rd 0 0 0 7 5 0 0 IMM 0 6 6 0 A 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 B 3 1 1 1 B B B B A F F F A D 9 C rd 1 A A E 0 IMM 7 5 0 C 0 IMM 0 erd 0 7 5 0 5 0 IMM rd A 3 0 A 1 0 6 3 rn 0 E abs 6 3 rn 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B — B B W W L L B B B W W L L B W B W — — BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CLRMAC CMP CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAS DEC DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DIVXS DIVXS.W Rs,ERd DIVXU DIVXU.W Rs,ERd EEPMOV EEPMOV.B EEPMOV.W DIVXU.B Rs,Rd DIVXS.B Rs,Rd DEC.B Rd DAS Rd DAA Rd CMP.B #xx:8,Rd BTST Instruction Format 10th byte Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1003 of 1220 REJ09B0186-0300O Instruction Mnemonic Size 1st byte 1 1 0 erd rd 0 erd rd rd rd 0 erd 0 erd 0 abs abs 0 ern abs abs IMM 4 IMM 0 1 4 4 4 4 4 4 4 4 4 4 1 0 1 0 1 1 0 7 7 6 6 6 6 1 6 0 6 F F 8 8 D D B B 1 6 9 0 6 9 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 0 rs 0 0 0 0 0 0 0 0 0 0 abs abs 6 6 B B disp disp 2 2 0 0 disp disp rs 1 0 7 0 1 1 0 0 0 0 0 5 0 ern 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 3 3 1 7 F E D B A 9 B F B 7 B D B 5 A 0 7 7 7 5 7 F 7 D rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W L W L B W W L L — — — — — — B B B B W W W W W W W W W W EXTS.W Rd EXTS.L ERd EXTU EXTU.L ERd INC INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd JMP JMP @aa:24 JMP @@aa:8 JSR JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC #xx:8,CCR JSR @ERn JMP @ERn INC.B Rd EXTU.W Rd EXTS Instruction Format 10th byte Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1004 of 1220 REJ09B0186-0300O Instruction Mnemonic Size 1st byte 0 0 0 0 ern+1 0 ern+2 0 ern+3 0 0 0 0 0 0 em 0 em F IMM rs 0 ers 0 ers disp 6 A rd 2 disp 0 ers 0 ers abs 0 abs abs 2 1 erd 1 erd disp 6 A A rs disp 0 erd 1 erd abs 8 A 0 rs 0 ers 0 ers 8 0 ers rd rd rd rd F 0 6 B disp 2 rd disp rs IMM rs abs abs rs 0 rs rs rd rd rd 0 rd rd rd 0 6 6 7 6 2 6 6 6 6 7 6 3 6 6 7 0 6 6 7 9 D 9 A A rs C 8 E 8 A A rd C 8 E 8 C rd 1 6 0 6 D 3 3 0 ers 3 2 0 ers 1 3 0 6 D 7 1 2 0 6 D 7 1 1 0 6 D 7 1 0 abs 4 1 6 B 2 1 0 abs 4 0 6 B 2 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W L L L L L — B B B B B B B B B B B B B B B B W W W W W LDC @aa:32,CCR LDC @aa:32,EXR LDM*3 LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs,MACL MAC MOV MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa :16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.B #xx:8,Rd MAC @ERn+,@ERm+ LDMAC ERs,MACH LDC Instruction Format 10th byte Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1005 of 1220 REJ09B0186-0300O Instruction Mnemonic Size 1st byte 6 0 ers 0 abs abs 2 1 erd 1 erd disp 6 disp B A rs 0 erd 1 erd 8 abs abs IMM A 0 0 erd 1 ers 0 erd 0 0 ers 0 erd 0 ers 0 erd disp 6 B 2 0 erd disp 0 ers 0 ers 0 erd 0 0 erd 0 erd 2 1 erd 0 ers 1 erd 0 ers 0 erd 0 6 B disp A 0 ers disp abs abs 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 6 B B 0 6 D 0 7 8 0 6 F 0 6 9 0 6 B 0 6 B 0 6 D 0 7 8 0 6 F 0 6 9 rs rs rs 0 rs rs rd rd 6 6 6 6 7 6 6 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 F A B B D 8 F 9 B B D rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W W W W W W W W L L L L L L L L L L L L L L B B B W B W 5 2 5 0 0 1 C rs rs 0 1 C 0 0 rd 0 erd 5 5 0 2 rs rs rd 0 erd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16 ,ERd MOV.L @aa:32 ,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd)*1 MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVFPE @aa:16,Rd MOVTPE MOVTPE Rs,@aa:16 MULXS MULXS.W Rs,ERd MULXU MULXU.W Rs,ERd MULXU.B Rs,Rd MULXS.B Rs,Rd MOV Instruction Format 10th byte Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1006 of 1220 REJ09B0186-0300O 1 erd 0 ers 8 A 0 ers 0 ers abs abs Cannot be used in the H8S/2643 Group Instruction Mnemonic Size 1st byte 1 1 1 0 erd 0 rd rd 0 erd IMM rs 4 IMM rs 4 0 erd 0 6 4 0 ers 0 erd IMM 4 0 4 IMM 7 0 6 D 7 0 ern F 0 6 D F 8 C 9 D B 0 erd 0 erd F rd rd rd rd 0 rn 0 ern 0 rn 1 IMM F rd rd rd 0 1 1 1 C 1 7 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 2 2 2 2 2 2 1 D 1 D 1 4 1 A 4 9 4 rd 7 3 7 1 7 0 0 0 7 B 7 9 rd 7 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B W L — B W L B B W W L L B B W L W L B B W W L L NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOT.W Rd NOT.L ERd OR OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC ORC #xx:8,EXR POP POP.L ERn PUSH PUSH.L ERn ROTL ROTL.B #2, Rd ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd ROTL.L #2, ERd ROTL.B Rd PUSH.W Rn POP.W Rn ORC #xx:8,CCR OR.B #xx:8,Rd NOT.B Rd NOP NEG Instruction Format 10th byte Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1007 of 1220 REJ09B0186-0300O Instruction Mnemonic Size 1st byte 1 1 1 1 1 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 0 rd rd rd rd 0 erd 0 erd 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 0 F 0 B 0 D 0 9 0 C 0 8 4 7 6 7 3 7 3 3 3 5 3 1 3 4 3 0 2 7 2 3 2 5 2 1 2 4 2 0 3 F 3 B 3 D rd 3 9 rd 3 C rd 3 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B W W L L B B W W L L B B W W L L — — B B W W L L ROTR.B Rd ROTR.B #2, Rd ROTR.W Rd ROTR.W #2, Rd ROTR.L ERd ROTR.L #2, ERd ROTXL ROTXL.B Rd ROTXL.B #2, Rd ROTXL.W Rd ROTXL.W #2, Rd ROTXL.L ERd ROTXL.L #2, ERd ROTXR ROTXR.B Rd ROTXR.B #2, Rd ROTXR.W Rd ROTXR.W #2, Rd ROTXR.L ERd ROTXR.L #2, ERd RTE RTE RTS SHAL.B Rd SHAL.B #2, Rd SHAL.W Rd SHAL.W #2, Rd SHAL.L ERd SHAL.L #2, ERd RTS SHAL ROTR Instruction Format 10th byte Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1008 of 1220 REJ09B0186-0300O Instruction Mnemonic Size 1st byte 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 4 4 4 1 4 1 4 1 0 1 0 1 1 4 0 1 4 1 6 6 6 7 7 6 6 1 6 4 0 9 9 F F 8 8 D D 2 1 rd 1 erd 1 erd 1 erd 1 erd 0 erd 0 erd 1 erd 1 erd 0 0 0 0 0 0 0 0 6 6 B B disp disp A A 0 0 disp disp 2 0 rd 1 8 0 1 0 erd 7 1 0 erd 3 1 5 rd 1 1 rd 1 4 rd 1 0 rd 0 0 erd 7 0 0 erd 3 0 5 rd 0 1 rd 0 4 rd 0 0 rd 1 0 erd F 1 0 erd B 1 D rd 1 9 rd 1 C rd 1 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B W W L L B B W W L L B B W W L L — B B W W SHAR.B Rd SHAR.B #2, Rd SHAR.W Rd SHAR.W #2, Rd SHAR.L ERd SHAR.L #2, ERd SHLL SHLL.B #2, Rd SHLL.W Rd SHLL.W #2, Rd SHLL.L ERd SHLL.L #2, ERd SHLR SHLR.B #2, Rd SHLR.W Rd SHLR.W #2, Rd SHLR.L ERd SHLR.L #2, ERd SLEEP SLEEP STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) W STC.W EXR,@(d:16,ERd) W STC.W CCR,@(d:32,ERd) W STC.W EXR,@(d:32,ERd) W STC.W CCR,@-ERd STC.W EXR,@-ERd W W STC SHLR.B Rd SHLL.B Rd SHAR Instruction Format 10th byte Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1009 of 1220 REJ09B0186-0300O Instruction Mnemonic Size 1st byte 0 abs abs abs abs 0 0 0 0 0 ern 0 ern 0 ern 0 0 0 0 ers 0 ers rd rd IMM rd 0 erd IMM 0 1 7 1 7 1 1 1 1 B IMM rs E 00 IMM IMM rs 5 rs 5 F rd 0 erd 0 6 5 IMM 0 ers 0 erd rd rd IMM 0 0 7 B 0 erd rd C 1 0 5 D 1 7 6 7 0 1 A 5 9 5 rd 7 1 E rd B 9 0 erd B 8 0 erd B 0 0 erd A 1 ers 0 erd A 3 9 rs 9 3 8 rs 2 3 2 3 1 3 0 6 D F 1 2 0 6 D F 1 1 0 6 D F 1 4 1 6 B A 0 1 4 0 6 B A 0 1 4 1 6 B 8 0 1 4 0 6 B 8 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W W W L L L L L B W W L L L L L B B B — B B W W L L STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM*3 STM.L(ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP STM.L (ERn-ERn+3), @-SP STMAC STMAC MACL,ERd SUB SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBS #2,ERd SUBS #4,ERd SUBX SUBX Rs,Rd TAS*2 TAS @ERd TRAPA #x:2 XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd TRAPA XOR SUBX #xx:8,Rd SUBS #1,ERd SUB.B Rs,Rd STMAC MACH,ERd STC Instruction Format 10th byte Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1010 of 1220 REJ09B0186-0300O Instruction Mnemonic Size 1st byte 0 0 1 4 1 0 5 IMM 5 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B XORC #xx:8,CCR XORC #xx:8,EXR XORC Instruction Format 10th byte Notes: 1. Bit 7 of the 4th byte of the MOV.L ERs, @(d:32,ERd) instruction can be either 1 or 0. 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 3. Only register ER0 to ER6 should be used when using the STM/LDM instruction. Legend: IMM: abs: disp: rs, rd, rn: ers, erd, ern, erm: Immediate data (2, 3, 8, 16, or 32 bits) Absolute address (8, 16, 24, or 32 bits) Displacement (8, 16, or 32 bits) Register field (4 bits specifying an 8-bit or 16-bit register. The symbols rs, rd, and rn correspond to operand symbols Rs, Rd,and Rn.) Register field (3 bits specifying an address register or 32-bit register. The symbols ers, erd, ern, and erm correspond to operand symbols ERs, ERd, ERn, and ERm.) The register fields specify general registers as follows. Address Register 32-Bit Register 16-Bit Register Register Field 0000 0001 • • • 0111 1000 1001 • • • 1111 R0 R1 • • • R7 E0 E1 • • • E7 0000 0001 • • • 0111 1000 1001 • • • 1111 General Register Register Field 8-Bit Register General Register R0H R1H • • • R7H R0L R1L • • • R7L Register Field 000 001 • • • 111 ER0 ER1 • • • ER7 General Register Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1011 of 1220 REJ09B0186-0300O A.3 Table A.3 Operation Code Map (1) Instruction when most significant bit of BH is 0. Instruction code AH AL BH BL Instruction when most significant bit of BH is 1. 1st byte 2nd byte Appendix A Instruction Set AL AH 0 NOP Table A.3(2) OR MOV.B 3 4 BRA BCC RTS OR MOV XOR AND BST MOV Table A.3(2) BSR RTE TRAPA Table A.3(2) BCS BNE MULXU BSET 7 8 ADD ADDX CMP SUBX OR XOR AND MOV 9 A B C D E F Note: * Cannot be used in the H8S/2643 Group. BNOT BCLR BTST DIVXU MULXU DIVXU BRN BEQ BVC BVS BHI BLS 5 6 BIST BLD BOR BXOR BAND BILD BIOR BIXOR BIAND BPL JMP BMI BGE BSR XOR AND SUB Table A.3(2) ORC XORC ANDC LDC ADD 1 2 0 1 4 5 6 7 8 9 A B C 2 3 D MOV CMP E ADDX SUBX F Table A.3(2) Table A.3(2) Operation Code Map Table A.3 shows the operation code map. Rev. 3.00 Jan 11, 2005 page 1012 of 1220 REJ09B0186-0300O LDC Table STC * * A.3(2) STMAC LDMAC Table Table Table A.3(2) A.3(2) A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) BLT BGT JSR MOV Table A.3(3) Table A.3(2) Table A.3(2) EEPMOV BLE Table A.3 Operation Code Map (2) Instruction code AH AL BH BL 1st byte 2nd byte BH AH AL 01 MOV STM STC SLEEP INC ADDS INC INC ADDS DAA SHLL SHLL SHLR ROTXL ROTXR EXTU EXTU SHLR ROTXL ROTXR NOT DEC SUBS DEC DAS BRA MOV MOV MOV ADD CMP SUB ADD CMP SUB Table A.3(4) MOV OR OR Table * A.3(4) MOVFPE XOR XOR AND AND BRN BHI BLS BCC BCS BNE BEQ BVC MOV BVS BPL MOV BMI DEC SUBS NOT ROTXR ROTXL SHLR SHLL SHAL SHAR ROTL ROTR NEG NEG 0A 0B 0F 10 11 12 13 17 1A 1B 1F 58 6A 79 7A LDM LDC MAC* CLRMAC * 0 5 7 6 B 8 1 2 9 A 3 4 C Table A.3(3) ADD D Table A.3(3) E TAS F Table A.3(3) INC MOV SHAL SHAR ROTL ROTR EXTS SUB DEC CMP BGE MOVTPE* BLT BGT INC SHAL SHAR ROTL ROTR EXTS DEC BLE Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1013 of 1220 REJ09B0186-0300O Note: * Cannot be used in the H8S/2643 Group. Table A.3 Operation Code Map (3) Instruction code AH AL BH BL CH CL DH DL 1st byte 2nd byte 3rd byte 4th byte Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. Appendix A Instruction Set CL AH AL BH BL CH 0 MULXS DIVXS OR BTST BTST BSET BSET BTST BTST BSET BSET BNOT BCLR BNOT BCLR BNOT BCLR BNOT BCLR XOR AND DIVXS MULXS 1 2 3 4 5 6 7 8 9 A B C D E F 01C05 01D05 01F06 7Cr06 *1 7Cr07 *1 7Dr06 *1 7Dr07 7Eaa6 7Eaa7 7Faa6 *2 7Faa7 *2 Notes: 1. r is the register specification field. 2. aa is the absolute address specification. *2 *2 *1 BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST Rev. 3.00 Jan 11, 2005 page 1014 of 1220 REJ09B0186-0300O BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST Table A.3 Operation Code Map (4) Instruction code AH AL BH BL CH CL DH DL EH EL FH FL Instruction when most significant bit of FH is 0. Instruction when most significant bit of FH is 1. EL AHALBHBLCHCLDHDLEH 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 0 4 5 6 7 8 9 A BTST 1 2 3 B C D E F 6A10aaaa6* 6A10aaaa7* 6A18aaaa6* BSET 6A18aaaa7* BNOT BCLR BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST Instruction code AH AL BH BL CH CL DH DL 1st byte 2nd byte 3rd byte 4th byte 5th byte EH EL 6th byte FH FL 7th byte GH GL 8th byte HH HL Instruction when most significant bit of HH is 0. Instruction when most significant bit of HH is 1. GL AHALBHBL ... FHFLGH 0 4 BTST 1 2 3 5 6 7 8 9 A B C D E F 6A30aaaaaaaa6* 6A30aaaaaaaa7* 6A38aaaaaaaa6* BSET 6A38aaaaaaaa7* Note: * aa is the absolute address specification. BNOT BCLR BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1015 of 1220 REJ09B0186-0300O Appendix A Instruction Set A.4 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table A.5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A.4 indicates the number of states required for each cycle. The number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN Examples: Advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. BSET #0, @FFFFC7:8 From table A.5: I = L = 2, J = K = M = N = 0 From table A.4: SI = 4, SL = 2 Number of states required for execution = 2 × 4 + 2 × 2 = 12 2. JSR @@30 From table A.5: I = J = K = 2, L = M = N = 0 From table A.4: SI = SJ = SK = 4 Number of states required for execution = 2 × 4 + 2 × 4 + 2 × 4 = 24 Rev. 3.00 Jan 11, 2005 page 1016 of 1220 REJ09B0186-0300O Appendix A Instruction Set Table A.4 Number of States per Cycle Access Conditions On-Chip Supporting Module External Device 8-Bit Bus 16-Bit Bus Cycle Instruction fetch Stack operation Byte data access Word data access Internal operation SI SK SL SM SN On-Chip 8-Bit Memory Bus 1 4 16-Bit Bus 2 2-State 3-State 2-State 3-State Access Access Access Access 4 6 + 2m 2 3+m Branch address read SJ 2 4 1 1 1 2 4 1 3+m 6 + 2m 1 1 1 Legend: m: Number of wait states inserted into external device access Rev. 3.00 Jan 11, 2005 page 1017 of 1220 REJ09B0186-0300O Appendix A Instruction Set Table A.5 Number of Cycles in Instruction Execution Instruction Fetch Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Internal Operation N Instruction ADD Mnemonic ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd I 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 2 1 2 2 3 4 2 2 2 2 2 2 2 2 2 2 ADDS ADDX ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 1 1 1 1 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 Rev. 3.00 Jan 11, 2005 page 1018 of 1220 REJ09B0186-0300O Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Fetch Instruction Bcc Mnemonic BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 I 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3 4 1 2 2 3 4 Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 Rev. 3.00 Jan 11, 2005 page 1019 of 1220 REJ09B0186-0300O Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Fetch Instruction BIAND Mnemonic BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8 BIOR #xx:8,@aa:16 BIOR #xx:8,@aa:32 BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 1 1 1 1 1 1 1 1 Rev. 3.00 Jan 11, 2005 page 1020 of 1220 REJ09B0186-0300O Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Fetch Instruction BNOT Mnemonic BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR BSR d:8 BSR d:16 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 2 2 1 2 2 3 4 Internal Operation N 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 1 2 2 2 2 Rev. 3.00 Jan 11, 2005 page 1021 of 1220 REJ09B0186-0300O Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Fetch Instruction BTST Mnemonic BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CMP CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAS DEC DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 1*3 11 19 11 19 Rev. 3.00 Jan 11, 2005 page 1022 of 1220 REJ09B0186-0300O Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K L 2n + 2* 2 2 Instruction Fetch Instruction EEPMOV Mnemonic EEPMOV.B EEPMOV.W EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR I 2 2 1 1 1 1 1 1 1 2 2 2 2 2 2 1 2 1 1 2 2 3 3 5 5 2 2 3 3 4 4 Word Data Access M Internal Operation N 2n + 2* 1 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Rev. 3.00 Jan 11, 2005 page 1023 of 1220 REJ09B0186-0300O Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K 4 6 8 L Word Data Access M Instruction Fetch Instruction LDM * 5 Internal Operation N 1 1 1 1* 1* 3 3 Mnemonic LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) I 2 2 2 1 1 2 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 LDMAC LDMAC ERs,MACH LDMAC ERs,MACL MAC MOV MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Rev. 3.00 Jan 11, 2005 page 1024 of 1220 REJ09B0186-0300O Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M 1 1 1 1 1 1 Instruction Fetch Instruction MOV Mnemonic MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVTPE MULXS MOVFPE @:aa:16,Rd MOVTPE Rs,@:aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOP NOT.B Rd NOT.W Rd NOT.L ERd 2 2 1 1 1 1 1 1 1 1 1 I 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 Internal Operation N 2 2 2 2 2 2 2 2 2 2 2 2 1 1 Can not be used in the H8S/2643 Group 2*3 3* 3 3 2* 3*3 Rev. 3.00 Jan 11, 2005 page 1025 of 1220 REJ09B0186-0300O Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Fetch Instruction OR Mnemonic OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC ORC #xx:8,CCR ORC #xx:8,EXR POP POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd I 1 1 2 1 3 2 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Internal Operation N 1 2 1 2 1 1 1 1 Rev. 3.00 Jan 11, 2005 page 1026 of 1220 REJ09B0186-0300O Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Fetch Instruction ROTXR Mnemonic ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd RTE RTS SHAL RTE RTS SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP SLEEP I 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Internal Operation N 2/3*1 2 1 1 1 Rev. 3.00 Jan 11, 2005 page 1027 of 1220 REJ09B0186-0300O Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Fetch Instruction STC Mnemonic STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd I 1 1 2 2 Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 4 6 8 1 1 1 * 3 STC.W CCR,@(d:16,ERd) 3 STC.W EXR,@(d:16,ERd) 3 STC.W CCR,@(d:32,ERd) 5 STC.W EXR,@(d:32,ERd) 5 STC.W CCR,@-ERd STC.W EXR,@-ERd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM *5 STM.L (ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP STM.L (ERn-ERn+3), @-SP STMAC STMAC MACH,ERd STMAC MACL,ERd SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBX 4 2 2 3 3 4 4 2 2 2 1 1 1 2 1 3 1 1 1 1 2 2 2 2/3*1 2 1 1 *3 SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS* TAS @ERd TRAPA #x:2 TRAPA 2 Rev. 3.00 Jan 11, 2005 page 1028 of 1220 REJ09B0186-0300O Appendix A Instruction Set Branch Address Read J Byte Stack Data Operation Access K L Word Data Access M Instruction Fetch Instruction XOR Mnemonic XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC XORC #xx:8,CCR XORC #xx:8,EXR I 1 1 2 1 3 2 1 2 Internal Operation N Notes: 1. 2 when EXR is invalid, 3 when EXR is valid. 2. When n bytes of data are transferred. 3. An internal operation may require between 0 and 3 additional states, depending on the preceding instruction. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 5. Only register ER0 to ER6 should be used when using the STM/LDM instruction. Rev. 3.00 Jan 11, 2005 page 1029 of 1220 REJ09B0186-0300O Appendix A Instruction Set A.5 Bus States during Instruction Execution Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See table A.4 for the number of states per cycle. How to Read the Table: Order of execution Instruction JMP@aa:24 1 R:W 2nd 2 3 4 5 6 7 8 Internal operation, R:W EA 1 state End of instruction Read effective address (word-size read) No read or write Read 2nd word of current instruction (word-size read) Legend R:B R:W W:B W:W :M 2nd 3rd 4th 5th NEXT EA VEC Byte-size read Word-size read Byte-size write Word-size write Transfer of the bus is not performed immediately after this cycle Address of 2nd word (3rd and 4th bytes) Address of 3rd word (5th and 6th bytes) Address of 4th word (7th and 8th bytes) Address of 5th word (9th and 10th bytes) Address of next instruction Effective address Vector address Rev. 3.00 Jan 11, 2005 page 1030 of 1220 REJ09B0186-0300O Appendix A Instruction Set Figure A.1 shows timing waveforms for the address bus and the , , and signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. φ Address bus RD HWR, LWR High level R:W 2nd Fetching 3rd byte of instruction Fetching 4th byte of instruction Internal operation R:W EA Fetching 1nd byte of instruction at jump address Fetching 2nd byte of instruction at jump address Figure A.1 Address Bus, , , and Timing (8-Bit Bus, Three-State Access, No Wait States) Rev. 3.00 Jan 11, 2005 page 1031 of 1220 REJ09B0186-0300O RWL RWH DR RWL RWH DR Table A.6 Instruction Execution Cycles 2 3 4 5 6 7 8 9 R:W NEXT R:W 3rd R:W NEXT Appendix A Instruction Set R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W NEXT Rev. 3.00 Jan 11, 2005 page 1032 of 1220 REJ09B0186-0300O Instruction ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 1 R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT 3 R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA Instruction BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd 1 R:W NEXT R:W 2nd 2 R:W EA Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state R:B:M EA R:B:M EA R:W 3rd R:W:M NEXT W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA 4 5 6 7 8 9 Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1033 of 1220 REJ09B0186-0300O 2 R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1034 of 1220 REJ09B0186-0300O 3 R:W 4th 4 R:B:M EA 5 6 R:W:M NEXT W:B EA 7 8 9 R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT Instruction BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT 2 R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:W EA Internal operation, 1 state R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:W:M stack (H) R:W EA R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA W:W stack (L) W:W:M stack (H) W:W stack (L) R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA Instruction BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR d:8 BSR d:16 1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd 3 R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th 4 5 6 W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA 7 8 9 Rev. 3.00 Jan 11, 2005 page 1035 of 1220 REJ09B0186-0300O BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA Appendix A Instruction Set 2 R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd Internal operation, 1 state R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1036 of 1220 REJ09B0186-0300O Instruction BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC 1 R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT 3 4 5 R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT 6 7 8 9 R:W NEXT R:W 3rd R:W NEXT CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd R:W NEXT Internal operation, 11 states R:W NEXT Internal operation, 19 states Internal operation, 11 states Internal operation, 19 states R:B EAd*1 R:B EAs*2 W:B EAd*2 R:B EAs*1 R:B EAd*1 R:B EAs*2 W:B EAd*2 R:B EAs*1 ← Repeated n times*2 → R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Instruction INC.W #1/2,Rd INC.L #1/2,ERd JMP @ERn JMP @aa:24 JMP @@aa:8 JSR @ERn JSR @aa:24 R:W EA R:W NEXT R:W 2nd R:W NEXT Internal operation, R:W EA 1 state R:W EA W:W:M stack (H) W:W stack (L) Internal operation, R:W EA W:W:M stack (H) W:W stack (L) 1 state R:W:M aa:8 R:W aa:8 W:W:M stack (H) W:W stack (L) R:W NEXT R:W EA Internal operation, R:W EA 1 state R:W:M aa:8 R:W aa:8 1 R:W NEXT R:W NEXT R:W NEXT R:W 2nd 2 3 4 5 6 7 8 9 JSR @@aa:8 LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W NEXT R:W EA R:W EA R:W 5th R:W 5th R:W EA R:W NEXT R:W NEXT R:W EA R:W EA R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W:M stack (H)*3 R:W stack (L)*3 R:W:M stack (H)*3 R:W stack (L)*3 R:W:M stack (H)*3 R:W stack (L)*3 ←Repeated n times *3→ R:W EA R:W EA LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.L @SP+, (ERn–ERn+1)*9 LDM.L @SP+,(ERn–ERn+2)*9 R:W 2nd LDM.L @SP+,(ERn–ERn+3)*9 R:W 2nd LDMAC ERs,MACH R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W EA R:W EA R:W NEXT R:W NEXT R:W 4th R:W 4th Internal operation, 1 state R:W NEXT Internal operation, 1 state R:W 3rd R:W NEXT R:W 3rd R:W NEXT R:W 3rd R:W 4th R:W 3rd R:W 4th R:W:M NEXT Internal operation, 1 state R:W NEXT Internal operation, 1 state R:W NEXT Internal operation, 1 state Internal operation, 1 state R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1037 of 1220 REJ09B0186-0300O Instruction LDMAC ERs,MACL R:W EAm 1 R:W NEXT 2 3 Internal operation, 1 state R:W NEXT R:W EAh 4 5 6 7 8 9 Appendix A Instruction Set MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd R:B EA R:W 4th R:B EA R:W NEXT R:B EA R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:B EA R:W NEXT R:B EA Rev. 3.00 Jan 11, 2005 page 1038 of 1220 REJ09B0186-0300O MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@–ERd W:B EA R:W 4th W:B EA R:W NEXT W:B EA R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:B EA R:W NEXT R:W 3rd Internal operation, 1 state R:B EA R:W NEXT R:W 3rd W:B EA R:W NEXT R:W 3rd Internal operation, 1 state W:B EA R:W NEXT R:W 3rd R:W NEXT W:B EA R:W NEXT W:B EA MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+, Rd R:W EA R:W 4th R:W EA R:W EA R:W NEXT R:W NEXT R:W EA R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:B EA MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@–ERd W:W EA R:E 4th W:W EA W:W EA R:W NEXT MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W EA R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd W:W EA R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd W:W EA R:W NEXT W:W EA 2 R:W 3rd 3 R:W NEXT 4 5 6 7 8 9 Instruction MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd R:W:M NEXT R:W:M 3rd R:W:M 3rd R:W:M NEXT R:W EA+2 R:W NEXT R:W EA+2 R:W:M EA R:W EA+2 R:W EA+2 R:W:M EA R:W EA+2 R:W EA+2 R:W:M EA R:W 5th R:W:M EA 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@–ERd W:W EA+2 R:W NEXT W:W EA+2 W:W:M EA W:W EA+2 W:W:M EA W:W EA+2 W:W:M EA R:W NEXT R:W:M EA R:W NEXT W:W EA+2 W:W:M EA R:W 5th W:W:M EA R:W:M EA R:W NEXT R:W:M 4th Internal operation, 1 state R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W 4th R:W 2nd R:W:M NEXT W:W:M EA R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W:M 4th R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W 4th Cannot be used in the H8S/2643 Group W:W EA+2 R:W NEXT Internal operation, 2 states R:W NEXT Internal operation, 3 states Internal operation, 2 states Internal operation, 3 states R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W NEXT MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1039 of 1220 REJ09B0186-0300O Instruction POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn R:W 2nd W:W EA+2 R:W NEXT R:W 2nd R:W EA+2 Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1040 of 1220 REJ09B0186-0300O 1 R:W NEXT 2 3 4 Internal operation, R:W EA 1 state R:W:M NEXT Internal operation, R:W:M EA 1 state Internal operation, W:W EA 1 state R:W:M NEXT Internal operation, W:W:M EA 1 state 5 6 7 8 9 ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd RTE R:W stack (EXR) R:W:M stack (H) R:W stack (H) R:W stack (L) 1 state R:W stack (L) RTS SHAL.B Rd R:W NEXT R:W NEXT Internal operation, R:W*4 1 state Internal operation, R:W*4 R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT 2 3 4 5 6 7 8 9 Internal operation:M Instruction SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@–ERd R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W NEXT W:W EA W:W EA R:W 5th R:W 5th W:W EA 1 R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT W:W EA W:W EA STC EXR,@–ERd STC CCR,@aa:16 STC EXR,@aa:16 R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 3rd R:W 3rd Rev. 3.00 Jan 11, 2005 page 1041 of 1220 REJ09B0186-0300O W:W EA W:W EA R:W NEXT R:W NEXT R:W 4th R:W 4th Internal operation, 1 state Internal operation, 1 state R:W NEXT R:W NEXT W:W EA W:W EA W:W EA Appendix A Instruction Set 1 Instruction STC CCR,@aa:32 R:W 2nd STC EXR,@aa:32 R:W 2nd STM.L(ERn–ERn+1),@–SP*9 R:W 2nd STM.L(ERn–ERn+2),@–SP*9 R:W 2nd STM.L(ERn–ERn+3),@–SP*9 R:W 2nd W:W:M stack (H)*3 W:W stack (L)*3 W:W:M stack (H)*3 W:W stack (L)*3 Appendix A Instruction Set 2 3 R:W 3rd R:W 4th R:W 3rd R:W 4th R:W:M NEXT Internal operation, 1 state R:W:M NEXT Internal operation, 1 state R:W:M NEXT Internal operation, 1 state 4 5 R:W NEXT W:W EA R:W NEXT W:W EA W:W:M stack (H)*3 W:W stack (L)*3 6 7 8 9 R:W NEXT R:W 3rd R:W NEXT Rev. 3.00 Jan 11, 2005 page 1042 of 1220 REJ09B0186-0300O STMAC MACH,ERd STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd*8 TRAPA #x:2 R:W NEXT R:B:M EA Internal operation, W:W stack (L) 1 state W:B EA W:W stack (H) W:W stack (EXR) R:W:M VEC R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W VEC+2 Internal operation, R:W*7 1 state R:W NEXT R:W 3rd R:W NEXT R:W NEXT XOR.B #xx8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC #xx:8,CCR XORC #xx:8,EXR R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT Instruction Reset exception handling Interrupt exception handling R:W*6 W:W stack (EXR) R:W:M VEC R:W VEC+2 1 R:W VEC 2 R:W VEC+2 3 4 Internal operation, R:W*5 1 state Internal operation, W:W stack (L) W:W stack (H) 1 state 5 6 7 8 9 Internal operation, R:W*7 1 state Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. EAs is the contents of ER5. EAd is the contents of ER6. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these bus cycles are not executed. Repeated two times to save or restore two registers, three times for three registers, or four times for four registers. Start address after return. Start address of the program. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read operation is replaced by an internal operation. Start address of the interrupt-handling routine. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Only register ER0 to ER6 should be used when using the STM/LDM instruction. Appendix A Instruction Set Rev. 3.00 Jan 11, 2005 page 1043 of 1220 REJ09B0186-0300O Appendix A Instruction Set A.6 Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below. m= 31 for longword operands 15 for word operands 7 for byte operands Si Di Ri Dn — The i-th bit of the source operand The i-th bit of the destination operand The i-th bit of the result The specified bit in the destination operand Not affected Modified according to the result of the instruction (see definition) 0 1 * Z' C' Always cleared to 0 Always set to 1 Undetermined (no guaranteed value) Z flag before instruction execution C flag before instruction execution Rev. 3.00 Jan 11, 2005 page 1044 of 1220 REJ09B0186-0300O Appendix A Instruction Set Table A.7 Instruction ADD Condition Code Modification H N Z V C Definition N = Rm Z= · · ...... · + V = Sm · Dm · · · Rm C = Sm · Dm + Dm · ADDS ADDX ————— + Sm · N = Rm V = Sm · Dm · AND ANDC BAND Bcc BCLR BIAND BILD BIOR BIST BIXOR BLD BNOT BOR BSET BSR BST BTST BXOR CLRMAC ———— ————— ————— ———— ———— ————— ———— ———— ————— ———— ————— ————— ————— ———— ————— C = C' · —— —— Z= C = C' + Dn C = Dn C= ———— C = C' · — 0 — N = Rm Z= · C = Sm · Dm + Dm · Stores the corresponding bits of the result. No flags change when the operand is EXR. C = C' · Dn 'C nD + nD 'C C = C' · Dn + nD C = C' + mR mR mD mS mR 0R · · Dn Rev. 3.00 Jan 11, 2005 page 1045 of 1220 REJ09B0186-0300O 0R 1–mR mR mR Z = Z' · · ...... · + · · Rm + Sm · · ...... · 4–mR 4–mR H = Sm–4 · Dm–4 + Dm–4 · + Sm–4 · 4–mR mR mR mD mS mR 0R 1–mR mR nD nD nD 4–mR H = Sm–4 · Dm–4 + Dm–4 · + Sm–4 · Appendix A Instruction Set Instruction CMP H N Z V C Definition N = Rm Z= V= DAA * * · C = Sm · N = Rm Z= DAS * * · + · Rm + Sm · Rm C: decimal arithmetic carry N = Rm C: decimal arithmetic borrow DEC — — N = Rm V = Dm · DIVXS DIVXU EEPMOV EXTS EXTU INC — — —— —— N = Sm · Z= Z= ————— — —0 — 0 0 — — — Z= Z= Z= V= JMP JSR LDC LDM LDMAC MAC ————— ————— ————— ————— ————— Stores the corresponding bits of the result. No flags change when the operand is EXR. · · N = Sm Z= · · ...... · Z= · · ...... · + · Dm N = Rm · N = Rm · Rm Rev. 3.00 Jan 11, 2005 page 1046 of 1220 REJ09B0186-0300O 0R mD 1–mR mR · · ...... · 0R 0R 1–mR mR 1–mR mR · · ...... · · ...... · 0S · ...... · 0S · ...... · 0R · ...... · mD · Dm · 4–mD 4–mD + Sm · H = Sm–4 · + · Rm–4 + Sm–4 · Rm–4 0R · ...... · 0R 0R mD mD mR mS 1–mR mR 1–mS mS · Rm 1–mS mS mS mD mR 1–mR mR 1–mR mR 1–mR mR Appendix A Instruction Set Instruction MOV MOVFPE MOVTPE MULXS MULXU NEG — —— N = R2m Z= ————— · · ...... · H — N Z V 0 C — Definition N = Rm Can not be used in H8S/2643 Group Z= · · ...... · H = Dm–4 + Rm–4 N = Rm V = Dm · Rm Z= · · ...... · C = Dm + Rm NOP NOT OR ORC POP PUSH ROTL — — — 0 0 0 — — ————— — — 0 0 — — N = Rm N = Rm Z= Z= · · · ...... · · ...... · Stores the corresponding bits of the result. No flags change when the operand is EXR. N = Rm N = Rm Z= Z= N = Rm Z= · · · ...... · · ...... · · ...... · C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTR — 0 N = Rm C = D0 (1-bit shift) or C = D1 (2-bit shift) Z= · · ...... · Rev. 3.00 Jan 11, 2005 page 1047 of 1220 REJ09B0186-0300O 0R 0R 1–mR mR · 0R 0R 0R 0R 0R 0R 0R 1–m2R m2R 1–mR mR 1–mR mR 1–mR mR 1–mR mR 1–mR mR 1–mR mR 1–mR mR Appendix A Instruction Set Instruction ROTXL H — N Z V 0 C Definition N = Rm C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTXR — 0 N = Rm C = D0 (1-bit shift) or C = D1 (2-bit shift) RTE RTS SHAL ————— — N = Rm V = Dm · Dm–1 + Z= · · ...... · Stores the corresponding bits of the result. Z= · · ...... · Z= · · ...... · V = Dm · Dm–1 · Dm–2 · SHAR — 0 N = Rm C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) Z= SHLL — 0 · · ...... · C = D0 (1-bit shift) or C = D1 (2-bit shift) N = Rm C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) SHLR —0 0 N = Rm C = D0 (1-bit shift) or C = D1 (2-bit shift) SLEEP STC STM STMAC ————— ————— ————— — — N = 1 if MAC instruction resulted in negative value in MAC register Z = 1 if MAC instruction resulted in zero value in MAC register V = 1 if MAC instruction resulted in overflow Z= · · ...... · Z= · · ...... · Rev. 3.00 Jan 11, 2005 page 1048 of 1220 REJ09B0186-0300O 2–mD 1–mD mD 1–mD mD 0R 1–mR mR · 0R 0R 0R 0R 0R 1–mR mR 1–mR mR 1–mR mR 1–mR mR 1–mR mR (1-bit shift) · · (2-bit shift) Appendix A Instruction Set Instruction SUB H N Z V C Definition N = Rm Z= V= SUBS SUBX ————— · C = Sm · + · Rm + Sm · Rm · Rm–4 + Sm–4 · Rm–4 N = Rm V= TAS TRAPA XOR XORC — 0 — C = Sm · N = Dm Z= ————— — 0 — Z= · + · Rm + Sm · Rm N = Rm Stores the corresponding bits of the result. No flags change when the operand is EXR. Rev. 3.00 Jan 11, 2005 page 1049 of 1220 REJ09B0186-0300O 0R 1–mR mR · · ...... · 0D · ...... · mD mD mD mR mS · Dm · 0R 1–mD mD mR Z = Z' · · ...... · 4–mD 4–mD H = Sm–4 · + + Sm · mD · Dm · 4–mD 4–mD + Sm · H = Sm–4 · + · Rm–4 + Sm–4 · Rm–4 0R · ...... · mD mD mR mS 1–mR mR · Rm · Rm Appendix B Internal I/O Register Appendix B Internal I/O Register B.1 Addresses Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width (bits) Register Address Name H'FDAC DADR2 H'FDAD DADR3 H'FDAE DACR23 H'FDB0 IrCR H'FDB4 SCRX D/A2, D/A3 8 DAOE1 IrE — DAOE0 IrCKS2 IICX1 — DA12/ PWME DA4 DA12/ DA4/ DA12/ PWME DA4 DA12/ DA4/ CMIEA CMIEA CMFA CMFA DAE IrCKS1 IICX0 — — IrCKS0 IICE — — — FLSHE CLR3 — — — CLR2 DA8/ OEA DA0 DA8/ DA0/ DA8/ OEA DA0 DA8/ DA0/ CKS2 CKS2 OS2 OS2 — — — CLR1 — — — CLR0 SCI0, IrDA IIC H'FDB5 DDCSWR — H'FDB8 DADRAH0/ DA13/ DACR0 TEST H'FDB9 DADRAL0 DA5 H'FDBA DADRBH0/ DA13/ DACNTH0 H'FDBB DADRBL0/ DA5/ DACNTL0 H'FDBC DADRAH1/ DA13/ DACR1 TEST H'FDBD DADRAL1 DA5 H'FDBE DADRBH1/ DA13/ DACNTH1 H'FDBF DADRBL1/ DA5/ DACNTL1 H'FDC0 TCR2 H'FDC1 TCR3 H'FDC2 TCSR2 H'FDC3 TCSR3 H'FDC4 TCORA2 H'FDC5 TCORA3 H'FDC6 TCORB2 H'FDC7 TCORB3 H'FDC8 TCNT2 H'FDC9 TCNT3 CMIEB CMIEB CMFB CMFB DA11/— DA10/— DA9/ OEB DA3 DA11/ DA3/ DA2 DA10/ DA2/ DA1 DA9/ DA1/ DA7/OS DA6/CKS PWM0 CFS DA7/ CFS/ — DA6/ REGS DA11/— DA10/— DA9/ OEB DA3 DA11/ DA3/ OVIE OVIE OVF OVF DA2 DA10/ DA2/ CCLR1 CCLR1 — — DA1 DA9/ DA1/ CCLR0 CCLR0 OS3 OS3 DA7/OS DA6/CKS PWM1 CFS DA7/ CFS/ CKS1 CKS1 OS1 OS1 — DA6/ REGS CKS0 CKS0 OS0 OS0 TMR2, TMR3 16 H'FDD1 BRR3 H'FDD2 SCR3 H'FDD3 TDR3 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Rev. 3.00 Jan 11, 2005 page 1050 of 1220 REJ09B0186-0300O E SMR3 GM BLK PE O/ E A H'FDD0 SMR3 C/ CHR PE O/ STOP BCP1 MP BCP0 CKS1 CKS1 CKS0 CKS0 SCI3, 8 Smart card interface Appendix B Internal I/O Register Register Address Name H'FDD4 SSR3 SSR3 H'FDD5 RDR3 H'FDD6 SCMR3 H'FDD8 SMR4 SMR4 H'FDD9 BRR4 H'FDDA SCR4 H'FDDB TDR4 H'FDDC SSR4 SSR4 H'FDDD RDR4 H'FDDE SCMR4 H'FDE4 SBYCR H'FDE5 SYSCR H'FDE6 SCKCR H'FDE7 MDCR — SSBY MACS PSTOP — — STS2 — — — — SYS1 INTM1 — — — STS0 INTM0 — — SDIR OPE NMIEG STCS — SINV — — — SMIF — RAME SCK0 MDS0 System TDRE TDRE RDRF RDRF ORER ORER FER ERS PER PER TEND TEND MPB MPB MPBT MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 — — CHR BLK — PE PE — SDIR STOP BCP1 SINV MP BCP0 — CKS1 CKS1 SMIF CKS0 CKS0 SCI4, Smart card interface Module Name Data Bus Width (bits) Bit 7 TDRE TDRE Bit 6 RDRF RDRF Bit 5 ORER ORER Bit 4 FER ERS Bit 3 PER PER Bit 2 TEND TEND Bit 1 MPB MPB Bit 0 MPBT MPBT SCI3, 8 Smart card interface GM O/ H'FDE8 MSTPCRA MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 H'FDE9 MSTPCRB MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 H'FDEA MSTPCRC MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 H'FDEB PFCR CSS07 CSS36 LSON — BAA22 BAA14 BAA6 — BAA22 BAA14 BAA6 CDA CDB BUZZE NESEL — BAA21 BAA13 BAA5 — BAA21 BAA13 BAA5 LCASS AE3 AE2 — — BAA18 BAA10 BAA2 — BAA18 BAA10 BAA2 AE1 STC1 — BAA17 BAA9 BAA1 — BAA17 BAA9 BAA1 AE0 STC0 — BAA16 BAA8 BAA0 — BAA16 BAA8 BAA0 PBC H'FDEC LPWRCR DTON H'FE00 BARA H'FE01 H'FE02 H'FE03 H'FE04 BARB H'FE05 H'FE06 H'FE07 H'FE08 BCRA H'FE09 BCRB H'FE12 ISCRH H'FE13 ISCRL H'FE14 IER H'FE15 ISR — BAA23 BAA15 BAA7 — BAA23 BAA15 BAA7 CMFA CMFB SUBSTP RFCUT — BAA20 BAA12 BAA4 — BAA20 BAA12 BAA4 — BAA19 BAA11 BAA3 — BAA19 BAA11 BAA3 BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 BIEA BAMRB2 BAMRB1 BAMRB0 CSELB1 CSELB0 BIEB IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Interrupt IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA controller IRQ7E IRQ7F IRQ6E IRQ6F IRQ5E IRQ5F IRQ4E IRQ4F IRQ3E IRQ3F IRQ2E IRQ2F IRQ1E IRQ1F IRQ0E IRQ0F E E A C/ O/ MRESE — SCK2 MDS2 SCK1 MDS1 Rev. 3.00 Jan 11, 2005 page 1051 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register Register Address Name H'FE16 DTCERA H'FE17 DTCERB H'FE18 DTCERC H'FE19 DTCERD H'FE1A DTCERE H'FE1B DTCERF H'FE1E DTCERI H'FE1F DTVECR H'FE26 PCR H'FE27 PMR H'FE28 NDERH H'FE29 NDERL H'FE2A PODRH H'FE2B PODRL H'FE2C NDRH H'FE2D NDRL H'FE2E NDRH H'FE2F NDRL H'FE30 P1DDR H'FE31 P2DDR H'FE32 P3DDR H'FE34 P5DDR H'FE36 P7DDR H'FE37 P8DDR H'FE39 PADDR H'FE3A PBDDR H'FE3B PCDDR H'FE3C PDDDR H'FE3D PEDDR H'FE3E PFDDR H'FE3F PGDDR H'FE40 PAPCR H'FE41 PBPCR H'FE42 PCPCR H'FE43 PDPCR H'FE44 PEPCR H'FE46 P3ODR Module Name DTC Data Bus Width (bits) 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 DTCED7 DTCED6 DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0 DTCEE7 DTCEE6 DTCEE5 DTCEE4 DTCEE3 DTCEE2 DTCEE1 DTCEE0 DTCEF7 DTCEF6 DTCEF5 DTCEF4 DTCEF3 DTCEF2 DTCEF1 DTCEF0 DTCEI7 DTCEI6 DTCEI5 DTCEI4 DTCEI3 DTCEI2 DTCEI1 DTCEI0 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 PPG G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV NDER8 NDER0 POD8 POD0 NDR8 NDR0 NDR8 NDR0 Port NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER7 POD15 POD7 NDR15 NDR7 — — NDER6 POD14 POD6 NDR14 NDR6 — — NDER5 POD13 POD5 NDR13 NDR5 — — NDER4 POD12 POD4 NDR12 NDR4 — — NDER3 POD11 POD3 NDR11 NDR3 NDR11 NDR3 NDER2 POD10 POD2 NDR10 NDR2 NDR10 NDR2 NDER1 POD9 POD1 NDR9 NDR1 NDR9 NDR1 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR — — — — — P52DDR P51DDR P50DDR P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR — P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR — — — PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR P37ODR P36ODR P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR Rev. 3.00 Jan 11, 2005 page 1052 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register Register Address Name H'FE47 PAODR H'FE48 PBODR H'FE49 PCODR H'FE80 TCR3 H'FE81 TMDR3 H'FE82 TIOR3H H'FE83 TIOR3L H'FE84 TIER3 H'FE85 TSR3 H'FE86 TCNT3 H'FE87 H'FE88 TGR3A H'FE89 H'FE8A TGR3B H'FE8B H'FE8C TGR3C H'FE8D H'FE8E TGR3D H'FE8F H'FE90 TCR4 H'FE91 TMDR4 H'FE92 TIOR4 H'FE94 TIER4 H'FE95 TSR4 H'FE96 TCNT4 H'FE97 H'FE98 TGR4A H'FE99 H'FE9A TGR4B H'FE9B H'FEA0 TCR5 H'FEA1 TMDR5 H'FEA2 TIOR5 H'FEA4 TIER5 H'FEA5 TSR5 H'FEA6 TCNT5 H'FEA7 — — IOB3 TTGE TCFD CCLR1 — IOB2 — — CCLR0 — IOB1 TCIEU TCFU CKEG1 — IOB0 TCIEV TCFV CKEG0 MD3 IOA3 — — TPSC2 MD2 IOA2 — — TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU5 — — IOB3 TTGE TCFD CCLR1 — IOB2 — — CCLR0 — IOB1 TCIEU TCFU CKEG1 — IOB0 TCIEV TCFV CKEG0 MD3 IOA3 — — TPSC2 MD2 IOA2 — — TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU4 Module Name Data Bus Width (bits) 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Port PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR CCLR2 — IOB3 IOD3 TTGE — CCLR1 — IOB2 IOD2 — — CCLR0 BFB IOB1 IOD1 — — CKEG1 BFA IOB0 IOD0 TCIEV TCFV CKEG0 MD3 IOA3 IOC3 TGIED TGFD TPSC2 MD2 IOA2 IOC2 TGIEC TGFC TPSC1 MD1 IOA1 IOC1 TGIEB TGFB TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TPU3 16 Rev. 3.00 Jan 11, 2005 page 1053 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register Register Address Name H'FEA8 TGR5A H'FEA9 H'FEAA TGR5B H'FEAB H'FEB0 TSTR H'FEB1 TSYR H'FEC0 IPRA H'FEC1 IPRB H'FEC2 IPRC H'FEC3 IPRD H'FEC4 IPRE H'FEC5 IPRF H'FEC6 IPRG H'FEC7 IPRH H'FEC8 IPRI H'FEC9 IPRJ H'FECA IPRK H'FECB IPRL H'FECE IPRO H'FED0 ABWCR H'FED1 ASTCR H'FED2 WCRH H'FED3 WCRL H'FED4 BCRH H'FED5 BCRL H'FED6 MCR — — — — — — — — — — — — — — — ABW7 AST7 W71 W31 ICIS1 BRLE TPC — — IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 ABW6 AST6 W70 W30 ICIS0 CST5 SYNC5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 ABW5 AST5 W61 W21 CST4 SYNC4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 ABW4 AST4 W60 W20 CST3 SYNC3 — — — — — — — — — — — — — ABW3 AST3 W51 W11 CST2 SYNC2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 ABW2 AST2 W50 W10 CST1 SYNC1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 ABW1 AST1 W41 W01 RMTS1 WDBE RLW1 CKS1 CST0 SYNC0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 ABW0 AST0 W40 W00 RMST0 WAITE RLW0 CKS0 Bus controller Interrupt controller 8 TPU Module Name TPU5 Data Bus Width (bits) 16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BRSTRM BRSTS1 BRSTS0 RMTS2 OES CW2 DDS MXC1 CMIE RCTS MXC0 CKS2 BREQOE — BE CBRM RCDM H'FED7 DRAMCR RFSHE H'FED8 RTCNT H'FED9 RTCOR H'FEDB RAMER H'FEE0 MAR0AH H'FEE1 H'FEE2 MAR0AL H'FEE3 H'FEE4 IOAR0A H'FEE5 — — RMODE CMF — — — — — — RAMS — RAM2 — RAM1 — RAM0 — FLASH DMAC 16 Rev. 3.00 Jan 11, 2005 page 1054 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register Register Address Name H'FEE6 ETCR0A H'FEE7 H'FEE8 MAR0BH H'FEE9 H'FEEA MAR0BL H'FEEB H'FEEC IOAR0B H'FEED H'FEEE ETCR0B H'FEEF H'FEF0 MAR1AH H'FEF1 H'FEF2 MAR1AL H'FEF3 H'FEF4 IOAR1A H'FEF5 H'FEF6 ETCR1A H'FEF7 H'FEF8 MAR1BH H'FEF9 H'FEFA MAR1BL H'FEFB H'FEFC IOAR1B H'FEFD H'FEFE ETCR1B H'FEFF H'FF00 H'FF01 H'FF02 H'FF04 H'FF05 H'FF06 H'FF07 H'FF09 P1DR P2DR P3DR P5DR — P7DR P8DR PADR P17DR P27DR P37DR — — P77DR — PA7DR PB7DR PC7DR PD7DR P16DR P26DR P36DR — — P76DR P86DR PA6DR PB6DR PC6DR PD6DR P15DR P25DR P35DR — — P75DR P85DR PA5DR PB5DR PC5DR PD5DR P14DR P24DR P34DR — — P74DR P84DR PA4DR PB4DR PC4DR PD4DR P13DR P23DR P33DR — — P73DR P83DR PA3DR PB3DR PC3DR PD3DR P12DR P22DR P32DR P52DR — P72DR P82DR PA2DR PB2DR PC2DR PD2DR P11DR P21DR P31DR P51DR — P71DR P81DR PA1DR PB1DR PC1DR PD1DR P10DR P20DR P30DR P50DR — P70DR P80DR PA0DR PB0DR PC0DR PD0DR Port 8 — — — — — — — — — — — — — — — — — — — — — — — — Module Name DMAC Data Bus Width (bits) 16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FF0A PBDR H'FF0B PCDR H'FF0C PDDR Rev. 3.00 Jan 11, 2005 page 1055 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register Register Address Name H'FF0D PEDR H'FF0E PFDR H'FF0F PGDR H'FF10 H'FF11 H'FF12 H'FF13 H'FF14 H'FF15 H'FF16 H'FF17 H'FF18 H'FF19 H'FF1A TGR0B H'FF1B H'FF1C TGR0C H'FF1D H'FF1E TGR0D H'FF1F H'FF20 H'FF21 H'FF22 H'FF24 H'FF25 H'FF26 H'FF27 H'FF28 H'FF29 H'FF2A TGR1B H'FF2B H'FF30 H'FF31 H'FF32 H'FF34 H'FF35 TCR2 TMDR2 TIOR2 TIER2 TSR2 — — IOB3 TTGE TCFD CCLR1 — IOB2 — — CCLR0 — IOB1 TCIEU TCFU CKEG1 — IOB0 TCIEV TCFV CKEG0 MD3 IOA3 — — TPSC2 MD2 IOA2 — — TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU2 TGR1A TCR1 TMDR1 TIOR1 TIER1 TSR1 TCNT1 — — IOB3 TTGE TCFD CCLR1 — IOB2 — — CCLR0 — IOB1 TCIEU TCFU CKEG1 — IOB0 TCIEV TCFV CKEG0 MD3 IOA3 — — TPSC2 MD2 IOA2 — — TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU1 TGR0A TCR0 TMDR0 TIOR0H TIOR0L TIER0 TSR0 TCNT0 Module Name Port Data Bus Width (bits) 8 Bit 7 PE7DR PF7DR — CCLR2 — IOB3 IOD3 TTGE — Bit 6 PE6DR PF6DR — CCLR1 — IOB2 IOD2 — — Bit 5 PE5DR PF5DR — CCLR0 BFB IOB1 IOD1 — — Bit 4 PE4DR PF4DR Bit 3 PE3DR PF3DR Bit 2 PE2DR PF2DR Bit 1 PE1DR PF1DR Bit 0 PE0DR PF0DR PG4DR PG3DR PG2DR PG1DR PG0DR CKEG1 BFA IOB0 IOD0 TCIEV TCFV CKEG0 MD3 IOA3 IOC3 TGIED TGFD TPSC2 MD2 IOA2 IOC2 TGIEC TGFC TPSC1 MD1 IOA1 IOC1 TGIEB TGFB TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TPU0 16 Rev. 3.00 Jan 11, 2005 page 1056 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register Register Address Name H'FF36 H'FF37 H'FF38 H'FF39 H'FF3A TGR2B H'FF3B H'FF60 H'FF61 H'FF62 H'FF63 H'FF64 H'FF65 H'FF66 H'FF67 H'FF68 H'FF69 DMAWER — DMATCR — DMACR0A DTSZ DMACR0B DTSZ DMACR1A DTSZ DMACR1B DTSZ DMABCRH FAE1 DMABCRL DTE1B TCR0 TCR1 CMIEB CMIEB CMFB CMFB — — DTID DTID DTID DTID FAE0 DTE1A CMIEA CMIEA CMFA CMFA — TEE1 RPE RPE RPE RPE SAE1 DTE0B OVIE OVIE OVF OVF — TEE0 DTDIR DTDIR DTDIR DTDIR SAE0 DTE0A CCLR1 CCLR1 ADTE — WE1B — DTF3 DTF3 DTF3 DTF3 DTA1B WE1A — DTF2 DTF2 DTF2 DTF2 DTA1A WE0B — DTF1 DTF1 DTF1 DTF1 DTA0B WE0A — DTF0 DTF0 DTF0 DTF0 DTA0A 16 DMAC 8 TGR2A TCNT2 Module Name TPU2 Data Bus Width (bits) 16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DTIE1B DTIE1A DTIE0B DTIE0A CCLR0 CCLR0 OS3 OS3 CKS2 CKS2 OS2 OS2 CKS1 CKS1 OS1 OS1 CKS0 CKS0 OS0 OS0 TMR0, TMR1 H'FF6A TCSR0 H'FF6B TCSR1 H'FF6C TCORA0 H'FF6D TCORA1 H'FF6E TCORB0 H'FF6F TCORB1 H'FF70 H'FF71 H'FF74 (write) H'FF75 (read) H'FF76 (write) H'FF77 (read) RSTCSR RSTCSR TCNT0 TCNT1 TCNT0 TCNT0 WOVF RSTE WOVF RSTE ICCR0 ICE IEIC MST TRS E SMR0 GM BLK PE O/ E A H'FF78 SMR0 C/ CHR TI TCSR0/ OVF WT/ TME — — CKS2 CKS1 CKS0 WDT0 RSTS — — — — — RSTS — — — — — PE O/ STOP BCP1 ACKE MP BCP0 BBSY CKS1 CKS1 IRIC CKS0 CKS0 SCP SCI0, IIC0, 8 Smart card interface Rev. 3.00 Jan 11, 2005 page 1057 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register Register Address Name H'FF79 BRR0 ICSR0 H'FF7A SCR0 H'FF7B TDR0 H'FF7C SSR0 SSR0 H'FF7D RDR0 H'FF7E SCMR0 ICDR0/ SARX0 H'FF7F ICMR0/ SAR0 H'FF80 SMR1 SMR1 ICCR1 H'FF81 BRR1 ICSR1 H'FF82 H'FF83 H'FF84 SCR1 TDR1 SSR1 SSR1 H'FF85 H'FF86 RDR1 SCMR1 ICDR1/ SARX1 H'FF87 ICMR1/ SAR1 H'FF88 SMR2 SMR2 H'FF89 BRR2 TIE RIE TE RE MPIE TEIE CKE1 CKE0 — ICDR7/ — ICDR6/ — ICDR5/ — ICDR4/ SDIR ICDR3/ SINV ICDR2/ — ICDR1/ SMIF ICDR0/ TDRE TDRE RDRF RDRF ORER ORER FER ERS PER PER TEND TEND MPB MPB MPBT MPBT ESTP TIE STOP RIE IRTR TE AASX RE AL MPIE AAS TEIE ADZ CKE1 ACKB CKE0 — ICDR7/ SVAX6 MLS/ SVA6 — ICDR6/ SVAX5 WAIT/ SVA5 CHR BLK IEIC — ICDR5/ SVAX4 CKS2/ SVA4 PE PE MST — ICDR4/ SVAX3 CKS1/ SVA3 SDIR ICDR3/ SVAX2 CKS0/ SVA2 STOP BCP1 ACKE SINV ICDR2/ SVAX1 BC2/ SVA1 MP BCP0 BBSY — ICDR1/ SVAX0 BC1/ SVA0 CKS1 CKS1 IRIC SMIF ICDR0/ FSX BC0/ FS CKS0 CKS0 SCP SCI1, IIC1, Smart card interface TDRE TDRE RDRF RDRF ORER ORER FER ERS PER PER TEND TEND MPB MPB MPBT MPBT ESTP TIE STOP RIE IRTR TE AASX RE AL MPIE AAS TEIE ADZ CKE1 ACKB CKE0 Module Name Data Bus Width (bits) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCI0, IIC0, 8 Smart card interface ICE TRS SVARX6 SVARX5 SVARX4 SVARX3 SVARX2 SVARX1 SVARX0 FSX MLS/ SVA6 WAIT/ SVA5 CHR BLK CKS2/ SVA4 PE PE CKS1/ SVA3 CKS0/ SVA2 STOP BCP1 BC2/ SVA1 MP BCP0 BC1/ SVA0 CKS1 CKS1 BC0/ FS CKS0 CKS0 SCI2, Smart card interface IIC1 H'FF8A SCR2 H'FF8B TDR2 Rev. 3.00 Jan 11, 2005 page 1058 of 1220 REJ09B0186-0300O E GM O/ E A C/ O/ E GM O/ E A C/ O/ Appendix B Internal I/O Register Register Address Name H'FF8C SSR2 SSR2 H'FF8D RDR2 H'FF8E SCMR2 H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 ADDRAH ADDRAL ADDRBH ADDRBL — AD9 AD1 AD9 AD1 — AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE TRGS0 — AD7 — AD7 — AD7 — AD7 — ADST — TME — AD6 — AD6 — AD6 — AD6 — SCAN — PSS SDIR AD5 — AD5 — AD5 — AD5 — CH3 CKS1 RST/ SINV AD4 — AD4 — AD4 — AD4 — CH2 CKS0 CKS2 — AD3 — AD3 — AD3 — AD3 — CH1 — CKS1 SMIF AD2 — AD2 — AD2 — AD2 — CH0 — CKS0 WDT1 16 A/D Module Name SCI2, Smart card interface Data Bus Width (bits) 8 Bit 7 TDRE TDRE Bit 6 RDRF RDRF Bit 5 ORER ORER Bit 4 FER FER Bit 3 PER PER Bit 2 TEND TEND Bit 1 MPB MPB Bit 0 MPBT MPBT ADDRCH AD9 ADDRCL AD1 ADDRDH AD9 ADDRDL ADCSR ADCR AD1 ADF TRGS1 OVF H'FFA3 TCNT1 (read) H'FFA4 DADR0 H'FFA5 DADR1 H'FFA6 DACR01 H'FFA8 FLMCR1 H'FFA9 FLMCR2 H'FFAA EBR1 H'FFAB EBR2 H'FFAC FLPWCR H'FFB0 PORT1 H'FFB1 PORT2 H'FFB2 PORT3 H'FFB3 PORT4 H'FFB4 PORT5 H'FFB6 PORT7 H'FFB7 PORT8 H'FFB8 PORT9 DAOE1 FWE FLER EB7 — DAOE0 SWE1 — EB6 — DAE ESU1 — EB5 — — P15 P25 P35 P45 — P75 P85 P95 — PSU1 — EB4 — — P14 P24 P34 P44 — P74 P84 P94 — EV1 — EB3 EB11 — P13 P23 P33 P43 — P73 P83 P93 — PV1 — EB2 EB10 — P12 P22 P32 P42 P52 P72 P82 P92 — E1 — EB1 EB9 — P11 P21 P31 P41 P51 P71 P81 P91 — P1 — EB0 EB8 — P10 P20 P30 P40 P50 P70 P80 P90 Port FLASH D/A0, D/A1 8 PDWND — P17 P27 P37 P47 — P77 — P97 P16 P26 P36 P46 — P76 P86 P96 IMN Rev. 3.00 Jan 11, 2005 page 1059 of 1220 REJ09B0186-0300O (write) TCNT1 TI H'FFA2 TCSR1/ WT/ Appendix B Internal I/O Register Register Address Name H'FFB9 PORTA H'FFBA PORTB H'FFBB PORTC H'FFBC PORTD H'FFBD PORTE H'FFBE PORTF H'FFBF PORTG Module Name Port Data Bus Width (bits) 8 Bit 7 PA7 PB7 PC7 PD7 PE7 PF7 — Bit 6 PA6 PB6 PC6 PD6 PE6 PF6 — Bit 5 PA5 PB5 PC5 PD5 PE5 PF5 — Bit 4 PA4 PB4 PC4 PD4 PE4 PF4 PG4 Bit 3 PA3 PB3 PC3 PD3 PE3 PF3 PG3 Bit 2 PA2 PB2 PC2 PD2 PE2 PF2 PG2 Bit 1 PA1 PB1 PC1 PD1 PE1 PF1 PG1 Bit 0 PA0 PB0 PC0 PD0 PE0 PF0 PG0 Rev. 3.00 Jan 11, 2005 page 1060 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register B.2 Functions H'FFA4 H'FFA5 H'FDAC H'FDAD 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W DADR0—D/A Data Register 0 DADR1—D/A Data Register 1 DADR2—D/A Data Register 2 DADR3—D/A Data Register 3 Bit : 7 0 R/W 6 0 R/W D/A0 D/A1 D/A2 D/A3 Initial value : R/W : DACR01—D/A Control Register 01 DACR23—D/A Control Register 23 Bit : 7 DAOE1 Initial value : R/W : 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W D/A enable DAOE1 DAOE0 0 0 1 DAE * 0 1 0 1 * H'FFA6 H'FDAE 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — D/A0, 1 D/A2, 3 0 — 1 — 1 0 1 Description Disables channel 0, 1 (channel 2, 3) D/A conversion Enables channel 0 (channel 2) D/A conversion Disables channel 1 (channel 3) D/A conversion Enables channel 0, 1 (channel 2, 3) D/A conversion Disables channel 0 (channel 2) D/A conversion Enables channel 1 (channel 3) D/A conversion Enables channel 0, 1 (channel 2, 3) D/A conversion Enables channel 0, 1 (channel 2, 3) D/A conversion * : Don’t care D/A output enable 0 0 Disables analog output DA0 (DA2) 1 Enables channel 0 D/A conversion. Also enables analog output DA0 (DA2) D/A output enable 1 0 Disables analog output DA1 (DA3) 1 Enables channel 1 D/A conversion. Also enables analog output DA1 (DA3) Rev. 3.00 Jan 11, 2005 page 1061 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register IrCR—IrDA Control Register Bit : 7 IrE Initial value : R/W : 0 R/W 6 IrCKS2 0 R/W 5 IrCKS1 0 R/W 4 IrCKS0 0 R/W H'FDB0 3 — 0 — 2 — 0 — 1 — 0 — SCI0, IrDA 0 — 0 — IrDA clock select 2 to 0 Bit 6 IrCKS2 0 Bit 5 IrCKS1 0 1 1 0 1 Bit 4 IrCKS0 0 1 0 1 0 1 0 1 Description B × 3/16 (3/16ths of bit rate) φ/2 φ/4 φ/8 φ/16 φ/32 φ/64 φ/128 IrDA enable 0 1 TxD0/IrTxD and RxD0/IrRxD pins function as TxD0 and RxD0 TxD0/IrTxD and RxD0/IrRxD pins function as IrTx0 and IrRxD SCRX—Serial Control Register X Bit : 7 — Initial value : R/W : 0 R/W 6 IICX1 0 R/W 5 IICX0 0 R/W 4 IICE 0 R/W 3 H'FDB4 2 — 0 R/W 1 — 0 R/W 0 — 0 R/W IIC FLSHE 0 R/W Flash memory control register enable 0 1 Flash control registers deselected in area H'FFFFA8 to H'FFFFAC Flash control registers selected in area H'FFFFA8 to H'FFFFAC I2C master enable 0 1 Disables CPU access of I2C bus interface data register and control register 2 Enables CPU access of I C bus interface data register and control register I2C transfer rate select 1, 0 The master mode transfer rate is selected in combination with CKS2 to CKS0 in ICMR. For details, see the section on the I2C bus mode register. Rev. 3.00 Jan 11, 2005 page 1062 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register DDCSWR—DDC Switch Register Bit : 7 — Initial value : R/W : 0 R/(W)*1 6 — 0 R/(W)*1 5 — 0 R/(W)*1 4 — 0 R/(W)*1 H'FDB5 3 CLR3 1 W*2 2 CLR2 1 W*2 1 CLR1 1 W*2 0 CLR0 1 W*2 IIC Reserved bit IIC clear 3 to 0 Description CLR3 CLR2 CLR1 CLR0 0 0 — — Setting prohibited 1 0 0 Setting prohibited 1 IIC0 internal latch cleared 1 0 IIC1 internal latch cleared IIC0 and IIC1 internal latch cleared 1 Invalid setting 1 — — — Notes: 1. Should always be written with 0. 2. Always read as 1. Rev. 3.00 Jan 11, 2005 page 1063 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register DACR0—PWM (D/A) Control Register 0 DACR1—PWM (D/A) Control Register 1 Bit : 7 TEST Initial value : R/W : 0 R/W 6 PWME 0 R/W 5 — 1 — 4 — 1 — 3 OEB 0 R/W 2 OEA 0 R/W H'FDB8 H'FDBC 1 OS 0 R/W 0 CKS 0 R/W PWM0 PWM1 Clock select 0 1 Output select 0 1 Output enable A 0 1 Output enable B 0 1 PWM enable 0 1 Test mode 0 1 PWM (D/A) in user status and operating normally PWM (D/A) in test status and will not return correct result of conversion DACNT operates as 14-bit up-counter Count stops when DACNT = H'0003 PWM (D/A) channel B output (PWM1/PWM3 output pin) disabled PWM (D/A) channel B output (PWM1/PWM3 output pin) enabled PWM (D/A) channel A output (PWM0/PWM2 output pin) disabled PWM (D/A) channel A output (PWM0/PWM2 output pin) enabled Direct PWM output Inverted PWM output Resolution (T) = system clock cycle (tcyc) Resolution (T) = system clock cycle (tcyc) × 2 Rev. 3.00 Jan 11, 2005 page 1064 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register DADRAH0—PWM (D/A) Data Register AH0 DADRAL0—PWM (D/A) Data Register AL0 DADRBH0—PWM (D/A) Data Register BH0 DADRBL0—PWM (D/A) Data Register BL0 DADRAH1—PWM (D/A) Data Register AH1 DADRAL1—PWM (D/A) Data Register AL1 DADRBH1—PWM (D/A) Data Register BH1 DADRBL1—PWM (D/A) Data Register BL1 DADRH Bit (CPU) Bit (Data) DADRA Initial value : R/W : : 15 13 1 14 12 1 13 11 1 12 10 1 11 9 1 10 8 1 9 7 1 8 6 1 7 5 1 6 4 1 5 3 1 H'FDB8 H'FDB9 H'FDBA H'FDBB H'FDBC H'FDBD H'FDBE H'FDBF DADRL 4 2 1 3 1 1 2 0 1 1 — 1 0 — 1 PWM0 PWM0 PWM0 PWM0 PWM1 PWM1 PWM1 PWM1 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS — : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W — Carrier frequency select 0 1 Basic cycle = resolution (T) × 64. DADR range = H'0401 to H'FFFD Basic cycle = resolution (T) × 256. DADR range = H'0103 to H'FFFF D/A data 13 to 0 DADRB R/W : DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS REGS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register select 0 1 Carrier frequency select 0 1 Basic cycle = resolution (T) × 64. DADR range = H'0401 to H'FFFD Basic cycle = resolution (T) × 256. DADR range = H'0103 to H'FFFF DADRA and DADRB access enabled DACR and DACNT access enabled Initial value : D/A data 13 to 0 Rev. 3.00 Jan 11, 2005 page 1065 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register DACNTH0—PWM (D/A) Counter H0 DACNTL0—PWM (D/A) Counter L0 DACNTH1—PWM (D/A) Counter H1 DACNTL1—PWM (D/A) Counter L1 DACNTH Bit (CPU) : 15 7 0 14 6 0 13 5 0 12 4 0 11 3 0 10 2 0 9 1 0 8 0 0 H'FDBA H'FDBB H'FDBE H'FDBF DACNTL 7 8 0 6 9 0 5 10 0 4 11 0 3 12 0 2 13 0 1 — 1 PWM0 PWM0 PWM1 PWM1 0 — REGS 1 Bit (counter) : Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W — R/W Register select 0 1 DADRA and DADRB access enabled DACR and DACNT access enabled Rev. 3.00 Jan 11, 2005 page 1066 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TCR0—Timer Control Register 0 TCR1—Timer Control Register 1 TCR2—Timer Control Register 2 TCR3—Timer Control Register 3 Bit : 7 CMIEB Initial value : R/W : 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 H'FF68 H'FF69 H'FDC0 H'FDC1 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W TMR0 TMR1 TMR2 TMR3 CCLR0 0 R/W Clock select 2 to 0 CKS2 0 CKS1 CKS0 0 1 1 0 0 1 0 1 0 Description Clock input disabled Internal clock: Counting on falling edge of φ/8 Internal clock: Counting on falling edge of φ/64 Internal clock: Counting on falling edge of φ/8192 Channel 0: Counting on TCNT1 overflow signal * Channel 1: Counting on TCNT0 compare match A * Channel 2: Counting on TCNT3 overflow signal * Channel 3: Counting on TCNT2 compare match A * External clock: Counting on rising edge External clock: Counting on falling edge External clock: Counting on both rising and falling edges 1 1 0 1 Note: * No countup clock is generated if the channel 0 (channel 2) clock input is the TCNT1 (TCNT3) overflow signal, and that the channel 1 (channel 3) clock input is the TCNT0 (TCNT2) compare match signal. Do not, therefore, attempt to make such a setting. Counter clear 1, 0 CCLR1 CCLR0 0 1 0 1 0 1 Description Clearing disabled Cleared by compare match A Cleared by compare match B Cleared by rising edge of external reset input Timer overflow interrupt enable 0 1 OVF interrupt request (OVI) disabled OVF interrupt request (OVI) enabled Compare match interrupt enable A 0 1 CMFA interrupt request (CMIA) disabled CMFA interrupt request (CMIA) enabled Compare match interrupt enable B 0 1 CMFB interrupt request (CMIB) disabled CMFB interrupt request (CMIB) enabled Rev. 3.00 Jan 11, 2005 page 1067 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TCSR0—Timer Control/Status Register 0 TCSR1—Timer Control/Status Register 1 TCSR2—Timer Control/Status Register 2 TCSR3—Timer Control/Status Register 3 TCSR0 Bit H'FF6A H'FF6B H'FDC2 H'FDC3 TMR0 TMR1 TMR2 TMR3 : 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ADTE 0 R/W 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W Initial value : R/W : TCSR1, TCSR3 Bit : Initial value : R/W : 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 — 1 — 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W TCSR2 Bit : 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 — 0 R/W 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W Initial value : R/W : Bit 7: Compare match flag B [Clearing conditions] 0 • Reading CMFB then writing 0 to CMFB when CMFB = 1 • When DTC is started by CMIB interrupt and DTC MRB DISEL bit is 0 1 [Setting condition] • When TCNT=TCORB Bit 6: Compare match flag A 0 [Clearing conditions] • Reading CMFA then writing 0 to CMFA when CMFA = 1 • When DTC is started by CMIA interrupt and DTC MRB DISEL bit is 0 1 [Setting condition] • When TCNT=TCORA Bit 5: Timer overflow flag 0 [Clearing condition] • Reading OVF then writing 0 to OVF when OVF = 1 1 [Setting condition] • When TCNT changes from H’FF to H’00 Bit 4: A/D trigger enable 0 A/D conversion start request by compare match A disabled 1 A/D conversion start request by compare match A enabled Bits 3 to 0: Output select 3 to 0 OS3 0 1 OS2 0 1 0 1 Description No change at compare match B 0 output at compare match B 1 output at compare match B Inverted output each compare match B (toggle output) OS1 0 1 OS0 0 1 0 1 Description No change at compare match A 0 output at compare match A 1 output at compare match A Inverted output each compare match A (toggle output) Note: * Only 0 can be written to bits 7 to 5 (to clear these flags). Rev. 3.00 Jan 11, 2005 page 1068 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TCORA0—Time Constant Register A0 TCORA1—Time Constant Register A1 TCORA2—Time Constant Register A2 TCORA3—Time Constant Register A3 TCORA0 (TCORA2) Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FF6C H'FF6D H'FDC4 H'FDC5 TCORA1 (TCORA3) 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TMR0 TMR1 TMR2 TMR3 0 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB0—Time Constant Register B0 TCORB1—Time Constant Register B1 TCORB2—Time Constant Register B2 TCORB3—Time Constant Register B3 TCORB0 (TCORB2) Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FF6E H'FF6F H'FDC6 H'FDC7 TCORB1 (TCORB3) 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TMR0 TMR1 TMR2 TMR3 0 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT0—Timer Counter 0 TCNT1—Timer Counter 1 TCNT2—Timer Counter 2 TCNT3—Timer Counter 3 TCNT0 (TCNT2) Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FF70 H'FF71 H'FDC8 H'FDC9 TCNT1 (TCNT3) 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TMR0 TMR1 TMR2 TMR3 0 0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 3.00 Jan 11, 2005 page 1069 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register SMR0—Serial Mode Register 0 SMR1—Serial Mode Register 1 SMR2—Serial Mode Register 2 SMR3—Serial Mode Register 3 SMR4—Serial Mode Register 4 Bit : 7 C/A Initial value : R/W : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF78 H'FF80 H'FF88 H'FDD0 H'FDD8 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SCI0 SCI1 SCI2 SCI3 SCI4 Clock select 1 and 0 CKS1 0 1 CKS0 0 1 0 1 Description φ clock φ/4 clock φ/16 clock φ/64 clock Multiprocessor mode 0 1 Multiprocessor function disabled Multiprocessor format selected Stop bit length 0 1 1 stop bit: In transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. 2 stop bits: In transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. Parity mode 0 1 Even parity*1 Odd parity*2 Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Parity enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled* Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Character length 0 1 8-bit data 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible to choose between LSB-first or MSB-first transfer. Communication mode 0 1 Asynchronous mode Clocked synchronous mode Rev. 3.00 Jan 11, 2005 page 1070 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register SMR0—Serial Mode Register 0 SMR1—Serial Mode Register 1 SMR2—Serial Mode Register 2 SMR3—Serial Mode Register 3 SMR4—Serial Mode Register 4 Bit : 7 GM Initial value : R/W : 0 R/W 6 BLK 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF78 H'FF80 H'FF88 H'FDD0 H'FDD8 3 BCP1 0 R/W 2 BCP0 0 R/W 1 CKS1 0 R/W Smart Card Interface 0 CKS0 0 R/W Basic clock pulse 1, 0 Description BCP1 BCP0 0 0 32 clock 1 64 clock 1 0 372 clock 1 256 clock Block transfer mode 0 Operation of normal smart card interface mode (1) Error signal output, detection, and automatic resending of data (2) TXI interrupt generated by TEND flag (3) TEND flag set 12.5etu after start of transmission (after 11.0etu in GSM mode) Operation in block transfer mode (1) No error signal output, detection, or automatic resending of data (2) TXI interrupt generated by TDRE flag (3) TEND flag set 11.5etu after start of transmission (after 11.0etu in GSM mode) 1 GSM Mode 0 Operation in normal smart card interface mode (1) TEND flag set 12.5etu (11.5etu in block transfer mode) after start of first bit (2) ON/OFF control only of clock output Operation in GSM mode smart card interface mode (1) TEND flag set 11.0etu after start of first bit (2) In addition to ON/OFF control of clock output, High/Low control also enabled (set by SCR) 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit). Note: Set bit 5 to 1 when using the Smart Card interface. Rev. 3.00 Jan 11, 2005 page 1071 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register BRR0—Bit Rate Register 0 BRR1—Bit Rate Register 1 BRR2—Bit Rate Register 2 BRR3—Bit Rate Register 3 BRR4—Bit Rate Register 4 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF79 H'FF81 H'FF89 H'FDD1 H'FDD9 3 1 R/W 2 1 R/W 1 1 R/W 0 1 SCI0 SCI1 SCI2 SCI3 SCI4 Initial value : R/W : R/W Rev. 3.00 Jan 11, 2005 page 1072 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register SCR0—Serial Control Register 0 SCR1—Serial Control Register 1 SCR2—Serial Control Register 2 SCR3—Serial Control Register 3 SCR4—Serial Control Register 4 Bit : 7 TIE Initial value : R/W : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W Clock enable 1, 0 Bit 1 CKE1 0 Bit 0 CKE0 0 H'FF7A H'FF82 H'FF8A H'FDD2 H'FDDA 0 CKE0 0 R/W SCI0 SCI1 SCI2 SCI3 SCI4 Description Async mode Internal clock/SCK pin set as I/O port*1 Clock sync mode Internal clock/SCK pin set for sync clock output*1 1 Async mode Internal clock/SCK pin set for clock output*2 Clock sync mode Internal clock/SCK pin set for sync clock output 1 0 Async mode External clock/SCK pin set for clock input*3 Clock sync mode External clock/SCK pin set for sync clock input 1 Async mode External clock/SCK pin set for clock input*3 Clock sync mode External clock/SCK pin set for sync clock input Notes: 1. Initial value 2. Clock output at same frequency as bit rate 3. Clock input at 16 times frequency of bit rate Transmit end interrupt enable 0 Transmit end interrupt (TEI) requests disabled* 1 Transmit end interrupt (TEI) requests enabled* Note: * To cancel a TEI, clear SSR TDRE flag to 0 after reading TDRE=1, then either clear the TEND flag to 0 or clear the TEIE bit to 0. Multiprocessor interrupt enable 0 Multiprocessor interrupt disabled (normal receive operations) [Clearing conditions] • Clear the MPIE bit to 0 • When data MPB=1 is received Multiprocessor interrupt enabled* Until data is received that the multiprocessor bit = 1, receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and SSR RDRF, FER, and ORER flags cannot be set. 1 Note: * On reception of receive data that includes MPB=0, the receive data is not sent from the RSR to the RDR, and, on detection of receive errors, the SSR RDRF, FER and ORER flags are not set. On reception of receive data that includes MPB=1, the SSR MPB bit is set to 1 and the MPIE bit is automatically cleared to 0. If an RXI or ERI interrupt request occurs (when the SCR TIE or RIE bit is set to 1), the FER and ORER flags can be set. Receive enable 0 Disable receive operation *1 1 Enable receive operation *2 Notes: 1. Clearing the RE bit has no effect on the RDRF, FER, PER, or ORER flags. 2. Serial receiving starts on detection of the start bit when in async mode, or on detection of sync clock input in clock sync mode. Before setting the RE bit to 1, be sure to set the SMR to decide the receive format. Transmit enable 0 Disable transmit operation *1 1 Enable transmit operation *2 Notes: 1. The SSR TDRE flag is set to 1 (fixed). 2. Transmission starts when, in this state, transmit data is written to TDR and the SSR TDRE flag is cleared to 0. Before setting the TE bit to 1, be sure to set the SMR to decide the transmit format. Receive interrupt enable 0 Disable receive data full interrupt (RXI) requests and receive error interrupt (ERI) requests * 1 Enable receive data full interrupt (RXI) requests and receive error interrupt (ERI) requests Note: * To cancel RXI and ERI interrupt requests, either clear the RDRF or FER, PER, or ORER flags after reading “1”, or clear the RIE bit to 0. Transmit interrupt enable 0 Disable transmit data empty interrupt (TXI) requests 1 Enable transmit data empty interrupt (TXI) requests Note: To clear TXI interrupt requests, clear the TDRE flag to 0 after reading “1”, or clear the TIE bit to 0. Rev. 3.00 Jan 11, 2005 page 1073 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TDR0—Transmit Data Register 0 TDR1—Transmit Data Register 1 TDR2—Transmit Data Register 2 TDR3—Transmit Data Register 3 TDR4—Transmit Data Register 4 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF7B H'FF83 H'FF8B H'FDD3 H'FDDB 3 1 R/W 2 1 R/W 1 1 R/W 0 1 SCI0 SCI1 SCI2 SCI3 SCI4 Initial value : R/W : R/W Rev. 3.00 Jan 11, 2005 page 1074 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register SSR0—Serial Status Register 0 SSR1—Serial Status Register 1 SSR2—Serial Status Register 2 SSR3—Serial Status Register 3 SSR4—Serial Status Register 4 Bit : 7 TDRE Initial value : R/W : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* H'FF7C H'FF84 H'FF8C H'FDD4 H'FDDC 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W SCI0 SCI1 SCI2 SCI3 SCI4 Multiprocessor bit transfer (MPBT) 0 1 Transfer data “multiprocessor bit = 0” Transfer data “multiprocessor bit = 1” Multiprocessor bit (MPB) 0 1 [Clearing condition]* • When data “multiprocessor bit = 0” is received [Setting condition] • When data “multiprocessor bit = 1” is received Note: * The existing status is continued when, in multiprocessor format, the SCR RE bit is cleared to 0. Transmit end (TEND) 0 [Clearing conditions] • Writing 0 to TDRE flag after reading TDRE = 1 • When data is written to TDR by DMAC or DTC by TXI interrupt request [Setting conditions] • When SCR TE bit = 0 • When TDRE = 1 at transfer of last bit of any byte of serial transmit character 1 Parity error (PER) 0 1 [Clearing condition]*1 • Writing 0 to PER after reading PER = 1 [Setting condition] • When receiving, when the number of 1s in receive data plus parity bit does not match the even or odd parity specified in the SMR O/E bit *2 Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. Framing error (FER) 0 1 [Clearing condition] *1 • Writing 0 to FER after reading FER = 1 [Setting condition] • When SCI checks if the stop bit at the end of receive data is 1 on completion of receiving, the stop bit is found to be 0 Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. Overrun error (ORER) 0 1 [Clearing condition]*1 • Writing 0 to ORER after reading ORER = 1 [Setting condition] • On completion of next serial receive operation when RDRF = 1*2 Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. Receive data register full (RDRF) 0 [Clearing conditions] • Writing 0 to RDRF after reading RDRF = 1 • After reading RDR data by DMAC or DTC by RXI interrupt request [Setting condition] • When receive data is sent from RSR to RDR on normal completion of serial receive operation 1 Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Transmit data register empty (TDRE) 0 [Clearing conditions] • Writing 0 to TDRE after reading TDRE = 1 • When data written to TDR by DMAC or DTC by TXI interrupt request [Setting conditions] • When SCR TE bit = 0 • When data is sent from TDR to TSR and data can be written to TDR 1 Note: * Only 0 can be written to these bits (to clear these flags). Rev. 3.00 Jan 11, 2005 page 1075 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register RDR0—Receive Data Register 0 RDR1—Receive Data Register 1 RDR2—Receive Data Register 2 RDR3—Receive Data Register 3 RDR4—Receive Data Register 4 Bit : 7 0 R 6 0 R 5 0 R 4 0 R H'FF7D H'FF85 H'FF8D H'FDD5 H'FDDD 3 0 R 2 0 R 1 0 R 0 0 R SCI0 SCI1 SCI2 SCI3 SCI4 Initial value : R/W : SCMR0—Smart Card Mode Register 0 SCMR1—Smart Card Mode Register 1 SCMR2—Smart Card Mode Register 2 SCMR3—Smart Card Mode Register 3 SCMR4—Smart Card Mode Register 4 Bit : 7 — Initial value : R/W : 1 — 6 — 1 — 5 — 1 — 4 — 1 — H'FF7E H'FF86 H'FF8E H'FDD6 H'FDDE 3 SDIR 0 R/W 2 SINV 0 R/W 1 — 1 — 0 SCI0 SCI1 SCI2 SCI3 SCI4 SMIF 0 R/W Smart card interface mode select 0 1 Operates as normal SCI (Smart Card interface function disabled) Enables smart card interface function Smart card data invert 0 1 TDR contents are transmitted without modification Receive data is stored in RDR without modification TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Smart card data transfer direction 0 1 Sends TDR contents LSB first Receive data stored in RDR as LSB first Sends TDR contents MSB first Receive data stored in RDR as MSB first Rev. 3.00 Jan 11, 2005 page 1076 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register SBYCR—Standby Control Register Bit : 7 SSBY Initial value : R/W : 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W H'FDE4 3 OPE 1 R/W 2 — 0 — 1 — 0 — System 0 — 0 — Output port enable 0 In software standby mode, watch mode, and during direct transfer, the address bus and bus control signal are in the high-impedance state 1 In software standby mode, watch mode, and during direct transfer, the address bus and bus control signal remain in the output state Standby timer select 2 to 0 Description STS2 STS1 STS0 0 0 0 Standby time: 8192 states 1 Standby time: 16384 states 1 0 Standby time: 32768 states 1 Standby time: 65536 states Standby time: 131072 states 1 0 0 Standby time: 262144 states 1 Reserved 1 0 Standby time: 16 states 1 Software standby 0 When the SLEEP command is executed in high-speed or medium-speed modes, the operation enters sleep mode When the SLEEP command is executed in sub-active mode, the operation enters sub-sleep mode 1 When the SLEEP command is executed in high-speed and medium-speed modes, operation enters software standby mode, sub-active mode, and watch mode When the SLEEP command is executed in sub-active mode, operation enters watch mode and high-speed mode Rev. 3.00 Jan 11, 2005 page 1077 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register SYSCR—System Control Register Bit : 7 MACS Initial value : R/W : 0 R/W 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W H'FDE5 3 0 R/W 2 0 R/W 1 — 0 — 0 System NMIEG MRESE RAME 1 R/W RAM Enable 0 1 Internal RAM disabled Internal RAM enabled Manual reset select bit 0 Manual reset disabled Pins P74/TMO2/MRES can be used as P74/TMO2 I/O pins Manual reset enabled Pins P74/TMO2/MRES can be used as MRES input pins Pin RES 0 1 1 NMI edge select 0 1 Interrupt control mode 1, 0 INTM1 0 1 INTM0 0 1 0 1 MAC saturation 0 1 Non-saturating calculation for MAC instruction Saturating calculation for MAC instruction Interrupt control mode 1 MRES 1 0 1 Reset Type Power-on reset Manual reset Operation state Interrupt request issued on falling edge of NMI input Interrupt request issued on rising edge of NMI input Description Interrupt controlled by bit I Do not set Interrupt controlled by bits I2 to I0 and IPR Do not set 0 — 2 — Rev. 3.00 Jan 11, 2005 page 1078 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register SCKCR—System Clock Control Register Bit : 7 PSTOP Initial value : R/W : 0 R/W 6 — 0 — 5 — 0 — 4 — 0 — 3 H'FDE6 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W System STCS 0 R/W System clock select 2 to 0 SCK2 0 SCK1 0 1 1 0 1 Frequency multiplier switching mode select 0 1 Specified multiplier valid after transferring to software standby mode, watch mode, and sub-active mode Specified multiplier valid immediately after setting value in STC bit SCK0 0 1 0 1 0 1 — Description Bus master set to high-speed mode. Medium-speed clock: φ/2 Medium-speed clock: φ//4 Medium-speed clock: φ8 Medium-speed clock: φ/16 Medium-speed clock: φ/32 — φ clock output disable PSTOP High-speed mode, Medium-speed mode, Sub-active mode φ output High level (fixed) Sleep mode, Software standby mode, Hardware standby Sub-Sleep mode Watch mode, Direct transition mode φ output High level (fixed) High level (fixed) High level (fixed) High impedance High impedance 0 1 Rev. 3.00 Jan 11, 2005 page 1079 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register MDCR—Mode Control Register Bit : 7 — Initial value : R/W : 1 R/W 6 — 0 — 5 — 0 — 4 — 0 — H'FDE7 3 — 0 — 2 MDS2 —* R 1 MDS1 —* R System 0 MDS0 —* R Note: * Determined by pins MD2 to MD0. Mode select 2 to 0 * Input level determined by mode pins. MSTPCRA—Module Stop Control Register A Bit : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W H'FDE8 3 1 R/W 2 1 R/W 1 1 R/W System 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : Module stop 0 1 Module stop mode is cleared Module stop mode is set MSTPCRB—Module Stop Control Register B Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FDE9 3 1 R/W 2 1 R/W 1 1 R/W System 0 1 R/W MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : R/W : Module stop 0 1 Module stop mode canceled Module stop mode enabled Rev. 3.00 Jan 11, 2005 page 1080 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register MSTPCRC—Module Stop Control Register C Bit : 7 1 R/W 6 1 R/W Module stop 0 1 Module stop mode canceled Module stop mode enabled H'FDEA 4 1 3 1 R/W 2 1 R/W 1 1 R/W System 0 1 R/W 5 1 R/W MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : R/W : R/W Rev. 3.00 Jan 11, 2005 page 1081 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register PFCR—Pin Function Control Register Bit : 7 CSS07 Initial value : R/W : 0 R/W 6 CSS36 0 R/W 5 BUZZE 0 R/W 4 LCASS 0 R/W H'FDEB 3 AE3 1/0 R/W 2 AE2 1/0 R/W 1 AE1 0 R/W 0 System AE0 1/0 R/W Address output enable 3 to 0* AE3 AE2 AE1 AE0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A8 to A23 address output disabled A8 address output enabled. A9 to A23 address output disabled A8 and A9 address output enabled. A10 to A23 address output disabled A8 to A10 address output enabled. A11 to A23 address output disabled A8 to A11 address output enabled. A12 to A23 address output disabled A8 to A12 address output enabled. A13 to A23 address output disabled A8 to A13 address output enabled. A14 to A23 address output disabled A8 to A14 address output enabled. A15 to A23 address output disabled A8 to A15 address output enabled. A16 to A23 address output disabled A8 to A16 address output enabled. A17 to A23 address output disabled A8 to A17 address output enabled. A18 to A23 address output disabled A8 to A18 address output enabled. A19 to A23 address output disabled A8 to A19 address output enabled. A20 to A23 address output disabled A8 to A20 address output enabled. A21 to A23 address output disabled A8 to A21 address output enabled. A22 and A23 address output disabled A8 to A23 address output enabled Note: * In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000. In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101. Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to 1. LCAS output pin select bit 0 1 LCAS signal output from PF2 LCAS signal output from PF6 BUZZ output enable 0 1 Functions as PF1 input pin Functions as BUZZ output pin CS3/CS6 Select 0 1 Selects CS3 Selects CS6 CS0/CS7 Select 0 1 Selects CS0 Selects CS7 Rev. 3.00 Jan 11, 2005 page 1082 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register LPWRCR—Low-Power Control Register Bit : 7 DTON Initial value : R/W : 0 R/W 6 LSON 0 R/W 5 0 R/W 4 0 R/W H'FDEC 3 0 R/W 2 — 0 R/W 1 STC1 0 R/W 0 STC0 0 R/W System NESEL SUBSTP RFCUT Frequency multiplier STC1 0 1 STC0 0 1 0 1 Description ×1 ×2 ×4 Do not set Note: A system clock frequency multiplied by the multiplication factor (STC1 and STC0) should not exceed the maximum operating frequency defined in section 25, Electrical Characteristics. Current consumption and noise can be reduced by using this function's PLL × 4 setting and lowering the external clock frequency. Oscillator circuit feedback resistor control bit 0 1 Subclock enable 0 1 Subclock generation enabled Subclock generation disabled Feedback resistor ON when main clock operating; OFF when not operation Feedback resistor OFF Noise elimination sampling frequency select 0 Sampling uses φ/32 clock 1 Sampling uses φ/4 clock Low-speed ON flag 0 • When the SLEEP command is executed in high-speed mode or medium-speed mode, operation transfers to sleep mode, software standby mode, or watch mode* • When the SLEEP command is executed in sub-active mode, operation transfers to watch mode, or directly to high-speed mode • Operation transfers to high-speed mode after watch mode is canceled • When the SLEEP command is executed in high-speed mode, operation transfers to watch mode or sub-active mode • When the SLEEP command is executed in sub-active mode, operation transfers to sub-sleep mode or watch mode • Operation transfers to sub-active mode immediately watch mode is canceled 1 Note: * Always select high-speed mode when transferring to watch mode or sub-active mode. Direct transfer ON flag 0 • When the SLEEP command is executed in high-speed mode or medium-speed mode, operation transfers to sleep mode, software standby mode, or watch mode* • When the SLEEP command is executed in sub-active mode, operation transfers to sub-sleep mode or watch mode 1 • When the SLEEP command is executed in high-speed mode or medium-speed mode, operation transfers directly to sub-active mode*, or transfers to sleep mode or software standby mode • When the SLEEP command is executed in sub-active mode, operation transfers directly to high-speed mode or transfers to sub-sleep mode Note: * Always select high-speed mode when transferring to watch mode or sub-active mode. Rev. 3.00 Jan 11, 2005 page 1083 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register BARA—Break Address Register A BARB—Break Address Register B Bit : 31 — ··· ··· 24 23 22 21 20 19 18 17 H'FE00 H'FE04 16 ··· 7 6 5 4 3 2 1 PBC PBC 0 BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA — ··· 0 7 6 5 4 3 2 1 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 ··· 0 0 0 0 0 0 0 0 Initial value : R/W : Unde- ··· Unde- 0 fined fined — ··· — R/W R/W R/W R/W R/W R/W R/W R/W ··· R/W R/W R/W R/W R/W R/W R/W R/W Break address 23 to 0 Note: The bit configuration of BARB is the same as that of BARA. Rev. 3.00 Jan 11, 2005 page 1084 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register BCRA—Break Control Register A BCRB—Break Control Register B Bit : 7 CMFA Initial value : R/W : 0 R/(W)* 6 CDA 0 R/W 5 4 H'FE08 H'FE09 3 2 1 0 BIEA 0 R/W PBC PBC BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Break interrupt enable 0 1 Break condition select CSELA1 CSELA0 0 0 1 1 Break address mask register A2 to A0 BAMRA BAMRA BAMRA 1 2 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Description All bits, without masking BARA, included in break condition BAA0 (LSB) masked and not included in break condition BAA1 and BAA0 (low 2 bits) masked and not included in break condition BAA2 to BAA0 (low 3 bits) masked and not included in break condition BAA3 to BAA0 (low 4 bits) masked and not included in break condition BAA7 to BAA0 (low 8 bits) masked and not included in break condition BAA11 to BAA0 (low 12 bits) masked and not included in break condition BAA15 to BAA0 (low 16 bits) masked and not included in break condition 0 1 0 1 Description Sets instruction fetch as break condition Sets data read cycle as break condition Sets data write cycle as break condition Sets data read/write cycle as break condition Disables PC break interrupt Enables PC break interrupt CPU cycle/DTC cycle select A 0 1 When the CPU is the bus master, PC break performed When the CPU or DTC is the bus master, PC break performed Condition match flag A 0 1 [Clearing condition] • Writing 0 to CMFA after reading CMFA = 1 [Setting condition] • When channel A conditions are true Notes: The bit configuration of BCRB is the same as that of BCRA. * Only 0 can be written to these bits (to clear these flags). Rev. 3.00 Jan 11, 2005 page 1085 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register ISCRH—IRQ Sense Control Register H ISCRL—IRQ Sense Control Register L ISCRH Bit : 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W H'FE12 H'FE13 Interrupt Controller Interrupt Controller 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : R/W : ISCRL Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : R/W : IRQ7 sense control A, B to IRQ0 sense control A, IRQ7SCB IRQ7SCA to IRQ0SCB to IRQ0SCA 0 1 0 1 0 1 Description Interrupt request issued when IRQ7 to IRQ0 input level low Interrupt request issued on falling edge of IRQ7 to IRQ0 input Interrupt request issued on rising edge of IRQ7 to IRQ0 input Interrupt request issued on both falling and rising edges of IRQ7 to IRQ0 input IER—IRQ Enable Register Bit : 7 IRQ7E Initial value : R/W : 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W H'FE14 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W Interrupt Controller 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W IRQ7 to IRA0 enable 0 1 Disables IRQn interrupt Enables IRQn interrupt (n = 7 to 0) Rev. 3.00 Jan 11, 2005 page 1086 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register ISR—IRQ Status Register Bit : 7 IRQ7F Initial value : R/W : 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* H'FE15 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* Interrupt Controller 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* IRQ7 to IRQ0 flag 0 [Clearing conditions] • Writing 0 to flag IRQnF after reading IRQnF = 1 • When interrupt exception processing is executed when set for LOW-level detection (IRQnSCB = IRQnSCA = 0) and, in addition, the IRQn input level is HIGH • When IRQn interrupt exception processing is executed when set for rising edge or falling edge or both rising edge and falling edge detection (IRQnSCB = 1 and IRQnSCA = 1) • When the DTC starts due to IRQn interrupt and the DTC MRB DISEL bit is 0 [Setting conditions] • When the IRQn input level changes to LOW when set for LOW level detection (IRQnSCB = IRQnSCA = 0) • When a falling edge occurs at the IRQn input when set for falling edge detection (IRQnSCB = 0, IRQnSCA = 1) • When a rising edge occurs at the IRQn input when set for rising edge detection (IRQnSCB = 1, IRQnSCA = 0) • When either a falling edge or rising edge occurs at the IRQn input when set for both falling edge and rising edge detection (IRQnSCB = IRQnSCA = 1) (n = 7 to 0) 1 Note: * Only 0 can be written to these bits (to clear these flags). Rev. 3.00 Jan 11, 2005 page 1087 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register DTCER—DTC Enable Register H'FE16 to H'FE1E 5 DTCE5 0 R/W 4 DTCE4 0 R/W 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTC Bit : 7 DTCE7 0 R/W 6 DTCE6 0 R/W DTCE0 0 R/W Initial value : R/W : DTC activation enable 0 DTC activation by interrupt disabled [Clearing conditions] • When data transmission ends with the DISEL bit = 1 • On completion of the specified number of transmissions DTC activation by interrupt enabled [Holding condition] • When DISEL = 0 and the specified number of transmissions has not completed (n = 7 to 0) 1 Rev. 3.00 Jan 11, 2005 page 1088 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register DTVECR—DTC Vector Register Bit : 7 0 R/(W)*1 6 0 5 0 4 0 H'FE1F 3 0 2 0 1 0 0 0 DTC SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : R/W : R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 DTC software startup enable 0 DTC software startup disabled [Clearing conditions] • When DISEL = 0 and the specified number of transmissions has not completed • When 0 is written after a software startup data transmit end interrupt (SWDTEND) request is sent to the CPU DTC software startup enabled [Retention conditions] • When DISEL = 1 and data transmission ends • On completion of the specified number of transmissions • During data transmission by software startup DTC software startup vector 6 to 0 Notes: 1. Only 1 can be written to the SWDTE bit. 2. DTVEC6 to DTVEC0 can be written to when SWDTE = 0. 1 Rev. 3.00 Jan 11, 2005 page 1089 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register PCR—PPG Output Control Register Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FE26 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W PPG G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value : R/W : Group 0 compare match select 1, 0 G0CMS1 G0CMS0 Pulse output group 0 output trigger 0 1 0 1 0 1 TPU channel 0 compare match TPU channel 1 compare match TPU channel 2 compare match TPU channel 3 compare match Group 1 compare match select 1, 0 G1CMS1 G1CMS0 Pulse output group 1 output trigger 0 1 0 1 0 1 Group 2 compare match select 1, 0 G2CMS1 G2CMS0 0 1 0 1 0 1 Group 3 compare match select 1, 0 G3CMS1 G3CMS0 Pulse output group 3 output trigger 0 1 0 1 0 1 TPU channel 0 compare match TPU channel 1 compare match TPU channel 2 compare match TPU channel 3 compare match Pulse output group 2 output trigger TPU channel 0 compare match TPU channel 1 compare match TPU channel 2 compare match TPU channel 3 compare match TPU channel 0 compare match TPU channel 1 compare match TPU channel 2 compare match TPU channel 3 compare match Rev. 3.00 Jan 11, 2005 page 1090 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register PMR—PPG Output Mode Register Bit : 7 G3INV Initial value : R/W : 1 R/W 6 G2INV 1 R/W 5 G1INV 1 R/W 4 G0INV 1 R/W H'FE27 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PPG G3NOV G2NOV G1NOV G0NOV Group 0 non-overlap 0 1 Pulse output group 0 set for normal operation (output value updated on compare match A for selected TPU) Pulse output group 0 set for non-overlap operation (1 output and 0 output can be output independently on compare matches A and B of selected TPU) Group 1 non-overlap 0 1 Pulse output group 1 set for normal operation (output value updated on compare match A for selected TPU) Pulse output group 1 set for non-overlap operation (1 output and 0 output can be output independently on compare matches A and B of selected TPU) Group 2 non-overlap 0 1 Pulse output group 2 set for normal operation (output value updated on compare match A for selected TPU) Pulse output group 2 set for non-overlap operation (1 output and 0 output can be output independently on compare matches A and B of selected TPU) Group 3 non-overlap 0 1 Pulse output group 3 set for normal operation (output value updated on compare match A for selected TPU) Pulse output group 3 set for non-overlap operation (1 output and 0 output can be output independently on compare matches A and B of selected TPU) Group 0 inversion 0 1 Pulse output group 0 set for inverted output (pin output level is set low when PODRL = 1) Pulse output group 0 set for direct output (pin output level is set high when PODRL = 1) Group 1 inversion 0 1 Pulse output group 1 set for inverted output (pin output level is set low when PODRL = 1) Pulse output group 1 set for direct output (pin output level is set high when PODRL = 1) Group 2 inversion 0 1 Pulse output group 2 set for inverted output (pin output level is set low when PODRH = 1) Pulse output group 2 set for direct output (pin output level is set high when PODRH = 1) Group 3 inversion 0 1 Pulse output group 3 set for inverted output (pin output level is set low when PODRH = 1) Pulse output group 3 set for direct output (pin output level is set high when PODRH = 1) Rev. 3.00 Jan 11, 2005 page 1091 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register NDERH—Next Data Enable Register H NDERL—Next Data Enable Register L NDERH Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE28 H'FE29 PPG PPG 3 0 R/W 2 0 R/W 1 0 R/W 0 NDER8 0 R/W NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 Initial value : R/W : Next data enable 15 to 8 NDER15 to NDER8 0 1 Description Pulse output PO15 to PO8 disabled (transfer from NDR15-NDR8 to POD15-POD8 disabled) Pulse output PO15 to PO8 enabled (transfer from NDR15-NDR8 to POD15-POD8 enabled) NDERL Bit : 7 NDER7 Initial value : R/W : 0 R/W 6 NDER6 0 R/W 5 NDER5 0 R/W 4 NDER4 0 R/W 3 NDER3 0 R/W 2 NDER2 0 R/W 1 NDER1 0 R/W 0 NDER0 0 R/W Next data enable 7 to 0 NDER7 to NDER0 0 1 Description Pulse output PO7 to PO0 disabled (transfer from NDR7-NDR0 to POD7-POD0 disabled) Pulse output PO7 to PO0 enabled (transfer from NDR7-NDR0 to POD7-POD0 enabled) Rev. 3.00 Jan 11, 2005 page 1092 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register PODRH—Output Data Register H PODRL—Output Data Register L PODRH Bit : 7 POD15 Initial value : R/W : 0 R/(W)* 6 POD14 0 R/(W)* 5 POD13 0 R/(W)* 4 POD12 0 R/(W)* H'FE2A H'FE2B PPG PPG 3 POD11 0 R/(W)* 2 POD10 0 R/(W)* 1 POD9 0 R/(W)* 0 POD8 0 R/(W)* PODRL Bit : 7 POD7 Initial value : R/W : 0 R/(W)* 6 POD6 0 R/(W)* 5 POD5 0 R/(W)* 4 POD4 0 R/(W)* 3 POD3 0 R/(W)* 2 POD2 0 R/(W)* 1 POD1 0 R/(W)* 0 POD0 0 R/(W)* Note: * The bits set for pulse output by NDER are read-only bits. Rev. 3.00 Jan 11, 2005 page 1093 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register NDRH—Next Data Register H Same trigger for pulse output groups: Address: H'FE2C Bit : 7 NDR15 Initial value : R/W : 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W H'FE2C, H'FE2E PPG 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Address: H'FE2E Bit : 7 — Initial value : R/W : 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Different triggers for pulse output groups: Address: H'FE2C Bit : 7 NDR15 Initial value : R/W : 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Address: H'FE2E Bit : 7 — Initial value : R/W : 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Note: For details see section 12.2.4, Notes on NDR Access. Rev. 3.00 Jan 11, 2005 page 1094 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register NDRL—Next Data Register L Same trigger for pulse output groups: Address: H'FE2D Bit : 7 NDR7 Initial value : R/W : 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W H'FE2D, H'FE2F PPG 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Address: H'FE2F Bit : 7 — Initial value : R/W : 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Different triggers for pulse output groups: Address: H'FE2D Bit : 7 NDR7 Initial value : R/W : 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Address: H'FE2F Bit : 7 — Initial value : R/W : 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Note: For details see section 12.2.4, Notes on NDR Access. Rev. 3.00 Jan 11, 2005 page 1095 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register P1DDR—Port 1 Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FE30 3 0 W 2 0 W 1 0 W 0 0 W Port P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : R/W : P2DDR—Port 2 Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FE31 3 0 W 2 0 W 1 0 W 0 0 W Port P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : R/W : P3DDR—Port 3 Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FE32 3 0 W 2 0 W 1 0 W 0 0 W Port P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value : R/W : P5DDR—Port 5 Data Direction Register Bit : 7 — R/W : — 6 — — 5 — — 4 — — H'FE34 3 — — 2 0 W 1 0 W 0 0 W Port P52DDR P51DDR P50DDR Initial value : undefined undefined undefined undefined undefined P7DDR—Port 7 Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FE36 3 0 W 2 0 W 1 0 W 0 0 W Port P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR Initial value : R/W : Rev. 3.00 Jan 11, 2005 page 1096 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register P8DDR—Port 8 Data Direction Register Bit : 7 — Initial value : undefined R/W : — 6 0 W 5 0 W 4 0 W H'FE37 3 0 W 2 0 W 1 0 W 0 0 W Port P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR PADDR—Port A Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FE39 3 0 W 2 0 W 1 0 W 0 0 W Port PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Initial value : R/W : PBDDR—Port B Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FE3A 3 0 W 2 0 W 1 0 W 0 0 W Port PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value : R/W : PCDDR—Port C Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FE3B 3 0 W 2 0 W 1 0 W 0 0 W Port PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Initial value : R/W : Rev. 3.00 Jan 11, 2005 page 1097 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register PDDDR—Port D Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FE3C 3 0 W 2 0 W 1 0 W 0 0 W Port PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : R/W : PEDDR—Port E Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FE3D 3 0 W 2 0 W 1 0 W 0 0 W Port PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : R/W : PFDDR—Port F Data Direction Register Bit Modes 4 to 6 Initial value R/W Mode 7 Initial value R/W : : 0 W 0 W 0 W 0 W : : 1 W 0 W 0 W 0 W : 7 6 5 4 H'FE3E 3 2 1 0 Port PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Rev. 3.00 Jan 11, 2005 page 1098 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register PGDDR—Port G Data Direction Register Bit Modes 4 and 5 Initial value R/W Modes 6 and 7 Initial value R/W : Undefined Undefined Undefined : — — — 0 W : Undefined Undefined Undefined : — — — 1 W : 7 — 6 — 5 — 4 H'FE3F 3 2 1 0 Port PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W PAPCR—Port A Pull-Up MOS Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE40 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial value : R/W : PBPCR—Port B Pull-Up MOS Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE41 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : R/W : PCPCR—Port C Pull-Up MOS Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE42 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : R/W : Rev. 3.00 Jan 11, 2005 page 1099 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register PDPCR—Port D Pull-Up MOS Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE43 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : R/W : PEPCR—Port E Pull-Up MOS Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE44 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : R/W : P3ODR—Port 3 Open-Drain Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE46 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port P37ODR P36ODR P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR Initial value : R/W : PAODR—Port A Open Drain Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE47 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial value : R/W : Rev. 3.00 Jan 11, 2005 page 1100 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register PBODR—Port B Open Drain Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE48 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR Initial value : R/W : PCODR—Port C Open Drain Control Register Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FE49 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR Initial value : R/W : Rev. 3.00 Jan 11, 2005 page 1101 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TCR0—Timer Control Register 0 TCR3—Timer Control Register 3 Channel 0: TCR0 Channel 3: TCR3 Bit : 7 CCLR2 Initial value : R/W : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 H'FF10 H'FE80 TPU0 TPU3 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W CKEG1 CKEG0 R/W Time prescaler 2, 1, 0 TCR0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 TCR3 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Clock edge 1, 0 CKEG1 0 1 CKEG0 0 1 — Counts on rising edge Counts on falling edge Counts on both edges Description Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input Internal clock: counts on φ/1024 Internal clock: counts on φ/256 Internal clock: counts on φ/4096 Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input Note: Internal clock edge selection is valid only when the input clock is ø/4 or slower. This setting is ignored when the input clock is ø/1 or an overflow or underflow in another channel is selected. Counter clear 2, 1, 0 CCLR2 0 CCLR1 0 1 CCLR0 0 1 0 1 1 0 1 0 1 0 1 TCNT clearing disabled TCNT cleared at TGRA compare match/input capture TCNT cleared at TGRB compare match/input capture TCNT cleared when other channel counters with synchronized clearing or synchronized operation are cleared *1 TCNT clearing disabled TCNT cleared at TGRC compare match/input capture *2 TCNT cleared at TGRD compare match/input capture *2 TCNT cleared when other channel counters with synchronized clearing or synchronized operation are cleared *1 Description Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Rev. 3.00 Jan 11, 2005 page 1102 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TMDR0—Timer Mode Register 0 TMDR3—Timer Mode Register 3 Channel 0: TMDR0 Channel 3: TMDR3 Bit : 7 — Initial value : R/W : 1 — 6 — 1 — 5 BFB 0 R/W 4 BFA 0 R/W H'FF11 H'FE81 TPU0 TPU3 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W Mode 3 to 0 MD3*1 MD2*2 0 0 MD1 0 1 1 0 1 1 * * MD0 0 1 0 1 0 1 0 1 * Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase calculation mode 1 Phase calculation mode 2 Phase calculation mode 3 Phase calculation mode 4 — * : Don't care Notes: 1. MD3 is a reserved bit. Only write 0 to this bit. 2. Phase calculation mode cannot be set for channels 0 and 3. Only write 0 to MD2. Buffer operation A 0 1 Normal TGRA operation Buffer operation of TGRA and TGRC Buffer operation B 0 1 Normal TGRB operation Buffer operation of TGRB and TGRD Rev. 3.00 Jan 11, 2005 page 1103 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TIOR3H—Timer I/O Control Register 3H Bit : 7 IOB3 Initial value : R/W : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FE82 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 TPU3 IOA0 0 R/W TGR3A I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR3A is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR3A is 1 input capture * register * Capture input source is TIOCA3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock *: Don't care TGR3B I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR3B is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR3B is 1 input capture * register * Capture input source is TIOCB3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT4 count-up/ source is channel count-down*1 4/count clock *: Don't care Note: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and φ/1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. Rev. 3.00 Jan 11, 2005 page 1104 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TIOR4—Timer I/O Control Register 4 Bit : 7 IOB3 Initial value : R/W : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FE92 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 TPU4 IOA0 0 R/W TGR4A I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR4A is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR4A is 1 input capture * register * Capture input source is TIOCA4 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at generation of TGR3A source is TGR3A compare match/input capture compare match/ input capture *: Don't care TGR4B I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR4B is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR4B is 1 input capture * register * Capture input source is TIOCB4 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at generation of TGR3C source is TGR3C compare match/input capture compare match/ input capture *: Don't care Rev. 3.00 Jan 11, 2005 page 1105 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TIOR5—Timer I/O Control Register 5 Bit : 7 IOB3 Initial value : R/W : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FEA2 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 TPU5 IOA0 0 R/W TGR5A I/O Control 0 0 0 1 1 0 1 1 * 0 1 0 TGR5A is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR5A is Capture input source is 1 input capture TIOCA5 pin * register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care TGR5B I/O Control 0 0 0 1 1 0 1 1 * 0 1 0 TGR5B is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR5B is Capture input source is 1 input capture TIOCB5 pin * register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Rev. 3.00 Jan 11, 2005 page 1106 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TIOR0H—Timer I/O Control Register 0H Bit : 7 IOB3 Initial value : R/W : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FF12 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 TPU0 IOA0 0 R/W TGR0A I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR0A is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR0A is 1 input capture * register * Capture input source is TIOCA0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT1 count-up/ source is channel count-down 1/count clock *: Don't care TGR0B I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR0B is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR0B is 1 input capture * register * Capture input source is TIOCB0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at TCNT1 count-up/ Capture input source is channel count-down*1 1/count clock *: Don't care Note: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and φ/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. Rev. 3.00 Jan 11, 2005 page 1107 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TIOR1—Timer I/O Control Register 1 Bit : 7 IOB3 Initial value : R/W : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FF22 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 TPU1 IOA0 0 R/W TGR1A I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR1A is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR1A is 1 input capture * register * Capture input source is TIOCA1 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at generation of source is TGR0A channel 0/TGR0A compare match/ compare match/ input capture input capture *: Don't care TGR1B I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR1B is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR1B is 1 input capture * register * Capture input source is TIOCB1 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at generation of TGR0C source is TGR0C compare match/input capture compare match/ input capture *: Don't care Rev. 3.00 Jan 11, 2005 page 1108 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TIOR2—Timer I/O Control Register 2 Bit : 7 IOB3 Initial value : R/W : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FF32 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 TPU2 IOA0 0 R/W TGR2A I/O Control 0 0 0 1 1 0 1 1 * 0 1 0 TGR2A is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR2A is Capture input source is 1 input capture TIOCA2 pin * register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care TGR2B I/O Control 0 0 0 1 1 0 1 1 * 0 1 0 TGR2B is Output disabled 1 output Initial output is 0 compare output 0 register 1 0 1 0 1 0 TGR2B is Capture input source is 1 input capture TIOCB2 pin * register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Rev. 3.00 Jan 11, 2005 page 1109 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TIOR3L—Timer I/O Control Register 3L Bit : 7 IOD3 Initial value : R/W : 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W H'FE83 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W TPU3 TGR3C I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR3C is Output disabled 1 output Initial output is 0 compare 0 register*1 output 1 0 1 0 1 0 TGR3C is 1 input capture * register*1 * Capture input source is TIOCC3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock *: Don't care Note: 1. When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. TGR3D I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR3D is Output disabled 1 output Initial output is 0 compare 0 register*2 output 1 0 1 0 1 0 TGR3D is 1 input capture * register*2 * Capture input source is TIOCD3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT4 count-up/ source is channel count-down*1 4/count clock *: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and φ/1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Rev. 3.00 Jan 11, 2005 page 1110 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TIOR0L—Timer I/O Control Register 0L Bit : 7 IOD3 Initial value : R/W : 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W H'FF13 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W TPU0 TGR0C I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR0C is Output disabled 1 output Initial output is 0 compare 0 register*1 output 1 0 1 0 1 0 TGR0C is 1 input capture * register*1 * Capture input source is TIOCC0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at TCNT1 count-up/ Capture input source is channel count-down 1/count clock *: Don't care Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. TGR0D I/O Control 0 0 0 1 1 0 1 1 0 0 1 1 * 0 TGR0D is Output disabled 1 output Initial output is 0 compare 0 register*2 output 1 0 1 0 1 0 TGR0D is 1 input capture * register*2 * Capture input source is TIOCD0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at TCNT1 count-up/ Capture input source is channel count-down*1 1/count clock *: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and φ/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Rev. 3.00 Jan 11, 2005 page 1111 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TIER0—Timer Interrupt Enable Register 0 TIER3—Timer Interrupt Enable Register 3 Channel 0: TIER0 Channel 3: TIER3 Bit : 7 TTGE Initial value : R/W : 0 R/W 6 — 1 — 5 — 0 — 4 TCIEV 0 R/W H'FF14 H'FE84 TPU0 TPU3 3 TGIED 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR interrupt enable A 0 1 TGFA bit interrupt request (TGIA) disabled TGFA bit interrupt request (TGIA) enabled TGR interrupt enable B 0 1 TGFB bit interrupt request (TGIB) disabled TGFB bit interrupt request (TGIB) enabled TGR interrupt enable C 0 1 TGFC bit interrupt request (TGIC) disabled TGFC bit interrupt request (TGIC) enabled TGR interrupt enable D 0 1 TGFD bit interrupt request (TGID) disabled TGFD bit interrupt request (TGID) enabled Overflow interrupt enable 0 1 TCFV interrupt request (TCIV) disabled TCFV interrupt request (TCIV) enabled A/D conversion start request enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev. 3.00 Jan 11, 2005 page 1112 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TSR0—Timer Status Register 0 TSR3—Timer Status Register 3 Channel 0: TSR0 Channel 3: TSR3 Bit : 7 — Initial value : R/W : 1 — 6 — 1 — 5 — 0 — 4 TCFV 0 R/(W)* H'FF15 H'FE85 TPU0 TPU3 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* Input capture/output compare flag A 0 [Clearing conditions] • When the DTC is started by a TGIA interrupt and the DTC MRB DISEL bit is 0 • When the DMAC is started by a TGIA interrupt and the DMAC DMABCR DTA bit is 1 • Writing 0 to TGFA after reading TGFA = 1 1 [Setting conditions] • When TGRA is functioning as the output compare register and TCNT = TGRA • When TGRA is functioning as the input capture register and the value of TCNT is sent to TGRA by the input capture signal Input capture/output compare flag B 0 [Clearing conditions] • When the DTC is started by a TGIB interrupt and the DTC MRB DISEL bit is 0 • Writing 0 to TGFB after reading TGFB = 1 1 [Setting conditions] • When TGRB is functioning as the output compare register and TCNT = TGRB • When TGRB is functioning as the input capture register and the value of TCNT is sent to TGRB by the input capture signal Input capture/output compare flag C 0 [Clearing conditions] • When the DTC is started by a TGIC interrupt and the DTC MRB DISEL bit is 0 • Writing 0 to TGFC after reading TGFC = 1 1 [Setting conditions] • When TGRC is functioning as the output compare register and TCNT = TGRC • When TGRC is functioning as the input capture register and the value of TCNT is sent to TGRC by the input capture signal Input capture/output compare flag D 0 [Clearing conditions] • When the DTC is started by a TGID interrupt and the DTC MRB DISEL bit is 0 • Writing 0 to TGFD after reading TGFD = 1 1 [Setting conditions] • When TGRD is functioning as the output compare register and TCNT = TGRD • When TGRD is functioning as the input capture register and the value of TCNT is sent to TGRD by the input capture signal Overflow flag 0 [Clearing condition] • Writing 0 to TCFV after reading TCFV = 1 1 [Setting condition] • When the TCNT value overflows (H’FFFF → H’0000) Note: * Only 0 can be written to these bits (to clear these flags). Rev. 3.00 Jan 11, 2005 page 1113 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TCNT0—Timer Counter 0 (up-counter) TCNT0—Timer Counter 1 (up/down-counter*) TCNT0—Timer Counter 2 (up/down-counter*) TCNT0—Timer Counter 3 (up-counter) TCNT0—Timer Counter 4 (up/down-counter*) TCNT0—Timer Counter 5 (up/down-counter*) Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FF16 H'FF26 H'FF36 H'FE86 H'FE96 H'FEA6 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU0 TPU1 TPU2 TPU3 TPU4 TPU5 0 0 Initial value : R/W Note: * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W This register can be used as an up/down counter only in phase calculation mode (and when counting overflows and underflows in other channels in phase calculation mode) In all other cases, this register functions as an up-counter. Rev. 3.00 Jan 11, 2005 page 1114 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TGR0A—Timer General Register 0A TGR0B—Timer General Register 0B TGR0C—Timer General Register 0C TGR0D—Timer General Register 0D TGR1A—Timer General Register 1A TGR1B—Timer General Register 1B TGR2A—Timer General Register 2A TGR2B—Timer General Register 2B TGR3A—Timer General Register 3A TGR3B—Timer General Register 3B TGR3C—Timer General Register 3C TGR3D—Timer General Register 3D TGR4A—Timer General Register 4A TGR4B—Timer General Register 4B TGR5A—Timer General Register 5A TGR5B—Timer General Register 5B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FF18 H'FF1A H'FF1C H'FF1E H'FF28 H'FF2A H'FF38 H'FF3A H'FE88 H'FE8A H'FE8C H'FE8E H'FE98 H'FE9A H'FEA8 H'FEAA 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU0 TPU0 TPU0 TPU0 TPU1 TPU1 TPU2 TPU2 TPU3 TPU3 TPU3 TPU3 TPU4 TPU4 TPU5 TPU5 0 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 3.00 Jan 11, 2005 page 1115 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TCR1—Timer Control Register 1 TCR2—Timer Control Register 2 TCR4—Timer Control Register 4 TCR5—Timer Control Register 5 Channel 1: TCR1 Channel 2: TCR2 Channel 4: TCR4 Channel 5: TCR5 Bit : 7 — Initial value : R/W : 0 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W H'FF20 H'FF30 H'FE90 H'FEA0 TPU1 TPU2 TPU4 TPU5 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W CKEG1 CKEG0 Time prescaler 2, 1, 0 TCR1 0 0 0 Internal clock: counts on φ/1 1 1 1 0 1 0 1 0 1 0 1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on φ/256 Counts on TCNT2 overflow/underflow Note: This setting is ignored when channel 1 is in phase counting mode. TCR2 0 0 0 Internal clock: counts on φ/1 1 1 1 0 1 0 1 0 1 0 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input 1 Internal clock: counts on φ/1024 Note: This setting is ignored when channel 2 is in phase counting mode. TCR4 0 0 1 1 0 1 0 1 0 1 0 1 0 Internal clock: counts on φ/1 Internal clock: counts on ø/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on φ/1024 1 Counts on TCNT5 overflow/underflow Note: This setting is ignored when channel 4 is in phase counting mode. TCR5 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on φ/256 External clock: counts on TCLKD pin input Note: This setting is ignored when channel 5 is in phase counting mode. Clock edge 1, 0 CKEG1 0 1 CKEG0 0 1 — Counts on rising edge Counts on falling edge Counts on both edges Description Note: Internal clock edge selection is valid only when the input clock is φ/4 or slower. This setting is ignored when the input clock is φ/1 or an overflow or underflow in another channel is selected. Counter clear 2, 1, 0 Reserve*2 0 CCLR1 0 1 CCLR0 0 1 0 1 TCNT clearing disabled TCNT cleared at TGRA compare match/input capture TCNT cleared at TGRB compare match/input capture TCNT cleared when other channel counters with synchronized clearing or synchronized operation are cleared *1 Description Notes: 1. Sync operation is selected by setting 1 in the TSYR SYNC bit. 2. Bit 7 of channels 1, 2, 4, and 5 is reserved. This bit always returns 0 when read, and cannot be written to. Rev. 3.00 Jan 11, 2005 page 1116 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TMDR1—Timer Mode Register 1 TMDR2—Timer Mode Register 2 TMDR4—Timer Mode Register 4 TMDR5—Timer Mode Register 5 Channel 1: TMDR1 Channel 2: TMDR2 Channel 4: TMDR4 Channel 5: TMDR5 Bit : 7 — Initial value : R/W : 1 — Mode 3 to 0 MD3*1 0 MD2*2 0 MD1 0 1 1 0 1 1 * * MD0 0 1 0 1 0 1 0 1 * H'FF21 H'FF31 H'FE91 H'FEA1 TPU1 TPU2 TPU4 TPU5 6 — 1 — 5 — 0 — 4 — 0 — 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase calculation mode 1 Phase calculation mode 2 Phase calculation mode 3 Phase calculation mode 4 — * : Don’t care Notes: 1. MD3 is a reserved bit. Only write 0 to this bit. 2. Phase calculation mode cannot be set for channels 0 and 3. Only write 0 to MD2. Rev. 3.00 Jan 11, 2005 page 1117 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TIER1—Timer Interrupt Enable Register 1 TIER2—Timer Interrupt Enable Register 2 TIER4—Timer Interrupt Enable Register 4 TIER5—Timer Interrupt Enable Register 5 Channel 1: TIER1 Channel 2: TIER2 Channel 4: TIER4 Channel 5: TIER5 Bit : 7 TTGE Initial value : R/W : 0 R/W 6 — 1 — 5 TCIEU 0 R/W 4 TCIEV 0 R/W H'FF24 H'FF34 H'FE94 H'FEA4 TPU1 TPU2 TPU4 TPU5 3 — 0 — 2 — 0 — 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR interrupt enable A 0 1 TGFA bit interrupt request (TGIA) disabled TGFA bit interrupt request (TGIA) enabled TGR interrupt enable B 0 1 TGFB bit interrupt request (TGIB) disabled TGFB bit interrupt request (TGIB) enabled Overflow interrupt enable 0 1 TCFV interrupt request (TCIV) disabled TCFV interrupt request (TCIV) enabled Underflow interrupt enable 0 1 TCFU interrupt request (TCIU) disabled TCFU interrupt request (TCIU) enabled A/D conversion start request enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev. 3.00 Jan 11, 2005 page 1118 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TSR1—Timer Status Register 1 TSR2—Timer Status Register 2 TSR4—Timer Status Register 4 TSR5—Timer Status Register 5 Channel 1: TSR1 Channel 2: TSR2 Channel 4: TSR4 Channel 5: TSR5 Bit : 7 TCFD Initial value : R/W : 1 R 6 — 1 — 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 H'FF25 H'FF35 H'FE95 H'FEA5 TPU1 TPU2 TPU4 TPU5 2 — 0 — 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* — 0 — Input capture/output compare flag A 0 [Clearing conditions] • When the DTC is started by a TGIA interrupt and the DTC MRB DISEL bit is 0 • When the DMAC is started by a TGIA interrupt and the DMAC DMABCR DTA bit is 1 • Writing 0 to TGFA after reading TGFA = 1 [Setting conditions] • When TGRA is functioning as the output compare register and TCNT = TGRA • When TGRA is functioning as the input capture register and the value of TCNT is sent to TGRA by the input capture signal 1 Input capture/output compare flag B 0 [Clearing conditions] • When the DTC is started by a TGIB interrupt and the DTC MRB DISEL bit is 0 • Writing 0 to TGFB after reading TGFB = 1 [Setting conditions] • When TGRB is functioning as the output compare register and TCNT = TGRB • When TGRB is functioning as the input capture register and the value of TCNT is sent to TGRB by the input capture signal 1 Overflow flag 0 1 [Clearing condition] • Writing 0 to TCFV after reading TCFV = 1 [Setting condition] • When the TCNT value overflows (H'FFFF → H'0000) Underflow flag 0 1 [Clearing condition] • Writing 0 to TCFU after reading TCFU = 1 [Setting condition] • When the TCNT value underflows (H'0000 → H'FFFF) Count direction flag 0 1 TCNT counts down TCNT counts up Note: * Only 0 can be written to these bits (to clear these flags). Rev. 3.00 Jan 11, 2005 page 1119 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TSTR—Timer Start Register Bit : 7 — Initial value : R/W : 0 — 6 — 0 — 5 CST5 0 R/W 4 CST4 0 R/W H'FEB0 3 CST3 0 R/W 2 CST2 0 R/W 1 TPU Common 0 CST0 0 R/W CST1 0 R/W Counter start 5 to 0 0 1 TCNTn counting operation disabled TCNTn counting operation enabled (n = 5 to 0) Note: When the TIOC pin is operating as an output pin, writing 0 to a CST bit disables counting. The TIOC pins output compare output level is maintained. When a CST bit is 0, the output level of the pin is updated to the set initial output value by writing to TIOR. TSYR—Timer Synchro Register Bit : 7 — Initial value : R/W : 0 — 6 — 0 — 5 SYNC5 0 R/W 4 SYNC4 0 R/W H'FEB1 3 SYNC3 0 R/W 2 SYNC2 0 R/W 1 TPU Common 0 SYNC0 0 R/W SYNC1 0 R/W Timer sync 5 to 0 0 1 TCNTn operate independently (TCNTs are preset and cleared independently of other channels) TCNTn operate in sync mode. Synchronized TCNT presetting and clearing enabled (n = 5 to 0) Notes: 1. The SYNC bit of a minimum of two channels must be set to 1 in order to select sync operation. 2. To enable sync clearing, in addition to the SYNC bits, the TCR CCLR2 to CCLR0 bits must be set for the TCNT clearing factors. Rev. 3.00 Jan 11, 2005 page 1120 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register IPRA—Interrupt Priority Register A IPRB—Interrupt Priority Register B IPRC—Interrupt Priority Register C IPRD—Interrupt Priority Register D IPRE—Interrupt Priority Register E IPRF—Interrupt Priority Register F IPRG—Interrupt Priority Register G IPRH—Interrupt Priority Register H IPRI—Interrupt Priority Register I IPRJ—Interrupt Priority Register J IPRK—Interrupt Priority Register K IPRL—Interrupt Priority Register L IPRO—Interrupt Priority Register O Bit : 7 — Initial value : R/W : 0 — 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECE 3 — 0 — 2 IPR2 1 R/W Interrupt Controller 1 IPR1 1 R/W 0 IPR0 1 R/W Interrupt factors vs IPR Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK IPRL IPRO IRQ0 IRQ2 IRQ3 IRQ6 IRQ7 Watchdog timer 0 PC brake TPU channel 0 TPU channel 2 TPU channel 4 8-bit timer channel 0 DMAC SCI channel 1 8-bit timer 2, 3 SCI channel 3 Bit 6 to 4 IRQ1 IRQ4 IRQ5 DTC Refresh timer ADC Watchdog timer 1 TPU channel 1 TPU channel 3 ITPU channel 5 8-bit timer channel 1 SCI channel 0 SCI channel 2 IIC (optional) SCI channel 4 2 to 0 Rev. 3.00 Jan 11, 2005 page 1121 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register ABWCR—Bus Width Control Register Bit : 7 ABW7 Mode 5 to 7 : Initial value : R/W Mode 4 Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W : 1 R/W 1 R/W 1 R/W 1 R/W 6 ABW6 5 ABW5 4 ABW4 H'FED0 3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W Bus Controller 1 ABW1 1 R/W 0 R/W 0 ABW0 1 R/W 0 R/W Area 7 to 0 bus width control 0 1 Sets area n to 16-bit access Sets area n to 8-bit access (n = 7 to 0) ASTCR—Access State Control Register Bit : 7 AST7 Initial value : R/W : 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W H'FED1 3 AST3 1 R/W 2 AST2 1 R/W 1 Bus Controller 0 AST0 1 R/W AST1 1 R/W Area 7 to 0 access state control 0 1 Area n set as 2-state access area Insertion of wait states in area n external area access is disabled External area access of area n set as 3-state access area Insertion of wait states in area n external area access is enabled (n = 7 to 0) Rev. 3.00 Jan 11, 2005 page 1122 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register WCRH—Wait Control Register H Bit : 7 W71 Initial value : R/W : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W H'FED2 3 W51 1 R/W 2 W50 1 R/W 1 Bus Controller 0 W40 1 R/W W41 1 R/W Area 4 wait control 1, 0 W41 0 1 W40 0 1 0 1 Area 5 wait control 1, 0 W51 0 1 W50 0 1 0 1 Area 6 wait control 1, 0 W61 0 1 W60 0 1 0 1 Area 7 wait control 1, 0 W71 0 1 W70 0 1 0 1 Description No program wait inserted when accessing external area of area 7 1 program wait state inserted when accessing external area of area 7 2 program wait states inserted when accessing external area of area 7 3 program wait states inserted when accessing external area of area 7 Description No program wait inserted when accessing external area of area 6 1 program wait state inserted when accessing external area of area 6 2 program wait states inserted when accessing external area of area 6 3 program wait states inserted when accessing external area of area 6 Description No program wait inserted when accessing external area of area 5 1 program wait state inserted when accessing external area of area 5 2 program wait states inserted when accessing external area of area 5 3 program wait states inserted when accessing external area of area 5 Description No program wait inserted when accessing external area of area 4 1 program wait state inserted when accessing external area of area 4 2 program wait states inserted when accessing external area of area 4 3 program wait states inserted when accessing external area of area 4 Rev. 3.00 Jan 11, 2005 page 1123 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register WCRL—Wait Control Register Bit : 7 W31 Initial value : R/W : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W H'FED3 3 W11 1 R/W 2 W10 1 R/W 1 Bus Controller 0 W00 1 R/W W01 1 R/W Area 0 wait control W01 0 1 W00 0 1 0 1 Area 1 wait control W11 0 1 W10 0 1 0 1 Area 2 wait control W21 0 1 W20 0 1 0 1 Area 3 wait control W31 0 1 W30 0 1 0 1 Description No program wait inserted when accessing external area of area 3 1 program wait state inserted when accessing external area of area 3 2 program wait states inserted when accessing external area of area 3 3 program wait states inserted when accessing external area of area 3 Description No program wait inserted when accessing external area of area 2 1 program wait state inserted when accessing external area of area 2 2 program wait states inserted when accessing external area of area 2 3 program wait states inserted when accessing external area of area 2 Description No program wait inserted when accessing external area of area 1 1 program wait state inserted when accessing external area of area 1 2 program wait states inserted when accessing external area of area 1 3 program wait states inserted when accessing external area of area 1 Description No program wait inserted when accessing external area of area 0 1 program wait state inserted when accessing external area of area 0 2 program wait states inserted when accessing external area of area 0 3 program wait states inserted when accessing external area of area 0 Rev. 3.00 Jan 11, 2005 page 1124 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register BCRH—Bus Control Register H Bit : 7 ICIS1 Initial value : R/W : 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W H'FED4 3 0 R/W 2 0 R/W 1 0 Bus Controller 0 0 R/W BRSTRM BRSTS1 BRSTS0 RMTS2 RMTS1 RMTS0 R/W RAM type select RMTS2 RMTS1 RMTS0 0 0 1 1 1 0 1 0 1 1 Normal area DRAM area Contiguous DRAM area Area 5 Area 4 Normal area Area 3 Area 2 DRAM area DRAM area Normal area Note: When all areas selected in the DRAM area are set for 8-bit access, the PF2 pin can be used as an I/O port or BREQO or WAIT. When set for contiguous DRAM the bus widths for areas 2 to 5 and the number of access states (number of programmable waits) must be set to the same values. Do not attempt to set combinations other than those shown in the table. Burst cycle select 0 0 1 Burst access = 4 words max Burst access = 8 words max Burst cycle select 1 0 1 Burst cycle = 1 state Burst cycle = 2 states Burst ROM enable 0 1 Area 0 is basic bus interface Area 0 is burst ROM interface Idle cycle insertion 0 0 1 No idle cycle is inserted when an external read cycle follows an external write cycle An idle cycle is inserted when an external read cycle follows an external write cycle Idle cycle insertion 1 0 1 No idle cycle is inserted when an external read cycle follows an external read cycle of another area An idle cycle is inserted when an external read cycle follows an external read cycle of another area Rev. 3.00 Jan 11, 2005 page 1125 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register BCRL—Bus Control Register L Bit : 7 0 R/W 6 0 R/W 5 — 0 — 4 OES 0 R/W H'FED5 3 DDS 1 R/W 2 RCTS 0 R/W 1 Bus Controller 0 WAITE 0 R/W BRLE BREQOE Initial value : R/W : WDBE 0 R/W WAIT pin enable 0 1 Wait input via WAIT pin disabled The WAIT pin can be used as an I/O port Wait input via WAIT pin enabled Write data buffer enable 0 1 Do not use write data buffer function Use write data buffer function Read CAS timing select 0 1 CAS signal output timing is the same when reading and writing When reading, the CAS signal is asserted one half cycle faster than when writing DACK timing select 0 When performing DMAC single address transmission to the DRAM space, always perform full access. The DACK signal level changes to low from Tr or T1 cycle Burst access is also available when performing DMAC single address transmission to the DRAM space. The DACK signal level changes to low from TC1 or T2 cycle 1 OE select 0 1 CS3 pin used as port or as CS3 signal output When only area 2 is set as DRAM, or when areas 2 to 5 are set as contiguous DRAM space, the CS3 pin is used as the OE pin BREQO pin enable 0 1 BREQO output disabled. BREQO can be used as an I/O port BREQO output enabled Bus release enable 0 1 Release of external bus privileges disabled. BREQ, BACK, and BREQO can be used as I/O ports Release of external bus privileges enabled Rev. 3.00 Jan 11, 2005 page 1126 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register MCR—Memory Control Register Bit : 7 TPC Initial value : R/W : 0 R/W 6 BE 0 R/W 5 RCDM 0 R/W 4 CW2 0 R/W H'FED6 3 MXC1 0 R/W 2 MXC0 0 R/W 1 RLW1 0 R/W Bus Controller 0 RLW0 0 R/W Refresh cycle wait control 1, 0 RLW1 RLW0 0 1 Multiplex shift count 1, 0 MXC1 MXC0 0 0 Description 8-bit shift (1) When set for 8-bit access space: Row addresses A23 to A8 are targets of comparison (2) When set for 16-bit access space: Row addresses A23 to A9 are targets of comparison 9-bit shift (1) When set for 8-bit access space: Row addresses A23 to A9 are targets of comparison (2) When set for 16-bit access space: Row addresses A23 to A10 are targets of comparison 10-bit shift (1) When set for 8-bit access space: Row addresses A23 to A10 are targets of comparison (2) When set for 16-bit access space: Row addresses A23 to A11 are targets of comparison — 0 1 0 1 Description Do not insert wait state Insert 1 wait state Insert 2 wait states Insert 3 wait states 1 1 0 1 Reserved bit RAS down mode 0 1 DRAM interface: RAS up mode selected DRAM interface: RAS down mode selected Burst access enable 0 1 Burst access disabled (permanently full access) DRAM space accessed in high-speed page mode TP cycle control 0 1 One precharge cycle state inserted Two precharge cycle states inserted Rev. 3.00 Jan 11, 2005 page 1127 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register DRAMCR—DRAM Control Register Bit : 7 RFSHE Initial value : R/W : 0 R/W 6 CBRM 0 R/W 5 RMODE 0 R/W 4 CMF 0 R/W H'FED7 3 CMIE 0 R/W 2 CKS2 0 R/W 1 Bus Controller 0 CKS0 0 R/W CKS1 0 R/W Refresh counter clock select CKS2 0 CKS1 0 1 1 0 1 CKS0 0 1 0 1 0 1 0 1 Compare match interrupt enable 0 1 CMF flag interrupt request (CMI) disabled CMF flag interrupt request (CMI) enabled Description No counting operation Counting on φ/2 Counting on φ/8 Counting on φ/32 Counting on φ/128 Counting on φ/512 Counting on φ/2048 Counting on φ/4096 Compare match flag 0 1 [Clearing condition] • Writing 0 to CMF flag after reading CMF = 1 [Setting condition] • When RTCNT = RTCOR Refresh mode 0 1 Do not perform self-refresh in software standby mode Perform self-refresh in software standby mode CBR refresh mode 0 1 Refresh control 0 1 Do not perform refresh control Perform refresh control External access enabled at CAS-before-RAS refresh External access disabled at CAS-before-RAS refresh Rev. 3.00 Jan 11, 2005 page 1128 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register RTCNT—Refresh Timer Counter Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FED8 3 0 R/W 2 0 R/W 1 0 Bus Controller 0 0 R/W Initial value : R/W : R/W RTCOR—Refresh Time Constant Register Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FED9 3 1 R/W 2 1 R/W 1 1 Bus Controller 0 1 R/W Initial value : R/W : R/W RAMER—RAM Emulation Register Bit : 7 — Initial value : R/W : 0 R 6 — 0 R 5 — 0 R/W 4 — 0 R/W H'FEDB 3 RAMS 0 R/W 2 RAM2 0 R/W 1 RAM1 0 R/W FLASH 0 RAM0 0 R/W Flash memory area selection RAMS RAM1 0 1 1 1 1 1 1 1 1 RAM Select 0 1 Emulation not selected Program/erase-protection of all flash memory blocks is disabled Emulation selected Program/erase-protection of all flash memory blocks is enabled * 0 0 0 0 1 1 1 1 RAM1 RAM0 * 0 0 1 1 0 0 1 1 * 0 1 0 1 0 1 0 1 Addresses Block name H'FFD000–H'FFDFFF RAM area 4 kbytes H'000000–H'000FFF H'001000–H'001FFF H'002000–H'002FFF H'003000–H'003FFF H'004000–H'004FFF H'005000–H'005FFF H'006000–H'006FFF H'007000–H'007FFF EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) * : Don’t care Rev. 3.00 Jan 11, 2005 page 1129 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register MAR0AH—Memory Address Register 0AH MAR0AL—Memory Address Register 0AL Bit MAR R/W Bit MAR R/W : : : : : 31 — 0 — 15 30 — 0 — 14 29 — 0 — 13 28 — 0 — 12 27 — 0 — 11 26 — 0 — 10 25 — 0 — 9 24 — 0 H'FEE0 H'FEE2 23 * 22 * 21 * 20 * 19 * 18 * 17 * DMAC DMAC 16 * Initial value : — R/W R/W R/W R/W R/W R/W R/W R/W 8 7 6 5 4 3 2 1 0 Initial value : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W In short address mode: Specifies transfer destination/transfer source address In full address mode: Not used * : Undefined IOAR0A—I/O Address Register 0A IOAR1A—I/O Address Register 1A Bit IOAR R/W : : * * * * * * * * 15 14 13 12 11 10 9 8 H'FEE4 H'FEF4 7 * 6 * 5 * 4 * 3 * 2 * 1 * DMAC DMAC 0 * Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W In short address mode: Specifies transfer destination/transfer source address In full address mode: Not used * : Undefined Rev. 3.00 Jan 11, 2005 page 1130 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register ETCR0A—Transfer Count Register 0A Bit ETCR0A R/W Sequential mode, Idle mode, and Normal mode Repeat mode Block transfer mode : : * * * * * * * * 15 14 13 12 11 10 9 8 H'FEE6 7 6 5 4 3 2 DMAC 1 0 Initial value : : * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter Holds number of transfers Holds block size Transfer counter Block size counter *: Undefined MAR0BH—Memory Address Register 0BH MAR0BL—Memory Address Register 0BL Bit MAR0BH R/W Bit MAR0BL R/W : : : : : * * * * * * * * 31 — 0 — 15 30 — 0 — 14 29 — 0 — 13 28 — 0 — 12 27 — 0 — 11 26 — 0 — 10 25 — 0 — 9 24 — 0 H'FEE8 H'FEEA 23 * 22 * 21 * 20 * 19 * 18 * 17 * DMAC DMAC 16 * Initial value : — R/W R/W R/W R/W R/W R/W R/W R/W 8 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W In short address mode: Specifies transfer destination/transfer source address In full address mode: Specifies transfer destination *: Undefined Rev. 3.00 Jan 11, 2005 page 1131 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register IOAR0B—I/O Address Register 0B IOAR1B—I/O Address Register 1B Bit IOAR0B R/W : : * * * * * * * * 15 14 13 12 11 10 9 8 H'FEEC H'FEFC 7 * 6 * 5 * 4 * 3 * 2 * 1 * DMAC DMAC 0 * Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W In short address mode: Specifies transfer destination/transfer source address In full address mode: Not used *: Undefined ETCR0B—Transfer Count Register 0B Bit ETCR0B R/W Sequential mode and idle mode Repeat mode Block transfer mode : : * * * * * * * * 15 14 13 12 11 10 9 8 H'FEEE 7 6 5 4 3 2 DMAC 1 0 Initial value : * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter Holds number of transfers Block transfer counter Transfer counter *: Undefined Note: Not used in normal mode. Rev. 3.00 Jan 11, 2005 page 1132 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register MAR1AH—Memory Address Register 1AH MAR1AL—Memory Address Register 1AL Bit MAR1AH R/W Bit MAR1AL R/W : : : : : * * * * * * * * 31 — 0 — 15 30 — 0 — 14 29 — 0 — 13 28 — 0 — 12 27 — 0 — 11 26 — 0 — 10 25 — 0 — 9 24 — 0 H'FEF0 H'FEF2 23 * 22 * 21 * 20 * 19 * 18 * 17 * DMAC DMAC 16 * Initial value : — R/W R/W R/W R/W R/W R/W R/W R/W 8 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W In short address mode: Specifies transfer destination/transfer source address In full address mode: Not used *: Undefined ETCR1A—Transfer Count Register 1A Bit ETCR1A R/W Sequential mode, Idle mode, and Normal mode Repeat mode Block transfer mode : : * * * * * * * * 15 14 13 12 11 10 9 8 H'FEF6 7 6 5 4 3 2 DMAC 1 0 Initial value : * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter Holds number of transfers Holds block size Transfer counter Block size counter *: Undefined Rev. 3.00 Jan 11, 2005 page 1133 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register MAR1BH—Memory Address Register 1BH MAR1BL—Memory Address Register 1BL Bit MAR1BH R/W Bit MAR1BL R/W : : : : : * * * * * * * * 31 — 0 — 15 30 — 0 — 14 29 — 0 — 13 28 — 0 — 12 27 — 0 — 11 26 — 0 — 10 25 — 0 — 9 24 — 0 H'FEF8 H'FEFA 23 * 22 * 21 * 20 * 19 * DMAC DMAC 18 * 17 * 16 * Initial value : — R/W R/W R/W R/W R/W R/W R/W R/W 8 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W In short address mode: Specifies transfer destination/transfer source address In full address mode: Not used *: Undefined ETCR1B—Transfer Count Register 1B Bit ETCR1B R/W Sequential mode and idle mode Repeat mode Block transfer mode : : * * * * * * * * 15 14 13 12 11 10 9 8 H'FEFE 7 6 5 4 3 DMAC 2 1 0 Initial value : * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter Holds number of transfers Block transfer counter Transfer counter *: Undefined Note: Not used in normal mode. Rev. 3.00 Jan 11, 2005 page 1134 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register P1DR—Port 1 Data Register Bit : 7 P17DR Initial value : R/W : 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4 P14DR 0 R/W H'FF00 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 Port P10DR 0 R/W P2DR—Port 2 Data Register Bit : 7 P27DR Initial value : R/W : 0 R/W 6 P26DR 0 R/W 5 P25DR 0 R/W 4 P24DR 0 R/W H'FF01 3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W 0 Port P20DR 0 R/W P3DR—Port 3 Data Register Bit : 7 P37DR Initial value : R/W : 0 R/W 6 P36DR 0 R/W 5 P35DR 0 R/W 4 P34DR 0 R/W H'FF02 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 Port P30DR 0 R/W P5DR—Port 5 Data Register Bit : 7 — R/W : — 6 — — 5 — — 4 — — H'FF04 3 — — 2 P52DR 0 R/W 1 P51DR 0 R/W 0 Port P50DR 0 R/W Initial value : undefined undefined undefined undefined undefined P7DR—Port 7 Data Register Bit : 7 P77DR Initial value : R/W : 0 R/W 6 P76DR 0 R/W 5 P75DR 0 R/W 4 P74DR 0 R/W H'FF06 3 P73DR 0 R/W 2 P72DR 0 R/W 1 P71DR 0 R/W 0 Port P70DR 0 R/W Rev. 3.00 Jan 11, 2005 page 1135 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register P8DR—Port 8 Data Register Bit : 7 — Initial value : undefined R/W : — 6 P86DR 0 R/W 5 P85DR 0 R/W 4 P84DR 0 R/W H'FF07 3 P83DR 0 R/W 2 P82DR 0 R/W 1 P81DR 0 R/W 0 Port P80DR 0 R/W PADR—Port A Data Register Bit : 7 PA7DR Initial value : R/W : 0 R/W 6 PA6DR 0 R/W 5 PA5DR 0 R/W 4 PA4DR 0 R/W H'FF09 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 Port PA0DR 0 R/W PBDR—Port B Data Register Bit : 7 PB7DR Initial value : R/W : 0 R/W 6 PB6DR 0 R/W 5 PB5DR 0 R/W 4 PB4DR 0 R/W H'FF0A 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W 0 Port PB0DR 0 R/W PCDR—Port C Data Register Bit : 7 PC7DR Initial value : R/W : 0 R/W 6 PC6DR 0 R/W 5 PC5DR 0 R/W 4 PC4DR 0 R/W H'FF0B 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W 0 Port PC0DR 0 R/W PDDR—Port D Data Register Bit : 7 PD7DR Initial value : R/W : 0 R/W 6 PD6DR 0 R/W 5 PD5DR 0 R/W 4 PD4DR 0 R/W H'FF0C 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W 0 Port PD0DR 0 R/W Rev. 3.00 Jan 11, 2005 page 1136 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register PEDR—Port E Data Register Bit : 7 PE7DR Initial value : R/W : 0 R/W 6 PE6DR 0 R/W 5 PE5DR 0 R/W 4 PE4DR 0 R/W H'FF0D 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W 0 Port PE0DR 0 R/W PFDR—Port F Data Register Bit : 7 PF7DR Initial value : R/W : 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4 PF4DR 0 R/W H'FF0E 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W 0 Port PF0DR 0 R/W PGDR—Port G Data Register Bit : 7 — R/W : — 6 — — 5 — — 4 0 R/W H'FF0F 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Port PG4DR PG3DR PG2DR PG1DR PG0DR Initial value : Undefined Undefined Undefined Rev. 3.00 Jan 11, 2005 page 1137 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register DMAWER—DMA Write Enable Register Bit DMAWER R/W : : : 7 — 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 H'FF60 2 WE1A 0 R/W 1 WE0B 0 R/W 0 WE0A 0 R/W DMAC WE1B 0 R/W Initial value : Write enable 0A 0 1 Write enable 0B 0 1 Write enable 1A 0 1 Write enable 1B 0 1 Disables writing to all DMACR1B bits, DMABCR bits 11, 7, and 3, and DMATCR bit 5 Enables writing to all DMACR1B bits, DMABCR bits 11, 7, and 3, and DMATCR bit 5 Disables writing to all DMACR1A bits, and DMABCR bits 10, 6, and 2 Enables writing to all DMACR1A bits, and DMABCR bits 10, 6, and 2 Disables writing to all DMACR0B bits, DMABCR bits 9, 5, and 1, and DMATCR bit 4 Enables writing to all DMACR0B bits, DMABCR bits 9, 5, and 1, and DMATCR bit 4 Disables writing to all DMACR0A bits, and DMABCR bits 8, 4, and 0 Enables writing to all DMACR0A bits, and DMABCR bits 8, 4, and 0 DMATCR—DMA Terminal Control Register Bit DMATCR R/W : : : 7 — 0 — 6 — 0 — 5 TEE1 0 R/W 4 TEE0 0 R/W H'FF61 3 — 0 — 2 — 0 — 1 — 0 — 0 — 0 — DMAC Initial value : Transfer end pin enable 0 0 1 Disables TEND0 pin output Enables TEND0 pin output Transfer end pin enable 1 0 1 Disables TEND1 pin output Enables TEND1 pin output Rev. 3.00 Jan 11, 2005 page 1138 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register DMACR0A—DMA Control Register 0A DMACR0B—DMA Control Register 0B DMACR1A—DMA Control Register 1A DMACR1B—DMA Control Register 1B Full address mode Bit DMACRA R/W : : : 15 DTSZ 0 R/W 14 SAID 0 R/W 13 SAIDE 0 R/W 12 BLKDIR 0 R/W H'FF62 H'FF63 H'FF64 H'FF65 DMAC DMAC DMAC DMAC 11 BLKE 0 R/W 10 — 0 R/W 9 — 0 R/W 8 — 0 R/W Initial value : Block Direction/Block Enable 0 0 1 1 0 1 Transfer in normal mode Transfer in block transfer mode, destination is block area Transfer in normal mode Transfer in block transfer mode, source is block area Source Address Increment/Decrement 0 0 1 MARA is fixed MARA is incremented after a data transfer • When DTSZ = 0, MARA is incremented by 1 after a transfer • When DTSZ = 1, MARA is incremented by 2 after a transfer MARA is fixed MARA is decremented after a data transfer • When DTSZ = 0, MARA is decremented by 1 after a transfer • When DTSZ = 1, MARA is decremented by 2 after a transfer 1 0 1 Data Transfer Size 0 1 Byte-size transfer Word-size transfer Rev. 3.00 Jan 11, 2005 page 1139 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register Full address mode Bit DMACRB R/W : : : 7 — 0 R/W 6 DAID 0 R/W 5 DAIDE 0 R/W 4 — 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W Initial value : Data Transfer Factor DTF3 DTF2 DTF1 DTF0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 — Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input* Activated by DREQ pin low-level input Activated by SCI channel 0 transmit-data-empty interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmit-data-empty interrupt Activated by SCI channel 1 reception complete interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt — — Block Transfer Mode — — Activated by DREQ pin falling edge input Activated by DREQ pin low-level input — — Auto-request (cycle steal) Auto-request (burst) — — — — — — — — Normal Mode Note: * Detected as a low level in the first transfer after transfer is enabled. Destination Address Increment/Decrement 0 0 1 MARB is fixed MARB is incremented after a data transfer • When DTSZ = 0, MARB is incremented by 1 after a transfer • When DTSZ = 1, MARB is incremented by 2 after a transfer MARB is fixed MARB is decremented after a data transfer • When DTSZ = 0, MARB is decremented by 1 after a transfer • When DTSZ = 1, MARB is decremented by 2 after a transfer 1 0 1 Rev. 3.00 Jan 11, 2005 page 1140 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register Short address mode Bit DMACR Initial value Read/Write 7 DTSZ 0 R/W 6 DTID 0 R/W 5 RPE 0 R/W 4 DTDIR 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W Channel A 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Data Transfer Direction 0 1 0 1 0 1 Transfer with MAR as source address and IOAR as destination address Transfer with IOAR as source address and MAR as destination address Transfer with MAR as source address and DACK pin as write strobe Transfer with DACK pin as read strobe and MAR as destination address — Activated by A/D converter conversion end interrupt — — Activated by DREQ pin falling edge input Activated by DREQ pin low-level input 1 DTF1 0 R/W 0 DTF0 0 R/W Channel B Data Transfer Factor Activated by SCI channel 0 transmit-dataempty interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmit-dataempty interrupt Activated by SCI channel 1 reception complete interrupt Activated by TPU channel 0 compare match/ input capture A interrupt Activated by TPU channel 1 compare match/ input capture A interrupt Activated by TPU channel 2 compare match/ input capture A interrupt Activated by TPU channel 3 compare match/ input capture A interrupt Activated by TPU channel 4 compare match/ input capture A interrupt Activated by TPU channel 5 compare match/ input capture A interrupt — — Repeat Enable 0 1 0 1 0 1 Transfer in sequential mode (no transfer end interrupt) Transfer in sequential mode (with transfer end interrupt) Transfer in repeat mode (no transfer end interrupt) Transfer in idle mode (with transfer end interrupt) Data Transfer Increment/Decrement 0 MAR is incremented after a data transfer • When DTSZ = 0, MAR is incremented by 1 after a transfer • When DTSZ = 1, MAR is incremented by 2 after a transfer MAR is decremented after a data transfer • When DTSZ = 0, MAR is decremented by 1 after a transfer • When DTSZ = 1, MAR is decremented by 2 after a transfer 1 Data Transfer Size 0 1 Byte-size transfer Word-size transfer Rev. 3.00 Jan 11, 2005 page 1141 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register DMABCR—DMA Band Control Register Short address mode Bit : 15 FAE1 0 R/W 14 FAE0 0 R/W 13 SAE1 0 R/W 12 SAE0 0 R/W H'FF66 DMAC 11 DTA1B 0 R/W 10 DTA1A 0 R/W 9 DTA0B 0 R/W 8 DTA0A 0 R/W DMABCRH : Initial value : R/W : Data transfer acknowledge 0A 0 1 Clearing of selected internal interrupt factor at DMA transfer disabled Clearing of selected internal interrupt factor at DMA transfer enabled Data transfer acknowledge 0B 0 1 Clearing of selected internal interrupt factor at DMA transfer disabled Clearing of selected internal interrupt factor at DMA transfer enabled Data transfer acknowledge 1A 0 1 Clearing of selected internal interrupt factor at DMA transfer disabled Clearing of selected internal interrupt factor at DMA transfer enabled Data transfer acknowledge 1B 0 1 Clearing of selected internal interrupt factor at DMA transfer disabled Clearing of selected internal interrupt factor at DMA transfer enabled Single address enable 0 0 1 0 1 Transfer in dual address mode Transfer in single address mode Single address enable 1 Transfer in dual address mode Transfer in single address mode Full address enable 0 0 1 Short address mode Full address mode Full address enable 1 0 1 Short address mode Full address mode Rev. 3.00 Jan 11, 2005 page 1142 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register Bit : 7 DTE1B 0 R/W 6 DTE1A 0 R/W 5 DTE0B 0 R/W 4 DTE0A 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W DMABCRL : Initial value : R/W : DTIE1B DTIE1A DTIE0B DTIE0A Data transfer interrupt enable 0A 0 1 Transfer end interrupt disabled Transfer end interrupt enabled Data transfer interrupt enable 0B 0 1 Transfer end interrupt disabled Transfer end interrupt enabled Data transfer interrupt enable 1A 0 1 Transfer end interrupt disabled Transfer end interrupt enabled Data transfer interrupt enable 1B 0 1 Transfer end interrupt disabled Transfer end interrupt enabled Data transfer enable 0A 0 1 Data transfer disabled Data transfer enabled Data transfer enable 0B 0 1 Data transfer disabled Data transfer enabled Data transfer enable 1A 0 1 Data transfer disabled Data transfer enabled Data transfer enable 1B 0 1 Data transfer disabled Data transfer enabled Rev. 3.00 Jan 11, 2005 page 1143 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register Full address mode Bit : 15 FAE1 0 R/W 14 FAE0 0 R/W 13 — 0 R/W 12 — 0 R/W 11 DTA1 0 R/W 10 — 0 R/W 9 DTA0 0 R/W 8 — 0 R/W DMABCRH : Initial value : R/W : Data transfer acknowledge 0 0 Clearing of selected internal interrupt source at time of DMA transfer is disabled 1 Clearing of selected internal interrupt source at time of DMA transfer is enabled Data transfer acknowledge 1 0 1 Full address enable 0 0 Short address mode 1 Full address mode Full address enable 1 0 Short address mode 1 Full address mode Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled Rev. 3.00 Jan 11, 2005 page 1144 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register Bit : 7 DTME1 0 R/W 6 DTE1 0 R/W 5 DTME0 0 R/W 4 DTE0 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W DMABCRL : Initial value : R/W : DTIE1B DTIE1A DTIE0B DTIE0A Data transfer end interrupt enable 0A 0 Transfer end interrupt disabled 1 Transfer end interrupt enabled Data transfer end interrupt enable 1A 0 Transfer end interrupt disabled 1 Transfer end interrupt enabled Data transfer interrupt enable 0B 0 Transfer break interrupt disabled 1 Transfer break interrupt enabled Data transfer interrupt enable 1B 0 Transfer break interrupt disabled 1 Transfer break interrupt enabled Data transfer enable 0 0 Data transfer disabled 1 Data transfer enabled Data transfer master enable 0 0 Data transfer disabled In normal mode, cleared to 0 by an NMI interrupt 1 Data transfer enabled Data transfer enable 1 0 Data transfer disabled 1 Data transfer enabled Data transfer master enable 1 0 Data transfer disabled In burst mode, cleared to 0 by an NMI interrupt 1 Data transfer enabled Rev. 3.00 Jan 11, 2005 page 1145 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TCSR0—Timer Control/Status Register 0 Bit : 7 OVF Initial value : R/W : 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 — 1 — H'FF74 (W), H'FF74 (R) 3 — 1 — 2 CKS2 0 R/W 1 CKS1 0 R/W WDT0 0 CKS0 0 R/W Clock select 2 to 0 WDT0 input clock select CKS2 0 CKS1 0 CKS0 Clock Overflow cycle* (when φ = 25 MHz) φ/2 20.4 µs 0 φ/64 1 652.8 µs φ/128 1 0 1.3 ms φ/512 1 5.2 ms φ/2048 20.9 ms 1 0 0 φ/8192 1 83.6 ms φ/32768 1 0 334.2 ms φ/131072 1 1.34 s Note: * The overflow cycle starts when TCNT starts counting from H'00 and ends when an overflow occurs. Timer enable 0 1 Initializes TCNT to H'00 and disables the counting operation TCNT performs counting operation Timer mode select 0 1 Interval timer mode: Interval timer interrupt (WOVI) request sent to CPU when overflow occurs at TCNT Watchdog timer mode: WDTOVF signal output externally when overflow occurs at TCNT * Note: * See section 15.2.3, Reset control/status register (RSTCSR) for details of when TCNT overflows in watchdog timer mode. Overflow flag 0 [Clearing condition] • When 0 is written to OVF bit after reading TCSR when OVF = 1 1 [Setting conditions] • When TCNT overflows (changes from H'FF to H'00) • When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset Notes: TCSR is write-protected by a password to prevent accidental overwriting. For details see section 15.2.5, Notes on Register Access. * Only 0 can be written to these bits (to clear these flags). Rev. 3.00 Jan 11, 2005 page 1146 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TCNT0—Timer Counter 0 TCNT1—Timer Counter 1 Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FF74 (W), H'FF75 (R) H'FFA2 (W), H'FFA3 (R) 3 0 R/W 2 0 R/W 1 0 R/W 0 0 WDT0 WDT1 Initial value : R/W : R/W Note: TCNT is write-protected by a password to prevent accidental overwriting. For details see section 15.2.5, Notes on Register Access. RSTCSR—Reset Control/Status Register Bit : 7 WOVF Initial value : R/W : 0 R/(W)* 6 RSTE 0 R/W 5 RSTS 0 R/W 4 — 1 — H'FF76 (W), H'FF77 (R) 3 — 1 — 2 — 1 — 1 — 1 — WDT0 0 — 1 — Reset select 0 1 Reset enable 0 No internal reset on TCNT overflow * 1 Internal reset performed on TCNT overflow Note: * The LSI is not internally reset, but TCNT and TCSR in WDT are reset. Watchdog timer overflow flag 0 1 [Clearing condition] • Writing 0 to WOVF after reading TCSR when WOVF = 1 [Setting condition] • When, in watchdog timer mode, TCNT overflows (H'FF→ H'00) Power-on reset Manual reset Notes: RSTCSR is write-protected by a password to prevent accidental overwriting. For details see section 15.2.5, Notes on Register Access. * Only 0 can be written to these bits (to clear these flags). Rev. 3.00 Jan 11, 2005 page 1147 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register ICCR0—I2C Bus Control Register ICCR1—I2C Bus Control Register Bit : 7 ICE Initial value : R/W : 0 R/W 6 IEIC 0 R/W 5 MST 0 R/W 4 TRS 0 R/W 3 H'FF78 H'FF80 2 BBSY 0 R/W 1 IRIC 0 R/(W)* 0 SCP 0 R/W IIC0 IIC1 ACKE 0 R/W Start condition/stop condition prohibit 0 Writing 0 issues a start or stop condition, in combination with the BBSY flag 1 Reading always returns a value of 1 Writing is ignored I2C Bus interface interrupt request flag 0 1 Waiting for transfer, or transfer in progress Interrupt requested Note: For details see section 18.2.5, I2C Bus Control Register. Bus busy 0 Bus is free [Clearing condition] • When a stop condition is detected Bus is free [Clearing condition] • When a stop condition is detected 1 Acknowledge bit judgement selection 0 1 The value of the acknowledge bit is ignored, and continuous transfer is performed If the acknowledge bit is 1, continuous transfer is interrupted Master/slave select, transmit/receive select 0 1 0 1 0 1 Slave receive mode Slave transmit mode Master receive mode Master transmit mode Note: For details see section 18.2.5, I2C Bus Control Register. I2C Bus Interface Interrupt Enable 0 1 Interrupts disabled Interrupts enabled I2C Bus Interface Enable 0 1 I2C bus interface module disabled, with SCL and SDA signal pins set to port function I2C bus interface module internal states initialized SAR and SARX can be accessed I2C bus interface module enabled for transfer operations (pins SCL and SDA are driving the bus) ICMR and ICDR can be accessed Note: * Only 0 can be written, for flag clearing. Rev. 3.00 Jan 11, 2005 page 1148 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register ICSR0—I2C Bus Status Register ICSR1—I2C Bus Status Register Bit : 7 ESTP Initial value : R/W : 0 R/(W)* 6 STOP 0 R/(W)* 5 IRTR 0 R/(W)* 4 AASX 0 R/(W)* 3 AL 0 R/(W)* 2 AAS 0 R/(W)* 1 ADZ 0 H'FF79 H'FF81 0 ACKB 0 R/W IIC0 IIC1 R/(W)* Acknowledge bit 0 When receiving, 0 is output at acknowledge output timing When transmitting, this bit shows that an acknowledge (0) has not been sent from the receiving device When receiving, 1 is output at acknowledge output timing When transmitting, this bit shows that an acknowledge (1) has been sent from the receiving device 1 General call address confirmation flag 0 General call address not confirmed [Clearing conditions] • When data is written to ICDR (when sending), or when data is read from ICDR (when receiving) • When 0 is written after reading ADZ = 1 • In master mode General call address confirmation [Setting condition] • When general call address is detected is in slave receive mode and FSX = 0 or FS = 0) 1 Slave address confirmation flag 0 Slave address or general call address not confirmed [Clearing conditions] • When data is written to ICDR (when sending), or when data is read from ICDR (when receiving) • When 0 is written after reading AAS = 1 • In master mode Slave address or general call address confirmed [Setting condition] • When slave address or general call address is detected in slave receive mode and FS = 0 1 Arbitration lost flag 0 Secure bus [Clearing conditions] • When data is written to ICDR (when sending), or when data is read (when receiving) • When 0 is written after reading AL = 1 Bus arbitration lost [Setting conditions] • When there is a mismatch between internal SDA and SDA pin at rise in SCL in master transmit mode • When the internal SCL level is HIGH at the fall in SCL in master transmit mode 1 2nd slave address confirmation flag 0 2nd slave address not confirmed [Clearing conditions] • When 0 is written after reading AASX = 1 • When start conditions are detected • In master mode 2nd slave address confirmed [Setting condition] • When 2nd slave address is detected in slave receive mode and FSX = 0 1 I2C bus interface continuous transmit and receive interrupt request flag 0 Transmit wait state, or transmitting [Clearing conditions] • Whe conditionsn 0 written after reading IRTR = 1 • When IRIC flag is cleared to 0 Continuous transmit state [Setting conditions] • In I2C bus interface slave mode When 1 is set in TDRE or RDRF flag when AASX = 1 • In other than I2C bus interface slave mode When TDRE or RDRF flag is set to 1 1 Normal end condition detection flag 0 No normal end condition [Clearing conditions] • When 0 is written after reading STOP = 1 • When IRIC flag is cleared to 0 Normal end condition detected in slave mode in I2C bus format [Setting conditions] • On detection of stop condition on completion of sending frame • No meaning when in other than slave mode in I2C bus format 1 Error stop condition detection flag 0 No error stop condition [Clearing conditions] • When 0 written after reading ESTP = 1 • When IRIC flag is cleared to 0 • Error stop condition detected in slave mode in I2C bus format [Setting conditions] • On detection of stop condition while sending frame • No meaning when in other than slave mode in I2C bus format 1 Note: * Only 0 can be written to these bits (to clear these flags). Rev. 3.00 Jan 11, 2005 page 1149 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register ICDR0—I2C Bus Data Register ICDR1—I2C Bus Data Register Bit : 7 ICDR7 Initial value : R/W ICDRR Bit : 7 — R 6 — R 5 — R 4 — R : — R/W 6 ICDR6 — R/W 5 ICDR5 — R/W 4 ICDR4 — R/W H'FF7E H'FF86 3 ICDR3 — R/W 2 ICDR2 — R/W 1 ICDR1 — R/W 0 ICDR0 — R/W IIC0 IIC1 3 — R 2 — R 1 — R 0 — R ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0 Initial value : R/W ICDRS Bit : : 7 — — 6 — — 5 — — 4 — — 3 — — 2 — — 1 — — 0 — — ICDRS7 ICDRS6 ICDRR5 ICDRS4 ICDRS3 ICDRS2 ICDRS1 ICDRS0 Initial value : R/W ICDRT Bit : 7 — W 6 — W 5 — W 4 — W 3 — W 2 — W 1 — W 0 — W ICDRT7 ICDRT6 ICDRT5 ICDRT4 ICDRT3 ICDRT2 ICDRT1 ICDRT0 Initial value : R/W : : TDRE, RDRF (Internal flag) Bit Initial value R/W : : : — TDRE 0 — — RDRF 0 — SARX0—2nd Slave Address Register SARX1—2nd Slave Address Register Bit : 7 SVAX6 Initial value : R/W : 0 R/W 6 SVAX5 0 R/W 5 SVAX4 0 R/W 4 SVAX3 0 R/W 2nd slave address H'FF7E H'FF86 3 SVAX2 0 R/W 2 SVAX1 0 R/W 1 SVAX0 0 R/W 0 FSX 1 R/W IIC0 IIC1 Format select X Rev. 3.00 Jan 11, 2005 page 1150 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register ICMR0—I2C Bus Mode Register ICMR1—I2C Bus Mode Register Bit : 7 MLS Initial value : R/W : 0 R/W 6 WAIT 0 R/W 5 CKS2 0 R/W 4 CKS1 0 R/W 3 CKS0 0 R/W H'FF7F H'FF87 2 BC2 0 R/W 1 BC1 0 R/W 0 BC0 0 R/W IIC0 IIC1 Bit counter Bit 2 BC2 0 Bit 1 BC1 0 1 1 0 1 Bit 0 BC0 0 1 0 1 0 1 0 1 Bit/frame Clock sync serial format 8 1 2 3 4 5 6 7 I2C bus format 9 2 3 4 5 6 7 8 Transmit clock select SCRX Bit 5 bits 5, 6 IICX 0 CKS2 0 Bit 4 Bit 3 Clock Transfer rate CKS1 0 1 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 φ/28 φ/40 φ/48 φ/64 φ/80 φ/100 φ/112 φ/128 φ/56 φ/80 φ/96 φ/128 φ/160 φ/200 φ/224 φ/256 φ = 5 MHz φ = 8 MHz φ = 10 MHz φ = 16 MHz φ = 20 MHz φ = 25 MHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 89.3 kHz 62.5 kHz 52.1 kHz 39.1 kHz 31.3 kHz 25.0 kHz 22.3 kHz 19.5 kHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz 143 kHz 100 kHz 83.3 kHz 62.5 kHz 50.0 kHz 40.0 kHz 35.7 kHz 31.3 kHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 571 kHz 400 kHz 333 kHz 250 kHz 200 kHz 160 kHz 143 kHz 125 kHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz 714 kHz 500 kHz 417 kHz 313 kHz 250 kHz 200 kHz 179 kHz 156 kHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz 893 kHz 625 kHz 521 kHz 391 kHz 313 kHz 250 kHz 223 kHz 195 kHz 446 kHz 313 kHz 260 kHz 195 kHz 156 kHz 125 kHz 112 kHz 97.7 kHz 1 0 1 1 0 0 1 1 0 1 Wait insert bit 0 1 Send data followed by acknowledge bit Insert wait between data and acknowledge bit MSB-first/LSB-first select 0 1 MSB first LSB first Rev. 3.00 Jan 11, 2005 page 1151 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register SAR0—Slave Address Register SAR1—Slave Address Register Bit : 7 SVA6 Initial value : R/W : 0 R/W 6 SVA5 0 R/W 5 SVA4 0 R/W 4 SVA3 0 R/W Slave address Format select DDCSWR bit 6 SW 0 SAR bit 0 FS 0 SARX bit 0 FSX 0 1 H'FF7F H'FF87 3 SVA2 0 R/W 2 SVA1 0 R/W 1 SVA0 0 R/W 0 FS 0 R/W IIC0 IIC1 Operating mode I2C bus format • SAR and SARX slave addresses recognized (initial value) I2C bus format • SAR slave address recognized • SARX slave address ignored I2C bus format • SAR slave address ignored • SARX slave address recognized Synchronous serial format • SAR and SARX slave addresses ignored • Must not be set 1 0 1 1 — — ADDRAH—A/D Data Register AH ADDRAL—A/D Data Register AL ADDRBH—A/D Data Register BH ADDRBL—A/D Data Register BL ADDRCH—A/D Data Register CH ADDRCL—A/D Data Register CL ADDRDH—A/D Data Register DH ADDRDL—A/D Data Register DL Bit : 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 7 0 R 6 0 R 5 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R A/D A/D A/D A/D A/D A/D A/D A/D 0 — 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — Initial value : R/W : Rev. 3.00 Jan 11, 2005 page 1152 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register ADCSR—A/D Control/Status Register Bit : 7 ADF Initial value : R/W : 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W H'FF98 3 CH3 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W A/D Channel select 2 to 0 CH3 CH2 CH1 CH0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Single mode (SCAN = 0) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 Scan mode (SCAN = 1) AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 AN8 AN8, AN9 AN8 to AN10 AN8 to AN11 AN12 AN12, AN13 AN12 to AN14 AN12 to AN15 Channel select 3 0 1 AN8 to AN11 set as group 0 analog input pins, and AN12 to AN15 as group 1 analog input pins AN0 to AN3 set as group 0 analog input pins, and AN4 to AN7 set as group 1 analog input pins Scan mode 0 1 Single mode Scan mode A/D start 0 A/D conversion disabled 1 (1) Single mode: A/D conversion starts. Automatically cleared to 0 on completion of conversion on specified channel (2) Scan mode: A/D conversion starts. The selected channel continues to be sequentially converted until this bit is cleared to 0 by a software, reset, or standby mode is selected, or module stop mode is selected A/D interrupt enable 0 1 A/D end flag 0 [Clearing conditions] • Writing 0 to the ADF flag after reading ADF = 1 • When DTC is started by an ADI interrupt and ADDR is read [Setting conditions] • Single mode: On completion of A/D conversion • Scan mode: On completion of conversion of all specified channels A/D conversion end interrupt (ADI) requests disabled A/D conversion end interrupt (ADI) requests enabled 1 Note: * Only 0 can be written to these bits (to clear these flags). Rev. 3.00 Jan 11, 2005 page 1153 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register ADCR—A/D Control Register Bit : 7 TRGS1 Initial value : R/W : 0 R/W 6 TRGS0 0 R/W 5 — 1 — 4 — 1 — Clock select 1, 0 H'FF99 3 CKS1 0 R/W 2 CKS0 0 R/W 1 — 1 — 0 — 1 — A/D CKS1 CKS0 Description 0 0 Conversion time = 530 states (Max.) Conversion time = 266 states (Max.) 1 Conversion time = 134 states (Max.) 1 0 1 Conversion time = 68 states (Max.) Time trigger select 1, 0 TRGS1 TRGS0 Description 0 0 Enables starting of A/D conversion by software Enables starting of A/D conversion by TPU conversion start trigger 1 Enables starting of A/D conversion by 8-bit timer conversion start trigger 1 0 Enables starting of A/D conversion by external trigger pin (ADTRG) 1 Rev. 3.00 Jan 11, 2005 page 1154 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register TCSR1—Timer Control/Status Register 1 Bit : 7 OVF Initial value : R/W : 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 PSS 0 R/W 3 RST/NMI 0 R/W 2 CKS2 0 R/W 1 H'FFA2 (W), H'FFA2 (R) 0 CKS0 0 R/W WDT1 CKS1 0 R/W Clock select 2 to 0 Overflow cycle * (when φ = 25 MHz) (when φSUB = 32.768 kHz) φ/2 0 0 0 0 20.4 µs φ/64 1 652.8 µs φ/128 1 0 1.3 ms φ/512 1 5.2 ms φ/2048 1 0 0 20.9 ms φ/8192 1 83.6 ms φ/32768 1 0 334.2 ms φ/131072 1 1.34 s φSUB/2 1 0 0 0 15.6 ms φSUB/4 1 31.3 ms φSUB/8 1 0 62.5 ms φSUB/16 1 125 ms φSUB/32 1 0 0 250 ms φSUB/64 1 500 ms φSUB/128 1 0 1s φSUB/256 1 2s Note: * The overflow cycle starts when TCNT starts counting from H’00 and ends when an overflow occurs. Reset or NMI 0 NMI interrupt request 1 Internal reset request Prescaler select 0 TCNT counts the divided clock output by the φ-based prescaler (PSM) 1 TCNT counts the divided clock output by the φSUB-based prescaler (PSS) Timer enable 0 1 Initializes TCNT to H’00 and disables the counting operation TCNT performs counting operation PSS CSK2 CSK1 CSK0 Clock Timer mode select 0 1 Interval timer mode: Interval timer interrupt (WOVI) request sent to CPU when overflow occurs at TCNT Watchdog timer mode: Reset or NMI interrupt request sent to CPU when overflow occurs at TCNT Overflow flag 0 [Clearing conditions] • When 0 is written to TME bit • When 0 is written to OVF bit after reading TCSR when OVF = 1 [Setting conditions] • When TCNT overflows (H’FF → H’00) • When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset 1 Notes: TCSR is write-protected by a password to prevent accidental overwriting. For details see section 15.2.5, Notes on Register Access. * Only 0 can be written to these bits (to clear these flags). Rev. 3.00 Jan 11, 2005 page 1155 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register FLMCR1—Flash Memory Control Register 1 Bit : 7 FWE Initial value : R/W : —* R 6 SWE1 0 R/W 5 ESU1 0 R/W 4 PSU1 0 R/W 3 EV1 0 R/W H'FFA8 2 PV1 0 R/W 1 E1 0 R/W 0 P1 0 R/W FLASH Program 1 0 1 Exits program mode Enters program mode [Setting condition] • When FWE = 1, SWE1 = 1, and PSU1 = 1 Erase 1 0 1 Exits erase mode. Enters erase mode [Setting condition] • When FWE = 1, SWE1 = 1, and ESU1 = 1 Program verify 1 0 1 Exits program verify mode Enters program verify mode [Setting condition] • When FWE = 1 and SWE1 = 1 Erase verify 1 0 1 Exits erase verify mode Enters erase verify mode [Setting condition] • When FWE = 1 and SWE1 = 1 Program setup bit 1 0 1 Exits program setup Program setup [Setting condition] • When FWE = 1 and SWE1 = 1 Erase setup bit 1 0 1 Exits erase setup Erase setup [Setting condition] • When FWE = 1 and SWE1 = 1 Software write enable bit 1 0 1 Writing disabled Writing enabled [Setting condition] • When FWE = 1 Flash write enable bit 0 1 When LOW level signal input to FWE pin (hardware protect status) When HIGH level signal input to FWE pin Note: * Determined by the state of the FWE pin. Rev. 3.00 Jan 11, 2005 page 1156 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register FLMCR2—Flash Memory Control Register 2 Bit : 7 FLER Initial value : R/W : 0 R 6 — 0 — 5 — 0 — 4 — 0 — H'FFA9 3 — 0 — 2 — 0 — 1 — 0 — FLASH 0 — 0 — Flash memory error 0 Flash memory operating normally Flash memory protection against writing and erasing (error protection) is ignored [Clearing condition] • At a power-on reset and in hardware standby mode Shows that an error has occurred when writing to or erasing flash memory Flash memory protection against writing and erasing (error protection) is enabled [Setting condition] • See section 22.8.3, Error Protection 1 EBR1—Erase Block Register 1 Bit : 7 EB7 Initial value : R/W : 0 R/W 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W H'FFAA 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W FLASH 0 EB0 0 R/W EBR2—Erase Block Register 2 Bit : 7 — Initial value : R/W : 0 R/W 6 — 0 R/W 5 — 0 R/W 4 — 0 R/W H'FFAB 3 EB11 0 R/W 2 EB10 0 R/W 1 EB9 0 R/W FLASH 0 EB8 0 R/W Rev. 3.00 Jan 11, 2005 page 1157 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register FLPWCR—Flash Memory Power Control Register Bit : 7 PDWND Initial value : R/W : 0 R/W 6 — 0 R 5 — 0 R 4 — 0 R H'FFAC 3 — 0 R 2 — 0 R 1 — 0 R FLASH 0 — 0 R Power-down disable 0 1 Transition to flash memory power-down mode enabled Transition to flash memory power-down mode disabled PORT1—Port 1 Register Bit : 7 P17 Initial value : R/W : —* R 6 P16 —* R 5 P15 —* R 4 P14 —* R H'FFB0 3 P13 —* R 2 P12 —* R 1 P11 —* R 0 P10 —* R Port Note: * Determined by status of pins P17 to P10. PORT2—Port 2 Register Bit : 7 P27 Initial value : R/W : —* R 6 P26 —* R 5 P25 —* R 4 P24 —* R H'FFB1 3 P23 —* R 2 P22 —* R 1 P21 —* R 0 Port P20 —* R Note: * Determined by status of pins P27 to P20. Rev. 3.00 Jan 11, 2005 page 1158 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register PORT3—Port 3 Register Bit : 7 P37 Initial value : R/W : —* R 6 P36 —* R 5 P35 —* R 4 P34 —* R H'FFB2 3 P33 —* R 2 P32 —* R 1 P31 —* R 0 P30 —* R Port Note: * Determined by status of pins P37 to P30. PORT4—Port 4 Register Bit : 7 P47 Initial value : R/W : —* R 6 P46 —* R 5 P45 —* R 4 P44 —* R H'FFB3 3 P43 —* R 2 P42 —* R 1 P41 —* R 0 P40 —* R Port Note: * Determined by status of pins P47 to P40. PORT5—Port 5 Register Bit : 7 — R/W : — 6 — — 5 — — 4 — — H'FFB4 3 — — 2 P52 —* R 1 P51 —* R 0 P50 —* R Port Initial value : Undefined Undefined Undefined Undefined Undefined Note: * Determined by status of pins P52 to P50. Rev. 3.00 Jan 11, 2005 page 1159 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register PORT7—Port 7 Register Bit : 7 P77 Initial value : R/W : —* R 6 P76 —* R 5 P75 —* R 4 P74 —* R H'FFB6 3 P73 —* R 2 P72 —* R 1 P71 —* R 0 P70 —* R Port Note: * Determined by status of pins P77 to P70. PORT8—Port 8 Register Bit : 7 — Initial value : Undefined R/W : — 6 P86 —* R 5 P85 —* R 4 P84 —* R H'FFB7 3 P83 —* R 2 P82 —* R 1 P81 —* R 0 Port P80 —* R Note: * Determined by status of pins P86 to P80. PORT9—Port 9 Register Bit : 7 P97 Initial value : R/W : —* R 6 P96 —* R 5 P95 —* R 4 P94 —* R H'FFB8 3 P93 —* R 2 P92 —* R 1 P91 —* R 0 P90 —* R Port Note: * Determined by status of pins P97 to P90. Rev. 3.00 Jan 11, 2005 page 1160 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register PORTA—Port A Register Bit : 7 — R/W : — 6 — — 5 — — 4 — — H'FFB9 3 PA3 —* R 2 PA2 —* R 1 PA1 —* R 0 PA0 —* R Port Initial value : Undefined Undefined Undefined Undefined Note: * Determined by status of pins PA3 to PA0. PORTB—Port B Register Bit : 7 PB7 Initial value : R/W : —* R 6 PB6 —* R 5 PB5 —* R 4 PB4 —* R H'FFBA 3 PB3 —* R 2 PB2 —* R 1 PB1 —* R 0 PB0 —* R Port Note: * Determined by status of pins PB7 to PB0. PORTC—Port C Register Bit : 7 PC7 Initial value : R/W : —* R 6 PC6 —* R 5 PC5 —* R 4 PC4 —* R H'FFBB 3 PC3 —* R 2 PC2 —* R 1 PC1 —* R 0 PC0 —* R Port Note: * Determined by status of pins PC7 to PC0. PORTD—Port D Register Bit : 7 PD7 Initial value : R/W : —* R 6 PD6 —* R 5 PD5 —* R 4 PD4 —* R H'FFBC 3 PD3 —* R 2 PD2 —* R 1 PD1 —* R 0 PD0 —* R Port Note: * Determined by status of pins PD7 to PD0. Rev. 3.00 Jan 11, 2005 page 1161 of 1220 REJ09B0186-0300O Appendix B Internal I/O Register PORTE—Port E Register Bit : 7 PE7 Initial value : R/W : —* R 6 PE6 —* R 5 PE5 —* R 4 PE4 —* R H'FFBD 3 PE3 —* R 2 PE2 —* R 1 PE1 —* R 0 PE0 —* R Port Note: * Determined by status of pins PE7 to PE0. PORTF—Port F Register Bit : 7 PF7 Initial value : R/W : —* R 6 PF6 —* R 5 PF5 —* R 4 PF4 —* R H'FFBE 3 PF3 —* R 2 PF2 —* R 1 PF1 —* R 0 PF0 —* R Port Note: * Determined by status of pins PF7 to PF0. PORTG—Port G Register Bit : 7 — R/W : — 6 — — 5 — — 4 PG4 —* R H'FFBF 3 PG3 —* R 2 PG2 —* R 1 PG1 —* R 0 PG0 —* R Port Initial value : Undefined Undefined Undefined Note: * Determined by status of pins PG4 to PG0. Rev. 3.00 Jan 11, 2005 page 1162 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagrams Reset Internal data bus R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C P1n * WDR1 Internal address bus PPG module Pulse output enable Pulse output TPU module Output compare Output/PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input Legend: WDDR1: Write to P1DDR WDR1: Write to P1DR RDR1: Read P1DR RPOR1: Read port 1 n = 0 or 1 Note: * Priority order: Address output > Output compare output > PWM output > DMA transfer acknowledge output > pulse output > DR output Figure C.1 (a) Port 1 Block Diagram (Pins P10 and P11) Rev. 3.00 Jan 11, 2005 page 1163 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset WDDR1 Reset R Q D P1nDR C * WDR1 P1n RDR1 RPOR1 Internal address bus PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input External clock input Legend: WDDR1: WDR1: RDR1: RPOR1: n = 2 or 3 Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: address output > output compare output/PWM output > pulse output > DR output Figure C.1 (b) Port 1 Block Diagram (Pins P12 and P13) Rev. 3.00 Jan 11, 2005 page 1164 of 1220 REJ09B0186-0300O Internal data bus R Q D P1nDDR C Appendix C I/O Port Block Diagrams Reset R Q D P14DDR C WDDR1 Reset R Q D P14DR C WDR1 P14 * RDR1 RPOR1 Internal data bus PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input Interrupt controller IRQ0 interrupt input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: output compare output/PWM output > pulse output > DR output Figure C.1 (c) Port 1 Block Diagram (Pin P14) Rev. 3.00 Jan 11, 2005 page 1165 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset R Q D P15DDR C WDDR1 Reset R Q D P15DR C WDR1 PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 P15 * RPOR1 Internal data bus Input capture input External clock input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: output compare output/PWM output > pulse output > DR output Figure C.1 (d) Port 1 Block Diagram (Pin P15) Rev. 3.00 Jan 11, 2005 page 1166 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset R Q D P16DDR C WDDR1 Reset R Q D P16DR C * WDR1 P16 Internal data bus PWM module PWM2 output enable PWM2 output PPG module Pulse output enable Pulse output TPU module Output compare Output/PWM output enable Output compare output/ PWM output Input capture input Input controller IRQ1 interrupt input RDR1 RPOR1 Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: output compare output/PWM output > PWM2 output > pulse output > DR output Figure C.1 (e) Port 1 Block Diagram (Pin P16) Rev. 3.00 Jan 11, 2005 page 1167 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset R Q D P17DDR C WDDR1 Reset R Q D P17DR C * WDR1 P17 Internal data bus PWM module PWM3 output enable PWM3 output PPG module Pulse output enable Pulse output TPU module Output compare Output/PWM output enable Output compare output/ PWM output Input capture input External clock input RDR1 RPOR1 Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: output compare output/PWM output > PWM3 output > pulse output > DR output Figure C.1 (f) Port 1 Block Diagram (Pin P17) Rev. 3.00 Jan 11, 2005 page 1168 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams C.2 Port 2 Block Diagram Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2 P2n * Internal data bus PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR2 RPOR2 Input capture input External clock input Legend: WDDR2: WDR2: RDR2: RPOR2: Write to P2DDR Write to P2DR Read P2DR Read port 2 Note: * Priority order: output compare output/PWM output > PWM output > pulse output > DR output Figure C.2 Port 2 Block Diagram (Pins P20 to P27) Rev. 3.00 Jan 11, 2005 page 1169 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams C.3 Port 3 Block Diagrams Reset R Q D P30DDR C WDDR3 *1 Reset R Q D P30DR C WDR3 *2 Reset R Q D P30ODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data P30 Internal data bus TxD0/IrTxD RDR3 RPOR3 Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal Figure C.3 (a) Port 3 Block Diagram (Pin P30) Rev. 3.00 Jan 11, 2005 page 1170 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset R Q D P31DDR C *1 WDDR3 Internal data bus Reset P31 R Q D P31DR C *2 WDR3 Reset R Q D P31ODR C WODR3 RODR3 SCI module RDR3 Serial receive data enable RPOR3 Serial receive data RxD0/IrRxD Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal Figure C.3 (b) Port 3 Block Diagram (Pin P31) Rev. 3.00 Jan 11, 2005 page 1171 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset Internal data bus R Q D P32DDR C WDDR3 *2 Reset R Q D P32DR C WDR3 *3 Reset R Q D P32ODR C WODR3 RODR3 P32 *1 IIC1 module SDA1 output IIC1 output enable SDA1 input SCI module Serial clock output enable Serial clock output Serial clock input enable RDR3 RPOR3 Serial clock input Interrupt controller IRQ4 interrupt input Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Priority order: IIC output > Serial clock output > DR output 2. Output enable signal 3. Open drain control signal Figure C.3 (c) Port 3 Block Diagram (Pin P32) Rev. 3.00 Jan 11, 2005 page 1172 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset R Q D P33DDR C WDDR3 *1 Reset R Q D P33DR C WDR3 *2 Reset R Q D P33ODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data TxD1 P33 RDR3 RPOR3 IIC1 module SCL1 output IIC1 output enable SCL1 input Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal Figure C.3 (d) Port 3 Block Diagram (Pin P33) Rev. 3.00 Jan 11, 2005 page 1173 of 1220 REJ09B0186-0300O Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D P34DDR C *1 *3 P34 WDDR3 R Q D P34DR C WDR3 Reset R Q D P34ODR C WODR3 RODR3 *2 Internal data bus SCI module Serial receive data enable Serial receive data RxD1 Reset RDR3 RPOR3 IIC0 module SDA0 output IIC0 output enable SDA0 Input Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal 3. Priority order: IIC output > DR output Figure C.3 (e) Port 3 Block Diagram (Pin P34) Rev. 3.00 Jan 11, 2005 page 1174 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset R Q D P35DDR C WDDR3 *2 Internal data bus Reset R Q D P35DR C WDR3 P35 *1 *3 Reset R Q D P35ODR C WODR3 RODR3 SCI module Serial clock output enable Serial clock output Serial clock input enable RDR3 RPOR3 Serial clock input IIC0 module SCL0 output IIC0 output enable SCL0 input Interrupt controller IRQ5 interrupt input Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Priority order: IIC output > Serial clock output > DR output 2. Output enable signal 3. Open drain control signal Figure C.3 (f) Port 3 Block Diagram (Pin P35) Rev. 3.00 Jan 11, 2005 page 1175 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset R Q D P36DDR C *1 WDDR3 Internal data bus Reset P36 R Q D P36DR C *2 WDR3 Reset R Q D P36ODR C WODR3 RODR3 SCI module RDR3 Serial receive data enable RPOR3 Serial receive data RxD4 Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal Figure C.3 (g) Port 3 Block Diagram (Pin P36) Rev. 3.00 Jan 11, 2005 page 1176 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset R Q D P37DDR C WDDR3 *1 Internal data bus Reset R Q D P37DR C WDR3 P37 *2 Reset R Q D P37ODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data RDR3 TxD4 RPOR3 Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal Figure C.3 (h) Port 3 Block Diagram (Pin P37) Rev. 3.00 Jan 11, 2005 page 1177 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams C.4 Port 4 Block Diagrams Internal data bus A/D converter module Analog input RPOR4 P4n Legend: RPOR4: Read port 4 n = 0 to 5 Figure C.4 (a) Port 4 Block Diagram (Pins P40 to P45) RPOR4 P4n Internal data bus A/D converter module Analog input D/A converter module Output enable Analog output Legend: RPOR4: Read port 4 n = 6 or 7 Figure C.4 (b) Port 4 Block Diagram (Pins P46 and P47) Rev. 3.00 Jan 11, 2005 page 1178 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams C.5 Port 5 Block Diagrams Reset R Q D P50DDR C WDDR5 Reset P50 R Q D P50DR C WDR5 SCI module Serial transmit enable Serial transmit data TxD2 RDR5 RPOR5 Legend: WDDR5: WDR5: RDR5: RPOR5: Write to P5DDR Write to P5DR Read P5DR Read port 5 Figure C.5 (a) Port 5 Block Diagram (Pin P50) Rev. 3.00 Jan 11, 2005 page 1179 of 1220 REJ09B0186-0300O Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D P51DDR C WDDR5 Reset P51 R Q D P51DR C WDR5 RDR5 SCI module Serial receive data enable RPOR5 Internal data bus Serial receive data RxD2 Legend: WDDR5: WDR5: RDR5: RPOR5: Write to P5DDR Write to P5DR Read P5DR Read port 5 Figure C.5 (b) Port 5 Block Diagram (Pin P51) Rev. 3.00 Jan 11, 2005 page 1180 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset R Q D P52DDR C WDDR5 Reset P52 R Q D P52DR C WDR5 Internal data bus SCI module Serial clock output enable Serial clock output RDR5 Serial clock input enable RPOR5 Serial clock input Legend: WDDR5: WDR5: RDR5: RPOR5: Write to P5DDR Write to P5DR Read P5DR Read port 5 Figure C.5 (c) Port 5 Block Diagram (Pin P52) Rev. 3.00 Jan 11, 2005 page 1181 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams C.6 Port 7 Block Diagrams Reset R Q D P7nDDR C WDDR7 Mode 7 P7n Modes 4 to 6 Reset R Q D P7nDR C WDR7 Internal data bus Bus controller Chip select RDR7 RPOR7 8-bit timer Legend: WDDR7: WDR7: RDR7: RPOR7: n = 0 or 1 Reset/Count input Write to P7DDR Write to P7DR Read P7DR Read port 7 Figure C.6 (a) Port 7 Block Diagram (Pins P70 and P71) Rev. 3.00 Jan 11, 2005 page 1182 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset R Q D P72DDR C WDDR7 Mode 7 * Reset R Q D P72DR C WDR7 P72 Modes 4 to 6 Internal data bus Bus controller Chip select RDR7 8-bit timer Timer output TMO0 Timer output enable RPOR7 Legend: WDDR7: WDR7: RDR7: RPOR7: Write to P7DDR Write to P7DR Read P7DR Read port 7 Note: * Priority order: (Mode 7) 8-bit timer output > DR output (Modes 4 to 6) Chip select output > 8-bit timer output > DR output Figure C.6 (b) Port 7 Block Diagram (Pin P72) Rev. 3.00 Jan 11, 2005 page 1183 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset R Q D P73DDR C WDDR7 Mode 7 * Reset R Q D P73DR C WDR7 Bus controller Chip select P73 Modes 4 to 6 RDR7 RPOR7 8-bit timer Timer output TMO1 Timer output enable Legend: WDDR7: WDR7: RDR7: RPOR7: Write to P7DDR Write to P7DR Read P7DR Read port 7 Note: * Priority order: (Mode 7) 8-bit timer output > DR output (Modes 4 to 6) Chip select output > 8-bit timer output > DR output Figure C.6 (c) Port 7 Block Diagram (Pin P73) Rev. 3.00 Jan 11, 2005 page 1184 of 1220 REJ09B0186-0300O Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D P74DDR C WDDR7 Reset P74 R Q D P74DR C WDR7 Internal data bus 8-bit timer 8-bit timer output enable 8-bit timer output RDR7 RPOR7 System controller Manual reset input enable Manual reset input Legend: WDDR7: WDR7: RDR7: RPOR7: Write to P7DDR Write to P7DR Read P7DR Read port 7 Figure C.6 (d) Port 7 Block Diagram (Pin P74) Rev. 3.00 Jan 11, 2005 page 1185 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset R Q D P75DDR C WDDR7 Reset R Q D P75DR C WDR7 P75 * Internal data bus 8-bit timer Timer output enable Timer output SCI module Serial clock output enable Serial clock RDR7 Serial clock input enable RPOR7 Serial clock input Legend: WDDR7: WDR7: RDR7: RPOR7: Write to P7DDR Write to P7DR Read P7DR Read port 7 Note: *Priority order: Serial clock output > 8-bit timer output > DR output Figure C.6 (e) Port 7 Block Diagram (Pin P75) Rev. 3.00 Jan 11, 2005 page 1186 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset R Q D P76DDR C WDDR7 Reset P76 R Q D P76DR C WDR7 Internal data bus SCI module RDR7 Serial receive data enable RPOR7 Serial receive data RxD3 Legend: WDDR7: WDR7: RDR7: RPOR7: Write to P7DDR Write to P7DR Read P7DR Read port 7 Figure C.6 (f) Port 7 Block Diagram (Pin P76) Rev. 3.00 Jan 11, 2005 page 1187 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset R Q D P77DDR C WDDR7 Reset R Q D P77DR C WDR7 P77 Internal data bus SCI module Serial transmit enable data Serial transmit data TxD3 RDR7 RPOR7 Legend: WDDR7: WDR7: RDR7: RPOR7: Write to P7DDR Write to P7DR Read P7DR Read port 7 Figure C.6 (g) Port 7 Block Diagram (Pin P77) Rev. 3.00 Jan 11, 2005 page 1188 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams C.7 Port 8 Block Diagrams Reset R Q D D P8nDDR C WDDR8 Reset P8n R Q D P8nDR C WDR8 RDR8 RPOR8 DMA controller DMA request Legend: WDDR8: WDR8: RDR8: RPOR8: Write to P8DDR Write to P8DR Read P8DR Read port 8 Figure C.7 (a) Port 8 Block Diagram (Pins P80 and P81) Rev. 3.00 Jan 11, 2005 page 1189 of 1220 REJ09B0186-0300O Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D P8nDDR C WDDR8 Reset P8n * R Q D P8nDR C WDR8 DMA controller DMA transfer end enable DMA transfer end RDR8 RPOR8 Legend: WDDR8: Write to P8DDR WDR8: Write to P8DR Read P8DR RDR8: RPOR8: Read port 8 Note: * Priority order: DMA transfer end output > DR output Figure C.7 (b) Port 8 Block Diagram (Pins P82 and P83) Rev. 3.00 Jan 11, 2005 page 1190 of 1220 REJ09B0186-0300O Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D P8nDDR C WDDR8 Reset P8n * R Q D P8nDR C WDR8 DMA controller DMA transfer acknowledge enable DMA transfer acknowledge RDR8 RPOR8 Legend: WDDR8: WDR8: RDR8: RPOR8: Write to P8DDR Write to P8DR Read P8DR Read port 8 Note: * Priority order: DMA transfer acknowledge output > DR output Figure C.7 (c) Port 8 Block Diagram (Pins P84 and P85) Rev. 3.00 Jan 11, 2005 page 1191 of 1220 REJ09B0186-0300O Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D D P86DDR C WDDR8 Reset P86 R Q D P86DR C WDR8 RDR8 RPOR8 Legend: WDDR8: WDR8: RDR8: RPOR8: Write to P8DDR Write to P8DR Read P8DR Read port 8 Figure C.7 (d) Port 8 Block Diagram (Pin P86) Rev. 3.00 Jan 11, 2005 page 1192 of 1220 REJ09B0186-0300O Internal data bus Appendix C I/O Port Block Diagrams C.8 Port 9 Block Diagrams RPOR9 P9n Internal data bus A/D converter module Analog input Legend: RPOR9: Read port 9 n = 0 to 5 Figure C.8 (a) Port 9 Block Diagram (Pins P90 to P95) RPOR9 P9n Internal data bus A/D converter module Analog input D/A converter module Output enable Analog output Legend: RPOR9: Read port 9 n = 6 or 7 Figure C.8 (b) Port 9 Block Diagram (Pins P96 and P97) Rev. 3.00 Jan 11, 2005 page 1193 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams C.9 Port A Block Diagrams Reset R Q D PAnPCR C WPCRA RPCRA Reset R Q D PAnDDR C WDDRA *1 Reset R Q D PAnDR C WDRA Reset R Q D PAnODR C WODRA RODRA PAn Modes 4 to 6 Address enable *2 RDRA RPORA Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: n = 0 to 7 Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Notes: 1. Output enable signal 2. Open drain control signal Figure C.9 Port A Block Diagram (Pins PA0 to PA7) Rev. 3.00 Jan 11, 2005 page 1194 of 1220 REJ09B0186-0300O Internal address bus Internal data bus Appendix C I/O Port Block Diagrams C.10 Port B Block Diagram Reset R Q D PBnPCR C WPCRB RPCRB Reset R Q D PBnDDR C WDDRB *1 Reset R Q D PBnDR C WDRB Reset R Q D PBnODR C WODRB RODRB PB1 Modes 4 to 6 Address enable *2 RDRB RPORB Legend: WDDRB: WDRB: WODRB: WPCRB: RDRB: RPORB: RODRB: RPCRB: n = 0 to 7 Write to PBDDR Write to PBDR Write to PBODR Write to PBPCR Read PBDR Read port B Read PBODR Read PBPCR Notes: 1. Output enable signal 2. Open drain control signal Figure C.10 Port B Block Diagram (Pins PB0 to PB7) Rev. 3.00 Jan 11, 2005 page 1195 of 1220 REJ09B0186-0300O Internal address bus Internal data bus Appendix C I/O Port Block Diagrams C.11 Port C Block Diagrams Reset R Q D PCnPCR C WPCRC RPCRC Reset R Q D PCnDDR C WDDRA *1 Reset R Q D PCnDR C WDRA *2 Reset R Q D PCnODR C WODRC RODRC PCn Modes 4 and 5 Mode 6 RDRC RPORC Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: n = 0 to 5 Write to PCDDR Write to PCDR Write to PCODR Write to PCPCR Read PCDR Read port A Read PCODR Read PCPCR Notes: 1. Output enable signal 2. Open drain control signal Figure C.11 (a) Port C Block Diagram (Pins PC0 to PC5) Rev. 3.00 Jan 11, 2005 page 1196 of 1220 REJ09B0186-0300O Internal address bus Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D PCnPCR C WPCRC RPCRC PWM output PWM output enable Reset R Q D PCnDDR C WDDRA *1 Reset R Q D PCnDR C WDRA *2 Reset R Q D PCnODR C WODRC RODRC PCn Modes 4 and 5 Mode 6 RDRC RPORC Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: n = 6 or 7 Write to PCDDR Write to PCDR Write to PCODR Write to PCPCR Read PCDR Read port A Read PCODR Read PCPCR Notes: 1. Output enable signal 2. Open drain control signal Figure C.11 (b) Port C Block Diagram (Pins PC6 and PC7) Rev. 3.00 Jan 11, 2005 page 1197 of 1220 REJ09B0186-0300O Internal address bus Internal data bus Appendix C I/O Port Block Diagrams C.12 Port D Block Diagram Reset Internal upper data bus R Q D PDnPCR C WPCRD RPCRD Reset R Q D PDnDDR C WDDRD Reset R Q D PDnDR C WDRD External address write PDn Mode 7 Modes 4 to 6 External address upper write RDRD RPORD External address upper read Legend: WDDRD: WDRD: WPCRD: RDRD: RPORD: RPCRD: n = 1 to 7 Write to PDDDR Write to PDDR Write to PDPCR Read PDDR Read port D Read PDPCR Figure C.12 Port D Block Diagram (Pins PD1 to PD7) Rev. 3.00 Jan 11, 2005 page 1198 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams C.13 Port E Block Diagram Reset Internal upper data bus WPCRE RPCRE Reset R Q D PEnDDR C WDDRE Reset R Q D PEnDR C WDRE External address write PEn Mode 7 Modes 4 to 6 RDRE RPORE External addres lower read Legend: WDDRE: WDRE: WPCRE: RDRE: RPORE: RPCRE: n = 1 to 7 Write to PEDDR Write to PEDR Write to PEPCR Read PEDR Read port E Read PEPCR Figure C.13 Port E Block Diagram (Pins PE1 to PE7) Rev. 3.00 Jan 11, 2005 page 1199 of 1220 REJ09B0186-0300O Internal lower data bus R Q D PEnPCR C Appendix C I/O Port Block Diagrams C.14 Port F Block Diagrams R Q D PF0DDR C WDDRF Modes 4 to 6 Internal data bus Bus controller BRLE bit Bus request input IRQ interrupt input Reset Reset PF0 R Q D PF0DR C WDRF RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.14 (a) Port F Block Diagram (Pin PF0) Rev. 3.00 Jan 11, 2005 page 1200 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset R Q D PF1DDR C WDDRF Reset R Q D PF1DR C WDRF Modes 4 to 6 BUZZ output BUZZ output enable PF1 Internal data bus Bus controller BRLE output Bus request acknowledge output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.14 (b) Port F Block Diagram (Pin PF1) Rev. 3.00 Jan 11, 2005 page 1201 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams R Q D PF2DDR C WDDRF Reset Modes 4 to 6 Internal data bus Reset Bus controller Wait enable PF2 Modes 4 to 6 R Q D PF2DR C WDRF Modes 4 to 6 Bus request output enable Bus request output RDRF RPORF Wait input LCAS output enable LCASS bit LCAS output Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.14 (c) Port F Block Diagram (Pin PF2) Rev. 3.00 Jan 11, 2005 page 1202 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset R Q D PF3DDR C WDDRF Reset R Q D PF3DR C WDRF PF3 Modes 4 to 6 Internal data bus Bus controller LWR output RDRF RPORF ADTRG input IRQ interrupt input Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.14 (d) Port F Block Diagram (Pin PF3) Rev. 3.00 Jan 11, 2005 page 1203 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset R Q D PF4DDR C WDDRF Reset R Q D PF4DR C WDRF PF4 Modes 4 to 6 Internal data bus Bus controller HWR output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.14 (e) Port F Block Diagram (Pin PF4) Rev. 3.00 Jan 11, 2005 page 1204 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset R Q D PF5DDR C WDDRF Reset R Q D PF5DR C WDRF PF5 Modes 4 to 6 Internal data bus Bus controller RD output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.14 (f) Port F Block Diagram (Pin PF5) Rev. 3.00 Jan 11, 2005 page 1205 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset R Q D PF6DDR C WDDRF Reset R Q D PF6DR C WDRF LCAS output LCAS output enable LCASS Bus controller AS output RDRF PF6 Modes 4 to 6 RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.14 (g) Port F Block Diagram (Pin PF6) Rev. 3.00 Jan 11, 2005 page 1206 of 1220 REJ09B0186-0300O Internal data bus Appendix C I/O Port Block Diagrams Modes 4 to 6 Reset S* R Q D D PF7DDR C WDDRF Reset R Q D PF7DR C WDRF PF7 Internal data bus φ RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Note: * Set priority Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.14 (h) Port F Block Diagram (Pin PF7) Rev. 3.00 Jan 11, 2005 page 1207 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams C.15 Port G Block Diagrams Reset R Q D PG0DDR C WDDRG Reset R Q D PG0DR C WDRG Modes 4 to 6 PG0 Internal data bus Bus controller CAS enable CAS output RDRG RPORG IRQ interrupt input Legend: WDDRG: WDRG: RDRG: RPORG: Write to PGDDR Write to PGDR Read PGDR Read port G Figure C.15 (a) Port G Block Diagram (Pin PG0) Rev. 3.00 Jan 11, 2005 page 1208 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Reset R Q D PG1DDR C WDDRG Reset R Q D PG1DR C WDRG OE output OE output enable Bus controller Chip select PG1 Modes 4 to 6 RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: Write to PGDDR Write to PGDR Read PGDR Read port G Figure C.15 (b) Port G Block Diagram (Pin PG1) Rev. 3.00 Jan 11, 2005 page 1209 of 1220 REJ09B0186-0300O Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D PGnDDR C WDDRG Reset R Q D PGnDR C WDRG PGn Modes 4 to 6 Internal data bus Bus controller Chip select RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: n = 2 or 3 Write to PGDDR Write to PGDR Read PGDR Read port G Figure C.15 (c) Port G Block Diagram (Pins PG2 and PG3) Rev. 3.00 Jan 11, 2005 page 1210 of 1220 REJ09B0186-0300O Appendix C I/O Port Block Diagrams Modes Modes 4 and 5 6 and 7 Reset WDDRG Reset R Q D PG4DR C WDRG PG4 Modes 4 to 6 Internal data bus S R Q D PG4DDR C Bus controller Chip select RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: Write to PGDDR Write to PGDR Read PGDR Read port G Figure C.15 (d) Port G Block Diagram (Pin PG4) Rev. 3.00 Jan 11, 2005 page 1211 of 1220 REJ09B0186-0300O Appendix D Pin States Appendix D Pin States D.1 Port States in Each Mode Table D.1 I/O Port States in Each Processing State MCU Port Name Operating Pin Name Mode Port 1 Port 2 Port 3 Port 4 Port 5 4 to 7 4 to 7 4 to 7 4 to 7 4 to 7 7 4 to 6 PowerOn Reset T T T T T T T Hardware Software Standby Standby Mode Mode T T T T T T T kept kept kept T kept kept Bus Release State kept kept kept T kept kept Program Execution State Sleep Mode I/O port I/O port I/O port Input port I/O port I/O port [DDR = 0] Input port [DDR = 1] to I/O port Manual Reset kept kept kept T kept kept kept Port 8 Port 9 Port A 4 to 7 4 to 7 4, 5 6 T T L T kept T kept kept T T T T kept T [Address output, OPE = 0] T [Address output, OPE = 1] kept [Otherwise] kept kept [Address output, OPE = 0] T [Address output, OPE = 1] kept [Otherwise] kept kept kept T [Address output] T [Otherwise] kept [Address output] A23 to A16 [Otherwise] I/O port 7 Port B 4, 5 6 T L T kept kept kept T T T kept [Address output] T [Otherwise] kept [Address output] A15 to A8 [Otherwise] I/O port 7 T kept T kept Rev. 3.00 Jan 11, 2005 page 1212 of 1220 REJ09B0186-0300O 4SC 7SC Input port I/O port I/O port 4SC 5SC 6SC 7SC P73/ P72/ P71/ P70/ [DDR · OPE = 0] T T [DDR · OPE = 1] H Appendix D Pin States Program Execution State Sleep Mode A7 to A0 MCU Port Name Operating Pin Name Mode Port C 4, 5 PowerOn Reset L Manual Reset kept Hardware Software Standby Standby Mode Mode T [OPE = 0] T [OPE = 1] kept [DDR = 1, OPE = 0] T [DDR = 1, OPE = 1] kept [DDR = 0] kept kept T kept kept T kept [DDR = 0] T [DDR = 1] H [DDR = 0] T [DDR = 1] H [OPE = 0] T [LCAS output, OPE = 1] Bus Release State T 6 T kept T T [DDR = 1] A7 to A0 [DDR = 0] I/O port 7 Port D 4 to 6 7 Port E 4 to 6 8 bit bus T T T T kept T* kept kept T* kept kept T T T T T T T kept T kept kept T kept kept I/O port Data bus I/O port I/O port Data bus I/O port [DDR = 0] T [DDR = 1] Clock output [DDR = 0] T [DDR = 1] Clock output [LCAS output] 16 bit T bus 7 PF7/ φ 4 to 6 T Clock output 7 T kept T kept [AS output, OPE = 1] H 7 T kept T kept kept I/O port Rev. 3.00 Jan 11, 2005 page 1213 of 1220 REJ09B0186-0300O SACL SA SACL SACL SA PF6/ 4 to 6 H H T T [Otherwise] Appendix D Pin States Program Execution State Sleep Mode MCU Port Name Operating Pin Name Mode PowerOn Reset H Manual Reset H Hardware Software Standby Standby Mode Mode T [OPE = 0] T [OPE = 1] H kept [LCAS output, OPE = 0] T [LCAS output, OPE = 1] Bus Release State T / / 7 T T kept [CAS output] H [Otherwise] kept T T kept PF2/ / 4 to 6 [Otherwise] kept 7 T T kept kept T T kept [BRLE = 0, BUZZE = 0] I/O port [BRLE = 0, BUZZE = 1] H [BRLE = 1] H kept [BRLE = 0] kept [BRLE = 1] T kept [DDR = 1, OPE = 0] T [DDR = 1, OPE = 1] H [DDR = 0] T kept kept [BRLE = 0, BUZZE = 0] I/O port [BRLE = 0, BUZZE = 1] H [BRLE = 1] L kept T 7 T T kept kept T T 7 T H T kept kept T T kept T 7 T kept T kept Rev. 3.00 Jan 11, 2005 page 1214 of 1220 REJ09B0186-0300O 0SC 0SC PG4/ 4, 5 6 [DDR = 0] Input port [DDR = 1] QERB 2QRI QERB PF0/ / 4 to 6 [BRLE = 0] I/O port [BRLE = 1] I/O port KCAB KCAB PF1/ BUZZ 4 to 6 [BRLE = 0, BUZZE = 0] I/O port [BRLE = 0, BUZZE = 1] BUZZ [BRLE = 1] I/O port TIAW [WAITE = 1] T OQERB SACL / [LCAS output] [LCAS output] T [BREQOE = 1] [BREQOE = 1] RWL RWH DR I/O port I/O port I/O port OQERB SACL OQERB TIAW SACL 3QRI GRTDA RWL RWH DR PF5/ PF4/ PF3/ 4 to 6 , , [WAITE = 1] Appendix D Pin States Program Execution State Sleep Mode [DDR = 0] Input port [DDR = 1] to MCU Port Name Operating Pin Name Mode PowerOn Reset T Manual Reset kept Hardware Software Standby Standby Mode Mode T [DDR = 1, OPE = 0] T [DDR = 1, OPE = 1] H [DDR = 0] T kept [DDR = 1, OPE = 0] T [DDR = 1, OPE = 1] H [DDR = 0] T kept [DRAME = 0] kept [DRAME = 1, OPE = 1] Bus Release State T 7 T T kept kept T T kept T 7 T T kept kept T T kept T [DRAME = 1, OPE = 1] T 7 T kept T kept kept I/O port Legend: H: L: T: kept: DDR: OPE: WAITE: BRLE: BREQOE: DRAME: LCASE: High level Low level High impedance Input port becomes high-impedance, output port retains state Data direction register Output port enable Wait input enable Bus release enable BREQO pin enable DRAM space setting DRAM space setting, CW2 = LCASS = 0 Note: * Indicates the state after completion of the executing bus cycle. Rev. 3.00 Jan 11, 2005 page 1215 of 1220 REJ09B0186-0300O SAC SAC 6QRI SAC PG0/ / 4 to 6 [DRAME = 0] I/O port [DRAME = 1] 3SC EO 7QRI EO 3SC PG1/ / / 4 to 6 [DDR = 0] Input port [OE = 0, DDR = 1] [OE = 1, DDR = 1] I/O port 1SC 2SC I/O port 2SC 1SC PG3/ PG2/ 4 to 6 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the signal low at least 10 states before the signal goes low, as shown below. must remain low until signal goes low (delay from low to high: 0 ns or more). STBY t1 ≥ 10 tcyc RES t2 ≥ 0 ns Figure E.1 Timing of Transition to Hardware Standby Mode (2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents does not have to be driven low as in (1). do not need to be retained, Timing of Recovery from Hardware Standby Mode STBY t ≥ 100 ns RES tOSC tNMIRH NMI Figure E.2 Timing of Recovery from Hardware Standby Mode Rev. 3.00 Jan 11, 2005 page 1216 of 1220 REJ09B0186-0300O YBTS Drive the signal low and the NMI signal high approximately 100 ns or more before goes high to execute a power-on reset. SER SER SER YBTS SER YBTS SER YBTS Appendix F Product Code Lineup Appendix F Product Code Lineup Table F.1 H8S/2643 Group Product Code Lineup Product Type H8S/2643 F-ZTAT Masked ROM H8S/2642 H8S/2641 Product Code HD64F2643 HD6432643 HD6432642 HD6432641 Mark Code HD64F2643FC HD64F2643TF HD6432643FC HD6432643TF HD6432642FC HD6432642TF HD6432641FC HD6432641TF Package (Package Code) 144-pin QFP (FP-144J) 144-pin TQFP (TFP-144) 144-pin QFP (FP-144J) 144-pin TQFP (TFP-144) 144-pin QFP (FP-144J) 144-pin TQFP (TFP-144) 144-pin QFP (FP-144J) 144-pin TQFP (TFP-144) Rev. 3.00 Jan 11, 2005 page 1217 of 1220 REJ09B0186-0300O Appendix G Package Dimensions Appendix G Package Dimensions Figures G.1 and G.2 show the FP-144J and TFP-144 package dimensions of the H8S/2643 Group. 22.0 ± 0.2 20 108 109 73 72 Unit: mm 22.0 ± 0.2 144 1 * 0.22 ± 0.05 37 3.05 Max 0.5 36 * 0.17 ± 0.05 0.15 ± 0.04 2.70 0.20 ± 0.04 0.10 M 1.25 1.0 0˚ – 8˚ 0.5 ± 0.1 0.10 *Dimension including the plating thickness Base material dimension 0.10 +0.15 –0.10 Package Code JEDEC JEITA Mass (reference value) FP-144J — Conforms 2.4 g Figure G.1 FP-144J Package Dimensions Rev. 3.00 Jan 11, 2005 page 1218 of 1220 REJ09B0186-0300O Appendix G Package Dimensions Unit: mm 73 72 18.0 ± 0.2 16 108 109 18.0 ± 0.2 144 1 *0.18 ± 0.05 0.16 ± 0.04 36 37 0.4 1.0 1.20 Max 0.07 M *0.17 ± 0.05 0.15 ± 0.04 1.00 1.0 0˚ – 8˚ 0.5 ± 0.1 Package Code JEDEC JEITA Mass (reference value) TFP-144 — Conforms 0.6 g 0.08 *Dimension including the plating thickness Base material dimension Figure G.2 FP-144 Package Dimensions 0.10 ± 0.05 Rev. 3.00 Jan 11, 2005 page 1219 of 1220 REJ09B0186-0300O Appendix G Package Dimensions Rev. 3.00 Jan 11, 2005 page 1220 of 1220 REJ09B0186-0300O Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2643 Group, H8S/2643F-ZTAT Publication Date: 1st Edition, May, 2000 Rev.3.00, January 11, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. © 2005. Renesas Technology Corp. All rights reserved. Printed in Japan. ™ Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: 2265-6688, Fax: 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: (2) 2715-2888, Fax: (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: (21) 6472-1001, Fax: (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: 6213-0200, Fax: 6278-8001 http://www.renesas.com Colophon 2.0 H8S/2643 Group, H8S/2643F-ZTAT Hardware Manual ™

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