H8S2214

REJ09B0189-0400 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 H8S/2214 Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series H8S/2214 HD64F2214 HD6432214 Rev. 4.00 Revision Date: Sep. 18, 2008 Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. 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You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev.4.00 Sep. 18, 2008 Page ii of lx REJ09B0189-0400 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. ⎯ The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. ⎯ The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. ⎯ The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. ⎯ When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. ⎯ The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev.4.00 Sep. 18, 2008 Page iii of lx REJ09B0189-0400 Configuration of this Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of this Manual 3. Overview 4. Table of Contents 5. Summary 6. Description of Functional Modules • • CPU and System-Control Modules On-chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Features ii) I/O pins iii) Description of Registers iv) Description of Operation v) Usage: Points for Caution When designing an application system that includes this LSI, take the points for caution into account. Each section includes points for caution in relation to the descriptions given, and points for caution in usage are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix • • Product-type codes and external dimensions Main Revisions for this edition The history of revisions is a summary of sections that have been revised and sections that have been added to earlier versions. This does not include all of the revised contents. For details, confirm by referring to the main description of this manual. 10. Appendix/Appendices Rev.4.00 Sep. 18, 2008 Page iv of lx REJ09B0189-0400 Preface This LSI is a single-chip microcomputer made up of the H8S/2000 CPU with an internal 32-bit architecture as its core, and the peripheral functions required to configure a system. This LSI is equipped with ROM, RAM, a bus controller, data transfer controller (DTC), a DMA controller (DMAC), two types of timers, a serial communication interface (SCI), a D/A converter, an A/D converter, and I/O ports as on-chip supporting modules. This LSI is suitable for use as an embedded processor for high-level control systems. Its on-chip ROM are flash memory (FZTAT™*) and masked ROM that provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. This is particularly applicable to application devices with specifications that will most probably change. Note: * F-ZTAT is a trademark of Renesas Technology, Corp. Target Users: This manual was written for users who will be using the H8S/2214 Group in the design of application systems. Members of this audience are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8S/2214 Group to the above audience. Refer to the H8S/2600 Series, H8S/2000 Series Software Manual for a detailed description of the instruction set. Notes on reading this manual: • In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. • In order to understand the details of the CPU’s functions Read the H8S/2600 Series, H8S/2000 Series Software Manual. • In order to understand the details of a register when its name is known The addresses, bits, and initial values of the registers are summarized in appendix B, Internal I/O Registers. Example: Related Manuals: Bit order: The MSB is on the left and the LSB is on the right. The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ Rev.4.00 Sep. 18, 2008 Page v of lx REJ09B0189-0400 H8S/2214 Group Manuals: Document Title H8S/2214 Group Hardware Manual H8S/2600 Series, H8S/2000 Series Software Manual Document No. This manual REJ09B0139 User’s Manuals for Development Tools: Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimized Linkage Editor User’s Manual H8S, H8/300 Series Simulator/Debugger (for Windows) User’s Manual H8S, H8/300 Series High-performance Embedded Workshop 3 Tutorial H8S, H8/300 Series High-performance Embedded Workshop 3 User's Manual Document No. REJ10B0058 ADE-702-037 REJ10B0024 REJ10B0026 Rev.4.00 Sep. 18, 2008 Page vi of lx REJ09B0189-0400 Main Revisions for This Edition Item Page Revisions (See Manual for Details) Note added Pin No. TFP-100B, TFP-100BV, TFP-100G, TFP-100GV BP-112, BP-112V, TBP-112A, TBP-112AV Mode 4 Pin Name 1.3.2 Pin Functions 8 to 11 in Each Operating Mode Table 1.2 Pin Functions in Each Operating Mode 2.3 Address Space 25 Mode 5 Mode 6 Mode 7 PROM Mode* Note: * NC pins must be left open. Description added ... The H8S/2000 CPU provides linear access to a maximum 64kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. Note that the modes and address spaces that can actually be used differ between individual products. See section 3, MCU Operating Modes, for details. Figure 2.6 Memory Map Figure amended H'0000 64 kbyte H'FFFF 16 Mbyte Program area H'00000000 H'00FFFFFF Data area Cannot be used by the H8S/2214 Group H'FFFFFFFF (a) Normal Mode* Note: * Not available in the H8S/2214 Group. (b) Advanced Mode Rev.4.00 Sep. 18, 2008 Page vii of lx REJ09B0189-0400 Item 2.6.1 Overview Table 2.1 Instruction Classification Page 34 Revisions (See Manual for Details) Note added Function Data transfer Instructions MOV 1 1 POP* , PUSH* LDM* , STM* 5 5 3 Size BWL WL L B Types 5 MOVFPE, MOVTPE* Notes : 5. The STM/LDM instructions may only be used with the ER0 to ER6 registers. 2.6.2 Instructions and Addressing Modes Table 2.2 Combinations of Instructions and Addressing Modes 35 Note added Function Instruction Data transfer MOV POP, PUSH LDM*3, STM*3 MOVFPE*1, MOVTPE*1 Notes : 3. The STM/LDM instructions may only be used with the ER0 to ER6 registers. 2.6.3 Table of Instructions Classified by Function Table 2.3 Instructions Classified by Function 38 Note added Type Data transfer Instruction 2 LDM* 1 Size* Function @SP+ → Rn (register list) Pops two or more general registers from the stack. Rn (register list) → @–SP Pushes two or more general registers onto the stack. L L 2 STM* 40 Note amended Type Arithmetic operations Instruction 3 TAS* 1 Size* Function @ERd – 0, 1 → ( of @ERd) Tests memory contents, and sets the most significant bit (bit 7) to 1. B 46 Note added Notes : 2. The STM/LDM instructions may only be used with the ER0 to ER6 registers. 3. This instruction should be used with the ER0, ER1, ER4, or ER5 general register only. Rev.4.00 Sep. 18, 2008 Page viii of lx REJ09B0189-0400 Item Page Revisions (See Manual for Details) Description added ... In this case, the relevant flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt handling routine, etc. See section 2.10.3, Bit Manipulation Instruction Usage Notes, for details. 2.6.5 Notes on Use 48 of Bit-Manipulation Instructions 2.8.1 Overview Figure 2.15 Processing States Figure 2.16 State Transitions 56 Note added Note : * The power-down state also includes a medium-speed mode and module stop mode. See section 17, PowerDown Modes, for details. 57 Figure amended Sleep mode Interrupt request Software standby mode STBY = high, RES = low Hardware standby mode*2 Low Power States 5.1.2 Block Diagram Figure 5.1 Block Diagram of Interrupt Controller 92 Figure amended INTM1 INTM0 SYSCR NMIEG NMI input IRQ input NMI input unit IRQ input unit ISR ISCR IER Rev.4.00 Sep. 18, 2008 Page ix of lx REJ09B0189-0400 Item 5.3.1 External Interrupts Figure 5.3 Timing of Setting IRQnF 5.5.1 Contention between Interrupt Generation and Disabling 5.5.5 IRQ Interrupts Page 100 Revisions (See Manual for Details) Note added Note : n = 7 to 0 113 Description amended When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction. 115 Newly added Newly added Legend added Legend: ABWCR : Bus width control register ASTCR: Access state control register BCRH: Bus control register H BCRL: Bus control register L WCRH: Wait state control register H WCRL: Wait state control register L 5.5.6 NMI Interrupt 115 Usage Notes 6.1.2 Block Diagram Figure 6.1 Block Diagram of Bus Controller 120 7.3.4 DMA Control 195 Register (DMACR) Bits 10 to 7— Reserved Bit 4—Reserved 196 Description added Although these bits are readable/writable, only 0 should be written here. Description added Although this bit is readable/writable, only 0 should be written here. 7.3.5 DMA Band Control Register (DMABCR) Bits 10 and 8— Reserved (DTA1A, DTA0A) 200 Description added Reserved bits in full address mode. Read and write possible. Although these bits are readable/writable, only 0 should be written here. 7.5.4 Repeat Mode 217 Description amended Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit in DMABCRL to 0. Rev.4.00 Sep. 18, 2008 Page x of lx REJ09B0189-0400 Item 7.5.9 DMAC Bus Cycles (Dual Address Mode) (2) Full Address Mode (Cycle Steal Mode) Page 234 Revisions (See Manual for Details) Description amended Either a one-byte or a one-word transfer is performed for each transfer request, and after the transfer the bus is released. 8.2.5 DTC Transfer 258 Count Register A (CRA) Description amended In repeat mode or block transfer mode, CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). In repeat mode, CRAH holds the transfer count and CRAL functions as an 8-bit transfer counter (1 to 256). In block transfer mode, CRAH holds the block size and functions as an 8-bit block size counter (1 to 256). CRAL is decremented by 1 every time data is transferred and when the counter value becomes H'00 the contents of CRAH are transferred. This operation is repeated. Note added 8.3.1 Overview Figure 8.2 Flowchart of DTC Operation 262 Transfer Counter = 0 or DISEL = 1 No Clear an activation flag Yes Clear DTCER Interrupt exception * handling End Note: * See the section on the corresponding peripheral module for details on the content of the processing required for interrupt handling. 8.3.2 Activation Sources 264 Description added ... The activation source flag, in the case of RXI0, for example, is the RDRF flag of SCI0. Since there are multiple factors that can initiate DTC operation, the flag that initiated the transfer is not cleared after the last byte (or word) is transferred. The corresponding interrupt handler must perform the required processing. Rev.4.00 Sep. 18, 2008 Page xi of lx REJ09B0189-0400 Item 8.3.8 Chain Transfer Page 273 Revisions (See Manual for Details) Description added Figure 8.9 shows the memory map for chain transfer. The DTC reads the start address for the register information from the DTC vector address corresponding to the DTC activation factor. After the data transfer completes, the CHNE bit in this register is tested, and if it is 1, the next register information allocated sequentially is read and a transfer is performed. This operation continues until a data transfer for register information whose CHNE bit is 0 completes. 8.5 Usage Notes (1) Module Stop 9.2.2 Register Configuration (1) Port 1 Data Direction Register (P1DDR) 280 Description added ... However, 1 cannot be written in the MSTPA6 bit while the DTC is operating. See section 17, Power-Down Modes, for details. 286 Description added ... P1DDR cannot be read; if it is, an undefined value will be read. Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit to 0, makes that pin an input pin. Since this register is a write-only register, do not use bit manipulation instructions to write to this register. See section 2.10.4, Access Methods for Registers with Write-Only Bits. 9.3.2 Register Configuration (1) Port 3 Data Direction Register (P3DDR) 9.5.2 Register Configuration (1) Port 7 Data Direction Register (P7DDR) 9.7.2 Register Configuration (1) Port A Data Direction Register (PADDR) 297 Description added Setting a P3DDR bit to 1 makes the corresponding port 3 pin an output pin, while clearing the bit to 0 makes the pin an input pin. Since this register is a write-only register, do not use bit manipulation instructions to write to this register. See section 2.10.4, Access Methods for Registers with Write-Only Bits. 309 Description added Setting a P7DDR bit to 1 makes the corresponding port 7 pin an output pin, while clearing the bit to 0 makes the pin an input pin. Since this register is a write-only register, do not use bit manipulation instructions to write to this register. See section 2.10.4, Access Methods for Registers with Write-Only Bits. 316 Description added Bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read. Since this register is a write-only register, do not use bit manipulation instructions to write to this register. See section 2.10.4, Access Methods for Registers with Write-Only Bits. Rev.4.00 Sep. 18, 2008 Page xii of lx REJ09B0189-0400 Item 9.8.2 Register Configuration (1) Port B Data Direction Register (PBDDR) 9.9.2 Register Configuration (1) Port C Data Direction Register (PCDDR) Page 323 Revisions (See Manual for Details) Description added ... PBDDR cannot be read; if it is, an undefined value will be read. Since this register is a write-only register, do not use bit manipulation instructions to write to this register. See section 2.10.4, Access Methods for Registers with Write-Only Bits. 331 Description added ... PCDDR cannot be read; if it is, an undefined value will be read. Setting a PCDDR bit to 1 makes the corresponding port C pin an output pin, while clearing the bit to 0, makes the pin an input pin. Since this register is a write-only register, do not use bit manipulation instructions to write to this register. See section 2.10.4, Access Methods for Registers with Write-Only Bits. 9.10.2 Register Configuration (1) Port D Data Direction Register (PDDDR) 338 Description added ... PDDDR cannot be read; if it is, an undefined value will be read. Setting a PDDDR bit to 1 makes the corresponding port C pin an output pin, while clearing the bit to 0, makes the pin an input pin. Since this register is a write-only register, do not use bit manipulation instructions to write to this register. See section 2.10.4, Access Methods for Registers with Write-Only Bits. 9.11.2 Register Configuration (1) Port E Data Direction Register (PEDDR) 343 Description added ... PEDDR cannot be read; if it is, an undefined value will be read. Setting a PEDDR bit to 1 makes the corresponding port C pin an output pin, while clearing the bit to 0, makes the pin an input pin. Since this register is a write-only register, do not use bit manipulation instructions to write to this register. See section 2.10.4, Access Methods for Registers with Write-Only Bits. 9.12.2 Register Configuration (1) Port F Data Direction Register (PFDDR) 349 Description added ... PFDDR cannot be read; if it is, an undefined value will be read. Setting a PFDDR bit to 1 makes the corresponding port C pin an output pin, while clearing the bit to 0, makes the pin an input pin. Since this register is a write-only register, do not use bit manipulation instructions to write to this register. See section 2.10.4, Access Methods for Registers with Write-Only Bits. 9.13.2 Register Configuration (1) Port G Data Direction Register (PGDDR) 354 Description added ... Also, bits 7 to 5 are reserved, and will return an undefined value if read. Setting a PGDDR bit to 1 makes the corresponding port C pin an output pin, while clearing the bit to 0, makes the pin an input pin. Since this register is a write-only register, do not use bit manipulation instructions to write to this register. See section 2.10.4, Access Methods for Registers with Write-Only Bits. Rev.4.00 Sep. 18, 2008 Page xiii of lx REJ09B0189-0400 Item 9.14 Handling of Unused Pins 10.2.1 Timer Control Register (TCR) Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0) 10.2.5 Timer Status Register (TSR) Bit 3—Input Capture/Output Compare Flag D (TGFD) Bit 2—Input Capture/Output Compare Flag C (TGFC) Page 358 368 Revisions (See Manual for Details) Newly added Note amended Note: Internal clock edge selection is valid when the input clock is φ/4 or slower. This setting is ignored if the input clock is φ /1, or when overflow/underflow of another channel is selected. (Counting occurs on the falling edge of φ when φ/1 is selected.) 383 Description amended Bit 3 TGFD 0 Description [Clearing conditions] • • (Initial value) When DTC is activated by a TGID interrupt, the DTC module MRB register DISEL bit is 0, and furthermore the transfer counter is not 0. When 0 is written to TGFD after reading TGFD = 1 Description amended Bit 2 TGFC 0 Description [Clearing conditions] • • (Initial value) When DTC is activated by a TGIC interrupt, the DTC module MRB register DISEL bit is 0, and furthermore the transfer counter is not 0. When 0 is written to TGFC after reading TGFC = 1 Bit 1—Input Capture/Output Compare Flag B (TGFB) 384 Description amended Bit 1 TGFB 0 Description [Clearing conditions] • • (Initial value) When DTC is activated by a TGIB interrupt, the DTC module MRB register DISEL bit is 0, and furthermore the transfer counter is not 0. When 0 is written to TGFB after reading TGFB = 1 Bit 0—Input Capture/Output Compare Flag A (TGFA) Description amended Bit 0 TGFA 0 Description [Clearing conditions] • • • (Initial value) When DTC is activated by a TGIA interrupt, the DTC module MRB register DISEL bit is 0, and furthermore the transfer counter is not 0. When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 When 0 is written to TGFA after reading TGFA = 1 Rev.4.00 Sep. 18, 2008 Page xiv of lx REJ09B0189-0400 Item Page Revisions (See Manual for Details) Description added 10.7 Usage Notes 427 (1) Module Stop Mode Settings Figure 10.53 436 Contention between TCNT Write and Overflow Figure amended TCNT write cycle T2 T1 φ Address TCNT address Write signal TCNT write data H'FFFF Prohibited M TCNT TCFV flag 451 11.5.5 OVF Flag Clear Operation in Interval Timer Mode 12.2.7 Serial Status Register (SSR) Bit 7—Transmit Data Register Empty (TDRE) 468 Newly added Note added Bit 7 TDRE 0 Description [Clearing conditions] • • When 0 is written to TDRE after reading TDRE = 1 When the DMAC or DTC* is activated by a TXI interrupt and writes data to TDR Note: * This bit is cleared by DTC when DISEL = 0 and furthermore the transfer counter is not 0. Bit 6—Receive Data Register Full (RDRF) Note added Bit 6 RDRF 0 Description [Clearing conditions] • • When 0 is written to RDRF after reading RDRF = 1 When the DMAC or DTC* is activated by an RXI interrupt and reads data from RDR (Initial value) Note: * This bit is cleared by DTC when DISEL = 0 and furthermore the transfer counter is not 0. Rev.4.00 Sep. 18, 2008 Page xv of lx REJ09B0189-0400 Item 12.2.7 Serial Status Register (SSR) Bit 2—Transmit End (TEND) Page 470 Revisions (See Manual for Details) Note added Bit 2 TEND 0 Description [Clearing conditions] • • When 0 is written to TDRE after reading TDRE = 1 When the DMAC or DTC* is activated by a TXI interrupt and writes data to TDR Note: * This bit is cleared by DTC when DISEL = 0 and furthermore the transfer counter is not 0. 12.3.2 Operation in 493 Asynchronous Mode Figure 12.7 Sample SCI Initialization Flowchart Note added Start initialization Clear TE and RE bits in SCR to 0 [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [4] Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE* bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits Note: * The RE bit must be set when the RxD pin is in the 1 state. If the RE bit is set t 1 with the RxD pin in the 0 state, this event may be mistakenly recognized as a start bit. Rev.4.00 Sep. 18, 2008 Page xvi of lx REJ09B0189-0400 Item Page Revisions (See Manual for Details) Note added Initialization Start transmission [1] 12.3.2 Operation in 494 Asynchronous Mode Figure 12.8 Sample Serial Transmission Flowchart Read TDRE flag in SSR [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC* is activated by a transmit data empty interrupt (TXI) request, and date is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. Note: * The TDRE flag check and clear operations are performed automatically by DTC only when the DTC DISEL bit is 0 and furthermore the transfer counter is not 0. Therefore the CPU must clear the TDRE flag when either DISEL is 1 or when DISEL is 0 and furthermore the transfer counter is 0. No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1 Yes No Break output? Yes Clear DR to 0 and set DDR to 1 [4] Clear TE bit in SCR to 0 Rev.4.00 Sep. 18, 2008 Page xvii of lx REJ09B0189-0400 Item Page Revisions (See Manual for Details) Note added Initialization [1] 12.3.2 Operation in 497 Asynchronous Mode Figure 12.10 Sample Serial Reception Data Flowchart (1) Start reception [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing and break detection: If a receive error occurs, read the [2] ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error Yes processing, ensure that the PER ∨ FER ∨ ORER = 1 ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot No Error processing be resumed if any of these flags (Continued on next page) are set to 1. In the case of a framing error, a break can be detected by reading the value of [4] Read RDRF flag in SSR the input port corresponding to the RxD pin. Read ORER, PER, and FER flags in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] SCI status check and receive data read : Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] [5] Serial reception continuation procedure: To continue serial reception, Yes before the stop bit for the current frame is received, read the Clear RE bit in SCR to 0 RDRF flag, read RDR, and clear the RDRF flag to 0. The RDRF flag is cleared automatically when DMAC or DTC* is Note: * The RDRF flag is cleared automatically by DTC activated by an RXI interrupt and only when the DTC DISEL bit is 0 and the RDR value is read. furthermore the transfer counter is not 0. Therefore the CPU must clear the RDRF flag when either DISEL is 1 or when DISEL is 0 and furthermore the transfer counter is 0. All data received? No Rev.4.00 Sep. 18, 2008 Page xviii of lx REJ09B0189-0400 Item 12.3.3 Multiprocessor Communication Function Figure 12.14 Sample Multiprocessor Serial Transmission Flowchart Page 503 Revisions (See Manual for Details) Note added Initialization Start transmission [1] [1] SCI initialization: Read TDRE flag in SSR [2] The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. No TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No TEND = 1 Yes No Break output? Yes [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is [3] possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC* is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to [4] 1, clear DR to 0, then clear the TE bit in SCR to 0. Note: * The TDRE flag is cleared automatically by DTC only when the DTC DISEL bit is 0 and furthermore the transfer counter is not 0. Therefore the CPU must clear the TDRE flag when either DISEL is 1 or when DISEL is 0 and furthermore the transfer counter is 0. Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 Rev.4.00 Sep. 18, 2008 Page xix of lx REJ09B0189-0400 Item Page Revisions (See Manual for Details) Note added Initialization Start transmission [1] 12.3.4 Operation in 512 Clocked Synchronous Mode Figure 12.21 Sample Serial Transmission Flowchart [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC* is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. Note: * The TDRE flag is cleared automatically by DTC only when the DTC DISEL bit is 0 and furthermore the transfer counter is not 0. Therefore the CPU must clear the TDRE flag when either DISEL is 1 or when DISEL is 0 and furthermore the transfer counter is 0. Read TDRE flag in SSR [2] No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1 Yes Clear TE bit in SCR to 0 Rev.4.00 Sep. 18, 2008 Page xx of lx REJ09B0189-0400 Item Page Revisions (See Manual for Details) Note added Initialization Start reception [1] 12.3.4 Operation in 515 Clocked Synchronous Mode Figure 12.23 Sample Serial Reception Flowchart [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Read ORER flag in SSR Yes ORER = 1 No [2] [3] Error processing (Continued below) [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. The RDRF flag is cleared automatically when the DMAC or DTC* is activated by a receive data full interrupt (RXI) request and the RDR value is read. Note: * The RDRF flag is cleared automatically by DTC only when the DTC DISEL bit is 0 and furthermore the transfer counter is not 0. Therefore the CPU must clear the RDRF flag when either DISEL is 1 or when DISEL is 0 and furthermore the transfer counter is 0. Read RDRF flag in SSR [4] No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [3] [5] Error processing Overrun error processing Clear ORER flag in SSR to 0 Rev.4.00 Sep. 18, 2008 Page xxi of lx REJ09B0189-0400 Item Page Revisions (See Manual for Details) Note added Initialization Start transmission/reception [1] 12.3.4 Operation in 517 Clocked Synchronous Mode Figure 12.25 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error processing: Read ORER flag in SSR Yes [3] Error processing ORER = 1 No If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DMAC or DTC* is activated by a receive data full interrupt (RXI) request and the RDR value is read. No All data received? Yes [5] Clear TE and RE bits in SCR to 0 Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. * The TDRE flag and RDRF flag clear operations are performed automatically by DTC only when the corresponding DTC transfer DISEL bit is 0 and furthermore the transfer counter is not 0. Therefore the CPU must clear the corresponding flag when either the corresponding DTC transfer DISEL is 1 or when the corresponding DTC transfer DISEL is 0 and furthermore the transfer counter is 0. Rev.4.00 Sep. 18, 2008 Page xxii of lx REJ09B0189-0400 Item Page Revisions (See Manual for Details) Note added ... The TDRE flag is cleared to 0 automatically when data transfer is performed by the DMAC or DTC*. ... ... The RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC or DTC*. ... Note : * The flag is cleared when DISEL is 0 and furthermore the transfer counter is not 0. 12.4 SCI Interrupts 518 12.5 Usage Notes 520 (1) Module Stop Mode Settings (8) Restrictions on Use of DMAC or DTC 523 Description added Description added (b) When RDR is read by the DMAC or DTC, be sure to set the activation source to the relevant SCI reception end interrupt (RXI). (c) During data transfers, flags are cleared automatically by DTC only when the DTC DISEL bit is 0 and furthermore the transfer counter is not 0. Therefore the CPU must clear the flags when either DISEL is 1 or when DISEL is 0 and furthermore the transfer counter is 0. In particular, note that during transmission, data will not be transmitted correctly unless the CPU clears the TDRE flag. 17.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Table 17.4 Oscillation Stabilization Time Settings 18.7 Usage Note • Characteristics of the F-ZTAT and Mask ROM Versions • General Notes on Printed Circuit Board Deign 630 Table amended STS2 STS1 STS0 Standby Time 16 MHz 13 MHz 10 MHz 8 MHz 0 0 0 1 1 0 1 1 0 0 1 1 0 1 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states 2048 states 16 states 0.51 1.0 2.0 4.1 8.2 16.4 0.13 1.0 0.63 1.3 2.5 5.0 10.1 20.2 0.16 1.2 0.82 1.6 3.3 6.6 13.1 26.2 0.20 1.6 1.0 2.0 4.1 8.2 16.4 32.8 0.26 2.0 6 MHz 1.4 2.7 5.5 10.9 21.8 43.7 0.34 2.7 4 MHz 2.0 4.1 8.2 16.4 32.8 65.5 0.51 4.0 2 MHz 4.1 8.2 16.4 32.8 65.5 131.1 1.0 8.0 µs Unit ms : Recommended time setting 659 Title added Description added Rev.4.00 Sep. 18, 2008 Page xxiii of lx REJ09B0189-0400 Item Page Revisions (See Manual for Details) Note added Addressing Mode/ Instruction Length (Bytes) A.1 Instruction List 665 Table A.1 Data Transfer Instructions Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — Condition Code Operation (@SP ERn32,SP+4 SP) Repeated for each register restored IHNZVC —————— No. of States*1 Advanced 7/9/11 [1] Mnemonic LDM* LDM @SP+,(ERm-ERn) L 4 STM* STM (ERm-ERn),@-SP L 4 (SP-4 SP,ERn32 @SP) Repeated for each register saved —————— 7/9/11 [1] Note : The STM/LDM instructions may only be used with the ER0 to ER6 registers. Table A.2 Arithmetic Instructions 669 Note added Addressing Mode/ Instruction Length (Bytes) Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — Condition Code Operation @ERd-0→CCR set, (1)→ ( of @ERd IHNZVC —— No. of States*1 Advanced 4 Mnemonic TAS* TAS @ERd*2 ↔ ↔ B 4 0— Note : The TAS instruction may only be used with the ER0, ER1, ER4, and ER5 registers. A.4 Number of 711 States Required for Instruction Execution Table A.15 Number of Cycles in Instruction Execution 715 Note added Branch Instruction Address Fetch Read Instruction LDM*4 Mnemonic LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) I 2 2 2 J Byte Stack Data Operation Access K 4 6 8 L Word Data Access M Internal Operation N 1 1 1 Note amended Branch Instruction Address Fetch Read Instruction STM*4 Mnemonic STM.L (ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP STM.L (ERn-ERn+3), @-SP TAS*3 TAS @ERd I 2 2 2 2 J Byte Stack Data Operation Access K 4 6 8 2 L Word Data Access M Internal Operation N 1 1 1 716 Note added Notes : 4. The STM/LDM instructions may only be used with the ER0 to ER6 registers. Rev.4.00 Sep. 18, 2008 Page xxiv of lx REJ09B0189-0400 Item A.5 Bus States during Instruction Execution Table A.16 Instruction Execution Cycles Page 724 Revisions (See Manual for Details) Note added 1 Instruction LDM.L @SP+, R:W 2nd (ERn–ERn+1)*9 LDM.L @SP+,(ERn–ERn+2)*9 R:W 2nd LDM.L @SP+,(ERn–ERn+3)*9 R:W 2nd 2 3 4 5 R:W:M NEXT Internal operation, R:W:M stack (H)*3 R:W stack (L)*3 1 state Internal operation, R:W:M stack (H)*3 R:W stack (L)*3 1 state R:W NEXT Internal operation, R:W:M stack (H)*3 R:W stack (L)*3 1 state R:W NEXT 6 7 8 9 729 Note added 1 Instruction STM.L(ERn–ERn+1),@–SP*9 R:W 2nd STM.L(ERn–ERn+2),@–SP*9 R:W 2nd 2 3 4 5 R:W:M NEXT Internal operation, W:W:M stack (H)*3 W:W stack (L)*3 1 state *3 W:W stack (L)*3 R:W:M NEXT Internal operation, W:W:M stack (H) 1 state R:W:M NEXT Internal operation, W:W:M stack (H)*3 W:W stack (L)*3 1 state 6 7 8 9 STM.L(ERn–ERn+3),@–SP*9 R:W 2nd 730 Note added Notes : 9. The STM/LDM instructions may only be used with the ER0 to ER6 registers. A.6 Condition Code Modification Table A.17 Condition Code Modification 733 Note added Instruction LDM* 2 H N Z V C Definition ————— 735 Note added Instruction STM* 2 H N Z V C Definition ————— 736 Note added Instruction TAS* 1 H — N Z V 0 C — Definition N = Dm Z = Dm · Dm–1 · ...... · D0 Notes : 2. The STM/LDM instructions may only be used with the ER0 to ER6 registers. B.2 Functions TCR1—Timer Control Register 1 785 Description added Clock Edge 1 and 0 0 0 Count at rising edge 1 Count at falling edge 1 — Count at both edges Note: The internal clock edge selection is valid when the input clock is φ/4 or slower. This setting is ignored if the input clock is φ/1, or when overflow/underflow of another channel is selected. (Counting occurs on the falling edge of φ when φ/1 is selected.) Rev.4.00 Sep. 18, 2008 Page xxv of lx REJ09B0189-0400 Item B.2 Functions TCR2—Timer Control Register 2 Page 791 Revisions (See Manual for Details) Description added Clock Edge 1 and 0 0 0 Count at rising edge 1 Count at falling edge 1 — Count at both edges Note: The internal clock edge selection is valid when the input clock is φ/4 or slower. This setting is ignored if the input clock is φ/1, or when overflow/underflow of another channel is selected. (Counting occurs on the falling edge of φ when φ/1 is selected.) TCSR0—Timer Control/Status Register 801 Note added Bit Initial value Read/Write 7 OVF 0 R/(W)*1 6 WT/IT 0 R/W 5 TME 0 R/W 4 — 1 — 3 — 1 — 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Clock Select 2 to 0 CKS2 CKS1 CKS0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Clock φ/2 (Initial value) φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Overflow Period* (when φ = 10 MHz) 51.2 µs 1.6 ms 3.2 ms 13.2 ms 52.4 ms 209.8 ms 838.8 ms 3.36 s Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. Timer Enable 0 TCNT is initialized to H'00 and count operation is halted 1 TCNT counts Timer Mode Select 0 Interval timer mode: Interval timer interrupt (WOVI) request is sent to CPU when TCNT overflows 1 Watchdog timer mode: Internal reset can be selected when TCNT overflows* Note: * For details of the case where TCNT overflows in watchdog timer mode, see section 11.2.3, Reset Control/Status Register (RSTCSR). Overflow Flag 0 [Clearing condition] • Cleared by reading*2 TCSR when OVF = 1, then writing 0 to OVF 1 [Setting condition] • When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. Notes: 1. Only 0 can be written, to clear the flag. TCSR is write-protected by a password to prevent accidental overwriting. For details see section 11.2.4, Notes on Register Access. 2. If the interval timer interrupt is disabled and the OVF flag is polled, the application should read the OVF = 1 state at least twice. Rev.4.00 Sep. 18, 2008 Page xxvi of lx REJ09B0189-0400 Item B.2 Functions SSR0—Serial Status Register 0 Page 807 Revisions (See Manual for Details) Note added Bit : 7 TDRE Initial value : R/W : 1 R/(W)*1 6 RDRF 0 5 ORER 0 4 FER 0 3 PER 0 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] • When data with a 0 multiprocessor bit is received 1 [Setting condition] • When data with a 1 multiprocessor bit is received Transmit End 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC*2 is activated by a TXI interrupt request and writes data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character 1 Parity Error 0 [Clearing condition] • When 0 is written to PER after reading PER = 1 1 [Setting condition] • When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing Error 0 [Clearing condition] • When 0 is written to FER after reading FER = 1 1 [Setting condition] • When the SCI checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 Overrun Error 0 [Clearing condition] • When 0 is written to ORER after reading ORER = 1 1 [Setting condition] • When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DTC*2 is activated by an RXI interrupt request and reads data to RDR 1 [Setting condition] • When serial reception ends normally and receive data is transferred from RSR to RDR Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC*2 is activated by a TXI interrupt request and writes data to TDR 1 [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR Notes: 1. Only 0 can be written, to clear the flag. 2. Flags are only cleared when DISEL is 0 and furthermore the transfer counter is not 0. Rev.4.00 Sep. 18, 2008 Page xxvii of lx REJ09B0189-0400 Item B.2 Functions SSR1—Serial Status Register 1 Page 813 Revisions (See Manual for Details) Note added Bit : 7 TDRE Initial value : R/W : 1 R/(W)*1 6 RDRF 0 5 ORER 0 4 FER 0 3 PER 0 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] • When data with a 0 multiprocessor bit is received 1 [Setting condition] • When data with a 1 multiprocessor bit is received Transmit End 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC*2 is activated by a TXI interrupt request and writes data to TDR 1 [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character Parity Error 0 [Clearing condition] • When 0 is written to PER after reading PER = 1 1 [Setting condition] • When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing Error 0 [Clearing condition] • When 0 is written to FER after reading FER = 1 1 [Setting condition] • When the SCI checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 Overrun Error 0 [Clearing condition] • When 0 is written to ORER after reading ORER = 1 1 [Setting condition] • When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DTC*2 is activated by an RXI interrupt request and reads data from RDR 1 [Setting condition] • When serial reception ends normally and receive data is transferred from RSR to RDR Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC*2 is activated by a TXI interrupt request and writes data to TDR 1 [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR Notes: 1. Only 0 can be written, to clear the flag. 2. Flags are only cleared when DISEL is 0 and furthermore the transfer counter is not 0. Rev.4.00 Sep. 18, 2008 Page xxviii of lx REJ09B0189-0400 Item B.2 Functions SSR2—Serial Status Register 2 Page 819 Revisions (See Manual for Details) Note added Bit : 7 TDRE Initial value : R/W : 1 R/(W)*1 6 RDRF 0 5 ORER 0 4 FER 0 3 PER 0 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] • When data with a 0 multiprocessor bit is received 1 [Setting condition] • When data with a 1 multiprocessor bit is received Transmit End 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC*2 is activated by a TXI interrupt request and writes data to TDR 1 [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character Parity Error 0 [Clearing condition] • When 0 is written to PER after reading PER = 1 1 [Setting condition] • When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing Error 0 [Clearing condition] • When 0 is written to FER after reading FER = 1 1 [Setting condition] • When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 Overrun Error 0 [Clearing condition] • When 0 is written to ORER after reading ORER = 1 1 [Setting condition] • When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DTC*2 is activated by an RXI interrupt request and reads data from RDR 1 [Setting condition] • When serial reception ends normally and receive data is transferred from RSR to RDR Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC*2 is activated by a TXI interrupt request and writes data to TDR 1 [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR Notes: 1. Only 0 can be written, to clear the flag. 2. Flags are only cleared when DISEL is 0 and furthermore the transfer counter is not 0. Rev.4.00 Sep. 18, 2008 Page xxix of lx REJ09B0189-0400 Item C.3 Port 4 Block Diagram Figure C.9 Port 4 Block Diagram (Pins P40 to P44, P46, and P47) Figure C.10 Port 4 Block Diagram (Pin P45) Appendix G Package Dimensions Figure G.1 TFP100B, TFP-100BV Package Dimensions Figure G.2 TFP100G, TFP-100GA Package Dimensions Figure G.3 TBP112A, TBP-112AV Package Dimensions Page 835 Revisions (See Manual for Details) Legend amended RPOR4: Read port 4 Legend amended RPOR4: Read port 4 869 Figure replaced 870 Figure replaced 871 Figure replaced Figure G.4 BP-112, 872 BP-112V Package Dimensions Figure replaced All trademarks and registered trademarks are the property of their respective owners. Rev.4.00 Sep. 18, 2008 Page xxx of lx REJ09B0189-0400 Contents Section 1 Overview............................................................................................... 1 1.1 1.2 1.3 Overview................................................................................................................................ 1 Internal Block Diagrams ........................................................................................................ 5 Pin Description....................................................................................................................... 6 1.3.1 Pin Arrangements...................................................................................................... 6 1.3.2 Pin Functions in Each Operating Mode .................................................................... 8 1.3.3 Pin Functions .......................................................................................................... 12 Section 2 CPU..................................................................................................... 17 2.1 Overview.............................................................................................................................. 17 2.1.1 Features................................................................................................................... 17 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................... 18 2.1.3 Differences from H8/300 CPU................................................................................ 19 2.1.4 Differences from H8/300H CPU............................................................................. 19 CPU Operating Modes ......................................................................................................... 20 Address Space ...................................................................................................................... 25 Register Configuration ......................................................................................................... 26 2.4.1 Overview................................................................................................................. 26 2.4.2 General Registers .................................................................................................... 27 2.4.3 Control Registers .................................................................................................... 28 2.4.4 Initial Register Values............................................................................................. 30 Data Formats ........................................................................................................................ 31 2.5.1 General Register Data Formats ............................................................................... 31 2.5.2 Memory Data Formats ............................................................................................ 33 Instruction Set ...................................................................................................................... 34 2.6.1 Overview................................................................................................................. 34 2.6.2 Instructions and Addressing Modes ........................................................................ 35 2.6.3 Table of Instructions Classified by Function .......................................................... 37 2.6.4 Basic Instruction Formats ....................................................................................... 47 2.6.5 Notes on Use of Bit-Manipulation Instructions ...................................................... 48 Addressing Modes and Effective Address Calculation ........................................................ 48 2.7.1 Addressing Mode .................................................................................................... 48 2.7.2 Effective Address Calculation................................................................................. 52 Processing States.................................................................................................................. 56 2.8.1 Overview................................................................................................................. 56 2.8.2 Reset State............................................................................................................... 57 2.8.3 Exception-Handling State ....................................................................................... 58 Rev.4.00 Sep. 18, 2008 Page xxxi of lx REJ09B0189-0400 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.8.4 Program Execution State......................................................................................... 61 2.8.5 Bus-Released State ................................................................................................. 61 2.8.6 Power-Down State .................................................................................................. 61 2.9 Basic Timing........................................................................................................................ 62 2.9.1 Overview................................................................................................................. 62 2.9.2 On-Chip Memory (ROM, RAM) ............................................................................ 62 2.9.3 On-Chip Supporting Module Access Timing ......................................................... 64 2.9.4 External Address Space Access Timing ................................................................. 65 2.10 Usage Notes ......................................................................................................................... 65 2.10.1 TAS Instruction....................................................................................................... 65 2.10.2 STM/LDM Instruction Usage ................................................................................. 66 2.10.3 Bit Manipulation Instructions ................................................................................. 66 2.10.4 Access Methods for Registers with Write-Only Bits .............................................. 68 Section 3 MCU Operating Modes .......................................................................71 3.1 Overview.............................................................................................................................. 71 3.1.1 Operating Mode Selection ...................................................................................... 71 3.1.2 Register Configuration............................................................................................ 72 Register Descriptions ........................................................................................................... 72 3.2.1 Mode Control Register (MDCR) ............................................................................ 72 3.2.2 System Control Register (SYSCR) ......................................................................... 73 Operating Mode Descriptions .............................................................................................. 75 3.3.1 Mode 4 .................................................................................................................... 75 3.3.2 Mode 5 .................................................................................................................... 75 3.3.3 Mode 6 .................................................................................................................... 76 3.3.4 Mode 7 .................................................................................................................... 76 Pin Functions in Each Operating Mode ............................................................................... 77 Memory Map in Each Operating Mode ............................................................................... 77 3.2 3.3 3.4 3.5 Section 4 Exception Handling .............................................................................79 4.1 Overview.............................................................................................................................. 79 4.1.1 Exception Handling Types and Priority.................................................................. 79 4.1.2 Exception Handling Operation................................................................................ 80 4.1.3 Exception Sources and Vector Table ...................................................................... 80 Reset ................................................................................................................................ 82 4.2.1 Overview................................................................................................................. 82 4.2.2 Reset Types............................................................................................................. 82 4.2.3 Reset Sequence ....................................................................................................... 83 4.2.4 Interrupts after Reset............................................................................................... 85 4.2.5 State of On-Chip Supporting Modules after Reset Release .................................... 85 Traces ................................................................................................................................ 86 4.2 4.3 Rev.4.00 Sep. 18, 2008 Page xxxii of lx REJ09B0189-0400 4.4 4.5 4.6 4.7 Interrupts .............................................................................................................................. 87 Trap Instruction.................................................................................................................... 88 Stack Status after Exception Handling................................................................................. 89 Notes on Use of the Stack .................................................................................................... 90 Section 5 Interrupt Controller ............................................................................. 91 5.1 Overview.............................................................................................................................. 91 5.1.1 Features................................................................................................................... 91 5.1.2 Block Diagram ........................................................................................................ 92 5.1.3 Pin Configuration.................................................................................................... 93 5.1.4 Register Configuration............................................................................................ 93 Register Descriptions ........................................................................................................... 94 5.2.1 System Control Register (SYSCR) ......................................................................... 94 5.2.2 Interrupt Priority Registers A to D, F, G, J, K, M (IPRA to IPRD, IPRF, IPRG, IPRJ, IPRK, IPRM)................................................. 95 5.2.3 IRQ Enable Register (IER) ..................................................................................... 96 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)........................................ 97 5.2.5 IRQ Status Register (ISR)....................................................................................... 98 Interrupt Sources .................................................................................................................. 99 5.3.1 External Interrupts .................................................................................................. 99 5.3.2 Internal Interrupts.................................................................................................. 101 5.3.3 Interrupt Exception Handling Vector Table.......................................................... 101 Interrupt Operation............................................................................................................. 104 5.4.1 Interrupt Control Modes and Interrupt Operation ................................................. 104 5.4.2 Interrupt Control Mode 0 ...................................................................................... 107 5.4.3 Interrupt Control Mode 2 ...................................................................................... 109 5.4.4 Interrupt Exception Handling Sequence ............................................................... 111 5.4.5 Interrupt Response Times ..................................................................................... 112 Usage Notes ....................................................................................................................... 113 5.5.1 Contention between Interrupt Generation and Disabling...................................... 113 5.5.2 Instructions that Disable Interrupts ....................................................................... 114 5.5.3 Times when Interrupts Are Disabled .................................................................... 114 5.5.4 Interrupts during Execution of EEPMOV Instruction........................................... 115 5.5.5 IRQ Interrupts ....................................................................................................... 115 5.5.6 NMI Interrupt Usage Notes................................................................................... 115 DTC and DMAC Activation by Interrupt .......................................................................... 116 5.6.1 Overview............................................................................................................... 116 5.6.2 Block Diagram ...................................................................................................... 116 5.6.3 Operation .............................................................................................................. 117 5.2 5.3 5.4 5.5 5.6 Rev.4.00 Sep. 18, 2008 Page xxxiii of lx REJ09B0189-0400 Section 6 Bus Controller....................................................................................119 6.1 Overview............................................................................................................................ 119 6.1.1 Features................................................................................................................. 119 6.1.2 Block Diagram...................................................................................................... 120 6.1.3 Pin Configuration.................................................................................................. 121 6.1.4 Register Configuration.......................................................................................... 122 Register Descriptions ......................................................................................................... 123 6.2.1 Bus Width Control Register (ABWCR)................................................................ 123 6.2.2 Access State Control Register (ASTCR) .............................................................. 124 6.2.3 Wait Control Registers H and L (WCRH, WCRL)............................................... 125 6.2.4 Bus Control Register H (BCRH) .......................................................................... 129 6.2.5 Bus Control Register L (BCRL) ........................................................................... 131 6.2.6 Pin Function Control Register (PFCR) ................................................................. 132 Overview of Bus Control ................................................................................................... 134 6.3.1 Area Divisions ...................................................................................................... 134 6.3.2 Bus Specifications................................................................................................. 135 6.3.3 Memory Interfaces................................................................................................ 136 6.3.4 Interface Specifications for Each Area ................................................................. 137 6.3.5 Chip Select Signals ............................................................................................... 138 Basic Bus Interface ............................................................................................................ 139 6.4.1 Overview............................................................................................................... 139 6.4.2 Data Size and Data Alignment.............................................................................. 139 6.4.3 Valid Strobes......................................................................................................... 141 6.4.4 Basic Timing......................................................................................................... 142 6.4.5 Wait Control ......................................................................................................... 150 Burst ROM Interface.......................................................................................................... 152 6.5.1 Overview............................................................................................................... 152 6.5.2 Basic Timing......................................................................................................... 152 6.5.3 Wait Control ......................................................................................................... 154 Idle Cycle........................................................................................................................... 155 6.6.1 Operation .............................................................................................................. 155 6.6.2 Pin States in Idle Cycle ......................................................................................... 158 Bus Release........................................................................................................................ 159 6.7.1 Overview............................................................................................................... 159 6.7.2 Operation .............................................................................................................. 159 6.7.3 Pin States in External Bus Released State............................................................. 160 6.7.4 Transition Timing ................................................................................................. 161 6.7.5 Usage Note............................................................................................................ 162 Bus Arbitration................................................................................................................... 162 6.8.1 Overview............................................................................................................... 162 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Rev.4.00 Sep. 18, 2008 Page xxxiv of lx REJ09B0189-0400 6.8.2 Operation .............................................................................................................. 162 6.8.3 Bus Transfer Timing ............................................................................................. 163 6.8.4 External Bus Release Usage Note......................................................................... 163 6.9 Resets and the Bus Controller ............................................................................................ 164 6.10 External Module Expansion Function................................................................................ 164 6.10.1 Overview............................................................................................................... 164 6.10.2 Pin Configuration.................................................................................................. 165 6.10.3 Register Configuration.......................................................................................... 165 6.10.4 Interrupt Request Input Pin Select Register 0 (IPINSEL0)................................... 166 6.10.5 External Module Connection Output Pin Select Register (OPINSEL) ................. 168 6.10.6 Module Stop Control Register B (MSTPCRB)..................................................... 170 6.10.7 Basic Timing......................................................................................................... 171 6.10.8 Notes on Use of External Module Extended Functions ........................................ 172 Section 7 DMA Controller................................................................................ 173 7.1 Overview............................................................................................................................ 173 7.1.1 Features................................................................................................................. 173 7.1.2 Block Diagram ...................................................................................................... 174 7.1.3 Overview of Functions.......................................................................................... 175 7.1.4 Pin Configuration.................................................................................................. 177 7.1.5 Register Configuration.......................................................................................... 178 Register Descriptions (1) (Short Address Mode) ............................................................... 179 7.2.1 Memory Address Register (MAR)........................................................................ 180 7.2.2 I/O Address Register (IOAR) ............................................................................... 180 7.2.3 Execute Transfer Count Register (ETCR) ............................................................ 181 7.2.4 DMA Control Register (DMACR)........................................................................ 182 7.2.5 DMA Band Control Register (DMABCR)............................................................ 186 Register Descriptions (2) (Full Address Mode) ................................................................. 191 7.3.1 Memory Address Register (MAR)........................................................................ 191 7.3.2 I/O Address Register (IOAR) ............................................................................... 191 7.3.3 Execute Transfer Count Register (ETCR) ............................................................ 192 7.3.4 DMA Control Register (DMACR)........................................................................ 194 7.3.5 DMA Band Control Register (DMABCR)............................................................ 198 Register Descriptions (3).................................................................................................... 204 7.4.1 DMA Write Enable Register (DMAWER) ........................................................... 204 7.4.2 DMA Terminal Control Register (DMATCR)...................................................... 207 7.4.3 Module Stop Control Register A (MSTPCRA) .................................................... 208 Operation............................................................................................................................ 209 7.5.1 Transfer Modes ..................................................................................................... 209 7.5.2 Sequential Mode ................................................................................................... 211 7.5.3 Idle Mode.............................................................................................................. 214 Rev.4.00 Sep. 18, 2008 Page xxxv of lx REJ09B0189-0400 7.2 7.3 7.4 7.5 7.6 7.7 7.5.4 Repeat Mode ......................................................................................................... 217 7.5.5 Normal Mode........................................................................................................ 221 7.5.6 Block Transfer Mode ............................................................................................ 224 7.5.7 DMAC Activation Sources ................................................................................... 230 7.5.8 Basic DMAC Bus Cycles...................................................................................... 232 7.5.9 DMAC Bus Cycles (Dual Address Mode)............................................................ 233 7.5.10 DMAC Multi-Channel Operation ......................................................................... 240 7.5.11 Relation between the DMAC, External Bus Requests, and the DTC ................... 242 7.5.12 NMI Interrupts and DMAC .................................................................................. 243 7.5.13 Forced Termination of DMAC Operation............................................................. 244 7.5.14 Clearing Full Address Mode................................................................................. 245 Interrupts............................................................................................................................ 246 Usage Notes ....................................................................................................................... 247 Section 8 Data Transfer Controller (DTC) ........................................................251 8.1 Overview............................................................................................................................ 251 8.1.1 Features................................................................................................................. 251 8.1.2 Block Diagram...................................................................................................... 252 8.1.3 Register Configuration.......................................................................................... 253 Register Descriptions ......................................................................................................... 254 8.2.1 DTC Mode Register A (MRA) ............................................................................. 254 8.2.2 DTC Mode Register B (MRB).............................................................................. 256 8.2.3 DTC Source Address Register (SAR)................................................................... 257 8.2.4 DTC Destination Address Register (DAR)........................................................... 257 8.2.5 DTC Transfer Count Register A (CRA) ............................................................... 258 8.2.6 DTC Transfer Count Register B (CRB)................................................................ 258 8.2.7 DTC Enable Register (DTCER) ........................................................................... 259 8.2.8 DTC Vector Register (DTVECR)......................................................................... 260 8.2.9 Module Stop Control Register A (MSTPCRA) .................................................... 261 Operation ........................................................................................................................... 262 8.3.1 Overview............................................................................................................... 262 8.3.2 Activation Sources................................................................................................ 264 8.3.3 DTC Vector Table ................................................................................................ 265 8.3.4 Location of Register Information in Address Space ............................................. 268 8.3.5 Normal Mode........................................................................................................ 269 8.3.6 Repeat Mode ......................................................................................................... 270 8.3.7 Block Transfer Mode ............................................................................................ 271 8.3.8 Chain Transfer ...................................................................................................... 273 8.3.9 Operation Timing.................................................................................................. 274 8.3.10 Number of DTC Execution States ........................................................................ 275 8.3.11 Procedures for Using DTC.................................................................................... 277 8.2 8.3 Rev.4.00 Sep. 18, 2008 Page xxxvi of lx REJ09B0189-0400 8.4 8.5 8.3.12 Examples of Use of the DTC ................................................................................ 278 Interrupts ............................................................................................................................ 280 Usage Notes ....................................................................................................................... 280 Section 9 I/O Ports ............................................................................................ 281 9.1 9.2 Overview............................................................................................................................ 281 Port 1 .............................................................................................................................. 285 9.2.1 Overview............................................................................................................... 285 9.2.2 Register Configuration.......................................................................................... 286 9.2.3 Pin Functions ........................................................................................................ 288 Port 3 .............................................................................................................................. 296 9.3.1 Overview............................................................................................................... 296 9.3.2 Register Configuration.......................................................................................... 297 9.3.3 Pin Functions ........................................................................................................ 302 Port 4 .............................................................................................................................. 304 9.4.1 Overview............................................................................................................... 304 9.4.2 Register Configuration.......................................................................................... 304 9.4.3 Pin Functions ........................................................................................................ 307 Port 7 .............................................................................................................................. 308 9.5.1 Overview............................................................................................................... 308 9.5.2 Register Configuration.......................................................................................... 309 9.5.3 Pin Functions ........................................................................................................ 312 Port 9 .............................................................................................................................. 314 9.6.1 Overview............................................................................................................... 314 9.6.2 Register Configuration.......................................................................................... 314 9.6.3 Pin Functions ........................................................................................................ 315 Port A .............................................................................................................................. 315 9.7.1 Overview............................................................................................................... 315 9.7.2 Register Configuration.......................................................................................... 316 9.7.3 Pin Functions ........................................................................................................ 319 9.7.4 MOS Input Pull-Up Function................................................................................ 321 Port B .............................................................................................................................. 322 9.8.1 Overview............................................................................................................... 322 9.8.2 Register Configuration.......................................................................................... 323 9.8.3 Pin Functions ........................................................................................................ 325 9.8.4 MOS Input Pull-Up Function................................................................................ 329 Port C .............................................................................................................................. 330 9.9.1 Overview............................................................................................................... 330 9.9.2 Register Configuration.......................................................................................... 331 9.9.3 Pin Functions in Each Mode ................................................................................. 333 9.9.4 MOS Input Pull-Up Function................................................................................ 336 Rev.4.00 Sep. 18, 2008 Page xxxvii of lx REJ09B0189-0400 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 Port D .............................................................................................................................. 337 9.10.1 Overview............................................................................................................... 337 9.10.2 Register Configuration.......................................................................................... 338 9.10.3 Pin Functions in Each Mode ................................................................................. 340 9.10.4 MOS Input Pull-Up Function................................................................................ 341 9.11 Port E .............................................................................................................................. 342 9.11.1 Overview............................................................................................................... 342 9.11.2 Register Configuration.......................................................................................... 343 9.11.3 Pin Functions in Each Mode ................................................................................. 345 9.11.4 MOS Input Pull-Up Function................................................................................ 346 9.12 Port F .............................................................................................................................. 348 9.12.1 Overview............................................................................................................... 348 9.12.2 Register Configuration.......................................................................................... 349 9.12.3 Pin Functions ........................................................................................................ 351 9.13 Port G .............................................................................................................................. 353 9.13.1 Overview............................................................................................................... 353 9.13.2 Register Configuration.......................................................................................... 354 9.13.3 Pin Functions ........................................................................................................ 356 9.14 Handling of Unused Pins ................................................................................................... 358 Section 10 16-Bit Timer Pulse Unit (TPU) .......................................................359 10.1 Overview............................................................................................................................ 359 10.1.1 Features................................................................................................................. 359 10.1.2 Block Diagram...................................................................................................... 363 10.1.3 Pin Configuration.................................................................................................. 364 10.1.4 Register Configuration.......................................................................................... 365 10.2 Register Descriptions ......................................................................................................... 366 10.2.1 Timer Control Register (TCR).............................................................................. 366 10.2.2 Timer Mode Register (TMDR) ............................................................................. 370 10.2.3 Timer I/O Control Register (TIOR) ...................................................................... 372 10.2.4 Timer Interrupt Enable Register (TIER) ............................................................... 379 10.2.5 Timer Status Register (TSR)................................................................................. 381 10.2.6 Timer Counter (TCNT)......................................................................................... 385 10.2.7 Timer General Register (TGR) ............................................................................. 385 10.2.8 Timer Start Register (TSTR) ................................................................................ 386 10.2.9 Timer Synchro Register (TSYR) .......................................................................... 387 10.2.10 Module Stop Control Register A (MSTPCRA) .................................................... 388 10.3 Interface to Bus Master ...................................................................................................... 389 10.3.1 16-Bit Registers .................................................................................................... 389 10.3.2 8-Bit Registers ...................................................................................................... 389 10.4 Operation ........................................................................................................................... 391 Rev.4.00 Sep. 18, 2008 Page xxxviii of lx REJ09B0189-0400 10.4.1 Overview............................................................................................................... 391 10.4.2 Basic Functions..................................................................................................... 392 10.4.3 Synchronous Operation......................................................................................... 399 10.4.4 Buffer Operation ................................................................................................... 401 10.4.5 PWM Modes ......................................................................................................... 405 10.4.6 Phase Counting Mode ........................................................................................... 411 10.5 Interrupts ............................................................................................................................ 416 10.5.1 Interrupt Sources and Priorities............................................................................. 416 10.5.2 DTC and DMAC Activation ................................................................................. 417 10.6 Operation Timing............................................................................................................... 418 10.6.1 Input/Output Timing ............................................................................................. 418 10.6.2 Interrupt Signal Timing......................................................................................... 423 10.7 Usage Notes ....................................................................................................................... 427 Section 11 Watchdog Timer (WDT)................................................................. 437 11.1 Overview............................................................................................................................ 437 11.1.1 Features................................................................................................................. 437 11.1.2 Block Diagram ...................................................................................................... 438 11.1.3 Register Configuration.......................................................................................... 439 11.2 Register Descriptions ......................................................................................................... 440 11.2.1 Timer Counter (TCNT)......................................................................................... 440 11.2.2 Timer Control/Status Register (TCSR) ................................................................. 440 11.2.3 Reset Control/Status Register (RSTCSR) ............................................................. 442 11.2.4 Notes on Register Access...................................................................................... 444 11.3 Operation............................................................................................................................ 446 11.3.1 Watchdog Timer Operation .................................................................................. 446 11.3.2 Interval Timer Operation ...................................................................................... 447 11.3.3 Timing of Setting of Overflow Flag (OVF) .......................................................... 448 11.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) .......................... 449 11.4 Interrupts ............................................................................................................................ 449 11.5 Usage Notes ....................................................................................................................... 450 11.5.1 Contention between Timer Counter (TCNT) Write and Increment ...................... 450 11.5.2 Changing Value of CKS2 to CKS0....................................................................... 450 11.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................. 451 11.5.4 Internal Reset in Watchdog Timer Mode.............................................................. 451 11.5.5 OVF Flag Clear Operation in Interval Timer Mode.............................................. 451 Section 12 Serial Communication Interface (SCI) ........................................... 453 12.1 Overview............................................................................................................................ 453 12.1.1 Features................................................................................................................. 453 12.1.2 Block Diagram ...................................................................................................... 455 Rev.4.00 Sep. 18, 2008 Page xxxix of lx REJ09B0189-0400 12.2 12.3 12.4 12.5 12.1.3 Pin Configuration.................................................................................................. 457 12.1.4 Register Configuration.......................................................................................... 458 Register Descriptions ......................................................................................................... 459 12.2.1 Receive Shift Register (RSR) ............................................................................... 459 12.2.2 Receive Data Register (RDR) ............................................................................... 459 12.2.3 Transmit Shift Register (TSR) .............................................................................. 460 12.2.4 Transmit Data Register (TDR).............................................................................. 460 12.2.5 Serial Mode Register (SMR) ................................................................................ 461 12.2.6 Serial Control Register (SCR)............................................................................... 464 12.2.7 Serial Status Register (SSR) ................................................................................. 467 12.2.8 Bit Rate Register (BRR) ....................................................................................... 472 12.2.9 Smart Card Mode Register (SCMR) ..................................................................... 480 12.2.10 Serial Extended Mode Register 0 (SEMR0) ......................................................... 481 12.2.11 Module Stop Control Register B (MSTPCRB)..................................................... 486 Operation ........................................................................................................................... 487 12.3.1 Overview............................................................................................................... 487 12.3.2 Operation in Asynchronous Mode ........................................................................ 490 12.3.3 Multiprocessor Communication Function............................................................. 501 12.3.4 Operation in Clocked Synchronous Mode ............................................................ 509 SCI Interrupts..................................................................................................................... 518 Usage Notes ....................................................................................................................... 520 Section 13 D/A Converter .................................................................................531 13.1 Overview............................................................................................................................ 531 13.1.1 Features................................................................................................................. 531 13.1.2 Block Diagram...................................................................................................... 532 13.1.3 Pin Configuration.................................................................................................. 533 13.1.4 Register Configuration.......................................................................................... 533 13.2 Register Descriptions ......................................................................................................... 534 13.2.1 D/A Data Register 0 (DADR0)............................................................................. 534 13.2.2 D/A Control Register (DACR) ............................................................................. 534 13.2.3 Module Stop Control Register C (MSTPCRC)..................................................... 535 13.3 Operation ........................................................................................................................... 536 Section 14 RAM ................................................................................................539 14.1 Overview............................................................................................................................ 539 14.1.1 Block Diagram...................................................................................................... 539 14.1.2 Register Configuration.......................................................................................... 540 14.2 Register Descriptions ......................................................................................................... 540 14.2.1 System Control Register (SYSCR) ....................................................................... 540 14.3 Operation ........................................................................................................................... 541 Rev.4.00 Sep. 18, 2008 Page xl of lx REJ09B0189-0400 14.4 Usage Note......................................................................................................................... 541 Section 15 ROM ............................................................................................... 543 15.1 Overview............................................................................................................................ 543 15.1.1 Block Diagram ...................................................................................................... 543 15.1.2 Register Configuration.......................................................................................... 544 15.2 Register Descriptions ......................................................................................................... 544 15.2.1 Mode Control Register (MDCR) .......................................................................... 544 15.3 Operation............................................................................................................................ 545 15.4 Overview of Flash Memory ............................................................................................... 546 15.4.1 Features................................................................................................................. 546 15.4.2 Block Diagram ...................................................................................................... 547 15.4.3 Mode Transitions .................................................................................................. 548 15.4.4 On-Board Programming Modes............................................................................ 549 15.4.5 Flash Memory Emulation in RAM ....................................................................... 551 15.4.6 Differences between Boot Mode and User Program Mode................................... 552 15.4.7 Block Divisions..................................................................................................... 553 15.5 Pin Configuration............................................................................................................... 554 15.6 Register Configuration ....................................................................................................... 555 15.7 Register Descriptions ......................................................................................................... 556 15.7.1 Flash Memory Control Register 1 (FLMCR1)...................................................... 556 15.7.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 559 15.7.3 Erase Block Register 1 (EBR1)............................................................................. 560 15.7.4 Erase Block Register 2 (EBR2)............................................................................. 560 15.7.5 RAM Emulation Register (RAMER).................................................................... 561 15.7.6 Serial Control Register X (SCRX) ........................................................................ 563 15.8 On-Board Programming Modes ......................................................................................... 564 15.8.1 Boot Mode ............................................................................................................ 564 15.8.2 User Program Mode.............................................................................................. 569 15.9 Programming/Erasing Flash Memory ................................................................................ 571 15.9.1 Program Mode ...................................................................................................... 571 15.9.2 Program-Verify Mode........................................................................................... 572 15.9.3 Erase Mode ........................................................................................................... 574 15.9.4 Erase-Verify Mode................................................................................................ 574 15.10 Protection ........................................................................................................................... 576 15.10.1 Hardware Protection ............................................................................................. 576 15.10.2 Software Protection............................................................................................... 577 15.10.3 Error Protection..................................................................................................... 578 15.11 Flash Memory Emulation in RAM..................................................................................... 580 15.12 Interrupt Handling when Programming/Erasing Flash Memory........................................ 582 15.13 Flash Memory Programmer Mode ..................................................................................... 582 Rev.4.00 Sep. 18, 2008 Page xli of lx REJ09B0189-0400 15.13.1 Socket Adapter Pin Correspondence Diagram...................................................... 583 15.13.2 Programmer Mode Operation ............................................................................... 585 15.13.3 Memory Read Mode ............................................................................................. 586 15.13.4 Auto-Program Mode ............................................................................................. 590 15.13.5 Auto-Erase Mode.................................................................................................. 592 15.13.6 Status Read Mode ................................................................................................. 594 15.13.7 Status Polling ........................................................................................................ 595 15.13.8 Programmer Mode Transition Time ..................................................................... 596 15.13.9 Notes on Memory Programming........................................................................... 597 15.14 Flash Memory and Power-Down States............................................................................. 597 15.14.1 Note on Power-Down States ................................................................................. 598 15.15 Flash Memory Programming and Erasing Precautions...................................................... 598 15.16 Note on Switching from F-ZTAT Version to Masked ROM Version ............................... 604 Section 16 Clock Pulse Generator .....................................................................605 16.1 Overview............................................................................................................................ 605 16.1.1 Block Diagram...................................................................................................... 605 16.1.2 Register Configuration.......................................................................................... 606 16.2 Register Descriptions ......................................................................................................... 606 16.2.1 System Clock Control Register (SCKCR) ............................................................ 606 16.2.2 Low-Power Control Register (LPWRCR) ............................................................ 607 16.3 System Clock Oscillator..................................................................................................... 609 16.3.1 Connecting a Crystal Resonator............................................................................ 609 16.3.2 External Clock Input............................................................................................. 611 16.4 Duty Adjustment Circuit.................................................................................................... 615 16.5 Medium-Speed Clock Divider ........................................................................................... 615 16.6 Bus Master Clock Selection Circuit................................................................................... 615 16.7 Note on Crystal Resonator ................................................................................................. 615 Section 17 Power-Down Modes ........................................................................617 17.1 Overview............................................................................................................................ 617 17.1.1 Register Configuration.......................................................................................... 620 17.2 Register Descriptions ......................................................................................................... 620 17.2.1 Standby Control Register (SBYCR) ..................................................................... 620 17.2.2 System Clock Control Register (SCKCR) ............................................................ 622 17.2.3 Module Stop Control Register (MSTPCR) ........................................................... 623 17.3 Medium-Speed Mode......................................................................................................... 624 17.4 Sleep Mode ........................................................................................................................ 625 17.4.1 Sleep Mode ........................................................................................................... 625 17.4.2 Clearing Sleep Mode............................................................................................. 625 17.5 Module Stop Mode ............................................................................................................ 626 Rev.4.00 Sep. 18, 2008 Page xlii of lx REJ09B0189-0400 17.5.1 Module Stop Mode ............................................................................................... 626 17.5.2 Usage Notes .......................................................................................................... 628 17.6 Software Standby Mode..................................................................................................... 628 17.6.1 Software Standby Mode........................................................................................ 628 17.6.2 Clearing Software Standby Mode ......................................................................... 629 17.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode.... 629 17.6.4 Software Standby Mode Application Example..................................................... 630 17.6.5 Usage Notes .......................................................................................................... 631 17.7 Hardware Standby Mode.................................................................................................... 632 17.7.1 Hardware Standby Mode ...................................................................................... 632 17.7.2 Hardware Standby Mode Timing.......................................................................... 632 17.8 φ Clock Output Disabling Function ................................................................................... 633 Section 18 Electrical Characteristics ................................................................ 635 18.1 18.2 18.3 18.4 Absolute Maximum Ratings .............................................................................................. 635 Power Supply Voltage and Operating Frequency Range ................................................... 636 DC Characteristics ............................................................................................................. 637 AC Characteristics ............................................................................................................. 642 18.4.1 Clock Timing ........................................................................................................ 642 18.4.2 Control Signal Timing .......................................................................................... 644 18.4.3 Bus Timing ........................................................................................................... 646 18.4.4 Timing of On-Chip Supporting Modules.............................................................. 653 18.4.5 DMAC Timing...................................................................................................... 656 18.5 D/A Convervion Characteristics ........................................................................................ 657 18.6 Flash Memory Characteristics............................................................................................ 658 18.7 Usage Note......................................................................................................................... 659 Appendix A Instruction Set .............................................................................. 661 A.1 A.2 A.3 A.4 A.5 A.6 Instruction List ................................................................................................................... 661 Instruction Codes ............................................................................................................... 685 Operation Code Map.......................................................................................................... 699 Number of States Required for Instruction Execution ....................................................... 703 Bus States during Instruction Execution ............................................................................ 717 Condition Code Modification ............................................................................................ 731 Appendix B Internal I/O Register ..................................................................... 737 B.1 B.2 Addresses ........................................................................................................................... 737 Functions............................................................................................................................ 744 Appendix C I/O Port Block Diagrams .............................................................. 827 C.1 Port 1 Block Diagrams....................................................................................................... 827 Rev.4.00 Sep. 18, 2008 Page xliii of lx REJ09B0189-0400 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.11 C.12 Port 3 Block Diagrams....................................................................................................... 831 Port 4 Block Diagram ........................................................................................................ 835 Port 7 Block Diagrams....................................................................................................... 836 Port 9 Block Diagram ........................................................................................................ 841 Port A Block Diagrams ...................................................................................................... 842 Port B Block Diagram........................................................................................................ 846 Port C Block Diagram........................................................................................................ 847 Port D Block Diagram........................................................................................................ 848 Port E Block Diagram ........................................................................................................ 849 Port F Block Diagrams....................................................................................................... 850 Port G Block Diagrams ...................................................................................................... 856 Appendix D Pin States.......................................................................................861 D.1 Port States in Each Processing State .................................................................................. 861 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode ......................................................865 E.1 E.2 Timing of Transition to Hardware Standby Mode ............................................................. 865 Timing of Recovery from Hardware Standby Mode.......................................................... 865 Appendix F Product Code Lineup .....................................................................867 Appendix G Package Dimensions .....................................................................869 Rev.4.00 Sep. 18, 2008 Page xliv of lx REJ09B0189-0400 Figures Section 1 Overview Figure 1.1 H8S/2214 Group Internal Block Diagram................................................................... 5 Figure 1.2 H8S/2214 Group Pin Arrangement (TFP-100B, TFP-100BV, TFP-100G, TFP-100GV: Top View)................................. 6 Figure 1.3 H8S/2214 Group Pin Arrangement (BP-112, BP-112V, TBP-112A, TBP-112AV: Top View) ......................................... 7 Section 2 CPU Figure 2.1 CPU Operating Modes .............................................................................................. 20 Figure 2.2 Exception Vector Table (Normal Mode)................................................................... 21 Figure 2.3 Stack Structure in Normal Mode............................................................................... 22 Figure 2.4 Exception Vector Table (Advanced Mode)............................................................... 23 Figure 2.5 Stack Structure in Advanced Mode........................................................................... 24 Figure 2.6 Memory Map............................................................................................................. 25 Figure 2.7 CPU Registers ........................................................................................................... 26 Figure 2.8 Usage of General Registers ....................................................................................... 27 Figure 2.9 Stack .......................................................................................................................... 28 Figure 2.10 General Register Data Formats (1)............................................................................ 31 Figure 2.11 General Register Data Formats (2)............................................................................ 32 Figure 2.12 Memory Data Formats............................................................................................... 33 Figure 2.13 Instruction Formats (Examples) ................................................................................ 47 Figure 2.14 Branch Address Specification in Memory Indirect Mode ......................................... 52 Figure 2.15 Processing States ....................................................................................................... 56 Figure 2.16 State Transitions ........................................................................................................ 57 Figure 2.17 Stack Structure after Exception Handling (Examples) .............................................. 60 Figure 2.18 On-Chip Memory Access Cycle................................................................................ 62 Figure 2.19 Pin States during On-Chip Memory Access.............................................................. 63 Figure 2.20 On-Chip Supporting Module Access Cycle .............................................................. 64 Figure 2.21 Pin States during On-Chip Supporting Module Access............................................. 65 Figure 2.22 Flowchart for Access Methods for Registers that Include Write-Only Bits .............. 69 Section 3 MCU Operating Modes Figure 3.1 Memory Map in Each Operating Mode in the H8S/2214.......................................... 78 Section 4 Exception Handling Figure 4.1 Exception Sources ..................................................................................................... 80 Figure 4.2 Reset Sequence (Modes 2 and 3: Not available in the H8S/2214) ............................ 84 Rev.4.00 Sep. 18, 2008 Page xlv of lx REJ09B0189-0400 Figure 4.3 Figure 4.4 Figure 4.5 Figure 4.6 Figure 4.7 Reset Sequence (Mode 4).......................................................................................... 85 Interrupt Sources and Number of Interrupts.............................................................. 87 Stack Status after Exception Handling (Normal Modes: Not available in the H8S/2214)...................................................... 89 Stack Status after Exception Handling (Advanced Modes) ...................................... 89 Operation when SP Value Is Odd.............................................................................. 90 Section 5 Interrupt Controller Figure 5.1 Block Diagram of Interrupt Controller...................................................................... 92 Figure 5.2 Block Diagram of Interrupts IRQn.......................................................................... 100 Figure 5.3 Timing of Setting IRQnF ........................................................................................ 100 Figure 5.4 Block Diagram of Interrupt Control Operation ....................................................... 105 Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0.. 108 Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2.. 110 Figure 5.7 Interrupt Exception Handling.................................................................................. 111 Figure 5.8 Contention between Interrupt Generation and Disabling ........................................ 114 Figure 5.9 Interrupt Control for DTC and DMAC ................................................................... 116 Section 6 Bus Controller Figure 6.1 Block Diagram of Bus Controller ........................................................................... 120 Figure 6.2 Overview of Area Divisions.................................................................................... 134 Figure 6.3 CSn Signal Output Timing (n = 0 to 7) ................................................................... 138 Figure 6.4 Access Sizes and Data Alignment Control (8-Bit Access Space) ........................... 139 Figure 6.5 Access Sizes and Data Alignment Control (16-Bit Access Space) ......................... 140 Figure 6.6 Bus Timing for 8-Bit 2-State Access Space ............................................................ 142 Figure 6.7 Bus Timing for 8-Bit 3-State Access Space ............................................................ 143 Figure 6.8 Bus Timing for 16-Bit 2-State Access Space (Even Address Byte Access)............ 144 Figure 6.9 Bus Timing for 16-Bit 2-State Access Space (Odd Address Byte Access) ............. 145 Figure 6.10 Bus Timing for 16-Bit 2-State Access Space (Word Access) ................................. 146 Figure 6.11 Bus Timing for 16-Bit 3-State Access Space (Even Address Byte Access)............ 147 Figure 6.12 Bus Timing for 16-Bit 3-State Access Space (Odd Address Byte Access) ............. 148 Figure 6.13 Bus Timing for 16-Bit 3-State Access Space (Word Access) ................................. 149 Figure 6.14 Example of Wait State Insertion Timing................................................................. 151 Figure 6.15 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1).................. 153 Figure 6.16 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0).................. 154 Figure 6.17 Example of Idle Cycle Operation (1) ...................................................................... 155 Figure 6.18 Example of Idle Cycle Operation (2) ...................................................................... 156 Figure 6.19 Relationship between Chip Select (CS) and Read (RD) ......................................... 157 Figure 6.20 Bus-Released State Transition Timing.................................................................... 161 Figure 6.21 Multichip Block Diagram........................................................................................ 165 Figure 6.22 Timing of External Module Area Access by DTC .................................................. 171 Rev.4.00 Sep. 18, 2008 Page xlvi of lx REJ09B0189-0400 Figure 6.23 On-Chip ROM Valid Extended Mode (Mode 6) Address Map............................... 172 Section 7 DMA Controller Figure 7.1 Block Diagram of DMAC ....................................................................................... 174 Figure 7.2 Areas for Register Re-Setting by DTC (Example: Channel 0A)............................. 204 Figure 7.3 Operation in Sequential Mode................................................................................. 212 Figure 7.4 Example of Sequential Mode Setting Procedure ..................................................... 213 Figure 7.5 Operation in Idle Mode ........................................................................................... 215 Figure 7.6 Example of Idle Mode Setting Procedure................................................................ 216 Figure 7.7 Operation in Repeat mode....................................................................................... 219 Figure 7.8 Example of Repeat Mode Setting Procedure........................................................... 220 Figure 7.9 Operation in Normal Mode ..................................................................................... 222 Figure 7.10 Example of Normal Mode Setting Procedure.......................................................... 223 Figure 7.11 Operation in Block Transfer Mode (BLKDIR = 0) ................................................. 225 Figure 7.12 Operation in Block Transfer Mode (BLKDIR = 1) ................................................. 226 Figure 7.13 Operation Flow in Block Transfer Mode ................................................................ 228 Figure 7.14 Example of Block Transfer Mode Setting Procedure.............................................. 229 Figure 7.15 Example of DMA Transfer Bus Timing.................................................................. 232 Figure 7.16 Example of Short Address Mode Transfer .............................................................. 233 Figure 7.17 Example of Full Address Mode (Cycle Steal) Transfer .......................................... 234 Figure 7.18 Example of Full Address Mode (Burst Mode) Transfer.......................................... 235 Figure 7.19 Example of Full Address Mode (Block Transfer Mode) Transfer .......................... 236 Figure 7.20 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer................. 237 Figure 7.21 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer..... 238 Figure 7.22 Example of DREQ Level Activated Normal Mode Transfer .................................. 239 Figure 7.23 Example of DREQ Level Activated Block Transfer Mode Transfer ...................... 240 Figure 7.24 Example of Multi-Channel Transfer ....................................................................... 241 Figure 7.25 Example of Procedure for Continuing Transfer on Channel Interrupted by NMI Interrupt ..................................................................................................... 243 Figure 7.26 Example of Procedure for Forcibly Terminating DMAC Operation....................... 244 Figure 7.27 Example of Procedure for Clearing Full Address Mode ......................................... 245 Figure 7.28 Block Diagram of Transfer End/Transfer Break Interrupt ...................................... 246 Figure 7.29 DMAC Register Update Timing ............................................................................. 247 Figure 7.30 Contention between DMAC Register Update and CPU Read................................. 248 Section 8 Data Transfer Controller (DTC) Figure 8.1 Block Diagram of DTC ........................................................................................... 252 Figure 8.2 Flowchart of DTC Operation................................................................................... 262 Figure 8.3 Block Diagram of DTC Activation Source Control ................................................ 265 Figure 8.4 Correspondence between DTC Vector Address and Register Information ............. 268 Figure 8.5 Location of Register Information in Address Space................................................ 268 Rev.4.00 Sep. 18, 2008 Page xlvii of lx REJ09B0189-0400 Figure 8.6 Figure 8.7 Figure 8.8 Figure 8.9 Figure 8.10 Figure 8.11 Memory Mapping in Normal Mode ........................................................................ 269 Memory Mapping in Repeat Mode ......................................................................... 270 Memory Mapping in Block Transfer Mode ............................................................ 272 Chain Transfer Memory Map.................................................................................. 273 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ................... 274 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2)...................................... 274 Figure 8.12 DTC Operation Timing (Example of Chain Transfer) ............................................ 275 Section 9 I/O Ports Figure 9.1 Port 1 Pin Functions ................................................................................................ 285 Figure 9.2 Port 3 Pin Functions ................................................................................................ 296 Figure 9.3 Port 4 Pin Functions ................................................................................................ 304 Figure 9.4 Port 7 Pin Functions ................................................................................................ 308 Figure 9.5 Port 9 Pin Functions ................................................................................................ 314 Figure 9.6 Port A Pin Functions ............................................................................................... 315 Figure 9.7 Port B Pin Functions ............................................................................................... 322 Figure 9.8 Port C Pin Functions ............................................................................................... 330 Figure 9.9 Port C Pin Functions (Modes 4 and 5) .................................................................... 333 Figure 9.10 Port C Pin Functions (Mode 6)................................................................................ 334 Figure 9.11 Port C Pin Functions (Mode 7)................................................................................ 335 Figure 9.12 Port D Pin Functions ............................................................................................... 337 Figure 9.13 Port D Pin Functions (Modes 4 to 6)....................................................................... 340 Figure 9.14 Port D Pin Functions (Mode 7) ............................................................................... 341 Figure 9.15 Port E Pin Functions................................................................................................ 342 Figure 9.16 Port E Pin Functions (Modes 4 to 6) ....................................................................... 345 Figure 9.17 Port E Pin Functions (Mode 7)................................................................................ 346 Figure 9.18 Port F Pin Functions................................................................................................ 348 Figure 9.19 Port G Pin Functions ............................................................................................... 353 Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.1 Block Diagram of TPU ........................................................................................... 363 Figure 10.2 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)] ...................... 389 Figure 10.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)].................. 390 Figure 10.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)] ............. 390 Figure 10.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)] ....... 390 Figure 10.6 Example of Counter Operation Setting Procedure .................................................. 392 Figure 10.7 Free-Running Counter Operation ............................................................................ 393 Figure 10.8 Periodic Counter Operation..................................................................................... 394 Figure 10.9 Example Of Setting Procedure For Waveform Output By Compare Match ........... 395 Figure 10.10 Example of 0 Output/1 Output Operation ............................................................... 396 Rev.4.00 Sep. 18, 2008 Page xlviii of lx REJ09B0189-0400 Figure 10.11 Example of Toggle Output Operation ..................................................................... 396 Figure 10.12 Example of Input Capture Operation Setting Procedure ......................................... 397 Figure 10.13 Example of Input Capture Operation....................................................................... 398 Figure 10.14 Example of Synchronous Operation Setting Procedure .......................................... 399 Figure 10.15 Example of Synchronous Operation........................................................................ 400 Figure 10.16 Compare Match Buffer Operation........................................................................... 401 Figure 10.17 Input Capture Buffer Operation............................................................................... 402 Figure 10.18 Example of Buffer Operation Setting Procedure..................................................... 402 Figure 10.19 Example of Buffer Operation (1) ............................................................................ 403 Figure 10.20 Example of Buffer Operation (2) ............................................................................ 404 Figure 10.21 Example of PWM Mode Setting Procedure ............................................................ 407 Figure 10.22 Example of PWM Mode Operation (1) ................................................................... 408 Figure 10.23 Example of PWM Mode Operation (2) ................................................................... 409 Figure 10.24 Example of PWM Mode Operation (3) ................................................................... 410 Figure 10.25 Example of Phase Counting Mode Setting Procedure............................................. 411 Figure 10.26 Example of Phase Counting Mode 1 Operation ...................................................... 412 Figure 10.27 Example of Phase Counting Mode 2 Operation ...................................................... 413 Figure 10.28 Example of Phase Counting Mode 3 Operation ...................................................... 414 Figure 10.29 Example of Phase Counting Mode 4 Operation ...................................................... 415 Figure 10.30 Count Timing in Internal Clock Operation.............................................................. 418 Figure 10.31 Count Timing in External Clock Operation ............................................................ 418 Figure 10.32 Output Compare Output Timing ............................................................................. 419 Figure 10.33 Input Capture Input Signal Timing.......................................................................... 420 Figure 10.34 Counter Clear Timing (Compare Match) ................................................................ 421 Figure 10.35 Counter Clear Timing (Input Capture) .................................................................... 421 Figure 10.36 Buffer Operation Timing (Compare Match) ........................................................... 422 Figure 10.37 Buffer Operation Timing (Input Capture) ............................................................... 422 Figure 10.38 TGI Interrupt Timing (Compare Match) ................................................................. 423 Figure 10.39 TGI Interrupt Timing (Input Capture) ..................................................................... 424 Figure 10.40 TCIV Interrupt Setting Timing................................................................................ 425 Figure 10.41 TCIU Interrupt Setting Timing................................................................................ 425 Figure 10.42 Timing for Status Flag Clearing by CPU ................................................................ 426 Figure 10.43 Timing for Status Flag Clearing by DTC/DMAC Activation ................................. 426 Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode .................. 427 Figure 10.45 Contention between TCNT Write and Clear Operations......................................... 428 Figure 10.46 Contention between TCNT Write and Increment Operations ................................. 429 Figure 10.47 Contention between TGR Write and Compare Match............................................. 430 Figure 10.48 Contention between Buffer Register Write and Compare Match............................ 431 Figure 10.49 Contention between TGR Read and Input Capture ................................................. 432 Figure 10.50 Contention between TGR Write and Input Capture ................................................ 433 Figure 10.51 Contention between Buffer Register Write and Input Capture................................ 434 Rev.4.00 Sep. 18, 2008 Page xlix of lx REJ09B0189-0400 Figure 10.52 Contention between Overflow and Counter Clearing ............................................. 435 Figure 10.53 Contention between TCNT Write and Overflow .................................................... 436 Section 11 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Figure 11.6 Figure 11.7 Figure 11.8 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Watchdog Timer (WDT) Block Diagram of WDT.......................................................................................... 438 Format of Data Written to TCNT and TCSR (Example of WDT0) ........................ 444 Format of Data Written to RSTCSR (Example of WDT0) ..................................... 445 Operation in Watchdog Timer Mode ...................................................................... 446 Operation in Interval Timer Mode .......................................................................... 447 Timing of OVF Setting ........................................................................................... 448 Timing of WOVF Setting........................................................................................ 449 Contention between TCNT Write and Increment.................................................... 450 Serial Communication Interface (SCI) Block Diagram of SCI0........................................................................................... 455 Block Diagram of SCI1 and SCI2 ........................................................................... 456 Examples of Base Clock when Average Transfer Rate Is Selected (1)................... 484 Examples of Base Clock when Average Transfer Rate Is Selected (2)................... 485 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits).................................................. 490 Figure 12.6 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode). 492 Figure 12.7 Sample SCI Initialization Flowchart ....................................................................... 493 Figure 12.8 Sample Serial Transmission Flowchart ................................................................... 494 Figure 12.9 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 496 Figure 12.10 Sample Serial Reception Data Flowchart (1) .......................................................... 497 Figure 12.11 Sample Serial Reception Data Flowchart (2) .......................................................... 498 Figure 12.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 500 Figure 12.13 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) ............................................ 502 Figure 12.14 Sample Multiprocessor Serial Transmission Flowchart .......................................... 503 Figure 12.15 Example of SCI Operation in Transmission (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)................................ 505 Figure 12.16 Sample Multiprocessor Serial Reception Flowchart (1).......................................... 506 Figure 12.17 Sample Multiprocessor Serial Reception Flowchart (2).......................................... 507 Figure 12.18 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)................................ 508 Figure 12.19 Data Format in Synchronous Communication ........................................................ 509 Figure 12.20 Sample SCI Initialization Flowchart ....................................................................... 511 Figure 12.21 Sample Serial Transmission Flowchart ................................................................... 512 Rev.4.00 Sep. 18, 2008 Page l of lx REJ09B0189-0400 Figure 12.22 Example of SCI Operation in Transmission............................................................ 514 Figure 12.23 Sample Serial Reception Flowchart ........................................................................ 515 Figure 12.24 Example of SCI Operation in Reception ................................................................. 516 Figure 12.25 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ........ 517 Figure 12.26 Receive Data Sampling Timing in Asynchronous Mode ........................................ 522 Figure 12.27 Example of Clocked Synchronous Transmission by DTC ...................................... 524 Figure 12.28 Sample Flowchart for Mode Transition during Transmission................................. 525 Figure 12.29 Asynchronous Transmission Using Internal Clock ................................................. 526 Figure 12.30 Synchronous Transmission Using Internal Clock ................................................... 526 Figure 12.31 Sample Flowchart for Mode Transition during Reception ...................................... 527 Figure 12.32 Operation when Switching from SCK Pin Function to Port Pin Function .............. 528 Figure 12.33 Operation when Switching from SCK Pin Function to Port Pin Function (Example of Preventing Low-Level Output)........................................................... 529 Section 13 D/A Converter Figure 13.1 Block Diagram of D/A Converter ........................................................................... 532 Figure 13.2 Example of D/A Converter Operation..................................................................... 537 Section 14 RAM Figure 14.1 Block Diagram of RAM .......................................................................................... 539 Section 15 ROM Figure 15.1 Block Diagram of ROM .......................................................................................... 543 Figure 15.2 Block Diagram of Flash Memory............................................................................ 547 Figure 15.3 Flash Memory State Transitions.............................................................................. 548 Figure 15.4 Boot Mode............................................................................................................... 549 Figure 15.5 User Program Mode ................................................................................................ 550 Figure 15.6 Reading Overlap RAM Data in User Mode or User Program Mode....................... 551 Figure 15.7 Writing Overlap RAM Data in User Program Mode............................................... 552 Figure 15.8 Flash Memory Blocks ............................................................................................. 553 Figure 15.9 System Configuration in Boot Mode....................................................................... 565 Figure 15.10 Boot Mode Execution Procedure............................................................................. 566 Figure 15.11 Automatic SCI Bit Rate Adjustment ....................................................................... 567 Figure 15.12 RAM Areas in Boot Mode ...................................................................................... 568 Figure 15.13 User Program Mode Execution Procedure .............................................................. 570 Figure 15.14 Program/Program-Verify Flowchart........................................................................ 573 Figure 15.15 Erase/Erase-Verify Flowchart ................................................................................. 575 Figure 15.16 Flash Memory State Transitions.............................................................................. 579 Figure 15.17 Flowchart for Flash Memory Emulation in RAM ................................................... 580 Figure 15.18 Example of RAM Overlap Operation...................................................................... 581 Figure 15.19 On-Chip ROM Memory Map.................................................................................. 583 Rev.4.00 Sep. 18, 2008 Page li of lx REJ09B0189-0400 Figure 15.20 Socket Adapter Pin Correspondence Diagram ........................................................ 584 Figure 15.21 Timing Waveforms for Memory Read after Memory Write ................................... 587 Figure 15.22 Timing Waveforms in Transition from Memory Read Mode to Another Mode..... 588 Figure 15.23 CE and OE Enable State Read Timing Waveforms ................................................ 589 Figure 15.24 CE and OE Clock System Read Timing Waveforms .............................................. 589 Figure 15.25 Auto-Program Mode Timing Waveforms ............................................................... 591 Figure 15.26 Auto-Erase Mode Timing Waveforms .................................................................... 593 Figure 15.27 Status Read Mode Timing Waveforms ................................................................... 594 Figure 15.28 Oscillation Stabilization Time, Boot Program Transfer Time, and Power-Down Sequence..................................................................................... 596 Figure 15.29 Power-On/Off Timing (Boot Mode) ....................................................................... 601 Figure 15.30 Power-On/Off Timing (User Program Mode) ......................................................... 602 Figure 15.31 Mode Transition Timing (Example: Boot Mode → User Mode ↔ User Program Mode).............................. 603 Section 16 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 Figure 16.5 Figure 16.6 Figure 16.7 Figure 16.8 Section 17 Figure 17.1 Figure 17.2 Figure 17.3 Figure 17.4 Section 18 Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5 Figure 18.6 Figure 18.7 Figure 18.8 Figure 18.9 Clock Pulse Generator Block Diagram of Clock Pulse Generator ............................................................... 605 Connection of Crystal Resonator (Example)........................................................... 609 Crystal Resonator Equivalent Circuit...................................................................... 609 Example of Incorrect Board Design ........................................................................ 610 External Clock Input (Examples) ............................................................................ 611 External Clock Input Timing................................................................................... 612 Example of External Clock Switching Circuit ........................................................ 613 Example of External Clock Switchover Timing...................................................... 614 Power-Down Modes Mode Transitions..................................................................................................... 619 Medium-Speed Mode Transition and Clearance Timing ........................................ 625 Software Standby Mode Application Example ....................................................... 631 Hardware Standby Mode Timing (Example) .......................................................... 633 Electrical Characteristics Power Supply Voltage and Operating Ranges ........................................................ 636 Output Load Circuit ................................................................................................ 642 System Clock Timing.............................................................................................. 643 Oscillator Settling Timing ....................................................................................... 643 Reset Input Timing.................................................................................................. 644 Interrupt Input Timing............................................................................................. 645 Basic Bus Timing/Two-State Access ...................................................................... 648 Basic Bus Timing/Three-State Access .................................................................... 649 Basic Bus Timing/Three-State Access with One Wait State................................... 650 Rev.4.00 Sep. 18, 2008 Page lii of lx REJ09B0189-0400 Figure 18.10 Burst ROM Access Timing/Two-State Access ....................................................... 651 Figure 18.11 External Bus Release Timing .................................................................................. 652 Figure 18.12 I/O Port Input/Output Timing.................................................................................. 654 Figure 18.13 TPU Input/Output Timing ....................................................................................... 654 Figure 18.14 TPU Clock Input Timing......................................................................................... 654 Figure 18.15 SCK Clock Input Timing ........................................................................................ 655 Figure 18.16 SCI Input/Output Timing/Clock Synchronous Mode.............................................. 655 Figure 18.17 DMAC TEND Output Timing................................................................................. 656 Figure 18.18 DMAC DREQ Output Timing ................................................................................ 656 Appendix A Instruction Set Figure A.1 Address Bus, RD, HWR, and LWR Timing (8-Bit Bus, Three-State Access, No Wait States) .................................................... 718 Appendix C I/O Port Block Diagrams Figure C.1 Port 1 Block Diagram (Pins P10 and P11) .............................................................. 827 Figure C.2 Port 1 Block Diagram (Pins P12 and P13) .............................................................. 828 Figure C.3 Port 1 Block Diagram (Pins P14 and P16) .............................................................. 829 Figure C.4 Port 1 Block Diagram (Pins P15 and P17) .............................................................. 830 Figure C.5 Port 3 Block Diagram (Pins P30 and P33) .............................................................. 831 Figure C.6 Port 3 Block Diagram (Pins P31 and P34) .............................................................. 832 Figure C.7 Port 3 Block Diagram (Pins P32 and P35) .............................................................. 833 Figure C.8 Port 3 Block Diagram (Pin P36).............................................................................. 834 Figure C.9 Port 4 Block Diagram (Pins P40 to P44, P46, and P47).......................................... 835 Figure C.10 Port 4 Block Diagram (Pin P45).............................................................................. 835 Figure C.11 Port 7 Block Diagram (Pins P70 and P71) .............................................................. 836 Figure C.12 Port 7 Block Diagram (Pins P72 and P73) .............................................................. 837 Figure C.13 Port 7 Block Diagram (Pin P74).............................................................................. 838 Figure C.14 Port 7 Block Diagram (Pins P75 and P76) .............................................................. 839 Figure C.15 Port 7 Block Diagram (Pin P77).............................................................................. 840 Figure C.16 Port 9 Block Diagram (Pin P96).............................................................................. 841 Figure C.17 Port A Block Diagram (Pin PA0) ............................................................................ 842 Figure C.18 Port A Block Diagram (Pin PA1) ............................................................................ 843 Figure C.19 Port A Block Diagram (Pin PA2) ............................................................................ 844 Figure C.20 Port A Block Diagram (Pin PA3) ............................................................................ 845 Figure C.21 Port B Block Diagram (Pins PB0 to PB7) ............................................................... 846 Figure C.22 Port C Block Diagram (Pins PC0 to PC7) ............................................................... 847 Figure C.23 Port D Block Diagram (Pins PD0 to PD7) .............................................................. 848 Figure C.24 Port E Block Diagram (Pins PE0 to PE7)................................................................ 849 Figure C.25 Port F Block Diagram (Pin PF0) ............................................................................. 850 Figure C.26 Port F Block Diagram (Pin PF1) ............................................................................. 851 Rev.4.00 Sep. 18, 2008 Page liii of lx REJ09B0189-0400 Figure C.27 Figure C.28 Figure C.29 Figure C.30 Figure C.31 Figure C.32 Figure C.33 Figure C.34 Port F Block Diagram (Pin PF2) ............................................................................. 852 Port F Block Diagram (Pin PF3) ............................................................................. 853 Port F Block Diagram (Pins PF4 to PF6) ................................................................ 854 Port F Block Diagram (Pin PF7) ............................................................................. 855 Port G Block Diagram (Pin PG0)............................................................................ 856 Port G Block Diagram (Pin PG1)............................................................................ 857 Port G Block Diagram (Pins PG2 and PG3) ........................................................... 858 Port G Block Diagram (Pin PG4)............................................................................ 859 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Figure E.1 Timing of Transition to Hardware Standby Mode .................................................. 865 Figure E.2 Timing of Recovery from Hardware Standby Mode............................................... 865 Appendix G Package Dimensions Figure G.1 TFP-100B, TFP-100BV Package Dimensions ........................................................ 869 Figure G.2 TFP-100G, TFP-100GA Package Dimensions........................................................ 870 Figure G.3 TBP-112A, TBP-112AV Package Dimensions....................................................... 871 Figure G.4 BP-112, BP-112V Package Dimensions ................................................................. 872 Rev.4.00 Sep. 18, 2008 Page liv of lx REJ09B0189-0400 Tables Section 1 Overview Table 1.1 Overview ..................................................................................................................... 2 Table 1.2 Pin Functions in Each Operating Mode....................................................................... 8 Table 1.3 Pin Functions............................................................................................................. 12 Section 2 CPU Table 2.1 Instruction Classification........................................................................................... 34 Table 2.2 Combinations of Instructions and Addressing Modes............................................... 35 Table 2.3 Instructions Classified by Function ........................................................................... 38 Table 2.4 Addressing Modes..................................................................................................... 49 Table 2.5 Absolute Address Access Ranges ............................................................................. 50 Table 2.6 Effective Address Calculation................................................................................... 53 Table 2.7 Exception Handling Types and Priority .................................................................... 58 Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Selection............................................................................... 71 Table 3.2 MCU Registers .......................................................................................................... 72 Table 3.3 Relationship between RES and MRES pin Values and Type of Reset...................... 74 Table 3.4 Pin Functions in Each Mode...................................................................................... 77 Section 4 Exception Handling Table 4.1 Exception Handling Types and Priority .................................................................... 79 Table 4.2 Exception Vector Table............................................................................................. 81 Table 4.3 Reset Types ............................................................................................................... 82 Table 4.4 Status of CCR and EXR after Trace Exception Handling ......................................... 86 Table 4.5 Status of CCR and EXR after Trap Instruction Exception Handling ........................ 88 Section 5 Interrupt Controller Interrupt Controller Pins............................................................................................ 93 Table 5.1 Table 5.2 Interrupt Controller Registers.................................................................................... 93 Table 5.3 Correspondence between Interrupt Sources and IPR Settings................................... 95 Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities ................................. 102 Table 5.5 Interrupt Control Modes.......................................................................................... 104 Table 5.6 Interrupts Selected in Each Interrupt Control Mode (1) .......................................... 105 Table 5.7 Interrupts Selected in Each Interrupt Control Mode (2) .......................................... 106 Table 5.8 Operations and Control Signal Functions in Each Interrupt Control Mode ............ 106 Table 5.9 Interrupt Response Times........................................................................................ 112 Rev.4.00 Sep. 18, 2008 Page lv of lx REJ09B0189-0400 Table 5.10 Table 5.11 Number of States in Interrupt Handling Routine Execution Statuses ..................... 113 Interrupt Source Selection and Clearing Control .................................................... 118 Section 6 Bus Controller Bus Controller Pins ................................................................................................. 121 Table 6.1 Table 6.2 Bus Controller Registers ......................................................................................... 122 Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) ......................................... 136 Table 6.4 Data Buses Used and Valid Strobes ........................................................................ 141 Table 6.5 Pin States in Idle Cycle ........................................................................................... 158 Table 6.6 Pin States in Bus Released State ............................................................................. 160 Table 6.7 External Module Expansion Function Pins ............................................................. 165 Table 6.8 Bus Controller Registers ......................................................................................... 166 Section 7 DMA Controller Table 7.1 Overview of DMAC Functions (Short Address Mode)........................................... 175 Table 7.2 Overview of DMAC Functions (Full Address Mode)............................................. 176 Table 7.3 DMAC Pins ............................................................................................................. 177 Table 7.4 DMAC Registers ..................................................................................................... 178 Table 7.5 Short Address Mode and Full Address Mode (For 1 Channel: Example of Channel 0).................................................................. 179 Table 7.6 DMAC Transfer Modes .......................................................................................... 209 Table 7.7 Register Functions in Sequential Mode................................................................... 211 Table 7.8 Register Functions in Idle Mode ............................................................................. 214 Table 7.9 Register Functions in Repeat Mode ........................................................................ 217 Table 7.10 Register Functions in Normal Mode ....................................................................... 221 Table 7.11 Register Functions in Block Transfer Mode ........................................................... 224 Table 7.12 DMAC Activation Sources ..................................................................................... 230 Table 7.13 DMAC Channel Priority Order ............................................................................... 241 Table 7.14 Interrupt Source Priority Order ............................................................................... 246 Section 8 Data Transfer Controller (DTC) DTC Registers ......................................................................................................... 253 Table 8.1 Table 8.2 DTC Functions ........................................................................................................ 263 Table 8.3 Activation Source and DTCER Clearance .............................................................. 264 Table 8.4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs ................. 266 Table 8.5 Register Information in Normal Mode .................................................................... 269 Table 8.6 Register Information in Repeat Mode ..................................................................... 270 Table 8.7 Register Information in Block Transfer Mode ........................................................ 271 Table 8.8 DTC Execution Statuses.......................................................................................... 275 Table 8.9 Number of States Required for Each Execution Status ........................................... 276 Rev.4.00 Sep. 18, 2008 Page lvi of lx REJ09B0189-0400 Section 9 I/O Ports H8S/2214 Group Port Functions ............................................................................. 282 Table 9.1 Table 9.2 Port 1 Registers ....................................................................................................... 286 Table 9.3 Port 1 Pin Functions ................................................................................................ 288 Table 9.4 Port 3 Registers ....................................................................................................... 297 Table 9.5 Port 3 Pin Functions ................................................................................................ 302 Table 9.6 Port 4 Registers ....................................................................................................... 304 Table 9.7 Port 7 Registers ....................................................................................................... 309 Table 9.8 Port 7 Pin Functions ................................................................................................ 312 Table 9.9 Port 9 Registers ....................................................................................................... 314 Table 9.10 Port A Registers ...................................................................................................... 316 Table 9.11 Port A Pin Functions ............................................................................................... 319 Table 9.12 MOS Input Pull-Up States (Port A)......................................................................... 321 Table 9.13 Port B Registers....................................................................................................... 323 Table 9.14 Port B Pin Functions................................................................................................ 325 Table 9.15 MOS Input Pull-Up States (Port B)......................................................................... 329 Table 9.16 Port C Registers....................................................................................................... 331 Table 9.17 MOS Input Pull-Up States (Port C)......................................................................... 336 Table 9.18 Port D Registers ...................................................................................................... 338 Table 9.19 MOS Input Pull-Up States (Port D)......................................................................... 341 Table 9.20 Port E Registers ....................................................................................................... 343 Table 9.21 MOS Input Pull-Up States (Port E) ......................................................................... 347 Table 9.22 Port F Registers ....................................................................................................... 349 Table 9.23 Port F Pin Functions ................................................................................................ 351 Table 9.24 Port G Registers ...................................................................................................... 354 Table 9.25 Port G Pin Functions ............................................................................................... 356 Table 9.26 Handling of Unused Input Pins ............................................................................... 358 Section 10 Table 10.1 Table 10.2 Table 10.3 Table 10.4 Table 10.5 Table 10.6 Table 10.7 Table 10.8 Table 10.9 Table 10.10 Table 10.11 16-Bit Timer Pulse Unit (TPU) TPU Functions......................................................................................................... 361 TPU Pins ................................................................................................................. 364 TPU Registers ......................................................................................................... 365 TPU Clock Sources ................................................................................................. 368 Register Combinations in Buffer Operation............................................................ 401 PWM Output Registers and Output Pins................................................................. 406 Phase Counting Mode Clock Input Pins.................................................................. 411 Up/Down-Count Conditions in Phase Counting Mode 1 ........................................ 412 Up/Down-Count Conditions in Phase Counting Mode 2 ........................................ 413 Up/Down-Count Conditions in Phase Counting Mode 3 ........................................ 414 Up/Down-Count Conditions in Phase Counting Mode 4 ........................................ 415 Rev.4.00 Sep. 18, 2008 Page lvii of lx REJ09B0189-0400 Table 10.12 Interrupt Sources and DMA Controller (DMAC) and Data Transfer (DTC) Activation................................................................................................................ 416 Section 11 Watchdog Timer (WDT) Table 11.1 WDT Registers........................................................................................................ 439 Section 12 Serial Communication Interface (SCI) Table 12.1 SCI Pins................................................................................................................... 457 Table 12.2 SCI Registers........................................................................................................... 458 Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) ................................... 473 Table 12.4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ....................... 476 Table 12.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode, when ABCS = 0). 478 Table 12.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode, when ABCS = 0)................................................................ 479 Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)....... 479 Table 12.8 SMR Settings and Serial Transfer Format Selection............................................... 488 Table 12.9 SMR and SCR Settings and SCI Clock Source Selection ....................................... 488 Table 12.10 SMR0, SCR0, SEMR0 Settings and SCI Clock Source Selection (SCI0 Only) ..... 489 Table 12.11 Serial Transfer Formats (Asynchronous Mode) ...................................................... 491 Table 12.12 Receive Errors and Conditions for Occurrence....................................................... 500 Table 12.13 SCI Interrupt Sources .............................................................................................. 519 Table 12.14 State of SSR Status Flags and Transfer of Receive Data ....................................... 521 Section 13 D/A Converter Table 13.1 Pin Configuration .................................................................................................... 533 Table 13.2 D/A Converter Registers ......................................................................................... 533 Section 14 RAM Table 14.1 RAM Register ......................................................................................................... 540 Section 15 ROM Table 15.1 ROM Register ......................................................................................................... 544 Table 15.2 Operating Modes and ROM Area (F-ZTAT Version and Masked ROM Version) 545 Table 15.3 Differences between Boot Mode and User Program Mode..................................... 552 Table 15.4 Pin Configuration .................................................................................................... 554 Table 15.5 Register Configuration ............................................................................................ 555 Table 15.6 Flash Memory Erase Blocks.................................................................................... 561 Table 15.7 Flash Memory Area Divisions ................................................................................ 562 Table 15.8 Setting On-Board Programming Modes.................................................................. 564 Table 15.9 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is Possible ................................................................................................................... 567 Rev.4.00 Sep. 18, 2008 Page lviii of lx REJ09B0189-0400 Table 15.10 Table 15.11 Table 15.12 Table 15.13 Table 15.14 Table 15.15 Table 15.16 Table 15.17 Table 15.18 Table 15.19 Table 15.20 Table 15.21 Table 15.22 Table 15.23 Table 15.24 Table 15.25 Hardware Protection................................................................................................ 576 Software Protection ................................................................................................. 577 Programmer Mode Pin Settings............................................................................... 583 Settings for Various Operating Modes In Programmer Mode................................. 585 Programmer Mode Commands................................................................................ 586 AC Characteristics in Transition to Memory Read Mode ....................................... 586 AC Characteristics in Transition from Memory Read Mode to Another Mode ...... 587 AC Characteristics in Memory Read Mode ............................................................ 588 AC Characteristics in Auto-Program Mode ............................................................ 591 AC Characteristics in Auto-Erase Mode ................................................................. 592 AC Characteristics in Status Read Mode ................................................................ 594 Status Read Mode Return Commands..................................................................... 595 Status Polling Output Truth Table........................................................................... 595 Stipulated Transition Times to Command Wait State ............................................. 596 Flash Memory Operating States .............................................................................. 597 Registers Present in F-ZTAT Version but Absent in Masked ROM Version ......... 604 Section 16 Clock Pulse Generator Table 16.1 Clock Pulse Generator Register............................................................................... 606 Table 16.2 Damping Resistance Value...................................................................................... 609 Table 16.3 Crystal Resonator Parameters.................................................................................. 610 Table 16.4 External Clock Input Conditions ............................................................................. 612 Table 16.5 External Clock Input Conditions when the Duty Adjustment Circuit Is not Used .. 612 Section 17 Power-Down Modes Table 17.1 LSI Internal States in Each Mode............................................................................ 618 Table 17.2 Power-Down Mode Registers.................................................................................. 620 Table 17.3 MSTP Bits and Corresponding On-Chip Supporting Modules ............................... 627 Table 17.4 Oscillation Stabilization Time Settings ................................................................... 630 Table 17.5 φ Pin State in Each Processing Mode ...................................................................... 633 Section 18 Electrical Characteristics Table 18.1 Absolute Maximum Ratings.................................................................................... 635 Table 18.2 DC Characteristics (1) ............................................................................................. 637 Table 18.3 DC Characteristics (2) ............................................................................................. 639 Table 18.4 DC Characteristics (3) ............................................................................................. 640 Table 18.5 Permissible Output Currents.................................................................................... 641 Table 18.6 Clock Timing........................................................................................................... 642 Table 18.7 Control Signal Timing............................................................................................. 644 Table 18.8 Bus Timing.............................................................................................................. 646 Table 18.9 Timing of On-Chip Supporting Modules ................................................................ 653 Rev.4.00 Sep. 18, 2008 Page lix of lx REJ09B0189-0400 Table 18.10 DMAC Timing ........................................................................................................ 656 Table 18.11 D/A Conversion Characteristics .............................................................................. 657 Table 18.12 Flash Memory Characteristics................................................................................. 658 Appendix A Instruction Set Table A.1 Data Transfer Instructions ....................................................................................... 663 Table A.2 Arithmetic Instructions............................................................................................ 666 Table A.3 Logical Instructions................................................................................................. 670 Table A.4 Shift Instructions ..................................................................................................... 671 Table A.5 Bit-Manipulation Instructions ................................................................................. 674 Table A.6 Branch Instructions ................................................................................................. 679 Table A.7 System Control Instructions .................................................................................... 682 Table A.8 Block Transfer Instructions ..................................................................................... 684 Table A.9 Instruction Codes..................................................................................................... 685 Table A.10 Operation Code Map (1) ......................................................................................... 699 Table A.11 Operation Code Map (2) ......................................................................................... 700 Table A.12 Operation Code Map (3) ......................................................................................... 701 Table A.13 Operation Code Map (4) ......................................................................................... 702 Table A.14 Number of States per Cycle..................................................................................... 704 Table A.15 Number of Cycles in Instruction Execution ............................................................ 705 Table A.16 Instruction Execution Cycles................................................................................... 719 Table A.17 Condition Code Modification.................................................................................. 732 Appendix D Pin States Table D.1 I/O Port States in Each Processing State ................................................................. 861 Appendix F Product Code Lineup H8S/2214 Product Code Lineup.............................................................................. 867 Table F.1 Rev.4.00 Sep. 18, 2008 Page lx of lx REJ09B0189-0400 Section 1 Overview Section 1 Overview 1.1 Overview The H8S/2214 Group is a microcomputer (MCU: microcomputer unit), built around the H8S/2000 CPU, employing Renesas' proprietary architecture, and equipped with the on-chip peripheral functions necessary for system configuration. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. On-chip peripheral functions required for system configuration include DMA controller (DMAC) data transfer controller (DTC) bus masters, ROM and RAM memory, a 16-bit timer-pulse unit (TPU), watchdog timer (WDT), serial communication interface (SCI), D/A converter, and I/O ports. The on-chip ROM is either flash memory (F-ZTAT™*) or masked ROM, with a capacity of 128 kbytes. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching has been speeded up, and processing speed increased. Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or external expansion mode. The features of the H8S/2214 Group are shown in table 1.1. Note: * F-ZTAT is a trademark of Renesas Technology, Corp. Rev.4.00 Sep. 18, 2008 Page 1 of 872 REJ09B0189-0400 Section 1 Overview Table 1.1 Item CPU Overview Specification • General-register machine ⎯ Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control ⎯ Maximum clock rate 16 MHz ⎯ High-speed arithmetic operations (at 16-MHz operation) 8/16/32-bit register-register add/subtract : 62.5 ns 16 × 16-bit register-register multiply : 1250 ns 32 ÷ 16-bit register-register divide : 1250 ns • Instruction set suitable for high-speed operation ⎯ Sixty-five basic instructions ⎯ 8/16/32-bit move/arithmetic and logic instructions ⎯ Unsigned/signed multiply and divide instructions ⎯ Powerful bit-manipulation instructions • Two CPU operating modes ⎯ Normal mode : 64-kbyte address space (not available in the H8S/2214 Group) ⎯ Advanced mode : 16-Mbyte address space Bus controller • • • • • • • DMA controller (DMAC) • • • • Address space divided into 8 areas, with bus specifications settable independently for each area Chip select output possible for each area Choice of 8-bit or 16-bit access space for each area 2-state or 3-state access space can be designated for each area Number of program wait states can be set for each area Burst ROM directly connectable External bus release function Choice of short address mode or full address mode Four channels in short address mode Two channels in full address mode Transfer possible in repeat mode, block transfer mode, etc. Can be activated by internal interrupt Rev.4.00 Sep. 18, 2008 Page 2 of 872 REJ09B0189-0400 Section 1 Overview Item Data transfer controller (DTC) Specification • • • • 16-bit timer-pulse unit (TPU) • • • Watchdog timer (WDT) × 1 channel Serial communication interface (SCI) × 3 channels (SCI0 to SCI2) D/A converter I/O ports Memory Interrupt controller • • • Can be activated by internal interrupt or software Multiple transfers or multiple types of transfer possible for one activation source Transfer possible in repeat mode, block transfer mode, etc. Request can be sent to CPU for interrupt that activated DTC 3-channel 16-bit timer on-chip Pulse I/O processing capability for up to 8 pins Automatic 2-phase encoder count capability Watchdog timer or interval timer selectable Asynchronous mode or synchronous mode selectable Multiprocessor communication function • • • • • • • • Resolution: 8 bits Output: 1 channel 72 I/O pins, 9 input-only pins Flash memory or masked ROM: 128 kbytes High-speed static RAM: 12 kbytes Nine external interrupt pins (NMI, IRQ0 to IRQ7) Eight external expansion interrupt pins (EXIRQ7 to EXIRQ0) 31 internal interrupt sources Eight priority levels settable Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Power-down state • • • • • Rev.4.00 Sep. 18, 2008 Page 3 of 872 REJ09B0189-0400 Section 1 Overview Item Operating modes Specification Four MCU operating modes CPU Operating Description Mode Mode 4 5 6 7 Advanced On-chip ROM disabled expansion mode On-chip ROM disabled expansion mode On-chip ROM enabled expansion mode Single-chip mode External Data Bus On-Chip ROM Disabled Disabled Enabled Enabled Initial Value 16 bits 8 bits 8 bits — Maximum Value 16 bits 16 bits 16 bits Clock pulse generator Clock pulse generators • • • System clock pulse generator: 2 to 16 MHz 100-pin plastic TQFP (TFP-100B, TFP-100BV, TFP-100G, TFP-100GV) 112-pin plastic FBGA (BP-112, BP-112V, TBP-112A, TBP-112AV) Model Name Masked ROM Version HD6432214 F-ZTAT Version HD64F2214 ROM/RAM (Bytes) 128 k/12 k Package Code TFP-100B, TFP-100BV, TFP-100G, TFP-100GV, TBP-112A, TBP-112AV, BP-112, BP-112V On-chip duty correction circuit Packages Product lineup Note: Package codes ending in the letter V designate Pb-free products. Rev.4.00 Sep. 18, 2008 Page 4 of 872 REJ09B0189-0400 Section 1 Overview 1.2 Internal Block Diagrams Figures 1.1 shows internal block diagram of the H8S/2214. VCC VCC VSS VSS RESERVE VSS PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 Port D PE7 / D7 PE6 / D6 PE5/ D5 PE4/ D4 PE3/ D3 PE2/ D2 PE1/ D1 PE0/ D0 Port E Interrupt controller DMAC Peripheral data bus Bus controller Port B H8S/2000 CPU Internal data bus Internal address bus MD2 MD1 MD0 EXTAL XTAL STBY RES NMI FWE System clock pulse generator PA3 /A19/SCK2 PA2 /A18/RxD2 PA1 /A17/TxD2 PA0 /A16 PB7 /A15 PB6 /A14 PB5 /A13 PB4 /A12 PB3 / A11 PB2 /A10 PB1 /A9 PB0 /A8 PC7 /A7 PC6 /A6 PC5 /A5 PC4 /A4 PC3 /A3 PC2 /A2 PC1 /A1 PC0 /A0 P36 / EXIRQ7 P35 /SCK1/IRQ5 P34 /RxD1 P33 /TxD1 P32 /SCK0/IRQ4 P31 /RxD0 P30 /TxD0 AVCC Vref AVSS DTC Peripheral address bus WDT0 PF7 / φ PF6 / AS PF5 / RD PF4 / HWR PF3 / LWR/IRQ3 PF2 / WAIT PF1 / BACK PF0 / BREQ/IRQ2 PG4 / CS0 PG3 / CS1 PG2 / CS2 PG1 / CS3/IRQ7 PG0 / IRQ6 ROM (128 kB) Port F SCI0 (1 channel, High speed UART) RAM (12 kB) SCI1, 2 (2 channels) Port G TPU (3 channels) D/A converter (1 channel) Port 1 Port 7 Port 4 Port 9 P10/TIOCA0 /A20 P11/TIOCB0 /A21 P12/TIOCC0/ TCLKA/A22 P13/TIOCD0/ TCLKB/A23 P14/TIOCA1/IRQ0 P15/TIOCB1/ TCLKC P16/TIOCA2/IRQ1 P17/TIOCB2/TCLKD P40/ EXIRQ0 P41/ EXIRQ1 P42/ EXIRQ2 P43/ EXIRQ3 P44/ EXIRQ4 P45 P46/ EXIRQ5 P47/ EXIRQ6 Figure 1.1 H8S/2214 Group Internal Block Diagram Rev.4.00 Sep. 18, 2008 Page 5 of 872 REJ09B0189-0400 P70 /DREQ0/CS4 P71 /DREQ1/ CS5 P72 /TEND0/ CS6 P73 /TEND1/ CS7 P74/ MRES/ EXDTCE P75/ EXMS P76/EXMSTP P77 P96/DA0 RESERVE Port 3 Port C Port A Section 1 Overview 1.3 1.3.1 Pin Description Pin Arrangements Figures 1.2 and 1.3 show the pin arrangements of the H8S/2214. PF0/BREQ/IRQ2 PF1/BACK PF2/WAIT PF3/LWR/IRQ3 PF4/HWR PF5/RD PF6/AS PF7/φ MD2 FWE EXTAL VSS XTAL VCC STBY NMI RES VSS RESERVE MD1 MD0 AVCC Vref P40/EXIRQ0 P41/EXIRQ1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Figure 1.2 H8S/2214 Group Pin Arrangement (TFP-100B, TFP-100BV, TFP-100G, TFP-100GV: Top View) Rev.4.00 Sep. 18, 2008 Page 6 of 872 REJ09B0189-0400 PE5/D5 PE6/D6 PE7/D7 PD0/D8 PD1/D9 PD2/D10 PD3/D11 PD4/D12 PD5/D13 PD6/D14 PD7/D15 VCC PC0/A0 VSS PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P30/TxD0 P31/RxD0 P32/SCK0/IRQ4 P33/TxD1 P34/RxD1 P35/SCK1/IRQ5 P36/EXIRQ7 P77 P76/EXMSTP P75/EXMS P74/MRES/EXDTCE P73/TEND1/CS7 P72/TEND0/CS6 P71/DREQ1/CS5 P70/DREQ0/CS4 PG0/IRQ6 PG1/CS3/IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 TFP-100B TFP-100BV TFP-100G TFP-100GV (Top view) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P42/EXIRQ2 P43/EXIRQ3 P44/EXIRQ4 P45 P46/EXIRQ5 P47/EXIRQ6 P96/DA0 RESERVE AVSS P17/TIOCB2/TCLKD P16/TIOCA2/IRQ1 P15/TIOCB1/TCLKC P14/TIOCA1/IRQ0 P13/TIOCD0/TCLKB/A23 P12/TIOCC0/TCLKA/A22 P11/TIOCB0/A21 P10/TIOCA0/A20 PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 PB7/A15 PB6/A14 PB5/A13 PB4/A12 Section 1 Overview 11 Reserve PF1/ BACK PF4/HWR PF7/φ EXTAL XTAL STBY VSS MD0 P40/ EXIRQ0 Reserve 10 P30/TxD0 Reserve PF2/ WAIT PF0/ BREQ/ IRQ2 PF5/RD FWE VSS VCC Reserve AVCC P41/ EXIRQ1 P42/ EXIRQ2 9 P33/TxD1 P32/ SCK0/ IRQ4 P35/ SCK1/ IRQ5 PF3/ LWR/ IRQ3 MD2 VCC NMI MD1 Reserve P43/ EXIRQ3 P45 8 P36/ EXIRQ7 P34/RxD1 P31/RxD1 PF6/AS VSS RES Vref P44/ EXIRQ4 P46/ EXIRQ5 P96/DA0 7 P75/ EXMS P72/ TEND0/ CS6 PG0/ IRQ6 P74/ P76/ MRES/ EXDTCE EXMSTP P71/ DREQ1/ CS5 P73/ TEND1/ CS7 P77 6 P70/ DREQ0/ CS4 5 PG1/CS3/ PG2/CS2 PG4/CS0 IRQ7 BP-112 BP-112V TBP-112 TBP-112V (Top view) P47/ EXIRQ6 P17/ TIOCB2/ TCLKD P10/ TIOCA0/ A20 Reserve AVSS AVSS P14/ TIOCA1/ IRQ0 P11/ TIOCB0/ A21 P16/ TIOCA2/ IRQ1 P13/ TIOCD0/ TCLKB/ A23 P15/ TIOCB1/ TCLKC P12/ TIOCC0/ TCLKA/ A22 4 PG3/CS1 PE0/D0 PE2/D2 PE7/D7 PD5/D13 VSS PC5/A5 PB6/A14 PA1/A17/ PA2/A18/ PA3/A19/ TxD2 RxD2 SCK2 3 PE1/D1 PE3/D3 Reserve PD2/D10 PD6/D14 VCC PC3/A3 PB0/A8 PB3/A11 PB7/A15 PA0/A16 2 PE4/D4 PE5/D5 PD0/D8 PD3/D11 VCC VSS PC2/A2 PC6/A6 PB1/A9 PB4/A12 PB5/A13 1 Reserve PE6/D6 PD1/D9 PD4/D12 PD7/D15 PC0/A0 PC1/A1 PC4/A4 PC7/A7 PB2/A10 Reserve INDEX A B C D E F G H J K L Figure 1.3 H8S/2214 Group Pin Arrangement (BP-112, BP-112V, TBP-112A, TBP-112AV: Top View) Rev.4.00 Sep. 18, 2008 Page 7 of 872 REJ09B0189-0400 Section 1 Overview 1.3.2 Pin Functions in Each Operating Mode Table 1.2 shows the pin functions of the H8S/2214 Group in each of the operating modes. Table 1.2 Pin Functions in Each Operating Mode Pin Name Pin No. TFP-100B, TFP-100BV, TFP-100G, TFP-100GV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 BP-112, BP-112V, TBP-112A, TBP-112AV Mode 4 B2 B1 D4 C2 C1 D3 D2 D1 E4 E3 E1 E2, F3 F1 F2, F4 G1 G2 G3 H1 G4 H2 J1 H3 J2 K1 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 D13 D14 D15 VCC A0 VSS A1 A2 A3 A4 A5 A6 A7 PB0/A8 PB1/A9 PB2/A10 Mode 5 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 D13 D14 D15 VCC A0 VSS A1 A2 A3 A4 A5 A6 A7 PB0/A8 PB1/A9 PB2/A10 Mode 6 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 D11 D12 D13 D14 D15 VCC PC0/A0 VSS PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 Mode 7 PE5 PE6 PE7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 VCC PC0 VSS PC1 PC2 PC3 PC4 PC5 PC6 PC7 PB0 PB1 PB2 PROM Mode* NC NC NC D0 D1 D2 D3 D4 D5 D6 D7 VCC A0 VSS A1 A2 A3 A4 A5 A6 A7 A8 OE A10 Rev.4.00 Sep. 18, 2008 Page 8 of 872 REJ09B0189-0400 Section 1 Overview Pin No. TFP-100B, TFP-100BV, TFP-100G, TFP-100GV 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 BP-112, BP-112V, TBP-112A, TBP-112AV Mode 4 J3 K2 L2 H4 K3 L3 J4 K4 L4 H5 J5 L5 K5 J6 L6 K6 H6 K7, L7 J7 L8 H7 K8 L9 J8 K9 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 Pin Name Mode 5 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 Mode 6 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 Mode 7 PB3 PB4 PB5 PB6 PB7 PA0 PA1/TxD2 PA2/RxD2 PA3/SCK2 PROM Mode* A11 A12 A13 A14 A15 A16 VCC VCC NC NC NC NC NC VSS NC VSS NC VSS NC NC NC NC NC NC NC P10/TIOCA0/A20 P10/TIOCA0/A20 P10/TIOCA0/A20 P10/TIOCA0 P11/TIOCB0/A21 P11/TIOCB0/A21 P11/TIOCB0/A21 P11/TIOCB0 P12/TIOCC0/ TCLKA/A22 P13/TIOCD0/ TCLKB/A23 P14/TIOCA1/ IRQ0 P15/TIOCB1/ TCLKC P16/TIOCA2/ IRQ1 P17/TIOCB2/ TCLKD AVSS Reserve P96/DA0 P47/EXIRQ6 P46/EXIRQ5 P45 P44/EXIRQ4 P43/EXIRQ3 P12/TIOCC0/ TCLKA/A22 P13/TIOCD0/ TCLKB/A23 P14/TIOCA1/ IRQ0 P15/TIOCB1/ TCLKC P16/TIOCA2/ IRQ1 P17/TIOCB2/ TCLKD AVSS Reserve P96/DA0 P47/EXIRQ6 P46/EXIRQ5 P45 P44/EXIRQ4 P43/EXIRQ3 P12/TIOCC0/ TCLKA/A22 P13/TIOCD0/ TCLKB/A23 P14/TIOCA1/ IRQ0 P15/TIOCB1/ TCLKC P16/TIOCA2/ IRQ1 P17/TIOCB2/ TCLKD AVSS Reserve P96/DA0 P47/EXIRQ6 P46/EXIRQ5 P45 P44/EXIRQ4 P43/EXIRQ3 P12/TIOCC0/ TCLKA P13/TIOCD0/ TCLKB P14/TIOCA1/ IRQ0 P15/TIOCB1/ TCLKC P16/TIOCA2/ IRQ1 P17/TIOCB2/ TCLKD AVSS Reserve P96/DA0 P47/EXIRQ6 P46/EXIRQ5 P45 P44/EXIRQ4 P43/EXIRQ3 Rev.4.00 Sep. 18, 2008 Page 9 of 872 REJ09B0189-0400 Section 1 Overview Pin No. TFP-100B, TFP-100BV, TFP-100G, TFP-100GV 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 BP-112, BP-112V, TBP-112A, TBP-112AV Mode 4 L10 K10 K11 H8 J10 J11 H9 H10 H11 G8 G9 G11 F9, G10 F11 F8, F10 E11 E10 E9 D11 E8 D10 C11 D9 C10 B11 C9 A10 D8 B9 P42/EXIRQ2 P41/EXIRQ1 P40/EXIRQ0 Vref AVCC MD0 MD1 Reserve VSS RES NMI STBY VCC XTAL VSS EXTAL FWE MD2 PF7/φ AS RD HWR PF3/LWR/IRQ3 PF2/WAIT PF1/BACK Pin Name Mode 5 P42/EXIRQ2 P41/EXIRQ1 P40/EXIRQ0 Vref AVCC MD0 MD1 Reserve VSS RES NMI STBY VCC XTAL VSS EXTAL FWE MD2 PF7/φ AS RD HWR PF3/LWR/IRQ3 PF2/WAIT PF1/BACK Mode 6 P42/EXIRQ2 P41/EXIRQ1 P40/EXIRQ0 Vref AVCC MD0 MD1 Reserve VSS RES NMI STBY VCC XTAL VSS EXTAL FWE MD2 PF7/φ AS RD HWR PF3/LWR/IRQ3 PF2/WAIT PF1/BACK Mode 7 P42/EXIRQ2 P41/EXIRQ1 P40/EXIRQ0 Vref AVCC MD0 MD1 Reserve VSS RES NMI STBY VCC XTAL VSS EXTAL FWE MD2 PF7/φ PF6 PF5 PF4 PF3/IRQ3 PF2 PF1 PROM Mode* NC NC NC VCC VCC VSS VSS NC NC VPP A9 VSS VCC NC VSS NC FWE VSS NC NC NC NC VCC CE PGM VCC NC NC NC PF0/BREQ/IRQ2 PF0/BREQ/IRQ2 PF0/BREQ/IRQ2 PF0/IRQ2 P30/TxD0 P31/RxD1 P32/SCK0/IRQ4 P30/TxD0 P31/RxD1 P32/SCK0/IRQ4 P30/TxD0 P31/RxD1 P32/SCK0/IRQ4 P30/TxD0 P31/RxD1 P32/SCK0/IRQ4 Rev.4.00 Sep. 18, 2008 Page 10 of 872 REJ09B0189-0400 Section 1 Overview Pin No. TFP-100B, TFP-100BV, TFP-100G, TFP-100GV 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 — BP-112, BP-112V, TBP-112A, TBP-112AV Mode 4 A9 C8 B8 A8 D7 C7 A7 B7 C6 A6 B6 D6 A5 B5 C5 A4 D5 B4 A3 C4 B3 A2 P33/TxD1 P34/RxD1 P35/SCK1/IRQ5 P36/EXIRQ7 P77 P76/EXMSTP P75/EXMS P74/MRES/ EXDTCE Pin Name Mode 5 P33/TxD1 P34/RxD1 P35/SCK1/IRQ5 P36/EXIRQ7 P77 P76/EXMSTP P75/EXMS P74/MRES/ EXDTCE Mode 6 P33/TxD1 P34/RxD1 P35/SCK1/IRQ5 P36/EXIRQ7 P77 P76/EXMSTP P75/EXMS P74/MRES/ EXDTCE Mode 7 P33/TxD1 P34/RxD1 P35/SCK1/IRQ5 P36/EXIRQ7 P77 P76/EXMSTP P75/EXMS P74/MRES/ EXDTCE PROM Mode* NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VSS Reserve P73/TEND1/CS7 P73/TEND1/CS7 P73/TEND1/CS7 P73/TEND1 P72/TEND0/CS6 P72/TEND0/CS6 P72/TEND0/CS6 P72/TEND0 P71/DREQ1/CS5 P71/DREQ1/CS5 P71/DREQ1/CS5 P71/DREQ1 P70/DREQ0/CS4 P70/DREQ0/CS4 P70/DREQ0/CS4 P70/DREQ0 PG0/IRQ6 PG1/CS3/IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 PG0/IRQ6 PG1/CS3/IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 Reserve PG0/IRQ6 PG1/CS3/IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 Reserve PG0/IRQ6 PG1/IRQ7 PG2 PG3 PG4 PE0 PE1 PE2 PE3 PE4 Reserve A1, A11, B10, Reserve C3, J9, L1, L11 Note: * NC pins must be left open. Rev.4.00 Sep. 18, 2008 Page 11 of 872 REJ09B0189-0400 Section 1 Overview 1.3.3 Pin Functions Table 1.3 outlines the pin functions of the H8S/2214. Table 1.3 Type Power Pin Functions Symbol VCC VSS I/O Input Input Input Name and Function Power supply: For connection to the power supply. All VCC pins should be connected to the system power supply. Ground: For connection to ground (0 V). All VSS pins should be connected to the system power supply (0 V). Crystal: Connects to a crystal oscillator. See section 16, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. External clock: Connects to a crystal oscillator. The EXTAL pin can also input an external clock. See section 16, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. Clock XTAL EXTAL Input φ Operating mode control MD2 to MD0 Output System clock: Supplies the system clock to an external device. Input Mode pins: These pins set the operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the H8S/2214 is operating. Except when the mode is changed, the mode pins (MD2 to MD0) must be pulled down or pulled up to a fixed level until powering off. MD2 0 MD1 0 1 1 0 1 MD0 0 1 0 1 0 1 0 1 Operating Mode — — — — Mode 4 Mode 5 Mode 6 Mode 7 Rev.4.00 Sep. 18, 2008 Page 12 of 872 REJ09B0189-0400 Section 1 Overview Type System control Symbol RES MRES STBY BREQ BACK FWE Interrupts NMI IRQ7 to IRQ0 Address bus Data bus Bus control A23 to A0 D15 to D0 CS7 to CS0 AS RD HWR I/O Input Input Input Input Name and Function Reset input: When this pin is driven low, the chip enters the power-on reset state. Manual reset: When this pin is driven low, the chip enters the manual reset state. Standby: When this pin is driven low, a transition is made to hardware standby mode. Bus request: Used by an external bus master to issue a bus request to the H8S/2214. Output Bus request acknowledge: Indicates that the bus has been released to an external bus master. Input Input Input Flash write enable: Enables/disables flash memory programming. Nonmaskable interrupt: Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high. Interrupt request 7 to 0: These pins request a maskable interrupt. Output Address bus: These pins output an address. I/O Data bus: These pins constitute a bidirectional data bus. Output Chip select: Signals for selecting areas 7 to 0. Output Address strobe: When this pin is low, it indicates that address output on the address bus is enabled. Output Read: When this pin is low, it indicates that the external address space can be read. Output High write: A strobe signal that writes to external space and indicates that the upper half (D15 to D8) of the data bus is enabled. Output Low write: A strobe signal that writes to external space and indicates that the lower half (D7 to D0) of the data bus is enabled. Input Wait: Requests insertion of a wait state in the bus cycle when accessing external 3-state address space. External expansion interrupt request 7 to 0: Input pins for interrupt requests from external modules. LWR WAIT External expansion EXIRQ7 to Input EXIRQ0 EXMS Output External expansion module select: Select signal for external modules. Rev.4.00 Sep. 18, 2008 Page 13 of 872 REJ09B0189-0400 Section 1 Overview Type External expansion Symbol EXDTC EXMSTP DMA controller (DMAC) DREQ1, DREQ0 TEND1, TEND0 16-bit timerTCLKD to pulse unit (TPU) TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 Serial communication interface (SCI) TxD2, TxD1, TxD0 RxD2, RxD1, RxD0 SCK2, SCK1 SCK0 D/A converter DA0 AVCC I/O Name and Function Output External expansion DTC transfer end: DTC data transfer end signal for EXIRQ7 to EXIRQ0 input. Output External expansion module stop: Module stop signal for external modules. Input DMA request 1 and 0: These pins request DMAC activation. Output DMA transfer end 1 and 0: These pins indicate the end of DMAC data transfer. Input I/O Clock input D to A: These pins input an external clock. Input capture/output compare match A0 to D0: The TGR0A to TGR0D input capture input or output compare output, or PWM output pins. Input capture/output compare match A1 and B1: The TGR1A and TGR1B input capture input or output compare output, or PWM output pins. Input capture/output compare match A2 and B2: The TGR2A and TGR2B input capture input or output compare output, or PWM output pins. I/O I/O Output Transmit data: Data output pins. Input Receive data: Data input pins. I/O Serial clock: Clock I/O pins. Output Analog output: D/A converter analog output pins. Input Analog power supply: This is the power supply pin for the D/A converter. When the D/A converter is not used, this pin should be connected to the system power supply (VCC). Analog ground: This is the ground pin for the D/A converter. This pin should be connected to the system power supply (0 V). Analog reference power supply: This is the reference voltage input pin for the D/A converter. When the D/A converter is not used, this pin should be connected to the system power supply (VCC). AVSS Input Vref Input Rev.4.00 Sep. 18, 2008 Page 14 of 872 REJ09B0189-0400 Section 1 Overview Type I/O ports Symbol P17 to P10 P36 to P30 P47 to P40 P77 to P70 P96 PA3 to PA0 PB7 to PB0 PC7 to PC0 PD7 to PD0 PE7 to PE0 PF7 to PF0 PG4 to PG0 RESERVE I/O I/O Name and Function Port 1: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 1 data direction register (P1DDR). Port 3: A 7-bit I/O port. Input or output can be designated for each bit by means of the port 3 data direction register (P3DDR). Port 4: An 8-bit input port. Port 7: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 7 data direction register (P7DDR). Port 9: A 1-bit input port. Port A: A 4-bit I/O port. Input or output can be designated for each bit by means of the port A data direction register (PADDR). Port B: An 8-bit I/O port. Input or output can be designated for each bit by means of the port B data direction register (PBDDR). Port C: An 8-bit I/O port. Input or output can be designated for each bit by means of the port C data direction register (PCDDR). Port D: An 8-bit I/O port. Input or output can be designated for each bit by means of the port D data direction register (PDDDR). Port E: An 8-bit I/O port. Input or output can be designated for each bit by means of the port E data direction register (PEDDR). Port F: An 8-bit I/O port. Input or output can be designated for each bit by means of the port F data direction register (PFDDR). Port G: A 5-bit I/O port. Input or output can be designated for each bit by means of the port G data direction register (PGDDR). Reserved pins: These pins should be open and should not be connected to any device. I/O Input I/O Input I/O I/O I/O I/O I/O I/O I/O RESERVE — Rev.4.00 Sep. 18, 2008 Page 15 of 872 REJ09B0189-0400 Section 1 Overview Rev.4.00 Sep. 18, 2008 Page 16 of 872 REJ09B0189-0400 Section 2 CPU Section 2 CPU 2.1 Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2000 CPU has the following features. • Upward-compatible with H8/300 and H8/300H CPUs ⎯ Can execute H8/300 and H8/300H object programs • General-register architecture ⎯ Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • Sixty-five basic instructions ⎯ 8/16/32-bit arithmetic and logic instructions ⎯ Multiply and divide instructions ⎯ Powerful bit-manipulation instructions • Eight addressing modes ⎯ Register direct [Rn] ⎯ Register indirect [@ERn] ⎯ Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] ⎯ Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn] ⎯ Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] ⎯ Immediate [#xx:8, #xx:16, or #xx:32] ⎯ Program-counter relative [@(d:8,PC) or @(d:16,PC)] ⎯ Memory indirect [@@aa:8] • 16-Mbyte address space ⎯ Program: 16 Mbytes ⎯ Data: 16 Mbytes (4 Gbytes architecturally) Rev.4.00 Sep. 18, 2008 Page 17 of 872 REJ09B0189-0400 Section 2 CPU • High-speed operation ⎯ All frequently-used instructions execute in one or two states ⎯ Maximum clock rate ⎯ 8 × 8-bit register-register multiply ⎯ 16 ÷ 8-bit register-register divide ⎯ 16 × 16-bit register-register multiply ⎯ 32 ÷ 16-bit register-register divide • Two CPU operating modes ⎯ Normal mode* ⎯ Advanced mode Note: * Not available in the H8S/2214 Group. • Power-down state ⎯ Transition to power-down state by SLEEP instruction ⎯ CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU : 16 MHz : 750 ns : 750 ns : 1250 ns : 1250 ns ⎯ 8/16/32-bit register-register add/subtract : 62.5 ns The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. • Register configuration The MAC register is supported only by the H8S/2600 CPU. • Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. • Number of execution states The number of exection states of the MULXU and MULXS instructions. Internal Operation Instruction MULXU MULXS Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21 Rev.4.00 Sep. 18, 2008 Page 18 of 872 REJ09B0189-0400 Section 2 CPU There are also differences in the address space, CCR and EXR register functions, power-down state, etc., depending on the product. 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers ⎯ Eight 16-bit expanded registers, plus one 8-bit and two 32-bit control registers, have been added • Expanded address space ⎯ Normal mode* supports the same 64-kbyte address space as the H8/300 CPU ⎯ Advanced mode supports a maximum 16-Mbyte address space Note: * Not available in the H8S/2214 Group. • Enhanced addressing ⎯ The addressing modes have been enhanced to make effective use of the 16-Mbyte address space • Enhanced instructions ⎯ Addressing modes of bit-manipulation instructions have been enhanced ⎯ Signed multiply and divide instructions have been added ⎯ Two-bit shift instructions have been added ⎯ Instructions for saving and restoring multiple registers have been added ⎯ A test and set instruction has been added • Higher speed ⎯ Basic instructions execute twice as fast 2.1.4 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. • Additional control register ⎯ One 8-bit and two 32-bit control registers have been added • Enhanced instructions ⎯ Addressing modes of bit-manipulation instructions have been enhanced ⎯ Two-bit shift instructions have been added ⎯ Instructions for saving and restoring multiple registers have been added ⎯ A test and set instruction has been added Rev.4.00 Sep. 18, 2008 Page 19 of 872 REJ09B0189-0400 Section 2 CPU • Higher speed ⎯ Basic instructions execute twice as fast 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal* and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data areas combined). The mode is selected by the mode pins of the microcontroller. Note: * Not available in the H8S/2214 Group. Normal mode* Maximum 64-kbytes, program and data areas combined CPU operating modes Advanced mode Maximum 16-Mbytes for program and data areas combined Note: * Not available in the H8S/2214 Group. Figure 2.1 CPU Operating Modes (1) Normal Mode (not available in the H8S/2214 Group) The exception vector table and stack have the same structure as in the H8/300 CPU. (a) Address Space A maximum address space of 64 kbytes can be accessed. (b) Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@–Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. Rev.4.00 Sep. 18, 2008 Page 20 of 872 REJ09B0189-0400 Section 2 CPU (c) Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. (d) Exception Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The configuration of the exception vector table in normal mode is shown in figure 2.2. For details of the exception vector table, see section 4, Exception Handling. H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Power-on reset exception vector Manual reset exception vector (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.2 Exception Vector Table (Normal Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. Rev.4.00 Sep. 18, 2008 Page 21 of 872 REJ09B0189-0400 Section 2 CPU (e) Stack Structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. SP PC (16 bits) SP *2 (SP ) EXR*1 Reserved*1 *3 CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. Figure 2.3 Stack Structure in Normal Mode (2) Advanced Mode (a) Address Space Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program and data areas combined). (b) Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. (c) Instruction Set All instructions and addressing modes can be used. Rev.4.00 Sep. 18, 2008 Page 22 of 872 REJ09B0189-0400 Section 2 CPU (d) Exception Vector Table and Memory Indirect Branch Addresses In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Power-on reset exception vector H'00000003 H'00000004 Reserved Manual reset exception vector H'00000007 H'00000008 Exception vector table H'0000000B H'0000000C (Reserved for system use) H'00000010 Reserved Exception vector 1 Figure 2.4 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table. Rev.4.00 Sep. 18, 2008 Page 23 of 872 REJ09B0189-0400 Section 2 CPU (e) Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. SP SP Reserved PC (24 bits) *2 (SP ) EXR*1 Reserved*1 *3 CCR PC (24 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. Figure 2.5 Stack Structure in Advanced Mode Rev.4.00 Sep. 18, 2008 Page 24 of 872 REJ09B0189-0400 Section 2 CPU 2.3 Address Space Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. Note that the modes and address spaces that can actually be used differ between individual products. See section 3, MCU Operating Modes, for details. H'0000 64 kbyte H'FFFF 16 Mbyte Program area H'00000000 H'00FFFFFF Data area Cannot be used by the H8S/2214 Group H'FFFFFFFF (a) Normal Mode* Note: * Not available in the H8S/2214 Group. (b) Advanced Mode Figure 2.6 Memory Map Rev.4.00 Sep. 18, 2008 Page 25 of 872 REJ09B0189-0400 Section 2 CPU 2.4 2.4.1 Register Configuration Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Control Registers (CR) 23 PC 76543210 EXR T — — — — I2 I1 I0 76543210 CCR I UI H U N Z V C Legend: SP: PC: EXR: T: I2 to I0: CCR: I: UI: 0 Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit* H: U: N: Z: V: C: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Note: * In the H8S/2214 Group, this bit cannot be used as an interrupt mask. Figure 2.7 CPU Registers Rev.4.00 Sep. 18, 2008 Page 26 of 872 REJ09B0189-0400 Section 2 CPU 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2.8 illustrates the usage of the general registers. The usage of each register can be selected independently. • Address registers • 32-bit registers • 16-bit registers E registers (extended registers) (E0 to E7) • 8-bit registers ER registers (ER0 to ER7) R registers (R0 to R7) RH registers (R0H to R7H) RL registers (R0L to R7L) Figure 2.8 Usage of General Registers Rev.4.00 Sep. 18, 2008 Page 27 of 872 REJ09B0189-0400 Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the stack. Free area SP (ER7) Stack area Figure 2.9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored (When an instruction is fetched, the least significant PC bit is regarded as 0). (2) Extended Control Register (EXR) This 8-bit register contains the trace bit (T) and interrupt mask bit (I). Bit 7—Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is executed. Bits 6 to 3—Reserved: These bits are reserved. They are always read as 1. Rev.4.00 Sep. 18, 2008 Page 28 of 872 REJ09B0189-0400 Section 2 CPU Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. All interrupts, including NMI, are disabled for three states after one of these instructions is executed, except for STC. (3) Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller. Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. With the H8S/2214 Group, this bit cannot be used as an interrupt mask bit. Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data. Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: • Add instructions, to indicate a carry • Subtract instructions, to indicate a borrow • Shift and rotate instructions, to indicate a carry Rev.4.00 Sep. 18, 2008 Page 29 of 872 REJ09B0189-0400 Section 2 CPU The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to appendix A.1, Instruction List. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. 2.4.4 Initial Register Values Reset exception handling loads the CPU’s program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. Rev.4.00 Sep. 18, 2008 Page 30 of 872 REJ09B0189-0400 Section 2 CPU 2.5 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figures 2.10 and 2.11 show the data formats in general registers. Data Type Register Number Data Format 1-bit data RnH 7 0 76543210 Don’t care 7 0 76543210 1-bit data RnL Don’t care 4-bit BCD data RnH 7 Upper 43 Lower 0 Don’t care 7 43 Upper 0 Don’t care LSB 7 0 LSB Lower 0 4-bit BCD data RnL Don’t care Byte data RnH 7 MSB Byte data RnL Don’t care MSB Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.10 General Register Data Formats (1) Rev.4.00 Sep. 18, 2008 Page 31 of 872 REJ09B0189-0400 Section 2 CPU Data Type Register Number Data Format Word data Rn 15 MSB 0 LSB Word data 15 MSB Longword data 31 MSB En 0 LSB ERn 16 15 En Rn 0 LSB Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.11 General Register Data Formats (2) Rev.4.00 Sep. 18, 2008 Page 32 of 872 REJ09B0189-0400 Section 2 CPU 2.5.2 Memory Data Formats Figure 2.12 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 0 0 Data Format Byte data Address L MSB LSB Word data Address 2M MSB Address 2M + 1 LSB Longword data Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB Figure 2.12 Memory Data Formats When ER7 is used as an address register to access the stack, the operand size should be word size or longword size. Rev.4.00 Sep. 18, 2008 Page 33 of 872 REJ09B0189-0400 Section 2 CPU 2.6 2.6.1 Instruction Set Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Function Data transfer Instruction Classification Instructions MOV 1 1 POP* , PUSH* LDM* , STM* 5 5 3 MOVFPE, MOVTPE* Size BWL WL L B BWL B BWL L BW WL B BWL BWL B — — Types 5 Arithmetic operations ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS 4 TAS* 19 Logic operations Shift Bit manipulation Branch System control Block data transfer AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR 2 Bcc* , JMP, BSR, JSR, RTS EEPMOV 4 8 14 5 9 1 TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — Total: 65 Notes: B: Byte size; W: Word size; L: Longword size. 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in the H8S/2214 Group. 4. This instruction should be used with the ER0, ER1, ER4, or ER5 general register only. 5. The STM/LDM instructions may only be used with the ER0 to ER6 registers. Rev.4.00 Sep. 18, 2008 Page 34 of 872 REJ09B0189-0400 2.6.2 Addressing Modes Table 2.2 Function Instruction #xx Rn @ERn @(d:16,ERn) @(d:32,ERn) @–ERn/@ERn+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,PC) @(d:16,PC) @@aa:8 Data transfer BWL — — — BWL BWL B L BWL B BW BW BWL WL — B — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — B — — — — — — — — — — — — — — — — — L — — — — — — — — — — — WL BWL BWL BWL BWL B BWL — BWL — — — — MOV BWL — POP, PUSH LDM*3, STM*3 — MOVFPE*1, MOVTPE*1 — Arithmetic operations ADD, CMP BWL SUB WL ADDX, SUBX B ADDS, SUBS — INC, DEC — DAA, DAS — Instructions and Addressing Modes — MULXU, DIVXU MULXS, DIVXS — NEG — EXTU, EXTS TAS*2 — — Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Combinations of Instructions and Addressing Modes Rev.4.00 Sep. 18, 2008 Page 35 of 872 REJ09B0189-0400 Notes: 1. Cannot be used in the H8S/2214 Group. 2. This instruction should be used with the ER0, ER1, ER4, or ER5 general register only. 3. The STM/LDM instructions may only be used with the ER0 to ER6 registers. — Section 2 CPU Addressing Modes Function Instruction #xx Rn @ERn @(d:16,ERn) @(d:32,ERn) @–ERn/@ERn+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,PC) @(d:16,PC) @@aa:8 — Section 2 CPU Logic operations BWL — — — — — — — — — B — B — — — — — — — — — — — — — — — — — — — — — — — B W W W W — W — — — — B W W W W — W — — — — — — — — — — — — — — — — — — — W W — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — B B — — — B B — B — — BWL — — — — — — — — — — BWL — — — — — — — — — — — — — — BWL — — — — — — — — — — — AND, OR, XOR — — — — — — NOT Shift Bit manipulation Branch Bcc, BSR JMP, JSR RTS Rev.4.00 Sep. 18, 2008 Page 36 of 872 REJ09B0189-0400 — — — BW System control TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP Block data transfer Legend: B: Byte W: Word L: Longword Section 2 CPU 2.6.3 Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation Rd Rs Rn ERn (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + – × ÷ ∧ ∨ ⊕ → ¬ :8/:16/:24/:32 General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev.4.00 Sep. 18, 2008 Page 37 of 872 REJ09B0189-0400 Section 2 CPU Table 2.3 Type Data transfer Instructions Classified by Function Instruction MOV 1 Size* Function (EAs) → Rd, Rs → (Ead) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Cannot be used in the H8S/2214. Cannot be used in the H8S/2214. @SP+ → Rn Pops a register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn → @–SP Pushes a register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP. @SP+ → Rn (register list) Pops two or more general registers from the stack. Rn (register list) → @–SP Pushes two or more general registers onto the stack. B/W/L MOVFPE MOVTPE POP B B W/L PUSH W/L LDM* 2 L L 2 STM* Rev.4.00 Sep. 18, 2008 Page 38 of 872 REJ09B0189-0400 Section 2 CPU Type Arithmetic operations Instruction ADD SUB 1 Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction). Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. Rd ± 1 → Rd, Rd ± 2 → Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust → Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd × Rs → Rd Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. Rd × Rs → Rd Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. Rd ÷ Rs → Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder. B/W/L ADDX SUBX B INC DEC B/W/L ADDS SUBS DAA DAS L B MULXU B/W MULXS B/W DIVXU B/W Rev.4.00 Sep. 18, 2008 Page 39 of 872 REJ09B0189-0400 Section 2 CPU Type Arithmetic operations Instruction DIVXS 1 Size* Function Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder. Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 – Rd → Rd Takes the two’s complement (arithmetic complement) of data in a general register. Rd (zero extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. @ERd – 0, 1 → ( of @ERd) Tests memory contents, and sets the most significant bit (bit 7) to 1. B/W CMP B/W/L NEG B/W/L EXTU W/L EXTS W/L TAS* 3 B Rev.4.00 Sep. 18, 2008 Page 40 of 872 REJ09B0189-0400 Section 2 CPU Type Logic operations Instruction AND 1 Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. ¬ (Rd) → (Rd) Takes the one’s complement of general register contents. Rd (shift) → Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. Rd (shift) → Rd Performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. Rd (rotate) → Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. Rd (rotate) → Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. B/W/L OR B/W/L XOR B/W/L NOT B/W/L Shift operations SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR B/W/L B/W/L B/W/L B/W/L Rev.4.00 Sep. 18, 2008 Page 41 of 872 REJ09B0189-0400 Section 2 CPU Type Bitmanipulation instructions Instruction BSET 1 Size* Function 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ¬ ( of ) → ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ¬ ( of ) → Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. C ∧ ( of ) → C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ∧ ¬ ( of ) → C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ∨ ( of ) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ∨ ¬ ( of ) → C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. B BCLR B BNOT B BTST B BAND B BIAND B BOR B BIOR B Rev.4.00 Sep. 18, 2008 Page 42 of 872 REJ09B0189-0400 Section 2 CPU Type Bitmanipulation instructions Instruction BXOR 1 Size* Function C ⊕ ( of ) → C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕ ¬ ( of ) → C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. ( of ) → C Transfers a specified bit in a general register or memory operand to the carry flag. ¬ ( of ) → C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. C → ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. ¬ C → ( of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. B BIXOR B BLD B BILD B BST B BIST B Rev.4.00 Sep. 18, 2008 Page 43 of 872 REJ09B0189-0400 Section 2 CPU Type Branch instructions Instruction Bcc Size — Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE JMP BSR JSR RTS — — — — Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never C∨Z=0 C∨Z=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 N⊕V=0 N⊕V=1 Z ∨ (N ⊕ V) = 0 Z ∨ (N ⊕ V) = 1 Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine Rev.4.00 Sep. 18, 2008 Page 44 of 872 REJ09B0189-0400 Section 2 CPU Type Instruction 1 Size* Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR → (EAd), EXR → (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR Logically ANDs the CCR or EXR contents with immediate data. CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR Logically ORs the CCR or EXR contents with immediate data. CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 → PC Only increments the program counter. System control TRAPA instructions RTE SLEEP LDC — — — B/W STC B/W ANDC B ORC B XORC B NOP — Rev.4.00 Sep. 18, 2008 Page 45 of 872 REJ09B0189-0400 Section 2 CPU Type Block data transfer instruction Instruction EEPMOV.B Size — Function if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6. R4L or R4: size of block (bytes) ER5: starting source address ER6: starting destination address Execution of the next instruction begins as soon as the transfer is completed. Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. The STM/LDM instructions may only be used with the ER0 to ER6 registers. 3. This instruction should be used with the ER0, ER1, ER4, or ER5 general register only. EEPMOV.W — Rev.4.00 Sep. 18, 2008 Page 46 of 872 REJ09B0189-0400 Section 2 CPU 2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc field). Figure 2.13 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc rn rm MOV.B @(d:16, Rn), Rm, etc. Figure 2.13 Instruction Formats (Examples) (1) Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. (2) Register Field Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. Rev.4.00 Sep. 18, 2008 Page 47 of 872 REJ09B0189-0400 Section 2 CPU (3) Effective Address Extension Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. (4) Condition Field Specifies the branching condition of Bcc instructions. 2.6.5 Notes on Use of Bit-Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, carry out bit manipulation, then write back the byte of data. Caution is therefore required when using these instructions on a register containing write-only bits, or a port. The BCLR instruction can be used to clear internal I/O register flags to 0. In this case, the relevant flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt handling routine, etc. See section 2.10.3, Bit Manipulation Instructions Usage Notes, for details. 2.7 2.7.1 Addressing Modes and Effective Address Calculation Addressing Mode The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Rev.4.00 Sep. 18, 2008 Page 48 of 872 REJ09B0189-0400 Section 2 CPU Table 2.4 No. 1 2 3 4 5 6 7 8 Addressing Modes Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @–ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 (1) Register Direct—Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. (2) Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). (3) Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. (4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. Rev.4.00 Sep. 18, 2008 Page 49 of 872 REJ09B0189-0400 Section 2 CPU • Register indirect with pre-decrement—@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. (5) Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.5 indicates the accessible absolute address ranges. Table 2.5 Absolute Address Access Ranges Normal Mode* 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF Absolute Address Data address Note: * Not available in the H8S/2214 Group. Rev.4.00 Sep. 18, 2008 Page 50 of 872 REJ09B0189-0400 Section 2 CPU (6) Immediate—#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) Program-Counter Relative—@(d:8, PC) or @(d:16, PC) This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an even number. (8) Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF* in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Note: * Not available in the H8S/2214 Group. Rev.4.00 Sep. 18, 2008 Page 51 of 872 REJ09B0189-0400 Section 2 CPU Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode* (b) Advanced Mode Note: * Not available in the H8S/2214 Group. Figure 2.14 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation Table 2.6 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Rev.4.00 Sep. 18, 2008 Page 52 of 872 REJ09B0189-0400 No. Effective Address Calculation Addressing Mode and Instruction Format Effective Address (EA) 1 Operand is general register contents. Table 2.6 Register direct (Rn) op rm rn 2 31 General register contents Don’t care 0 31 24 23 0 Register indirect (@ERn) op r 3 31 General register contents 31 disp 31 Sign extension disp 0 Don’t care 24 23 0 Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) 0 Effective Address Calculation op r 4 31 General register contents 0 Register indirect with post-increment or pre-decrement • Register indirect with post-increment @ERn+ 31 24 23 Don’t care 0 op r 1, 2, or 4 31 General register contents 31 24 23 Don’t care Operand Size Value added Byte Word Longword 1 2 4 1, 2, or 4 0 0 • Register indirect with pre-decrement @–ERn Rev.4.00 Sep. 18, 2008 Page 53 of 872 REJ09B0189-0400 op r Section 2 CPU No. Effective Address Calculation Addressing Mode and Instruction Format Effective Address (EA) 5 31 24 23 H'FFFF Don’t care Absolute address 87 0 @aa:8 Section 2 CPU op abs @aa:16 31 24 23 Sign extension abs Don’t care 16 15 0 op @aa:24 31 24 23 abs Don’t care 0 Rev.4.00 Sep. 18, 2008 Page 54 of 872 REJ09B0189-0400 31 abs 24 23 Don’t care op @aa:32 0 op 6 IMM Immediate #xx:8/#xx:16/#xx:32 Operand is immediate data. op No. Effective Address Calculation 23 PC contents 0 Addressing Mode and Instruction Format Effective Address (EA) 7 Program-counter relative @(d:8, PC)/@(d:16, PC) op 23 Sign extension disp 31 24 23 Don’t care disp 0 0 8 Memory indirect @@aa:8 • Normal mode* op 31 0 abs 31 H'000000 87 abs 24 23 Don’t care 16 15 H'00 0 15 Memory contents 0 • Advanced mode op 31 H'000000 31 abs 87 abs 0 Memory contents 31 24 23 Don’t care 0 0 Rev.4.00 Sep. 18, 2008 Page 55 of 872 REJ09B0189-0400 Section 2 CPU Note: * Not available in the H8S/2214 Group. Section 2 CPU 2.8 2.8.1 Processing States Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.15 shows a diagram of the processing states. Figure 2.16 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, interrupt, or trap instruction. Processing states Program execution state The CPU executes program instructions in sequence. Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU. Sleep mode Power-down state CPU operation is stopped to conserve power.* Software standby mode Hardware standby mode Note: * The power-down state also includes a medium-speed mode and module stop mode. See section 17, Power-Down Modes, for details. Figure 2.15 Processing States Rev.4.00 Sep. 18, 2008 Page 56 of 872 REJ09B0189-0400 Section 2 CPU End of bus request Bus request Program execution state End of bus request Bus request Bus-released state End of exception handling SLEEP instruction with SSBY = 1 SLEEP instruction with SSBY = 0 Request for exception handling Sleep mode Interrupt request Exception-handling state External interrupt RES = high MRES = high STBY = high, RES = low Manual reset state*1 Reset state Power-on reset state*1 Hardware standby mode*2 Low Power States Software standby mode Notes: 1. From any state except hardware standby mode, a transition to the power-on reset state occurs whenever RES goes low. From any state except hardware standby mode and the power-on reset state, a transition to the manual reset state occurs whenever MRES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. Figure 2.16 State Transitions 2.8.2 Reset State When the RES input goes low all current processing stops and the CPU enters the power-on reset state. When the MRES input goes low, the CPU enters the manual reset state. All interrupts are disabled in the reset state. Reset exception handling starts when the RES or MRES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, refer to section 11, Watchdog Timer (WDT). Rev.4.00 Sep. 18, 2008 Page 57 of 872 REJ09B0189-0400 Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for resets, traces, interrupts, and trap instructions. Table 2.7 indicates the types of exception handling and their priority. Trap instruction exception handling is always accepted, in the program execution state. Exception handling and the stack structure depend on the interrupt control mode set in SYSCR. Table 2.7 Priority High Exception Handling Types and Priority Type of Exception Reset Detection Timing Synchronized with clock Start of Exception Handling Exception handling starts immediately after a low-to-high transition at the RES or MRES pin, or when the watchdog timer overflows. When the trace (T) bit is set to 1, the trace starts at the end of the current instruction or current exception-handling sequence When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Exception handling starts when a trap (TRAPA) instruction is 3 executed* Trace End of instruction execution or end of exception-handling 1 sequence* End of instruction execution or end of exception-handling 2 sequence* When TRAPA instruction is executed Interrupt Trap instruction Low Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not executed at the end of the RTE instruction. 2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. 3. Trap instruction exception handling is always accepted, in the program execution state. Rev.4.00 Sep. 18, 2008 Page 58 of 872 REJ09B0189-0400 Section 2 CPU (2) Reset Exception Handling After the RES or MRES pin has gone low and the reset state has been entered, reset exception handling starts when RES or MRES goes high again. The CPU enters the power-on reset state when the RES pin is low, and the manual reset state when the MRES pin is low. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. (3) Traces Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR is set to 1. When trace mode is established, trace exception handling starts at the end of each instruction. At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode is cleared. Interrupt masks are not affected. The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to return from the trace exception-handling routine, trace mode is entered again. Trace exceptionhandling is not executed at the end of the RTE instruction. Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit. (4) Interrupt Exception Handling and Trap Instruction Exception Handling When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution starts from that start address. Figure 2.17 shows the stack after exception handling ends. Rev.4.00 Sep. 18, 2008 Page 59 of 872 REJ09B0189-0400 Section 2 CPU Normal mode*2 SP SP CCR CCR*1 PC (16 bits) EXR Reserved*1 CCR CCR*1 PC (16 bits) (a) Interrupt control mode 0 (b) Interrupt control mode 2 Advanced mode SP SP CCR PC (24 bits) EXR Reserved*1 CCR PC (24 bits) (c) Interrupt control mode 0 Notes: 1. Ignored when returning. 2. Not available in the H8S/2214 Group. (d) Interrupt control mode 2 Figure 2.17 Stack Structure after Exception Handling (Examples) Rev.4.00 Sep. 18, 2008 Page 60 of 872 REJ09B0189-0400 Section 2 CPU 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. There are two other bus masters in addition to the CPU: the DMA controller (DMAC) and data transfer controller (DTC). For further details, refer to section 6, Bus Controller. 2.8.6 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode, software standby mode, and hardware standby mode. There are also three other power-down modes: medium-speed mode, module stop mode, and subactive mode. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. For details, refer to section 17, PowerDown Modes. (1) Sleep Mode A transition to sleep mode is made if the SLEEP instruction is executed while the SSBY bit in SBYCR and the LSON bit in LPWRCR are both cleared to 0. In sleep mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU registers are retained. (2) Software Standby Mode A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, and the LSON bit in LPWRCR and the PSS bit in TCSR (WDT1) are both cleared to 0. In software standby mode, the CPU and clock halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states. (3) Hardware Standby Mode A transition to hardware standby mode is made when the STBY pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting Rev.4.00 Sep. 18, 2008 Page 61 of 872 REJ09B0189-0400 Section 2 CPU modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. 2.9 2.9.1 Basic Timing Overview The CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge of φ to the next is referred to as a “state”. The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 On-Chip Memory (ROM, RAM) On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 2.18 shows the on-chip memory access cycle. Figure 2.19 shows the pin states. Bus cycle T1 φ Internal address bus Internal read signal Internal data bus Internal write signal Write access Internal data bus Write data Read data Address Read access Figure 2.18 On-Chip Memory Access Cycle Rev.4.00 Sep. 18, 2008 Page 62 of 872 REJ09B0189-0400 Section 2 CPU Bus cycle T1 φ Address bus AS RD HWR, LWR Data bus Unchanged High High High High-impedance state Figure 2.19 Pin States during On-Chip Memory Access Rev.4.00 Sep. 18, 2008 Page 63 of 872 REJ09B0189-0400 Section 2 CPU 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.20 shows the access timing for the on-chip supporting modules. Figure 2.21 shows the pin states. Bus cycle T1 T2 φ Internal address bus Address Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Write data Read data Figure 2.20 On-Chip Supporting Module Access Cycle Rev.4.00 Sep. 18, 2008 Page 64 of 872 REJ09B0189-0400 Section 2 CPU Bus cycle T1 T2 φ Address bus Unchanged AS RD HWR, LWR High High High Data bus High-impedance state Figure 2.21 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6, Bus Controller. 2.10 2.10.1 Usage Notes TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas Technology H8S and H8/300 Series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used. Rev.4.00 Sep. 18, 2008 Page 65 of 872 REJ09B0189-0400 Section 2 CPU 2.10.2 STM/LDM Instruction Usage With the STM or LDM instruction, the ER7 register is used as the stack pointer, and thus cannot be used as a register that allows save (STM) or restore (LDM) operation. With a single STM or LDM instruction, two to four registers can be saved or restored. The available registers are as follows: For two registers: ER0 and ER1, ER2 and ER3, or ER4 and ER5 For three registers: ER0 to ER2, or ER4 to ER6 For four registers: ER0 to ER3 For the Renesas Technology H8S or H8/300 Series C/C++ Compiler, the STM/LDM instruction including ER7 is not created. 2.10.3 Bit Manipulation Instructions When a register that includes write-only bits is manipulated by a bit manipulation instruction, there are cases where the bits manipulated are not manipulated correctly or bits unrelated to the bits manipulated are changed. When a register containing write-only bits is read, the value read is either a fixed value or an undefined value. This means that the bit manipulation instructions that use the value of bits read in their operation (BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, and BILD) will not perform correct bit operations. Also, bit manipulation instructions that perform a write operation on the data read after the calculation (BSET, BCLR, BNOT, BST, and BIST) may change bits unrelated to the bits manipulated. Thus extreme care is required when performing bit manipulation instructions on registers that include write-only bits. The BSET, BCLR, BNOT, BST, and BIST instructions perform their operations in the following order. 1. Read the data in byte units 2. Perform the bit manipulation operation according to the instruction on the data read. 3. Write the data back in byte units Rev.4.00 Sep. 18, 2008 Page 66 of 872 REJ09B0189-0400 Section 2 CPU Example: Using the BCLR instruction to clear only P14 in the port 1 P1DDR register. The P1DDR register consists of 8 write-only bits and sets the I/O direction of the port 1 pins. Reading this register is invalid. When read, the values returned are undefined. Here we present an example in which P14 is specified to be an input port using the BCLR instruction. Currently, P17 to 14 are set to be output pins and P13 to P10 are set to be input pins. At this point, the value of P1DDR is H'F0. P17 I/O P1DDR Output 1 P16 Output 1 P15 Output 1 P14 Output 1 P13 Input 0 P12 Input 0 P11 Input 0 P10 Input 0 To switch P14 from the Output pin to the input pin function, the value of P1DDR bit 4 must be changed from 1 to 0 (H'F0 → H'E0). Here we assume that the BCLR instruction is used to clear P1DDR bit 4. BCLR #4, @P1DDR However if a bit manipulation instruction of the type shown above is used on P1DDR, which is a write-only register, the following problem may occur. Although the first thing that happens is that data is read from P1DDR in byte units, the value read at this time is undefined. An undefined value is a value that is either 0 or 1 in the register but reads out as an arbitrary value whose relationship to the actual value is unknown. Since the P1DDR bits are all write-only bits, every bit reads out as an undefined value. Although the actual value of P1DDR at this point is H'F0, assume that bit 3 becomes a 1 here, and the value read out is H'F8. P17 I/O P1DDR Read value Output 1 1 P16 Output 1 1 P15 Output 1 1 P14 Output 1 1 P13 Input 0 1 P12 Input 0 0 P11 Input 0 0 P10 Input 0 0 Rev.4.00 Sep. 18, 2008 Page 67 of 872 REJ09B0189-0400 Section 2 CPU The bit manipulation operation is performed on this value that was read. In this example, bit 4 will be cleared for H'F8. P17 I/O P1DDR After bit manipulation Output 1 1 P16 Output 1 1 P15 Output 1 1 P14 Output 1 0 P13 Input 0 1 P12 Input 0 0 P11 Input 0 0 P10 Input 0 0 After the bit manipulation operation, this data will be written to P1DDR, and the BCLR instruction completes. P17 I/O P1DDR Write value Output 1 1 P16 Output 1 1 P15 Output 1 1 P14 Input 0 0 P13 Output 1 1 P12 Input 0 0 P11 Input 0 0 P10 Input 0 0 Although the instruction was expected to write H'E0 back to P1DDR, it actually wrote H'E8, and P13, which was expected to be an input pin, is changed to function as an output pin. While this section described the case where P13 was read out as a 1, since the values read are undefined when P17 to P10 are read, when this bit manipulation instruction completes, bits that were 0 may be changed to 1, and bits that were 1 may be changed to 0. To avoid this sort of problem, see section 2.10.4, Access Methods for Registers with Write-Only Bits for methods for modifying registers that include write-only bits. Also note that it is possible to use the BCLR instruction to clear to 0 flags in internal I/O registers. In this case, if it is clear from the interrupt handler or other information that the corresponding flag is set to 1, then there is no need to read the value of the corresponding flag in advance. 2.10.4 Access Methods for Registers with Write-Only Bits Undefined values will be read out if a data transfer instruction is executed for a register that includes write-only bits, or if a bit manipulation instruction is executed for a register that includes write-only bits. To avoid reading undefined values, use methods such as those shown below to access registers that include write-only bits. The basic method for writing to a register that includes write-only bits is to create a work area in internal RAM or other memory area and first write the data to that area. Then, perform the desired access operation for that memory and finally write that data to the register that includes write-only bits. Rev.4.00 Sep. 18, 2008 Page 68 of 872 REJ09B0189-0400 Section 2 CPU Write data to the work area Initial value write Write the work area data to the register that includes write-only bits Access the work area data (data transfer and bit manipulation instructions can be used) Modifying the value of a register that includes write-only bits Write the work area data to the register that includes write-only bits Figure 2.22 Flowchart for Access Methods for Registers that Include Write-Only Bits Example: To clear only P14 in the port 1 P1DDR The P1DDR register consists of 8 write-only bits and sets the I/O direction of the port 1 pins. Reading this register is invalid. When read, the values returned are undefined. Here we present an example in which P14 is specified to be an input port using the BCLR instruction. First, we write the initial value H'F0 written to P1DDR to the work area in RAM (RAM0). MOV.B MOV.B MOV.B #H'F0, R0L, R0L, R0L @PAM0 @P1DDR P17 I/O P1DDR RAM0 Output 1 1 P16 Output 1 1 P15 Output 1 1 P14 Output 1 1 P13 Input 0 0 P12 Input 0 0 P11 Input 0 0 P10 Input 0 0 Rev.4.00 Sep. 18, 2008 Page 69 of 872 REJ09B0189-0400 Section 2 CPU To switch P14 from being an output pin to being an input pin, we must change the value of P1DDR bit 4 from 1 to 0 (H'F0 → H'E0). Here, were execute a BCLR instruction for RAM0. BCLR I/O P1DDR RAM0 #4, @RAM0 P17 Output 1 1 P16 Output 1 1 P15 Output 1 1 P14 Output 1 0 P13 Input 0 0 P12 Input 0 0 P11 Input 0 0 P10 Input 0 0 Since RAM0 can be read and written, when the bit manipulation instruction is executed, only bit 4 in RAM0 is cleared. Then we write this RAM0 value to P1DDR. MOV.B MOV.B @RAM0, R0L, P17 I/O P1DDR RAM0 Output 1 1 R0L @P1DDR P16 Output 1 1 P15 Output 1 1 P14 Input 0 0 P13 Input 0 0 P12 Input 0 0 P11 Input 0 0 P10 Input 0 0 If this procedure is used to write registers that include write-only bits, programs can be written without depending on the type of the instructions used. Rev.4.00 Sep. 18, 2008 Page 70 of 872 REJ09B0189-0400 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 3.1.1 Overview Operating Mode Selection The H8S/2214 Group has four operating modes (modes 4 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD2 to MD0). Table 3.1 lists the MCU operating modes. Table 3.1 MCU Operating Mode Selection External Data Bus On-Chip ROM — Initial Width — Max. Width CPU MCU Operating Operating Description Mode MD2 MD1 MD0 Mode 0* 1* 2* 3* 4 5 6 7 1 1 0 0 0 1 0 1 0 1 0 1 0 1 — — Advanced On-chip ROM disabled, Disabled expanded mode On-chip ROM enabled, Enabled expanded mode Single-chip mode 16 bits 8 bits 8 bits — 16 bits 16 bits 16 bits Note: * Not available in the H8S/2214 Group. The CPU’s architecture allows for 4 Gbytes of address space, but the H8S/2214 Group actually accesses a maximum of 16 Mbytes. Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. Rev.4.00 Sep. 18, 2008 Page 71 of 872 REJ09B0189-0400 Section 3 MCU Operating Modes Note that the functions of each pin depend on the operating mode. The H8S/2214 Group can be used only in modes 4 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.2 Register Configuration The H8S/2214 Group has a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) that controls the operation of the H8S/2214 Group. Table 3.2 summarizes these registers. Table 3.2 Name Mode control register System control register MCU Registers Abbreviation MDCR SYSCR R/W R R/W Initial Value Undetermined H'01 Address* H'FDE7 H'FDE5 Note: * Lower 16 bits of the address. 3.2 3.2.1 Bit Register Descriptions Mode Control Register (MDCR) : 7 — 1 — 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 MDS2 —* R 1 MDS1 —* R 0 MDS0 —* R Initial value: R/W : Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2214 Group. Bit 7—Reserved: Read-only bit, always read as 1. Bits 6 to 3—Reserved: Read-only bits, always read as 0. Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are read-only bits-they cannot be written to. The mode pin (MD2 to MD0) input Rev.4.00 Sep. 18, 2008 Page 72 of 872 REJ09B0189-0400 Section 3 MCU Operating Modes levels are latched into these bits when MDCR is read. These latches are canceled by a power-on reset, but are retained after a manual reset. 3.2.2 Bit System Control Register (SYSCR) : 7 — 0 R/W 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 MRESE 0 R/W 1 — 0 — 0 RAME 1 R/W Initial value: R/W : SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, the detected edge for NMI, and enables or disables MRES pin input and on-chip RAM. SYSCR is initialized to H'01 by a power-on reset and in hardware standby mode. In a manual reset, the INTM1, INTM0, NMIEG, and RAME bits are initialized, but the MRESE bit is not. SYSCR is not initialized in software standby mode. Bit 7—Reserved: Only 0 should be written to this bit. Bit 6—Reserved: Read-only bit, always read as 0. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and Interrupt Operation. Bit 5 INTM1 0 1 Bit 4 INTM0 0 1 0 1 Interrupt Control Mode 0 — 2 — Description Control of interrupts by I bit Setting prohibited Control of interrupts by I2 to I0 bits and IPR Setting prohibited (Initial value) Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input. Bit 3 NMIEG 0 1 Description An interrupt is requested at the falling edge of NMI input An interrupt is requested at the rising edge of NMI input (Initial value) Rev.4.00 Sep. 18, 2008 Page 73 of 872 REJ09B0189-0400 Section 3 MCU Operating Modes Bit 2—Manual Reset Select (MRESE): Enables or disables the MRES pin. Table 3.3 shows the relationship between the RES and MRES pin values and type of reset. For details of resets, see section 4.2, Resets. Bit 2 MRESE 0 1 Description Manual reset is disabled P74/MRES pin can be used as P74 I/O pin Manual reset is enabled P74/MRES pin can be used as MRES input pin (Initial value) Table 3.3 RES 0 1 1 Relationship between RES and MRES pin Values and Type of Reset Pins MRES * 0 1 Type of Reset Power-on reset Manual reset Operating state *: Don’t care Bit 1—Reserved: Read-only bit, always read as 0. Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset status is released. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) Note: When the DTC is used, the RAME bit should not be cleared to 0. Rev.4.00 Sep. 18, 2008 Page 74 of 872 REJ09B0189-0400 Section 3 MCU Operating Modes 3.3 3.3.1 Operating Mode Descriptions Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Pins P13 to P10, and ports A, B, and C function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. Pins P13 to P11 function as input ports immediately after a reset. Address (A23 to A21) output can be enabled or disabled by bits AE3 to AE0 in the pin function control register (PFCR) regardless of the corresponding data direction register (DDR) values. Pin 10 and ports A and B function as address (A20 to A8) outputs immediately after a reset. Address output can be enabled or disabled by bits AE3 to AE0 in PFCR regardless of the corresponding DDR values. Pins for which address output is disabled among pins P13 to P10 and in ports A and B become port outputs when the corresponding DDR bits are set to 1. Port C always has an address (A7 to A0) output function. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. 3.3.2 Mode 5 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Pins P13 to P10, and ports A, B, and C function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. Pins P13 to P11 function as input ports immediately after a reset. Address (A23 to A21) output can be enabled or disabled by bits AE3 to AE0 in the pin function control register (PFCR) regardless of the corresponding data direction register (DDR) values. Pin 10 and ports A and B function as address (A20 to A8) outputs immediately after a reset. Address output can be enabled or disabled by bits AE3 to AE0 in PFCR regardless of the corresponding DDR values. Pins for which address output is disabled among pins P13 to P10 and in ports A and B become port outputs when the corresponding DDR bits are set to 1. Port C always has an address (A7 to A0) output function. Rev.4.00 Sep. 18, 2008 Page 75 of 872 REJ09B0189-0400 Section 3 MCU Operating Modes The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.3 Mode 6 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Pins P13 to P10, and ports A and B function as input ports immediately after a reset. Address (A23 to A8) output can be enabled or disabled by bits AE3 to AE0 in the pin function control register (PFCR) regardless of the corresponding data direction register (DDR) values. Pins for which address output is disabled among pins P13 to P10 and in ports A and B become port outputs when the corresponding DDR bits are set to 1. Ports D and E function as a data bus, and part of port F carries data bus signals. Port C is an input port immediately after a reset. Addresses A7 to A0 are output by setting the corresponding DDR bits to 1. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.4 Mode 7 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. Rev.4.00 Sep. 18, 2008 Page 76 of 872 REJ09B0189-0400 Section 3 MCU Operating Modes 3.4 Pin Functions in Each Operating Mode The pin functions of ports 1, and A to F vary depending on the operating mode. Table 3.4 shows their functions in each operating mode. Table 3.4 Port Port 1 P13 to P11 P10 Port A Port B Port C Port D Port E Port F PF7 PF6 to PF4 PF3 PF2 to PF0 Legend: P: I/O port A: Address bus output D: Data bus I/O C: Control signals, clock I/O *: After reset PA3 to PA0 Pin Functions in Each Mode Mode 4 P*/A P/A* P/A* P/A* A D P/D* P/C* C P/C* P*/C Mode 5 P*/A P/A* P/A* P/A* A D P*/D P/C* C P*/C P*/C Mode 6 P*/A P*/A P*/A P*/A P*/A D P*/D P/C* C P*/C P*/C Mode 7 P P P P P P P P*/C P 3.5 Memory Map in Each Operating Mode The H8S/2214 memory map is shown in figure 3.1. The address space is 16 Mbytes in modes 4 to 7 (advanced modes). The address space is divided into eight areas for modes 4 to 7. For details, see section 6, Bus Controller. Rev.4.00 Sep. 18, 2008 Page 77 of 872 REJ09B0189-0400 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 External address space On-chip ROM On-chip ROM H'01FFFF H'020000 H'FFB000 H'FFC000 On-chip RAM* H'FFEFC0 External address space External address space Reserved area* On-chip RAM* H'FFC000 H'FFEFBF On-chip RAM Reserved area* H'FFB000 H'FFC000 H'FFEFC0 External address space H'FFF800 Internal I/O registers H'FFFF40 External address space H'FFF800 Internal I/O registers H'FFFF40 External address space H'FFF800 Internal I/O registers H'FFFF3F H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM H'FFFFFF H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.1 Memory Map in Each Operating Mode in the H8S/2214 Rev.4.00 Sep. 18, 2008 Page 78 of 872 REJ09B0189-0400 Section 4 Exception Handling Section 4 Exception Handling 4.1 4.1.1 Overview Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times, in the program execution state. Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR. Table 4.1 Priority High Exception Handling Types and Priority Exception Handling Type Reset Start of Exception Handling Starts immediately after a low-to-high transition at the RES or MRES pin, or when the watchdog timer overflows. The CPU enters the power-on reset state when the RES pin is low, and the manual reset state when the MRES pin is low. Starts when execution of the current instruction or exception handling ends, if the trace (T) bit is set to 1 Starts when execution of the current instruction or exception handling ends, if an interrupt request has 2 been issued* 3 1 Trace* Interrupt Low Trap instruction (TRAPA)* Started by execution of a trap instruction (TRAPA) Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in program execution state. Rev.4.00 Sep. 18, 2008 Page 79 of 872 REJ09B0189-0400 Section 4 Exception Handling 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out. 4.1.3 Exception Sources and Vector Table The exception sources are classified as shown in figure 4.1. Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Reset Trace Exception sources Direct transition Power-on reset Manual reset External interrupts: NMI, IRQ7 to IRQ0 Interrupts External expansion interrupts: EXIRQ7 to EXIRQ0 Internal interrupts: 31 interrupt sources Trap instruction Figure 4.1 Exception Sources Rev.4.00 Sep. 18, 2008 Page 80 of 872 REJ09B0189-0400 Section 4 Exception Handling Table 4.2 Exception Vector Table Vector Address* 1 Exception Source Power-on reset Manual reset Reserved for system use Vector Number 0 1 2 3 4 Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063 ⎜ H'01BC to H'01BF Trace Direct transition External interrupt NMI Trap instruction (4 sources) 5 6 7 8 9 10 11 Reserved for system use 12 13 14 15 External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 16 17 18 19 20 21 22 23 24 ⎜ 111 2 Internal interrupt* Notes: 1. Lower 16 bits of the address. 2. For details of internal interrupt vectors, see section 5.3.3, Interrupt Exception Handling Vector Table. Rev.4.00 Sep. 18, 2008 Page 81 of 872 REJ09B0189-0400 Section 4 Exception Handling 4.2 4.2.1 Reset Overview A reset has the highest exception priority. When the RES or MRES pin goes low, all processing halts and the H8S/2214 enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the RES or MRES pin changes from low to high. The levels of the RES and MRES pins at reset determine whether a power-on reset or a manual reset is effected. The H8S/2214 can also be reset by overflow of the watchdog timer. For details see section 11, Watchdog Timer (WDT). 4.2.2 Reset Types A reset can be of either of two types: a power-on reset or a manual reset. Reset types are shown in table 4.3. A power-on reset should be used when powering on. The internal state of the CPU is initialized by either type of reset. A power-on reset also initializes all the registers in the on-chip supporting modules, while a manual reset initializes all the registers in the on-chip supporting modules except for the bus controller and I/O ports, which retain their previous states. With a manual reset, since the on-chip supporting modules are initialized, ports used as on-chip supporting module I/O pins are switched to I/O ports controlled by DDR and DR. Table 4.3 Reset Types Reset Transition Conditions Type Power-on reset Manual reset MRES * Low RES Low High CPU Initialized Initialized Internal State On-Chip Supporting Modules Initialized Initialized, except for bus controller and I/O ports *: Don’t care Rev.4.00 Sep. 18, 2008 Page 82 of 872 REJ09B0189-0400 Section 4 Exception Handling A reset caused by the watchdog timer can also be of either of two types: a power-on reset or a manual reset. When the MRES pin is used, MRES pin input must be enabled by setting the MRESE bit to 1 in SYSCR. 4.2.3 Reset Sequence The H8S/2214 Group enters the reset state when the RES or MRES pin goes low. To ensure that the H8S/2214 Group is reset, hold the RES or MRES pin low for at least 20 ms at power-up. To reset the H8S/2214 Group during operation, hold the RES or MRES pin low for at least 20 states. When the RES or MRES pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip supporting modules are initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4.2 and 4.3 show examples of the reset sequence. Rev.4.00 Sep. 18, 2008 Page 83 of 872 REJ09B0189-0400 Section 4 Exception Handling Vector Internal Prefetch of first program fetch processing instruction φ RES, MRES Internal address bus Internal read signal Internal write signal Internal data bus (2) (1) (3) High (4) (1) Reset exception handling vector address (for a power-on reset, (1) = H'0000; for a manual reset, (1) = H'0002) (2) Start address (contents of reset exception handling vector address) (3) Start address ((3) = (2)) (4) First program instruction Figure 4.2 Reset Sequence (Modes 2 and 3: Not available in the H8S/2214) Rev.4.00 Sep. 18, 2008 Page 84 of 872 REJ09B0189-0400 Section 4 Exception Handling Vector fetch Internal Prefetch of first processing program instruction * * φ RES, MRES Address bus RD HWR, LWR D15 to D0 * (1) (3) (5) High (2) (4) (6) (1) (3) Reset exception handling vector address (for a power-on reset, (1) = H'000000, (3) = H'000002; for a manual reset, (1) = H'000004, (3) = H'000006) (2) (4) Start address (contents of reset exception handling vector address) (5) Start address ((5) = (2) (4)) (6) First program instruction Note: * Three program wait states are inserted. Figure 4.3 Reset Sequence (Mode 4) 4.2.4 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx:32, SP). 4.2.5 State of On-Chip Supporting Modules after Reset Release After reset release, MSTPCRA is initialized to H'3F, MSTPCRB and MSTPCRC are initialized to H'FF, and all modules except the DMAC and DTC enter module stop mode. Consequently, onchip supporting module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited. Rev.4.00 Sep. 18, 2008 Page 85 of 872 REJ09B0189-0400 Section 4 Exception Handling 4.3 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking. Table 4.4 shows the state of CCR and EXR after execution of trace exception handling. Interrupts are accepted even within the trace exception handling routine. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Table 4.4 Status of CCR and EXR after Trace Exception Handling CCR Interrupt Control Mode 0 2 1 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution. I UI I2 to I0 EXR T Trace exception handling cannot be used. — — 0 Rev.4.00 Sep. 18, 2008 Page 86 of 872 REJ09B0189-0400 Section 4 Exception Handling 4.4 Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0), eight external expansion sources (EXIRQ7 to EXIRQ0), and 31 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), 16-bit timer-pulse unit (TPU), serial communication interface (SCI), data transfer controller (DTC), and DMA controller (DMAC). Each interrupt source has a separate vector address. NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. For details of interrupts, see section 5, Interrupt Controller. External interrupts NMI (1) IRQ7 to IRQ0 (8) Interrupts External expansion interrupts: EXIRQ7 to EXIRQ0 (8) Internal interrupts WDT* (1) TPU (13) SCI (12) DTC (1) DMAC (4) Notes: Numbers in parentheses are the numbers of interrupt sources. * When the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. Figure 4.4 Interrupt Sources and Number of Interrupts Rev.4.00 Sep. 18, 2008 Page 87 of 872 REJ09B0189-0400 Section 4 Exception Handling 4.5 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.5 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.5 Status of CCR and EXR after Trap Instruction Exception Handling CCR Interrupt Control Mode 0 2 I 1 1 UI — — I2 to I0 — — EXR T — 0 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution. Rev.4.00 Sep. 18, 2008 Page 88 of 872 REJ09B0189-0400 Section 4 Exception Handling 4.6 Stack Status after Exception Handling Figures 4.5 and 4.6 show the stack after completion of trap instruction exception handling and interrupt exception handling. SP SP CCR CCR* PC (16 bits) EXR Reserved* CCR CCR* PC (16 bits) (a) Interrupt control mode 0 Note: * Ignored on return. (b) Interrupt control mode 2 Figure 4.5 Stack Status after Exception Handling (Normal Modes: Not available in the H8S/2214) SP SP CCR PC (24 bits) EXR Reserved* CCR PC (24 bits) (a) Interrupt control mode 0 Note: * Ignored on return. (b) Interrupt control mode 2 Figure 4.6 Stack Status after Exception Handling (Advanced Modes) Rev.4.00 Sep. 18, 2008 Page 89 of 872 REJ09B0189-0400 Section 4 Exception Handling 4.7 Notes on Use of the Stack When accessing word data or longword data, the H8S/2214 Group assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.7 shows an example of what happens when the SP value is odd. CCR SP PC SP R1L PC H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFF SP TRAP instruction executed MOV.B R1L, @–ER7 SP set to H'FFFEFF Data saved above SP Contents of CCR lost Legend: CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4.7 Operation when SP Value Is Odd Rev.4.00 Sep. 18, 2008 Page 90 of 872 REJ09B0189-0400 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 5.1.1 Overview Features The H8S/2214 Group controls interrupts by means of an interrupt controller. The interrupt controller has the following features: • Two interrupt control modes ⎯ Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with IPR ⎯ An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. ⎯ NMI is assigned the highest priority level of 8, and can be accepted at all times. • Independent vector addresses ⎯ All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. • Nine external interrupts ⎯ NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. ⎯ Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ7 to IRQ0. • DTC or DMAC control ⎯ DTC or DMAC activation is performed by means of interrupts. • Eight external expansion interrupt input pins Rev.4.00 Sep. 18, 2008 Page 91 of 872 REJ09B0189-0400 Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5.1. INTM1 INTM0 SYSCR NMIEG NMI input IRQ input NMI input unit IRQ input unit ISR ISCR IER Priority determination I I2 to I0 Interrupt request Vector number CPU Internal interrupt request SWDTEND to TEI2 External expansion interrupt sources EXIRQ0 to EXIRQ7 Interrupt controller IPR CCR EXR Legend: ISCR: IER: ISR: IPR: SYSCR: IRQ sense control register IRQ enable register IRQ status register Interrupt priority register System control register Figure 5.1 Block Diagram of Interrupt Controller Rev.4.00 Sep. 18, 2008 Page 92 of 872 REJ09B0189-0400 Section 5 Interrupt Controller 5.1.3 Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Name Nonmaskable interrupt External interrupt requests 7 to 0 External expansion interrupt sources 7 to 0 Interrupt Controller Pins Symbol NMI I/O Input Function Nonmaskable external interrupt; rising or falling edge can be selected Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected Interrupts from external expansion modules. Interrupt is accepted on low level. IRQ7 to IRQ0 Input EXIRQ7 to EXIRQ0 Input 5.1.4 Register Configuration Table 5.2 summarizes the registers of the interrupt controller. Table 5.2 Name System control register IRQ sense control register H IRQ sense control register L IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register F Interrupt priority register G Interrupt priority register J Interrupt priority register K Interrupt priority register M Interrupt Controller Registers Abbreviation SYSCR ISCRH ISCRL IER ISR IPRA IPRB IPRC IPRD IPRF IPRG IPRJ IPRK IPRM R/W R/W R/W R/W R/W 2 R/(W)* Initial Value H'01 H'00 H'00 H'00 H'00 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 1 Address* H'FDE5 H'FE12 H'FE13 H'FE14 H'FE15 H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC5 H'FEC6 H'FEC9 H'FECA H'FECC R/W R/W R/W R/W R/W R/W R/W R/W R/W Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. Rev.4.00 Sep. 18, 2008 Page 93 of 872 REJ09B0189-0400 Section 5 Interrupt Controller 5.2 5.2.1 Bit Register Descriptions System Control Register (SYSCR) : 7 — 0 R/W 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 MRESE 0 R/W 1 — 0 — 0 RAME 1 R/W Initial value: R/W : SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control Register (SYSCR). SYSCR is initialized to H'01 by a power-on reset and in hardware standby mode. In a manual reset, the INTM1, INTM0, NMIEG, and RAME bits are initialized, but the MRESE bit is not. SYSCR is not initialized in software standby mode. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes for the interrupt controller. Bit 5 INTM1 0 1 Bit 4 INTM0 0 1 0 1 Interrupt Control Mode 0 — 2 — Description Interrupts are controlled by I bit Setting prohibited Interrupts are controlled by bits I2 to I0, and IPR Setting prohibited (Initial value) Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. Bit 3 NMIEG 0 1 Description Interrupt request generated at falling edge of NMI input Interrupt request generated at rising edge of NMI input (Initial value) Rev.4.00 Sep. 18, 2008 Page 94 of 872 REJ09B0189-0400 Section 5 Interrupt Controller 5.2.2 Interrupt Priority Registers A to D, F, G, J, K, M (IPRA to IPRD, IPRF, IPRG, IPRJ, IPRK, IPRM) Bit : 7 — 0 — 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W 3 — 0 — 2 IPR2 1 R/W 1 IPR1 1 R/W 0 IPR0 1 R/W Initial value: R/W : The IPR registers are nine 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between IPR settings and interrupt sources is shown in table 5.3. The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI. The IPR registers are initialized to H'77 by a reset and in hardware standby mode. They are not initialized in software standby mode. Bits 7 and 3—Reserved: Read-only bits, always read as 0. Table 5.3 Correspondence between Interrupt Sources and IPR Settings Bits Register IPRA IPRB IPRC IPRD IPRF IPRG IPRJ IPRK IPRM 6 to 4 IRQ0 IRQ2 IRQ3 IRQ6 IRQ7 Watchdog timer 0 TPU channel 0 TPU channel 2 DMAC SCI channel 1 EXIRQ3 to EXIRQ0 2 to 0 IRQ1 IRQ4 IRQ5 DTC —* TPU channel 1 — SCI channel 0 SCI channel 2 EXIRQ7 to EXIRQ4 Note: * Reserved bits. These bits cannot be modified and are always read as 1. Rev.4.00 Sep. 18, 2008 Page 95 of 872 REJ09B0189-0400 Section 5 Interrupt Controller As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority level, level 7, by setting H'7. When interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to the CPU. 5.2.3 Bit IRQ Enable Register (IER) : 7 IRQ7E 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W Initial value: R/W : IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ7 to IRQ0. IER is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to IRQ0 are enabled or disabled. Bit n IRQnE 0 1 Description IRQn interrupts disabled IRQn interrupts enabled (n = 7 to 0) (Initial value) Rev.4.00 Sep. 18, 2008 Page 96 of 872 REJ09B0189-0400 Section 5 Interrupt Controller 5.2.4 ISCRH Bit IRQ Sense Control Registers H and L (ISCRH, ISCRL) : 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value: R/W : ISCRL Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value: R/W : The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0. The ISCR registers are initialized to H'0000 by a reset and in hardware standby mode. They are not initialized in software standby mode. Bits 15 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB) Bits 15 to 0 IRQ7SCB to IRQ0SCB 0 IRQ7SCA to IRQ0SCA 0 1 1 0 1 Description Interrupt request generated at IRQ7 to IRQ0 input low level (initial value) Interrupt request generated at falling edge of IRQ7 to IRQ0 input Interrupt request generated at rising edge of IRQ7 to IRQ0 input Interrupt request generated at both falling and rising edges of IRQ7 to IRQ0 input Rev.4.00 Sep. 18, 2008 Page 97 of 872 REJ09B0189-0400 Section 5 Interrupt Controller 5.2.5 Bit IRQ Status Register (ISR) : 7 IRQ7F 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* Initial value: R/W : Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0—IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests. Bit n IRQnF 0 Description [Clearing conditions] • • • • 1 (Initial value) Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high When IRQn interrupt exception handling is executed when falling, rising, or bothedge detection is set (IRQnSCB = 1 or IRQnSCA = 1) When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA = 0) When a falling edge occurs in IRQn input when falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1) When a rising edge occurs in IRQn input when rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0) When a falling or rising edge occurs in IRQn input when both-edge detection is set (IRQnSCB = IRQnSCA = 1) (n = 7 to 0) [Setting conditions] • • • • Rev.4.00 Sep. 18, 2008 Page 98 of 872 REJ09B0189-0400 Section 5 Interrupt Controller 5.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (53 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ2 to IRQ0 can be used to restore the H8S/2214 Group from software standby mode. (1) NMI Interrupt NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. The vector number for NMI interrupt exception handling is 7. (2) IRQ7 to IRQ0 Interrupts Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to IRQ0 have the following features: • Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ7 to IRQ0. • Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER. • The interrupt priority level can be set with IPR. • The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. A block diagram of interrupts IRQn is shown in figure 5.2. Rev.4.00 Sep. 18, 2008 Page 99 of 872 REJ09B0189-0400 Section 5 Interrupt Controller IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input Clear signal Note: n = 7 to 0 IRQn interrupt S R Q request Figure 5.2 Block Diagram of Interrupts IRQn Figure 5.3 shows the timing of setting IRQnF. φ IRQn input pin IRQnF Note: n = 7 to 0 Figure 5.3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as an I/O pin for another function. Since interrupt request flags IRQ7F to IRQ0F are set when the setting condition is satisfied, regardless of the IER setting, only the necessary flags should be referenced. (3) EXIRQ7 to EXIRQ0 Interrupts Interrupts EXIRQ7 to EXIRQ0 are for use by external expansion modules. An interrupt is requested by a low-level input signal at one of pins EXIRQ7 to EXIRQ0. Rev.4.00 Sep. 18, 2008 Page 100 of 872 REJ09B0189-0400 Section 5 Interrupt Controller 5.3.2 Internal Interrupts There are 31 sources for internal interrupts from on-chip supporting modules. • For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. • The interrupt priority level can be set by means of IPR. • The DMAC and DTC can be activated by a TPU, 8-bit timer, SCI, or other interrupt request. When the DMAC and DTC is activated by an interrupt, the interrupt control mode and interrupt mask bits are not affected. 5.3.3 Interrupt Exception Handling Vector Table Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of the IPR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5.4. Rev.4.00 Sep. 18, 2008 Page 101 of 872 REJ09B0189-0400 Section 5 Interrupt Controller Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address* Vector Number 7 16 17 18 19 20 21 22 23 24 25 32 33 34 35 36 — 37 38 39 Advanced Mode H'001C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C H'0060 H'0064 H'0080 H'0084 H'0088 H'008C H'0090 H'0094 H'0098 H'009C IPRA6 to IPRA 4 IPRA2 to IPRA 0 IPRB6 to IPRB 4 IPRB2 to IPRB 0 IPRC6 to IPRC 4 IPRC2 to IPRC 0 IPRD6 to IPRD 4 IPRF6 to IPRF 4 IPR Priority High Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Origin of Interrupt Source External pin SWDTEND DTC (software activation interrupt end) WOVI0 (interval timer) TGI0A (TGR0A input capture/compare match) TGI0B (TGR0B input capture/compare match) TGI0C (TGR0C input capture/compare match) TGI0D (TGR0D input capture/compare match) TCI0V (overflow 0) Reserved Watchdog timer 0 TPU channel 0 Low Note: * Lower 16 bits of the start address. Rev.4.00 Sep. 18, 2008 Page 102 of 872 REJ09B0189-0400 Section 5 Interrupt Controller Vector Address* Vector Number 40 41 42 43 TPU channel 2 44 45 46 47 72 73 74 75 80 81 82 83 84 85 86 87 88 89 90 91 104 105 106 107 108 109 110 111 Advanced Mode H'00A0 H'00A4 H'00A8 H'00AC H'00B0 H'00B4 H'00B8 H'00BC H'0120 H'0124 H'0128 H'012C H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C H'01A0 H'01A4 H'01A8 H'01AC H'01B0 H'01B4 H'01B8 H'01DC IPRJ2 to IPRJ 0 IPRJ6 to IPRJ4 IPRG6 to IPRG 4 IPR IPRF2 to IPRF 0 Priority High Interrupt Source TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow 2) TCI2U (underflow 2) Origin of Interrupt Source TPU channel 1 DEND0A (channel 0/channel 0A DMAC transfer end) DEND0B (channel 0B transfer end) DEND1A (channel 1/channel 1A transfer end) DEND1B (channel 1B transfer end) ERI0 (receive error 0) RXI0 (reception completed 0) TXI0 (transmit data empty 0) TEI0 (transmission end 0) ERI1 (receive error 1) RXI1 (reception completed 1) TXI1 (transmit data empty 1) TEI1 (transmission end 1) ERI2 (receive error 2) RXI2 (reception completed 2) TXI2 (transmit data empty 2) TEI2 (transmission end 2) EXIRQ0 EXIRQ1 EXIRQ2 EXIRQ3 EXIRQ4 EXIRQ5 EXIRQ6 EXIRQ7 Note: * Lower 16 bits of the start address. SCI channel 0 SCI channel 1 IPRK6 to IPRK 4 SCI channel 2 IPRK2 to IPRK 0 External module IPRM6 to IPRM4 IPRM2 to IPRM0 Low Rev.4.00 Sep. 18, 2008 Page 103 of 872 REJ09B0189-0400 Section 5 Interrupt Controller 5.4 5.4.1 Interrupt Operation Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2214 Group differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 5.5 shows the interrupt control modes. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated by the I and UI bits in the CPU’s CCR, and bits I2 to I0 in EXR. Table 5.5 Interrupt Control Modes Interrupt Mask Bits Description I — I2 to I0 Interrupt mask control is performed by the I bit. Setting prohibited 8-level interrupt mask control is performed by bits I2 to I0. 8 priority levels can be set with IPR. Setting prohibited SYSCR Interrupt Priority Setting Control Mode INTM1 INTM0 Registers 0 — 2 1 0 0 1 0 — — IPR — 1 — — Rev.4.00 Sep. 18, 2008 Page 104 of 872 REJ09B0189-0400 Section 5 Interrupt Controller Figure 5.4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 I Interrupt acceptance control Interrupt source Default priority determination 8-level mask control Vector number IPR I2 to I0 Interrupt control mode 2 Figure 5.4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5.6 shows the interrupts selected in each interrupt control mode. Table 5.6 Interrupts Selected in Each Interrupt Control Mode (1) Interrupt Mask Bits Interrupt Control Mode 0 2 I 0 1 * Selected Interrupts All interrupts NMI interrupts All interrupts *: Don't care (2) 8-Level Control In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). Rev.4.00 Sep. 18, 2008 Page 105 of 872 REJ09B0189-0400 Section 5 Interrupt Controller The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level. Table 5.7 Interrupts Selected in Each Interrupt Control Mode (2) Selected Interrupts All interrupts Highest-priority-level (IPR) interrupt whose priority level is greater than the mask level (IPR > I2 to I0). Interrupt Control Mode 0 2 (3) Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5.8 shows operations and control signal functions in each interrupt control mode. Table 5.8 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Acceptance Control I 8-Level Control I2 to I0 IPR Default Priority Determination 2 Interrupt Setting Control Mode INTM1 INTM0 T (Trace) 0 0 0 IM 1 2 1 0 X —* Legend: : Interrupt operation control performed X : No operation. (All interrupts enabled) IM : Used as interrupt mask bit PR : Sets priority. — : Not used. Notes: 1. Set to 1 when interrupt is accepted. 2. Keep the initial setting. X — IM —* PR — T Rev.4.00 Sep. 18, 2008 Page 106 of 872 REJ09B0189-0400 Section 5 Interrupt Controller 5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. [3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. Rev.4.00 Sep. 18, 2008 Page 107 of 872 REJ09B0189-0400 Section 5 Interrupt Controller Program execution status Interrupt generated? Yes Yes No NMI No No I=0 Yes Hold pending No IRQ0 Yes No IRQ1 Yes EXIRQ7 Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev.4.00 Sep. 18, 2008 Page 108 of 872 REJ09B0189-0400 Section 5 Interrupt Controller 5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5.6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.4 is selected. [3] Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. Rev.4.00 Sep. 18, 2008 Page 109 of 872 REJ09B0189-0400 Section 5 Interrupt Controller Program execution status Interrupt generated? Yes Yes NMI No No No Level 7 interrupt? Yes Mask level 6 or below? Yes Level 6 interrupt? No Yes Mask level 5 or below? Yes No Level 1 interrupt? No Yes No Mask level 0? Yes No Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev.4.00 Sep. 18, 2008 Page 110 of 872 REJ09B0189-0400 5.4.4 Interrupt acceptance Instruction prefetch Stack Vector fetch Internal operation Internal operation Interrupt service routine instruction prefetch Interrupt level determination Wait for end of instruction φ Interrupt request signal Internal address bus (1) (7) (9) (11) (3) (5) (13) Interrupt Exception Handling Sequence Internal read signal Internal write signal (2) (8) (10) Internal data us (4) (6) (12) (14) Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Figure 5.7 Interrupt Exception Handling (6) (8) Saved PC and saved CCR (9) (11) Vector address (10) (12) Interrupt handling routine start address (vector address contents) (13) Interrupt handling routine start address ((13) = (10) (12)) (14) First instruction of interrupt handling routine Rev.4.00 Sep. 18, 2008 Page 111 of 872 REJ09B0189-0400 Section 5 Interrupt Controller (1) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address) (2) (4) Instruction code (Not executed) (3) Instruction prefetch address (Not executed) (5) SP-2 (7) SP-4 Section 5 Interrupt Controller 5.4.5 Interrupt Response Times The H8S/2214 Group is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling highspeed processing. Table 5.9 shows interrupt response times—the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.9 are explained in table 5.10. Table 5.9 Interrupt Response Times Normal Mode* No. 1 2 3 4 5 6 Execution Status 1 Interrupt priority determination* 5 Advanced Mode INTM1 = 0 3 (1 to 19) + 2 · SI 2 · SK 2 · SI 2 · SI 2 12 to 32 INTM1 = 1 3 (1 to 19) + 2 · SI 3 · SK 2 · SI 2 · SI 2 13 to 33 INTM1 = 0 3 INTM1 = 1 3 (1 to 19) + 2 · SI 3 · SK SI 2 · SI 2 12 to 32 Number of wait states until executing (1 to 19) 2 instruction ends* + 2 · SI PC, CCR, EXR stack save Vector fetch 3 Instruction fetch* 4 Internal processing* 2 · SK SI 2 · SI 2 11 to 31 Total (using on-chip memory) Notes: 1. 2. 3. 4. 5. Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Not available in the H8S/2214 Group. Rev.4.00 Sep. 18, 2008 Page 112 of 872 REJ09B0189-0400 Section 5 Interrupt Controller Table 5.10 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8 Bit Bus Symbol Instruction fetch Branch address read Stack manipulation SI SJ SK m: Number of wait states in an external device access. Internal Memory 1 2-State Access 4 3-State Access 6+2m 16 Bit Bus 2-State Access 2 3-State Access 3+m 5.5 5.5.1 Usage Notes Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.8 shows and example in which the TGIEA bit in 16-bit timer TIER0 is cleared to 0. The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. Rev.4.00 Sep. 18, 2008 Page 113 of 872 REJ09B0189-0400 Section 5 Interrupt Controller TIER0 write cycle by CPU TGIOA exception handling φ Internal address bus TIER0 address Internal write signal TGIEA TGFA TGIOA interrupt signal Figure 5.8 Contention between Interrupt Generation and Disabling 5.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.5.3 Times when Interrupts Are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. Rev.4.00 Sep. 18, 2008 Page 114 of 872 REJ09B0189-0400 Section 5 Interrupt Controller 5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 5.5.5 IRQ Interrupts When operating from a clock signal, interrupt requests are accepted in synchronization with the clock. Interrupt requests are accepted asynchronously in software standby mode. See section 18.4.2, Control Signal Timing, for the input conditions. 5.5.6 NMI Interrupt Usage Notes The NMI interrupt invokes exception handling that is performed by cooperation between the interrupt controller and the CPU built into this IC during normal operation under the conditions stipulated in the electrical characteristics. No operations, including the NMI interrupt, are guaranteed if there are abnormal inputs to the IC pins or if there are software problems (e.g. if the application has crashed or gone into an infinite loop). In such cases, the IC can be returned to the normal program execution state by applying an external reset. Rev.4.00 Sep. 18, 2008 Page 115 of 872 REJ09B0189-0400 Section 5 Interrupt Controller 5.6 5.6.1 DTC and DMAC Activation by Interrupt Overview The DTC and DMAC can be activated by an interrupt. In this case, the following options are available: • Interrupt request to CPU • Activation request to DTC • Activation request to DMAC • Selection of a number of the above For details of interrupt requests that can be used with to activate the DTC and DMAC, see section 7, DMA Controller (DMAC) and section 8, Data Transfer Controller (DTC). 5.6.2 Block Diagram Figure 5.9 shows a block diagram of the DTC and DMAC interrupt controller. DMAC Clear signal Disenable signal Interrupt request IRQ interrupt Interrupt source clear signal Selection circuit Select signal Clear signal DTCER DTC activation request vector number Control logic Clear signal DTC On-chip supporting module DTVECR SWDTE clear signal Determination of priority Interrupt controller CPU interrupt request vector number CPU I, I2 to I0 Figure 5.9 Interrupt Control for DTC and DMAC Rev.4.00 Sep. 18, 2008 Page 116 of 872 REJ09B0189-0400 Section 5 Interrupt Controller 5.6.3 Operation The interrupt controller has three main functions in DTC and DMAC control. (1) Selection of Interrupt Source DMAC inputs activation factor directly to each channel. The activation factors for each channel of DMAC are selected by DTF3 to DTF0 bits of DMACR. The DTA bit of DMABCR can be used to select whether the selected activation factors are managed by DMAC. By setting the DTA bit to 1, the interrupt factor which were the activation factor for that DMAC do not act as the DTC activation factor or the CPU interrupt factor. Interrupt factors other than the interrupts managed by the DMAC are selected as DTC activation request or CPU interrupt request by the DTCE bit of the DTCEA to DTCEG of DTC. By specifying the DISEL bit of the DTC's MRB, it is possible to clear the DTCE bit to 0 after DTC data transfer, and request a CPU interrupt. If DTC carries out the designate number of data transfers and the transfer counter reads 0, after DTC data transfer, the DTCE bit is also cleared to 0, and a CPU interrupt requested. (2) Determination of Priority The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 8.4, Interrupts, and section 8.3.3, DTC Vector Table for the respective priority. (3) Operation Order If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. If the same interrupt is selected as the DMAC activation factor and as the DTC activation factor or CPU interrupt factor, these operate independently. They operate in accordance with the respective operating states and bus priorities. Table 5.11 shows the interrupt factor clear control and selection of interrupt factors by specification of the DTA bit of DMAC's DMABCR, DTCE bits of DTC's DTCEA to DTCEG, and the DISEL bit of DTC's MRB. Rev.4.00 Sep. 18, 2008 Page 117 of 872 REJ09B0189-0400 Section 5 Interrupt Controller Table 5.11 Interrupt Source Selection and Clearing Control Settings DMAC DTA 0 DTC DTCE 0 1 DISEL * 0 1 * Interrupt Sources Selection/Clearing Control DMAC DTC X X X CPU 1 * X Legend: : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. X : The relevant bit cannot be used. * : Don’t care (4) Notes on Use The SCI interrupt source is cleared when the DMAC or DTC reads or writes to the prescribed register, and is not dependent upon the DTA bit, DTCE bit, or DISEL bit. Rev.4.00 Sep. 18, 2008 Page 118 of 872 REJ09B0189-0400 Section 6 Bus Controller Section 6 Bus Controller 6.1 Overview The H8S/2214 Group has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU, DMA controller (DMAC), and data transfer controller (DTC). 6.1.1 Features The features of the bus controller are listed below. • Manages external address space in area units ⎯ Manages the external space as 8 areas of 2-Mbytes ⎯ Bus specifications can be set independently for each area ⎯ Burst ROM interface can be set • Basic bus interface ⎯ Chip select (CS0 to CS7) can be output for areas 0 to 7 ⎯ 8-bit access or 16-bit access can be selected for each area ⎯ 2-state access or 3-state access can be selected for each area ⎯ Program wait states can be inserted for each area • Burst ROM interface ⎯ Burst ROM interface can be set for area 0 ⎯ Choice of 1- or 2-state burst access • Idle cycle insertion ⎯ An idle cycle can be inserted in case of an external read cycle between different areas ⎯ An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle • Bus arbitration function ⎯ Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, and DTC • Other features ⎯ External bus release function Rev.4.00 Sep. 18, 2008 Page 119 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. CS0 to CS7 Area decoder Internal address bus ABWCR External bus control signals ASTCR BCRH BCRL BREQ BACK Bus controller Internal data bus Internal control signals Bus mode signal WAIT Wait controller WCRH WCRL CPU bus request signal DTC bus request signal Bus arbiter DMAC bus request signal CPU bus acknowledge signal DTC bus acknowledge signal Legend: ABWCR: Bus width control register ASTCR: Access state control register BCRH: Bus control register H BCRL: Bus control register L WCRH: Wait state control register H WCRL: Wait state control register L DMAC bus acknowledge signal Figure 6.1 Block Diagram of Bus Controller Rev.4.00 Sep. 18, 2008 Page 120 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.1.3 Pin Configuration Table 6.1 summarizes the pins of the bus controller. Table 6.1 Name Address strobe Read High write Bus Controller Pins Symbol AS RD HWR I/O Output Output Output Function Strobe signal indicating that address output on address bus is enabled. Strobe signal indicating that external space is being read. Strobe signal indicating that external space is to be written, and upper half (D15 to D8) of data bus is enabled. Strobe signal indicating that external space is to be written, and lower half (D7 to D0) of data bus is enabled. Strobe signal indicating that areas 0 to 7 are selected. Wait request signal when accessing external 3-state access space. Request signal that releases bus to external device. Acknowledge signal indicating that bus has been released. Low write Chip select 0 to 7 Wait Bus request Bus request acknowledge LWR CS0 to CS7 WAIT BREQ BACK Output Output Input Input Output Rev.4.00 Sep. 18, 2008 Page 121 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.1.4 Register Configuration Table 6.2 summarizes the registers of the bus controller. Table 6.2 Bus Controller Registers Initial Value Name Bus width control register Access state control register Wait control register H Wait control register L Bus control register H Bus control register L Pin function control register Abbreviation ABWCR ASTCR WCRH WCRL BCRH BCRL PFCR R/W R/W R/W R/W R/W R/W R/W R/W Power-On Reset H'FF/H'00* H'FF H'FF H'FF H'D0 H'08 3 H'0D/H'00* 2 Manual Reset Retained Retained Retained Retained Retained Retained Retained Address* H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FDEB 1 Notes: 1. Lower 16 bits of the address. 2. Determined by the MCU operating mode. Initialized to H'00 in mode 4, and to H'FF in modes 5 to 7. 3. Initialized to H'0D in modes 4 and 5, and to H'00 in modes 6 and 7. Rev.4.00 Sep. 18, 2008 Page 122 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.2 6.2.1 Bit Register Descriptions Bus Width Control Register (ABWCR) : 7 ABW7 6 ABW6 1 R/W 0 R/W 5 ABW5 1 R/W 0 R/W 4 ABW4 1 R/W 0 R/W 3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W 1 ABW1 1 R/W 0 R/W 0 ABW0 1 R/W 0 R/W Modes 5 to 7 Initial value : RW Mode 4 Initial value : RW : : 1 R/W 0 R/W ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. ABWCR sets the data bus width for the external memory space. The bus width for on-chip memory and internal I/O registers is fixed regardless of the settings in ABWCR. After a power-on reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 5, 6, and 7, and to H'00 in mode 4. It is not initialized by a manual reset or in software standby mode. Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the corresponding area is to be designated for 8-bit access or 16-bit access. Bit n ABWn 0 1 Description Area n is designated for 16-bit access Area n is designated for 8-bit access (n = 7 to 0) Rev.4.00 Sep. 18, 2008 Page 123 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.2.2 Bit Access State Control Register (ASTCR) : 7 AST7 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W 3 AST3 1 R/W 2 AST2 1 R/W 1 AST1 1 R/W 0 AST0 1 R/W Initial value : R/W : ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR. ASTCR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is to be designated as a 2-state access space or a 3-state access space. Wait state insertion is enabled or disabled at the same time. Bit n ASTn 0 1 Description Area n is designated for 2-state access Wait state insertion in area n external space is disabled Area n is designated for 3-state access Wait state insertion in area n external space is enabled (Initial value) (n = 7 to 0) Rev.4.00 Sep. 18, 2008 Page 124 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a power-on reset and in hardware standby mode. They are not initialized by a manual reset or in software standby mode. (1) WCRH Bit : 7 W71 Initial value : R/W : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3 W51 1 R/W 2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1. Bit 7 W71 0 1 Bit 6 W70 0 1 0 1 Description Program wait not inserted when external space area 7 is accessed 1 program wait state inserted when external space area 7 is accessed 2 program wait states inserted when external space area 7 is accessed 3 program wait states inserted when external space area 7 is accessed (Initial value) Rev.4.00 Sep. 18, 2008 Page 125 of 872 REJ09B0189-0400 Section 6 Bus Controller Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit 5 W61 0 1 Bit 4 W60 0 1 0 1 Description Program wait not inserted when external space area 6 is accessed 1 program wait state inserted when external space area 6 is accessed 2 program wait states inserted when external space area 6 is accessed 3 program wait states inserted when external space area 6 is accessed (Initial value) Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 W51 0 1 Bit 2 W50 0 1 0 1 Description Program wait not inserted when external space area 5 is accessed 1 program wait state inserted when external space area 5 is accessed 2 program wait states inserted when external space area 5 is accessed 3 program wait states inserted when external space area 5 is accessed (Initial value) Bits 1 and 0—Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1. Bit 1 W41 0 1 Bit 0 W40 0 1 0 1 Description Program wait not inserted when external space area 4 is accessed 1 program wait state inserted when external space area 4 is accessed 2 program wait states inserted when external space area 4 is accessed 3 program wait states inserted when external space area 4 is accessed (Initial value) Rev.4.00 Sep. 18, 2008 Page 126 of 872 REJ09B0189-0400 Section 6 Bus Controller (2) WCRL Bit : 7 W31 Initial value : R/W : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3 W11 1 R/W 2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1. Bit 7 W31 0 1 Bit 6 W30 0 1 0 1 Description Program wait not inserted when external space area 3 is accessed 1 program wait state inserted when external space area 3 is accessed 2 program wait states inserted when external space area 3 is accessed 3 program wait states inserted when external space area 3 is accessed (Initial value) Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1. Bit 5 W21 0 1 Bit 4 W20 0 1 0 1 Description Program wait not inserted when external space area 2 is accessed 1 program wait state inserted when external space area 2 is accessed 2 program wait states inserted when external space area 2 is accessed 3 program wait states inserted when external space area 2 is accessed (Initial value) Rev.4.00 Sep. 18, 2008 Page 127 of 872 REJ09B0189-0400 Section 6 Bus Controller Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 W11 0 1 Bit 2 W10 0 1 0 1 Description Program wait not inserted when external space area 1 is accessed 1 program wait state inserted when external space area 1 is accessed 2 program wait states inserted when external space area 1 is accessed 3 program wait states inserted when external space area 1 is accessed (Initial value) Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1. Bit 1 W01 0 1 Bit 0 W00 0 1 0 1 Description Program wait not inserted when external space area 0 is accessed 1 program wait state inserted when external space area 0 is accessed 2 program wait states inserted when external space area 0 is accessed 3 program wait states inserted when external space area 0 is accessed (Initial value) Rev.4.00 Sep. 18, 2008 Page 128 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.2.4 Bit Bus Control Register H (BCRH) : 7 ICIS1 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W 3 0 R/W 2 — 0 R/W 1 — 0 R/W 0 — 0 R/W BRSTRM BRSTS1 BRSTS0 Initial value : R/W : BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1 0 1 Description Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas (Initial value) Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed. Bit 6 ICIS0 0 1 Description Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles (Initial value) Rev.4.00 Sep. 18, 2008 Page 129 of 872 REJ09B0189-0400 Section 6 Bus Controller Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface. Bit 5 BRSTRM 0 1 Description Area 0 is basic bus interface Area 0 is burst ROM interface (Initial value) Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 0 1 Description Burst cycle comprises 1 state Burst cycle comprises 2 states (Initial value) Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 0 1 Description Max. 4 words in burst access Max. 8 words in burst access (Initial value) Bits 2 to 0—Reserved: Only 0 should be written to these bits. Rev.4.00 Sep. 18, 2008 Page 130 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.2.5 Bit Bus Control Register L (BCRL) : 7 BRLE 0 R/W 6 — 0 R/W 5 — 0 — 4 — 0 R/W 3 — 1 R/W 2 — 0 R/W 1 — 0 R/W 0 WAITE 0 R/W Initial value : R/W : BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, and enabling or disabling of WAIT pin input. BCRL is initialized to H'08 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release. Bit 7 BRLE 0 1 Description External bus release is disabled. BREQ and BACK can be used as I/O ports. (Initial value) External bus release is enabled. Bit 6—Reserved: Only 0 should be written to this bit. Bit 5—Reserved: This bit cannot be modified and is always read as 0. Bit 4—Reserved: Only 0 should be written to this bit. Bit 3—Reserved: Only 1 should be written to this bit. Bits 2 and 1—Reserved: Only 0 should be written to these bits. Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin. Bit 0 WAITE 0 1 Description Wait input by WAIT pin disabled. WAIT pin can be used as I/O port. Wait input by WAIT pin enabled (Initial value) Rev.4.00 Sep. 18, 2008 Page 131 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.2.6 Bit Pin Function Control Register (PFCR) : 7 — 6 — 0 0 R/W 5 — 0 0 R/W 4 — 0 0 R/W 3 AE3 1 0 R/W 2 AE2 1 0 R/W 1 AE1 0 0 R/W 0 AE0 1 0 R/W Modes 4 and 5 Initial value Modes 6 and 7 Initial value R/W : : 0 R/W : 0 PFCR is an 8-bit readable/writable register that performs address output control in external expanded mode. PFCR is initialized to H'0D (modes 4 and 5) or H'00 (modes 6 and 7) by a power-on reset and in hardware standby mode. It retains its previous state in a manual reset and in software standby mode. Bits 7 to 4—Reserved: Only 0 should be written to these bits. Bits 3 to 0—Address Output Enable 3 to 0 (AE3 to AE0): These bits select enabling or disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is enabled for address output, the address is output regardless of the corresponding DDR setting. When a pin is disabled for address output, it becomes an output port when the corresponding DDR bit is set to 1. Rev.4.00 Sep. 18, 2008 Page 132 of 872 REJ09B0189-0400 Section 6 Bus Controller Bit 3 AE3 0 Bit 2 AE2 0 Bit 1 AE1 0 1 1 0 1 1 0 0 1 1 0 Bit 0 AE0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 Description A8 to A23 output disabled A8 output enabled; A9 to A23 output disabled A8, A9 output enabled; A10 to A23 output disabled A8 to A10 output enabled; A11 to A23 output disabled A8 to A11 output enabled; A12 to A23 output disabled A8 to A12 output enabled; A13 to A23 output disabled A8 to A13 output enabled; A14 to A23 output disabled A8 to A14 output enabled; A15 to A23 output disabled A8 to A15 output enabled; A16 to A23 output disabled A8 to A16 output enabled; A17 to A23 output disabled A8 to A17 output enabled; A18 to A23 output disabled A8 to A18 output enabled; A19 to A23 output disabled A8 to A19 output enabled; A20 to A23 output disabled A8 to A20 output enabled; A21 to A23 output disabled (Initial value*2) A8 to A21 output enabled; A22, A23 output disabled A8 to A23 output enabled (Initial value*1) Notes: 1. In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000. In expanded mode with ROM, address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to 1. 2. In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101. In ROMless expanded mode, address pins A0 to A7 are always made address output. Rev.4.00 Sep. 18, 2008 Page 133 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.3 6.3.1 Overview of Bus Control Area Divisions In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode*, it controls a 64-kbyte address space comprising part of area 0. Figure 6.2 shows an outline of the memory map. Chip select signals (CS0 to CS7) can be output for each area. Note: * Not available in the H8S/2214 Group. H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) H'FFFFFF (1) Advanced mode (2) Normal mode* H'0000 H'FFFF Note: * Not available in the H8S/2214 Group. Figure 6.2 Overview of Area Divisions Rev.4.00 Sep. 18, 2008 Page 134 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. (1) Bus Width A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is always set. (2) Number of Access States Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a 3-state access space. With the burst ROM interface, the number of access states may be determined without regard to ASTCR. When 2-state access space is designated, wait insertion is disabled. (3) Number of Program Wait States When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected. Table 6.3 shows the bus specifications for each basic bus interface area. Rev.4.00 Sep. 18, 2008 Page 135 of 872 REJ09B0189-0400 Section 6 Bus Controller Table 6.3 ABWCR ABWn 0 Bus Specifications for Each Area (Basic Bus Interface) ASTCR ASTn 0 1 WCRH, WCRL Wn1 — 0 1 Wn0 — 0 1 0 1 — 0 1 1 0 1 8 2 3 Bus Specifications (Basic Bus Interface) Bus Width 16 Program Wait Access States States 2 3 0 0 1 2 3 0 0 1 2 3 1 0 1 — 0 6.3.3 Memory Interfaces The H8S/2214 Group memory interfaces comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on, and a burst ROM interface (for area 0 only) that allows direct connection of burst ROM. An area for which the basic bus interface is designated functions as normal space, and an area for which the burst ROM interface is designated functions as burst ROM space. Rev.4.00 Sep. 18, 2008 Page 136 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.3.4 Interface Specifications for Each Area The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (see section 6.4, Basic Bus Interface, and 6.5, Burst ROM Interface) should be referred to for further details. (1) Area 0 Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external space. When area 0 external space is accessed, the CS0 signal can be output. Either basic bus interface or burst ROM interface can be selected for area 0. (2) Areas 1 to 6 In external expansion mode, all of areas 1 to 6 is external space. When area 1 to 6 external space is accessed, the CS1 to CS6 pin signals respectively can be output. Only the basic bus interface can be used for areas 1 to 6. (3) Area 7 Area 7 includes the on-chip RAM, external module expansion function space, and internal l/O registers. In external expansion mode, the space excluding the on-chip RAM, external module expansion function space, and internal l/O registers, is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space. When the P75MSOE bit in the external module connection output pin select register (OPINSEL) is set to 1, the external module expansion function is enabled and the signal is output for addresses H'FFFF40 to H'FFFF5F. When the P75MSOE bit is cleared to 0, the external module expansion function is disabled and the corresponding addresses are external space. When area 7 external space is accessed, the CS7 signal can be output. Only the basic bus interface can be used for the area 7. Rev.4.00 Sep. 18, 2008 Page 137 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.3.5 Chip Select Signals The H8S/2214 Group can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. Figure 6.3 shows an example of CSn (n = 0 to 7) output timing. Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR) for the port corresponding to the particular CSn pin. In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset. Pins CS1 to CS7 are placed in the input state after a power-on reset, and so the corresponding DDR should be set to 1 when outputting signals CS1 to CS7. In ROM-enabled expansion mode, pins CS0 to CS7 are all placed in the input state after a poweron reset, and so the corresponding DDR should be set to 1 when outputting signals CS0 to CS7. For details, see section 9, I/O Ports. Bus cycle T1 φ T2 T3 Address bus Area n external address CSn Figure 6.3 CSn Signal Output Timing (n = 0 to 7) Rev.4.00 Sep. 18, 2008 Page 138 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.4 6.4.1 Basic Bus Interface Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. (1) 8-Bit Access Space Figure 6.4 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses. Upper data bus Lower data bus D15 D8 D7 D0 Byte size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Word size Figure 6.4 Access Sizes and Data Alignment Control (8-Bit Access Space) Rev.4.00 Sep. 18, 2008 Page 139 of 872 REJ09B0189-0400 Section 6 Bus Controller (2) 16-Bit Access Space Figure 6.5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Lower data bus Upper data bus D15 D8 D7 D0 Byte size Byte size Word size Longword size 1st bus cycle 2nd bus cycle • Even address • Odd address Figure 6.5 Access Sizes and Data Alignment Control (16-Bit Access Space) Rev.4.00 Sep. 18, 2008 Page 140 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.4.3 Valid Strobes Table 6.4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.4 Area 8-bit access space Data Buses Used and Valid Strobes Access Read/ Size Write Byte Read Write Read Write Word Read Write Address — — Even Odd Even Odd — — HWR LWR RD Valid Strobe RD HWR RD Valid Invalid Valid Hi-Z Valid Upper Data Bus (D15 to D8) Valid Lower data bus (D7 to D0) Invalid Hi-Z Invalid Valid Hi-Z Valid Valid Valid 16-bit access Byte space HWR, LWR Valid Notes: Hi-Z: High impedance. Invalid: Input state; input value is ignored. Rev.4.00 Sep. 18, 2008 Page 141 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.4.4 Basic Timing (1) 8-Bit 2-State Access Space Figure 6.6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states cannot be inserted. Bus cycle T1 φ T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR (16-bit bus mode) Write LWR (8-bit bus mode) D15 to D8 High High impedance Valid High impedance D7 to D0 Note: n = 0 to 7 Figure 6.6 Bus Timing for 8-Bit 2-State Access Space Rev.4.00 Sep. 18, 2008 Page 142 of 872 REJ09B0189-0400 Section 6 Bus Controller (2) 8-Bit 3-State Access Space Figure 6.7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted. Bus cycle T1 φ T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR (16-bit bus mode) Write LWR (8-bit bus mode) D15 to D8 High High impedance Valid High impedance D7 to D0 Note: n = 0 to 7 Figure 6.7 Bus Timing for 8-Bit 3-State Access Space Rev.4.00 Sep. 18, 2008 Page 143 of 872 REJ09B0189-0400 Section 6 Bus Controller (3) 16-Bit 2-State Access Space Figures 6.8 to 6.10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted. Bus cycle T1 φ T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Note: n = 0 to 7 Figure 6.8 Bus Timing for 16-Bit 2-State Access Space (Even Address Byte Access) Rev.4.00 Sep. 18, 2008 Page 144 of 872 REJ09B0189-0400 Section 6 Bus Controller Bus cycle T1 φ T2 Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Valid Note: n = 0 to 7 Figure 6.9 Bus Timing for 16-Bit 2-State Access Space (Odd Address Byte Access) Rev.4.00 Sep. 18, 2008 Page 145 of 872 REJ09B0189-0400 Section 6 Bus Controller Bus cycle T1 φ T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 7 Figure 6.10 Bus Timing for 16-Bit 2-State Access Space (Word Access) Rev.4.00 Sep. 18, 2008 Page 146 of 872 REJ09B0189-0400 Section 6 Bus Controller (4) 16-Bit 3-State Access Space Figures 6.11 to 6.13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted. Bus cycle T1 φ T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 Valid High impedance D7 to D0 Note: n = 0 to 7 Figure 6.11 Bus Timing for 16-Bit 3-State Access Space (Even Address Byte Access) Rev.4.00 Sep. 18, 2008 Page 147 of 872 REJ09B0189-0400 Section 6 Bus Controller Bus cycle T1 φ T2 T3 Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Note: n = 0 to 7 Valid Figure 6.12 Bus Timing for 16-Bit 3-State Access Space (Odd Address Byte Access) Rev.4.00 Sep. 18, 2008 Page 148 of 872 REJ09B0189-0400 Section 6 Bus Controller Bus cycle T1 φ T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Note: n = 0 to 7 Valid Figure 6.13 Bus Timing for 16-Bit 3-State Access Space (Word Access) Rev.4.00 Sep. 18, 2008 Page 149 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.4.5 Wait Control When accessing external space, the H8S/2214 Group can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: (1) program wait insertion and (2) pin wait insertion using the WAIT pin. (1) Program Wait Insertion From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings of WCRH and WCRL. (2) Pin Wait Insertion Setting the WAITE bit in BCRH to 1 enables wait insertion by means of the WAIT pin. When external space is accessed in this state, program wait insertion is first carried out according to the settings in WCRH and WCRL. Then, if the WAIT pin is low at the falling edge of φ in the last T2 or TW state, a TW state is inserted. If the WAIT pin is held low, TW states are inserted until it goes high. This is useful when inserting four or more TW states, or when changing the number of TW states for different external devices. The WAITE bit setting applies to all areas. Rev.4.00 Sep. 18, 2008 Page 150 of 872 REJ09B0189-0400 Section 6 Bus Controller Figure 6.14 shows an example of wait state insertion timing. By program wait By WAIT pin T1 φ T2 TW TW TW T3 WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Note: indicates the timing of WAIT pin sampling. Figure 6.14 Example of Wait State Insertion Timing The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT input disabled. When a manual reset is performed, the contents of bus controller registers are retained, and the wait control settings remain the same as before the reset. Rev.4.00 Sep. 18, 2008 Page 151 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.5 6.5.1 Burst ROM Interface Overview With the H8S/2214 Group, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only. One or two states can be selected for burst access. 6.5.2 Basic Timing The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state insertion is possible. One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst ROM space, it becomes 16-bit access space regardless of the setting of the ABW0 bit in ABWCR. When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when the BRSTS0 bit is set to 1, burst access of up to 8 words is performed. The basic access timing for burst ROM space is shown in figures 6.15 and 6.16. The timing shown in figure 6.15 is for the case where the AST0 and BRSTS1 bits are both set to 1, and that in figure 6.16 is for the case where both these bits are cleared to 0. Rev.4.00 Sep. 18, 2008 Page 152 of 872 REJ09B0189-0400 Section 6 Bus Controller Full access T1 φ T2 T3 T1 Burst access T2 T1 T2 Address bus Only lower address changed CS0 AS RD Data bus Read data Read data Read data Figure 6.15 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) Rev.4.00 Sep. 18, 2008 Page 153 of 872 REJ09B0189-0400 Section 6 Bus Controller Full access Burst access T1 φ T2 T1 T1 Address bus Only lower address changed CS0 AS RD Data bus Read data Read data Read data Figure 6.16 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 6.5.3 Wait Control As with the basic bus interface, either (1) program wait insertion or (2) pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait Control. Wait states cannot be inserted in a burst cycle. Rev.4.00 Sep. 18, 2008 Page 154 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.6 6.6.1 Idle Cycle Operation When the H8S/2214 Group accesses external space, it can insert a 1-state idle cycle (TI) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on. (1) Consecutive Reads between Different Areas If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read cycle. Figure 6.17 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A φ Address bus CS (area A) CS (area B) RD Data bus Data collision (b) Idle cycle inserted (Initial value ICIS1 = 1) T1 T2 T3 Bus cycle B T1 T2 φ Address bus CS (area A) CS (area B) RD Data bus Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Long output floating time (a) Idle cycle not inserted (ICIS1 = 0) Figure 6.17 Example of Idle Cycle Operation (1) Rev.4.00 Sep. 18, 2008 Page 155 of 872 REJ09B0189-0400 Section 6 Bus Controller (2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 6.18 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 φ Address bus CS (area A) CS (area B) RD HWR Data bus Data collision (b) Idle cycle inserted (Initial value ICIS1 = 1) T2 T3 Bus cycle B T1 T2 φ Address bus CS (area A) CS (area B) RD HWR Data bus Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Long output floating time (a) Idle cycle not inserted (ICIS1 = 0) Figure 6.18 Example of Idle Cycle Operation (2) Rev.4.00 Sep. 18, 2008 Page 156 of 872 REJ09B0189-0400 Section 6 Bus Controller (3) Relationship between Chip Select (CS) Signal and Read (RD) Signal Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6.19. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the initial state after reset release, idle cycle insertion (b) is set. Bus cycle A T1 φ Address bus CS (area A) CS (area B) RD T2 T3 Bus cycle B T1 T2 φ Address bus CS (area A) CS (area B) RD Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Possibility of overlap between CS (area B) and RD (a) Idle cycle not inserted (ICIS1 = 0) (b) Idle cycle inserted (Initial value ICIS1 = 1) Figure 6.19 Relationship between Chip Select (CS) and Read (RD) Rev.4.00 Sep. 18, 2008 Page 157 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.6.2 Pin States in Idle Cycle Table 6.5 shows pin states in an idle cycle. Table 6.5 Pins A23 to A0 D15 to D0 CSn AS RD HWR LWR Pin States in Idle Cycle Pin State Contents of next bus cycle High impedance High High High High High Rev.4.00 Sep. 18, 2008 Page 158 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.7 6.7.1 Bus Release Overview The H8S/2214 Group can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. 6.7.2 Operation In external expansion mode, the bus can be released to an external device by setting the BRLE bit in BCRL to 1. Driving the BREQ pin low issues an external bus request to this LSI. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus-released state. In the external bus released state, an internal bus master can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request from the external bus master to be dropped. When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the external bus released state is terminated. In the event of simultaneous external bus release request and external access request generation, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low) Rev.4.00 Sep. 18, 2008 Page 159 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.7.3 Pin States in External Bus Released State Table 6.6 shows pin states in the external bus released state. Table 6.6 Pins A23 to A0 D15 to D0 CSn AS RD HWR LWR Pin States in Bus Released State Pin State High impedance High impedance High impedance High impedance High impedance High impedance High impedance Rev.4.00 Sep. 18, 2008 Page 160 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.7.4 Transition Timing Figure 6.20 shows the timing for transition to the bus-released state. CPU cycle CPU cycle T0 φ T1 T2 External bus released state High impedance Address bus Address High impedance Data bus CSn High impedance High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK Minimum 1 state [1] [2] [3] [4] [5] [1] [2] [3] [4] [5] Low level of BREQ pin is sampled at rise of T2 state. BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master. BREQ pin state is still sampled in external bus released state. High level of BREQ pin is sampled. BACK pin is driven high, ending bus release cycle. Note: n = 0 to 7 Figure 6.20 Bus-Released State Transition Timing Rev.4.00 Sep. 18, 2008 Page 161 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.7.5 Usage Note When MSTPCR is set to H'FFFFFF and a transition is made to sleep mode, the external bus release function halts. Therefore, MSTPCR should not be set to H'FFFFFF if the external bus release function is to be used in sleep mode. 6.8 6.8.1 Bus Arbitration Overview The H8S/2214 Group has a bus arbiter that arbitrates bus master operations. There are three bus masters, the CPU, DMAC, and DTC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. 6.8.2 Operation The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) DMAC > DTC > CPU (Low) An internal bus access by an internal bus master, and external bus release, can be executed in parallel. In the event of simultaneous external bus release request, and internal bus master external access request generation, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low) Rev.4.00 Sep. 18, 2008 Page 162 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.8.3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. (1) CPU The CPU is the lowest-priority bus master, and if a bus request is received from the DMAC and DTC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: • The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. See appendix A.5, Bus States during Instruction Execution, for timings at which the bus is not transferred. • If the CPU is in sleep mode, it transfers the bus immediately. (2) DTC The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). (3) DMAC The DMAC sends the bus arbiter a request for the bus when an activation request is generated. In the case of an external request in short address mode or normal mode, and in cycle steal mode, the DMAC releases the bus after a single transfer. In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after completion of the transfer. 6.8.4 External Bus Release Usage Note External bus release can be performed on completion of an external bus cycle. The CS signal remains low until the end of the external bus cycle. Therefore, when external bus release is performed, the CS signal may change from the low level to the high-impedance state. Rev.4.00 Sep. 18, 2008 Page 163 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.9 Resets and the Bus Controller In a power-on reset, the H8S/2214 Group, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. In a manual reset, the bus controller’s registers and internal state are maintained, and an executing external bus cycle is completed. In this case, WAIT input is ignored and write data is not guaranteed. 6.10 6.10.1 External Module Expansion Function Overview The H8S/2214 Group has an external module expansion function to provide for the addition of peripheral devices. Using this function to provide a combination of H8S/2214 Group and external modules makes it possible to implement a multichip system on the user board. Figure 6.21 shows a block diagram. Bus access states can be changed by means of a bus controller setting. The EXMS signal is output to external modules for addresses H'FFFF40 to H'FFFF5F. Priority and DTC activation can be specified for interrupts EXIRQ7 to EXIRQ0 in the same way as for the H8S/2214’s on-chip supporting functions. The DTC data transfer end signal for EXIRQ7 to EXIRQ0 interrupt input is output from EXDTCE. Also, the inverse of the value of bit 0 in module stop control register B is output from EXMSTP. Rev.4.00 Sep. 18, 2008 Page 164 of 872 REJ09B0189-0400 Section 6 Bus Controller A23 to A0 D15 to D0 H8S/2214 Group EXMSTP EXMS EXDTCE EXIRQ7 to EXIRQ0 External module Figure 6.21 Multichip Block Diagram 6.10.2 Pin Configuration Table 6.7 summarizes the pins of the external module expansion function. Table 6.7 Name External expansion interrupt request 7 to 0 External expansion module select External expansion DTC transfer end External expansion module stop External Module Expansion Function Pins Symbol EXIRQ7 to EXIRQ0 EXMS EXDTCE EXMSTP I/O Input Output Output Output Function Input pins for interrupt requests from external modules Select signal for external modules DTC transfer end signal for EXIRQ7 to EXIRQ0 interrupt input Module stop signal for external modules 6.10.3 Register Configuration Table 6.8 summarizes the registers of the bus controller. Rev.4.00 Sep. 18, 2008 Page 165 of 872 REJ09B0189-0400 Section 6 Bus Controller Table 6.8 Bus Controller Registers Initial Value Name Abbreviation R/W R/W R/W R/W Power-On Reset H'00 B'-000---H'FF Manual Reset Retained Retained H'FF Address* H'FE4A H'FE4E H'FDE9 Interrupt request input pin select IPINSEL0 register 0 External module connection output pin select register Module stop control register B OPINSEL MSTPCRB Note: * Lower 16 bits of the address. 6.10.4 Bit Interrupt Request Input Pin Select Register 0 (IPINSEL0) : 7 P36 IRQ7E 0 R/W 6 P47 IRQ6E 0 R/W 5 P46 IRQ5E 0 R/W 4 P44 IRQ4E 0 R/W 3 P43 IRQ3E 0 R/W 2 P42 IRQ2E 0 R/W 1 P41 IRQ1E 0 R/W 0 P40 IRQ0E 0 R/W Initial value : R/W : IPINSEL0 is an 8-bit readable/writable register that selects which pins are to be used for interrupt request input signals (EXIRQ7 to EXIRQ0) from externally connected modules when operating as H8S/2214 modules. IPINSEL0 is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state in a manual reset and in software standby mode. Bit 7—Enable of EXIRQ7 Input from P36 (P36IRQ7E): Selects whether or not P36 is used as the EXIRQ7 input pin. Bit 7 P36IRQ7E 0 1 Description P36 is not used as EXIRQ7 input P36 is used as EXIRQ7 input (Initial value) Rev.4.00 Sep. 18, 2008 Page 166 of 872 REJ09B0189-0400 Section 6 Bus Controller Bit 6—Enable of EXIRQ6 Input from P47 (P47IRQ6E): Selects whether or not P47 is used as the EXIRQ6 input pin. Bit 6 P47IRQ6E 0 1 Description P47 is not used as EXIRQ6 input P47 is used as EXIRQ6 input (Initial value) Bit 5—Enable of EXIRQ5 Input from P46 (P46IRQ5E): Selects whether or not P46 is used as the EXIRQ5 input pin. Bit 5 P46IRQ5E 0 1 Description P46 is not used as EXIRQ5 input P46 is used as EXIRQ5 input (Initial value) Bit 4—Enable of EXIRQ4 Input from P44 (P44IRQ4E): Selects whether or not P44 is used as the EXIRQ4 input pin. Bit 4 P44IRQ4E 0 1 Description P44 is not used as EXIRQ4 input P44 is used as EXIRQ4 input (Initial value) Bit 3—Enable of EXIRQ3 Input from P43 (P43IRQ3E): Selects whether or not P43 is used as the EXIRQ3 input pin. Bit 3 P43IRQ3E 0 1 Description P43 is not used as EXIRQ3 input P43 is used as EXIRQ3 input (Initial value) Rev.4.00 Sep. 18, 2008 Page 167 of 872 REJ09B0189-0400 Section 6 Bus Controller Bit 2—Enable of EXIRQ2 Input from P42 (P42IRQ2E): Selects whether or not P42 is used as the EXIRQ2 input pin. Bit 2 P42IRQ2E 0 1 Description P42 is not used as EXIRQ2 input P42 is used as EXIRQ2 input (Initial value) Bit 1—Enable of EXIRQ1 Input from P41 (P41IRQ1E): Selects whether or not P41 is used as the EXIRQ1 input pin. Bit 1 P41IRQ1E 0 1 Description P41 is not used as EXIRQ1 input P41 is used as EXIRQ1 input (Initial value) Bit 0—Enable of EXIRQ0 Input from P40 (P40IRQ0E): Selects whether or not P40 is used as the EXIRQ0 input pin. Bit 0 P40IRQ0E 0 1 Description P40 is not used as EXIRQ0 input P40 is used as EXIRQ0 input (Initial value) 6.10.5 Bit External Module Connection Output Pin Select Register (OPINSEL) : 7 — 6 P76 STPOE 0 R/W 5 P75 MSOE 0 R/W 4 P74 DTCOE 0 R/W 3 — 2 — 1 — 0 — Initial value : R/W : Undefined Undefined Undefined Undefined Undefined R/W — — — — OPINSEL is an 8-bit readable/writable register that selects whether or not output signals (EXDTCEN, EXMSTP, EXMSN) to externally connected modules are output to pins P77 to P74 in H8S/2214 Group operation. OPINSEL bits 6 to 4 are initialized to 000 by a power-on reset and in hardware standby mode. They retain their previous states in a manual reset and in software standby mode. Rev.4.00 Sep. 18, 2008 Page 168 of 872 REJ09B0189-0400 Section 6 Bus Controller Bit 7—Reserved: This bit will return an undefined value if read, and should only be written with 0. Bit 6—Enable of EXMSTP Output to P76 (P76STPOE): Selects whether or not the EXMSTP module stop signal to external modules (corresponding to bit 0 in MSTPCRB) is output to P76. Bit 6 P76STPOE 0 1 Description EXMSTP is not output to P76 EXMSTP is output to P76 (Initial value) Bit 5—Enable of EXMS Output to P75 (P75MSOE): Selects whether or not the EXMS module stop signal to external modules (corresponding to addresses H'FFFF40 to H'FFFF5F) is output to P75. Bit 5 P75MSOE 0 1 Description EXMS is not output to P75 EXMS is output to P75 (Initial value) Bit 4—Enable of EXDTCE Output to P74 (P74DTCOE): Selects whether or not the EXDTCE signal, indicating that DTC transfer corresponding to EXIRQ0—F input is in progress, is output to P74. This signal is used, for example, when the DTC in the chip has been activated by an interrupt (EXIRQ0 to EXIRQF) from an external module, and the interrupt request is to be cleared automatically on the external module side by DTC transfer. Bit 4 P74DTCOE 0 1 Description EXDTCE is not output to P74 EXDTCE is output to P74 (Initial value) Bits 3 to 0—Reserved: These bits will return an undefined value if read, and should only be written with 0. Rev.4.00 Sep. 18, 2008 Page 169 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.10.6 Bit Module Stop Control Register B (MSTPCRB) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : R/W : MSTPCRB is an 8-bit readable/writable register that performs module stop mode control. When the MSTPB0 bit is set to 1, the external module expansion function stops operation at the end of the bus cycle, and enters module stop mode. For details, see section 17.5, Module Stop Mode. MSTPCRB is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 0—Module Stop (MSTPB0): Specifies the external module expansion function module stop mode. Bit 0 MSTPB0 0 1 Description External module expansion function module stop mode is cleared External module expansion function module stop mode is set (Initial value) Rev.4.00 Sep. 18, 2008 Page 170 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.10.7 Basic Timing Figure 6.22 shows the timing of external module area (H'FFFF40 to H'FFFF5F) DTC data transfer using 3-state access. External module area read T1 φ T2 T3 T1 Write T2 T3 Address EXMS RD EXDTCE (a) Timing of external module area read by DTC Read T1 φ T2 T3 External module area write T1 T2 T3 Address EXMS WR EXDTCE (b) Timing of external module area write by DTC Figure 6.22 Timing of External Module Area Access by DTC Rev.4.00 Sep. 18, 2008 Page 171 of 872 REJ09B0189-0400 Section 6 Bus Controller 6.10.8 Notes on Use of External Module Extended Functions When accessing addresses in the range H'FFFF40 to H'FFFF5F in the LSI’s on-chip ROM valid extended mode (mode 6), care must be taken with regard to the following. Figure 6.23 is an address map for the on-chip ROM valid extended mode (mode 6). When bit P75MSOE in the external module connection output pin register (OPINSEL) is set to 1 and EXMS output from pin 75 is enabled, accessing external address [3] (address range: H'FFFF40 to H'FFFF5F) causes low-level output from EXMS. This low-level output is maintained thereafter even if on-chip ROM, on-chip RAM, or the on-chip I/O registers are accessed. As a countermeasure, output from EXMS can be driven high by accessing external addresses [1] and [2]. Consequently, after accessing external address [3], make sure to perform a dummy read of 1 byte to external addresses [1] and [2] to drive output from EXMS high before accessing on-chip RAM or the on-chip I/O registers. EXMS output state H'000000 On-chip ROM Previous value maintained H'020000 H'FFB000 H'FFC000 H'FFEFC0 H'FFF800 H'FFFF40 H'FFFF60 H'FFFFC0 H'FFFFFF External address [1] Reserved area On-chip RAM External address [2] Internal I/O registers External address [3] Internal I/O registers On-chip RAM High Previous value maintained Previous value maintained High Previous value maintained Low Previous value maintained Previous value maintained Figure 6.23 On-Chip ROM Valid Extended Mode (Mode 6) Address Map Rev.4.00 Sep. 18, 2008 Page 172 of 872 REJ09B0189-0400 Section 7 DMA Controller Section 7 DMA Controller 7.1 Overview The H8S/2214 Group has an on-chip DMA controller (DMAC) which can carry out data transfer on up to 4 channels. 7.1.1 Features The features of the DMAC are listed below. • Choice of short address mode or full address mode Short address mode ⎯ Maximum of 4 channels can be used ⎯ Choice of dual address mode ⎯ In dual address mode, one of the two addresses, transfer source and transfer destination, is specified as 24 bits and the other as16 bits ⎯ Choice of sequential mode, idle mode, or repeat mode for dual address mode Full address mode ⎯ Maximum of 2 channels can be used ⎯ Transfer source and transfer destination address specified as 24 bits ⎯ Choice of normal mode or block transfer mode • 16-Mbyte address space can be specified directly • Byte or word can be set as the transfer unit • Activation sources: internal interrupt, external request, auto-request (depending on transfer mode) ⎯ Three 16-bit timer-pulse unit (TPU) compare match/input capture interrupts ⎯ Serial communication interface (SCI0, SCI1) transmission complete interrupt, reception complete interrupt ⎯ External request ⎯ Auto-request • Module stop mode can be set ⎯ The initial setting enables DMAC registers to be accessed. DMAC operation is halted by setting module stop mode Rev.4.00 Sep. 18, 2008 Page 173 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.1.2 Block Diagram A block diagram of the DMAC is shown in figure 7.1. Internal address bus Internal interrupts TGI0A TGI1A TGI2A Channel 1B Channel 1A Channel 0B Channel 0A Address buffer Processor MAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B Module data bus TXI0 RXI0 TXI1 RXI1 External pins DREQ0 DREQ1 TEND0 TEND1 Interrupt signals DEND0A DEND0B DEND1A DEND1B Control logic DMAWER DMATCR DMACR0A DMACR0B DMACR1A DMACR1B DMABCR Data buffer Channel 1 Internal data bus Legend: DMAWER: DMATCR: DMABCR: DMACR: MAR: IOAR: ETCR: DMA write enable register DMA terminal control register DMA band control register (for all channels) DMA control register Memory address register I/O address register Executive transfer counter register Figure 7.1 Block Diagram of DMAC Rev.4.00 Sep. 18, 2008 Page 174 of 872 REJ09B0189-0400 Channel 0 IOAR0A Section 7 DMA Controller 7.1.3 Overview of Functions Tables 7.1 and 7.2 summarize DMAC functions in short address mode and full address mode, respectively. Table 7.1 Overview of DMAC Functions (Short Address Mode) Address Register Bit Length Transfer Mode Dual address mode • Sequential mode ⎯ 1-byte or 1-word transfer executed for one transfer request ⎯ Memory address incremented/decremented by 1 or 2 ⎯ 1 to 65536 transfers • Idle mode ⎯ 1-byte or 1-word transfer executed for one transfer request ⎯ Memory address fixed ⎯ 1 to 65536 transfers • Repeat mode ⎯ 1-byte or 1-word transfer executed for one transfer request ⎯ Memory address incremented/ decremented by 1 or 2 ⎯ After specified number of transfers (1 to 256), initial state is restored and operation continues • • • Transfer Source • Source Destination 16/24 TPU channel 0 to 24/16 2 compare match/input capture A interrupt SCI transmission complete interrupt SCI reception complete interrupt External request Rev.4.00 Sep. 18, 2008 Page 175 of 872 REJ09B0189-0400 Section 7 DMA Controller Table 7.2 Overview of DMAC Functions (Full Address Mode) Address Register Bit Length Transfer Mode • Normal mode Auto-request ⎯ Transfer request retained internally ⎯ Transfers continue for the specified number of times (1 to 65536) ⎯ Choice of burst or cycle steal transfer External request ⎯ 1-byte or 1-word transfer executed for one transfer request ⎯ 1 to 65536 transfers • Block transfer mode ⎯ Specified block size transfer executed for one transfer request ⎯ 1 to 65536 transfers ⎯ Either source or destination specifiable as block area ⎯ Block size: 1 to 256 bytes or words Transfer Source • Auto-request Source 24 Destination 24 • External request • TPU channel 0 to 24 2 compare match/input capture A interrupt SCI transmission complete interrupt SCI reception complete interrupt External request 24 • • • Rev.4.00 Sep. 18, 2008 Page 176 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.1.4 Pin Configuration Table 7.3 summarizes the DMAC pins. In short address mode, external request transfer, and transfer end output are not performed for channel A. When the DREQ pin is used, do not designate the corresponding port for output. With regard to the TEND pins, whether or not the corresponding port is used as a TEND pin can be specified by means of a register setting. Table 7.3 Channel 0 DMAC Pins Pin Name DMA request 0 DMA transfer end 0 Symbol DREQ0 TEND0 DREQ1 TEND1 I/O Input Output Input Output Function DMAC channel 0 external request DMAC channel 0 transfer end DMAC channel 1 external request DMAC channel 1 transfer end 1 DMA request 1 DMA transfer end 1 Rev.4.00 Sep. 18, 2008 Page 177 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.1.5 Register Configuration Table 7.4 summarizes the DMAC registers. Table 7.4 DMAC Registers Abbreviation R/W MAR0A IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B DMAWER DMACR0A DMACR0B DMACR1A DMACR1B DMABCR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Address* Bus Width 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 8 bits 8 bits 16 bits 16 bits 16 bits 16 bits 16 bits 8 bits Channel Name 0 Memory address register 0A I/O address register 0A Transfer count register 0A Memory address register 0B I/O address register 0B Transfer count register 0B 1 Memory address register 1A I/O address register 1A Transfer count register 1A Memory address register 1B I/O address register 1B Transfer count register 1B 0, 1 DMA write enable register DMA control register 0A DMA control register 0B DMA control register 1A DMA control register 1B DMA band control register Note: * Lower 16 bits of the address. Undefined H'FEE0 Undefined H'FEE4 Undefined H'FEE6 Undefined H'FEE8 Undefined H'FEEC Undefined H'FEEE Undefined H'FEF0 Undefined H'FEF4 Undefined H'FEF6 Undefined H'FEF8 Undefined H'FEFC Undefined H'FEFE H'00 H'00 H'00 H'00 H'00 H'00 H'0000 H'3F H'FF60 H'FF61 H'FF62 H'FF63 H'FF64 H'FF65 H'FF66 H'FDE8 DMA terminal control register DMATCR Module stop control register A MSTPCRA Rev.4.00 Sep. 18, 2008 Page 178 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.2 Register Descriptions (1) (Short Address Mode) Short address mode transfer can be performed for channels A and B independently. Short address mode transfer is specified for each channel by clearing the FAE bit in DMABCR to 0, as shown in table 7.5. Short address mode or full address mode can be selected for channels 1 and 0 independently by means of bits FAE1 and FAE0. Table 7.5 FAE0 0 Short Address Mode and Full Address Mode (For 1 Channel: Example of Channel 0) Description Short address mode specified (channels A and B operate independently) Channel 0A MAR0A IOAR0A ETCR0A DMACR0A MAR0B IOAR0B ETCR0B DMACR0B Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source, etc. Channel 0B Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source, etc. 1 Full address mode specified (channels A and B operate in combination) MAR0A MAR0B Specifies transfer source address Specifies transfer destination address Not used Not used Specifies number of transfers Specifies number of transfers (used in block transfer mode only) Specifies transfer size, mode, activation source, etc. Channel 0 IOAR0A IOAR0B ETCR0A ETCR0B DMACR0A DMACR0B Rev.4.00 Sep. 18, 2008 Page 179 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.2.1 Bit MAR R/W Bit MAR R/W Memory Address Register (MAR) : : : : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined 31 — 0 — 15 30 — 0 — 14 29 — 0 — 13 28 — 0 — 12 27 — 0 — 11 26 — 0 — 10 25 — 0 — 9 24 — 0 * * * * * * * * — R/W R/W R/W R/W R/W R/W R/W R/W 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 Initial value : Initial value : MAR is a 32-bit readable/writable register that specifies the transfer source address or destination address. The upper 8 bits of MAR are reserved: they are always read as 0, and cannot be modified. Whether MAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. MAR is incremented or decremented each time a byte or word transfer is executed, so that the address specified by MAR is constantly updated. For details, see section 7.2.4, DMA Control Register (DMACR). MAR is not initialized by a reset or in standby mode. 7.2.2 Bit IOAR R/W I/O Address Register (IOAR) : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : Rev.4.00 Sep. 18, 2008 Page 180 of 872 REJ09B0189-0400 Section 7 DMA Controller IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer source address or destination address. The upper 8 bits of the transfer address are automatically set to H'FF. Whether IOAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. IOAR is invalid in single address mode. IOAR is not incremented or decremented each time a transfer is executed, so that the address specified by IOAR is fixed. IOAR is not initialized by a reset or in standby mode. 7.2.3 Execute Transfer Count Register (ETCR) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of this register is different for sequential mode and idle mode on the one hand, and for repeat mode on the other. (1) Sequential Mode and Idle Mode Transfer Counter Bit ETCR R/W : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter (with a count range of 1 to 65536). ETCR is decremented by 1 each time a transfer is performed, and when the count reaches H'0000, the DTE bit in DMABCR is cleared, and transfer ends. Rev.4.00 Sep. 18, 2008 Page 181 of 872 REJ09B0189-0400 Section 7 DMA Controller (2) Repeat Mode Transfer Number Storage Bit ETCRH R/W : : * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W : 15 14 13 12 11 10 9 8 Initial value : Transfer Counter Bit ETCRL R/W : : * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W *: Undefined : 7 6 5 4 3 2 1 0 Initial value : In repeat mode, ETCR functions as transfer counter ETCRL (with a count range of 1 to 256) and transfer number storage register ETCRH. ETCRL is decremented by 1 each time a transfer is performed, and when the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this point, MAR is automatically restored to the value it had when the count was started. The DTE bit in DMABCR is not cleared, and so transfers can be performed repeatedly until the DTE bit is cleared by the user. ETCR is not initialized by a reset or in standby mode. 7.2.4 Bit DMACR R/W DMA Control Register (DMACR) : : : 7 DTSZ 0 R/W 6 DTID 0 R/W 5 RPE 0 R/W 4 DTDIR 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W Initial value : DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel. DMACR is initialized to H'00 by a reset, and in standby mode. Rev.4.00 Sep. 18, 2008 Page 182 of 872 REJ09B0189-0400 Section 7 DMA Controller Bit 7—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time. Bit 7 DTSZ 0 1 Description Byte-size transfer Word-size transfer (Initial value) Bit 6—Data Transfer Increment/Decrement (DTID): Selects incrementing or decrementing of MAR every data transfer in sequential mode or repeat mode. In idle mode, MAR is neither incremented nor decremented. Bit 6 DTID 0 Description MAR is incremented after a data transfer • • 1 • • When DTSZ = 0, MAR is incremented by 1 after a transfer When DTSZ = 1, MAR is incremented by 2 after a transfer When DTSZ = 0, MAR is decremented by 1 after a transfer When DTSZ = 1, MAR is decremented by 2 after a transfer (Initial value) MAR is decremented after a data transfer Bit 5—Repeat Enable (RPE): Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed. Bit 5 RPE 0 1 DMABCR DTIE 0 1 0 1 Description Transfer in sequential mode (no transfer end interrupt) Transfer in sequential mode (with transfer end interrupt) Transfer in repeat mode (no transfer end interrupt) Transfer in idle mode (with transfer end interrupt) (Initial value) For details of operation in sequential, idle, and repeat mode, see section 7.5.2, Sequential Mode, section 7.5.3, Idle Mode, and section 7.5.4, Repeat Mode. Bit 4—Data Transfer Direction (DTDIR): To specify the data transfer direction (source or destination). Rev.4.00 Sep. 18, 2008 Page 183 of 872 REJ09B0189-0400 Section 7 DMA Controller Bit 4 DTDIR 0 1 Description Transfer with MAR as source address and IOAR as destination address (Initial value) Transfer with IOAR as source address and MAR as destination address Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source). There are some differences in activation sources for channel A and for channel B. Channel A Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 1 1 0 1 1 0 0 Bit 0 DTF0 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 0 1 0 1 Description — — — — Activated by SCI channel 0 transmission complete interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmission complete interrupt Activated by SCI channel 1 reception complete interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt — — — — — (Initial value) Rev.4.00 Sep. 18, 2008 Page 184 of 872 REJ09B0189-0400 Section 7 DMA Controller Channel B Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 1 1 0 1 1 0 0 Bit 0 DTF0 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 0 1 0 1 Description — — Activated by DREQ pin falling edge input* Activated by DREQ pin low-level input Activated by SCI channel 0 transmission complete interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmission complete interrupt Activated by SCI channel 1 reception complete interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt — — — — — (Initial value) Note: * Detected as a low level in the first transfer after transfer is enabled. The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.10, DMAC Multi-Channel Operation. Rev.4.00 Sep. 18, 2008 Page 185 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.2.5 Bit DMA Band Control Register (DMABCR) : 15 FAE1 0 R/W 7 DTE1B 0 R/W 14 FAE0 0 R/W 6 DTE1A 0 R/W 13 — 0 R/W 5 DTE0B 0 R/W 12 — 0 R/W 4 DTE0A 0 R/W 11 DTA1B 0 R/W 3 DTIE1B 0 R/W 10 DTA1A 0 R/W 2 DTIE1A 0 R/W 9 DTA0B 0 R/W 1 DTIE0B 0 R/W 8 DTA0A 0 R/W 0 DTIE0A 0 R/W DMABCRH : Initial value : R/W Bit : : DMABCRL : Initial value : R/W : DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel. DMABCR is initialized to H'0000 by a reset, and in standby mode. Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short address mode or full address mode. In short address mode, channels 1A and 1B are used as independent channels. Bit 15 FAE1 0 1 Description Short address mode Full address mode (Initial value) Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short address mode or full address mode. In short address mode, channels 0A and 0B are used as independent channels. Bit 14 FAE0 0 1 Description Short address mode Full address mode (Initial value) Rev.4.00 Sep. 18, 2008 Page 186 of 872 REJ09B0189-0400 Section 7 DMA Controller Bit 13 and 12—Reserved: This bit is reserved and only 0 can be written to, writing 1 causes a malfunction error. Bits 11 to 8—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the CPU or DTC. When DTE = 1 and DTA = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the CPU or DTC regardless of the DTA bit setting. Bit 11—Data Transfer Acknowledge 1B (DTA1B): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1B data transfer factor setting. Bit 11 DTA1B 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bit 10—Data Transfer Acknowledge 1A (DTA1A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1A data transfer factor setting. Bit 10 DTA1A 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Rev.4.00 Sep. 18, 2008 Page 187 of 872 REJ09B0189-0400 Section 7 DMA Controller Bit 9—Data Transfer Acknowledge 0B (DTA0B): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0B data transfer factor setting. Bit 9 DTA0B 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bit 8—Data Transfer Acknowledge 0A (DTA0A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0A data transfer factor setting. Bit 8 DTA0A 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bits 7 to 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. The conditions for the DTE bit being cleared to 0 are as follows: • When initialization is performed • When the specified number of transfers have been completed in a transfer mode other than repeat mode • When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason When DTE = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the data transfer factor setting. When a request is issued by the activation source, DMA transfer is executed. The condition for the DTE bit being set to 1 is as follows: • When 1 is written to the DTE bit after the DTE bit is read as 0 Rev.4.00 Sep. 18, 2008 Page 188 of 872 REJ09B0189-0400 Section 7 DMA Controller Bit 7—Data Transfer Enable 1B (DTE1B): Enables or disables data transfer on channel 1B. Bit 7 DTE1B 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bit 6—Data Transfer Enable 1A (DTE1A): Enables or disables data transfer on channel 1A. Bit 6 DTE1A 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bit 5—Data Transfer Enable 0B (DTE0B): Enables or disables data transfer on channel 0B. Bit 5 DTE0B 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bit 4—Data Transfer Enable 0A (DTE0A): Enables or disables data transfer on channel 0A. Bit 4 DTE0A 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bits 3 to 0—Data Transfer End Interrupt Enable (DTIE): These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIE bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE bit to 1. Rev.4.00 Sep. 18, 2008 Page 189 of 872 REJ09B0189-0400 Section 7 DMA Controller Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1B transfer end interrupt. Bit 3 DTIE1B 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Bit 2—Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1A transfer end interrupt. Bit 2 DTIE1A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0B transfer end interrupt. Bit 1 DTIE0B 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Bit 0—Data Transfer Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0A transfer end interrupt. Bit 0 DTIE0A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Rev.4.00 Sep. 18, 2008 Page 190 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.3 Register Descriptions (2) (Full Address Mode) Full address mode transfer is performed with channels A and B together. For details of full address mode setting, see table 7.5. 7.3.1 Bit MAR R/W Bit MAR R/W Memory Address Register (MAR) : : : : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined 31 — 0 — 15 30 — 0 — 14 29 — 0 — 13 28 — 0 — 12 27 — 0 — 11 26 — 0 — 10 25 — 0 — 9 24 — 0 * * * * * * * * — R/W R/W R/W R/W R/W R/W R/W R/W 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 Initial value : Initial value : MAR is a 32-bit readable/writable register; MARA functions as the transfer source address register, and MARB as the destination address register. MAR is composed of two 16-bit registers, MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and cannot be modified. MAR is incremented or decremented each time a byte or word transfer is executed, so that the source or destination memory address can be updated automatically. For details, see section 7.3.4, DMA Control Register (DMACR). MAR is not initialized by a reset or in standby mode. 7.3.2 I/O Address Register (IOAR) IOAR is not used in full address transfer. Rev.4.00 Sep. 18, 2008 Page 191 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.3.3 Execute Transfer Count Register (ETCR) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The function of this register is different in normal mode and in block transfer mode. ETCR is not initialized by a reset or in standby mode. (1) Normal Mode ETCRA Transfer Counter Bit ETCR R/W : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each time a transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not used at this time. ETCRB ETCRB is not used in normal mode. Rev.4.00 Sep. 18, 2008 Page 192 of 872 REJ09B0189-0400 Section 7 DMA Controller (2) Block Transfer Mode ETCRA Holds block size Bit ETCRAH R/W : : * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W : 15 14 13 12 11 10 9 8 Initial value : Block size counter Bit ETCRAL R/W : : * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W *: Undefined : 7 6 5 4 3 2 1 0 Initial value : ETCRB Block Transfer Counter Bit ETCRB R/W : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH holds the block size. ETCRAL is decremented each time a 1-byte or 1-word transfer is performed, and when the count reaches H'00, ETCRAL is loaded with the value in ETCRAH. So by setting the block size in ETCRAH and ETCRAL, it is possible to repeatedly transfer blocks consisting of any desired number of bytes or words. ETCRB functions in block transfer mode, as a 16-bit block transfer counter. ETCRB is decremented by 1 each time a block is transferred, and transfer ends when the count reaches H'0000. Rev.4.00 Sep. 18, 2008 Page 193 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.3.4 DMA Control Register (DMACR) DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel. In full address mode, DMACRA and DMACRB have different functions. DMACR is initialized to H'0000 by a reset, and in standby mode. (1) DMACRA Bit : 15 DTSZ 0 R/W 14 SAID 0 R/W 13 SAIDE 0 R/W 12 BLKDIR 0 R/W 11 BLKE 0 R/W 10 — 0 R/W 9 — 0 R/W 8 — 0 R/W DMACRA : Initial value : R/W : (2) DMACRB Bit : 7 — 0 R/W 6 DAID 0 R/W 5 DAIDE 0 R/W 4 — 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W DMACRB : Initial value : R/W : Bit 15—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time. Bit 15 DTSZ 0 1 Description Byte-size transfer Word-size transfer (Initial value) Rev.4.00 Sep. 18, 2008 Page 194 of 872 REJ09B0189-0400 Section 7 DMA Controller Bit 14—Source Address Increment/Decrement (SAID) Bit 13—Source Address Increment/Decrement Enable (SAIDE): These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data transfer is performed. Bit 14 SAID 0 Bit 13 SAIDE 0 1 Description MARA is fixed MARA is incremented after a data transfer • • 1 0 1 When DTSZ = 0, MARA is incremented by 1 after a transfer When DTSZ = 1, MARA is incremented by 2 after a transfer (Initial value) MARA is fixed MARA is decremented after a data transfer • • When DTSZ = 0, MARA is decremented by 1 after a transfer When DTSZ = 1, MARA is decremented by 2 after a transfer Bit 12—Block Direction (BLKDIR) Bit 11—Block Enable (BLKE): These bits specify whether normal mode or block transfer mode is to be used. If block transfer mode is specified, the BLKDIR bit specifies whether the source side or the destination side is to be the block area. Bit 12 BLKDIR 0 1 Bit 11 BLKE 0 1 0 1 Description Transfer in normal mode Transfer in normal mode Transfer in block transfer mode, source side is block area (Initial value) Transfer in block transfer mode, destination side is block area For operation in normal mode and block transfer mode, see section 7.5, Operation. Bits 10 to 7—Reserved: Although these bits are readable/writable, only 0 should be written here. Rev.4.00 Sep. 18, 2008 Page 195 of 872 REJ09B0189-0400 Section 7 DMA Controller Bit 6—Destination Address Increment/Decrement (DAID) Bit 5—Destination Address Increment/Decrement Enable (DAIDE): These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed. Bit 6 DAID 0 Bit 5 DAIDE 0 1 Description MARB is fixed MARB is incremented after a data transfer • • 1 0 1 When DTSZ = 0, MARB is incremented by 1 after a transfer When DTSZ = 1, MARB is incremented by 2 after a transfer (Initial value) MARB is fixed MARB is decremented after a data transfer • • When DTSZ = 0, MARB is decremented by 1 after a transfer When DTSZ = 1, MARB is decremented by 2 after a transfer Bit 4—Reserved: Although this bit is readable/writable, only 0 should be written here. Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source). The factors that can be specified differ between normal mode and block transfer mode. • Normal Mode Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 1 1 0 1 1 * * Bit 0 DTF0 0 1 0 1 * 0 1 * Description — — Activated by DREQ pin falling edge input Activated by DREQ pin low-level input — Auto-request (cycle steal) Auto-request (burst) — *: Don't care (Initial value) Rev.4.00 Sep. 18, 2008 Page 196 of 872 REJ09B0189-0400 Section 7 DMA Controller • Block Transfer Mode Bit 3 DTF3 0 Bit DTF2 0 Bit 1 DTF1 0 1 1 0 1 1 0 0 Bit 0 DTF0 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 0 1 0 1 Description — — Activated by DREQ pin falling edge input* Activated by DREQ pin low-level input Activated by SCI channel 0 transmission complete interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmission complete interrupt Activated by SCI channel 1 reception complete interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt — — — — — (Initial value) Note: * Detected as a low level in the first transfer after transfer is enabled. The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.10, DMAC Multi-Channel Operation. Rev.4.00 Sep. 18, 2008 Page 197 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.3.5 Bit DMA Band Control Register (DMABCR) : 15 FAE1 0 R/W 7 DTME1 0 R/W 14 FAE0 0 R/W 6 DTE1 0 R/W 13 — 0 R/W 5 DTME0 0 R/W 12 — 0 R/W 4 DTE0 0 R/W 11 DTA1B 0 R/W 3 DTIE1B 0 R/W 10 DTA1A 0 R/W 2 DTIE1A 0 R/W 9 DTA0B 0 R/W 1 DTIE0B 0 R/W 8 DTA0A 0 R/W 0 DTIE0A 0 R/W DMABCRH : Initial value : R/W Bit : : DMABCRL : Initial value : R/W : DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel. DMABCR is initialized to H'0000 by a reset, and in standby mode. Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short address mode or full address mode. In full address mode, channels 1A and 1B are used together as a single channel. Bit 15 FAE1 0 1 Description Short address mode Full address mode (Initial value) Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short address mode or full address mode. In full address mode, channels 0A and 0B are used together as a single channel. Bit 14 FAE0 0 1 Description Short address mode Full address mode (Initial value) Rev.4.00 Sep. 18, 2008 Page 198 of 872 REJ09B0189-0400 Section 7 DMA Controller Bits 13 and 12—Reserved: This bit is reserved and only 0 can be written to, writing 1 causes a malfunction error. Bits 11 and 9—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the CPU or DTC. When the DTE = 1 and the DTA = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When the DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the CPU or DTC regardless of the DTA bit setting. The state of the DTME bit does not affect the above operations. Bit 11—Data Transfer Acknowledge 1 (DTA1B): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1 data transfer factor setting. Bit 11 DTA1B 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Rev.4.00 Sep. 18, 2008 Page 199 of 872 REJ09B0189-0400 Section 7 DMA Controller Bit 9—Data Transfer Acknowledge 0 (DTA0B): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0 data transfer factor setting. Bit 9 DTA0B 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bits 10 and 8—Reserved (DTA1A, DTA0A): Reserved bits in full address mode. Although these bits are readable/writable, only 0 should be written here. Bits 7 and 5—Data Transfer Master Enable (DTME): Together with the DTE bit, these bits control enabling or disabling of data transfer on the relevant channel. When both the DTME bit and the DTE bit are set to 1, transfer is enabled for the channel. If the relevant channel is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU. When the DTME bit is subsequently set to 1 again, the interrupted transfer is resumed. In block transfer mode, however, the DTME bit is not cleared by an NMI interrupt, and transfer is not interrupted. The conditions for the DTME bit being cleared to 0 are as follows: • When initialization is performed • When NMI is input in burst mode • When 0 is written to the DTME bit The condition for DTME being set to 1 is as follows: • When 1 is written to DTME after DTME is read as 0 Bit 7—Data Transfer Master Enable 1 (DTME1): Enables or disables data transfer on channel 1. Bit 7 DTME1 0 1 Description Data transfer disabled. In burst mode, cleared to 0 by an NMI interrupt Data transfer enabled (Initial value) Rev.4.00 Sep. 18, 2008 Page 200 of 872 REJ09B0189-0400 Section 7 DMA Controller Bit 5—Data Transfer Master Enable 0 (DTME0): Enables or disables data transfer on channel 0. Bit 5 DTME0 0 1 Description Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt (Initial value) Data transfer enabled Bits 6 and 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU. The conditions for the DTE bit being cleared to 0 are as follows: • When initialization is performed • When the specified number of transfers have been completed • When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason When DTE = 1 and DTME = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the data transfer factor setting. When a request is issued by the activation source, DMA transfer is executed. The condition for the DTE bit being set to 1 is as follows: • When 1 is written to the DTE bit after the DTE bit is read as 0 Bit 6—Data Transfer Enable 1 (DTE1): Enables or disables data transfer on channel 1. Bit 6 DTE1 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Rev.4.00 Sep. 18, 2008 Page 201 of 872 REJ09B0189-0400 Section 7 DMA Controller Bit 4—Data Transfer Enable 0 (DTE0): Enables or disables data transfer on channel 0. Bit 4 DTE0 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bits 3 and 1—Data Transfer Interrupt Enable B (DTIEB): These bits enable or disable an interrupt to the CPU or DTC when transfer is interrupted. If the DTIEB bit is set to 1 when DTME = 0, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC. A transfer break interrupt can be canceled either by clearing the DTIEB bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the DTME bit to 1. Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1 transfer break interrupt. Bit 3 DTIE1B 0 1 Description Transfer break interrupt disabled Transfer break interrupt enabled (Initial value) Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0 transfer break interrupt. Bit 1 DTIE0B 0 1 Description Transfer break interrupt disabled Transfer break interrupt enabled (Initial value) Rev.4.00 Sep. 18, 2008 Page 202 of 872 REJ09B0189-0400 Section 7 DMA Controller Bits 2 and 0—Data Transfer End Interrupt Enable A (DTIEA): These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If DTIEA bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIEA bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE bit to 1. Bit 2—Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1 transfer end interrupt. Bit 2 DTIE1A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Bit 0—Data Transfer Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0 transfer end interrupt. Bit 0 DTIE0A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Rev.4.00 Sep. 18, 2008 Page 203 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.4 7.4.1 Register Descriptions (3) DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions so that only specific bits of DMACR for the specific channel and also DMATCR and DMABCR can be changed to prevent inadvertent changes being made to registers other than those for the channel concerned. The restrictions applied by DMAWER are valid for the DTC. Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt, and reactivating channel 0A. The address register and count register area is re-set by the first DTC transfer, then the control register area is re-set by the second DTC chain transfer. When re-setting the control register area, perform masking by setting bits in DMAWER to prevent modification of the contents of the other channels. First transfer area MAR0A IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A DTC IOAR1A ETCR1A MAR1B IOAR1B ETCR1B DMAWER DMACR0A DMACR1A Second transfer area using chain transfer DMATCR DMACR0B DMACR1B DMABCR Figure 7.2 Areas for Register Re-Setting by DTC (Example: Channel 0A) Rev.4.00 Sep. 18, 2008 Page 204 of 872 REJ09B0189-0400 Section 7 DMA Controller Bit : 7 — 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 WE1B 0 R/W 2 WE1A 0 R/W 1 WE0B 0 R/W 0 WE0A 0 R/W DMAWER : Initial value : R/W : DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to the DMACR, DMABCR, and DMATCR by the DTC. DMAWER is initialized to H'00 by a reset, and in standby mode. Bits 7 to 4—Reserved: Read-only bits, always read as 0. Bit 3—Write Enable 1B (WE1B): Enables or disables writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR by the DTC. Bit 3 WE1B 0 1 Description Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are disabled (Initial value) Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are enabled Bit 2—Write Enable 1A (WE1A): Enables or disables writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR by the DTC. Bit 2 WE1A 0 1 Description Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are disabled (Initial value) Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are enabled Rev.4.00 Sep. 18, 2008 Page 205 of 872 REJ09B0189-0400 Section 7 DMA Controller Bit 1—Write Enable 0B (WE0B): Enables or disables writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR. Bit 1 WE0B 0 1 Description Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are disabled (Initial value) Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are enabled Bit 0—Write Enable 0A (WE0A): Enables or disables writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR. Bit 0 WE0A 0 1 Description Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled (Initial value) Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the DMAWER settings. These bits should be changed, if necessary, by CPU processing. In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0. To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable B for the channel to be reactivated. MAR, IOAR, and ETCR are always write-enabled regardless of the DMAWER settings. When modifying these registers, the channel for which the modification is to be made should be halted. Rev.4.00 Sep. 18, 2008 Page 206 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.4.2 Bit DMA Terminal Control Register (DMATCR) : : : 7 — 0 — 6 — 0 — 5 TEE1 0 R/W 4 TEE0 0 R/W 3 — 0 — 2 — 0 — 1 — 0 — 0 — 0 — DMATCR R/W Initial value : DMATCR is an 8-bit readable/writable register that controls enabling or disabling of DMAC transfer end pin output. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. DMATCR is initialized to H'00 by a reset, and in standby mode. Bits 7 and 6—Reserved: Read-only bits, always read as 0. Bit 5—Transfer End Enable 1 (TEE1): Enables or disables transfer end pin 1 (TEND1) output. Bit 5 TEE1 0 1 Description TEND1 pin output disabled TEND1 pin output enabled (Initial value) Bit 4—Transfer End Enable 0 (TEE0): Enables or disables transfer end pin 0 (TEND0) output. Bit 4 TEE0 0 1 Description TEND0 pin output disabled TEND0 pin output enabled (Initial value) The TEND pins are assigned only to channel B in short address mode. The transfer end signal indicates the transfer cycle in which the transfer counter reached 0, regardless of the transfer source. An exception is block transfer mode, in which the transfer end signal indicates the transfer cycle in which the block counter reached 0. Bits 3 to 0—Reserved: Read-only bits, always read as 0. Rev.4.00 Sep. 18, 2008 Page 207 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.4.3 Bit Module Stop Control Register A (MSTPCRA) : 7 0 R/W 6 0 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : MSTPCRA is an 8-bit readable/writable register that performs module stop mode control. When the MSTPA7 bit in MSTPCR is set to 1, the DMAC operation stops at the end of the bus cycle and a transition is made to module stop mode. For details, see section 17.5, Module Stop Mode. MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized by a manual reset and in software standby mode. Bit 7—Module Stop (MSTP7): Specifies the DMAC module stop mode. Bits 7 MSTPA7 0 1 Description DMAC module stop mode cleared DMAC module stop mode set (Initial value) Rev.4.00 Sep. 18, 2008 Page 208 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.5 7.5.1 Operation Transfer Modes Table 7.6 lists the DMAC modes. Table 7.6 DMAC Transfer Modes Transfer Source TPU channel 0 to 2 compare match/input capture A interrupt SCI transmission complete interrupt SCI reception complete interrupt External request External request Auto-request TPU channel 0 to 2 compare match/input capture A interrupt SCI transmission complete interrupt SCI reception complete interrupt External request • Max. 2-channel operation, combining channels A and B With auto-request, burst mode transfer or cycle steal transfer can be selected Remarks • Up to 4 channels can operate independently External request applies to channel B only Transfer Mode Short address mode Dual (1) Sequential mode • address (2) Idle mode mode (3) Repeat mode • • • • Full address mode (4) Normal mode (5) Block transfer mode • • • • • • • Rev.4.00 Sep. 18, 2008 Page 209 of 872 REJ09B0189-0400 Section 7 DMA Controller Operation in each mode is summarized below. (1) Sequential Mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. One address is specified as 24 bits, and the other as 16 bits. The transfer direction is programmable. (2) Idle Mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. One address is specified as 24 bits, and the other as 16 bits. The transfer source address and transfer destination address are fixed. The transfer direction is programmable. (3) Repeat Mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. When the specified number of transfers have been completed, the addresses and transfer counter are restored to their original settings, and operation is continued. No interrupt request is sent to the CPU or DTC. One address is specified as 24 bits, and the other as 16 bits. The transfer direction is programmable. (4) Normal Mode • Auto-request By means of register settings only, the DMAC is activated, and transfer continues until the specified number of transfers have been completed. An interrupt request can be sent to the CPU or DTC when transfer is completed. Both addresses are specified as 24 bits. ⎯ Cycle steal mode: The bus is released to another bus master every byte or word transfer. ⎯ Burst mode: The bus is held and transfer continued until the specified number of transfers have been completed. • External request In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. Both addresses are specified as 24 bits. Rev.4.00 Sep. 18, 2008 Page 210 of 872 REJ09B0189-0400 Section 7 DMA Controller (5) Block Transfer Mode In response to a single transfer request, a block transfer of the specified block size is carried out. This is repeated the specified number of times, once each time there is a transfer request. At the end of each single block transfer, one address is restored to its original setting. An interrupt request can be sent to the CPU or DTC when the specified number of block transfers have been completed. Both addresses are specified as 24 bits. 7.5.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7 summarizes register functions in sequential mode. Table 7.7 Register Functions in Sequential Mode Function Register 23 MAR 23 H'FF 15 ETCR 15 IOAR DTDIR = 0 DTDIR = 1 Initial Setting 0 Source Operation address register address register Destination Start address of Incremented/ address transfer destination decremented every register or transfer source transfer address register Fixed Start address of transfer source or transfer destination Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 0 Destination Source 0 Transfer counter Legend: MAR: Memory address register IOAR: I/O address register ETCR: Transfer count register DTDIR: Data transfer direction bit MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. Rev.4.00 Sep. 18, 2008 Page 211 of 872 REJ09B0189-0400 Section 7 DMA Controller IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. Figure 7.3 illustrates operation in sequential mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID ⋅ (2DTSZ ⋅ (N–1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.3 Operation in Sequential Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536. Rev.4.00 Sep. 18, 2008 Page 212 of 872 REJ09B0189-0400 Section 7 DMA Controller Transfer requests (activation sources) consist of external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 2 compare match/input capture A interrupts. External requests can be set for channel B only. Figure 7.4 shows an example of the setting procedure for sequential mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set transfer source and transfer destination addresses [2] [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Clear the RPE bit to 0 to select sequential mode. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts with the DTIE bit. • Set the DTE bit to 1 to enable transfer. Sequential mode setting Set DMABCRH Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Sequential mode Figure 7.4 Example of Sequential Mode Setting Procedure Rev.4.00 Sep. 18, 2008 Page 213 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.5.3 Idle Mode Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.8 summarizes register functions in idle mode. Table 7.8 Register Functions in Idle Mode Function Register 23 MAR 23 H'FF 15 ETCR 15 IOAR DTDIR = 0 DTDIR = 1 Initial Setting 0 Source Operation address register address register Destination Start address of Fixed address transfer destination register or transfer source address register Start address of Fixed transfer source or transfer destination Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 0 Destination Source 0 Transfer counter Legend: MAR: IOAR: ETCR: DTDIR: Memory address register I/O address register Transfer count register Data transfer direction bit MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is neither incremented nor decremented each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. Rev.4.00 Sep. 18, 2008 Page 214 of 872 REJ09B0189-0400 Section 7 DMA Controller Figure 7.5 illustrates operation in idle mode. MAR Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Figure 7.5 Operation in Idle Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536. Transfer requests (activation sources) consist of external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 2 compare match/input capture A interrupts. External requests can be set for channel B only. When the DMAC is used in single address mode, only channel B can be set. Rev.4.00 Sep. 18, 2008 Page 215 of 872 REJ09B0189-0400 Section 7 DMA Controller Figure 7.6 shows an example of the setting procedure for idle mode. Idle mode setting [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set DMABCRH Set transfer source and transfer destination addresses [2] Set number of transfers [3] [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Set the RPE bit to 1. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. • Set the DTIE bit to 1. • Set the DTE bit to 1 to enable transfer. Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Idle mode Figure 7.6 Example of Idle Mode Setting Procedure Rev.4.00 Sep. 18, 2008 Page 216 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.5.4 Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit in DMABCRL to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.9 summarizes register functions in repeat mode. Table 7.9 Register Functions in Repeat Mode Function Register 23 MAR DTDIR = 0 0 Source DTDIR = 1 Initial Setting Destination Start address of address transfer destination register or transfer source Operation Incremented/ decremented every transfer. Initial setting is restored when value reaches H'0000 Fixed address register 23 H'FF 15 IOAR 0 Destination Source address register transfers address register Start address of transfer source or transfer destination 7 ETCRH 0 Holds number of Number of transfers Fixed 7 ETCRL 0 Transfer counter Number of transfers Decremented every transfer. Loaded with ETCRH value when count reaches H'00 Legend: MAR: Memory address register IOAR: I/O address register ETCR: Transfer count register DTDIR: Data transfer direction bit Rev.4.00 Sep. 18, 2008 Page 217 of 872 REJ09B0189-0400 Section 7 DMA Controller MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. The number of transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when H'00 is set in both ETCRH and ETCRL, is 256. In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number of transfers. ETCRL is decremented by 1 each time a transfer is executed, and when its value reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR restoration operation is as shown below. MAR = MAR – (–1) DTID ·2 DTSZ · ETCRH The same value should be set in ETCRH and ETCRL. In repeat mode, operation continues until the DTE bit is cleared. To end the transfer operation, therefore, you should clear the DTE bit to 0. A transfer end interrupt request is not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the transfer after that terminated when the DTE bit was cleared. Rev.4.00 Sep. 18, 2008 Page 218 of 872 REJ09B0189-0400 Section 7 DMA Controller Figure 7.7 illustrates operation in repeat mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID ⋅ (2DTSZ ⋅ (N – 1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.7 Operation in Repeat mode Transfer requests (activation sources) consist of external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 2 compare match/input capture A interrupts. External requests can be set for channel B only. Rev.4.00 Sep. 18, 2008 Page 219 of 872 REJ09B0189-0400 Section 7 DMA Controller Figure 7.8 shows an example of the setting procedure for repeat mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in both ETCRH and ETCRL. [2] [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Set the RPE bit to 1. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. • Clear the DTIE bit to 0. • Set the DTE bit to 1 to enable transfer. Repeat mode setting Set DMABCRH Set transfer source and transfer destination addresses Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Repeat mode Figure 7.8 Example of Repeat Mode Setting Procedure Rev.4.00 Sep. 18, 2008 Page 220 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.5.5 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB. Table 7.10 summarizes register functions in normal mode. Table 7.10 Register Functions in Normal Mode Register 23 MARA 23 MARB 15 ETCRA Function 0 Source address Initial Setting Start address of transfer source Start address of transfer destination Operation Incremented/decremented every transfer, or fixed Incremented/decremented every transfer, or fixed register 0 Destination address register 0 Transfer counter Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 Legend: MARA: Memory address register A MARB: Memory address register B ETCRA: Transfer count register A MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented each time a transfer is performed, and when its value reaches H'0000 the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536. Rev.4.00 Sep. 18, 2008 Page 221 of 872 REJ09B0189-0400 Section 7 DMA Controller Figure 7.9 illustrates operation in normal mode. Address TA Transfer Address TB Address BA Legend: Address Address Address Address Where : Address BB TA TB BA BB LA LB N = LA = LB = LA + SAIDE ⋅ (–1)SAID ⋅ (2DTSZ ⋅ (N – 1)) = LB + DAIDE ⋅ (–1)DAID ⋅ (2DTSZ ⋅ (N – 1)) = Value set in MARA = Value set in MARB = Value set in ETCRA Figure 7.9 Operation in Normal Mode Transfer requests (activation sources) are external requests and auto-requests. With auto-request, the DMAC is only activated by register setting, and the specified number of transfers are performed automatically. With auto-request, cycle steal mode or burst mode can be selected. In cycle steal mode, the bus is released to another bus master each time a transfer is performed. In burst mode, the bus is held continuously until transfer ends. Rev.4.00 Sep. 18, 2008 Page 222 of 872 REJ09B0189-0400 Section 7 DMA Controller For setting details, see section 7.3.4, DMA Controller Register (DMACR). Figure 7.10 shows an example of the setting procedure for normal mode. [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the number of transfers in ETCRA. Set transfer source and transfer destination addresses [2] [4] Set each bit in DMACRA and DMACRB. • Set the transfer data size with the DTSZ bit. • Specify whether MARA is to be incremented, decremented, or fixed, with the SAID and SAIDE bits. • Clear the BLKE bit to 0 to select normal mode. • Specify whether MARB is to be incremented, decremented, or fixed, with the DAID and DAIDE bits. • Select the activation source with bits DTF3 to DTF0. [5] Read DTE = 0 and DTME = 0 in DMABCRL. Read DMABCRL [5] [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts with the DTIE bit. • Set both the DTME bit and the DTE bit to 1 to enable transfer. Normal mode setting Set DMABCRH Set number of transfers [3] Set DMACR [4] Set DMABCRL [6] Normal mode Figure 7.10 Example of Normal Mode Setting Procedure Rev.4.00 Sep. 18, 2008 Page 223 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.5.6 Block Transfer Mode In block transfer mode, transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in DMACRA to 1. In block transfer mode, a transfer of the specified block size is carried out in response to a single transfer request, and this is executed the specified number of times. The transfer source is specified by MARA, and the transfer destination by MARB. Either the transfer source or the transfer destination can be selected as a block area (an area composed of a number of bytes or words). Table 7.11 summarizes register functions in block transfer mode. Table 7.11 Register Functions in Block Transfer Mode Register 23 MARA 23 MARB Function 0 Source address Initial Setting Start address of transfer source Operation Incremented/decremented every transfer, or fixed register 0 Destination address register 7 0 Holds block ETCRAH Start address of Incremented/decremented transfer destination every transfer, or fixed Block size Fixed size Block size Block size Decremented every transfer; ETCRH value copied when count reaches H'00 Decremented every block transfer; transfer ends when count reaches H'0000 7 ETCRAL 15 ETCRB 0 counter 0 Block transfer counter Number of block transfers Legend: MARA: MARB: ETCRA: ETCRB: Memory address register A Memory address register B Transfer count register A Transfer count register B MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Rev.4.00 Sep. 18, 2008 Page 224 of 872 REJ09B0189-0400 Section 7 DMA Controller Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in DMACRA. To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL, and N in ETCRB. Figure 7.11 illustrates operation in block transfer mode when MARB is designated as a block area. Address TA 1st block Transfer Block area Address TB 2nd block Consecutive transfer of M bytes or words is performed in response to one request Address BB Nth block Address BA Legend: Address Address Address Address Where : TA TB BA BB LA LB N M = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (M · N – 1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7.11 Operation in Block Transfer Mode (BLKDIR = 0) Rev.4.00 Sep. 18, 2008 Page 225 of 872 REJ09B0189-0400 Section 7 DMA Controller Figure 7.12 illustrates operation in block transfer mode when MARA is designated as a block area. Address TA Block area Address BA Address TB Transfer Consecutive transfer of M bytes or words is performed in response to one request 2nd block 1st block Nth block Address BB Legend: Address Address Address Address Where : TA TB BA BB LA LB N M = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (N – 1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (M · N – 1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7.12 Operation in Block Transfer Mode (BLKDIR = 1) Rev.4.00 Sep. 18, 2008 Page 226 of 872 REJ09B0189-0400 Section 7 DMA Controller ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA is restored in accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR. ETCRB is decremented by 1 every block transfer, and when the count reaches H'0000 the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this point, an interrupt request is sent to the CPU or DTC. Figure 7.13 shows the operation flow in block transfer mode. Rev.4.00 Sep. 18, 2008 Page 227 of 872 REJ09B0189-0400 Section 7 DMA Controller Start (DTE = DTME = 1) No Transfer request? Yes Acquire bus Read address specified by MARA MARA = MARA + SAIDE · (–1)SAID · 2DTSZ Write to address specified by MARB MARB = MARB + DAIDE · (–1)DAID · 2DTSZ ETCRAL = ETCRAL – 1 No ETCRAL = H'00 Yes Release bus ETCRAL = ETCRAH BLKDIR = 0 Yes No MARB = MARB – DAIDE · (–1)DAID · 2DTSZ · ETCRAH MARA = MARA – SAIDE · (–1)SAID · 2DTSZ · ETCRAH ETCRB = ETCRB – 1 No ETCRB = H'0000 Yes Clear DTE bit to 0 to end transfer Figure 7.13 Operation Flow in Block Transfer Mode Transfer requests (activation sources) consist of external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 2 compare match/input capture A interrupts. Rev.4.00 Sep. 18, 2008 Page 228 of 872 REJ09B0189-0400 Section 7 DMA Controller For details, see section 7.3.4, DMA Control Register (DMACR). Figure 7.14 shows an example of the setting procedure for block transfer mode. Block transfer mode setting [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the block size in both ETCRAH and ETCRAL. Set the number of transfers in ETCRB. [4] Set each bit in DMACRA and DMACRB. • Set the transfer data size with the DTSZ bit. • Specify whether MARA is to be incremented, decremented, or fixed, with the SAID and SAIDE bits. • Set the BLKE bit to 1 to select block transfer mode. • Specify whether the transfer source or the transfer destination is a block area with the BLKDIR bit. • Specify whether MARB is to be incremented, decremented, or fixed, with the DAID and DAIDE bits. • Select the activation source with bits DTF3 to DTF0. [5] Read DTE = 0 and DTME = 0 in DMABCRL. Set DMABCRH Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Block transfer mode [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts to the CPU with the DTIE bit. • Set both the DTME bit and the DTE bit to 1 to enable transfer. Figure 7.14 Example of Block Transfer Mode Setting Procedure Rev.4.00 Sep. 18, 2008 Page 229 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.5.7 DMAC Activation Sources DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The activation sources that can be specified depend on the transfer mode and the channel, as shown in table 7.12. Table 7.12 DMAC Activation Sources Short Address Mode Channels 0A and 1A Channels 0B and 1B Full Address Mode Normal Mode X X X X X X X X X X X X Block Transfer Mode Activation Source Internal Interrupts TXI0 RXI0 TXI1 RXI1 TGI0A TGI1A TGI2A External Requests DREQ pin falling edge input DREQ pin low-level input Auto-request Legend: : Can be specified X : Cannot be specified (1) Activation by Internal Interrupt An interrupt request selected as a DMAC activation source can be sent simultaneously to the CPU and DTC. For details, see section 5, Interrupt Controller. With activation by an internal interrupt, the DMAC accepts the request independently of the interrupt controller. Consequently, interrupt controller priority settings are not accepted. If the DMAC is activated by a CPU interrupt source or an interrupt source that is not used as a DTC activation source (DTA = 1), the interrupt source flag is cleared automatically by the DMA transfer. With TXI and RXI interrupts, however, the interrupt source flag is not cleared unless the prescribed register is accessed in a DMA transfer. If the same interrupt is used as an activation source for more than one channel, the interrupt request flag is cleared when the highest-priority Rev.4.00 Sep. 18, 2008 Page 230 of 872 REJ09B0189-0400 Section 7 DMA Controller channel is activated first. Transfer requests for other channels are held pending in the DMAC, and activation is carried out in order of priority. When DTE = 0, such as after completion of a transfer, a request from the selected activation source is not sent to the DMAC, regardless of the DTA bit. In this case, the relevant interrupt request is sent to the CPU or DTC. In case of overlap with a CPU interrupt source or DTC activation source (DTA = 0), the interrupt request flag is not cleared by the DMAC. (2) Activation by External Request If an external request (DREQ pin) is specified as an activation source, the relevant port should be set to input mode in advance. Level sensing or edge sensing can be used for external requests. External request operation in normal mode (short address mode or full address mode) is described below. When edge sensing is selected, a 1-byte or 1-word transfer is executed each time a high-to-low transition is detected on the DREQ pin. The next transfer may not be performed if the next edge is input before transfer is completed. When level sensing is selected, the DMAC stands by for a transfer request while the DREQ pin is held high. While the DREQ pin is held low, transfers continue in succession, with the bus being released each time a byte or word is transferred. If the DREQ pin goes high in the middle of a transfer, the transfer is interrupted and the DMAC stands by for a transfer request. (3) Activation by Auto-Request Auto-request activation is performed by register setting only, and transfer continues to the end. With auto-request activation, cycle steal mode or burst mode can be selected. In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is transferred. DMA and CPU cycles usually alternate. In burst mode, the DMAC keeps possession of the bus until the end of the transfer, and transfer is performed continuously. Rev.4.00 Sep. 18, 2008 Page 231 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.5.8 Basic DMAC Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 7.15. In this example, wordsize transfer is performed from 16-bit , 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations. As with CPU cycles, DMA cycles conform to the bus controller settings. The address is not output to the external address bus in an access to on-chip memory or an internal I/O register. CPU cycle DMAC cycle (1-word transfer) CPU cycle T1 φ T2 T1 T2 T3 T1 T2 T3 Source address Address bus RD HWR LWR Destination address Figure 7.15 Example of DMA Transfer Bus Timing Rev.4.00 Sep. 18, 2008 Page 232 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.5.9 DMAC Bus Cycles (Dual Address Mode) (1) Short Address Mode Figure 7.16 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space. DMA read φ Address bus RD HWR LWR TEND DMA write DMA read DMA write DMA read DMA write DMA dead Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.16 Example of Short Address Mode Transfer A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released one or more bus cycles are inserted by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. In repeat mode, when TEND output is enabled, TEND output goes low in the transfer cycle in which the transfer counter reaches 0. Rev.4.00 Sep. 18, 2008 Page 233 of 872 REJ09B0189-0400 Section 7 DMA Controller (2) Full Address Mode (Cycle Steal Mode) Figure 7.17 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. DMA read φ Address bus RD HWR LWR TEND DMA write DMA read DMA write DMA read DMA write DMA dead Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.17 Example of Full Address Mode (Cycle Steal) Transfer Either a one-byte or a one-word transfer is performed for each transfer request, and after the transfer the bus is released. While the bus is released one bus cycle is inserted by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. Rev.4.00 Sep. 18, 2008 Page 234 of 872 REJ09B0189-0400 Section 7 DMA Controller (3) Full Address Mode (Burst Mode) Figure 7.18 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (burst mode) is performed from external 16-bit, 2-state access space to external 16bit, 2-state access space. DMA read φ Address bus RD HWR LWR TEND Bus release Burst transfer Last transfer cycle Bus release DMA write DMA read DMA write DMA read DMA write DMA dead Figure 7.18 Example of Full Address Mode (Burst Mode) Transfer In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. If a request from another higher-priority channel is generated after burst transfer starts, that channel has to wait until the burst transfer ends. If an NMI is generated while a channel designated for burst transfer is in the transfer enabled state, the DTME bit is cleared and the channel is placed in the transfer disabled state. If burst transfer has already been activated inside the DMAC, the bus is released on completion of a one-byte or one-word transfer within the burst transfer, and burst transfer is suspended. If the last transfer cycle of the burst transfer has already been activated inside the DMAC, execution continues to the end of the transfer even if the DTME bit is cleared. Rev.4.00 Sep. 18, 2008 Page 235 of 872 REJ09B0189-0400 Section 7 DMA Controller (4) Full Address Mode (Block Transfer Mode) Figure 7.19 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space. DMA read φ Address bus RD HWR LWR TEND Bus release Block transfer Bus release Last block transfer Bus release DMA write DMA read DMA write DMA dead DMA read DMA write DMA read DMA write DMA dead Figure 7.19 Example of Full Address Mode (Block Transfer Mode) Transfer A one-block transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released, one or more bus cycles are inserted by the CPU or DTC. In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a onestate DMA dead cycle is inserted after the DMA write cycle. One block is transmitted without interruption. NMI generation does not affect block transfer operation. Rev.4.00 Sep. 18, 2008 Page 236 of 872 REJ09B0189-0400 Section 7 DMA Controller (5) DREQ Pin Falling Edge Activation Timing Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7.20 shows an example of DREQ pin falling edge activated normal mode transfer. DMA read DMA write Bus release DMA read DMA write Bus release Bus release φ DREQ Address bus DMA control Channel Idle Request Transfer source Transfer destination Transfer source Transfer destination Read Write Idle Request Read Write Idle Request clear period Request clear period Minimum of 2 cycles [1] [2] [3] Minimum of 2 cycles [4] [5] [6] [7] Acceptance resumes Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the write cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.20 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA write cycle ends, acceptance resumes after the end of the write cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev.4.00 Sep. 18, 2008 Page 237 of 872 REJ09B0189-0400 Section 7 DMA Controller Figure 7.21 shows an example of DREQ pin falling edge activated block transfer mode transfer. 1 block transfer Bus release DMA read DMA write DMA Bus dead release 1 block transfer DMA read DMA write DMA dead Bus release φ DREQ Address bus DMA control Channel Idle Request Transfer source Transfer destination Transfer source Transfer destination Read Write Dead Idle Read Request Write Dead Idle Request clear period Request clear period Minimun of 2 cycles [1] [2] [3] Minimun of 2 cycles [4] [5] [6] [7] Acceptance resumes Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.21 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA dead cycle ends, acceptance resumes after the end of the dead cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev.4.00 Sep. 18, 2008 Page 238 of 872 REJ09B0189-0400 Section 7 DMA Controller (6) DREQ Level Activation Timing (Normal Mode) Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7.22 shows an example of DREQ level activated normal mode transfer. Bus release DMA read DMA write Bus release DMA read DMA write Bus release φ DREQ Address bus DMA control Channel Idle Request Transfer source Transfer destination Transfer source Transfer destination Read Write Idle Request Read Write Idle Request clear period Request clear period Minimum of 2 cycles [1] [2] [3] Minimum of 2 cycles [4] [5] [6] [7] Acceptance resumes Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMA cycle is started. [4] [7] Acceptance is resumed after the write cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.22 Example of DREQ Level Activated Normal Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the write cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev.4.00 Sep. 18, 2008 Page 239 of 872 REJ09B0189-0400 Section 7 DMA Controller Figure 7.23 shows an example of DREQ level activated block transfer mode transfer. 1 block transfer Bus release DMA read DMA right DMA Bus dead release 1 block transfer DMA read DMA right DMA dead Bus release ¿ DREQ Address bus DMA control Channel Idle Request Transfer source Transfer destination Transfer source Transfer destination Read Write Dead Idle Read Request Write Dead Idle Request clear period Request clear period Minimum of 2 cycles [1] [2] [3] Minimum of 2 cycles [4] [5] [6] [7] Acceptance resumes Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMA cycle is started. [4] [7] Acceptance is resumed after the dead cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7.23 Example of DREQ Level Activated Block Transfer Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. 7.5.10 DMAC Multi-Channel Operation The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table 7.13 summarizes the priority order for DMAC channels. Rev.4.00 Sep. 18, 2008 Page 240 of 872 REJ09B0189-0400 Section 7 DMA Controller Table 7.13 DMAC Channel Priority Order Short Address Mode Channel 0A Channel 0B Channel 1A Channel 1B Channel 1 Low Full Address Mode Channel 0 Priority High If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released the DMAC selects the highest-priority channel from among those issuing a request according to the priority order shown in table 7.13. During burst transfer, or when one block is being transferred in block transfer, the channel will not be changed until the end of the transfer. Figure 7.24 shows a transfer example in which transfer requests are issued simultaneously for channels 0A, 0B, and 1. DMA DMA write read DMA read φ Address bus RD HWR LWR DMA control Idle Read Channel 0A Channel 0B Channel 1 Bus release Write DMA write DMA read DMA write DMA read Idle Read Write Idle Read Write Read Request clear Request hold Request hold Selection Nonselection Request clear Request hold Bus release Selection Request clear Bus release Channel 1 transfer Channel 0A transfer Channel 0B transfer Figure 7.24 Example of Multi-Channel Transfer Rev.4.00 Sep. 18, 2008 Page 241 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.5.11 Relation between the DMAC, External Bus Requests, and the DTC There can be no break between a DMA cycle read and a DMA cycle write. This means that an external bus release cycle, or DTC cycle is not generated between the external read and external write in a DMA cycle. In the case of successive read and write cycles, such as in burst transfer or block transfer, an external bus released state may be inserted after a write cycle. Since the DTC has a lower priority than the DMAC, the DTC does not operate until the DMAC releases the bus. When DMA cycle reads or writes are accesses to on-chip memory or internal I/O registers, these DMA cycles can be executed at the same time as external bus release. However, simultaneous operation may not be possible when a write buffer is used. Rev.4.00 Sep. 18, 2008 Page 242 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.5.12 NMI Interrupts and DMAC When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and the DTME bit are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested. If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the CPU. The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again. Figure 7.25 shows the procedure for continuing transfer when it has been interrupted by an NMI interrupt on a channel designated for burst mode transfer. Resumption of transfer on interrupted channel [1] [2] [1] No Check that DTE = 1 and DTME = 0 in DMABCRL Write 1 to the DTME bit. DTE = 1 DTME = 0 Yes Set DTME bit to 1 [2] Transfer continues Transfer ends Figure 7.25 Example of Procedure for Continuing Transfer on Channel Interrupted by NMI Interrupt Rev.4.00 Sep. 18, 2008 Page 243 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.5.13 Forced Termination of DMAC Operation If the DTE bit for the channel currently operating is cleared to 0, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit. Figure 7.26 shows the procedure for forcibly terminating DMAC operation by software. [1] Clear the DTE bit in DMABCRL to 0. If you want to prevent interrupt generation after forced termination of DMAC operation, clear the DTIE bit to 0 at the same time. Forced termination of DMAC Clear DTE bit to 0 [1] Forced termination Figure 7.26 Example of Procedure for Forcibly Terminating DMAC Operation Rev.4.00 Sep. 18, 2008 Page 244 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.5.14 Clearing Full Address Mode Figure 7.27 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. [1] Clear both the DTE bit and the DTME bit in DMABCRL to 0; or wait until the transfer ends and the DTE bit is cleared to 0, then clear the DTME bit to 0. Also clear the corresponding DTIE bit to 0 at the same time. [2] Clear all bits in DMACRA and DMACRB to 0. [3] Clear the FAE bit in DMABCRH to 0. Initialize DMACR [2] Clearing full address mode Stop the channel [1] Clear FAE bit to 0 [3] Initialization; operation halted Figure 7.27 Example of Procedure for Clearing Full Address Mode Rev.4.00 Sep. 18, 2008 Page 245 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.6 Interrupts The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.14 shows the interrupt sources and their priority order. Table 7.14 Interrupt Source Priority Order Interrupt Name DEND0A DEND0B DEND1A DEND1B Interrupt Source Short Address Mode Interrupt due to end of transfer on channel 0A Interrupt due to end of transfer on channel 0B Interrupt due to end of transfer on channel 1A Interrupt due to end of transfer on channel 1B Full Address Mode Interrupt due to end of transfer on channel 0 Interrupt due to break in transfer on channel 0 Interrupt due to end of transfer on channel 1 Interrupt due to break in transfer on channel 1 Low Interrupt Priority Order High Enabling or disabling of each interrupt source is set by means of the DTIE bit for the corresponding channel in DMABCR, and interrupts from each source are sent to the interrupt controller independently. The relative priority of transfer end interrupts on each channel is decided by the interrupt controller, as shown in table 7.14. Figure 7.28 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is always generated when the DTIE bit is set to 1 while DTE bit is cleared to 0. DTE/ DTME Transfer end/transfer break interrupt DTIE Figure 7.28 Block Diagram of Transfer End/Transfer Break Interrupt In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to o while DTIEB bit is set to 1. In both short address mode and full address mode, DMABCR should be set so as to prevent the occurrence of a combination that constitutes a condition for interrupt generation during setting. Rev.4.00 Sep. 18, 2008 Page 246 of 872 REJ09B0189-0400 Section 7 DMA Controller 7.7 Usage Notes (1) DMAC Register Access during Operation Except for forced termination, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, the DMAC register should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below. (a) DMAC control starts one cycle before the bus cycle, with output of the internal address. Consequently, MAR is updated in the bus cycle before DMAC transfer. Figure 7.29 shows an example of the update timing for DMAC registers in dual address transfer mode. DMA transfer cycle DMA last transfer cycle DMA dead DMA read φ DMA Internal address DMA control DMA register operation Idle Transfer source Read Transfer destination Write DMA write DMA read DMA write Transfer source Idle Read Transfer destination Write Dead Idle [1] [2] [1] [2'] [3] [1] Transfer source address register MAR operation (incremented/decremented/fixed) Transfer counter ETCR operation (decremented) Block size counter ETCR operation (decremented in block transfer mode) [2] Transfer destination address register MAR operation (incremented/decremented/fixed) [2'] Transfer destination address register MAR operation (incremented/decremented/fixed) Block transfer counter ETCR operation (decremented, in last transfer cycle of a block in block transfer mode) [3] Transfer address register MAR restore operation (in block or repeat transfer mode) Transfer counter ETCR restore (in repeat transfer mode Block size counter ETCR restore (in block transfer mode) Notes: 1. In single address transfer mode, the update timing is the same as [1]. 2. The MAR operation is post-incrementing/decrementing of the DMA internal address value. Figure 7.29 DMAC Register Update Timing Rev.4.00 Sep. 18, 2008 Page 247 of 872 REJ09B0189-0400 Section 7 DMA Controller (b) If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC register is read as shown in figure 7.30. CPU longword read MAR upper word read φ DMA internal address DMA control DMA register operation Idle Transfe source Read Transfer destination Write MAR lower word read DMA transfer cycle DMA read DMA write Idle [1] [2] Note: The lower word of MAR is the updated value after the operation in [1]. Figure 7.30 Contention between DMAC Register Update and CPU Read (2) Module Stop When the MSTPA7 bit in MSTPCR is set to 1, the DMAC clock stops, and the module stop state is entered. However, 1 cannot be written to the MSTPA7 bit if any of the DMAC channels is enabled. This setting should therefore be made when DMAC operation is stopped. When the DMAC clock stops, DMAC register accesses can no longer be made. Since the following DMAC register settings are valid even in the module stop state, they should be invalidated, if necessary, before a module stop. • Transfer end/suspend interrupt (DTE = 0 and DTIE = 1) • TEND pin enable (TEE = 1) Rev.4.00 Sep. 18, 2008 Page 248 of 872 REJ09B0189-0400 Section 7 DMA Controller (3) Medium-Speed Mode When the DTA bit is 0, internal interrupt signals specified as DMAC transfer sources are edgedetected. In medium-speed mode, the DMAC operates on a medium-speed clock, while on-chip supporting modules operate on a high-speed clock. Consequently, if the period in which the relevant interrupt source is cleared by the CPU, DTC, or another DMAC channel, and the next interrupt is generated, is less than one state with respect to the DMAC clock (bus master clock), edge detection may not be possible and the interrupt may be ignored. Also, in medium-speed mode, DREQ pin sampling is performed on the rising edge of the mediumspeed clock. (4) Activation by Falling Edge on DREQ Pin DREQ pin falling edge detection is performed in synchronization with DMAC internal operations. The operation is as follows: [1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and switches to [2]. [2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3]. [3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and switches to [1]. After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is enabled is performed by detection of a low level. (5) Activation Source Acceptance At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that occurs before execution of the DMABCRL write to enable transfer. When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ pin low level remaining from the end of the previous transfer, etc. Rev.4.00 Sep. 18, 2008 Page 249 of 872 REJ09B0189-0400 Section 7 DMA Controller (6) Internal Interrupt after End of Transfer When the DTE bit is cleared to 0 by the end of transfer or an abort, the selected internal interrupt request will be sent to the CPU or DTC even if DTA is set to 1. Also, if internal DMAC activation has already been initiated when operation is aborted, the transfer is executed but flag clearing is not performed for the selected internal interrupt even if DTA is set to 1. An internal interrupt request following the end of transfer or an abort should be handled by the CPU as necessary. (7) Channel Re-Setting To reactivate a number of channels when multiple channels are enabled, use exclusive handling of transfer end interrupts, and perform DMABCR control bit operations exclusively. Note, in particular, that in cases where multiple interrupts are generated between reading and writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the DMABCR write data in the original interrupt handling routine will be incorrect, and the write may invalidate the results of the operations by the multiple interrupts. Ensure that overlapping DMABCR operations are not performed by multiple interrupts, and that there is no separation between read and write operations by the use of a bit-manipulation instruction. Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must first be read while cleared to 0 before the CPU can write a 1 to them. Rev.4.00 Sep. 18, 2008 Page 250 of 872 REJ09B0189-0400 Section 8 Data Transfer Controller (DTC) Section 8 Data Transfer Controller (DTC) 8.1 Overview The H8S/2214 Group includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 8.1.1 Features The features of the DTC are: • Transfer possible over any number of channels ⎯ Transfer information is stored in memory ⎯ One activation source can trigger a number of data transfers (chain transfer) • Wide range of transfer modes ⎯ Normal, repeat, and block transfer modes available ⎯ Incrementing, decrementing, and fixing of source and destination addresses can be selected • Direct specification of 16-Mbyte address space possible ⎯ 24-bit transfer source and destination addresses can be specified • Transfer can be set in byte or word units • A CPU interrupt can be requested for the interrupt that activated the DTC ⎯ An interrupt request can be issued to the CPU after one data transfer ends ⎯ An interrupt request can be issued to the CPU after the specified data transfers have completely ended • Activation by software is possible • Module stop mode can be set ⎯ The initial setting enables DTC registers to be accessed. DTC operation is halted by setting module stop mode. Rev.4.00 Sep. 18, 2008 Page 251 of 872 REJ09B0189-0400 Section 8 Data Transfer Controller (DTC) 8.1.2 Block Diagram Figure 8.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1. Internal address bus Interrupt controller DTC Register information On-chip RAM DTCERA to DTCERF, DTCERI CPU interrupt request DTC service request Legend: MRA, MRB: DTC mode registers A and B CRA, CRB: DTC transfer count registers A and B SAR: DTC source address register DAR: DTC destination address register DTCERA to DTCERF, DTCERI: DTC enable registers A to F and I DTVECR: DTC vector register Figure 8.1 Block Diagram of DTC Rev.4.00 Sep. 18, 2008 Page 252 of 872 REJ09B0189-0400 MRA MRB CRA CRB DAR SAR Interrupt request Control logic DTVECR Internal data bus Section 8 Data Transfer Controller (DTC) 8.1.3 Register Configuration Table 8.1 summarizes the DTC registers. Table 8.1 Name DTC mode register A DTC mode register B DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B DTC enable registers DTC vector register Module stop control register A DTC Registers Abbreviation MRA MRB SAR DAR CRA CRB DTCER DTVECR MSTPCRA R/W —* 2 —* 2 2 —* 2 —* 2 —* Initial Value Undefined Undefined Undefined Undefined Undefined Undefined H'00 H'00 H'3F 1 Address* 3 —* 3 —* 3 —* 3 —* 3 —* 3 —* —* 2 R/W R/W R/W H'FF16 to H'FE1B, H'FE1E H'FE1F H'FDE8 Notes: 1. Lower 16 bits of the address. 2. Registers within the DTC cannot be read or written to directly. 3. Register information is located in on-chip RAM addresses H'EBC0 to H'EFBF. It cannot be located in external memory space. When the DTC is used, do not clear the RAME bit in SYSCR to 0. Rev.4.00 Sep. 18, 2008 Page 253 of 872 REJ09B0189-0400 Section 8 Data Transfer Controller (DTC) 8.2 8.2.1 Bit Register Descriptions DTC Mode Register A (MRA) : 7 SM1 Undefined — 6 SM0 Undefined — 5 DM1 Undefined — 4 DM0 Undefined — 3 MD1 Undefined — 2 MD0 Undefined — 1 DTS Undefined — 0 Sz Undefined — Initial value : R/W : MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer. Bit 7 SM1 0 1 Bit 6 SM0 — 0 1 Description SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented, decremented, or left fixed after a data transfer. Bit 5 DM1 0 1 Bit 4 DM0 — 0 1 Description DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) Rev.4.00 Sep. 18, 2008 Page 254 of 872 REJ09B0189-0400 Section 8 Data Transfer Controller (DTC) Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 MD1 0 1 Bit 2 MD0 0 1 0 1 Description Normal mode Repeat mode Block transfer mode — Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. Bit 1 DTS 0 1 Description Destination side is repeat area or block area Source side is repeat area or block area Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred. Bit 0 Sz 0 1 Description Byte-size transfer Word-size transfer Rev.4.00 Sep. 18, 2008 Page 255 of 872 REJ09B0189-0400 Section 8 Data Transfer Controller (DTC) 8.2.2 Bit DTC Mode Register B (MRB) : 7 CHNE Undefined — 6 DISEL Undefined — 5 — Undefined — 4 — Undefined — 3 — Undefined — 2 — Undefined — 1 — Undefined — 0 — Undefined — Initial value: R/W : MRB is an 8-bit register that controls the DTC operating mode. Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER is not performed. Bit 7 CHNE 0 1 Description End of DTC data transfer (activation waiting state is entered) DTC chain transfer (new register information is read, then data is transferred) Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are disabled or enabled after a data transfer. Bit 6 DISEL 0 1 Description After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 (the DTC clears the interrupt source flag of the activating interrupt to 0) After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the interrupt source flag of the activating interrupt to 0) Bits 5 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2214 Group, and should always be written with 0. Rev.4.00 Sep. 18, 2008 Page 256 of 872 REJ09B0189-0400 Section 8 Data Transfer Controller (DTC) 8.2.3 Bit DTC Source Address Register (SAR) : 23 22 21 20 19 4 3 2 1 0 Initial value: R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ————— Unde- Unde- Unde- Unde- Undefined fined fined fined fined ————— SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 8.2.4 Bit DTC Destination Address Register (DAR) : 23 22 21 20 19 4 3 2 1 0 Initial value : R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ————— Unde- Unde- Unde- Unde- Undefined fined fined fined fined ————— DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. Rev.4.00 Sep. 18, 2008 Page 257 of 872 REJ09B0189-0400 Section 8 Data Transfer Controller (DTC) 8.2.5 Bit DTC Transfer Count Register A (CRA) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined ———————————————— CRAH CRAL CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). In repeat mode, CRAH holds the transfer count and CRAL functions as an 8-bit transfer counter (1 to 256). In block transfer mode, CRAH holds the block size and functions as an 8-bit block size counter (1 to 256). CRAL is decremented by 1 every time data is transferred and when the counter value becomes H'00 the contents of CRAH are transferred. This operation is repeated. 8.2.6 Bit DTC Transfer Count Register B (CRB) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined ———————————————— CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. Rev.4.00 Sep. 18, 2008 Page 258 of 872 REJ09B0189-0400 Section 8 Data Transfer Controller (DTC) 8.2.7 Bit DTC Enable Register (DTCER) : 7 DTCE7 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTCE0 0 R/W Initial value: R/W : The DTC enable registers comprise seven 8-bit readable/writable registers, DTCERA to DTCERG, with bits corresponding to the interrupt sources that can control enabling and disabling of DTC activation. These bits enable or disable DTC service for the corresponding interrupt sources. The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode. Bit n—DTC Activation Enable (DTCEn) Bit n DTCEn 0 Description DTC activation by this interrupt is disabled [Clearing conditions] • • 1 When the DISEL bit is 1 and the data transfer has ended When the specified number of transfers have ended (Initial value) DTC activation by this interrupt is enabled [Holding condition] • When the DISEL bit is 0 and the specified number of transfers have not ended (n = 7 to 0) A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources and DTCE bits is shown in table 8.4, together with the vector number generated for each interrupt controller. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. Rev.4.00 Sep. 18, 2008 Page 259 of 872 REJ09B0189-0400 Section 8 Data Transfer Controller (DTC) 8.2.8 Bit DTC Vector Register (DTVECR) : 7 0 R/(W)*1 6 0 R/W*2 5 0 R/W*2 4 0 R/W*2 3 0 R/W*2 2 0 R/W*2 1 0 R/W*2 0 0 R/W*2 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value: R/W : Notes: 1. Only 1 can be written to the SWDTE bit. 2. Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0. DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. DTVECR is initialized to H'00 by a reset and in hardware standby mode. Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. Bit 7 SWDTE 0 Description DTC software activation is disabled [Clearing conditions] • • 1 When the DISEL bit is 0 and the specified number of transfers have not ended When 0 is written to the DISEL bit after a software-activated data transfer end interrupt (SWDTEND) request has been sent to the CPU (Initial value) DTC software activation is enabled [Holding conditions] • • • When the DISEL bit is 1 and data transfer has ended When the specified number of transfers have ended During data transfer due to software activation Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + ((vector number) DR output Figure C.1 Port 1 Block Diagram (Pins P10 and P11) Rev.4.00 Sep. 18, 2008 Page 827 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams Reset Internal address bus WDDR1 Reset R Q D P1nDR C Modes 4 to 6 P1n * WDR1 Internal data bus R Q D P1nDDR C Bus controller Address output enable TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input External clock input Legend: WDDR1: Write to P1DDR WDR1: Write to P1DR RDR1: Read P1DR RPOR1: Read port 1 n = 2 or 3 Note: * Priority order: Output compare/PWM output > DR output Figure C.2 Port 1 Block Diagram (Pins P12 and P13) Rev.4.00 Sep. 18, 2008 Page 828 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1 P1n * TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Internal data bus Input capture input Interrupt controller IRQ interrupt input Legend: WDDR1: Write to P1DDR WDR1: Write to P1DR RDR1: Read P1DR RPOR1: Read port 1 n = 4 or 6 Note: * Priority order: Output compare/PWM output > DR output Figure C.3 Port 1 Block Diagram (Pins P14 and P16) Rev.4.00 Sep. 18, 2008 Page 829 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1 P1n * TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Internal data bus Input capture input External clock input Legend: WDDR1: WDR1: RDR1: RPOR1: n = 5 or 7 Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: Output compare/PWM output > DR output Figure C.4 Port 1 Block Diagram (Pins P15 and P17) Rev.4.00 Sep. 18, 2008 Page 830 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams C.2 Port 3 Block Diagrams Reset R Q D P3nDDR C WDDR3 Reset R Q D P3nDR C WDR3 Reset Open-drain control signal R Q D P3nODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data RDR3 P3n * RPOR3 Legend: WDDR3: Write to P3DDR WDR3: Write to P3DR WODR3: Write to P3ODR RDR3: Read P3DR RPOR3: Read port 3 RODR3: Read P3ODR n = 0 or 3: Note: * Priority order: Serial transmit data output > DR output Figure C.5 Port 3 Block Diagram (Pins P30 and P33) Rev.4.00 Sep. 18, 2008 Page 831 of 872 REJ09B0189-0400 Internal data bus Output enable signal Appendix C I/O Port Block Diagrams Reset R Q D P3nDDR C WDDR3 Reset * P3n R Q D P3nDR C WDR3 Reset Open-drain control signal R Q D P3nODR C WODR3 RODR3 Internal data bus Output enable signal SCI module Serial receive data enable RDR3 RPOR3 Serial receive data Legend: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR n = 1 or 4 WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Note: * Priority order: Serial receive data input > DR output Figure C.6 Port 3 Block Diagram (Pins P31 and P34) Rev.4.00 Sep. 18, 2008 Page 832 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams Reset R Q D P3nDDR C WDDR3 Reset R Q D P3nDR C WDR3 Open-drain control signal Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial clock output enable Serial clock output RDR3 Serial clock input enable Internal data bus Output enable signal P3n * RPOR3 Serial clock input Legend: WDDR3: Write to P3DDR WDR3: Write to P3DR WODR3: Write to P3ODR RDR3: Read P3DR RPOR3: Read port 3 RODR3: Read P3ODR n = 2 or 5 Interrupt controller IRQ interrupt input Note: * Priority order: Serial clock input > Serial clock output > DR output Figure C.7 Port 3 Block Diagram (Pins P32 and P35) Rev.4.00 Sep. 18, 2008 Page 833 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams Reset R Q D P36DDR C WDDR3 Reset P36 R Q D P36DR C WDR3 Reset Open-drain control signal R Q D P36ODR C WODR3 RODR3 RDR3 RPOR3 Internal data bus Output enable signal EXIRQ7 Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Figure C.8 Port 3 Block Diagram (Pin P36) Rev.4.00 Sep. 18, 2008 Page 834 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams C.3 Port 4 Block Diagram RPOR4 P4n Internal data bus EXIRQ0 to EXIRQ6 Legend: RPOR4: Read port 4 n= 0 to 4, 6, or 7 Figure C.9 Port 4 Block Diagram (Pins P40 to P44, P46, and P47) RPOR4 P45 Internal data bus A/D converter module Analog input Legend: RPOR4: Read port 4 Figure C.10 Port 4 Block Diagram (Pin P45) Rev.4.00 Sep. 18, 2008 Page 835 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams C.4 Port 7 Block Diagrams Reset WDDR7 Reset Mode 7 P7n Modes 4 to 6 R Q D P70DR C WDR7 Internal data bus Bus controller Chip select DMA controller DMA request input R Q D P70DDR C RDR7 RPOR7 Legend: WDDR7: Write to P7DDR WDR7: Write to P7DR Read P7DR RDR7: RPOR7: Read port 7 n = 0 or 1 Figure C.11 Port 7 Block Diagram (Pins P70 and P71) Rev.4.00 Sep. 18, 2008 Page 836 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams Reset R Q D P7nDDR C WDDR7 Reset Mode 7 R Q D P7nDR C WDR7 Internal data bus Bus controller Chip select DMA controller DMA transfer end enable DMA transfer end P7n * Modes 4 to 6 RDR7 RPOR7 Legend: WDDR7: Write to P7DDR WDR7: Write to P7DR Read P7DR RDR7: RPOR7: Read port 7 n = 2 or 3 Note: * Priority order: Compare match output > DR output Figure C.12 Port 7 Block Diagram (Pins P72 and P73) Rev.4.00 Sep. 18, 2008 Page 837 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams Reset R Q D P74DDR C WDDR7 Reset P74 R Q D P74DR C P74DTCOE WDR7 Internal data bus EXDTCE Manual reset input RDR7 RPOR7 Legend: WDDR7: WDR7: RDR7: RPOR7: Write to P7DDR Write to P7DR Read P7DR Read port 7 Figure C.13 Port 7 Block Diagram (Pin P74) Rev.4.00 Sep. 18, 2008 Page 838 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams Reset R Q D P7nDDR C WDDR7 Reset P7n R Q D P7nDR C P75MSOE or P76STPOE WDR7 Internal data bus EXMS or EXMSTP Manual reset input RDR7 RPOR7 Legend: WDDR7: Write to P7DDR WDR7: Write to P7DR Read P7DR RDR7: RPOR7: Read port 7 n = 5 or 6 Figure C.14 Port 7 Block Diagram (Pins P75 and P76) Rev.4.00 Sep. 18, 2008 Page 839 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams Reset R Q D P77DDR C WDDR7 Reset P77 R Q D P77DR C WDR7 RDR7 RPOR7 Legend: WDDR7: WDR7: RDR7: RPOR7: Write to P7DDR Write to P7DR Read P7DR Read port 7 Figure C.15 Port 7 Block Diagram (Pin P77) Rev.4.00 Sep. 18, 2008 Page 840 of 872 REJ09B0189-0400 Internal data bus Appendix C I/O Port Block Diagrams C.5 Port 9 Block Diagram RPOR9 P96 Internal data bus D/A converter module Output enable Analog output Legend: RPOR9: Read port 9 Figure C.16 Port 9 Block Diagram (Pin P96) Rev.4.00 Sep. 18, 2008 Page 841 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams C.6 Port A Block Diagrams Reset R Q D PA0PCR C WPCRA RPCRA Reset Output enable signal R Q D PA0DDR C WDDRA Reset R Q D PA0DR C WDRA Reset Open-drain control signal R Q D PA0ODR C WODRA RODRA Bus controller Address output enable Modes 4 to 6 PA0 * RDRA RPORA Legend: WDDRA: WDRA: WODRA: WPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR RDRA: RPORA: RODRA: RPCRA: Read PADR Read port A Read PAODR Read PAPCR Note: * Priority order: Address output > DR output Figure C.17 Port A Block Diagram (Pin PA0) Rev.4.00 Sep. 18, 2008 Page 842 of 872 REJ09B0189-0400 Internal address bus Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D PA1PCR C WPCRA RPCRA Reset Output enable signal R Q D PA1DDR C WDDRA Reset R Q D PA1DR C WDRA Reset Open-drain control signal R Q D PA1ODR C WODRA RODRA PA1 * Modes 4 to 6 Internal address bus Bus controller Address output enable SCI module Serial transmit enable Serial transmit data RDRA RPORA Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Note: * Priority order: Address output > Serial transmit data > DR output Figure C.18 Port A Block Diagram (Pin PA1) Rev.4.00 Sep. 18, 2008 Page 843 of 872 REJ09B0189-0400 Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D PA2PCR C WPCRA RPCRA Reset R Q D PA2DDR C Output enable signal WDDRA Reset R Q D PA2DR C WDRA Reset Open-drain control signal R Q D PA2ODR C WODRA RODRA Bus controller Address output enable SCI module Serial receive data enable PA2 * Modes 4 to 6 RDRA RPORA Internal address bus Serial receive data Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Note: * Priority order: Address output > Serial receive data input > DR output Figure C.19 Port A Block Diagram (Pin PA2) Rev.4.00 Sep. 18, 2008 Page 844 of 872 REJ09B0189-0400 Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D PA3PCR C WPCRA RPCRA Reset R Q D PA3DDR C WDDRA Reset R Q D PA3DR C WDRA Reset Open-drain control signal R Q D PA3ODR C WODRA RODRA Bus controller Address output enable SCI module Serial clock output enable Serial clock output Serial clock input enable Output enable signal PA3 * Modes 4 to 6 RDRA RPORA Internal address bus Internal data bus Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Serial clock input Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Note: * Priority order: Address output > Serial clock input > Serial clock output > DR output Figure C.20 Port A Block Diagram (Pin PA3) Rev.4.00 Sep. 18, 2008 Page 845 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams C.7 Port B Block Diagram Reset R Q D PBnPCR C WPCRB RPCRB Reset Output enable signal R Q D PBnDDR C WDDRB Reset R Q D PBnDR C WDRB PBn * Modes 4 to 6 Internal address bus Internal data bus Bus controller Address output enable RDRB RPORB Legend: WDDRB: WDRB: WPCRB: RDRB: RPORB: RPCRB: n = 0 to 7 Write to PBDDR Write to PBDR Write to PBPCR Read PBDR Read port B Read PBPCR Note: * Priority order: Address output > DR output Figure C.21 Port B Block Diagram (Pins PB0 to PB7) Rev.4.00 Sep. 18, 2008 Page 846 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams C.8 Port C Block Diagram Reset R Q D PCnPCR C WPCRC RPCRC Modes 4 and 5* Reset Output enable signal S R Q D PCnDDR C WDDRC Reset R Q D PCnDR C WDRC PCn Mode 7 Modes 4 to 6 RDRC RPORC Legend: WDDRC: WDRC: WPCRC: RDRC: RPORC: RPCRC: n = 0 to 7 Write to PCDDR Write to PCDR Write to PCPCR Read PCDR Read port C Read PCPCR Note: * Set priority Figure C.22 Port C Block Diagram (Pins PC0 to PC7) Rev.4.00 Sep. 18, 2008 Page 847 of 872 REJ09B0189-0400 Internal address bus Internal data bus Appendix C I/O Port Block Diagrams C.9 Port D Block Diagram Reset Internal upper data bus WPCRD RPCRD Reset R Q D PDnDDR C WDDRD Reset R Q D PDnDR C WDRD External address write PDn Mode 7 Modes 4 to 6 External address upper write External address lower write RDRD RPORD External address upper read External address lower read Legend: WDDRD: WDRD: WPCRD: RDRD: RPORD: RPCRD: n = 0 to 7 Write to PDDDR Write to PDDR Write to PDPCR Read PDDR Read port D Read PDPCR Figure C.23 Port D Block Diagram (Pins PD0 to PD7) Rev.4.00 Sep. 18, 2008 Page 848 of 872 REJ09B0189-0400 Internal lower data bus R Q D PDnPCR C Appendix C I/O Port Block Diagrams C.10 Port E Block Diagram Reset Internal upper data bus Internal lower data bus R Q D PEnPCR C WPCRE RPCRE Reset R Q D PEnDDR C WDDRE Reset R Q D PEnDR C WDRE 8-bit bus mode RDRE External address write PEn Mode 7 Modes 4 to 6 RPORE External address lower read Legend: WDDRE: WDRE: WPCRE: RDRE: RPORE: RPCRE: n = 0 to 7 Write to PEDDR Write to PEDR Write to PEPCR Read PEDR Read port E Read PEPCR Figure C.24 Port E Block Diagram (Pins PE0 to PE7) Rev.4.00 Sep. 18, 2008 Page 849 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams C.11 Port F Block Diagrams Reset WDDRF Reset PF0 R Q D PF0DR C Modes 4 to 6 WDRF Internal data bus Bus controller BRLE output Bus request input Interrupt controller IRQ interrupt input R Q D PF0DDR C RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.25 Port F Block Diagram (Pin PF0) Rev.4.00 Sep. 18, 2008 Page 850 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams Reset Internal data bus Bus controller BRLE output Bus request acknowledge output R Q D PF1DDR C WDDRF Reset PF1 * Modes 4 to 6 R Q D PF1DR C WDRF RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Note: * Priority order: Bus request acknowledge output > DR output Figure C.26 Port F Block Diagram (Pin PF1) Rev.4.00 Sep. 18, 2008 Page 851 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams Reset R Q D PF2DDR C WDDRF Reset PF2 R Q D PF2DR C Modes 4 to 6 WDRF Bus controller Wait enable RDRF RPORF Internal data bus Wait input Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.27 Port F Block Diagram (Pin PF2) Rev.4.00 Sep. 18, 2008 Page 852 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams Reset R Q D PF3DDR C WDDRF Reset PF3 R Q D PF3DR C WDRF Bus controller LWR output 16 bit bus mode Modes 4 to 6 RDRF RPORF Interrupt controller IRQ interrupt input Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.28 Port F Block Diagram (Pin PF3) Rev.4.00 Sep. 18, 2008 Page 853 of 872 REJ09B0189-0400 Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D PFnDDR C WDDRF Reset Mode 7 PFn Modes 4 to 6 R Q D PFnDR C WDRF Internal data bus Bus controller PF4: HWR output PF5: RD output PF6: AS output Modes 4 to 6 RDRF RPORF Legend: WDDRF: Write to PFDDR WDRF: Write to PFDR RDRF: Read PFDR RPORF: Read port F n = 4 to 6 Figure C.29 Port F Block Diagram (Pins PF4 to PF6) Rev.4.00 Sep. 18, 2008 Page 854 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams Modes 4 to 6* Reset S R Q D PF7DDR C WDDRF Reset PF7 R Q D PF7DR C WDRF φ RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Note: * Set priority Figure C.30 Port F Block Diagram (Pin PF7) Rev.4.00 Sep. 18, 2008 Page 855 of 872 REJ09B0189-0400 Internal data bus Appendix C I/O Port Block Diagrams C.12 Port G Block Diagrams Reset R Q D PG0DDR C WDDRG Reset PG0 R Q D PG0DR C WDRG RDRG RPORG Interrupt controller IRQ interrupt input Legend: WDDRG: WDRG: RDRG: RPORG: Write to PGDDR Write to PGDR Read PGDR Read port G Figure C.31 Port G Block Diagram (Pin PG0) Rev.4.00 Sep. 18, 2008 Page 856 of 872 REJ09B0189-0400 Internal data bus Appendix C I/O Port Block Diagrams Reset R Q D PG1DDR C WDDRG Reset Mode 7 PG1 Modes 4 to 6 R Q D PG1DR C WDRG Internal data bus Bus controller Chip select Interrupt controller IRQ interrupt input RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: Write to PGDDR Write to PGDR Read PGDR Read port G Figure C.32 Port G Block Diagram (Pin PG1) Rev.4.00 Sep. 18, 2008 Page 857 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams Reset R Q D PGnDDR C WDDRG Reset Mode 7 PGn Modes 4 to 6 R Q D PGnDR C WDRG Internal data bus Bus controller Chip select RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: n = 2 or 3 Write to PGDDR Write to PGDR Read PGDR Read port G Figure C.33 Port G Block Diagram (Pins PG2 and PG3) Rev.4.00 Sep. 18, 2008 Page 858 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams Modes Modes 4 and 5 6 and 7 Reset WDDRG Reset Mode 7 PG4 Modes 4 to 6 R Q D PG4DR C WDRG Internal data bus SR Q D PG4DDR C Bus controller Chip select RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: Write to PGDDR Write to PGDR Read PGDR Read port G Figure C.34 Port G Block Diagram (Pin PG4) Rev.4.00 Sep. 18, 2008 Page 859 of 872 REJ09B0189-0400 Appendix C I/O Port Block Diagrams Rev.4.00 Sep. 18, 2008 Page 860 of 872 REJ09B0189-0400 Appendix D Pin States Appendix D Pin States D.1 Port States in Each Processing State I/O Port States in Each Processing State MCU PowerOperating On Manual Mode Reset Reset 4 to 7 T T keep keep Hardware Software Standby Standby Mode, Mode Watch Mode T T keep keep BusReleased State keep keep Program Execution State, Sleep Mode, Subsleep Mode I/O port I/O port Table D.1 Port Name Pin Name P17 to P14 P13/TIOCD0/TCLKB/A23 7 P12/TIOCC0/TCLKA/A22 P11/TIOCB0/A21 Address output selected by AEn bit Port selected P10/TIOCA0/A20 4 to 6 T keep T [OPE = 0] T [OPE = 1] keep keep keep [OPE = 0] T [OPE = 1] keep keep keep T keep keep [DDR · OPE = 0] T [DDR · OPE = 1] H [DAOEn = 1] keep [DAOEn = 0] T keep [OPE = 0] T [OPE = 1] keep keep T Address output 4 to 6 7 T T L T keep keep keep T T T keep keep T I/O port I/O port Address output Address output 4, 5 selected by AEn 6 bit Port selected Port 3 Port 4 P77 to P74 P73/CS7 P72/CS6 P71/CS5 P70/CS4 4 to 6 4 to 7 4 to 7 4 to 7 7 4 to 6 T* T T T T T keep keep T keep keep keep T T T T T T keep keep T keep keep T I/O port I/O port Input port I/O port I/O port [DDR = 0] Input port [DDR = 1] CS7 to CS4 Input port P96/DA0 4 to 7 T T T keep Port A 7 Address output 4, 5 selected by AEn 6 bit Port selected 4 to 6 T L T keep keep T T keep T I/O port Address output T* keep T keep I/O port Rev.4.00 Sep. 18, 2008 Page 861 of 872 REJ09B0189-0400 Appendix D Pin States MCU PowerOperating On Manual Mode Reset Reset 7 Address output selected by AEn bit Port selected Port C 4, 5 6 T L T keep keep Hardware Software Standby Standby Mode, Mode Watch Mode T T keep [OPE = 0] T [OPE = 1] keep keep [OPE = 0] T [OPE = 1] keep [DDR · OPE = 0] T [DDR · OPE = 1] keep keep T keep keep T keep [DDR = 0] Input port [DDR = 1] H [DDR = 0] Input port [DDR = 1] H [OPE = 0] T [OPE = 1] H keep keep keep [OPE = 0] T [OPE = 1] H BusReleased State keep T Program Execution State, Sleep Mode, Subsleep Mode I/O port Address output Port Name Pin Name Port B 4 to 6 4, 5 T* L keep keep T T keep T I/O port Address output 6 T keep T T [DDR = 0] Input port [DDR = 1] Address output I/O port Data bus I/O port I/O port Data bus I/O port [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output AS, RD, HWR 7 Port D 4 to 6 7 Port E 8-bit bus 16-bit bus 4 to 6 4 to 6 7 PF7/φ 4 to 6 T T T T T T Clock output keep T keep keep T keep T T T T T T keep T keep keep T keep [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output T [[DDR = 0] T Input port [DDR = 1] Clock output keep T 7 T PF6/AS, PF5/RD, PF4/HWR 4 to 6 H H T 7 PF3/LWR/IRQ3 8-bit bus 16-bit bus 7 4 to 6 4 to 6 T T keep keep T T T T keep keep keep T I/O port I/O port I/O port LWR (Mode 4) keep H H (Modes 5 and 6) T Rev.4.00 Sep. 18, 2008 Page 862 of 872 REJ09B0189-0400 Appendix D Pin States MCU PowerOperating On Manual Mode Reset Reset 4 to 6 T keep Hardware Software Standby Standby Mode, Mode Watch Mode T [WAITE = 0] keep [WAITE = 1] T keep [BRLE = 0] keep [BRLE = 1] H keep [BRLE = 0] keep [BRLE = 1] T keep [DDR · OPE = 0] T [DDR · OPE = 1] H BusReleased State [WAITE = 0] keep [WAITE = 1] T keep L Program Execution State, Sleep Mode, Subsleep Mode [WAITE = 0] I/O port [WAITE = 1] WAIT I/O port [BRLE = 0] I/O port [BRLE = 1] BACK I/O port [BRLE = 0] I/O port [BRLE = 1] BREQ I/O port [DDR = 0] Input port [DDR = 1] CS0 (In sleep mode and subsleep mode: H) I/O port [DDR = 0] Input port [DDR = 1] CS1 to CS3 I/O port I/O port Port Name Pin Name PF2/WAIT 7 PF1/BACK 4 to 6 T T keep keep T T 7 PF0/BREQ/IREQ2 4 to 6 T T keep keep T T keep T 7 PG4/CS0 4, 5 6 T H T keep keep T T keep T 7 PG3/CS1 PG2/CS2 PG1/CS3/IRQ7 4 to 6 T T keep keep T T keep [DDR · OPE = 0] T [DDR · OPE = 1] H keep keep keep T 7 PG0/IRQ6 4 to 7 T T keep keep T T keep keep Legend: H: High level L: Low level T: High impedance keep: Input port becomes high-impedance, output port retains state DDR Data direction register OPE: Output port enable WAITE: Wait input enable BRLE: Bus release enable Note: * L in modes 4 and 5 (address output) Rev.4.00 Sep. 18, 2008 Page 863 of 872 REJ09B0189-0400 Appendix D Pin States Rev.4.00 Sep. 18, 2008 Page 864 of 872 REJ09B0189-0400 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Appendix E Timing of Transition to and Recovery from Hardware Standby Mode E.1 Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at least 10 states before the STBY signal goes low, as shown below. RES must remain low until STBY signal goes low (delay from STBY low to RES high: 0 ns or more). STBY t1 ≥ 10 tcyc RES t2 ≥ 0 ns Figure E.1 Timing of Transition to Hardware Standby Mode (2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained, RES does not have to be driven low as in (1). E.2 Timing of Recovery from Hardware Standby Mode Drive the RES signal low and the NMI signal high approximately 100 ns or more before STBY goes high to execute a power-on reset. STBY t ≥ 100 ns RES tOSC Figure E.2 Timing of Recovery from Hardware Standby Mode Rev.4.00 Sep. 18, 2008 Page 865 of 872 REJ09B0189-0400 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Rev.4.00 Sep. 18, 2008 Page 866 of 872 REJ09B0189-0400 Appendix F Product Code Lineup Appendix F Product Code Lineup Table F.1 H8S/2214 Product Code Lineup Part No. HD6432214 Mark Code 6432214(***)TE Package Product Type H8S/2214 Masked ROM version 100-pin TQFP (TFP-100B) *1 100-pin TQFP (TFP-100BV) 6432214(***)TEV 6432214(***)TF 6432214(***)TFV* 6432214(***)BQ 6432214(***)BR 6432214(***)BRV* 1 1 100-pin TQFP (TFP-100G) 100-pin TQFP (TFP-100GV) 112-pin TFBGA (TBP-112A) *1 112-pin TFBGA (TBP-112AV) 6432214(***)BQV 112-pin LFBGA (BP-112) 112-pin LFBGA (BP-112V) 100-pin TQFP (TFP-100B) 1 F-ZTAT version HD64F2214 64F2214TE16 64F2214TE16V* 64F2214TF16 1 64F2214TF16V* 100-pin TQFP (TFP-100BV) 100-pin TQFP (TFP-100G) 100-pin TQFP (TFP-100GV) 112-pin P-TFBGA (TBP-112A) 112-pin P-TFBGA (TBP-112AV) 112-pin P-LFBGA (BP-112) 112-pin P-LFBGA (BP-112V) 64F2214BQ16 64F2214BQ16V* 64F2214BR16 1 64F2214BR16V* 1 Legend: (***) indicates ROM code Notes: The above list includes products under developing. For the status for each product, please contact your Renesas sales agency. 1. Pb-free version Rev.4.00 Sep. 18, 2008 Page 867 of 872 REJ09B0189-0400 Appendix F Product Code Lineup Rev.4.00 Sep. 18, 2008 Page 868 of 872 REJ09B0189-0400 Appendix G Package Dimensions Appendix G Package Dimensions The package dimension that is shown in the Renesas Semiconductor Package Data Book has priority. Figures G.1 to G.4 show the H8S/2214 package dimensions. JEITA Package Code P-TQFP100-14x14-0.50 RENESAS Code PTQP0100KA-A Previous Code TFP-100B/TFP-100BV MASS[Typ.] 0.5g HD *1 D 51 75 76 50 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp b1 c1 *2 HE E c Terminal cross section ZE Reference Dimension in Millimeters Symbol 100 26 A2 1 ZD Index mark 25 θ F A1 L L1 Detail F e *3 y bp x M D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1 Nom Max 14 14 1.00 15.8 16.0 16.2 15.8 16.0 16.2 1.20 0.00 0.10 0.20 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 8° 0° 0.5 0.08 0.10 1.00 1.00 0.4 0.5 0.6 1.0 Min Figure G.1 TFP-100B, TFP-100BV Package Dimensions A Rev.4.00 Sep. 18, 2008 Page 869 of 872 REJ09B0189-0400 c Appendix G Package Dimensions JEITA Package Code P-TQFP100-12x12-0.40 RENESAS Code PTQP0100LC-A Previous Code MASS[Typ.] TFP-100G/TFP-100GV 0.4g HD *1 D 75 51 76 50 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp *2 HE E b1 Reference Dimension in Millimeters Symbol c1 c 100 26 1 ZD Index mark 25 F ZE Terminal cross section θ e *3 y bp A1 L L1 x M Detail F D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1 Nom Max 12 12 1.00 13.8 14.0 14.2 13.8 14.0 14.2 1.20 0.00 0.10 0.20 0.13 0.18 0.23 0.16 0.12 0.17 0.22 0.15 0° 8° 0.4 0.07 0.10 1.2 1.2 0.4 0.5 0.6 1.0 Min A2 Figure G.2 TFP-100G, TFP-100GA Package Dimensions Rev.4.00 Sep. 18, 2008 Page 870 of 872 REJ09B0189-0400 A c Appendix G Package Dimensions JEITA Package Code T-TFBGA112-10x10-0.80 RENESAS Code TTBG0112GA-A Previous Code TBP-112A/TBP-112AV MASS[Typ.] 0.2g D wSA wSB ×4 v y1 S S A y S e ZD A L K J H e A1 E Reference Symbol Dimension in Millimeters B G F E D C B A Min Nom 10.00 10.00 Max D E v w A ZE 0.20 0.30 1.20 0.35 0.45 0.40 0.80 0.50 0.55 0.08 0.10 0.2 0.45 A1 e b x y y1 SD SE ZD ZE 1 2 3 4 5 6 7 8 9 10 11 φb φ ×M S A B 1.00 1.00 Figure G.3 TBP-112A, TBP-112AV Package Dimensions Rev.4.00 Sep. 18, 2008 Page 871 of 872 REJ09B0189-0400 Appendix G Package Dimensions JEITA Package Code P-LFBGA112-10x10-0.80 RENESAS Code PLBG0112GA-A Previous Code BP-112/BP-112V MASS[Typ.] 0.3g D wSA wSB ×4 v y1 S S A y S e ZD A L K J A1 E H Reference Symbol Dimension in Millimeters e B G F E D C B A Min Nom 10.00 10.00 Max D E v w A ZE 0.15 0.20 1.40 0.35 0.45 0.40 0.80 0.50 0.55 0.08 0.10 0.2 0.45 A1 e b x y y1 SD SE ZD ZE 1 2 3 4 5 6 7 8 9 10 11 φb φ ×M S A B 1.00 1.00 Figure G.4 BP-112, BP-112V Package Dimensions Rev.4.00 Sep. 18, 2008 Page 872 of 872 REJ09B0189-0400 Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2214 Group Publication Date: 1st Edition, April 2000 Rev.4.00, September 18, 2008 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. © 2008. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: (21) 5877-1818, Fax: (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: 2265-6688, Fax: 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: (2) 2715-2888, Fax: (2) 3518-3399 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: 6213-0200, Fax: 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: (2) 796-3115, Fax: (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: 7955-9390, Fax: 7955-9510 Colophon 6.2 H8S/2214 Group Hardware Manual