H8S2357F

REJ09B0138-0600H The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 H8S/2357 Group, H8S/2357F-ZTATTM, H8S/2398F-ZTATTM Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series Rev. 6.00 Revision date: Oct. 28, 2004 www.renesas.com Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. 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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass-through current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product’s state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system’s operation is not guaranteed if they are accessed. Preface This LSI is a single-chip microcomputer with a 32-bit H8S/2000 CPU core, and a set of on-chip peripheral functions required for system configuration. This LSI is equipped with ROM, RAM, a bus controller, a data transfer controller (DTC), a programmable pulse generator (PPG), three types of timers, a serial communication interface (SCI), a D/A converter, an A/D converter, and I/O ports as on-chip peripheral functions. This LSI is suitable for use as an embedded microcomputer for high-level control systems. Its on-chip ROM is flash memory (F-ZTAT TM*), PROM (ZTAT®*), or masked ROM that provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. This is particularly applicable to application devices with specifications that will most probably change. Note: * F-ZTAT is a trademark of Renesas Technology, Corp. ZTAT is a registered trademark of Renesas Technology, Corp. Target Users: This manual was written for users who will be using the H8S/2357 Group in the design of application systems. Members of this audience are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8S/2357 Group to the above audience. Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of the instruction set. Notes on reading this manual: • In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions, and electrical characteristics. • In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual. • In order to understand the details of a register when its name is known The addresses, bits, and initial values of the registers are summarized in Appendix B, Internal I/O Register. Examples: Bit order: The MSB is on the left and the LSB is on the right. Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/eng/ H8S/2357 Group user's manuals: Manual Title H8S/2357 Group Hardware Manual H8S/2600 Series, H8S/2000 Series Programming Manual Document No. This manual REJ09B0139 Rev.6.00 Oct.28.2004 page i of xxiv REJ09B0138-0600H User's manuals for development tools: Manual Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual H8S, H8/300 Series Simulator/Debugger (for Windows) User's Manual H8S, H8/300 Series High-performance Embedded Workshop User's Manual Document No. REJ10B0058 ADE-702-037 ADE-702-201 Application Note: Manual Title H8S Family Technical Q & A Document No. REJ05B0397 Rev.6.00 Oct.28.2004 page ii of xxiv REJ09B0138-0600H Main Revisions for This Edition Item 1.1 Overview Table 1-1 Overview Page 5 Revision (See Manual for Details) Product lineup HD64F2398F20T*3 and HD64F2398TE20T*3 added 5V version F-ZTAT Version* HD64F2357F20 HD64F2357TE20 HD64F2398F20 HD64F2398TE20 HD64F2398F20T * 3 HD64F2398TE20T* 3 Note 3 added as follows Note: 3. For the HD64F2398F20T and HD64F2398TE20T only, the maximum number of times the flash memory can be reprogrammed is 1,000. 4.1.3 Exception Vector Table 72 Description amended In modes 6 and 7 the on-chip ROM ...In this case, clearing the EAE bit in BCRL enables the 128-kbyte (256-kbytes)* area comprising address H’000000 to H’01FFFF (H’03FFFF)* to be used. 6.6.1 When DDS = 1 Figure 6-28 DACK Output Timing when DDS = 1 (Example of DRAM Access) 149 Figure 6-28 amended HWR, (WE) Write D15 to D0 6.6.2 When DDS = 0 Figure 6-29 DACK Output Timing when DDS = 0 (Example of DRAM Access) 150 Figure 6-29 amended HWR, (WE) Write D15 to D0 6.8.2 Usage Notes Figure 6-35(a) Example of Idle Cycle Operation in RAS Down Mode (ICIS1 = 1) Figure 6-35(b) Example of Idle Cycle Operation in RAS Down Mode (ICIS0 = 1) 156 Figure 6-35(a) amended External read TI T1 T2 T3 DRAM TcI Figure 6-35(b) amended External read TI T1 T2 T3 DRAM TcI Rev.6.00 Oct.28.2004 page iii of xxiv REJ09B0138-0600H Item 9.8.2 Register Configuration Page 303 Revision (See Manual for Details) Note added Port A MOS Pull-Up Control Register (PAPCR) (ON-Chip ROM Version Only) Bit : 7 6 5 4 3 2 1 0 PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial value : R/W Note: : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390. 304 Port A Open Drain Control Register (PAODR) (ON-Chip ROM Version Only) Bit : 7 6 5 4 3 2 1 0 PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial value : R/W Note: : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390. 9.9.2 Register Configuration (OnChip ROM Version Only) 309 Note added Port B MOS Pull-Up Control Register (PBPCR) (ON-Chip ROM Version Only) Bit : 7 6 5 4 3 2 1 0 PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : R/W Note: : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390. 9.10.2 Register Configuration (OnChip ROM Version Only) 314 Note added Port C MOS Pull-Up Control Register (PCPCR) (ON-Chip ROM Version Only) Bit : 7 6 5 4 3 2 1 0 PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : R/W Note: : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390. 9.11.2 Register Configuration (OnChip ROM Version Only) 319 Note added Port D MOS Pull-Up Control Register (PDPCR) (ON-Chip ROM Version Only) Bit : 7 6 5 4 3 2 1 0 PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : R/W Note: : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390. Rev.6.00 Oct.28.2004 page iv of xxiv REJ09B0138-0600H Item 9.12.2 Register Configuration Page 324 Revision (See Manual for Details) Note added Port E MOS Pull-Up Control Register (PEPCR) (ON-Chip ROM Version Only) Bit : 7 6 5 4 3 2 1 0 PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : R/W Note: : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390. 10.4.5 Cascaded Operation Figure10-23 Example of Cascaded Operation (2) 10.7 Usage Note Figure 10-57 Contention between TCNT Write and Overflow 11.3.1 Overview Figure 11-2 PPG Output Operation 383 Figure 10-23 amended (Before) TCLKA → (After) TCLKC (Before) TCLKB → (After) TCLKD 409 Figure 10-57 amended TCFV flag Prohibited 423 Figure 11-2 amended DDR 14.2.8 Bit Rate Register (BRR) Table 14-4 BRR Setting for Various Bit Rates (Clocked Synchronous Mode) 19.15.1 Features 481 Note deleted form table 14-4 619 • Reprogramming capability Description amended Depending on the product, the maximum number of times the flash memory can be reprogrammed is either 100 or 1,000.  Reprogrammable up to 100 times: HD64F2398TE, HD64F2398F  Reprogrammable up to 1,000 times: HD64F2398TET, HD64F2398FT Rev.6.00 Oct.28.2004 page v of xxiv REJ09B0138-0600H Item 19.18.2 Program-Verify Mode Figure 19-48 Program/ProgramVerify Flowchart Page 639 Revision (See Manual for Details) Figure 19-48 amended, note *6 added Write pulse application subroutine Sub-routine write pulse Enable WDT Set PSU bit in FLMCR1 Wait (y) µs Set P bit in FLMCR1 n=1 Wait (z1) µs or (z2) µs or (z3) µs Clear P bit in FLMCR1 Wait (α) µs Clear PSU bit in FLMCR1 Wait (β) µs Disable WDT End sub *6 *6 *5*6 m=0 Write 128-byte data in RAM reprogram *1 data area consecutively to flash memory Sub-routine-call Write pulse (z1) µs or (z2) µs Set PV bit in FLMCR1 Wait (γ) µs H'FF dummy write to verify address Note: 7 Write Pulse Width Number of Writes (n) Write Time (z) µs 1 z1 2 z1 3 z1 4 z1 5 z1 6 z1 7 z2 8 z2 9 z2 10 z2 11 z2 12 z2 13 z2 . . . . . . 998 z2 999 z2 1000 z2 Note: Use a (z3) µs write pulse for additional programming. Increment address Wait (ε) µs Read verify data *6 *2 n←n+1 *6 See note 7 regarding pulse width switching. *6 *6 Start of programming Start Set SWE bit in FLMCR1 Wait (x) µs Store 128-byte program data in program data area and reprogram data area *6 *4 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. Read data = verify data? OK 6≥n? NG m=1 NG OK Additional program data computation Transfer additional program data to additional program data area Reprogram data computation Transfer reprogram data to reprogram data area 128-byte data verification completed? OK Clear PV bit in FLMCR1 Wait (η) µs *6 NG *4 *3 *4 NG RAM Program data area (128 bytes) Reprogram data area (128 bytes) 6≥n? Additional program data area (128 bytes) OK Sequentially write 128-byte data in additional program data area in RAM to flash memory Write Pulse (z3 µs additional write pulse) NG *1 *6 m = 0? OK Clear SWE bit in FLMCR1 Wait (θ) µs End of programming n ≥ N? OK Clear SWE bit in FLMCR1 *6 Wait (θ) µs Programming failure NG *6 22.3.6 Flash Memory Characteristics Table 22-21 Flash Memory Characteristics (HD64F2398F20, HD64F2398TE20) Table 22-22 Flash Memory Characteristics (HD64F2398F20T, HD64F2398TE20T) 724 Table 22-21 title amended 726 Table 22-22 added Rev.6.00 Oct.28.2004 page vi of xxiv REJ09B0138-0600H Item Table A-6 Instruction Execution Cycles 827 Table A-6 amended Page A.5 Bus States during Instruction Execution Instruction R:W:M aa:8 R:W aa:8 1 2 3 4 5 6 7 8 9 JMP @@aa:8 Advanced R:W NEXT Revision (See Manual for Details) JSR @ERn JSR @aa:24 Advanced R:W NEXT Advanced R:W 2nd Rev.6.00 Oct.28.2004 page vii of xxiv REJ09B0138-0600H JSR @@aa:8 Advanced R:W NEXT Internal operation, R:W EA 1 state R:W EA W:W:M stack (H) W:W stack (L) Internal operation, R:W EA W:W:M stack (H) W:W stack (L) 1 state R:W:M aa:8 R:W aa:8 W:W:M stack (H) W:W stack (L) R:W EA Item G. Product Code Lineup Table G-2 H8S/2398, H8S/2394, H8S/2392, H8S/2390 Group Product Code Lineup Page 1014 Revision (See Manual for Details) Table G-2 amended Product Type H8S/2398 Masked ROM F-ZTAT Product Code Mark Code Package (Package Code) HD6432398 HD6432398TE*1 120-pin TQFP (TFP-120) 128-pin QFP (FP-128B) HD6432398F*1 HD64F2398 HD64F2398TE*1 120-pin TQFP (TFP-120) 128-pin QFP (FP-128B) HD64F2398F*1 HD64F2398TET 120-pin TQFP (TFP-120) HD64F2398FT 128-pin QFP (FP-128B) H. Package Dimensions Figure H-1 TFP-120 Package Dimension 1015 Figure H-1 replaced Rev.6.00 Oct.28.2004 page viii of xxiv REJ09B0138-0600H Contents Section 1 Overview...............................................................................................................................1 1.1 1.2 1.3 Overview....................................................................................................................................................................... 1 Block Diagram..............................................................................................................................................................6 Pin Description ............................................................................................................................................................. 7 1.3.1 Pin Arrangement ............................................................................................................................................. 7 1.3.2 Pin Functions in Each Operating Mode......................................................................................................... 11 1.3.3 Pin Functions................................................................................................................................................. 15 Section 2 CPU.....................................................................................................................................21 2.1 Overview..................................................................................................................................................................... 21 2.1.1 Features ......................................................................................................................................................... 21 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU ........................................................................... 22 2.1.3 Differences from H8/300 CPU......................................................................................................................22 2.1.4 Differences from H8/300H CPU................................................................................................................... 23 2.2 CPU Operating Modes ............................................................................................................................................... 23 2.2.1 Advanced Mode............................................................................................................................................. 23 2.3 Address Space............................................................................................................................................................. 26 2.4 Register Configuration ............................................................................................................................................... 27 2.4.1 Overview ....................................................................................................................................................... 27 2.4.2 General Registers........................................................................................................................................... 27 2.4.3 Control Registers........................................................................................................................................... 28 2.4.4 Initial Register Values ................................................................................................................................... 29 2.5 Data Formats............................................................................................................................................................... 30 2.5.1 General Register Data Formats ..................................................................................................................... 30 2.5.2 Memory Data Formats................................................................................................................................... 32 2.6 Instruction Set............................................................................................................................................................. 33 2.6.1 Overview ....................................................................................................................................................... 33 2.6.2 Instructions and Addressing Modes ..............................................................................................................34 2.6.3 Table of Instructions Classified by Function................................................................................................. 35 2.6.4 Basic Instruction Formats..............................................................................................................................41 2.7 Addressing Modes and Effective Address Calculation ..............................................................................................41 2.7.1 Addressing Mode........................................................................................................................................... 41 2.7.2 Effective Address Calculation....................................................................................................................... 44 2.8 Processing States ........................................................................................................................................................47 2.8.1 Overview ....................................................................................................................................................... 47 2.8.2 Reset State ..................................................................................................................................................... 48 2.8.3 Exception-Handling State ............................................................................................................................. 48 2.8.4 Program Execution State ............................................................................................................................... 50 2.8.5 Bus-Released State ........................................................................................................................................50 2.8.6 Power-Down State......................................................................................................................................... 50 2.9 Basic Timing............................................................................................................................................................... 51 2.9.1 Overview ....................................................................................................................................................... 51 2.9.2 On-Chip Memory (ROM, RAM) ..................................................................................................................51 2.9.3 On-Chip Supporting Module Access Timing................................................................................................52 2.9.4 External Address Space Access Timing........................................................................................................53 2.10 Usage Note ................................................................................................................................................................. 53 2.10.1 TAS Instruction ............................................................................................................................................. 53 Rev.6.00 Oct.28.2004 page ix of xxiv REJ09B0138-0600H Section 3 MCU Operating Modes ......................................................................................................55 3.1 Overview..................................................................................................................................................................... 55 3.1.1 Operating Mode Selection (H8S/2357 F-ZTAT Only) ................................................................................. 55 3.1.2 Operating Mode Selection (ZTAT, Masked ROM, ROMless Version, and H8S/2398 F-ZTAT) ............... 56 3.1.3 Register Configuration ..................................................................................................................................57 Register Descriptions..................................................................................................................................................57 3.2.1 Mode Control Register (MDCR)................................................................................................................... 57 3.2.2 System Control Register (SYSCR) ............................................................................................................... 57 3.2.3 System Control Register 2 (SYSCR2) (F-ZTAT Version Only) ..................................................................58 Operating Mode Descriptions..................................................................................................................................... 60 3.3.1 Mode 1........................................................................................................................................................... 60 3.3.2 Mode 2 (H8S/2398 F-ZTAT Only) ............................................................................................................... 60 3.3.3 Mode 3 (H8S/2398 F-ZTAT Only) ............................................................................................................... 60 3.3.4 Mode 4 (On-Chip ROM Disabled Expansion Mode) ................................................................................... 60 3.3.5 Mode 5 (On-Chip ROM Disabled Expansion Mode) ................................................................................... 60 3.3.6 Mode 6 (On-Chip ROM Enabled Expansion Mode)..................................................................................... 60 3.3.7 Mode 7 (Single-Chip Mode) ......................................................................................................................... 61 3.3.8 Modes 8 and 9 ............................................................................................................................................... 61 3.3.9 Mode 10 (H8S/2357 F-ZTAT Only) ............................................................................................................. 61 3.3.10 Mode 11 (H8S/2357 F-ZTAT Only) ............................................................................................................. 61 3.3.11 Modes 12 and 13 (H8S/2357 F-ZTAT Only)................................................................................................61 3.3.12 Mode 14 (H8S/2357 F-ZTAT Only) ............................................................................................................. 61 3.3.13 Mode 15 (H8S/2357 F-ZTAT Only)............................................................................................................. 61 Pin Functions in Each Operating Mode......................................................................................................................62 Memory Map in Each Operating Mode......................................................................................................................62 3.2 3.3 3.4 3.5 Section 4 Exception Handling ............................................................................................................71 4.1 Overview..................................................................................................................................................................... 71 4.1.1 Exception Handling Types and Priority ........................................................................................................71 4.1.2 Exception Handling Operation ......................................................................................................................72 4.1.3 Exception Vector Table................................................................................................................................. 72 Reset ........................................................................................................................................................................... 74 4.2.1 Overview ....................................................................................................................................................... 74 4.2.2 Reset Types ................................................................................................................................................... 74 4.2.3 Reset Sequence..............................................................................................................................................75 4.2.4 Interrupts after Reset ..................................................................................................................................... 76 4.2.5 State of On-Chip Supporting Modules after Reset Release ..........................................................................76 Traces ......................................................................................................................................................................... 76 Interrupts..................................................................................................................................................................... 77 Trap Instruction ..........................................................................................................................................................78 Stack Status after Exception Handling ....................................................................................................................... 78 Notes on Use of the Stack........................................................................................................................................... 79 4.2 4.3 4.4 4.5 4.6 4.7 Section 5 Interrupt Controller.............................................................................................................81 5.1 Overview..................................................................................................................................................................... 81 5.1.1 Features ......................................................................................................................................................... 81 5.1.2 Block Diagram............................................................................................................................................... 82 5.1.3 Pin Configuration ..........................................................................................................................................82 5.1.4 Register Configuration ..................................................................................................................................83 Register Descriptions..................................................................................................................................................83 5.2.1 System Control Register (SYSCR) ............................................................................................................... 83 5.2 Rev.6.00 Oct.28.2004 page x of xxiv REJ09B0138-0600H 5.3 5.4 5.5 5.6 5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK) ..................................................................................... 84 5.2.3 IRQ Enable Register (IER) ........................................................................................................................... 85 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..............................................................................86 5.2.5 IRQ Status Register (ISR) ............................................................................................................................. 86 Interrupt Sources......................................................................................................................................................... 87 5.3.1 External Interrupts......................................................................................................................................... 87 5.3.2 Internal Interrupts ..........................................................................................................................................88 5.3.3 Interrupt Exception Handling Vector Table ..................................................................................................88 Interrupt Operation ..................................................................................................................................................... 91 5.4.1 Interrupt Control Modes and Interrupt Operation ......................................................................................... 91 5.4.2 Interrupt Control Mode 0............................................................................................................................... 93 5.4.3 Interrupt Control Mode 2............................................................................................................................... 95 5.4.4 Interrupt Exception Handling Sequence ....................................................................................................... 97 5.4.5 Interrupt Response Times..............................................................................................................................98 Usage Notes ................................................................................................................................................................99 5.5.1 Contention between Interrupt Generation and Disabling..............................................................................99 5.5.2 Instructions that Disable Interrupts ............................................................................................................... 99 5.5.3 Times when Interrupts are Disabled............................................................................................................100 5.5.4 Interrupts during Execution of EEPMOV Instruction................................................................................. 100 DTC and DMAC Activation by Interrupt................................................................................................................. 100 5.6.1 Overview ..................................................................................................................................................... 100 5.6.2 Block Diagram............................................................................................................................................. 101 5.6.3 Operation ..................................................................................................................................................... 101 5.6.4 Note on Use ................................................................................................................................................. 102 Section 6 Bus Controller...................................................................................................................103 6.1 Overview................................................................................................................................................................... 103 6.1.1 Features ....................................................................................................................................................... 103 6.1.2 Block Diagram............................................................................................................................................. 105 6.1.3 Pin Configuration ........................................................................................................................................106 6.1.4 Register Configuration ................................................................................................................................107 Register Descriptions................................................................................................................................................108 6.2.1 Bus Width Control Register (ABWCR) ......................................................................................................108 6.2.2 Access State Control Register (ASTCR)..................................................................................................... 109 6.2.3 Wait Control Registers H and L (WCRH, WCRL)..................................................................................... 110 6.2.4 Bus Control Register H (BCRH)................................................................................................................. 113 6.2.5 Bus Control Register L (BCRL)..................................................................................................................114 6.2.6 Memory Control Register (MCR) ............................................................................................................... 116 6.2.7 DRAM Control Register (DRAMCR)......................................................................................................... 118 6.2.8 Refresh Timer/Counter (RTCNT) ............................................................................................................... 119 6.2.9 Refresh Time Constant Register (RTCOR)................................................................................................. 120 Overview of Bus Control..........................................................................................................................................121 6.3.1 Area Partitioning ......................................................................................................................................... 121 6.3.2 Bus Specifications ....................................................................................................................................... 122 6.3.3 Memory Interfaces....................................................................................................................................... 123 6.3.4 Advanced Mode........................................................................................................................................... 123 6.3.5 Chip Select Signals ..........................................................................................................................................124 Basic Bus Interface................................................................................................................................................... 125 6.4.1 Overview ..................................................................................................................................................... 125 6.4.2 Data Size and Data Alignment ....................................................................................................................125 6.4.3 Valid Strobes ..............................................................................................................................................127 6.4.4 Basic Timing ............................................................................................................................................... 128 Rev.6.00 Oct.28.2004 page xi of xxiv REJ09B0138-0600H 6.2 6.3 6.4 6.4.5 Wait Control ................................................................................................................................................136 6.5 DRAM Interface....................................................................................................................................................... 138 6.5.1 Overview ..................................................................................................................................................... 138 6.5.2 Setting DRAM Space ..................................................................................................................................138 6.5.3 Address Multiplexing ..................................................................................................................................138 6.5.4 Data Bus ......................................................................................................................................................138 6.5.5 Pins Used for DRAM Interface ................................................................................................................... 139 6.5.6 Basic Timing ............................................................................................................................................... 140 6.5.7 Precharge State Control............................................................................................................................... 141 6.5.8 Wait Control ................................................................................................................................................141 6.5.9 Byte Access Control ....................................................................................................................................143 6.5.10 Burst Operation ........................................................................................................................................... 144 6.5.11 Refresh Control ........................................................................................................................................... 147 6.6 DMAC Single Address Mode and DRAM Interface................................................................................................149 6.6.1 When DDS = 1 ............................................................................................................................................149 6.6.2 When DDS = 0 ............................................................................................................................................150 6.7 Burst ROM Interface ................................................................................................................................................150 6.7.1 Overview ..................................................................................................................................................... 150 6.7.2 Basic Timing ............................................................................................................................................... 151 6.7.3 Wait Control ................................................................................................................................................152 6.8 Idle Cycle..................................................................................................................................................................153 6.8.1 Operation ..................................................................................................................................................... 153 6.8.2 Usage Notes................................................................................................................................................. 155 6.8.3 Pin States in Idle Cycle ............................................................................................................................... 157 6.9 Write Data Buffer Function ......................................................................................................................................158 6.10 Bus Release............................................................................................................................................................... 159 6.10.1 Overview ..................................................................................................................................................... 159 6.10.2 Operation ..................................................................................................................................................... 159 6.10.3 Pin States in External Bus Released State................................................................................................... 160 6.10.4 Transition Timing........................................................................................................................................161 6.10.5 Usage Note ..................................................................................................................................................161 6.11 Bus Arbitration ......................................................................................................................................................... 162 6.11.1 Overview ..................................................................................................................................................... 162 6.11.2 Operation ..................................................................................................................................................... 162 6.11.3 Bus Transfer Timing ................................................................................................................................... 163 6.11.4 External Bus Release Usage Note ............................................................................................................... 163 6.12 Resets and the Bus Controller................................................................................................................................... 164 Section 7 DMA Controller................................................................................................................165 7.1 Overview................................................................................................................................................................... 165 7.1.1 Features ....................................................................................................................................................... 165 7.1.2 Block Diagram............................................................................................................................................. 166 7.1.3 Overview of Functions ................................................................................................................................167 7.1.4 Pin Configuration ........................................................................................................................................169 7.1.5 Register Configuration ................................................................................................................................170 Register Descriptions (1) (Short Address Mode) ..................................................................................................... 171 7.2.1 Memory Address Registers (MAR)............................................................................................................. 172 7.2.2 I/O Address Register (IOAR)......................................................................................................................172 7.2.3 Execute Transfer Count Register (ETCR)................................................................................................... 173 7.2.4 DMA Control Register (DMACR)..............................................................................................................174 7.2.5 DMA Band Control Register (DMABCR)..................................................................................................177 Register Descriptions (2) (Full Address Mode) ....................................................................................................... 181 7.2 7.3 Rev.6.00 Oct.28.2004 page xii of xxiv REJ09B0138-0600H 7.4 7.5 7.6 7.7 7.3.1 Memory Address Register (MAR) ..............................................................................................................181 7.3.2 I/O Address Register (IOAR)......................................................................................................................181 7.3.3 Execute Transfer Count Register (ETCR)................................................................................................... 181 7.3.4 DMA Control Register (DMACR)..............................................................................................................183 7.3.5 DMA Band Control Register (DMABCR)..................................................................................................186 Register Descriptions (3) ..........................................................................................................................................190 7.4.1 DMA Write Enable Register (DMAWER) ................................................................................................. 190 7.4.2 DMA Terminal Control Register (DMATCR)............................................................................................192 7.4.3 Module Stop Control Register (MSTPCR) ................................................................................................. 193 Operation ..................................................................................................................................................................194 7.5.1 Transfer Modes ........................................................................................................................................... 194 7.5.2 Sequential Mode..........................................................................................................................................196 7.5.3 Idle Mode..................................................................................................................................................... 199 7.5.4 Repeat Mode ............................................................................................................................................... 201 7.5.5 Single Address Mode ..................................................................................................................................204 7.5.6 Normal Mode............................................................................................................................................... 207 7.5.7 Block Transfer Mode................................................................................................................................... 210 7.5.8 DMAC Activation Sources ......................................................................................................................... 215 7.5.9 Basic DMAC Bus Cycles ............................................................................................................................217 7.5.10 DMAC Bus Cycles (Dual Address Mode) ..................................................................................................218 7.5.11 DMAC Bus Cycles (Single Address Mode) ............................................................................................... 226 7.5.12 Write Data Buffer Function......................................................................................................................... 230 7.5.13 DMAC Multi-Channel Operation ............................................................................................................... 231 7.5.14 Relation between External Bus Requests, Refresh Cycles, the DTC, and the DMAC ............................... 232 7.5.15 NMI Interrupts and DMAC......................................................................................................................... 233 7.5.16 Forced Termination of DMAC Operation................................................................................................... 234 7.5.17 Clearing Full Address Mode ....................................................................................................................... 235 Interrupts................................................................................................................................................................... 236 Usage Notes ..............................................................................................................................................................237 Section 8 Data Transfer Controller ...................................................................................................241 8.1 Overview................................................................................................................................................................... 241 8.1.1 Features ....................................................................................................................................................... 241 8.1.2 Block Diagram............................................................................................................................................. 242 8.1.3 Register Configuration ................................................................................................................................243 Register Descriptions................................................................................................................................................244 8.2.1 DTC Mode Register A (MRA)....................................................................................................................244 8.2.2 DTC Mode Register B (MRB) ....................................................................................................................245 8.2.3 DTC Source Address Register (SAR)......................................................................................................... 246 8.2.4 DTC Destination Address Register (DAR) ................................................................................................. 246 8.2.5 DTC Transfer Count Register A (CRA) ..................................................................................................... 246 8.2.6 DTC Transfer Count Register B (CRB) ......................................................................................................246 8.2.7 DTC Enable Registers (DTCER) ................................................................................................................247 8.2.8 DTC Vector Register (DTVECR) ............................................................................................................... 247 8.2.9 Module Stop Control Register (MSTPCR) ................................................................................................. 248 Operation ..................................................................................................................................................................249 8.3.1 Overview ..................................................................................................................................................... 249 8.3.2 Activation Sources....................................................................................................................................... 251 8.3.3 DTC Vector Table ....................................................................................................................................... 252 8.3.4 Location of Register Information in Address Space ................................................................................... 255 8.3.5 Normal Mode............................................................................................................................................... 256 8.3.6 Repeat Mode ............................................................................................................................................... 257 Rev.6.00 Oct.28.2004 page xiii of xxiv REJ09B0138-0600H 8.2 8.3 8.4 8.5 8.3.7 Block Transfer Mode................................................................................................................................... 258 8.3.8 Chain Transfer............................................................................................................................................. 259 8.3.9 Operation Timing ........................................................................................................................................260 8.3.10 Number of DTC Execution States............................................................................................................... 261 8.3.11 Procedures for Using DTC ..........................................................................................................................262 8.3.12 Examples of Use of the D7TC..................................................................................................................... 262 Interrupts................................................................................................................................................................... 264 Usage Notes ..............................................................................................................................................................264 Section 9 I/O Ports............................................................................................................................265 Overview................................................................................................................................................................... 265 Port 1......................................................................................................................................................................... 269 9.2.1 Overview ..................................................................................................................................................... 269 9.2.2 Register Configuration ................................................................................................................................269 9.2.3 Pin Functions............................................................................................................................................... 271 9.3 Port 2......................................................................................................................................................................... 279 9.3.1 Overview ..................................................................................................................................................... 279 9.3.2 Register Configuration ................................................................................................................................279 9.3.3 Pin Functions............................................................................................................................................... 281 9.4 Port 3......................................................................................................................................................................... 289 9.4.1 Overview ..................................................................................................................................................... 289 9.4.2 Register Configuration................................................................................................................................. 289 9.4.3 Pin Functions............................................................................................................................................... 291 9.5 Port 4......................................................................................................................................................................... 293 9.5.1 Overview ..................................................................................................................................................... 293 9.5.2 Register Configuration ................................................................................................................................293 9.5.3 Pin Functions............................................................................................................................................... 293 9.6 Port 5......................................................................................................................................................................... 294 9.6.1 Overview ..................................................................................................................................................... 294 9.6.2 Register Configuration ................................................................................................................................294 9.6.3 Pin Functions............................................................................................................................................... 296 9.7 Port 6......................................................................................................................................................................... 297 9.7.1 Overview ..................................................................................................................................................... 297 9.7.2 Register Configuration ................................................................................................................................297 9.7.3 Pin Functions............................................................................................................................................... 299 9.8 Port A........................................................................................................................................................................301 9.8.1 Overview ..................................................................................................................................................... 301 9.8.2 Register Configuration ................................................................................................................................302 9.8.3 Pin Functions............................................................................................................................................... 304 9.8.4 MOS Input Pull-Up Function (On-Chip ROM Version Only) ................................................................... 306 9.9 Port B ........................................................................................................................................................................307 9.9.1 Overview ..................................................................................................................................................... 307 9.9.2 Register Configuration (On-Chip ROM Version Only)..............................................................................308 9.9.3 Pin Functions............................................................................................................................................... 310 9.9.4 MOS Input Pull-Up Function (On-Chip ROM Version Only) ................................................................... 311 9.10 Port C ........................................................................................................................................................................312 9.10.1 Overview ..................................................................................................................................................... 312 9.10.2 Register Configuration (On-Chip ROM Version Only)..............................................................................313 9.10.3 Pin Functions............................................................................................................................................... 315 9.10.4 MOS Input Pull-Up Function (On-Chip ROM Version Only) ................................................................... 316 9.11 Port D........................................................................................................................................................................317 9.11.1 Overview ..................................................................................................................................................... 317 Rev.6.00 Oct.28.2004 page xiv of xxiv REJ09B0138-0600H 9.1 9.2 9.11.2 Register Configuration (On-Chip ROM Version Only)..............................................................................318 9.11.3 Pin Functions............................................................................................................................................... 320 9.11.4 MOS Input Pull-Up Function (On-Chip ROM Version Only)....................................................................321 9.12 Port E ........................................................................................................................................................................322 9.12.1 Overview ..................................................................................................................................................... 322 9.12.2 Register Configuration ................................................................................................................................323 9.12.3 Pin Functions............................................................................................................................................... 325 9.12.4 MOS Input Pull-Up Function (On-Chip ROM Version Only) ................................................................... 326 9.13 Port F ........................................................................................................................................................................327 9.13.1 Overview ..................................................................................................................................................... 327 9.13.2 Register Configuration ................................................................................................................................328 9.13.3 Pin Functions............................................................................................................................................... 330 9.14 Port G........................................................................................................................................................................332 9.14.1 Overview ..................................................................................................................................................... 332 9.14.2 Register Configuration ................................................................................................................................332 9.14.3 Pin Functions............................................................................................................................................... 335 Section 10 16-Bit Timer Pulse Unit (TPU).......................................................................................337 10.1 Overview................................................................................................................................................................... 337 10.1.1 Features ....................................................................................................................................................... 337 10.1.2 Block Diagram............................................................................................................................................. 341 10.1.3 Pin Configuration ........................................................................................................................................342 10.1.4 Register Configuration ................................................................................................................................343 10.2 Register Descriptions................................................................................................................................................345 10.2.1 Timer Control Register (TCR) ....................................................................................................................345 10.2.2 Timer Mode Register (TMDR) ................................................................................................................... 349 10.2.3 Timer I/O Control Register (TIOR) ............................................................................................................351 10.2.4 Timer Interrupt Enable Register (TIER) ..................................................................................................... 361 10.2.5 Timer Status Register (TSR) ....................................................................................................................... 363 10.2.6 Timer Counter (TCNT) ............................................................................................................................... 366 10.2.7 Timer General Register (TGR) ................................................................................................................... 366 10.2.8 Timer Start Register (TSTR)....................................................................................................................... 366 10.2.9 Timer Synchro Register (TSYR)................................................................................................................. 367 10.2.10 Module Stop Control Register (MSTPCR) ................................................................................................. 368 10.3 Interface to Bus Master............................................................................................................................................. 369 10.3.1 16-Bit Registers........................................................................................................................................... 369 10.3.2 8-Bit Registers............................................................................................................................................. 370 10.4 Operation ..................................................................................................................................................................371 10.4.1 Overview ..................................................................................................................................................... 371 10.4.2 Basic Functions ........................................................................................................................................... 372 10.4.3 Synchronous Operation ............................................................................................................................... 377 10.4.4 Buffer Operation ......................................................................................................................................... 379 10.4.5 Cascaded Operation..................................................................................................................................... 382 10.4.6 PWM Modes ............................................................................................................................................... 383 10.4.7 Phase Counting Mode ................................................................................................................................. 388 10.5 Interrupts................................................................................................................................................................... 394 10.5.1 Interrupt Sources and Priorities................................................................................................................... 394 10.5.2 DTC/DMAC Activation ..............................................................................................................................396 10.5.3 A/D Converter Activation ........................................................................................................................... 396 10.6 Operation Timing ..................................................................................................................................................... 397 10.6.1 Input/Output Timing ................................................................................................................................... 397 10.6.2 Interrupt Signal Timing ............................................................................................................................... 401 Rev.6.00 Oct.28.2004 page xv of xxiv REJ09B0138-0600H 10.7 Usage Notes ..............................................................................................................................................................404 Section 11 Programmable Pulse Generator (PPG) ...........................................................................411 11.1 Overview................................................................................................................................................................... 411 11.1.1 Features ....................................................................................................................................................... 411 11.1.2 Block Diagram............................................................................................................................................. 412 11.1.3 Pin Configuration ........................................................................................................................................413 11.1.4 Registers ......................................................................................................................................................414 11.2 Register Descriptions................................................................................................................................................415 11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)..........................................................................415 11.2.2 Output Data Registers H and L (PODRH, PODRL) ................................................................................... 416 11.2.3 Next Data Registers H and L (NDRH, NDRL)........................................................................................... 416 11.2.4 Notes on NDR Access................................................................................................................................. 416 11.2.5 PPG Output Control Register (PCR)........................................................................................................... 418 11.2.6 PPG Output Mode Register (PMR)............................................................................................................. 419 11.2.7 Port 1 Data Direction Register (P1DDR) ....................................................................................................421 11.2.8 Port 2 Data Direction Register (P2DDR) ....................................................................................................421 11.2.9 Module Stop Control Register (MSTPCR) ................................................................................................. 422 11.3 Operation ..................................................................................................................................................................423 11.3.1 Overview ..................................................................................................................................................... 423 11.3.2 Output Timing ............................................................................................................................................. 424 11.3.3 Normal Pulse Output ................................................................................................................................... 425 11.3.4 Non-Overlapping Pulse Output ................................................................................................................... 426 11.3.5 Inverted Pulse Output ..................................................................................................................................429 11.3.6 Pulse Output Triggered by Input Capture ................................................................................................... 430 11.4 Usage Notes ..............................................................................................................................................................431 Section 12 8-Bit Timers....................................................................................................................433 12.1 Overview................................................................................................................................................................... 433 12.1.1 Features ....................................................................................................................................................... 433 12.1.2 Block Diagram............................................................................................................................................. 434 12.1.3 Pin Configuration ........................................................................................................................................435 12.1.4 Register Configuration ................................................................................................................................435 12.2 Register Descriptions................................................................................................................................................436 12.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1)................................................................................................. 436 12.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1) ......................................................................436 12.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1)....................................................................... 437 12.2.4 Time Control Registers 0 and 1 (TCR0, TCR1) ......................................................................................... 437 12.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1)......................................................................... 439 12.2.6 Module Stop Control Register (MSTPCR) ................................................................................................. 441 12.3 Operation ..................................................................................................................................................................442 12.3.1 TCNT Incrementation Timing..................................................................................................................... 442 12.3.2 Compare Match Timing ..............................................................................................................................443 12.3.3 Timing of External RESET on TCNT......................................................................................................... 444 12.3.4 Timing of Overflow Flag (OVF) Setting..................................................................................................... 444 12.3.5 Operation with Cascaded Connection ......................................................................................................... 445 12.4 Interrupts................................................................................................................................................................... 446 12.4.1 Interrupt Sources and DTC Activation........................................................................................................446 12.4.2 A/D Converter Activation ........................................................................................................................... 446 12.5 Sample Application ..................................................................................................................................................447 12.6 Usage Notes ..............................................................................................................................................................448 12.6.1 Contention between TCNT Write and Clear............................................................................................... 448 Rev.6.00 Oct.28.2004 page xvi of xxiv REJ09B0138-0600H 12.6.2 12.6.3 12.6.4 12.6.5 12.6.6 Contention between TCNT Write and Increment ....................................................................................... 449 Contention between TCOR Write and Compare Match ............................................................................. 450 Contention between Compare Matches A and B ........................................................................................450 Switching of Internal Clocks and TCNT Operation................................................................................... 451 Interrupts and Module Stop Mode............................................................................................................... 452 Section 13 Watchdog Timer .............................................................................................................453 13.1 Overview................................................................................................................................................................... 453 13.1.1 Features ....................................................................................................................................................... 453 13.1.2 Block Diagram............................................................................................................................................. 454 13.1.3 Pin Configuration ........................................................................................................................................454 13.1.4 Register Configuration ................................................................................................................................455 13.2 Register Descriptions................................................................................................................................................456 13.2.1 Timer Counter (TCNT) ............................................................................................................................... 456 13.2.2 Timer Control/Status Register (TCSR) ....................................................................................................... 456 13.2.3 Reset Control/Status Register (RSTCSR) ................................................................................................... 457 13.2.4 Notes on Register Access ............................................................................................................................459 13.3 Operation ..................................................................................................................................................................460 13.3.1 Watchdog Timer Operation......................................................................................................................... 460 13.3.2 Interval Timer Operation............................................................................................................................. 461 13.3.3 Timing of Setting Overflow Flag (OVF)..................................................................................................... 461 13.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ................................................................462 13.4 Interrupts................................................................................................................................................................... 462 13.5 Usage Notes ..............................................................................................................................................................463 13.5.1 Contention between Timer Counter (TCNT) Write and Increment ............................................................463 13.5.2 Changing Value of CKS2 to CKS0............................................................................................................. 463 13.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode....................................................... 463 13.5.4 System Reset by WDTOVF Signal ............................................................................................................. 463 13.5.5 Internal Reset in Watchdog Timer Mode ....................................................................................................464 Section 14 Serial Communication Interface (SCI) ...........................................................................465 14.1 Overview................................................................................................................................................................... 465 14.1.1 Features ....................................................................................................................................................... 465 14.1.2 Block Diagram............................................................................................................................................. 467 14.1.3 Pin Configuration ........................................................................................................................................467 14.1.4 Register Configuration ................................................................................................................................468 14.2 Register Descriptions................................................................................................................................................469 14.2.1 Receive Shift Register (RSR)......................................................................................................................469 14.2.2 Receive Data Register (RDR) ..................................................................................................................... 469 14.2.3 Transmit Shift Register (TSR)..................................................................................................................... 469 14.2.4 Transmit Data Register (TDR) ....................................................................................................................470 14.2.5 Serial Mode Register (SMR)....................................................................................................................... 470 14.2.6 Serial Control Register (SCR)..................................................................................................................... 472 14.2.7 Serial Status Register (SSR)........................................................................................................................475 14.2.8 Bit Rate Register (BRR)..............................................................................................................................478 14.2.9 Smart Card Mode Register (SCMR) ........................................................................................................... 485 14.2.10 Module Stop Control Register (MSTPCR) ................................................................................................. 486 14.3 Operation ..................................................................................................................................................................487 14.3.1 Overview ..................................................................................................................................................... 487 14.3.2 Operation in Asynchronous Mode............................................................................................................... 489 14.3.3 Multiprocessor Communication Function................................................................................................... 499 14.3.4 Operation in Clocked Synchronous Mode ..................................................................................................505 Rev.6.00 Oct.28.2004 page xvii of xxiv REJ09B0138-0600H 14.4 SCI Interrupts ........................................................................................................................................................... 512 14.5 Usage Notes ..............................................................................................................................................................514 Section 15 Smart Card Interface.......................................................................................................517 15.1 Overview................................................................................................................................................................... 517 15.1.1 Features ....................................................................................................................................................... 517 15.1.2 Block Diagram............................................................................................................................................. 518 15.1.3 Pin Configuration ........................................................................................................................................518 15.1.4 Register Configuration ................................................................................................................................519 15.2 Register Descriptions................................................................................................................................................520 15.2.1 Smart Card Mode Register (SCMR) ........................................................................................................... 520 15.2.2 Serial Status Register (SSR)........................................................................................................................521 15.2.3 Serial Mode Register (SMR)....................................................................................................................... 522 15.2.4 Serial Control Register (SCR)..................................................................................................................... 523 15.3 Operation ..................................................................................................................................................................524 15.3.1 Overview ..................................................................................................................................................... 524 15.3.2 Pin Connections........................................................................................................................................... 524 15.3.3 Data Format................................................................................................................................................. 525 15.3.4 Register Settings..........................................................................................................................................526 15.3.5 Clock ........................................................................................................................................................... 527 15.3.6 Data Transfer Operations ............................................................................................................................529 15.3.7 Operation in GSM Mode............................................................................................................................. 534 15.4 Usage Notes ..............................................................................................................................................................535 Section 16 A/D Converter ................................................................................................................539 16.1 Overview................................................................................................................................................................... 539 16.1.1 Features ....................................................................................................................................................... 539 16.1.2 Block Diagram............................................................................................................................................. 540 16.1.3 Pin Configuration ........................................................................................................................................540 16.1.4 Register Configuration ................................................................................................................................541 16.2 Register Descriptions................................................................................................................................................542 16.2.1 A/D Data Registers A to D (ADDRA to ADDRD)..................................................................................... 542 16.2.2 A/D Control/Status Register (ADCSR)....................................................................................................... 542 16.2.3 A/D Control Register (ADCR)....................................................................................................................544 16.2.4 Module Stop Control Register (MSTPCR) ................................................................................................. 545 16.3 Interface to Bus Master............................................................................................................................................. 546 16.4 Operation ..................................................................................................................................................................546 16.4.1 Single Mode (SCAN = 0) ............................................................................................................................546 16.4.2 Scan Mode (SCAN = 1) ..............................................................................................................................548 16.4.3 Input Sampling and A/D Conversion Time................................................................................................. 549 16.4.4 External Trigger Input Timing ....................................................................................................................550 16.5 Interrupts................................................................................................................................................................... 550 16.6 Usage Notes ..............................................................................................................................................................551 Section 17 D/A Converter ................................................................................................................555 17.1 Overview................................................................................................................................................................... 555 17.1.1 Features ....................................................................................................................................................... 555 17.1.2 Block Diagram............................................................................................................................................. 555 17.1.3 Pin Configuration ........................................................................................................................................556 17.1.4 Register Configuration ................................................................................................................................556 17.2 Register Descriptions................................................................................................................................................557 17.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1)......................................................................................... 557 Rev.6.00 Oct.28.2004 page xviii of xxiv REJ09B0138-0600H 17.2.2 D/A Control Register (DACR)....................................................................................................................557 17.2.3 Module Stop Control Register (MSTPCR) ................................................................................................. 558 17.3 Operation ..................................................................................................................................................................559 Section 18 RAM................................................................................................................................561 18.1 Overview................................................................................................................................................................... 561 18.1.1 Block Diagram ............................................................................................................................................561 18.1.2 Register Configuration ................................................................................................................................561 18.2 Register Descriptions................................................................................................................................................562 18.2.1 System Control Register (SYSCR) ............................................................................................................. 562 18.3 Operation ..................................................................................................................................................................562 18.4 Usage Note ............................................................................................................................................................... 562 Section 19 ROM................................................................................................................................563 19.1 Overview................................................................................................................................................................... 563 19.1.1 Block Diagram............................................................................................................................................. 563 19.1.2 Register Configuration ................................................................................................................................563 19.2 Register Descriptions................................................................................................................................................564 19.2.1 Mode Control Register (MDCR)................................................................................................................. 564 19.2.2 Bus Control Register L (BCRL)..................................................................................................................564 19.3 Operation ..................................................................................................................................................................565 19.4 PROM Mode (H8S/2357 ZTAT) ............................................................................................................................. 566 19.4.1 PROM Mode Setting................................................................................................................................... 566 19.4.2 Socket Adapter and Memory Map ..............................................................................................................567 19.5 Programming (H8S/2357 ZTAT) ............................................................................................................................. 569 19.5.1 Overview ..................................................................................................................................................... 569 19.5.2 Programming and Verification ....................................................................................................................570 19.5.3 Programming Precautions ........................................................................................................................... 572 19.5.4 Reliability of Programmed Data ................................................................................................................. 573 19.6 Overview of Flash Memory (H8S/2357 F-ZTAT)................................................................................................... 574 19.6.1 Features ....................................................................................................................................................... 574 19.6.2 Block Diagram............................................................................................................................................. 575 19.6.3 Flash Memory Operating Modes................................................................................................................. 576 19.6.4 Pin Configuration ........................................................................................................................................581 19.6.5 Register Configuration ................................................................................................................................581 19.7 Register Descriptions................................................................................................................................................582 19.7.1 Flash Memory Control Register 1 (FLMCR1)............................................................................................582 19.7.2 Flash Memory Control Register 2 (FLMCR2)............................................................................................584 19.7.3 Erase Block Registers 1 and 2 (EBR1, EBR2)............................................................................................585 19.7.4 System Control Register 2 (SYSCR2) ........................................................................................................586 19.7.5 RAM Emulation Register (RAMER) ..........................................................................................................586 19.8 On-Board Programming Modes ............................................................................................................................... 588 19.8.1 Boot Mode................................................................................................................................................... 588 19.8.2 User Program Mode ....................................................................................................................................592 19.9 Programming/Erasing Flash Memory....................................................................................................................... 594 19.9.1 Program Mode............................................................................................................................................. 594 19.9.2 Program-Verify Mode ................................................................................................................................. 594 19.9.3 Erase Mode..................................................................................................................................................596 19.9.4 Erase-Verify Mode ......................................................................................................................................596 19.10 Flash Memory Protection ......................................................................................................................................... 598 19.10.1 Hardware Protection....................................................................................................................................598 19.10.2 Software Protection ..................................................................................................................................... 599 Rev.6.00 Oct.28.2004 page xix of xxiv REJ09B0138-0600H 19.11 19.12 19.13 19.14 19.15 19.16 19.17 19.18 19.19 19.20 19.21 19.22 19.10.3 Error Protection ........................................................................................................................................... 599 Flash Memory Emulation in RAM........................................................................................................................... 601 19.11.1 Emulation in RAM ......................................................................................................................................601 19.11.2 RAM Overlap ..............................................................................................................................................602 Interrupt Handling when Programming/Erasing Flash Memory ..............................................................................603 Flash Memory Programmer Mode ........................................................................................................................... 604 19.13.1 Programmer Mode Setting ..........................................................................................................................604 19.13.2 Socket Adapters and Memory Map............................................................................................................. 604 19.13.3 Programmer Mode Operation......................................................................................................................605 19.13.4 Memory Read Mode....................................................................................................................................606 19.13.5 Auto-Program Mode ................................................................................................................................... 609 19.13.6 Auto-Erase Mode......................................................................................................................................... 611 19.13.7 Status Read Mode........................................................................................................................................612 19.13.8 Status Polling............................................................................................................................................... 613 19.13.9 Programmer Mode Transition Time............................................................................................................613 19.13.10 Notes on Memory Programming ............................................................................................................... 614 Flash Memory Programming and Erasing Precautions ............................................................................................614 Overview of Flash Memory (H8S/2398 F-ZTAT)................................................................................................... 619 19.15.1 Features ....................................................................................................................................................... 619 19.15.2 Overview ..................................................................................................................................................... 620 19.15.3 Flash Memory Operating Modes................................................................................................................. 621 19.15.4 On-Board Programming Modes ..................................................................................................................622 19.15.5 Flash Memory Emulation in RAM..............................................................................................................624 19.15.6 Differences between Boot Mode and User Program Mode......................................................................... 625 19.15.7 Block Configuration ....................................................................................................................................625 19.15.8 Pin Configuration ........................................................................................................................................626 19.15.9 Register Configuration ................................................................................................................................626 Register Descriptions................................................................................................................................................627 19.16.1 Flash Memory Control Register 1 (FLMCR1)............................................................................................627 19.16.2 Flash Memory Control Register 2 (FLMCR2)............................................................................................629 19.16.3 Erase Block Register 1 (EBR1)................................................................................................................... 629 19.16.4 Erase Block Registers 2 (EBR2) ................................................................................................................. 630 19.16.5 System Control Register 2 (SYSCR2) ........................................................................................................630 19.16.6 RAM Emulation Register (RAMER) ..........................................................................................................631 On-Board Programming Modes ............................................................................................................................... 632 19.17.1 Boot Mode................................................................................................................................................... 633 19.17.2 User Program Mode ....................................................................................................................................637 Programming/Erasing Flash Memory....................................................................................................................... 638 19.18.1 Program Mode............................................................................................................................................. 638 19.18.2 Program-Verify Mode ................................................................................................................................. 638 19.18.3 Erase Mode..................................................................................................................................................640 19.18.4 Erase-Verify Mode ......................................................................................................................................640 Flash Memory Protection ......................................................................................................................................... 642 19.19.1 Hardware Protection....................................................................................................................................642 19.19.2 Software Protection ..................................................................................................................................... 643 19.19.3 Error Protection ........................................................................................................................................... 644 Flash Memory Emulation in RAM........................................................................................................................... 645 19.20.1 Emulation in RAM ......................................................................................................................................645 19.20.2 RAM Overlap ..............................................................................................................................................646 Interrupt Handling when Programming/Erasing Flash Memory ..............................................................................647 Flash Memory Programmer Mode ........................................................................................................................... 647 19.22.1 Programmer Mode Setting ..........................................................................................................................647 Rev.6.00 Oct.28.2004 page xx of xxiv REJ09B0138-0600H 19.22.2 Socket Adapters and Memory Map............................................................................................................. 648 19.22.3 Programmer Mode Operation......................................................................................................................650 19.22.4 Memory Read Mode....................................................................................................................................651 19.22.5 Auto-Program Mode ................................................................................................................................... 653 19.22.6 Auto-Erase Mode......................................................................................................................................... 655 19.22.7 Status Read Mode........................................................................................................................................656 19.22.8 Status Polling............................................................................................................................................... 657 19.22.9 Programmer Mode Transition Time............................................................................................................657 19.22.10 Notes on Memory Programming ............................................................................................................... 658 19.23 Flash Memory Programming and Erasing Precautions ............................................................................................658 Section 20 Clock Pulse Generator ....................................................................................................661 20.1 Overview................................................................................................................................................................... 661 20.1.1 Block Diagram............................................................................................................................................. 661 20.1.2 Register Configuration ................................................................................................................................661 20.2 Register Descriptions................................................................................................................................................662 20.2.1 System Clock Control Register (SCKCR) ..................................................................................................662 20.3 Oscillator................................................................................................................................................................... 663 20.3.1 Connecting a Crystal Resonator ..................................................................................................................663 20.3.2 External Clock Input ................................................................................................................................... 664 20.4 Duty Adjustment Circuit........................................................................................................................................... 665 20.5 Medium-Speed Clock Divider..................................................................................................................................665 20.6 Bus Master Clock Selection Circuit ......................................................................................................................... 665 Section 21 Power-Down Modes .......................................................................................................667 21.1 Overview................................................................................................................................................................... 667 21.1.1 Register Configuration ................................................................................................................................668 21.2 Register Descriptions................................................................................................................................................669 21.2.1 Standby Control Register (SBYCR) ........................................................................................................... 669 21.2.2 System Clock Control Register (SCKCR) ..................................................................................................670 21.2.3 Module Stop Control Register (MSTPCR) ................................................................................................. 671 21.3 Medium-Speed Mode ............................................................................................................................................... 672 21.4 Sleep Mode............................................................................................................................................................... 672 21.5 Module Stop Mode ................................................................................................................................................... 673 21.5.1 Module Stop Mode ......................................................................................................................................673 21.5.2 Usage Notes................................................................................................................................................. 674 21.6 Software Standby Mode ........................................................................................................................................... 675 21.6.1 Software Standby Mode ..............................................................................................................................675 21.6.2 Clearing Software Standby Mode ............................................................................................................... 675 21.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode ......................................... 675 21.6.4 Software Standby Mode Application Example ........................................................................................... 676 21.6.5 Usage Notes................................................................................................................................................. 677 21.7 Hardware Standby Mode ..........................................................................................................................................678 21.7.1 Hardware Standby Mode............................................................................................................................. 678 21.7.2 Hardware Standby Mode Timing ................................................................................................................678 21.8 ø Clock Output Disabling Function..........................................................................................................................679 Section 22 Electrical Characteristics.................................................................................................681 22.1 Electrical Characteristics of Masked ROM Version (H8S/2398) and ROMless Versions (H8S/2394, H8S/2392, and H8S/2390)..................................................................................... 681 22.1.1 Absolute Maximum Ratings........................................................................................................................681 22.1.2 DC Characteristics....................................................................................................................................... 682 Rev.6.00 Oct.28.2004 page xxi of xxiv REJ09B0138-0600H 22.2 22.3 22.4 22.5 22.6 22.7 22.8 22.1.3 AC Characteristics....................................................................................................................................... 684 22.1.4 A/D Conversion Characteristics ..................................................................................................................701 22.1.5 D/A Conversion Characteristics ..................................................................................................................702 Usage Note (Internal Voltage Step Down for the H8S/2398, H8S/2394, H8S/2392, and H8S/2390) ................... 702 Electrical Characteristics of H8S/2398 F-ZTAT......................................................................................................703 22.3.1 Absolute Maximum Ratings........................................................................................................................703 22.3.2 DC Characteristics....................................................................................................................................... 704 22.3.3 AC Characteristics....................................................................................................................................... 706 22.3.4 A/D Conversion Characteristics ..................................................................................................................723 22.3.5 D/A Conversion Characteristics ..................................................................................................................724 22.3.6 Flash Memory Characteristics..................................................................................................................... 724 Notes on Use............................................................................................................................................................. 727 Usage Note (Internal Voltage Step Down for the H8S/2398 F-ZTAT) ..................................................................727 Electrical Characteristics of H8S/2357 Masked ROM and ZTAT Versions, and H8S/2352................................... 728 22.6.1 Absolute Maximum Ratings........................................................................................................................728 22.6.2 DC Characteristics....................................................................................................................................... 728 22.6.3 AC Characteristics....................................................................................................................................... 734 22.6.4 A/D Conversion Characteristics ..................................................................................................................753 22.6.5 D/A Convervion Characteristics ................................................................................................................. 754 Electrical Characteristics of H8S/2357 F-ZTAT Version ........................................................................................755 22.7.1 Absolute Maximum Ratings........................................................................................................................755 22.7.2 DC Characteristics....................................................................................................................................... 755 22.7.3 AC Characteristics....................................................................................................................................... 759 22.7.4 A/D Conversion Characteristics ..................................................................................................................764 22.7.5 D/A Conversion Characteristics ..................................................................................................................765 22.7.6 Flash Memory Characteristics..................................................................................................................... 765 Usage Note ............................................................................................................................................................... 768 Appendix A Instruction Set ..............................................................................................................769 A.1 A.2 A.3 A.4 A.5 A.6 Instruction List..........................................................................................................................................................769 Instruction Codes ......................................................................................................................................................792 Operation Code Map................................................................................................................................................. 806 Number of States Required for Instruction Execution ............................................................................................. 810 Bus States during Instruction Execution................................................................................................................... 820 Condition Code Modification................................................................................................................................... 834 Appendix B Internal I/O Register.....................................................................................................839 B.1 B.2 Addresses..................................................................................................................................................................839 Functions................................................................................................................................................................... 847 Appendix C I/O Port Block Diagrams..............................................................................................968 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.11 Port 1 Block Diagram............................................................................................................................................... 968 Port 2 Block Diagram............................................................................................................................................... 971 Port 3 Block Diagram............................................................................................................................................... 975 Port 4 Block Diagram............................................................................................................................................... 978 Port 5 Block Diagram ..............................................................................................................................................979 Port 6 Block Diagram............................................................................................................................................... 983 Port A Block Diagram ..............................................................................................................................................989 Port B Block Diagram ..............................................................................................................................................992 Port C Block Diagram ..............................................................................................................................................993 Port D Block Diagram ..............................................................................................................................................994 Port E Block Diagram............................................................................................................................................... 995 Rev.6.00 Oct.28.2004 page xxii of xxiv REJ09B0138-0600H C.12 Port F Block Diagram............................................................................................................................................... 996 C.13 Port G Block Diagram ............................................................................................................................................1004 Appendix D Pin States ....................................................................................................................1007 D.1 Port States in Each Mode ....................................................................................................................................... 1007 Appendix E Pin States at Power-On ...............................................................................................1011 E.1 E.2 When Pins Settle from an Indeterminate State at Power-On ................................................................................. 1011 When Pins Settle from the High-Impedance State at Power-On............................................................................1012 Appendix F Timing of Transition to and Recovery from Hardware Standby Mode........................1013 F.1 F.2 Timing of Transition to Hardware Standby Mode ................................................................................................. 1013 Timing of Recovery from Hardware Standby Mode..............................................................................................1013 Appendix G Product Code Lineup..................................................................................................1014 Appendix H Package Dimensions...................................................................................................1015 Rev.6.00 Oct.28.2004 page xxiii of xxiv REJ09B0138-0600H Rev.6.00 Oct.28.2004 page xxiv of xxiv REJ09B0138-0600H Section 1 Overview 1.1 Overview The H8S/2357 Group is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Renesas proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. On-chip peripheral functions required for system configuration include DMA controller (DMAC) and data transfer controller (DTC) bus masters, ROM and RAM memory, a 16-bit timer-pulse unit (TPU), programmable pulse generator (PPG), 8-bit timer, watchdog timer (WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O ports. Single-power-supply flash memory (F-ZTAT*1), PROM (ZTAT*2), and masked ROM versions are available, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently changing specifications. The features of the H8S/2357 Group are shown in table 1-1. Notes: 1. F-ZTAT is a trademark of Renesas Technology, Corp. 2. ZTAT is a registered trademark of Renesas Technology, Corp. Rev.6.00 Oct.28.2004 page 1 of 1016 REJ09B0138-0600H Table 1-1 Overview Item CPU Specification • General-register machine  Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation suitable for realtime control  Maximum clock rate: 20 MHz  High-speed arithmetic operations 8/16/32-bit register-register add/subtract: 50 ns 16 × 16-bit register-register multiply: 1000 ns 32 ÷ 16-bit register-register divide: 1000 ns Instruction set suitable for high-speed operation  Sixty-five basic instructions  8/16/32-bit move/arithmetic and logic instructions  Unsigned/signed multiply and divide instructions  Powerful bit-manipulation instructions CPU operating modes  Advanced mode: 16-Mbyte address space Address space divided into 8 areas, with bus specifications settable independently for each area Chip select output possible for each area Choice of 8-bit or 16-bit access space for each area 2-state or 3-state access space can be designated for each area Number of program wait states can be set for each area Burst ROM directly connectable Maximum 8-Mbyte DRAM directly connectable (or use of interval timer possible) External bus release function Choice of short address mode or full address mode 4 channels in short address mode 2 channels in full address mode Transfer possible in repeat mode, block transfer mode, etc. Single address mode transfer possible Can be activated by internal interrupt Can be activated by internal interrupt or software Multiple transfers or multiple types of transfer possible for one activation source Transfer possible in repeat mode, block transfer mode, etc. Request can be sent to CPU for interrupt that activated DTC • • • Bus controller • • • • • • • • DMA controller (DMAC) • • • • • • • • • • Data transfer controller (DTC) Rev.6.00 Oct.28.2004 page 2 of 1016 REJ09B0138-0600H Item 16-bit timer-pulse unit (TPU) Programmable pulse generator (PPG) Specification • • • • • • • • • • • • • • • • • • • • 6-channel 16-bit timer on-chip Pulse I/O processing capability for up to 16 pins Automatic 2-phase encoder count capability Maximum 16-bit pulse output possible with TPU as time base Output trigger selectable in 4-bit groups Non-overlap margin can be set Direct output or inverse output setting possible 8-bit up-counter (external event count capability) Two time constant registers Two-channel connection possible Watchdog timer or interval timer selectable Asynchronous mode or synchronous mode selectable Multiprocessor communication function Smart card interface function Resolution: 10 bits Input: 8 channels High-speed conversion: 6.7 µs minimum conversion time (at 20 MHz operation) Single or scan mode selectable Sample and hold circuit A/D conversion can be activated by external trigger or timer trigger Resolution: 8 bits Output: 2 channels 87 I/O pins, 8 input-only pins Flash memory, PROM, Masked ROM High-speed static RAM ROM 128 kbytes — 256 kbytes — — — RAM 8 kbytes 8 kbytes 8 kbytes 32 kbytes 8 kbytes 4 kbytes 8-bit timer 2 channels Watchdog timer Serial communication interface (SCI) 3 channels A/D converter D/A converter I/O ports Memory • • • • • Product Name H8S/2357 H8S/2352 H8S/2398 H8S/2394 H8S/2392 H8S/2390 Rev.6.00 Oct.28.2004 page 3 of 1016 REJ09B0138-0600H Item Interrupt controller Specification • • • • • • • • • Nine external interrupt pins (NMI, IRQ0 to IRQ7) 52 internal interrupt sources Eight priority levels settable Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Eight MCU operating modes (H8S/2357 F-ZTAT) External Data Bus On-Chip Initial ROM Value — — Maximum Value — Power-down state Operating modes CPU Operating Mode Mode Description 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Advanced User program mode — — Advanced Boot mode — Advanced On-chip ROM disabled expansion mode On-chip ROM enabled expansion mode Single-chip mode — — — Disabled 16 bits 8 bits Enabled 8 bits — — — 16 bits 16 bits 16 bits — — Enabled 8 bits — 16 bits — — — — Enabled 8 bits — 16 bits — Rev.6.00 Oct.28.2004 page 4 of 1016 REJ09B0138-0600H Item Operating modes Specification • Four MCU operating modes (H8S/2398 F-ZTAT, masked ROM, ROMless, and ZTAT) CPU Operating Mode — On-Chip ROM — External Data Bus Initial Maximum Value Value — — On-chip ROM disabled Disabled 16 bits 16 bits expansion mode 5* 2 On-chip ROM disabled Disabled 8 bits 16 bits expansion mode 6 On-chip ROM enabled Enabled 8 bits 16 bits expansion mode 7 Single-chip mode Enabled — — Notes: 1. In the H8S/2398 F-ZTAT, modes 2 and 3 indicate boot mode. For details on boot mode of the H8S/2398 F-ZTAT, refer to table 19-35 in section 19.17, On-Board Programming Modes. In addition, for details on user program mode, refer also to tables 19-35 in section 19.17, On-Board Programming Modes. 2. In ROMless version, only modes 4 and 5 are available. Clock pulse • On-chip duty correction circuit generator • 120-pin plastic TQFP (TFP-120) Packages • 128 pin plastic QFP (FP-128B) Product 5 V version 3.3 V version 3 V version lineup Operating 5 V ± 10% 3.0 to 5.5 V 2.7 to 5.5 V Supply Voltage Operating 2 to 20 MHz 10 to 20 MHz 2 to 13 MHz 2 to 10 MHz Frequency ROMless HD6412352F20 HD6412394F20 HD6412352F13 HD6412352F10 Version HD6412352TE20 HD6412394TE20 HD6412352TE13 HD6412352TE10 HD6412392F20 HD6412392TE20 HD6412390F20 HD6412390TE20 Mode 0 1 2* 1 3* 1 4* 2 Description — Advanced Masked ROM Version * 1 F-ZTAT Version * 2 HD6432357(A**)F HD6432398(A**)F HD6432357(A**)TE HD6432398(A**)TE HD64F2357F20 HD64F2357TE20 HD6432357(M **)F HD6432357(K**)F HD6432357(M **)TE HD6432357(K**)TE — HD64F2398F20 HD64F2357VF13 HD64F2398TE20 HD64F2357VTE13 HD64F2398F20T* 3 HD64F2398TE20T * 3 — HD6472357F13 HD6472357TE13 ZTAT Version Packages HD6472357F20 HD6472357TE20 HD6472357F10 HD6472357TE10 FP-128B FP-128B FP-128B TFP-120 TFP-120 TFP-120 Notes: 1. In masked ROM versions, (**) is the ROM code. 2. See sections 22.3.6 and 22.7.6, Flash Memory Characteristics, for FZTAT version operating supply voltage and temperature range for programming/erasing. 3. For the HD64F2398F20T and HD64F2398TE20T only, the maximum number of times the flash memory can be reprogrammed is 1,000. Rev.6.00 Oct.28.2004 page 5 of 1016 REJ09B0138-0600H 1.2 Block Diagram Figure 1-1 shows an internal block diagram of the H8S/2357 Group. PD7 /D15 PD6 /D14 PD5 /D13 PD4 /D12 PD3 /D11 PD2 /D10 PD1 /D9 PD0 /D8 Port D PE7 /D7 PE6 /D6 PE5 /D5 PE4 /D4 PE3 /D3 PE2 /D2 PE1 /D1 PE0 /D0 Port E VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS Internal data bus H8S/2000 CPU Internal address bus Bus controller MD2 MD1 MD0 EXTAL XTAL STBY RES WDTOVF (FWE, VCL)*1 NMI Port A Clock pulse generator PA7 / A23 / IRQ7 PA6 / A22 / IRQ6 PA5 / A21 / IRQ5 PA4 / A20 / IRQ4 PA3 / A19 PA2 / A18 PA1 / A17 PA0 / A16 PB7 / A15 PB6 / A14 PB5 / A13 PB4 / A12 PB3 / A11 PB2 / A10 PB1 / A9 PB0 / A8 PC7 / A7 PC6 / A6 PC5 / A5 PC4 / A4 PC3 / A3 PC2 / A2 PC1 / A1 PC0 / A0 P35 / SCK1 P34 / SCK0 P33 / RxD1 P32 / RxD0 P31 / TxD1 P30 / TxD0 P50 / TxD2 P51 / RxD2 P52 / SCK2 P53 / ADTRG Interrupt controller PF7 / ø PF6 / AS PF5 / RD PF4 / HWR PF3 / LWR PF2 /LCAS/WAIT/BREQO PF1 / BACK PF0 / BREQ PG4 / CS0 PG3 / CS1 PG2 / CS2 PG1 / CS3 PG0 / CAS P67 / CS7 / IRQ3 P66 / CS6 / IRQ2 P65 / IRQ1 P64 / IRQ0 P63 / TEND1 P62 / DREQ1 P61 / TEND0 / CS5 P60 / DREQ0 / CS4 DTC Port B Peripheral address bus Peripheral data bus ROM*2 Port F DMAC Port C WDT RAM Port G 8-bit timer SCI TPU D/A converter Port 6 Port 3 PPG A/D converter Port 5 Port 1 Port 2 Port 4 P10 /PO8/TIOCA0/DACK0 P11 /PO9/TIOCB0/DACK1 P12 /PO10/TIOCC0/TCLKA P13 /PO11/TIOCD0/TCLKB P14 /PO12/TIOCA1 P15 /PO13/TIOCB1/TCLKC P16 /PO14/TIOCA2 P17 /PO15/TIOCB2/TCLKD Vref AVCC AVSS Notes: 1. This pin functions as the WDTOVF pin function in ZTAT, and masked ROM products, and in the H8S/2352. In the H8S/2357F-ZTAT, the WDTOVF pin function is not available, because this pin is used as the FWE pin. In the H8S/2398, H8S/2394, H8S/2392, and H8S/2390, the WDTOVF pin function is not available, because this pin is used as the VCL pin. 2. In ROMless version, ROM is not supported. Figure 1-1 Block Diagram Rev.6.00 Oct.28.2004 page 6 of 1016 REJ09B0138-0600H P20 /PO0/TIOCA3 P21 /PO1/TIOCB3 P22 /PO2/TIOCC3/TMRI0 P23 /PO3/TIOCD3/TMCI0 P24 /PO4/TIOCA4/TMRI1 P25 /PO5/TIOCB4/TMCI1 P26 /PO6/TIOCA5/TMO0 P27 /PO7/TIOCB5/TMO1 P47 /AN7/DA1 P46 /AN6/DA0 P45 /AN5 P44 /AN4 P43 /AN3 P42 /AN2 P41 /AN1 P40 /AN0 1.3 1.3.1 Pin Description Pin Arrangement Figures 1-2 and 1-3 show the pin arrangement for the H8S/2357, H8S/2352 and figures 1-4 and 1-5 show the pin arrangements for the H8S/2398, H8S/2394, H8S/2392, and H8S/2390. P20 /PO0/TIOCA3 P21 /PO1/TIOCB3 P22 /PO2/TIOCC3/TMRI0 P23 /PO3/TIOCD3/TMCI0 P24 /PO4/TIOCA4/TMRI1 P25 /PO5/TIOCB4/TMCI1 P26 /PO6/TIOCA5/TMO0 P27 /PO7/TIOCB5/TMO1 P63 / TEND1 P62 / DREQ1 P61 / TEND0 / CS5 P51 /RxD2 P50 /TxD2 PF0 / BREQ PF1 / BACK PF2 / LCAS/WAIT / BREQO PF3 / LWR PF4 / HWR PF5 / RD PF6 / AS VCC PF7 /ø VSS EXTAL XTAL VCC STBY NMI RES WDTOVF (FWE)* 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Note: * This pin has the WDTOVF pin function in the ZTAT, masked ROM, and ROMless versions. In the F-ZTAT version, the WDTOVF pin function is not available, and this pin is the FWE pin. Figure 1-2 H8S/2357, H8S/2352 Pin Arrangement (TFP-120: Top View) VCC PC0 /A0 PC1 /A1 PC2 /A2 PC3 /A3 VSS PC4 /A4 PC5 /A5 PC6 /A6 PC7 /A7 PB0 /A8 PB1 /A9 PB2 /A10 PB3 /A11 VSS PB4 /A12 PB5 /A13 PB6 /A14 PB7 /A15 PA0 /A16 PA1 /A17 PA2 /A18 PA3 /A19 VSS PA4 /A20 / IRQ4 PA5 /A21 / IRQ5 PA6 /A22 / IRQ6 PA7 /A23 / IRQ7 P67 / CS7/ IRQ3 P66 / CS6/ IRQ2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SCK2 / P52 ADTRG / P53 AVCC Vref AN0 / P40 AN1 / P41 AN2 / P42 AN3 / P43 AN4 / P44 AN5 / P45 DA0 / AN6 / P46 DA1 / AN7 / P47 AVSS VSS TCLKD / TIOCB2 / PO15 / P17 TIOCA2 / PO14 / P16 TCLKC / TIOCB1 / PO13 / P15 TIOCA1 / PO12 / P14 TCLKB / TIOCD0 / PO11 / P13 TCLKA / TIOCC0 / PO10 / P12 DACK1 / TIOCB0 / PO9 / P11 DACK0 / TIOCA0 / PO8 / P10 MD0 MD1 MD2 CAS / PG0 CS3 / PG1 CS2 / PG2 CS1 / PG3 CS0 / PG4 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P60 / DREQ0 / CS4 VSS P35 / SCK1 P34 / SCK0 P33 / RxD1 P32 / RxD0 P31 / TxD1 P30 / TxD0 VCC PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 VSS PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 VSS PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 VCC P64 / IRQ0 P65 / IRQ1 Rev.6.00 Oct.28.2004 page 7 of 1016 REJ09B0138-0600H Note: * This pin has the WDTOVF pin function in the ZTAT, masked ROM, and ROMless versions. In the F-ZTAT version, the WDTOVF pin function is not available, and this pin is the FWE pin. Figure 1-3 H8S/2357, H8S/2352 Pin Arrangement (FP-128B: Top View) Rev.6.00 Oct.28.2004 page 8 of 1016 REJ09B0138-0600H PG3 / CS1 PG4 / CS0 VSS NC VCC PC0 /A0 PC1 /A1 PC2 /A2 PC3 /A3 VSS PC4 /A4 PC5 /A5 PC6 /A6 PC7 /A7 PB0 /A8 PB1 /A9 PB2 /A10 PB3 /A11 VSS PB4 /A12 PB5 /A13 PB6 /A14 PB7 /A15 PA0 /A16 PA1 /A17 PA2 /A18 PA3 /A19 VSS PA4 /A20 / IRQ4 PA5 /A21 / IRQ5 PA6 /A22 / IRQ6 PA7 /A23 / IRQ7 P67 / CS7/ IRQ3 P66 / CS6/ IRQ2 VSS VSS P65 / IRQ1 P64 / IRQ0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 AVCC Vref AN0 / P40 AN1 / P41 AN2 / P42 AN3 / P43 AN4 / P44 AN5 / P45 DA0 / AN6 / P46 DA1 / AN7 / P47 AVSS VSS TCLKD / TIOCB2 / PO15 / P17 TIOCA2 / PO14 / P16 TCLKC / TIOCB1 / PO13 / P15 TIOCA1 / PO12 / P14 TCLKB / TIOCD0 / PO11 / P13 TCLKA / TIOCC0 / PO10 / P12 DACK1 / TIOCB0 / PO9 / P11 DACK0 / TIOCA0 / PO8 / P10 MD0 MD1 MD2 CAS / PG0 CS3 / PG1 CS2 / PG2 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P53 / ADTRG P52 /SCK2 VSS VSS P51 /RxD2 P50 /TxD2 PF0 / BREQ PF1 / BACK PF2 / LCAS/WAIT / BREQO PF3 / LWR PF4 / HWR PF5 / RD PF6 / AS VCC PF7 /ø VSS EXTAL XTAL VCC STBY NMI RES WDTOVF (FWE*) P20 /PO0/TIOCA3 P21 /PO1/TIOCB3 P22 /PO2/TIOCC3/TMRI0 P23 /PO3/TIOCD3/TMCI0 P24 /PO4/TIOCA4/TMRI1 P25 /PO5/TIOCB4/TMCI1 P26 /PO6/TIOCA5/TMO0 P27 /PO7/TIOCB5/TMO1 P63 / TEND1 P62 / DREQ1 P61 / TEND0 / CS5 VSS VSS P60 / DREQ0 / CS4 VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 P35 / SCK1 P34 / SCK0 P33 / RxD1 P32 / RxD0 P31 / TxD1 P30 / TxD0 VCC PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 VSS PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 VSS PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 VCC 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P51 /RxD2 P50 /TxD2 PF0 / BREQ PF1 / BACK PF2 / LCAS/WAIT / BREQO PF3 / LWR PF4 / HWR PF5 / RD PF6 / AS VCC PF7 /ø VSS EXTAL XTAL VCC STBY NMI RES VCL P20 /PO0/TIOCA3 P21 /PO1/TIOCB3 P22 /PO2/TIOCC3/TMRI0 P23 /PO3/TIOCD3/TMCI0 P24 /PO4/TIOCA4/TMRI1 P25 /PO5/TIOCB4/TMCI1 P26 /PO6/TIOCA5/TMO0 P27 /PO7/TIOCB5/TMO1 P63 / TEND1 P62 / DREQ1 P61 / TEND0 / CS5 Figure 1-4 H8S/2398, H8S/2394, H8S/2392, H8S/2390 Pin Arrangement (FP-120: Top View) VCC PC0 /A0 PC1 /A1 PC2 /A2 PC3 /A3 VSS PC4 /A4 PC5 /A5 PC6 /A6 PC7 /A7 PB0 /A8 PB1 /A9 PB2 /A10 PB3 /A11 VSS PB4 /A12 PB5 /A13 PB6 /A14 PB7 /A15 PA0 /A16 PA1 /A17 PA2 /A18 PA3 /A19 VSS PA4 /A20 / IRQ4 PA5 /A21 / IRQ5 PA6 /A22 / IRQ6 PA7 /A23 / IRQ7 P67 / CS7/ IRQ3 P66 / CS6/ IRQ2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SCK2 / P52 ADTRG / P53 AVCC Vref AN0 / P40 AN1 / P41 AN2 / P42 AN3 / P43 AN4 / P44 AN5 / P45 DA0 / AN6 / P46 DA1 / AN7 / P47 AVSS VSS TCLKD / TIOCB2 / PO15 / P17 TIOCA2 / PO14 / P16 TCLKC / TIOCB1 / PO13 / P15 TIOCA1 / PO12 / P14 TCLKB / TIOCD0 / PO11 / P13 TCLKA / TIOCC0 / PO10 / P12 DACK1 / TIOCB0 / PO9 / P11 DACK0 / TIOCA0 / PO8 / P10 MD0 MD1 MD2 CAS / PG0 CS3 / PG1 CS2 / PG2 CS1 / PG3 CS0 / PG4 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P60 / DREQ0 / CS4 VSS P35 / SCK1 P34 / SCK0 P33 / RxD1 P32 / RxD0 P31 / TxD1 P30 / TxD0 VCC PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 VSS PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 VSS PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 VCC P64 / IRQ0 P65 / IRQ1 Rev.6.00 Oct.28.2004 page 9 of 1016 REJ09B0138-0600H AVCC Vref AN0 / P40 AN1 / P41 AN2 / P42 AN3 / P43 AN4 / P44 AN5 / P45 DA0 / AN6 / P46 DA1 / AN7 / P47 AVSS VSS TCLKD / TIOCB2 / PO15 / P17 TIOCA2 / PO14 / P16 TCLKC / TIOCB1 / PO13 / P15 TIOCA1 / PO12 / P14 TCLKB / TIOCD0 / PO11 / P13 TCLKA / TIOCC0 / PO10 / P12 DACK1 / TIOCB0 / PO9 / P11 DACK0 / TIOCA0 / PO8 / P10 MD0 MD1 MD2 CAS / PG0 CS3 / PG1 CS2 / PG2 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Rev.6.00 Oct.28.2004 page 10 of 1016 REJ09B0138-0600H Figure 1-5 H8S/2398, H8S/2394, H8S/2392, H8S/2390 Pin Arrangement (FP-128B: Top View) PG3 / CS1 PG4 / CS0 VSS NC VCC PC0 /A0 PC1 /A1 PC2 /A2 PC3 /A3 VSS PC4 /A4 PC5 /A5 PC6 /A6 PC7 /A7 PB0 /A8 PB1 /A9 PB2 /A10 PB3 /A11 VSS PB4 /A12 PB5 /A13 PB6 /A14 PB7 /A15 PA0 /A16 PA1 /A17 PA2 /A18 PA3 /A19 VSS PA4 /A20 / IRQ4 PA5 /A21 / IRQ5 PA6 /A22 / IRQ6 PA7 /A23 / IRQ7 P67 / CS7/ IRQ3 P66 / CS6/ IRQ2 VSS VSS P65 / IRQ1 P64 / IRQ0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 P35 / SCK1 P34 / SCK0 P33 / RxD1 P32 / RxD0 P31 / TxD1 P30 / TxD0 VCC PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 VSS PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 VSS PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 VCC P53 / ADTRG P52 /SCK2 VSS VSS P51 /RxD2 P50 /TxD2 PF0 / BREQ PF1 / BACK PF2 / LCAS/WAIT / BREQO PF3 / LWR PF4 / HWR PF5 / RD PF6 / AS VCC PF7 /ø VSS EXTAL XTAL VCC STBY NMI RES VCL P20 /PO0/TIOCA3 P21 /PO1/TIOCB3 P22 /PO2/TIOCC3/TMRI0 P23 /PO3/TIOCD3/TMCI0 P24 /PO4/TIOCA4/TMRI1 P25 /PO5/TIOCB4/TMCI1 P26 /PO6/TIOCA5/TMO0 P27 /PO7/TIOCB5/TMO1 P63 / TEND1 P62 / DREQ1 P61 / TEND0 / CS5 VSS VSS P60 / DREQ0 / CS4 VSS 1.3.2 Pin Functions in Each Operating Mode Table 1-2 shows the pin functions of the H8S/2357 Group in each of the operating modes. Table 1-2 Pin Functions in Each Operating Mode Pin No. Pin Name PROM Mode VCC A0 A1 A2 A3 VSS A4 A5 A6 A7 A8 OE A10 A11 VSS A12 A13 A14 A15 A16 VCC VCC NC VSS NC NC NC NC NC NC VSS VSS Flash Memory Programmer Mode VCC A0 A1 A2 A3 VSS A4 A5 A6 A7 A8 NC (A9)*3 A10 A11 VSS A12 A13 A14 A15 A16 NC (A17)*3 NC (A18)*3 NC VSS NC NC NC NC NC VCC VSS VSS TFP-120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 — — FP-128B 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Mode 4 *1 VCC A0 A1 A2 A3 VSS A4 A5 A6 A7 A8 A9 A10 A11 VSS A12 A13 A14 A15 A16 A17 A18 A19 VSS A20 PA 5/A 21 / IRQ5 PA 6/A 22 / IRQ6 PA 7/A 23 / IRQ7 P67/IRQ3 / CS7 P66/IRQ2 / CS6 VSS VSS Mode 5 *1 VCC A0 A1 A2 A3 VSS A4 A5 A6 A7 A8 A9 A10 A11 VSS A12 A13 A14 A15 A16 A17 A18 A19 VSS A20 PA 5/A 21 / IRQ5 PA 6/A 22 / IRQ6 PA 7/A 23 / IRQ7 P67/IRQ3 / CS7 P66/IRQ2 / CS6 VSS VSS Mode 6 VCC PC0/A 0 PC1/A 1 PC2/A 2 PC3/A 3 VSS PC4/A 4 PC5/A 5 PC6/A 6 PC7/A 7 PB 0/A 8 PB 1/A 9 PB 2/A 10 PB 3/A 11 VSS PB 4/A 12 PB 5/A 13 PB 6/A 14 PB 7/A 15 PA 0/A 16 PA 1/A 17 PA 2/A 18 PA 3/A 19 VSS PA 4/A 20 / IRQ4 PA 5/A 21 / IRQ5 PA 6/A 22 / IRQ6 PA 7/A 23 / IRQ7 P67/IRQ3 / CS7 P66/IRQ2 / CS6 VSS VSS Mode 7 VCC PC0 PC1 PC2 PC3 VSS PC4 PC5 PC6 PC7 PB 0 PB 1 PB 2 PB 3 VSS PB 4 PB 5 PB 6 PB 7 PA 0 PA 1 PA 2 PA 3 VSS PA 4/IRQ4 PA 5/IRQ5 PA 6/IRQ6 PA 7/IRQ7 P67/IRQ3 P66/IRQ2 VSS VSS Rev.6.00 Oct.28.2004 page 11 of 1016 REJ09B0138-0600H Pin No. Pin Name PROM Mode NC NC VCC NC NC NC NC VSS NC NC NC NC D0 D1 D2 D3 VSS D4 D5 D6 D7 VCC NC NC NC NC NC NC VSS NC VSS VSS NC NC NC NC Flash Memory Programmer Mode VSS VSS VCC NC NC NC NC VSS NC NC NC NC I/O0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 VCC NC NC NC (VCC)*3 NC NC NC VSS NC VSS VSS NC NC NC NC TFP-120 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 — — 61 62 63 64 FP-128B 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Mode 4 *1 P65/IRQ1 P64/IRQ0 VCC PE 0/D0 PE 1/D1 PE 2/D2 PE 3/D3 VSS PE 4/D4 PE 5/D5 PE 6/D6 PE 7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0 P35/SCK1 VSS Mode 5 *1 P65/IRQ1 P64/IRQ0 VCC PE 0/D0 PE 1/D1 PE 2/D2 PE 3/D3 VSS PE 4/D4 PE 5/D5 PE 6/D6 PE 7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0 P35/SCK1 VSS Mode 6 P65/IRQ1 P64/IRQ0 VCC PE 0/D0 PE 1/D1 PE 2/D2 PE 3/D3 VSS PE 4/D4 PE 5/D5 PE 6/D6 PE 7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0 P35/SCK1 VSS Mode 7 P65/IRQ1 P64/IRQ0 VCC PE 0 PE 1 PE 2 PE 3 VSS PE 4 PE 5 PE 6 PE 7 PD0 PD1 PD2 PD3 VSS PD4 PD5 PD6 PD7 VCC P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0 P35/SCK1 VSS P60/ DREQ0/ P60/ DREQ0/ P60/ DREQ0/ P60/DREQ0 CS4 CS4 CS4 VSS VSS P61/TEND0/ CS5 P62/DREQ1 P63/TEND1 P27/PO7/ TIOCB5/ TMO1 P26/PO6/ TIOCA5/ TMO0 VSS VSS P61/TEND0/ CS5 P62/DREQ1 P63/TEND1 P27/PO7/ TIOCB5/ TMO1 P26/PO6/ TIOCA5/ TMO0 VSS VSS P61/TEND0/ CS5 P62/DREQ1 P63/TEND1 P27/PO7/ TIOCB5/ TMO1 P26/PO6/ TIOCA5/ TMO0 VSS VSS P61/TEND0 P62/DREQ1 P63/TEND1 P27/PO7/ TIOCB5/ TMO1 P26/PO6/ TIOCA5/ TMO0 65 73 NC NC Rev.6.00 Oct.28.2004 page 12 of 1016 REJ09B0138-0600H Pin No. Pin Name PROM Mode NC Flash Memory Programmer Mode VCC (VSS ) *3 TFP-120 66 FP-128B 74 Mode 4 *1 P25/PO5/ TIOCB4/ TMCI 1 P24/PO4/ TIOCA4/ TMRI 1 P23/PO3/ TIOCD3/ TMCI 0 P22/PO2/ TIOCC3/ TMRI 0 P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 WDTOVF (FWE)*2 (VCL)*2 RES NMI STBY VCC XTAL EXTAL VSS PF7/ø VCC AS RD HWR LWR PF2/LCAS/ WAIT/ BREQO PF1/BACK PF0/BREQ P50/TxD2 P51/RxD2 VSS VSS P52/SCK2 P53/ADTRG AV CC Vref P40/AN0 P41/AN1 Mode 5 *1 P25/PO5/ TIOCB4/ TMCI 1 P24/PO4/ TIOCA4/ TMRI 1 P23/PO3/ TIOCD3/ TMCI 0 P22/PO2/ TIOCC3/ TMRI 0 P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 WDTOVF (FWE)*2 (VCL)*2 RES NMI STBY VCC XTAL EXTAL VSS PF7/ø VCC AS RD HWR LWR PF2/LCAS/ WAIT/ BREQO PF1/BACK PF0/BREQ P50/TxD2 P51/RxD2 VSS VSS P52/SCK2 P53/ADTRG AV CC Vref P40/AN0 P41/AN1 Mode 6 P25/PO5/ TIOCB4/ TMCI 1 P24/PO4/ TIOCA4/ TMRI 1 P23/PO3/ TIOCD3/ TMCI 0 P22/PO2/ TIOCC3/ TMRI 0 P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 WDTOVF (FWE)*2 (VCL)*2 RES NMI STBY VCC XTAL EXTAL VSS PF7/ø VCC AS RD HWR LWR PF2/LCAS/ WAIT/ BREQO PF1/BACK PF0/BREQ P50/TxD2 P51/RxD2 VSS VSS P52/SCK2 P53/ADTRG AV CC Vref P40/AN0 P41/AN1 Mode 7 P25/PO5/ TIOCB4/ TMCI 1 P24/PO4/ TIOCA4/ TMRI 1 P23/PO3/ TIOCD3/ TMCI 0 P22/PO2/ TIOCC3/ TMRI 0 P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 WDTOVF (FWE)*2 (VCL)*2 RES NMI STBY VCC XTAL EXTAL VSS PF7/ø VCC PF6 PF5 PF4 PF3 PF2 67 75 NC WE 68 76 NC CE 69 77 NC OE 70 71 72 78 79 80 NC NC NC NC NC FWE (VCL)*2 73 74 75 76 77 78 79 80 81 82 83 84 85 86 81 82 83 84 85 86 87 88 89 90 91 92 93 94 VPP A9 VSS VCC NC NC VSS NC VCC NC NC NC NC CE RES A9 (VCC)*3 VCC VCC XTAL EXTAL VSS NC VCC NC NC NC NC NC 87 88 89 90 — — 91 92 93 94 95 96 95 96 97 98 99 100 101 102 103 104 105 106 PF1 PF0 P50/TxD2 P51/RxD2 VSS VSS P52/SCK2 P53/ADTRG AV CC Vref P40/AN0 P41/AN1 PGM NC NC NC VSS VSS NC NC VCC VCC NC NC NC NC NC VCC (NC)*3 VSS VSS NC NC VCC VCC NC NC Rev.6.00 Oct.28.2004 page 13 of 1016 REJ09B0138-0600H Pin No. Pin Name PROM Mode NC NC NC NC NC NC VSS VSS NC Flash Memory Programmer Mode NC NC NC NC NC NC VSS VSS NC TFP-120 97 98 99 100 101 102 103 104 105 FP-128B 107 108 109 110 111 112 113 114 115 Mode 4 *1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ DA0 P47/AN7/ DA1 AV SS VSS P17/PO15/ TIOCB2/ TCLKD P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 MD0 MD1 MD2 PG 0/CAS PG 1/CS3 PG 2/CS2 PG 3/CS1 PG 4/CS0 VSS NC Mode 5 *1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ DA0 P47/AN7/ DA1 AV SS VSS P17/PO15/ TIOCB2/ TCLKD P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 MD0 MD1 MD2 PG 0/CAS PG 1/CS3 PG 2/CS2 PG 3/CS1 PG 4/CS0 VSS NC Mode 6 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ DA0 P47/AN7/ DA1 AV SS VSS P17/PO15/ TIOCB2/ TCLKD P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 MD0 MD1 MD2 PG 0/CAS PG 1/CS3 PG 2/CS2 PG 3/CS1 PG 4/CS0 VSS NC Mode 7 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ DA0 P47/AN7/ DA1 AV SS VSS P17/PO15/ TIOCB2/ TCLKD P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 MD0 MD1 MD2 PG 0 PG 1 PG 2 PG 3 PG 4 VSS NC 106 107 116 117 NC NC NC NC 108 109 118 119 NC NC NC NC 110 120 NC NC 111 121 NC NC 112 122 NC NC 113 114 115 116 117 118 119 120 — — 123 124 125 126 127 128 1 2 3 4 VSS VSS VSS NC NC NC NC NC VSS NC VSS VSS VSS NC NC NC NC NC VSS NC Notes: NC pins should be connected to VSS or left open. 1. In ROMless version, only modes 4 and 5 are available. 2. This pin functions as the WDTOVF pin function in ZTAT, and masked ROM products, and in the H8S/2352. In the H8S/2357F-ZTAT, the WDTOVF pin function is not available, because this pin is used as the FWE pin. In the H8S/2398, H8S/2394, H8S/2392, and H8S/2390, the WDTOVF pin function is not available, because this pin is used as the V CL pin. 3. The pin names in parentheses are available other than the H8S/2357 F-ZTAT. Rev.6.00 Oct.28.2004 page 14 of 1016 REJ09B0138-0600H 1.3.3 Pin Functions Table 1-3 outlines the pin functions of the H8S/2357 Group. Table 1-3 Pin Functions Pin No. Type Power Symbol VCC TFP-120 81, 76, 52, 33, 1 104, 79, 59, 47, 38, 24, 15, 6, FP-128B I/O 89, 84, 58, 39, 5, Input Name and Function Power supply: For connection to the power supply. All V CC pins should be connected to the system power supply. Ground: For connection to ground (0 V). All VSS pins should be connected to the system power supply (0 V). VSS 114, 100, Input 99, 87, 68, 67, 65, 53, 44, 36, 35, 28, 19, 10, 3 80 Internal voltage VCL*1 step-down drop pin Clock XTAL 72 INPUT Connects an external capacitor between this pin and the ground pin (0 V). This pin should never be connected to VCC. Input Connects to a crystal oscillator. See section 20, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. Connects to a crystal oscillator. The EXTAL pin can also input an external clock. See section 20, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. 77 85 EXTAL 78 86 Input ø 80 88 Output System clock: Supplies the system clock to an external device. Rev.6.00 Oct.28.2004 page 15 of 1016 REJ09B0138-0600H Pin No. Type Symbol TFP-120 115 to 113 FP-128B I/O 125 to 123 Input Name and Function Mode pins: These pins set the operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the H8S/2357 Group is operating. MD2 0 MD1 0 MD0 0 1 1 0 1 1 0 0 1 1 0 1 Operating Mode — — — — Mode 4* Mode 5* Mode 6 Mode 7 Operating mode MD2 to control MD0 Note: * In ROMless version, only modes 4 and 5 are available. System control RES 73 81 Input Reset input: When this pin is driven low, the chip is reset. The type of reset can be selected according to the NMI input level. At power-on, the NMI pin input level should be set high. Standby: When this pin is driven low, a transition is made to hardware standby mode. Bus request: Used by an external bus master to issue a bus request to the H8S/2357 Group. STBY 75 83 Input BREQ 88 96 Input BREQO 86 94 Output Bus request output: The external bus request signal used when an internal bus master accesses external space in the external busreleased state. Output Bus request acknowledge: Indicates that the bus has been released to an external bus master. Input Flash write enable: Enables/disables flash memory programming. Nonmaskable interrupt: Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high. Interrupt request 7 to 0: These pins request a maskable interrupt. BACK 87 95 FWE* 2 72 80 Interrupts NMI 74 82 Input IRQ7 to IRQ0 32 to 29, 28 to 25 38, 37, 34, 33, 32 to 29 Input Rev.6.00 Oct.28.2004 page 16 of 1016 REJ09B0138-0600H Pin No. Type Address bus Symbol A23 to A0 TFP-120 28 to 25, 23 to 16, 14 to 7, 5 to 2 51 to 48, 46 to 39, 37 to 34 FP-128B I/O 32 to 29, 27 to 20, 18 to 11, 9 to 6 57 to 54, 52 to 45, 43 to 40 Name and Function Output Address bus: These pins output an address. Data bus D15 to D0 CS7 to CS0 I/O Data bus: These pins constitute a bidirectional data bus. Bus control 120 to 117 128, 127, Output Chip select: Signals for selecting areas 7 to 0. 61, 60, 69, 66, 30, 29 34, 33, 2, 1 82 90 Output Address strobe: When this pin is low, it indicates that address output on the address bus is enabled. Output Read: When this pin is low, it indicates that the external address space can be read. Output High write/write enable: A strobe signal that writes to external space and indicates that the upper half (D15 to D8) of the data bus is enabled. The 2CAS type DRAM write enable signal. Output Low write: A strobe signal that writes to external space and indicates that the lower half (D7 to D0) of the data bus is enabled. Output Upper column address strobe/column address strobe: The 2CAS type DRAM upper column address strobe signal. Input Wait: Requests insertion of a wait state in the bus cycle when accessing external 3-state address space. AS RD 83 91 HWR 84 92 LWR 85 93 CAS 116 126 WAIT 86 94 LCAS 86 94 Output Lower column address strobe: The 2-CAS type DRAM lower column address strobe signal Input DMA request 1 and 0: These pins request DMAC activation. DMA controller (DMAC) DREQ1, DREQ0 TEND1, TEND0 DACK1, DACK0 62, 60 63, 61 70, 66 71, 69 Output DMA transfer end 1 and 0: These pins indicate the end of DMAC data transfer. Output DMA transfer acknowledge 1 and 0: These are the DMAC single address transfer acknowledge pins. 112, 111 122, 121 Rev.6.00 Oct.28.2004 page 17 of 1016 REJ09B0138-0600H Pin No. Type 16-bit timerpulse unit (TPU) Symbol TCLKD to TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TFP-120 FP-128B I/O Name and Function Clock input D to A: These pins input an external clock. Input capture/ output compare match A0 to D0: The TGR0A to TGR0D input capture input or output compare output, or PWM output pins. Input capture/ output compare match A1 and B1: The TGR1A and TGR1B input capture input or output compare output, or PWM output pins. Input capture/ output compare match A2 and B2: The TGR2A and TGR2B input capture input or output compare output, or PWM output pins. Input capture/ output compare match A3 to D3: The TGR3A to TGR3D input capture input or output compare output, or PWM output pins. Input capture/ output compare match A4 and B4: The TGR4A and TGR4B input capture input or output compare output, or PWM output pins. Input capture/ output compare match A5 and B5: The TGR5A and TGR5B input capture input or output compare output, or PWM output pins. 110, 109, 120, 119, Input 107, 105 117, 115 112 to 109 122 to 119 I/O 108, 107 118, 117 I/O TIOCA2, TIOCB2 106, 105 116, 115 I/O TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4 71 to 68 79 to 76 I/O 67, 66 75, 74 I/O TIOCA5, TIOCB5 65, 64 73, 72 I/O Programmable PO15 to pulse generator PO0 (PPG) 8-bit timer TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1 Watchdog timer (WDT) Serial communication interface (SCI) and Smart Card interface 112 to 105, 71 to 64 65, 64 68, 66 122 to 115, 79 to 72 73, 72 76, 74 Output Pulse output 15 to 0: Pulse output pins. Output Compare match output: The compare match output pins. Input Counter external clock input: Input pins for the external clock input to the counter. Counter external reset input: The counter reset input pins. 69, 67 77, 75 80 Input WDTOVF* 3 72 Output Watchdog timer overflows: The counter overflows signal output pin in watchdog timer mode. Output Transmit data (channel 0, 1, 2): Data output pins. Input Receive data (channel 0, 1, 2): Data input pins. Serial clock (channel 0, 1, 2): Clock I/O pins. TxD2, TxD1, TxD0 RxD2, RxD1, RxD0 SCK2, SCK1, SCK0 89, 54, 53 90, 56, 55 91, 58, 57 97, 60, 59 98, 62, 61 101, 64, 63 I/O Rev.6.00 Oct.28.2004 page 18 of 1016 REJ09B0138-0600H Pin No. Type A/D converter Symbol AN7 to AN0 ADTRG TFP-120 102 to 95 92 FP-128B I/O 112 to 105 102 Input Input Name and Function Analog 7 to 0: Analog input pins. A/D conversion external trigger input: Pin for input of an external trigger to start A/D conversion. D/A converter A/D converter and D/A converter DA1, DA0 AVCC 102, 101 93 112, 111 103 Output Analog output: D/A converter analog output pins. Input This is the power supply pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+5 V). This is the ground pin for the A/D converter and D/A converter. This pin should be connected to the system power supply (0 V). This is the reference voltage input pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+5 V). Port 1: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 1 data direction register (P1DDR). Port 2: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 2 data direction register (P2DDR). Port 3: A 6-bit I/O port. Input or output can be designated for each bit by means of the port 3 data direction register (P3DDR). Port 4: An 8-bit input port. Port 5: A 4-bit I/O port. Input or output can be designated for each bit by means of the port 5 data direction register (P5DDR). Port 6: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 6 data direction register (P6DDR). Port A: An 8-bit I/O port. Input or output can be designated for each bit by means of the port A data direction register (PADDR). AVSS 103 113 Input Vref 94 104 Input I/O ports P17 to P10 112 to 105 122 to 115 I/O P27 to P20 71 to 64 79 to 72 I/O P35 to P30 58 to 53 64 to 59 I/O P47 to P40 P53 to P50 102 to 95 92 to 89 112 to 105 Input 102, 101, I/O 98, 97 P67 to P60 63 to 60, 32 to 29 71 to 69, I/O 66, 38, 37, 34, 33 32 to 29, 27 to 24 I/O PA7 to PA0 28 to 25, 23 to 20 Rev.6.00 Oct.28.2004 page 19 of 1016 REJ09B0138-0600H Pin No. Type I/O ports Symbol PB7 to PB0 TFP-120 19 to 16, 14 to 11 FP-128B I/O 23 to 20, 18 to 15 I/O Name and Function Port B* 4: An 8-bit I/O port. Input or output can be designated for each bit by means of the port B data direction register (PBDDR). Port C* 4: An 8-bit I/O port. Input or output can be designated for each bit by means of the port C data direction register (PCDDR). Port D* 4: An 8-bit I/O port. Input or output can be designated for each bit by means of the port D data direction register (PDDDR). Port E: An 8-bit I/O port. Input or output can be designated for each bit by means of the port E data direction register (PEDDR). Port F: An 8-bit I/O port. Input or output can be designated for each bit by means of the port F data direction register (PFDDR). Port G: A 5-bit I/O port. Input or output can be designated for each bit by means of the port G data direction register (PGDDR). PC 7 to PC 0 10 to 7, 5 to 2 14 to 11, 9 to 6 I/O PD 7 to PD 0 51 to 48, 46 to 43 57 to 54, 52 to 49 I/O PE7 to PE0 42 to 39, 37 to 34 48 to 45, 43 to 40 I/O PF 7 to PF 0 88 to 82, 80 96 to 90, 88 I/O PG4 to PG0 120 to 116 128 to 126, 2, 1 I/O Notes: 1. 2. 3. 4. Applies to the H8S/2398, H8S/2394, H8S/2392, and H8S/2390 only. Applies to the H8S/2357F-ZTAT only. Not available in the F-ZTAT version, H8S/2398, H8S/2394, H8S/2392, H8S/2390. Applies to the on-chip ROM version only. Rev.6.00 Oct.28.2004 page 20 of 1016 REJ09B0138-0600H Section 2 CPU 2.1 Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2000 CPU has the following features. • Upward-compatible with H8/300 and H8/300H CPUs  Can execute H8/300 and H8/300H object programs • General-register architecture  Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • Sixty-five basic instructions  8/16/32-bit arithmetic and logic instructions  Multiply and divide instructions  Powerful bit-manipulation instructions • Eight addressing modes  Register direct [Rn]  Register indirect [@ERn]  Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]  Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]  Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]  Immediate [#xx:8, #xx:16, or #xx:32]  Program-counter relative [@(d:8,PC) or @(d:16,PC)]  Memory indirect [@@aa:8] • 16-Mbyte address space  Program: 16 Mbytes  Data: 16 Mbytes (architecturally 4-Gbyte) • High-speed operation  All frequently-used instructions execute in one or two states  Maximum clock rate : 20 MHz  8/16/32-bit register-register add/subtract : 50 ns  8 × 8-bit register-register multiply : 600 ns  16 ÷ 8-bit register-register divide : 600 ns  16 × 16-bit register-register multiply : 1000 ns  32 ÷ 16-bit register-register divide : 1000 ns • CPU operating mode  Advanced mode Rev.6.00 Oct.28.2004 page 21 of 1016 REJ09B0138-0600H • Power-down state  Transition to power-down state by SLEEP instruction  CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. • Register configuration The MAC register is supported only by the H8S/2600 CPU. • Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. • Number of execution states The number of exection states of the MULXU and MULXS instructions. Internal Operation Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21 There are also differences in the address space, CCR and EXR functions, power-down state, etc., depending on the product. 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers  Eight 16-bit expanded registers, and one 8-bit control register, have been added. • Expanded address space  Advanced mode supports a maximum 16-Mbyte address space. • Enhanced addressing  The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. • Enhanced instructions  Addressing modes of bit-manipulation instructions have been enhanced.  Signed multiply and divide instructions have been added.  2-bit shift instructions have been added.  Instructions for saving and restoring multiple registers have been added.  A test and set instruction has been added. • Higher speed  Basic instructions execute twice as fast. Rev.6.00 Oct.28.2004 page 22 of 1016 REJ09B0138-0600H 2.1.4 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. • Additional control register  One 8-bit control register has been added. • Enhanced instructions  Addressing modes of bit-manipulation instructions have been enhanced.  Two-bit shift instructions have been added.  Instructions for saving and restoring multiple registers have been added.  A test and set instruction has been added. • Higher speed  Basic instructions execute twice as fast. 2.2 CPU Operating Modes The H8S/2357 Group CPU has advanced operating mode. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data areas combined). The mode is selected by the mode pins of the microcontroller. 2.2.1 Advanced Mode Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program and data areas combined). Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. Instruction Set: All instructions and addressing modes can be used. Rev.6.00 Oct.28.2004 page 23 of 1016 REJ09B0138-0600H Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2-1). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Power-on reset exception vector H'00000003 H'00000004 Reserved Manual reset exception vector* H'00000007 H'00000008 Exception vector table H'0000000B H'0000000C (Reserved for system use) H'00000010 Reserved Exception vector 1 Note: * Manual reset is only supported in the H8S/2357 ZTAT. Figure 2-1 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table. Rev.6.00 Oct.28.2004 page 24 of 1016 REJ09B0138-0600H Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-2. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. SP SP Reserved PC (24 bits) *2 (SP ) EXR*1 Reserved*1*3 CCR PC (24 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. Figure 2-2 Stack Structure in Advanced Mode Rev.6.00 Oct.28.2004 page 25 of 1016 REJ09B0138-0600H 2.3 Address Space Figure 2-3 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 16Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'00000000 Program area H'00FFFFFF Data area Cannot be used by the H8S/2357 Group H'FFFFFFFF Advanced Mode Figure 2-3 Memory Map Rev.6.00 Oct.28.2004 page 26 of 1016 REJ09B0138-0600H 2.4 2.4.1 Register Configuration Overview The CPU has the internal registers shown in figure 2-4. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) Control Registers (CR) 23 PC 76543210 EXR T — — — — I2 I1 I0 76543210 CCR I UI H U N Z V C Legend: SP: Stack pointer PC: Program counter EXR: Extended control register T: Trace bit I2 to I0: Interrupt mask bits CCR: Condition-code register I: Interrupt mask bit UI: User bit or interrupt mask bit* 0 E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 H: U: N: Z: V: C: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Note: * In the H8S/2357 Group, this bit cannot be used as an interrupt mask. Figure 2-4 CPU Registers 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. Rev.6.00 Oct.28.2004 page 27 of 1016 REJ09B0138-0600H The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2-5 illustrates the usage of the general registers. The usage of each register can be selected independently. • Address registers • 32-bit registers • 16-bit registers E registers (extended registers) (E0 to E7) • 8-bit registers ER registers (ER0 to ER7) R registers (R0 to R7) RH registers (R0H to R7H) RL registers (R0L to R7L) Figure 2-5 Usage of General Registers General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-6 shows the stack. Free area SP (ER7) Stack area Figure 2-6 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) (2) Extended Control Register (EXR): This 8-bit register contains the trace bit (T) and three interrupt mask bits (I2 to I0). Bit 7—Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is executed. Bits 6 to 3—Reserved: These bits are reserved. They are always read as 1. Rev.6.00 Oct.28.2004 page 28 of 1016 REJ09B0138-0600H Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. All interrupts, including NMI, are disabled for three states after one of these instructions is executed, except for STC. (3) Condition-Code Register (CCR): This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller. Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. With the H8S/2357 Group, this bit cannot be used as an interrupt mask bit. Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data. Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: • Add instructions, to indicate a carry • Subtract instructions, to indicate a borrow • Shift and rotate instructions, to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to Appendix A.1, Instruction List. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. 2.4.4 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. Rev.6.00 Oct.28.2004 page 29 of 1016 REJ09B0138-0600H 2.5 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimaladjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2-7 shows the data formats in general registers. Data Type Register Number Data Format 1-bit data RnH 7 0 76543210 Don’t care 1-bit data RnL Don’t care 7 0 76543210 4-bit BCD data RnH 7 Upper 43 Lower 0 Don’t care 4-bit BCD data RnL Don’t care 7 Upper 43 Lower 0 Byte data RnH 7 MSB 0 Don’t care LSB 7 Don’t care 0 LSB Byte data RnL MSB Figure 2-7 General Register Data Formats Rev.6.00 Oct.28.2004 page 30 of 1016 REJ09B0138-0600H Data Type Register Number Data Format Word data Rn 15 MSB 0 LSB Word data 15 MSB Longword data 31 MSB En 0 LSB ERn 16 15 En Rn 0 LSB Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2-7 General Register Data Formats (cont) Rev.6.00 Oct.28.2004 page 31 of 1016 REJ09B0138-0600H 2.5.2 Memory Data Formats Figure 2-8 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 0 0 Data Format Byte data Address L MSB LSB Word data Address 2M MSB Address 2M + 1 LSB Longword data Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB Figure 2-8 Memory Data Formats When ER7 is used as an address register to access the stack, the operand size should be word size or longword size. Rev.6.00 Oct.28.2004 page 32 of 1016 REJ09B0138-0600H 2.6 2.6.1 Instruction Set Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2-1. Table 2-1 Instruction Classification Function Data transfer Instructions MOV POP* , PUSH* LDM, STM MOVFPE, MOVTPE* Arithmetic operations 3 1 1 Size BWL WL L B BWL B BWL L BW WL B BWL Types 5 ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS * 4 19 Logic operations Shift Bit manipulation Branch System control Block data transfer Total: AND, OR, XOR, NOT 4 8 14 5 9 1 65 SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc* 2, JMP, BSR, JSR, RTS B — TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — EEPMOV — Legend: B: Byte size W: Word size L: Longword size Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in the H8S/2357 Group. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev.6.00 Oct.28.2004 page 33 of 1016 REJ09B0138-0600H 2.6.2 Instructions and Addressing Modes Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2-2 Combinations of Instructions and Addressing Modes Addressing Modes @–ERn/@ERn+ @(d:16,ERn) @(d:32,ERn) @(d:8,PC) Function Instruction @ERn #xx @(d:16,PC) @@aa:8 @aa:16 @aa:24 @aa:32 @aa:8 Rn Data transfer MOV POP, PUSH LDM, STM MOVFPE, MOVTPE*1 ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, DIVXU MULXS, DIVXS NEG EXTU, EXTS TAS*2 BWL — — — BWL WL B — — — — — — — — BWL — — — — — — — — — B — B — — BWL — — — BWL BWL B L BWL B BW BW BWL WL — BWL BWL BWL B — — — — — — B B — — — BWL — — — — — — — — — — — — — B — — — B — — — — — — W W — — — BWL — — — — — — — — — — — — — — — — — — — — — — — — W W — — — BWL — — — — — — — — — — — — — — — — — — — — — — — — W W — — — BWL — — — — — — — — — — — — — — — — — — — — — — — — W W — — — B — — — — — — — — — — — — — — — — — B — — — — — — — — — — — BWL — — B — — — — — — — — — — — — — — B — — — — — — W W — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — BWL — — — — — — — — — — — — — — — — — B — — — — — — W W — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — WL L — — — — — — — — — — — — — — — — — — Arithmetic operations Logic operations AND, OR, XOR NOT Shift Bit manipulation Branch Bcc, BSR JMP, JSR RTS System control TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP Block data transfer Legend: B: Byte W: Word L: Longword — — — BW Notes: 1. Cannot be used in the H8S/2357 Group. 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev.6.00 Oct.28.2004 page 34 of 1016 REJ09B0138-0600H — 2.6.3 Table of Instructions Classified by Function Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3 is defined below. Operation Notation Rd Rs Rn ERn (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + – × ÷ ∧ ∨ ⊕ → ¬ :8/:16/:24/:32 General register (destination) * General register (source)* General register * General register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev.6.00 Oct.28.2004 page 35 of 1016 REJ09B0138-0600H Table 2-3 Instructions Classified by Function Type Data transfer Instruction MOV Size* 1 B/W/L Function (EAs) → Rd, Rs → (Ead) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Cannot be used in the H8S/2357 Group. Cannot be used in the H8S/2357 Group. @SP+ → Rn Pops a register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn → @–SP Pushes a register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP. @SP+ → Rn (register list) Pops two or more general registers from the stack. Rn (register list) → @–SP Pushes two or more general registers onto the stack. Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. Rd ± 1 → Rd, Rd ± 2 → Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust → Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd × Rs → Rd Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. Rd × Rs → Rd Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. MOVFPE MOVTPE POP B B W/L PUSH W/L LDM STM Arithmetic operations ADD SUB L L B/W/L ADDX SUBX B INC DEC B/W/L ADDS SUBS DAA DAS L B MULXU B/W MULXS B/W Rev.6.00 Oct.28.2004 page 36 of 1016 REJ09B0138-0600H Type Arithmetic operations Instruction DIVXU Size* 1 B/W Function Rd ÷ Rs → Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder. Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder. Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 – Rd → Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. @ERd – 0, 1 → ( of @ERd)* 2 Tests memory contents, and sets the most significant bit (bit 7) to 1. Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. ¬ (Rd) → (Rd) Takes the one's complement of general register contents. Rd (shift) → Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. Rd (shift) → Rd Performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. Rd (rotate) → Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. Rd (rotate) → Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. DIVXS B/W CMP B/W/L NEG B/W/L EXTU W/L EXTS W/L TAS B Logic operations AND B/W/L OR B/W/L XOR B/W/L NOT B/W/L Shift operations SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR B/W/L B/W/L B/W/L B/W/L Rev.6.00 Oct.28.2004 page 37 of 1016 REJ09B0138-0600H Type Bitmanipulation instructions Instruction BSET Size* 1 B Function 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ¬ ( of ) → ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ¬ ( of ) → Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. C ∧ ( of ) → C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ∧ ¬ ( of ) → C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ∨ ( of ) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ∨ ¬ ( of ) → C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ⊕ ( of ) → C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕ ¬ ( of ) → C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. ( of ) → C Transfers a specified bit in a general register or memory operand to the carry flag. ¬ ( of ) → C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. BCLR B BNOT B BTST B BAND B BIAND B BOR B BIOR B BXOR B BIXOR B BLD B BILD B Rev.6.00 Oct.28.2004 page 38 of 1016 REJ09B0138-0600H Type Bitmanipulation instructions Instruction BST Size* 1 B Function C → ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. ¬ C → ( of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never C∨Z=0 C∨Z=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 N⊕V=0 N⊕V=1 Z∨(N ⊕ V) = 0 Z∨(N ⊕ V) = 1 BIST B Branch instructions Bcc — JMP BSR JSR RTS System control TRAPA instructions RTE SLEEP LDC — — — — — — — B/W Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine. Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR → (EAd), EXR → (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. STC B/W Rev.6.00 Oct.28.2004 page 39 of 1016 REJ09B0138-0600H Type Instruction Size* 1 B Function CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR Logically ANDs the CCR or EXR contents with immediate data. CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR Logically ORs the CCR or EXR contents with immediate data. CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 → PC Only increments the program counter. if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6. R4L or R4: size of block (bytes) ER5: starting source address ER6: starting destination address Execution of the next instruction begins as soon as the transfer is completed. System control ANDC instructions ORC B XORC B NOP Block data transfer instruction EEPMOV.B — — EEPMOV.W — Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev.6.00 Oct.28.2004 page 40 of 1016 REJ09B0138-0600H 2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2-9 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc. rn rm MOV.B @(d:16, Rn), Rm, etc. Figure 2-9 Instruction Formats (Examples) (1) Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first 4 bits of the instruction. Some instructions have two operation fields. (2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. (3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. (4) Condition Field: Specifies the branching condition of Bcc instructions. 2.7 2.7.1 Addressing Modes and Effective Address Calculation Addressing Mode The CPU supports the eight addressing modes listed in table 2-4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Rev.6.00 Oct.28.2004 page 41 of 1016 REJ09B0138-0600H Table 2-4 Addressing Modes No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @–ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 (1) Register Direct—Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. (2) Register Indirect—@ERn: The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). (3) Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn): A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. (4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. • Register indirect with pre-decrement—@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. (5) Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2-5 indicates the accessible absolute address ranges. Rev.6.00 Oct.28.2004 page 42 of 1016 REJ09B0138-0600H Table 2-5 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF (6) Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an even number. (8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'000000 to H'0000FF). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Specified by @aa:8 Reserved Branch address Advanced Mode Figure 2-10 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) Rev.6.00 Oct.28.2004 page 43 of 1016 REJ09B0138-0600H 2.7.2 No. Effective Address Calculation Addressing Mode and Instruction Format Effective Address (EA) 1 rm rn Operand is general register contents. Table 2-6 Register direct (Rn) op 2 31 General register contents Don’t care r 0 31 24 23 0 Register indirect (@ERn) op 3 31 General register contents 31 24 23 r disp 31 Sign extension disp 0 Don’t care 0 0 Rev.6.00 Oct.28.2004 page 44 of 1016 REJ09B0138-0600H Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) Effective Address Calculation Effective Address Calculation op 4 31 General register contents r 1, 2, or 4 31 General register contents 31 r Operand Size Value added Byte Word Longword 1 2 4 1, 2, or 4 0 0 31 Register indirect with post-increment or pre-decrement • Register indirect with post-increment @ERn+ 24 23 0 Don’t care op • Register indirect with pre-decrement @–ERn 24 23 Don’t care 0 Table 2-6 indicates how effective addresses are calculated in each addressing mode. op No. Effective Address Calculation 5 @aa:8 31 24 23 H'FFFF abs Don’t care Addressing Mode and Instruction Format Absolute address 87 0 Effective Address (EA) op @aa:16 31 op abs Don’t care 16 15 24 23 Sign extension 0 @aa:24 31 abs Don’t care 24 23 0 op @aa:32 op abs 31 24 23 Don’t care 0 6 op IMM Immediate #xx:8/#xx:16/#xx:32 Operand is immediate data. Rev.6.00 Oct.28.2004 page 45 of 1016 REJ09B0138-0600H No. Effective Address Calculation 23 PC contents @(d:8, PC)/@(d:16, PC) 0 7 Program-counter relative Addressing Mode and Instruction Format Effective Address (EA) op 23 Sign extension disp 31 24 23 Don’t care disp 0 0 8 Memory indirect @@aa:8 • Advanced mode op 31 0 abs 0 Memory contents 31 H'000000 31 87 abs Rev.6.00 Oct.28.2004 page 46 of 1016 REJ09B0138-0600H 24 23 Don’t care 0 2.8 2.8.1 Processing States Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2-11 shows a diagram of the processing states. Figure 2-12 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, interrupt, or trap instruction. Processing states Program execution state The CPU executes program instructions in sequence. Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU. Sleep mode Power-down state CPU operation is stopped to conserve power.* Software standby mode Hardware standby mode Note: * The power-down state also includes a medium-speed mode, module stop mode etc. Figure 2-11 Processing States Rev.6.00 Oct.28.2004 page 47 of 1016 REJ09B0138-0600H End of bus request Bus request Program execution state End of bus request Bus request SLEEP instruction with SSBY = 0 Bus-released state End of exception handling Request for exception handling SLEEP instruction with SSBY = 1 Sleep mode Interrupt request Exception-handling state External interrupt RES = high Software standby mode Reset state*1 STBY = high, RES = low Hardware standby mode*2 Power-down state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. Figure 2-12 State Transitions 2.8.2 Reset State When the RES input goes low all current processing stops and the CPU enters the reset state. The CPU enters the poweron reset state when the NMI pin is high, or the manual reset* state when the NMI pin is low. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, refer to section 13, Watchdog Timer. Note: * Manual reset is only supported in the H8S/2357 ZTAT. 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2-7 indicates the types of exception handling and their priority. Trap instruction exception handling is always accepted, in the program execution state. Exception handling and the stack structure depend on the interrupt control mode set in SYSCR. Rev.6.00 Oct.28.2004 page 48 of 1016 REJ09B0138-0600H Table 2-7 Exception Handling Types and Priority Priority High Type of Exception Reset Detection Timing Synchronized with clock Start of Exception Handling Exception handling starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. When the trace (T) bit is set to 1, the trace starts at the end of the current instruction or current exception-handling sequence When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Exception handling starts when a trap (TRAPA) instruction is executed * 3 Trace End of instruction execution or end of exception-handling sequence* 1 End of instruction execution or end of exception-handling sequence* 2 When TRAPA instruction is executed Interrupt Trap instruction Low Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not executed at the end of the RTE instruction. 2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. 3. Trap instruction exception handling is always accepted, in the program execution state. (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. The CPU enters the power-on reset state when the NMI pin is high, or the manual reset* state when the NMI pin is low. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. Note : * Manual reset is only supported in the H8S/2357 ZTAT. (3) Traces Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR is set to 1. When trace mode is established, trace exception handling starts at the end of each instruction. At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode is cleared. Interrupt masks are not affected. The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to return from the trace exception-handling routine, trace mode is entered again. Trace exception-handling is not executed at the end of the RTE instruction. Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit. (4) Interrupt Exception Handling and Trap Instruction Exception Handling When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution starts from that start address. Rev.6.00 Oct.28.2004 page 49 of 1016 REJ09B0138-0600H Figure 2-13 shows the stack after exception handling ends. Advanced mode SP SP CCR PC (24 bits) EXR Reserved* CCR PC (24 bits) (c) Interrupt control mode 0 Note: *Ignored when returning. (d) Interrupt control mode 2 Figure 2-13 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts. There is two more bus masters in addition to the CPU: the DMA contraler (DMAC) and data transfer controller (DTC). For further details, refer to section 6, Bus Controller. 2.8.6 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are three modes in which the CPU stops operating: sleep mode, software standby mode, and hardware standby mode. There are also two other power-down modes: medium-speed mode, and module stop mode. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. For details, refer to section 21, Power-Down Modes. (1) Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) in the standby control register (SBYCR) is cleared to 0. In sleep mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU registers are retained. (2) Software Standby Mode: A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1. In software standby mode, the CPU and clock halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states. Rev.6.00 Oct.28.2004 page 50 of 1016 REJ09B0138-0600H (3) Hardware Standby Mode: A transition to hardware standby mode is made when the STBY pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. 2.9 2.9.1 Basic Timing Overview The CPU is driven by a system clock, denoted by the symbol ø. The period from one rising edge of ø to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 On-Chip Memory (ROM, RAM) On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 2-14 shows the on-chip memory access cycle. Figure 2-15 shows the pin states. Bus cycle T1 ø Internal address bus Internal read signal Internal data bus Internal write signal Write access Internal data bus Write data Read data Address Read access Figure 2-14 On-Chip Memory Access Cycle Rev.6.00 Oct.28.2004 page 51 of 1016 REJ09B0138-0600H Bus cycle T1 ø Address bus AS RD HWR, LWR Data bus Unchanged High High High High-impedance state Figure 2-15 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2-16 shows the access timing for the on-chip supporting modules. Figure 2-17 shows the pin states. Bus cycle T1 T2 ø Internal address bus Address Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Write data Read data Figure 2-16 On-Chip Supporting Module Access Cycle Rev.6.00 Oct.28.2004 page 52 of 1016 REJ09B0138-0600H Bus cycle T1 T2 ø Address bus Unchanged AS RD HWR, LWR High High High Data bus High-impedance state Figure 2-17 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6, Bus Controller. 2.10 2.10.1 Usage Note TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas H8S and H8/300 Series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used. Rev.6.00 Oct.28.2004 page 53 of 1016 REJ09B0138-0600H Rev.6.00 Oct.28.2004 page 54 of 1016 REJ09B0138-0600H Section 3 MCU Operating Modes 3.1 3.1.1 Overview Operating Mode Selection (H8S/2357 F-ZTAT Only) The H8S/2357 F-ZTAT has eight operating modes (modes 4 to 7, 10, 11, 14 and 15). These modes are determined by the mode pin (MD2 to MD0) and flash write enable pin (FWE) settings. The CPU operating mode and initial bus width can be selected as shown in table 3-1. Table 3-1 lists the MCU operating modes. Table 3-1 MCU Operating Mode Selection (H8S/2357 F-ZTAT Only) External Data Bus On-Chip Initial ROM Width — — Max. Width — MCU CPU Operating Operating Mode FWE MD2 MD1 MD0 Mode Description 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 1 0 1 1 0 0 1 1 0 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Advanced User program mode — — Advanced Boot mode — — — Advanced On-chip ROM disabled, Disabled 16 bits 16 bits expanded mode 8 bits 16 bits On-chip ROM enabled, Enabled 8 bits expanded mode Single-chip mode — — — — 16 bits — — Enabled 8 bits — — — 16 bits — — Enabled 8 bits — 16 bits — The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2357 Group actually accesses a maximum of 16 Mbytes. Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. Note that the functions of each pin depend on the operating mode. Modes 10, 11, 14, and 15 are boot modes and user program modes in which the flash memory can be programmed and erased. For details, see section 19, ROM. Rev.6.00 Oct.28.2004 page 55 of 1016 REJ09B0138-0600H The H8S/2357 F-ZTAT can only be used in modes 4 to 7, 10, 11, 14, and 15. This means that the flash write enable pin and mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.2 Operating Mode Selection (ZTAT, Masked ROM, ROMless Version, and H8S/2398 F-ZTAT) The H8S/2357 Group has four operating modes (modes 4 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD 2 to MD0). Table 3-2 lists the MCU operating modes. Table 3-2 MCU Operating Mode Selection (ZTAT, Masked ROM, ROMless , and H8S/2398 F-ZTAT) MCU CPU Operating Operating Description Mode MD2 MD1 MD0 Mode 0 1 2* 3* 4* 5* 6 7 1 1 2 2 External Data Bus On-Chip Initial ROM Width — — Max. Width — 0 0 0 1 — — 1 0 1 1 0 0 1 Advanced On-chip ROM disabled, Disabled 16 bits expanded mode 8 bits On-chip ROM enabled, Enabled 8 bits expanded mode Single-chip mode — 16 bits 16 bits 16 bits — 1 0 1 Notes: 1. In the H8S/2398 F-ZTAT, modes 2 and 3 indicate boot mode. For details on boot mode of the H8S/2398 FZTAT version, refer to table 19-35 in section 19.17, On-Board Programming Modes. In addition, for details on user program mode, refer also to tables 19-35 in section 19.17, On-Board Programming Modes. 2. In ROMless version, only modes 4 and 5 are available. The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2357 Group actually accesses a maximum of 16 Mbytes. Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. Note that the functions of each pin depend on the operating mode. The H8S/2357 Group cannot be used in modes 4 to 7. This means that the mode pins must be set to select 4 to 7 modes. Do not change the inputs at the mode pins during operation. Rev.6.00 Oct.28.2004 page 56 of 1016 REJ09B0138-0600H 3.1.3 Register Configuration The H8S/2357 Group has a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) and a system control register 2 (SYSCR2)*2 that control the operation of the H8S/2357 Group. Table 3-3 summarizes these registers. Table 3-3 MCU Registers Name Mode control register System control register System control register 2 * 2 Abbreviation MDCR SYSCR SYSCR2 R/W R R/W R/W Initial Value Undetermined H'01 H'00 Address* 1 H'FF3B H'FF39 H'FF42 Notes: 1. Lower 16 bits of the address. 2. The SYSCR2 register can only be used in the F-ZTAT version. In the masked ROM and ZTAT versions, this register cannot be written to and will return an undefined value if read. 3.2 3.2.1 Bit Register Descriptions Mode Control Register (MDCR) : 7 — 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 MDS2 —* R 1 MDS1 —* R 0 MDS0 —* R Initial value : R/W : 1 — Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2357 Group. Bit 7—Reserved: This bit cannot be modified and is always read as 1. Bits 6 to 3—Reserved: These bits cannot be modified and are always read as 0. Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are read-only bits, they cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a power-on reset, but are retained after a manual reset.* Note: * Manual reset is only supported in the H8S/2357 ZTAT. 3.2.2 Bit System Control Register (SYSCR) : 7 — 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 — 0 —* 1 — 0 R/W 0 RAME 1 R/W Initial value : R/W : 0 R/W Note: * R/W in the H8S/2390, H8S/2392, H8S/2394, and H8S/2398. Rev.6.00 Oct.28.2004 page 57 of 1016 REJ09B0138-0600H Bit 7—Reserved: Only 0 should be written to this bit. Bit 6—Reserved: This bit cannot be modified and is always read as 0. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and Interrupt Operation. Bit 5 INTM1 0 Bit 4 INTM0 0 1 1 0 1 Interrupt Control Mode Description 0 — 2 — Control of interrupts by I bit Setting prohibited Control of interrupts by I2 to I0 bits and IPR Setting prohibited (Initial value) Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input. Bit 3 NMIEG 0 1 Description An interrupt is requested at the falling edge of NMI input An interrupt is requested at the rising edge of NMI input (Initial value) Bit 2—Reserved: This bit cannot be modified and is always read as 0. This bit is reserved in the H8S/2390, H8S/2392, H8S/2394, and H8S/2398. Only 0 should be written to this bit. Bit 1—Reserved: Only 0 should be written to this bit. Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset status is released. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) 3.2.3 Bit System Control Register 2 (SYSCR2) (F-ZTAT Version Only) : 7 — 6 — 0 — 5 — 0 — 4 — 0 — 3 FLSHE 0 R/W 2 — 0 — 1 — 0 — 0 — 0 — Initial value : R/W : 0 — SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control. SYSCR2 is initialized to H'00 by a reset and in hardware standby mode. SYSCR2 can only be accessed in the F-ZTAT version. In other versions, this register cannot be written to and will return an undefined value if read. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0. Rev.6.00 Oct.28.2004 page 58 of 1016 REJ09B0138-0600H Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). For details, see section 19, ROM. Bit 3 FLSHE 0 1 Description Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB (Initial value) Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 0. Rev.6.00 Oct.28.2004 page 59 of 1016 REJ09B0138-0600H 3.3 3.3.1 Operating Mode Descriptions Mode 1 Mode 1 is not supported in this LSI, and must not be set. 3.3.2 Mode 2 (H8S/2398 F-ZTAT Only) This is a flash memory boot mode. For details, see section 19, ROM. MCU operation is the same as in mode 6. 3.3.3 Mode 3 (H8S/2398 F-ZTAT Only) This is a flash memory boot mode. For details, see section 19, ROM. MCU operation is the same as in mode 7. 3.3.4 Mode 4 (On-Chip ROM Disabled Expansion Mode) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B and C function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. 3.3.5 Mode 5 (On-Chip ROM Disabled Expansion Mode) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B and C function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.6 Mode 6 (On-Chip ROM Enabled Expansion Mode) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Ports A, B and C function as input ports immediately after a reset. They can each be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port D functions as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. Rev.6.00 Oct.28.2004 page 60 of 1016 REJ09B0138-0600H 3.3.7 Mode 7 (Single-Chip Mode) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. 3.3.8 Modes 8 and 9 Modes 8 and 9 are not supported in the H8S/2357 Group, and must not be set. 3.3.9 Mode 10 (H8S/2357 F-ZTAT Only) This is a flash memory boot mode. For details, see section 19, ROM. MCU operation is the same as in mode 6. 3.3.10 Mode 11 (H8S/2357 F-ZTAT Only) This is a flash memory boot mode. For details, see section 19, ROM. MCU operation is the same as in mode 7. 3.3.11 Modes 12 and 13 (H8S/2357 F-ZTAT Only) Modes 12 and 13 are not supported in the H8S/2357 Group, and must not be set. 3.3.12 Mode 14 (H8S/2357 F-ZTAT Only) This is a flash memory user program mode. For details, see section 19, ROM. MCU operation is the same as in mode 6. 3.3.13 Mode 15 (H8S/2357 F-ZTAT Only) This is a flash memory user program mode. For details, see section 19, ROM. MCU operation is the same as in mode 7. Rev.6.00 Oct.28.2004 page 61 of 1016 REJ09B0138-0600H 3.4 Pin Functions in Each Operating Mode The pin functions of ports A to F vary depending on the operating mode. Table 3-4 shows their functions in each operating mode. Table 3-4 Port Pin Functions in Each Mode Mode 2* 4 Mode 3* 4 P Mode 4* 2 P* 1/A A P* /A P* /A D P* /D P/C* 1 1 1 1 1 Mode 5* 2 P* 1/A A A A D Mode 6 P* 1/A P* 1/A P* /A D 1 Mode 7 P Mode 10* 3 P* 1/A P* 1/A P* /A D P* /D 1 1 Mode 11* 3 P Mode 14* 3 P* 1/A P* 1/A P* /A D P* /D 1 1 Mode 15* 3 P Port A PA7 to PA 5 P* 1/A PA4 to PA 0 Port B Port C Port D Port E Port F PF 7 P P P P P/C* P 1 A A D P/D* P/C* C P* /C 1 1 1 P P P P P P P P* /C P 1 P P P P P* 1/C P P* /D P/C* C P* /C 1 1 1 P* /D P/C* C P* /C 1 1 1 P P* /C P 1 P/C* C 1 1 P/C* C 1 1 PF 6 to PF3 C PF 2 to PF0 P* /C P* /C P* /C Legend: P: I/O port A: Address bus output D: Data bus I/O C: Control signals, clock I/O Notes: 1. After reset 2. In ROMless version, only modes 4 and 5 are available. 3. Applies to the H8S/2357 F-ZTAT only. 4. Applies to the H8S/2398 F-ZTAT only. 3.5 Memory Map in Each Operating Mode Figures 3-1 to 3-5 show memory maps for each of the operating modes. The address space is 16 Mbytes in modes 4 to 7. The address space is divided into eight areas for modes 4 to 7. For details, see section 6, Bus Controller. Rev.6.00 Oct.28.2004 page 62 of 1016 REJ09B0138-0600H Modes 4 and 5*4 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM External address space H'010000 H'00FFFF H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 H'01FFFF H'020000 H'FFDC00 On-chip RAM*3 H'FFFC00 H'FFFE40 H'FFFF08 H'FFFF28 H'FFFFFF H'FFDC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF External address space Internal I/O registers External address space Internal I/O registers External address space H'FFDC00 On-chip RAM H'FFFE40 H'FFFF07 Internal I/O registers H'FFFF28 H'FFFFFF Internal I/O registers Notes: 1. 2. 3. 4. External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Only modes 4 and 5 are provided in the H8S/2352. Figure 3-1 Memory Map in Each Operating Mode (H8S/2357, H8S/2352) (1) Rev.6.00 Oct.28.2004 page 63 of 1016 REJ09B0138-0600H Mode 10*4 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 11*4 Boot Mode (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 H'01FFFF H'020000 H'FFDC00 On-chip RAM *3 External address space H'FFDC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF H'FFFE40 H'FFFF07 Internal I/O registers H'FFFF28 H'FFFFFF Internal I/O registers Notes: 1. External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 2. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 3. On-chip RAM is used for flash memory programming. Do not clear the RAME bit to 0 in SYSCR. 4. Modes 10 and 11 are provided in the F-ZTAT version only. Figure 3-1 Memory Map in Each Operating Mode (H8S/2357, H8S/2352) (2) Rev.6.00 Oct.28.2004 page 64 of 1016 REJ09B0138-0600H Mode 14*4 User Program Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 15*4 User Program Mode (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 H'01FFFF H'020000 H'FFDC00 On-chip RAM *3 External address space H'FFDC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF H'FFFE40 H'FFFF07 Internal I/O registers H'FFFF28 H'FFFFFF Internal I/O registers Notes: 1. External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 2. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 3. On-chip RAM is used for flash memory programming. Do not clear the RAME bit to 0 in SYSCR. 4. Modes 14 and 15 are provided in the F-ZTAT version only. Figure 3-1 Memory Map in Each Operating Mode (H8S/2357, H8S/2352) (3) Rev.6.00 Oct.28.2004 page 65 of 1016 REJ09B0138-0600H Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 H'FFEC00 Reserved space*1 On-chip RAM*2 H'FFFC00 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. This is a reserved space. Access to this space is inhibited. The space can be made available for use as an external address space by clearing the RAME bit of the SYSCR to 0. 2. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3-2 Memory Map in Each Operating Mode (H8S/2390) Rev.6.00 Oct.28.2004 page 66 of 1016 REJ09B0138-0600H Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 On-chip RAM* H'FFFC00 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3-3 Memory Map in Each Operating Mode (H8S/2392) Rev.6.00 Oct.28.2004 page 67 of 1016 REJ09B0138-0600H Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FF7C00 On-chip RAM* H'FFFC00 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3-4 Memory Map in Each Operating Mode (H8S/2394) Rev.6.00 Oct.28.2004 page 68 of 1016 REJ09B0138-0600H Mode 2*5 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 3*5 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2*4 H'03FFFF H'040000 H'FFDC00 On-chip H'FFFC00 H'FFFE40 H'FFFF08 H'FFFF28 H'FFFFFF RAM*3 H'FFFBFF External address space Internal I/O registers External address space Internal I/O registers External address space H'FFDC00 On-chip RAM*3 H'FFFE40 H'FFFF07 Internal I/O registers H'FFFF28 H'FFFFFF Internal I/O registers Notes: 1. External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 2. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 3. The on-chip RAM is used when programming and erasing flash memory. Do not clear the RAME bit in SYSCR to 0. 4. Access to the reserved area is inhibited. 5. Modes 2 and 3 are provided in the F-ZTAT version only. Figure 3-5 Memory Map in Each Operating Mode (H8S/2398) (1) Rev.6.00 Oct.28.2004 page 69 of 1016 REJ09B0138-0600H Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM External address space H'010000 H'00FFFF H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2*4 H'03FFFF H'040000 H'FFDC00 On-chip RAM*3 H'FFFC00 H'FFFE40 H'FFFF08 H'FFFF28 H'FFFFFF H'FFDC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF External address space Internal I/O registers External address space Internal I/O registers External address space H'FFDC00 On-chip RAM H'FFFE40 H'FFFF07 Internal I/O registers H'FFFF28 H'FFFFFF Internal I/O registers Notes: 1. 2. 3. 4. External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Access to the reserved area is inhibited. Figure 3-5 Memory Map in Each Operating Mode (H8S/2398) (2) Rev.6.00 Oct.28.2004 page 70 of 1016 REJ09B0138-0600H Section 4 Exception Handling 4.1 4.1.1 Overview Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times, in the program execution state. Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR. Table 4-1 Exception Types and Priority Priority High Exception Type Reset Start of Exception Handling Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. The CPU enters the power-on reset state when the NMI pin is high, or the manual reset* 4 state when the NMI pin is low. Starts when execution of the current instruction or exception handling ends, if the trace (T) bit is set to 1 Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued* 2 Trace* 1 Interrupt Low Trap instruction (TRAPA)*3 Started by execution of a trap instruction (TRAPA) Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in program execution state. 4. Manual reset is only supported in the H8S/2357 ZTAT. Rev.6.00 Oct.28.2004 page 71 of 1016 REJ09B0138-0600H 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out. 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4-1. Different vector addresses are assigned to different exception sources. Table 4-2 lists the exception sources and their vector addresses. Reset Trace Exception sources Interrupts Power-on reset Manual reset* External interrupts: NMI, IRQ7 to IRQ0 Internal interrupts: 52 interrupt sources in on-chip supporting modules Trap instruction Note: * Manual reset is only supported in the H8S/2357 ZTAT. Figure 4-1 Exception Sources In modes 6 and 7 the on-chip ROM available for use after a power-on reset is the 64-kbyte area comprising addresses H'000000 to H'00FFFF. Care is required when setting vector addresses. In this case, clearing the EAE bit in BCRL enables the 128-kbyte (256-kbyte)* area comprising address H'000000 to H'01FFFF (H'03FFFF)* to be used. Note: * Since these values are different according to the on-chip ROM capacitance, see section 3.5, Memory Map in Each Operating Mode. Rev.6.00 Oct.28.2004 page 72 of 1016 REJ09B0138-0600H Table 4-2 Exception Vector Table Vector Address * 1 Exception Source Power-on reset Manual reset* 3 Vector Number 0 1 2 3 4 Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063  H'016C to H'016F Reserved for system use Trace Reserved for system use External interrupt NMI 5 6 7 8 9 10 11 Trap instruction (4 sources) Reserved for system use 12 13 14 15 External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 16 17 18 19 20 21 22 23 24  91 Internal interrupt * 2 Notes: 1. Lower 16 bits of the address. 2. For details of internal interrupt vectors, see section 5.3.3, Interrupt Exception Handling Vector Table. 3. Manual reset is only supported in the H8S/2357 ZTAT. Rev.6.00 Oct.28.2004 page 73 of 1016 REJ09B0138-0600H 4.2 4.2.1 Reset Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2357 Group enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the RES pin changes from low to high. In the F-ZTAT, masked ROM, and ROMless versions, a reset is always a power-on reset, regardless of the NMI pin level at the time. Also, a reset caused by the watchdog timer is always a power-on reset, regardless of the setting of the RSTS bit in the RSTCR register. In the ZTAT version, a reset may be either a power-on reset or a manual reset*, according to the NMI pin level at the time. A reset caused by the watchdog timer, also, may be either a power-on reset or a manual reset*. For details see section 13, Watchdog Timer. Note: * Manual reset is only supported in the H8S/2357 ZTAT. 4.2.2 Reset Types A reset can be of either of two types: a power-on reset or a manual reset*. Reset types are shown in table 4-3. A power-on reset should be used when powering on. The internal state of the CPU is initialized by either type of reset. A power-on reset also initializes all the registers in the on-chip supporting modules, while a manual reset* initializes all the registers in the on-chip supporting modules except for the bus controller and I/O ports, which retain their previous states. With a manual reset*, since the on-chip supporting modules are initialized, ports used as on-chip supporting module I/O pins are switched to I/O ports controlled by DDR and DR. Table 4-3 Reset Types Reset Transition Conditions Type Manual reset* NMI Low RES Low Low CPU Power-on reset High Initialized Initialized Initialized Initialized, except for bus controller and I/O ports Internal State On-Chip Supporting Modules A reset caused by the watchdog timer can also be of either of two types: a power-on reset or a manual reset*. Note: * Manual reset is only supported in the H8S/2357 ZTAT. Rev.6.00 Oct.28.2004 page 74 of 1016 REJ09B0138-0600H 4.2.3 Reset Sequence The H8S/2357 Group enters the reset state when the RES pin goes low. To ensure that the H8S/2357 Group is reset, hold the RES pin low for at least 20 ms at power-up. To reset the H8S/2357 Group during operation, hold the RES pin low for at least 20 states. When the RES pin goes high after being held low for the necessary time, the H8S/2357 Group starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip supporting modules are initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figure 4-2 show examples of the reset sequence. Internal Prefetch of first processing program instruction * * Vector fetch * ø RES Address bus RD HWR, LWR D15 to D0 (2) (1) (3) (5) High (4) (6) (1) (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) (5) Start address ((5) = (2) (4)) (6) First program instruction Note: * 3 program wait states are inserted. Figure 4-2 Reset Sequence (Mode 4) Rev.6.00 Oct.28.2004 page 75 of 1016 REJ09B0138-0600H 4.2.4 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx:32, SP). 4.2.5 State of On-Chip Supporting Modules after Reset Release After reset release, MSTPCR is initialized to H'3FFF and all modules except the DMAC and DTC enter module stop mode. Consequently, on-chip supporting module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited. 4.3 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking. Table 4-4 shows the state of CCR and EXR after execution of trace exception handling. Interrupts are accepted even within the trace exception handling routine. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Table 4-4 Status of CCR and EXR after Trace Exception Handling CCR Interrupt Control Mode 0 2 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution. 1 I UI I2 to I0 EXR T Trace exception handling cannot be used. — — 0 Rev.6.00 Oct.28.2004 page 76 of 1016 REJ09B0138-0600H 4.4 Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 52 internal sources in the on-chip supporting modules. Figure 4-3 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), refresh timer, 16-bit timer-pulse unit (TPU), 8-bit timer, serial communication interface (SCI), data transfer controller (DTC), DMA controller (DMAC), and A/D converter. Each interrupt source has a separate vector address. NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. For details of interrupts, see section 5, Interrupt Controller. External interrupts Interrupts NMI (1) IRQ7 to IRQ0 (8) Internal interrupts WDT*1 (1) Refresh timer*2 (1) TPU (26) 8-bit timer (6) SCI (12) DTC (1) DMAC (4) A/D converter (1) Notes: Numbers in parentheses are the numbers of interrupt sources. 1. When the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. 2. When the refresh timer is used as an interval timer, it generates an interrupt request at each compare match. Figure 4-3 Interrupt Sources and Number of Interrupts Rev.6.00 Oct.28.2004 page 77 of 1016 REJ09B0138-0600H 4.5 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4-5 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4-5 Status of CCR and EXR after Trap Instruction Exception Handling CCR Interrupt Control Mode 0 2 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution. I 1 1 UI — — I2 to I0 — — EXR T — 0 4.6 Stack Status after Exception Handling Figure 4-4 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP SP CCR PC (24 bits) EXR Reserved* CCR PC (24 bits) (a) Interrupt control mode 0 Note: * Ignored on return. (b) Interrupt control mode 2 Figure 4-4 Stack Status after Exception Handling (Advanced Modes) Rev.6.00 Oct.28.2004 page 78 of 1016 REJ09B0138-0600H 4.7 Notes on Use of the Stack When accessing word data or longword data, the H8S/2357 Group assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4-5 shows an example of what happens when the SP value is odd. CCR SP PC SP R1L PC H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFF SP TRAPA instruction executed MOV.B R1L, @–ER7 SP set to H'FFFEFF Data saved above SP Contents of CCR lost Legend: CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4-5 Operation when SP Value is Odd Rev.6.00 Oct.28.2004 page 79 of 1016 REJ09B0138-0600H Rev.6.00 Oct.28.2004 page 80 of 1016 REJ09B0138-0600H Section 5 Interrupt Controller 5.1 5.1.1 Overview Features The H8S/2357 Group controls interrupts by means of an interrupt controller. The interrupt controller has the following features: • Two interrupt control modes  Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with IPR  An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI.  NMI is assigned the highest priority level of 8, and can be accepted at all times. • Independent vector addresses  All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. • Nine external interrupts  NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI.  Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ7 to IRQ0. • DTC and DMAC control  DTC and DMAC activation is performed by means of interrupts. Rev.6.00 Oct.28.2004 page 81 of 1016 REJ09B0138-0600H 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in Figure 5-1. INTM1, INTM0 SYSCR NMIEG NMI input IRQ input NMI input unit IRQ input unit ISR ISCR IER Priority determination I I2 to I0 Interrupt request Vector number CPU Internal interrupt request SWDTEND to TEI CCR EXR IPR Interrupt controller Legend: ISCR: IRQ sense control register IRQ enable register IER: IRQ status register ISR: Interrupt priority register IPR: SYSCR: System control register Figure 5-1 Block Diagram of Interrupt Controller 5.1.3 Pin Configuration Table 5-1 summarizes the pins of the interrupt controller. Table 5-1 Interrupt Controller Pins Name Nonmaskable interrupt External interrupt requests 7 to 0 Symbol NMI I/O Input Function Nonmaskable external interrupt; rising or falling edge can be selected Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected IRQ7 to IRQ0 Input Rev.6.00 Oct.28.2004 page 82 of 1016 REJ09B0138-0600H 5.1.4 Register Configuration Table 5-2 summarizes the registers of the interrupt controller. Table 5-2 Interrupt Controller Registers Name System control register IRQ sense control register H IRQ sense control register L IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt priority register I Interrupt priority register J Interrupt priority register K Abbreviation SYSCR ISCRH ISCRL IER ISR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 2 Initial Value H'01 H'00 H'00 H'00 H'00 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 Address* 1 H'FF39 H'FF2C H'FF2D H'FF2E H'FF2F H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. 5.2 5.2.1 Bit Register Descriptions System Control Register (SYSCR) : 7 — 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 — 0 —* 1 — 0 R/W 0 RAME 1 R/W Initial value : R/W : 0 R/W Note: * R/W in the H8S/2390, H8S/2392, H8S/2394, and H8S/2398. SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control Register (SYSCR). SYSCR is initialized to H'01 by a reset and in hardware standby mode. It is not initialized in software standby mode. Rev.6.00 Oct.28.2004 page 83 of 1016 REJ09B0138-0600H Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes for the interrupt controller. Bit 5 INTM1 0 Bit 4 INTM0 0 1 1 0 1 Interrupt Control Mode 0 — 2 — Description Interrupts are controlled by I bit Setting prohibited Interrupts are controlled by bits I2 to I0, and IPR Setting prohibited (Initial value) Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. Bit 3 NMIEG 0 1 Description Interrupt request generated at falling edge of NMI input Interrupt request generated at rising edge of NMI input (Initial value) 5.2.2 Bit Interrupt Priority Registers A to K (IPRA to IPRK) : 7 — 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W 3 — 0 — 2 IPR2 1 R/W 1 IPR1 1 R/W 0 IPR0 1 R/W Initial value : R/W : 0 — The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between IPR settings and interrupt sources is shown in table 5-3. The IPR registers set a priority (levels 7 to 0) for each interrupt source other than NMI. The IPR registers are initialized to H'77 by a reset and in hardware standby mode. Bits 7 and 3—Reserved: These bits cannot be modified and are always read as 0. Rev.6.00 Oct.28.2004 page 84 of 1016 REJ09B0138-0600H Table 5-3 Correspondence between Interrupt Sources and IPR Settings Bits Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK 6 to 4 IRQ0 IRQ2 IRQ3 IRQ6 IRQ7 Watchdog timer —* TPU channel 0 TPU channel 2 TPU channel 4 8-bit timer channel 0 DMAC SCI channel 1 2 to 0 IRQ1 IRQ4 IRQ5 DTC Refresh timer A/D converter TPU channel 1 TPU channel 3 TPU channel 5 8-bit timer channel 1 SCI channel 0 SCI channel 2 Note: * Reserved bits. These bits cannot be modified and are always read as 1. As shown in table 5-3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority level, level 7, by setting H'7. When interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to the CPU. 5.2.3 Bit IRQ Enable Register (IER) : 7 IRQ7E 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W Initial value : R/W : 0 R/W IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ7 to IRQ0. IER is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to IRQ0 are enabled or disabled. Bit n IRQnE 0 1 Description IRQn interrupts disabled IRQn interrupts enabled (n = 7 to 0) (Initial value) Rev.6.00 Oct.28.2004 page 85 of 1016 REJ09B0138-0600H 5.2.4 ISCRH Bit IRQ Sense Control Registers H and L (ISCRH, ISCRL) : 15 14 13 12 11 10 9 8 IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : R/W ISCRL Bit : 7 6 5 4 3 2 1 0 : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0. ISCR registers are initialized to H'0000 by a reset and in hardware standby mode. Bits 15 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB) Bits 15 to 0 IRQ7SCB to IRQ0SCB 0 IRQ7SCA to IRQ0SCA 0 1 1 0 1 Description Interrupt request generated at IRQ7 to IRQ0 input low level (Initial value) Interrupt request generated at falling edge of IRQ7 to IRQ0 input Interrupt request generated at rising edge of IRQ7 to IRQ0 input Interrupt request generated at both falling and rising edges of IRQ7 to IRQ0 input 5.2.5 Bit IRQ Status Register (ISR) : 7 IRQ7F 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* Initial value : R/W : 0 R/(W)* Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0—IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests. Rev.6.00 Oct.28.2004 page 86 of 1016 REJ09B0138-0600H Bit n IRQnF 0 Description [Clearing conditions] • • • • (Initial value) Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1) When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 1 [Setting conditions] • • • • When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA = 0) When a falling edge occurs in IRQn input when falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1) When a rising edge occurs in IRQn input when rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0) When a falling or rising edge occurs in IRQn input when both-edge detection is set (IRQnSCB = IRQnSCA = 1) (n = 7 to 0) 5.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (52 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ2 to IRQ0 can be used to restore the H8S/2357 Group from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. The vector number for NMI interrupt exception handling is 7. IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to IRQ0 have the following features: • Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ7 to IRQ0. • Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER. • The interrupt priority level can be set with IPR. • The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5-2. Rev.6.00 Oct.28.2004 page 87 of 1016 REJ09B0138-0600H IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input IRQn interrupt S R Q request Clear signal Note: n=7 to 0 Figure 5-2 Block Diagram of Interrupts IRQ7 to IRQ0 Figure 5-3 shows the timing of setting IRQnF. ø IRQn input pin IRQnF Figure 5-3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as an I/O pin for another function. 5.3.2 Internal Interrupts There are 52 sources for internal interrupts from on-chip supporting modules. • For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. • The interrupt priority level can be set by means of IPR. • The DMAC and DTC can be activated by a TPU, SCI, or other interrupt request. When the DMAC or DTC is activated by an interrupt, the interrupt control mode and interrupt mask bits are not affected. 5.3.3 Interrupt Exception Handling Vector Table Table 5-4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of the IPR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5-4. Rev.6.00 Oct.28.2004 page 88 of 1016 REJ09B0138-0600H Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address* Vector Number 7 16 17 18 19 20 21 22 23 DTC Watchdog timer Refresh controller — A/D — 24 25 26 27 28 29 30 31 32 33 34 35 36 — 37 38 39 40 41 42 43 TPU channel 2 44 45 46 47 Advanced Mode H'001C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C H'0060 H'0064 H'0068 H'006C H'0070 H'0074 H'0078 H'007C H'0080 H'0084 H'0088 H'008C H'0090 H'0094 H'0098 H'009C H'00A0 H'00A4 H'00A8 H'00AC H'00B0 H'00B4 H'00B8 H'00BC Low IPRG6 to 4 IPRF2 to 0 IPRF6 to 4 IPR — IPRA6 to 4 IPRA2 to 0 IPRB6 to 4 IPRB2 to 0 IPRC6 to 4 IPRC2 to 0 IPRD6 to 4 IPRD2 to 0 IPRE6 to 4 IPRE2 to 0 Priority High Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 SWDTEND (software activation interrupt end) WOVI (interval timer) CMI (compare match) Reserved ADI (A/D conversion end) Reserved Origin of Interrupt Source External pin TGI0A (TGR0A input capture/ compare match) TGI0B (TGR0B input capture/ compare match) TGI0C (TGR0C input capture/ compare match) TGI0D (TGR0D input capture/ compare match) TCI0V (overflow 0) Reserved TPU channel 0 TGI1A (TGR1A input capture/ compare match) TGI1B (TGR1B input capture/ compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input capture/ compare match) TGI2B (TGR2B input capture/ compare match) TCI2V (overflow 2) TCI2U (underflow 2) TPU channel 1 Rev.6.00 Oct.28.2004 page 89 of 1016 REJ09B0138-0600H Interrupt Source TGI3A (TGR3A input capture/ compare match) TGI3B (TGR3B input capture/ compare match) TGI3C (TGR3C input capture/ compare match) TGI3D (TGR3D input capture/ compare match) TCI3V (overflow 3) Reserved Origin of Interrupt Source TPU channel 3 Vector Address* Vector Number 48 49 50 51 52 Advanced Mode H'00C0 H'00C4 H'00C8 H'00CC H'00D0 H'00D4 H'00D8 H'00DC H'00E0 H'00E4 H'00E8 H'00EC H'00F0 H'00F4 H'00F8 H'00FC H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011C H'0120 H'0124 H'0128 H'012C H'0130 H'0134 H'0138 H'013C IPRJ6 to 4 IPRI2 to 0 IPRI6 to 4 IPRH2 to 0 IPRH6 to 4 IPR IPRG2 to 0 Priority High — 53 54 55 56 57 58 59 TGI4A (TGR4A input capture/ compare match) TGI4B (TGR4B input capture/ compare match) TCI4V (overflow 4) TCI4U (underflow 4) TGI5A (TGR5A input capture/ compare match) TGI5B (TGR5B input capture/ compare match) TCI5V (overflow 5) TCI5U (underflow 5) CMIA0 (compare match A0) CMIB0 (compare match B0) OVI0 (overflow 0) Reserved CMIA1 (compare match A1) CMIB1 (compare match B1) OVI1 (overflow 1) Reserved DEND0A (channel 0/channel 0A transfer end) DEND0B (channel 0B transfer end) DEND1A (channel 1/channel 1A transfer end) DEND1B (channel 1B transfer end) Reserved TPU channel 4 TPU channel 5 60 61 62 63 8-bit timer channel 0 64 65 66 67 68 69 70 71 72 73 74 75 — 8-bit timer channel 1 — DMAC — 76 77 78 79 Low Rev.6.00 Oct.28.2004 page 90 of 1016 REJ09B0138-0600H Interrupt Source ERI0 (receive error 0) RXI0 (reception data full 0) TXI0 (transmit data empty 0) TEI0 (transmission end 0) ERI1 (receive error 1) RXI1 (reception data full 1) TXI1 (transmit data empty 1) TEI1 (transmission end 1) ERI2 (receive error 2) RXI2 (reception data full 2) TXI2 (transmit data empty 2) TEI2 (transmission end 2) Note: * Lower 16 bits of the start address. Origin of Interrupt Source SCI channel 0 Vector Address* Vector Number 80 81 82 83 Advanced Mode H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C Low IPRK2 to 0 IPRK6 to 4 IPR IPRJ2 to 0 Priority High SCI channel 1 84 85 86 87 SCI channel 2 88 89 90 91 5.4 5.4.1 Interrupt Operation Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2357 Group differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 5-5 shows the interrupt control modes. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated by the I and UI bits in the CPU’s CCR, and bits I2 to I0 in EXR. Table 5-5 Interrupt Control Modes SYSCR Interrupt Priority Setting Control Mode INTM1 INTM0 Registers 0 — 2 1 0 0 1 0 — — IPR Interrupt Mask Bits Description I — I2 to I0 Interrupt mask control is performed by the I bit. Setting prohibited 8-level interrupt mask control is performed by bits I2 to I0. 8 priority levels can be set with IPR. Setting prohibited — 1 — — Rev.6.00 Oct.28.2004 page 91 of 1016 REJ09B0138-0600H Figure 5-4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 I Interrupt acceptance control Interrupt source Default priority determination 8-level mask control Vector number IPR I2 to I0 Interrupt control mode 2 Figure 5-4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5-6 shows the interrupts selected in each interrupt control mode. Table 5-6 Interrupts Selected in Each Interrupt Control Mode (1) Interrupt Mask Bits Interrupt Control Mode 0 I 0 1 2 × Selected Interrupts All interrupts NMI interrupts All interrupts × : Don't care (2) 8-Level Control In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level. Table 5-7 Interrupts Selected in Each Interrupt Control Mode (2) Interrupt Control Mode 0 2 Selected Interrupts All interrupts Highest-priority-level (IPR) interrupt whose priority level is greater than the mask level (IPR > I2 to I0). Rev.6.00 Oct.28.2004 page 92 of 1016 REJ09B0138-0600H (3) Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5-8 shows operations and control signal functions in each interrupt control mode. Table 5-8 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Control Setting Mode INTM1 INTM0 0 2 0 1 0 0 Interrupt Acceptance Control I IM × —* 1 Default 8-Level Control Priority I2 to I0 IPR Determination ×— IM —* 2 PR T (Trace) — T Legend : Interrupt operation control performed ×: No operation. (All interrupts enabled) IM: Used as interrupt mask bit PR: Sets priority —: Not used Notes: 1. Set to 1 when interrupt is accepted. 2. Keep the initial setting. 5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Figure 5-5 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. [3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. Rev.6.00 Oct.28.2004 page 93 of 1016 REJ09B0138-0600H Program execution status Interrupt generated? Yes Yes No NMI No No I=0 Yes Hold pending No IRQ0 Yes No IRQ1 Yes TEI2 Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5-5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev.6.00 Oct.28.2004 page 94 of 1016 REJ09B0138-0600H 5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5-6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5-4 is selected. [3] Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. Rev.6.00 Oct.28.2004 page 95 of 1016 REJ09B0138-0600H Program execution status Interrupt generated? Yes Yes NMI No No No Level 7 interrupt? Yes Mask level 6 or below? Yes Level 6 interrupt? No Yes Mask level 5 or below? Yes No Level 1 interrupt? No Yes No Mask level 0 Yes No Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5-6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev.6.00 Oct.28.2004 page 96 of 1016 REJ09B0138-0600H 5.4.4 Interrupt acceptance Instruction prefetch Stack Vector fetch Internal operation Internal operation Interrupt service routine instruction prefetch Interrupt level determination Wait for end of instruction ø Interrupt Exception Handling Sequence Interrupt request signal Internal address bus (1) (7) (9) (3) (5) (11) (13) Internal read signal Internal write signal (2) (8) Figure 5-7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Figure 5-7 Interrupt Exception Handling (4) (6) (10) (12) Internal data bus (14) Rev.6.00 Oct.28.2004 page 97 of 1016 REJ09B0138-0600H (1) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4 (6) (8) Saved PC and saved CCR (9) (11) Vector address (10) (12) Interrupt handling routine start address (vector address contents) (13) Interrupt handling routine start address ((13) = (10) (12)) (14) First instruction of interrupt handling routine 5.4.5 Interrupt Response Times The H8S/2357 Group is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5-9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5-9 are explained in table 510. Table 5-9 Interrupt Response Times Advanced Mode No. 1 2 3 4 5 6 Notes: 1. 2. 3. 4. Execution Status Interrupt priority determination* 1 Number of wait states until executing instruction ends* 2 PC, CCR, EXR stack save Vector fetch Instruction fetch * 3 4 INTM1 = 0 3 1 to (19+2·SI) 2·S K 2·S I 2·S I 2 12 to 32 INTM1 = 1 3 1 to (19+2·SI) 3·S K 2·S I 2·S I 2 13 to 33 Internal processing* Total (using on-chip memory) Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Table 5-10 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8-Bit Bus Symbol Instruction fetch Branch address read Stack manipulation SI SJ SK Internal Memory 1 2-State Access 4 3-State Access 6 + 2m 16-Bit Bus 2-State Access 2 3-State Access 3+m Legend: m: Number of wait states in an external device access. Rev.6.00 Oct.28.2004 page 98 of 1016 REJ09B0138-0600H 5.5 5.5.1 Usage Notes Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higherpriority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared. Figure 5-8 shows an example in which the TGIEA bit in the TPU’s TIER0 register is cleared to 0. TIER0 write cycle by CPU TGI0A exception handling ø Internal address bus TIER0 address Internal write signal TGIEA TGFA TGI0A interrupt signal Figure 5-8 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 5.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. Rev.6.00 Oct.28.2004 page 99 of 1016 REJ09B0138-0600H 5.5.3 Times when Interrupts are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. 5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 5.6 5.6.1 DTC and DMAC Activation by Interrupt Overview The DTC and DMAC can be activated by an interrupt. In this case, the following options are available: • • • • Interrupt request to CPU Activation request to DTC Activation request to DMAC Selection of a number of the above For details of interrupt requests that can be used with to activate the DTC or DMAC, see section 8, Data Transfer Controller, and section 7, DMA Controller. Rev.6.00 Oct.28.2004 page 100 of 1016 REJ09B0138-0600H 5.6.2 Block Diagram Figure 5-9 shows a block diagram of the DTC and DMAC interrupt controller. DMAC Disable signal Clear signal Interrupt request IRQ interrupt Interrupt source On-chip clear signal supporting module Selection circuit Select signal Clear signal DTCER DTC activation request vector number Control logic Clear signal DTC DTVECR SWDTE clear signal Determination of priority CPU interrupt request vector number CPU I, I2 to I0 Interrupt controller Figure 5-9 Interrupt Control for DTC and DMAC 5.6.3 Operation The interrupt controller has three main functions in DTC and DMAC control. Selection of Interrupt Source: With the DMAC, the activation source is input directly to each channel. The activation source for each DMAC channel is selected with bits DTF3 to DTF0 in DMACR. Whether the selected activation source is to be managed by the DMAC can be selected with the DTA bit of DMABCR. When the DTA bit is set to 1, the interrupt source constituting that DMAC activation source is not a DTC activation source or CPU interrupt source. For interrupt sources other than interrupts managed by the DMAC, it is possible to select DTC activation request or CPU interrupt request with the DTCE bit of DTCERA to DTCERF in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of MRB in the DTC. When the DTC has performed the specified number of data transfers and the transfer counter value is zero, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU after the DTC data transfer. Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 7.6, Interrupts, and section 8.3.3, DTC Vector Table, for the respective priorities. With the DMAC, the activation source is input directly to each channel. Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. Rev.6.00 Oct.28.2004 page 101 of 1016 REJ09B0138-0600H If the same interrupt is selected as a DMAC activation source and a DTC activation source or CPU interrupt source, operations are performed for them independently according to their respective operating statuses and bus mastership priorities. Table 5-11 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTA bit of DMABCR in the DMAC, the DTCE bit of DTCERA to DTCERF in the DTC and the DISEL bit of MRB in the DTC. Table 5-11 Interrupt Source Selection and Clearing Control Settings DMAC DTA 0 DTC DTCE 0 1 DISEL * 0 1 1 * * Interrupt Source Selection/Clearing Control DMAC DTC × CPU ∆ × ∆ ∆ × ∆ × Legend: ∆ : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. × : The relevant bit cannot be used. * : Don't care 5.6.4 Note on Use SCI and A/D converter interrupt sources are cleared when the DMAC or DTC reads or writes to the prescribed register, and are not dependent upon the DTA bit or DISEL bit. Rev.6.00 Oct.28.2004 page 102 of 1016 REJ09B0138-0600H Section 6 Bus Controller 6.1 Overview The H8S/2357 Group has a on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU, DMA controller (DMAC), and data transfer controller (DTC). 6.1.1 Features The features of the bus controller are listed below. • Manages external address space in area units  In advanced mode, manages the external space as 8 areas of 2-Mbytes  Bus specifications can be set independently for each area  DRAM/burst ROM interfaces can be set • Basic bus interface  Chip select ( CS0 to CS7) can be output for areas 0 to 7  8-bit access or 16-bit access can be selected for each area  2-state access or 3-state access can be selected for each area  Program wait states can be inserted for each area • DRAM interface  DRAM interface can be set for areas 2 to 5 (in advanced mode)  Row address/column address multiplexed output (8/9/10 bits)  Two byte access methods (2-CAS)  Burst operation (fast page mode)  TP cycle insertion to secure RAS precharging time  Choice of CAS-before-RAS refreshing or self-refreshing • Burst ROM interface  Burst ROM interface can be set for area 0  Choice of 1- or 2-state burst access • Idle cycle insertion  An idle cycle can be inserted in case of an external read cycle between different areas  An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle • Write buffer functions  External write cycle and internal access can be executed in parallel  DMAC single-address mode and internal access can be executed in parallel • Bus arbitration function  Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, and DTC Rev.6.00 Oct.28.2004 page 103 of 1016 REJ09B0138-0600H • Other features  Refresh counter (refresh timer) can be used as an interval timer  External bus release function Rev.6.00 Oct.28.2004 page 104 of 1016 REJ09B0138-0600H 6.1.2 Block Diagram Figure 6-1 shows a block diagram of the bus controller. CS0 to CS7 Area decoder Internal address bus ABWCR External bus control signals ASTCR BCRH BCRL BREQ BACK BREQO Bus controller Internal control signals Bus mode signal WAIT WCRH WCRL DRAM controller MCR External DRAM signals DRAMCR RTCNT RTCOR CPU bus request signal DTC bus request signal Bus arbiter DMAC bus request signal CPU bus acknowledge signal DTC bus acknowledge signal DMAC bus acknowledge signal Figure 6-1 Block Diagram of Bus Controller Internal data bus Wait controller Rev.6.00 Oct.28.2004 page 105 of 1016 REJ09B0138-0600H 6.1.3 Pin Configuration Table 6-1 summarizes the pins of the bus controller. Table 6-1 Bus Controller Pins Symbol I/O AS RD HWR Output Output Output Function Strobe signal indicating that address output on address bus is enabled. Strobe signal indicating that external space is being read. Strobe signal indicating that external space is to be written, and upper half (D 15 to D8) of data bus is enabled. 2-CAS DRAM write enable signal. Strobe signal indicating that external space is to be written, and lower half (D7 to D0) of data bus is enabled. Strobe signal indicating that area 0 is selected. Strobe signal indicating that area 1 is selected. Strobe signal indicating that area 2 is selected. DRAM row address strobe signal when area 2 is in DRAM space. Strobe signal indicating that area 3 is selected. DRAM row address strobe signal when area 3 is in DRAM space. Strobe signal indicating that area 4 is selected. DRAM row address strobe signal when area 4 is in DRAM space. Strobe signal indicating that area 5 is selected. DRAM row address strobe signal when area 5 is in DRAM space. Strobe signal indicating that area 6 is selected. Strobe signal indicating that area 7 is selected. 2-CAS DRAM upper column address strobe signal. DRAM lower column address strobe signal. Wait request signal when accessing external 3state access space. Request signal that releases bus to external device. Acknowledge signal indicating that bus has been released. External bus request signal used when internal bus master accesses external space when external bus is released. Name Address strobe Read High write/write enable Low write LWR Output Chip select 0 Chip select 1 Chip select 2/row address strobe 2 Chip select 3/row address strobe 3 Chip select 4/row address strobe 4 Chip select 5/row address strobe 5 Chip select 6 Chip select 7 Upper column address strobe Lower column strobe Wait Bus request Bus request acknowledge Bus request output CS0 CS1 CS2 Output Output Output CS3 Output CS4 Output CS5 Output CS6 CS7 CAS LCAS WAIT BREQ BACK Output Output Output Output Input Input Output BREQO Output Rev.6.00 Oct.28.2004 page 106 of 1016 REJ09B0138-0600H 6.1.4 Register Configuration Table 6-2 summarizes the registers of the bus controller. Table 6-2 Bus Controller Registers Initial Value Name Bus width control register Access state control register Wait control register H Wait control register L Bus control register H Bus control register L Memory control register DRAM control register Refresh timer/counter Refresh time constant register Abbreviation ABWCR ASTCR WCRH WCRL BCRH BCRL MCR DRAMCR RTCNT RTCOR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Power-On Reset H'FF/H'00* 2 H'FF H'FF H'FF H'D0 H'3C H'00 H'00 H'00 H'FF Manual Reset * 3 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Address* 1 H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FED6 H'FED7 H'FED8 H'FED9 Notes: 1. Lower 16 bits of the address. 2. Determined by the MCU operating mode. 3. Manual reset is only supported in the H8S/2357 ZTAT. Rev.6.00 Oct.28.2004 page 107 of 1016 REJ09B0138-0600H 6.2 6.2.1 Bit Register Descriptions Bus Width Control Register (ABWCR) : 7 ABW7 6 ABW6 5 ABW5 4 ABW4 3 ABW3 2 ABW2 1 ABW1 0 ABW0 Modes 5 to 7 Initial value : R/W Mode 4 Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W : 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. ABWCR sets the data bus width for the external memory space. The bus width for on-chip memory and internal I/O registers is fixed regardless of the settings in ABWCR. After a power-on reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 5 to 7,*1 and to H'00 in mode 4. It is not initialized by a manual reset*2 or in software standby mode. Notes: 1. In ROMless version, modes 6 and 7 are not available. 2. Manual reset is only supported in the H8S/2357 ZTAT. Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the corresponding area is to be designated for 8-bit access or 16-bit access. Bit n ABWn 0 1 Description Area n is designated for 16-bit access Area n is designated for 8-bit access (n = 7 to 0) Rev.6.00 Oct.28.2004 page 108 of 1016 REJ09B0138-0600H 6.2.2 Bit Access State Control Register (ASTCR) : 7 AST7 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W 3 AST3 1 R/W 2 AST2 1 R/W 1 AST1 1 R/W 0 AST0 1 R/W Initial value : R/W : 1 R/W ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR. ASTCR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset* or in software standby mode. Note: * Manual reset is only supported in the H8S/2357 ZTAT. Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is to be designated as a 2-state access space or a 3-state access space. Wait state insertion is enabled or disabled at the same time. Bit n ASTn 0 1 Description Area n is designated for 2-state access Wait state insertion in area n external space is disabled Area n is designated for 3-state access Wait state insertion in area n external space is enabled (Initial value) (n = 7 to 0) Rev.6.00 Oct.28.2004 page 109 of 1016 REJ09B0138-0600H 6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a power-on reset and in hardware standby mode. They are not initialized by a manual reset* or in software standby mode. Note: * Manual reset is only supported in the H8S/2357 ZTAT. (1) WCRH Bit : 7 W71 Initial value : R/W : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3 W51 1 R/W 2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1. Bit 7 W71 0 Bit 6 W70 0 1 1 0 1 Description Program wait not inserted when external space area 7 is accessed 1 program wait state inserted when external space area 7 is accessed 2 program wait states inserted when external space area 7 is accessed 3 program wait states inserted when external space area 7 is accessed (Initial value) Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit 5 W61 0 Bit 4 W60 0 1 1 0 1 Description Program wait not inserted when external space area 6 is accessed 1 program wait state inserted when external space area 6 is accessed 2 program wait states inserted when external space area 6 is accessed 3 program wait states inserted when external space area 6 is accessed (Initial value) Rev.6.00 Oct.28.2004 page 110 of 1016 REJ09B0138-0600H Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 W51 0 Bit 2 W50 0 1 1 0 1 Description Program wait not inserted when external space area 5 is accessed 1 program wait state inserted when external space area 5 is accessed 2 program wait states inserted when external space area 5 is accessed 3 program wait states inserted when external space area 5 is accessed (Initial value) Bits 1 and 0—Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1. Bit 1 W41 0 Bit 0 W40 0 1 1 0 1 Description Program wait not inserted when external space area 4 is accessed 1 program wait state inserted when external space area 4 is accessed 2 program wait states inserted when external space area 4 is accessed 3 program wait states inserted when external space area 4 is accessed (Initial value) (2) WCRL Bit : 7 W31 Initial value : R/W : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3 W11 1 R/W 2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1. Bit 7 W31 0 Bit 6 W30 0 1 1 0 1 Description Program wait not inserted when external space area 3 is accessed 1 program wait state inserted when external space area 3 is accessed 2 program wait states inserted when external space area 3 is accessed 3 program wait states inserted when external space area 3 is accessed (Initial value) Rev.6.00 Oct.28.2004 page 111 of 1016 REJ09B0138-0600H Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1. Bit 5 W21 0 Bit 4 W20 0 1 1 0 1 Description Program wait not inserted when external space area 2 is accessed 1 program wait state inserted when external space area 2 is accessed 2 program wait states inserted when external space area 2 is accessed 3 program wait states inserted when external space area 2 is accessed (Initial value) Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 W11 0 Bit 2 W10 0 1 1 0 1 Description Program wait not inserted when external space area 1 is accessed 1 program wait state inserted when external space area 1 is accessed 2 program wait states inserted when external space area 1 is accessed 3 program wait states inserted when external space area 1 is accessed (Initial value) Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1. Bit 1 W01 0 Bit 0 W00 0 1 1 0 1 Description Program wait not inserted when external space area 0 is accessed 1 program wait state inserted when external space area 0 is accessed 2 program wait states inserted when external space area 0 is accessed 3 program wait states inserted when external space area 0 is accessed (Initial value) Rev.6.00 Oct.28.2004 page 112 of 1016 REJ09B0138-0600H 6.2.4 Bit Bus Control Register H (BCRH) : 7 ICIS1 6 ICIS0 1 R/W 5 4 3 2 RMTS2 0 R/W 1 RMTS1 0 R/W 0 RMTS0 0 R/W BRSTRM BRSTS1 BRSTS0 0 R/W 1 R/W 0 R/W Initial value : R/W : 1 R/W BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for areas 2 to 5 and area 0. BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset* or in software standby mode. Note: * Manual reset is only supported in the H8S/2357 ZTAT. Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1 0 1 Description Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas (Initial value) Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed . Bit 6 ICIS0 0 1 Description Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles (Initial value) Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface. Bit 5 BRSTRM 0 1 Description Area 0 is basic bus interface Area 0 is burst ROM interface (Initial value) Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 0 1 Description Burst cycle comprises 1 state Burst cycle comprises 2 states (Initial value) Rev.6.00 Oct.28.2004 page 113 of 1016 REJ09B0138-0600H Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 0 1 Description Max. 4 words in burst access Max. 8 words in burst access (Initial value) Bits 2 to 0—RAM Type Select (RMTS2 to RMTS0): These bits select the memory interface for areas 2 to 5 in advanced mode. When DRAM space is selected, the relevant area is designated as DRAM interface. Bit 2 RMTS2 0 Bit 1 RMTS1 0 Bit 0 RMTS0 0 1 1 0 1 1 — — Description Area 5 Normal space Normal space Normal space DRAM space — DRAM space DRAM space Area 4 Area 3 Area 2 Note: When areas selected in DRAM space are all 8-bit space, the PF 2 pin can be used as an I/O port, BREQO , or WAIT. 6.2.5 Bit Bus Control Register L (BCRL) : 7 BRLE 6 BREQOE 0 R/W 5 EAE 1 R/W 4 LCASS 1 R/W 3 DDS 1 R/W 2 — 1 R/W 1 WDBE 0 R/W 0 WAITE 0 R/W Initial value : R/W : 0 R/W BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, the LCAS signal, DMAC single address transfer, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT pin input. BCRL is initialized to H'3C by a power-on reset and in hardware standby mode. It is not initialized by a manual reset* or in software standby mode. Note: * Manual reset is only supported in the H8S/2357 ZTAT. Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release. Bit 7 BRLE 0 1 Description External bus release is disabled. BREQ , BACK , and BREQO can be used as I/O ports. (Initial value) External bus release is enabled. Rev.6.00 Oct.28.2004 page 114 of 1016 REJ09B0138-0600H Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request signal (BREQ ) in the external bus release state, when an internal bus master performs an external space access, or when a refresh request is generated. Bit 6 BREQOE 0 1 Description BREQO output disabled. BREQO can be used as I/O port. BREQO output enabled. (Initial value) Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'01FFFF*2 are to be internal addresses or external addresses. Bit 5 EAE 0 1 Description Addresses H'010000 to H'01FFFF* 2 are in on-chip ROM Addresses H'010000 to H'01FFFF* 2 are external addresses (external expansion mode) or a reserved area * 1 (single-chip mode) (Initial value) Notes: 1. Reserved areas should not be accessed. 2. Addresses H'010000 to H'01FFFF are in the H8S/2357. Addresses H'010000 to H'03FFFF are in the H8S/2398. Bit 4—LCAS Select (LCASS): Write 0 to this bit when using the DRAM interface. LCAS pin used for 2-CAS type DRAM interface LCAS signal. BREQO output and WAIT input cannot be used when LCAS signal is used. Bit 3—DACK Timing Select (DDS): Selects the DMAC single address transfer bus timing for the DRAM interface. Bit 3 DDS 0 Description When DMAC single address transfer is performed in DRAM space, full access is always executed DACK signal goes low from T r or T1 cycle 1 Burst access is possible when DMAC single address transfer is performed in DRAM space DACK signal goes low from T c1 or T2 cycle (Initial value) Bit 2—Reserved: Only 1 should be written to this bit. Bit 1—Write Data Buffer Enable (WDBE): Selects whether or not the write buffer function is used for an external write cycle or DMAC single address cycle. Bit 1 WDBE 0 1 Description Write data buffer function not used Write data buffer function used (Initial value) Rev.6.00 Oct.28.2004 page 115 of 1016 REJ09B0138-0600H Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin. Bit 0 WAITE 0 1 Description Wait input by WAIT pin disabled. WAIT pin can be used as I/O port. Wait input by WAIT pin enabled (Initial value) 6.2.6 Bit Memory Control Register (MCR) : 7 TPC 0 R/W 6 BE 0 R/W 5 RCDM 0 R/W 4 CW2 0 R/W 3 MXC1 0 R/W 2 MXC0 0 R/W 1 RLW1 0 R/W 0 RLW0 0 R/W Initial value : R/W : MCR is an 8-bit readable/writable register that selects the DRAM strobe control method, number of precharge cycles, access mode, address multiplexing shift size, and the number of wait states inserted during refreshing, when areas 2 to 5 are designated as DRAM interface. MCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset* or in software standby mode. Note: * Manual reset is only supported in the H8S/2357 ZTAT. Bit 7—TP Cycle Control (TPC): Selects whether a 1-state or 2-state precharge cycle (TP) is to be used when areas 2 to 5 designated as DRAM space are accessed. Bit 7 TPC 0 1 Description 1-state precharge cycle is inserted 2-state precharge cycle is inserted (Initial value) Bit 6—Burst Access Enable (BE): Selects enabling or disabling of burst access to areas 2 to 5 designated as DRAM space. DRAM space burst access is performed in fast page mode. Bit 6 BE 0 1 Description Burst disabled (always full access) For DRAM space access, access in fast page mode (Initial value) Bit 5—RAS Down Mode (RCDM): When areas 2 to 5 are designated as DRAM space and access to DRAM is interrupted, RCDM selects whether the next DRAM access is waited for with the RAS signal held low (RAS down mode), or the RAS signal is driven high again (RAS up mode). Bit 5 RCDM 0 1 Description DRAM interface: RAS up mode selected DRAM interface: RAS down mode selected (Initial value) Rev.6.00 Oct.28.2004 page 116 of 1016 REJ09B0138-0600H Bit 4—2-CAS Method Select (CW2): Write 1 to this bit when areas 2 to 5 are designated as 8-bit DRAM space, and 0 otherwise. Bit 4 CW2 0 1 Description 16-bit DRAM space selected 8-bit DRAM space selected (Initial value) Bits 3 and 2—Multiplex Shift Count 1 and 0 (MXC1, MXC0): These bits select the size of the shift to the lower half of the row address in row address/column address multiplexing for the DRAM interface. In burst operation on the DRAM interface, these bits also select the row address to be used for comparison. Bit 3 MXC1 0 Bit 2 MXC0 0 Description 8-bit shift (Initial value) • When 8-bit access space is designated: Row address A23 to A 8 used for comparison • When 16-bit access space is designated: Row address A23 to A 9 used for comparison 9-bit shift • When 8-bit access space is designated: Row address A23 to A 9 used for comparison • When 16-bit access space is designated: Row address A23 to A 10 used for comparison 10-bit shift • When 8-bit access space is designated: Row address A23 to A 10 used for comparison • When 16-bit access space is designated: Row address A23 to A 11 used for comparison — 1 1 0 1 Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1, RLW0): These bits select the number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle. This setting is used for all areas designated as DRAM space. Wait input by the WAIT pin is disabled. Bit 1 RLW1 0 1 Bit 0 RLW0 0 1 0 1 Description No wait state inserted 1 wait state inserted 2 wait states inserted 3 wait states inserted (Initial value) Rev.6.00 Oct.28.2004 page 117 of 1016 REJ09B0138-0600H 6.2.7 Bit DRAM Control Register (DRAMCR) : 7 RFSHE 0 R/W 6 RCW 0 R/W 5 RMODE 0 R/W 4 CMF 0 R/W 3 CMIE 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh counter clock, and controls the refresh timer. DRAMCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset* or in software standby mode. Note: * Manual reset is only supported in the H8S/2357 ZTAT. Bit 7—Refresh Control (RFSHE): Selects whether or not refresh control is performed. When refresh control is not performed, the refresh timer can be used as an interval timer. Bit 7 RFSHE 0 1 Description Refresh control is not performed Refresh control is performed (Initial value) Bit 6—RAS-CAS Wait (RCW): Controls wait state insertion in DRAM interface CAS-before-RAS refreshing. Bit 6 RCW 0 1 Description Wait state insertion in CAS-before-RAS refreshing disabled RAS falls in TRr cycle One wait state inserted in CAS-before-RAS refreshing RAS falls in TRc1 cycle (Initial value) Bit 5—Refresh Mode (RMODE): When refresh control is performed (RFSHE = 1), this bit selects whether normal refreshing (CAS-before-RAS refreshing for the DRAM interface) or self-refreshing is performed. Bit 5 RMODE 0 1 Description DRAM interface CAS-before-RAS refreshing used Self-refreshing used (Initial value) Bit 4—Compare Match Flag (CMF): Status flag that indicates a match between the values of RTCNT and RTCOR. When refresh control is performed (RFSHE = 1), 1 should be written to the CMF bit when writing to DRAMCR. Bit 4 CMF 0 Description [Clearing condition] Cleared by reading the CMF flag when CMF = 1, then writing 0 to the CMF flag (Initial value) [Setting condition] Set when RTCNT = RTCOR 1 Rev.6.00 Oct.28.2004 page 118 of 1016 REJ09B0138-0600H Bit 3—Compare Match Interrupt Enable (CMIE): Enables or disables interrupt requests (CMI) by the CMF flag when the CMF flag in DRAMCR is set to 1. When refresh control is performed (RFSHE = 1), the CMIE bit is always cleared to 0. Bit 3 CMIE 0 1 Description Interrupt request (CMI) by CMF flag disabled Interrupt request (CMI) by CMF flag enabled (Initial value) Bits 2 to 0—Refresh Counter Clock Select (CKS2 to CKS0): These bits select the clock to be input to RTCNT from among 7 internal clocks obtained by dividing the system clock (ø). When the input clock is selected with bits CKS2 to CKS0, RTCNT begins counting up. Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Count operation disabled Count uses ø/2 Count uses ø/8 Count uses ø/32 Count uses ø/128 Count uses ø/512 Count uses ø/2048 Count uses ø/4096 (Initial value) 6.2.8 Bit Refresh Timer/Counter (RTCNT) : 7 6 5 4 3 2 1 0 Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits CKS2 to CKS0 in DRAMCR. When RTCNT matches RTCOR (compare match), the CMF flag in DRAMCR is set to 1 and RTCNT is cleared to H'00. If the RFSHE bit in DRAMCR is set to 1 at this time, a refresh cycle is started. Also, if the CMIE bit in DRAMCR is set to 1, a compare match interrupt (CMI) is generated. RTCNT is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset* or in software standby mode. Note: * Manual reset is only supported in the H8S/2357 ZTAT. Rev.6.00 Oct.28.2004 page 119 of 1016 REJ09B0138-0600H 6.2.9 Bit Refresh Time Constant Register (RTCOR) : 7 6 5 4 3 2 1 0 Initial value : R/W : 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W RTCOR is an 8-bit readable/writable register that sets the period for compare match operations with RTCNT. The values of RTCOR and RTCNT are constantly compared, and if they match, the CMF flag in DRAMCR is set to 1 and RTCNT is cleared to H'00. RTCOR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset* or in software standby mode. Note: * Manual reset is only supported in the H8S/2357 ZTAT. Rev.6.00 Oct.28.2004 page 120 of 1016 REJ09B0138-0600H 6.3 6.3.1 Overview of Bus Control Area Partitioning In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. Figure 6-2 shows an outline of the memory map. Chip select signals (CS0 to CS7) can be output for each area. H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) H'FFFFFF Advanced mode Figure 6-2 Overview of Area Partitioning Rev.6.00 Oct.28.2004 page 121 of 1016 REJ09B0138-0600H 6.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is always set. Number of Access States: Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a 3-state access space. With the DRAM interface and burst ROM interface, the number of access states may be determined without regard to ASTCR. When 2-state access space is designated, wait insertion is disabled. Number of Program Wait States: When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected. Table 6-3 shows the bus specifications for each basic bus interface area. Table 6-3 Bus Specifications for Each Area (Basic Bus Interface) WCRH, WCRL ABWCR ABWn 0 ASTCR ASTn 0 1 Wn1 — 0 Wn0 — 0 1 1 0 1 1 0 1 — 0 — 0 1 1 0 1 8 2 3 Bus Specifications (Basic Bus Interface) Bus Width 16 Program Wait Access States States 2 3 0 0 1 2 3 0 0 1 2 3 Rev.6.00 Oct.28.2004 page 122 of 1016 REJ09B0138-0600H 6.3.3 Memory Interfaces The H8S/2357 Group memory interfaces comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can be selected independently for each area. An area for which the basic bus interface is designated functions as normal space, an area for which the DRAM interface is designated functions as DRAM space, and an area for which the burst ROM interface is designated functions as burst ROM space. 6.3.4 Advanced Mode The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (section 6.4, Basic Bus Interface, section 6.5, DRAM Interface, and section 6.7, Burst ROM Interface) should be referred to for further details. Area 0: Area 0 includes on-chip ROM*, and in ROM-disabled expansion mode, all of area 0 is external space. In ROMenabled expansion mode, the space excluding on-chip ROM* is external space. When area 0 external space is accessed, the CS0 signal can be output. Either basic bus interface or burst ROM interface can be selected for area 0. Note: * Applies to the on-chip ROM version only. Areas 1 and 6: In external expansion mode, all of areas 1 and 6 is external space. When area 1 and 6 external space is accessed, the CS1 and CS6 pin signals respectively can be output. Only the basic bus interface can be used for areas 1 and 6. Areas 2 to 5: In external expansion mode, all of areas 2 to 5 is external space. When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output. Basic bus interface or DRAM interface can be selected for areas 2 to 5. With the DRAM interface, signals CS2 to CS5 are used as RAS signals. Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space . When area 7 external space is accessed, the CS7 signal can be output. Only the basic bus interface can be used for the area 7 memory interface. Rev.6.00 Oct.28.2004 page 123 of 1016 REJ09B0138-0600H 6.3.5 Chip Select Signals The H8S/2357 Group can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. Figure 6-3 shows an example of CSn (n = 0 to 7) output timing. Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR) for the port corresponding to the particular CSn pin. In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset. Pins CS1 to CS7 are placed in the input state after a power-on reset, and so the corresponding DDR should be set to 1 when outputting signals CS1 to CS7. In the ROM-enabled expansion mode, pins CS0 to CS7 are all placed in the input state after a power-on reset, and so the corresponding DDR bits should be set to 1 when outputting signals CS0 to CS7. For details, see section 9, I/O Ports. When areas 2 to 5 are designated as DRAM space, outputs CS2 to CS5 are used as RAS signals. Bus cycle T1 ø T2 T3 Address bus Area n external address CSn Figure 6-3 CSn Signal Output Timing (n = 0 to 7) Rev.6.00 Oct.28.2004 page 124 of 1016 REJ09B0138-0600H 6.4 6.4.1 Basic Bus Interface Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6-3). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D 7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-Bit Access Space: Figure 6-4 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses. Upper data bus Lower data bus D15 D8 D7 D0 Byte size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Word size Figure 6-4 Access Sizes and Data Alignment Control (8-Bit Access Space) Rev.6.00 Oct.28.2004 page 125 of 1016 REJ09B0138-0600H 16-Bit Access Space: Figure 6-5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Upper data bus Lower data bus D15 D8 D7 D0 Byte size Byte size Word size Longword size 1st bus cycle 2nd bus cycle • Even address • Odd address Figure 6-5 Access Sizes and Data Alignment Control (16-Bit Access Space) Rev.6.00 Oct.28.2004 page 126 of 1016 REJ09B0138-0600H 6.4.3 Valid Strobes Table 6-4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6-4 Data Buses Used and Valid Strobes Area 8-bit access space Access Read/ Size Write Byte Read Write Read Address — — Even Odd Write Even Odd Word Read Write Legend: Hi-Z: High impedance Invalid: Input state; input value is ignored. — — HWR LWR RD Valid Strobe RD HWR RD Valid Invalid Valid Hi-Z Valid Upper Data Bus (D15 to D8) Valid Lower data bus (D7 to D0) Invalid Hi-Z Invalid Valid Hi-Z Valid Valid Valid 16-bit access Byte space HWR, LWR Valid Rev.6.00 Oct.28.2004 page 127 of 1016 REJ09B0138-0600H 6.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 6-6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted. Bus cycle T1 ø T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Note: n = 0 to 7 Figure 6-6 Bus Timing for 8-Bit 2-State Access Space Rev.6.00 Oct.28.2004 page 128 of 1016 REJ09B0138-0600H 8-Bit 3-State Access Space: Figure 6-7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle T1 ø T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid High impedance D7 to D0 Note: n = 0 to 7 Figure 6-7 Bus Timing for 8-Bit 3-State Access Space Rev.6.00 Oct.28.2004 page 129 of 1016 REJ09B0138-0600H 16-Bit 2-State Access Space: Figures 6-8 to 6-10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted. Bus cycle T1 ø T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Note: n = 0 to 7 Figure 6-8 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access) Rev.6.00 Oct.28.2004 page 130 of 1016 REJ09B0138-0600H Bus cycle T1 ø T2 Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Valid Note: n = 0 to 7 Figure 6-9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) Rev.6.00 Oct.28.2004 page 131 of 1016 REJ09B0138-0600H Bus cycle T1 ø T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 7 Figure 6-10 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) Rev.6.00 Oct.28.2004 page 132 of 1016 REJ09B0138-0600H 16-Bit 3-State Access Space: Figures 6-11 to 6-13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted. Bus cycle T1 ø T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid High impedance D7 to D0 Note: n = 0 to 7 Figure 6-11 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access) Rev.6.00 Oct.28.2004 page 133 of 1016 REJ09B0138-0600H Bus cycle T1 ø T2 T3 Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Note: n = 0 to 7 Valid Figure 6-12 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) Rev.6.00 Oct.28.2004 page 134 of 1016 REJ09B0138-0600H Bus cycle T1 ø T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Note: n = 0 to 7 Valid Figure 6-13 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) Rev.6.00 Oct.28.2004 page 135 of 1016 REJ09B0138-0600H 6.4.5 Wait Control When accessing external space, the H8S/2357 Group can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings of WCRH and WCRL. Pin Wait Insertion: Setting the WAITE bit in BCRL to 1 enables wait insertion by means of the WAIT pin. Program wait insertion is first carried out according to the settings in WCRH and WCRL. Then , if the WAIT pin is low at the falling edge of ø in the last T2 or Tw state, a Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. This is useful when inserting four or more Tw states, or when changing the number of Tw states for different external devices. The WAITE bit setting applies to all areas. Rev.6.00 Oct.28.2004 page 136 of 1016 REJ09B0138-0600H Figure 6-14 shows an example of wait state insertion timing. By program wait T1 ø T2 Tw By WAIT pin Tw Tw T3 WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Note: indicates the timing of WAIT pin sampling. Figure 6-14 Example of Wait State Insertion Timing The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT input disabled. When a manual reset* is performed, the contents of bus controller registers are retained, and the wait control settings remain the same as before the reset. Note: * Manual reset is only supported in the H8S/2357 ZTAT. Rev.6.00 Oct.28.2004 page 137 of 1016 REJ09B0138-0600H 6.5 6.5.1 DRAM Interface Overview When the H8S/2357 Group is in advanced mode, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. With the DRAM interface, DRAM can be directly connected to the H8S/2357 Group. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in BCRH. Burst operation is also possible, using fast page mode. 6.5.2 Setting DRAM Space Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in BCRH. The relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6-5. Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), and four areas (areas 2 to 5). Table 6-5 Settings of Bits RMTS2 to RMTS0 and Corresponding DRAM Spaces RMTS2 0 RMTS1 0 1 RMTS0 1 0 1 Area 5 Normal space Normal space DRAM space DRAM space Area 4 Area 3 Area 2 DRAM space 6.5.3 Address Multiplexing With DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC1 and MXC0 in MCR. Table 6-6 shows the relation between the settings of MXC1 and MXC0 and the shift size. Table 6-6 Address Multiplexing Settings by Bits MXC1 and MXC0 Shift MXC1 MXC0 Size Row 0 address 1 0 1 0 1 Column — address — 8 bits 9 bits 10 bits MCR Address Pins A23 to A 13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 to A 13 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A23 to A 13 A12 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A23 to A 13 A12 A11 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 ————————————— Setting — prohibited — A23 to A 13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 6.5.4 Data Bus If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM space. In 16-bit DRAM space, × 16-bit configuration DRAM can be connected directly. In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM space both the upper and lower halves of the data bus, D15 to D0, are enabled. Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2, Data Size and Data Alignment. Rev.6.00 Oct.28.2004 page 138 of 1016 REJ09B0138-0600H 6.5.5 Pins Used for DRAM Interface Table 6-7 shows the pins used for DRAM interfacing and their functions. Table 6-7 DRAM Interface Pins With DRAM Setting WE Pin HWR Name Write enable I/O Function Output When 2-CAS system is set, write enable for DRAM space access. LCAS CS2 LCAS RAS2 Lower column address strobe Output Lower column address strobe for 16-bit DRAM space access Row address strobe 2 Output Row address strobe when area 2 is designated as DRAM space. Output Row address strobe when area 3 is designated as DRAM space. Output Row address strobe when area 4 is designated as DRAM space. Output Row address strobe when area 5 is designated as DRAM space. CS3 RAS3 Row address strobe 3 CS4 RAS4 Row address strobe 4 CS5 RAS5 Row address strobe 5 CAS WAIT A12 to A 0 D15 to D0 UCAS WAIT A12 to A 0 D15 to D0 Upper column address strobe Output Upper column address strobe for DRAM space access Wait Address pins Data pins Input Wait request signal Output Row address/column address multiplexed output I/O Data input/output pins Rev.6.00 Oct.28.2004 page 139 of 1016 REJ09B0138-0600H 6.5.6 Basic Timing Figure 6-15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4 states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or disabling of wait insertion, and do not affect the number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states cannot be inserted in the DRAM access cycle. The 4 states of the basic timing consist of one T p (precharge cycle) state, one Tr (row address output cycle), and two Tc (column address output cycle) states, T c1 and T c2 . Tp Tr Tc1 Tc2 ø A23 to A0 Row Column CSn, (RAS) CAS, LCAS HWR, (WE) Read D15 to D0 HWR, (WE) Write D15 to D0 Note: n = 2 to 5 Figure 6-15 Basic Access Timing Rev.6.00 Oct.28.2004 page 140 of 1016 REJ09B0138-0600H 6.5.7 Precharge State Control When DRAM is accessed, RAS precharging time must be secured. With the H8S/2357 Series, one Tp state is always inserted when DRAM space is accessed. This can be changed to two Tp states by setting the TPC bit in MCR to 1. Set the appropriate number of T p cycles according to the DRAM connected and the operating frequency of the H8S/2357 Group. Figure 6-16 shows the timing when two Tp states are inserted. When the TPC bit is set to 1, two T p states are also used for refresh cycles. Tp1 Tp2 Tr Tc1 Tc2 ø A23 to A0 Row Column CSn, (RAS) CAS, LCAS HWR, (WE) Read D15 to D0 HWR, (WE) Write D15 to D0 Note: n = 2 to 5 Figure 6-16 Timing with Two Precharge States 6.5.8 Wait Control There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from 0 to 3 wait states can be inserted automatically between the Tc1 state and Tc2 state, according to the settings of WCRH and WCRL. Pin Wait Insertion: When the WAITE bit in BCRH is set to 1, wait input by means of the WAIT pin is enabled regardless of the setting of the AST bit in ASTCR. When DRAM space is accessed in this state, a program wait is first inserted. If the WAIT pin is low at the falling edge of ø in the last Tc1 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. Rev.6.00 Oct.28.2004 page 141 of 1016 REJ09B0138-0600H Figure 6-17 shows an example of wait state insertion timing. By program wait Tp ø Tr Tc1 Tw By WAIT pin Tw Tc2 WAIT Address bus CSn, (RAS) CAS Read Data bus Read data CAS Write Data bus Write data Notes: indicates the timing of WAIT pin sampling. n = 2 to 5 Figure 6-17 Example of Wait State Insertion Timing (CW2 = 1, 8-Bit Area Setting for Entire Space) Rev.6.00 Oct.28.2004 page 142 of 1016 REJ09B0138-0600H 6.5.9 Byte Access Control When DRAM with a ×16 configuration is connected, the 2-CAS system can be used for the control signals required for byte access. When the CW2 bit is cleared to 0 in MCR, the 2-CAS system is selected. Figure 6-18 shows the control timing in the 2CAS system, and figure 6-19 shows an example 2-CAS system DRAM connection. When only DRAM with a ×8 configuration is connected, set the CW2 bit to 1 in MCR. Tp Tr Tc1 Tc2 ø A23 to A0 Row Column CSn, (RAS) CAS Byte control LCAS HWR, (WE) Note: n = 2 to 5 Figure 6-18 2-CAS System Control Timing (Upper Byte Write Access) 2-CAS type 4-Mbit DRAM 256-kbyte x 16-bit configuration 9-bit column address RAS UCAS LCAS WE A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 OE Low address input: A8 to A0 Column address input: A8 to A0 H8S/2357 Group (Address shift size set to 9 bits) CS, (RAS) CAS LCAS HWR, (WE) A9 A8 A7 A6 A5 A4 A3 A2 A1 D15 to D0 Figure 6-19 Example of 2-CAS System Connection Rev.6.00 Oct.28.2004 page 143 of 1016 REJ09B0138-0600H 6.5.10 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number of consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit in MCR to 1. Burst Access (Fast Page Mode) Operation Timing: Figure 6-20 shows the operation timing for burst access. When there are consecutive access cycles for DRAM space, the CAS signal and column address output cycles (two states) continue as long as the row address is the same for consecutive access cycles. The row address used for the comparison is set with bits MXC1 and MXC0 in MCR. Tp ø A23 to A0 CSn, (RAS) CAS, LCAS HWR, (WE) Read D15 to D0 HWR, (WE) Write D15 to D0 Note: n = 2 to 5 Tr Tc1 Tc2 Tc1 Tc2 Row Column1 Column2 Figure 6-20 Operation Timing in Fast Page Mode The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion method and timing are the same as for full access. For details, see section 6.5.8, Wait Control. Rev.6.00 Oct.28.2004 page 144 of 1016 REJ09B0138-0600H RAS Down Mode and RAS Up Mode: Even when burst operation is selected, it may happen that access to DRAM space is not continuous, but is interrupted by access to another space. In this case, if the RAS signal is held low during the access to the other space, burst operation can be resumed when the same row address in DRAM space is accessed again. • RAS down mode To select RAS down mode, set the RCDM bit in MCR to 1. If access to DRAM space is interrupted and another space is accessed, the RAS signal is held low during the access to the other space, and burst access is performed if the row address of the next DRAM space access is the same as the row address of the previous DRAM space access. Figure 621 shows an example of the timing in RAS down mode. Note, however, that the RAS signal will go high if a refresh operation interrupts RAS down mode. External space access T1 T2 DRAM access Tp ø Tr Tc1 Tc2 DRAM access Tc1 Tc2 A23 to A0 CSn, (RAS) CAS, LCAS D15 to D0 Note: n = 2 to 5 Figure 6-21 Example of Operation Timing in RAS Down Mode Rev.6.00 Oct.28.2004 page 145 of 1016 REJ09B0138-0600H • RAS up mode To select RAS up mode, clear the RCDM bit in MCR to 0. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 6-22 shows an example of the timing in RAS up mode. In the case of burst ROM space access, the RAS signal is not restored to the high level. External space access T1 T2 DRAM access Tp ø Tr Tc1 Tc2 DRAM access Tc1 Tc2 A23 to A0 CSn, (RAS) CAS, LCAS D15 to D0 Note: n = 2 to 5 Figure 6-22 Example of Operation Timing in RAS Up Mode Rev.6.00 Oct.28.2004 page 146 of 1016 REJ09B0138-0600H 6.5.11 Refresh Control The H8S/2357 Group is provided with a DRAM refresh control function. Either of two refreshing methods can be selected: CAS-before-RAS (CBR) refreshing, or self-refreshing. CAS-before-RAS (CBR) Refreshing: To select CBR refreshing, set the RFSHE bit in DRAMCR to 1, and clear the RMODE bit to 0. With CBR refreshing, RTCNT counts up using the input clock selected by bits CKS2 to CKS0 in DRAMCR, and when the count matches the value set in RTCOR (compare match), refresh control is performed. At the same time, RTCNT is reset and starts counting again from H'00. Refreshing is thus repeated at fixed intervals determined by RTCOR and bits CKS2 to CKS0. Set a value in RTCOR and bits CKS2 to CKS0 that will meet the refreshing interval specification for the DRAM used. When bits CKS2 to CKS0 are set, RTCNT starts counting up. RTCNT and RTCOR settings should therefore be completed before setting bits CKS2 to CKS0. Do not clear the CMF flag when refresh control is being performed (RFSHE = 1). RTCNT operation is shown in figure 6-23, compare match timing in figure 6-24, and CBR refresh timings in figure 6-25. RTCNT RTCOR H'00 Refresh request Figure 6-23 RTCNT Operation ø RTCNT N H'00 RTCOR N Refresh request signal and CMF bit setting signal Figure 6-24 Compare Match Timing Rev.6.00 Oct.28.2004 page 147 of 1016 REJ09B0138-0600H TRp TRr TRc1 TRc2 ø CS, (RAS) CAS, LCAS Note: n = 2 to 5 Figure 6-25 CBR Refresh Timing When the RCW bit is set to 1, RAS signal output is delayed by one cycle. The width of the RAS signal should be adjusted with bits RLW1 and RLW0. These bits are only enabled in refresh operations. Figure 6-26 shows the timing when the RCW bit is set to 1. TRp TRr TRc1 TRw TRc2 ø CSn, (RAS) CAS, LCAS Note: n = 2 to 5 Figure 6-26 CBR Refresh Timing (When RCW = 1, RLW1 = 0, RLW0 = 1) Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. To select self-refreshing, set the RFSHE bit and RMODE bit in DRAMCR to 1. Then, when a SLEEP instruction is executed to enter software standby mode, the CAS and RAS signals are output and DRAM enters self-refresh mode, as shown in figure 6-27. When software standby mode is exited, the RMODE bit is cleared to 0 and self-refresh mode is cleared. When switching to software standby mode, if there is a CBR refresh request, CBR refreshing is executed before selfrefresh mode is entered. Rev.6.00 Oct.28.2004 page 148 of 1016 REJ09B0138-0600H TRp ø TRcr Software standby TRc3 CSn, (RAS) CAS, LCAS HWR, (WE) High Note: n = 2 to 5 Figure 6-27 Self-Refresh Timing (When CW2 = 1, or CW2 = 0 and LCASS = 0) 6.6 DMAC Single Address Mode and DRAM Interface When burst mode is selected with the DRAM interface, the DACK output timing can be selected with the DDS bit. When DRAM space is accessed in DMAC single address mode at the same time, whether or not burst access is to be performed is selected. 6.6.1 When DDS = 1 Burst access is performed by determining the address only, irrespective of the bus master. The DACK output goes low from the TC1 state in the case of the DRAM interface. Figure 6-28 shows the DACK output timing for the DRAM interface when DDS = 1. Tp ø A23 to A0 CSn, (RAS) CAS, (UCAS), LCAS, (LCAS) HWR, (WE) Read D15 to D0 HWR, (WE) Write D15 to D0 DACK Row Column Tr Tc1 Tc2 Note: n = 2 to 5 Figure 6-28 DACK Output Timing when DDS = 1 (Example of DRAM Access) Rev.6.00 Oct.28.2004 page 149 of 1016 REJ09B0138-0600H 6.6.2 When DDS = 0 When DRAM space is accessed in DMAC single address mode, full access (normal access) is always performed. The DACK output goes low from the Tr state in the case of the DRAM interface. In modes other than DMAC single address mode, burst access can be used when accessing DRAM space. Figure 6-29 shows the DACK output timing for the DRAM interface when DDS = 0. Tp ø A23 to A0 CSn, (RAS) CAS, (UCAS), LCAS, (LCAS) HWR, (WE) Read D15 to D0 HWR, (WE) Write D15 to D0 DACK Row Column Tr Tc1 Tc2 Note: n = 2 to 5 Figure 6-29 DACK Output Timing when DDS = 0 (Example of DRAM Access) 6.7 6.7.1 Burst ROM Interface Overview With the H8S/2357 Group, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only. One or two states can be selected for burst access. Rev.6.00 Oct.28.2004 page 150 of 1016 REJ09B0138-0600H 6.7.2 Basic Timing The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state insertion is possible. One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst ROM space, it becomes 16-bit access space regardless of the setting of the ABW0 bit in ABWCR. When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when the BRSTS0 bit is set to 1, burst access of up to 8 words is performed. The basic access timing for burst ROM space is shown in figures 6-30 (a) and (b). The timing shown in figure 6-30 (a) is for the case where the AST0 and BRSTS1 bits are both set to 1, and that in figure 6-30 (b) is for the case where both these bits are cleared to 0. Full access T1 ø T2 T3 T1 Burst access T2 T1 T2 Address bus Only lower address changed CS0 AS RD Data bus Read data Read data Read data Figure 6-30 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) Rev.6.00 Oct.28.2004 page 151 of 1016 REJ09B0138-0600H Full access T1 T2 Burst access T1 T1 ø Address bus Only lower address changed CS0 AS RD Data bus Read data Read data Read data Figure 6-30 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 6.7.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait Control. Wait states cannot be inserted in a burst cycle. Rev.6.00 Oct.28.2004 page 152 of 1016 REJ09B0138-0600H 6.8 6.8.1 Idle Cycle Operation When the H8S/2357 Group accesses external space, it can insert a 1-state idle cycle (TI) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on. (1) Consecutive Reads between Different Areas If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read cycle. This is enabled in advanced mode. Figure 6-31 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 ø Address bus CS (area A) CS (area B) RD Data bus T2 T3 Bus cycle B T1 T2 ø Address bus CS (area A) Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 , CS (area B) RD Data bus Data collision (b) Idle cycle inserted (Initial value ICIS1 = 1) Long output floating time (a) Idle cycle not inserted (ICIS1 = 0) Figure 6-31 Example of Idle Cycle Operation (1) Rev.6.00 Oct.28.2004 page 153 of 1016 REJ09B0138-0600H (2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 6-32 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 ø Address bus CS (area A) CS (area B) RD HWR Data bus T2 T3 Bus cycle B T1 T2 ø Address bus CS (area A) Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Long output floating time , CS (area B) RD HWR Data bus Data collision (b) Idle cycle inserted (Initial value ICIS0 = 1) (a) Idle cycle not inserted (ICIS0 = 0) Figure 6-32 Example of Idle Cycle Operation (2) Rev.6.00 Oct.28.2004 page 154 of 1016 REJ09B0138-0600H (3) Relationship between Chip Select (CS) Signal and Read ( RD) Signal Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 633. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the initial state after reset release, idle cycle insertion (b) is set. Bus cycle A T1 ø Address bus CS (area A) CS (area B) RD T2 T3 Bus cycle B T1 T2 ø Address bus CS (area A) CS (area B) RD Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Possibility of overlap between CS (area B) and RD (a) Idle cycle not inserted (ICIS1 = 0) (b) Idle cycle inserted (Initial value ICIS1 = 1) Figure 6-33 Relationship between Chip Select (CS) and Read (RD) 6.8.2 Usage Notes When DRAM space is accessed, the ICIS0 and ICIS1 bit settings are disabled. In the case of consecutive reads between different areas, for example, if the second access is a DRAM access, only a T p cycle is inserted, and a TI cycle is not. The timing in this case is shown in figure 6-34. However, in burst access in RAS down mode these settings are enabled, and an idle cycle is inserted. The timing in this case is shown in figures 6-35 (a) and (b). Rev.6.00 Oct.28.2004 page 155 of 1016 REJ09B0138-0600H External read T1 ø Address bus RD Data bus T2 T3 Tp DRAM space read Tr Tc1 Tc2 Figure 6-34 Example of DRAM Access after External Read DRAM space read Tp EXTAL Address RD RAS CAS, LCAS Data bus Tr Tc1 Tc2 TI External read T1 T2 T3 DRAM space read TcI Tc1 Tc2 Idle cycle Figure 6-35 (a) Example of Idle Cycle Operation in RAS Down Mode (ICIS1 = 1) DRAM space read Tp EXTAL Address RD HWR RAS CAS, LCAS Data bus Tr Tc1 Tc2 TI External read T1 T2 T3 DRAM space write TcI Tc1 Tc2 Idle cycle Figure 6-35 (b) Example of Idle Cycle Operation in RAS Down Mode (ICIS0 = 1) Rev.6.00 Oct.28.2004 page 156 of 1016 REJ09B0138-0600H 6.8.3 Pin States in Idle Cycle Table 6-8 shows pin states in an idle cycle. Table 6-8 Pin States in Idle Cycle Pins A23 to A 0 D15 to D0 CSn * CAS AS RD HWR LWR DACKm* 3 2 Pin State Contents of next bus cycle High impedance High * 1 High High High High High High Notes: 1. Remains low in DRAM space RAS down mode or a refresh cycle. 2. n = 0 to 7 3. m = 0, 1 Rev.6.00 Oct.28.2004 page 157 of 1016 REJ09B0138-0600H 6.9 Write Data Buffer Function The H8S/2357 Group has a write data buffer function in the external data bus. Using the write data buffer function enables external writes and DMA single address mode transfers to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit in BCRL to 1. Figure 6-36 shows an example of the timing when the write data buffer function is used. When this function is used, if an external write or DMA single address mode transfer continues for 2 states or longer, and there is an internal access next, only an external write is executed in the first state, but from the next state onward an internal access (on-chip memory or internal I/O register read/write) is executed in parallel with the external write rather than waiting until it ends. On-chip memory read Internal I/O register read External write cycle T1 T2 TW TW T3 Internal address bus Internal memory Internal read signal Internal I/O register address A23 to A0 External address External space write CSn HWR, LWR D15 to D0 Note : n = 0 to 7 Figure 6-36 Example of Timing when Write Data Buffer Function is Used Rev.6.00 Oct.28.2004 page 158 of 1016 REJ09B0138-0600H 6.10 6.10.1 Bus Release Overview The H8S/2357 Group can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. If an internal bus master wants to make an external access in the external bus released state, or if a refresh request is generated, it can issue a bus request off-chip. 6.10.2 Operation In external expansion mode, the bus can be released to an external device by setting the BRLE bit in BCRL to 1. Driving the BREQ pin low issues an external bus request to the H8S/2357 Group. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus-released state. In the external bus released state, an internal bus master can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request from the external bus master to be dropped. Even if a refresh request is generated in the external bus released state, refresh control is deferred until the external bus master drops the bus request. If the BREQOE bit in BCRL is set to 1, when an internal bus master wants to make an external access in the external bus released state, or when a refresh request is generated, the BREQO pin is driven low and a request can be made off-chip to drop the bus request. When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the external bus released state is terminated. If an external bus release request and external access occur simultaneously, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low) If a refresh request and external bus release request occur simultaneously, the order of priority is as follows: (High) Refresh > External bus release (Low) As a refresh and an external access by an internal bus master can be executed simultaneously, there is no relative order of priority for these two operations. Rev.6.00 Oct.28.2004 page 159 of 1016 REJ09B0138-0600H 6.10.3 Pin States in External Bus Released State Table 6-9 shows pin states in the external bus released state. Table 6-9 Pin States in Bus Released State Pins A23 to A 0 D15 to D0 CSn * CAS AS RD HWR LWR DACKm* Notes : 1. n = 0 to 7 2. m = 0, 1 2 1 Pin State High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High Rev.6.00 Oct.28.2004 page 160 of 1016 REJ09B0138-0600H 6.10.4 Transition Timing Figure 6-37 shows the timing for transition to the bus-released state. CPU cycle CPU cycle T0 ø T1 T2 External bus released state High impedance Address bus Address High impedance Data bus High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK BREQO * Minimum 1 state [1] [2] [3] [4] [5] [6] [1] [2] [3] [4] [5] [6] Low level of BREQ pin is sampled at rise of T2 state. BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master. BREQ pin state is still sampled in external bus released state. High level of BREQ pin is sampled. BACK pin is driven high, ending bus release cycle. BREQO signal goes high 1.5 clocks after BACK signal goes high. Note: * Output only when BREQOE is set to 1. Figure 6-37 Bus-Released State Transition Timing 6.10.5 Usage Note When MSTPCR is set to H'FFFF or H'EFFF and a transition is made to sleep mode, the external bus release function halts. Therefore, MSTPCR should not be set to H'FFFF or H'EFFF if the external bus release function is to be used in sleep mode. Rev.6.00 Oct.28.2004 page 161 of 1016 REJ09B0138-0600H 6.11 6.11.1 Bus Arbitration Overview The H8S/2357 Group has a bus arbiter that arbitrates bus master operations. There are three bus masters, the CPU, DTC, and DMAC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. 6.11.2 Operation The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) DMAC > DTC > CPU (Low) An internal bus access by an internal bus master, external bus release, and refreshing, can be executed in parallel. In the event of simultaneous external bus release request, refresh request, and internal bus master external access request generation, the order of priority is as follows: (High) Refresh > External bus release (Low) (High) External bus release > Internal bus master external access (Low) As a refresh and an external access by an internal bus master can be executed simultaneously, there is no relative order of priority for these two operations. Rev.6.00 Oct.28.2004 page 162 of 1016 REJ09B0138-0600H 6.11.3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC or DMAC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: • The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. See Appendix A.5, Bus States during Instruction Execution, for timings at which the bus is not transferred. • If the CPU is in sleep mode, it transfers the bus immediately. DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). DMAC: The DMAC sends the bus arbiter a request for the bus when an activation request is generated. In the case of an external request in short address mode or normal mode, and in cycle steal mode, the DMAC releases the bus after a single transfer. In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after completion of a transfer. 6.11.4 External Bus Release Usage Note External bus release can be performed on completion of an external bus cycle. The RD signal, DRAM interface RAS and CAS signals remain low until the end of the external bus cycle. Therefore, when external bus release is performed, the RD, RAS , and CAS signals may change from the low level to the high-impedance state. Rev.6.00 Oct.28.2004 page 163 of 1016 REJ09B0138-0600H 6.12 Resets and the Bus Controller In a power-on reset, the H8S/2357 Group, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. In a manual reset*, the bus controller’s registers and internal state are maintained, and an executing external bus cycle is completed. In this case, WAIT input is ignored. Also, since the DMAC is initialized by a manual reset*, DACK and TEND output is disabled and these pins become I/O ports controlled by DDR and DR. Note: * Manual reset is only supported in the H8S/2357 ZTAT. Rev.6.00 Oct.28.2004 page 164 of 1016 REJ09B0138-0600H Section 7 DMA Controller 7.1 Overview The H8S/2357 Group has a on-chip DMA controller (DMAC) which can carry out data transfer on up to 4 channels. 7.1.1 Features The features of the DMAC are listed below. • Choice of short address mode or full address mode Short address mode  Maximum of 4 channels can be used  Choice of dual address mode or single address mode  In dual address mode, one of the two addresses, transfer source and transfer destination, is specified as 24 bits and the other as 16 bits  In single address mode, transfer source or transfer destination address only is specified as 24 bits  In single address mode, transfer can be performed in one bus cycle  Choice of sequential mode, idle mode, or repeat mode for dual address mode and single address mode Full address mode  Maximum of 2 channels can be used  Transfer source and transfer destination address specified as 24 bits  Choice of normal mode or block transfer mode • 16-Mbyte address space can be specified directly • Byte or word can be set as the transfer unit • Activation sources: internal interrupt, external request, auto-request (depending on transfer mode)  Six 16-bit timer-pulse unit (TPU) compare match/input capture interrupts  Serial communication interface (SCI0, SCI1) transmission data empty interrupt, reception data full interrupt  A/D converter conversion end interrupt  External request  Auto-request • Module stop mode can be set  The initial setting enables DMAC registers to be accessed. DMAC operation is halted by setting module stop mode Rev.6.00 Oct.28.2004 page 165 of 1016 REJ09B0138-0600H 7.1.2 Block Diagram A block diagram of the DMAC is shown in figure 7-1. Internal address bus Internal interrupts TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A TXI0 RXI0 TXI1 RXI1 ADI External pins DREQ0 DREQ1 TEND0 TEND1 DACK0 DACK1 Interrupt signals DEND0A DEND0B DEND1A DEND1B Address buffer Processor Channel 1B Channel 1A Channel 0B Channel 0A MAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B Module data bus IOAR0A Control logic DMAWER DMATCR DMACR0A DMACR0B DMACR1A DMACR1B DMABCR Data buffer Channel 1 Internal data bus Legend: DMAWER: DMATCR: DMABCR: DMACR: MAR: IOAR: ETCR: DMA write enable register DMA terminal control register DMA band control register (for all channels) DMA control register Memory address register I/O address register Executive transfer counter register Figure 7-1 Block Diagram of DMAC Rev.6.00 Oct.28.2004 page 166 of 1016 REJ09B0138-0600H Channel 0 7.1.3 Overview of Functions Tables 7-1 (1) and (2) summarize DMAC functions in short address mode and full address mode, respectively. Table 7-1 (1) Overview of DMAC Functions (Short Address Mode) Address Register Bit Length Transfer Mode Dual address mode • Sequential mode  1-byte or 1-word transfer executed for one transfer request  Memory address incremented/decremented by 1 or 2  1 to 65,536 transfers • Idle mode • Transfer Source • TPU channel 0 to 5 compare match/input capture A interrupts SCI transmission data empty interrupt SCI reception data full interrupt A/D converter conversion end interrupt External request Source 24/16 Destination 16/24 •  1-byte or 1-word transfer • executed for one transfer request  Memory address fixed  1 to 65,536 transfers • Repeat mode  1-byte or 1-word transfer executed for one transfer request  Memory address incremented/ decremented by 1 or 2  After specified number of transfers (1 to 256), initial state is restored and operation continues Single address mode • • • 1-byte or 1-word transfer executed for one transfer request Transfer in 1 bus cycle using DACK pin in place of address specifying I/O Specifiable for sequential, idle, and repeat modes • • External request 24/ DACK DACK/24 Rev.6.00 Oct.28.2004 page 167 of 1016 REJ09B0138-0600H Table 7-1 (2) Overview of DMAC Functions (Full Address Mode) Address Register Bit Length Transfer Mode • Normal mode Auto-request  Transfer request retained internally  Transfers continue for the specified number of times (1 to 65,536)  Choice of burst or cycle steal transfer External request  1-byte or 1-word transfer executed for one transfer request  1 to 65,536 transfers • Block transfer mode  Specified block size transfer executed for one transfer request  1 to 65,536 transfers  Either source or destination specifiable as block area  Block size: 1 to 256 bytes or words Transfer Source • Auto-request Source 24 Destination 24 • External request • TPU channel 0 to 5 compare match/input capture A interrupts SCI transmission data empty interrupt SCI reception data full interrupt External request A/D converter conversion end interrupt 24 24 • • • • Rev.6.00 Oct.28.2004 page 168 of 1016 REJ09B0138-0600H 7.1.4 Pin Configuration Table 7-2 summarizes the DMAC pins. In short address mode, external request transfer, single address transfer, and transfer end output are not performed for channel A. The DMA transfer acknowledge function is used in channel B single address mode in short address mode. When the DREQ pin is used, do not designate the corresponding port for output. With regard to the DACK pins, setting single address transfer automatically sets the corresponding port to output, functioning as a DACK pin. With regard to the TEND pins, whether or not the corresponding port is used as a TEND pin can be specified by means of a register setting. Table 7-2 DMAC Pins Channel 0 Pin Name DMA request 0 DMA transfer acknowledge 0 DMA transfer end 0 1 DMA request 1 DMA transfer acknowledge 1 DMA transfer end 1 Symbol DREQ0 DACK0 TEND0 DREQ1 DACK1 TEND1 I/O Input Output Output Input Output Output Function DMAC channel 0 external request DMAC channel 0 single address transfer acknowledge DMAC channel 0 transfer end DMAC channel 1 external request DMAC channel 1 single address transfer acknowledge DMAC channel 1 transfer end Rev.6.00 Oct.28.2004 page 169 of 1016 REJ09B0138-0600H 7.1.5 Register Configuration Table 7-3 summarizes the DMAC registers. Table 7-3 DMAC Registers Channel Name 0 Memory address register 0A I/O address register 0A Transfer count register 0A Memory address register 0B I/O address register 0B Transfer count register 0B 1 Memory address register 1A I/O address register 1A Transfer count register 1A Memory address register 1B I/O address register 1B Transfer count register 1B 0, 1 DMA write enable register Abbreviation R/W MAR0A IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B DMAWER R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Address* Bus Width 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 8 bits 8 bits 16 bits 16 bits 16 bits 16 bits 16 bits 8 bits Undefined H'FEE0 Undefined H'FEE4 Undefined H'FEE6 Undefined H'FEE8 Undefined H'FEEC Undefined H'FEEE Undefined H'FEF0 Undefined H'FEF4 Undefined H'FEF6 Undefined H'FEF8 Undefined H'FEFC Undefined H'FEFE H'00 H'00 H'00 H'00 H'00 H'00 H'0000 H'3FFF H'FF00 H'FF01 H'FF02 H'FF03 H'FF04 H'FF05 H'FF06 H'FF3C DMA terminal control register DMATCR DMA control register 0A DMA control register 0B DMA control register 1A DMA control register 1B DMA band control register Module stop control register Note: * Lower 16 bits of the address. DMACR0A DMACR0B DMACR1A DMACR1B DMABCR MSTPCR Rev.6.00 Oct.28.2004 page 170 of 1016 REJ09B0138-0600H 7.2 Register Descriptions (1) (Short Address Mode) Short address mode transfer can be performed for channels A and B independently. Short address mode transfer is specified for each channel by clearing the FAE bit in DMABCR to 0, as shown in table 7-4. Short address mode or full address mode can be selected for channels 1 and 0 independently by means of bits FAE1 and FAE0. Table 7-4 Short Address Mode and Full Address Mode (For 1 Channel: Example of Channel 0) FAE0 0 Description Short address mode specified (channels A and B operate independently) Channel 0A MAR0A IOAR0A ETCR0A DMACR0A MAR0B IOAR0B ETCR0B DMACR0B Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source, etc. Channel 0B Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source, etc. 1 Full address mode specified (channels A and B operate in combination) MAR0A MAR0B Channel 0 IOAR0A IOAR0B ETCR0A ETCR0B DMACR0A DMACR0B Specifies transfer source address Specifies transfer destination address Not used Not used Specifies number of transfers Specifies number of transfers (used in block transfer mode only) Specifies transfer size, mode, activation source, etc. Rev.6.00 Oct.28.2004 page 171 of 1016 REJ09B0138-0600H 7.2.1 Bit MAR Memory Address Registers (MAR) : : 31 — 0 — 15 30 — 0 — 14 29 — 0 — 13 28 — 0 — 12 27 — 0 — 11 26 — 0 — 10 25 — 0 — 9 24 — 0 * * * * * * * * 23 22 21 20 19 18 17 16 Initial value : R/W Bit MAR : : : — R/W R/W R/W R/W R/W R/W R/W R/W 8 7 6 5 4 3 2 1 0 Initial value : R/W * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined MAR is a 32-bit readable/writable register that specifies the transfer source address or destination address. The upper 8 bits of MAR are reserved: they are always read as 0, and cannot be modified. Whether MAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. MAR is incremented or decremented each time a byte or word transfer is executed, so that the address specified by MAR is constantly updated. For details, see section 7.2.4, DMA Control Register (DMACR). MAR is not initialized by a reset or in standby mode. 7.2.2 Bit IOAR I/O Address Register (IOAR) : : * * * * * * * * * * * * * * * * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer source address or destination address. The upper 8 bits of the transfer address are automatically set to H'FF. Whether IOAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. IOAR is invalid in single address mode. IOAR is not incremented or decremented each time a transfer is executed, so that the address specified by IOAR is fixed. IOAR is not initialized by a reset or in standby mode. Rev.6.00 Oct.28.2004 page 172 of 1016 REJ09B0138-0600H 7.2.3 Execute Transfer Count Register (ETCR) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of this register is different for sequential mode and idle mode on the one hand, and for repeat mode on the other. (1) Sequential Mode and Idle Mode Transfer Counter Bit ETCR : : * * * * * * * * * * * * * * * * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter (with a count range of 1 to 65,536). ETCR is decremented by 1 each time a transfer is performed, and when the count reaches H'0000, the DTE bit in DMABCR is cleared, and transfer ends. (2) Repeat Mode Transfer Number Storage Bit ETCRH : : * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W 15 14 13 12 11 10 9 8 Initial value : R/W : Transfer Counter Bit ETCRL : : * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W * : Undefined 7 6 5 4 3 2 1 0 Initial value : R/W : In repeat mode, ETCR functions as transfer counter ETCRL (with a count range of 1 to 256) and transfer number storage register ETCRH. ETCRL is decremented by 1 each time a transfer is performed, and when the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this point, MAR is automatically restored to the value it had when the count was started. The DTE bit in DMABCR is not cleared, and so transfers can be performed repeatedly until the DTE bit is cleared by the user. ETCR is not initialized by a reset or in standby mode. Rev.6.00 Oct.28.2004 page 173 of 1016 REJ09B0138-0600H 7.2.4 Bit DMA Control Register (DMACR) : : 7 DTSZ 0 R/W 6 DTID5 0 R/W 5 RPE 0 R/W 4 DTDIR 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W DMACR Initial value : R/W : DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel. DMACR is initialized to H'00 by a reset, and in hardware standby mode. Bit 7—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time. Bit 7 DTSZ 0 1 Description Byte-size transfer Word-size transfer (Initial value) Bit 6—Data Transfer Increment/Decrement (DTID): Selects incrementing or decrementing of MAR every data transfer in sequential mode or repeat mode. In idle mode, MAR is neither incremented nor decremented. Bit 6 DTID 0 Description MAR is incremented after a data transfer • • 1 When DTSZ = 0, MAR is incremented by 1 after a transfer When DTSZ = 1, MAR is incremented by 2 after a transfer (Initial value) MAR is decremented after a data transfer • • When DTSZ = 0, MAR is decremented by 1 after a transfer When DTSZ = 1, MAR is decremented by 2 after a transfer Bit 5—Repeat Enable (RPE): Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed. Bit 5 RPE 0 DMABCR DTIE 0 1 1 0 1 Description Transfer in sequential mode (no transfer end interrupt) Transfer in sequential mode (with transfer end interrupt) Transfer in repeat mode (no transfer end interrupt) Transfer in idle mode (with transfer end interrupt) (Initial value) For details of operation in sequential, idle, and repeat mode, see section 7.5.2, Sequential Mode, section 7.5.3, Idle Mode, and section 7.5.4, Repeat Mode. Rev.6.00 Oct.28.2004 page 174 of 1016 REJ09B0138-0600H Bit 4—Data Transfer Direction (DTDIR): Used in combination with the SAE bit in DMABCR to specify the data transfer direction (source or destination). The function of this bit is therefore different in dual address mode and single address mode. DMABCR SAE 0 Bit 4 DTDIR 0 1 1 0 1 Description Transfer with MAR as source address and IOAR as destination address (Initial value) Transfer with IOAR as source address and MAR as destination address Transfer with MAR as source address and DACK pin as write strobe Transfer with DACK pin as read strobe and MAR as destination address Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source). There are some differences in activation sources for channel A and for channel B. Channel A Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 Bit 0 DTF0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Description — (Initial value) Activated by A/D converter conversion end interrupt — — Activated by SCI channel 0 transmission data empty interrupt Activated by SCI channel 0 reception data full interrupt Activated by SCI channel 1 transmission data empty interrupt Activated by SCI channel 1 reception data full interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt — — Rev.6.00 Oct.28.2004 page 175 of 1016 REJ09B0138-0600H Channel B Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 Bit 0 DTF0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Description — (Initial value) Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input* Activated by DREQ pin low-level input Activated by SCI channel 0 transmission data empty interrupt Activated by SCI channel 0 reception data full interrupt Activated by SCI channel 1 transmission data empty interrupt Activated by SCI channel 1 reception data full interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt — — Note: * Detected as a low level in the first transfer after transfer is enabled. The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.13, DMAC Multi-Channel Operation. Rev.6.00 Oct.28.2004 page 176 of 1016 REJ09B0138-0600H 7.2.5 Bit DMA Band Control Register (DMABCR) : 15 FAE1 0 R/W 7 DTE1B 0 R/W 14 FAE0 0 R/W 6 DTE1A 0 R/W 13 SAE1 0 R/W 5 DTE0B 0 R/W 12 SAE0 0 R/W 4 DTE0A 0 R/W 11 DTA1B 0 R/W 3 DTIE1B 0 R/W 10 DTA1A 0 R/W 2 DTIE1A 0 R/W 9 DTA0B 0 R/W 1 DTIE0B 0 R/W 8 DTA0A 0 R/W 0 DTIE0A 0 R/W DMABCRH : Initial value : R/W Bit : : DMABCRL : Initial value : R/W : DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel. DMABCR is initialized to H'0000 by a reset, and in hardware standby mode. Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short address mode or full address mode. Bit 15 FAE1 0 1 Description Short address mode Full address mode (Initial value) In short address mode, channels 1A and 1B are used as independent channels. Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short address mode or full address mode. Bit 14 FAE0 0 1 Description Short address mode Full address mode (Initial value) In short address mode, channels 0A and 0B are used as independent channels. Bit 13—Single Address Enable 1 (SAE1): Specifies whether channel 1B is to be used for transfer in dual address mode or single address mode. Bit 13 SAE1 0 1 Description Transfer in dual address mode Transfer in single address mode (Initial value) This bit is invalid in full address mode. Rev.6.00 Oct.28.2004 page 177 of 1016 REJ09B0138-0600H Bit 12—Single Address Enable 0 (SAE0): Specifies whether channel 0B is to be used for transfer in dual address mode or single address mode. Bit 12 SAE0 0 1 Description Transfer in dual address mode Transfer in single address mode (Initial value) This bit is invalid in full address mode. Bits 11 to 8—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the CPU or DTC. When DTE = 1 and DTA = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the CPU or DTC regardless of the DTA bit setting. Bit 11—Data Transfer Acknowledge 1B (DTA1B): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1B data transfer factor setting. Bit 11 DTA1B 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bit 10—Data Transfer Acknowledge 1A (DTA1A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1A data transfer factor setting. Bit 10 DTA1A 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bit 9—Data Transfer Acknowledge 0B (DTA0B): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0B data transfer factor setting. Bit 9 DTA0B 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Rev.6.00 Oct.28.2004 page 178 of 1016 REJ09B0138-0600H Bit 8—Data Transfer Acknowledge 0A (DTA0A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0A data transfer factor setting. Bit 8 DTA0A 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bits 7 to 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. The conditions for the DTE bit being cleared to 0 are as follows: • When initialization is performed • When the specified number of transfers have been completed in a transfer mode other than repeat mode • When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason When DTE = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the data transfer factor setting. When a request is issued by the activation source, DMA transfer is executed. The condition for the DTE bit being set to 1 is as follows: • When 1 is written to the DTE bit after the DTE bit is read as 0 Bit 7—Data Transfer Enable 1B (DTE1B): Enables or disables data transfer on channel 1B. Bit 7 DTE1B 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bit 6—Data Transfer Enable 1A (DTE1A): Enables or disables data transfer on channel 1A. Bit 6 DTE1A 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bit 5—Data Transfer Enable 0B (DTE0B): Enables or disables data transfer on channel 0B. Bit 5 DTE0B 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Rev.6.00 Oct.28.2004 page 179 of 1016 REJ09B0138-0600H Bit 4—Data Transfer Enable 0A (DTE0A): Enables or disables data transfer on channel 0A. Bit 4 DTE0A 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bits 3 to 0—Data Transfer End Interrupt Enable (DTIE): These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIE bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE bit to 1. Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1B transfer end interrupt. Bit 3 DTIE1B 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Bit 2—Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1A transfer end interrupt. Bit 2 DTIE1A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0B transfer end interrupt. Bit 1 DTIE0B 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Bit 0—Data Transfer Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0A transfer end interrupt. Bit 0 DTIE0A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Rev.6.00 Oct.28.2004 page 180 of 1016 REJ09B0138-0600H 7.3 Register Descriptions (2) (Full Address Mode) Full address mode transfer is performed with channels A and B together. For details of full address mode setting, see table 7-4. 7.3.1 Bit MAR Memory Address Register (MAR) : : 31 — 0 — 15 30 — 0 — 14 29 — 0 — 13 28 — 0 — 12 27 — 0 — 11 26 — 0 — 10 25 — 0 — 9 24 — 0 * * * * * * * * 23 22 21 20 19 18 17 16 Initial value : R/W Bit MAR : : : — R/W R/W R/W R/W R/W R/W R/W R/W 8 7 6 5 4 3 2 1 0 Initial value : R/W * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined MAR is a 32-bit readable/writable register; MARA functions as the transfer source address register, and MARB as the destination address register. MAR is composed of two 16-bit registers, MARH and MARL. The upper 8 bits of MARH are reserved; they are always read as 0, and cannot be modified. MAR is incremented or decremented each time a byte or word transfer is executed, so that the source or destination memory address can be updated automatically. For details, see section 7.3.4, DMA Control Register (DMACR). MAR is not initialized by a reset or in standby mode. 7.3.2 I/O Address Register (IOAR) IOAR is not used in full address transfer. 7.3.3 Execute Transfer Count Register (ETCR) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The function of this register is different in normal mode and in block transfer mode. ETCR is not initialized by a reset or in standby mode. Rev.6.00 Oct.28.2004 page 181 of 1016 REJ09B0138-0600H (1) Normal Mode ETCRA Transfer Counter Bit ETCR : : * * * * * * * * * * * * * * * * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each time a transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not used at this time. ETCRB ETCRB is not used in normal mode. (2) Block Transfer Mode ETCRA Holds block size Bit ETCRAH : : * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W 15 14 13 12 11 10 9 8 Initial value : R/W : Block size counter Bit ETCRAL : : * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W * : Undefined 7 6 5 4 3 2 1 0 Initial value : R/W : ETCRB Block Transfer Counter Bit ETCRB : : * * * * * * * * * * * * * * * * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH holds the block size. ETCRAL is decremented each time a 1-byte or 1-word transfer is performed, and when the count reaches H'00, ETCRAL is loaded with the value in ETCRAH. So by setting the block size in ETCRAH and ETCRAL, it is possible to repeatedly transfer blocks consisting of any desired number of bytes or words. ETCRB functions in block transfer mode, as a 16-bit block transfer counter. ETCRB is decremented by 1 each time a block is transferred, and transfer ends when the count reaches H'0000. Rev.6.00 Oct.28.2004 page 182 of 1016 REJ09B0138-0600H 7.3.4 DMA Control Register (DMACR) DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel. In full address mode, DMACRA and DMACRB have different functions. DMACR is initialized to H'0000 by a reset, and in hardware standby mode. DMACRA Bit : 15 DTSZ 0 R/W 14 SAID 0 R/W 13 SAIDE 0 R/W 12 BLKDIR 0 R/W 11 BLKE 0 R/W 10 — 0 R/W 9 — 0 R/W 8 — 0 R/W DMACRA : Initial value : R/W : DMACRB Bit : 7 — 0 R/W 6 DAID 0 R/W 5 DAIDE 0 R/W 4 — 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W DMACRB : Initial value : R/W : Bit 15—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time. Bit 15 DTSZ 0 1 Description Byte-size transfer Word-size transfer (Initial value) Bit 14—Source Address Increment/Decrement (SAID) Bit 13—Source Address Increment/Decrement Enable (SAIDE): These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data transfer is performed. Bit 14 SAID 0 Bit 13 SAIDE 0 1 Description MARA is fixed MARA is incremented after a data transfer • • 1 0 1 When DTSZ = 0, MARA is incremented by 1 after a transfer When DTSZ = 1, MARA is incremented by 2 after a transfer (Initial value) MARA is fixed MARA is decremented after a data transfer • • When DTSZ = 0, MARA is decremented by 1 after a transfer When DTSZ = 1, MARA is decremented by 2 after a transfer Bit 12—Block Direction (BLKDIR) Rev.6.00 Oct.28.2004 page 183 of 1016 REJ09B0138-0600H Bit 11—Block Enable (BLKE): These bits specify whether normal mode or block transfer mode is to be used. If block transfer mode is specified, the BLKDIR bit specifies whether the source side or the destination side is to be the block area. Bit 12 BLKDIR 0 Bit 11 BLKE 0 1 1 0 1 Description Transfer in normal mode (Initial value) Transfer in block transfer mode, destination side is block area Transfer in normal mode Transfer in block transfer mode, source side is block area For operation in normal mode and block transfer mode, see section 7.5, Operation. Bits 10 to 7—Reserved: Can be read or written to. Write 0 to these bits. Bit 6—Destination Address Increment/Decrement (DAID) Bit 5—Destination Address Increment/Decrement Enable (DAIDE): These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed. Bit 6 DAID 0 Bit 5 DAIDE 0 1 Description MARB is fixed MARB is incremented after a data transfer • • 1 0 1 When DTSZ = 0, MARB is incremented by 1 after a transfer When DTSZ = 1, MARB is incremented by 2 after a transfer (Initial value) MARB is fixed MARB is decremented after a data transfer • • When DTSZ = 0, MARB is decremented by 1 after a transfer When DTSZ = 1, MARB is decremented by 2 after a transfer Bit 4—Reserved: Can be read or written to. Write 0 to this bit. Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source). The factors that can be specified differ between normal mode and block transfer mode. • Normal Mode Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 Bit 0 DTF0 0 1 1 0 1 1 0 1 × × × 0 1 1 × Description — — Activated by DREQ pin falling edge input Activated by DREQ pin low-level input — Auto-request (cycle steal) Auto-request (burst) — ×: Don't care Rev.6.00 Oct.28.2004 page 184 of 1016 REJ09B0138-0600H (Initial value) • Block Transfer Mode Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 Bit 0 DTF0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Description — (Initial value) Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input* Activated by DREQ pin low-level input Activated by SCI channel 0 transmission data empty interrupt Activated by SCI channel 0 reception data full interrupt Activated by SCI channel 1 transmission data empty interrupt Activated by SCI channel 1 reception data full interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt — — Note: * Detected as a low level in the first transfer after transfer is enabled. The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.13, DMAC Multi-Channel Operation. Rev.6.00 Oct.28.2004 page 185 of 1016 REJ09B0138-0600H 7.3.5 Bit DMA Band Control Register (DMABCR) : 15 FAE1 0 R/W 7 DTME1 0 R/W 14 FAE0 0 R/W 6 DTE1 0 R/W 13 — 0 R/W 5 DTME0 0 R/W 12 — 0 R/W 4 DTE0 0 R/W 11 DTA1 0 R/W 3 DTIE1B 0 R/W 10 — 0 R/W 2 DTIE1A 0 R/W 9 DTA0 0 R/W 1 DTIE0B 0 R/W 8 — 0 R/W 0 DTIE0A 0 R/W DMABCRH : Initial value : R/W Bit : : DMABCRL : Initial value : R/W : DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel. DMABCR is initialized to H'0000 by a reset, and in standby mode. Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short address mode or full address mode. In full address mode, channels 1A and 1B are used together as a single channel. Bit 15 FAE1 0 1 Description Short address mode Full address mode (Initial value) Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short address mode or full address mode. In full address mode, channels 0A and 0B are used together as a single channel. Bit 14 FAE0 0 1 Description Short address mode Full address mode (Initial value) Bits 13 and 12—Reserved: Can be read or written to. Write 0 to these bits. Rev.6.00 Oct.28.2004 page 186 of 1016 REJ09B0138-0600H Bits 11 and 9—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the CPU or DTC. When the DTE = 1 and the DTA = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When the DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the CPU or DTC regardless of the DTA bit setting. The state of the DTME bit does not affect the above operations. Bit 11—Data Transfer Acknowledge 1 (DTA1): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1 data transfer factor setting. Bit 11 DTA1 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bit 9—Data Transfer Acknowledge 0 (DTA0): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0 data transfer factor setting. Bit 9 DTA0 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bits 10 and 8—Reserved: Can be read or written to. Write 0 to these bits. Bits 7 and 5—Data Transfer Master Enable (DTME): Together with the DTE bit, these bits control enabling or disabling of data transfer on the relevant channel. When both the DTME bit and the DTE bit are set to 1, transfer is enabled for the channel. If the relevant channel is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU. When the DTME bit is subsequently set to 1 again, the interrupted transfer is resumed. In block transfer mode, however, the DTME bit is not cleared by an NMI interrupt, and transfer is not interrupted. The conditions for the DTME bit being cleared to 0 are as follows: • When initialization is performed • When NMI is input in burst mode • When 0 is written to the DTME bit The condition for DTME being set to 1 is as follows: • When 1 is written to DTME after DTME is read as 0 Rev.6.00 Oct.28.2004 page 187 of 1016 REJ09B0138-0600H Bit 7—Data Transfer Master Enable 1 (DTME1): Enables or disables data transfer on channel 1. Bit 7 DTME1 0 1 Description Data transfer disabled. In burst mode, cleared to 0 by an NMI interrupt Data transfer enabled (Initial value) Bit 5—Data Transfer Master Enable 0 (DTME0): Enables or disables data transfer on channel 0. Bit 5 DTME0 0 1 Description Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt (Initial value) Data transfer enabled Bits 6 and 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU. The conditions for the DTE bit being cleared to 0 are as follows: • When initialization is performed • When the specified number of transfers have been completed • When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason When DTE = 1 and DTME = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the data transfer factor setting. When a request is issued by the activation source, DMA transfer is executed. The condition for the DTE bit being set to 1 is as follows: • When 1 is written to the DTE bit after the DTE bit is read as 0 Bit 6—Data Transfer Enable 1 (DTE1): Enables or disables data transfer on channel 1. Bit 6 DTE1 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bit 4—Data Transfer Enable 0 (DTE0): Enables or disables data transfer on channel 0. Bit 4 DTE0 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Rev.6.00 Oct.28.2004 page 188 of 1016 REJ09B0138-0600H Bits 3 and 1—Data Transfer Interrupt Enable B (DTIEB): These bits enable or disable an interrupt to the CPU or DTC when transfer is interrupted. If the DTIEB bit is set to 1 when DTME = 0, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC. A transfer break interrupt can be canceled either by clearing the DTIEB bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the DTME bit to 1. Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1 transfer break interrupt. Bit 3 DTIE1B 0 1 Description Transfer break interrupt disabled Transfer break interrupt enabled (Initial value) Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0 transfer break interrupt. Bit 1 DTIE0B 0 1 Description Transfer break interrupt disabled Transfer break interrupt enabled (Initial value) Bits 2 and 0—Data Transfer End Interrupt Enable A (DTIEA): These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If DTIEA bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIEA bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE bit to 1. Bit 2—Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1 transfer end interrupt. Bit 2 DTIE1A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Bit 0—Data Transfer Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0 transfer end interrupt. Bit 0 DTIE0A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Rev.6.00 Oct.28.2004 page 189 of 1016 REJ09B0138-0600H 7.4 7.4.1 Register Descriptions (3) DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions so that specific bits of DMACR for the specific channel, and also DMATCR and DMABCR, can be changed to prevent inadvertent rewriting of registers other than those for the channel concerned. The restrictions applied by DMAWER are valid for the DTC. Figure 7-2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt, and reactivating channel 0A. The address register and count register area is re-set by the first DTC transfer, then the control register area is re-set by the second DTC chain transfer. When re-setting the control register area, perform masking by setting bits in DMAWER to prevent modification of the contents of the other channels. First transfer area MAR0A IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A DTC IOAR1A ETCR1A MAR1B IOAR1B ETCR1B DMAWER DMACR0A DMACR1A Second transfer area using chain transfer DMATCR DMACR0B DMACR1B DMABCR Figure 7-2 Areas for Register Re-Setting by DTC (Example: Channel 0A) Bit : 7 — 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 WE1B 0 R/W 2 WE1A 0 R/W 1 WE0B 0 R/W 0 WE0A 0 R/W DMAWER : Initial value : R/W : DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to the DMACR, DMABCR, and DMATCR by the DTC. DMAWER is initialized to H'00 by a reset, and in standby mode. Rev.6.00 Oct.28.2004 page 190 of 1016 REJ09B0138-0600H Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0. Bit 3—Write Enable 1B (WE1B): Enables or disables writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR by the DTC. Bit 3 WE1B 0 1 Description Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are disabled (Initial value) Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are enabled Bit 2—Write Enable 1A (WE1A): Enables or disables writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR by the DTC. Bit 2 WE1A 0 1 Description Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are disabled (Initial value) Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are enabled Bit 1—Write Enable 0B (WE0B): Enables or disables writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR. Bit 1 WE0B 0 1 Description Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are disabled (Initial value) Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are enabled Bit 0—Write Enable 0A (WE0A): Enables or disables writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR. Bit 0 WE0A 0 1 Description Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled (Initial value) Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the DMAWER settings. These bits should be changed, if necessary, by CPU processing. In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0. To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable B for the channel to be reactivated. MAR, IOAR, and ETCR are always write-enabled regardless of the DMAWER settings. When modifying these registers, the channel for which the modification is to be made should be halted. Rev.6.00 Oct.28.2004 page 191 of 1016 REJ09B0138-0600H 7.4.2 Bit DMA Terminal Control Register (DMATCR) : 7 — 0 — 6 — 0 — 5 TEE1 0 R/W 4 TEE0 0 R/W 3 — 0 — 2 — 0 — 1 — 0 — 0 — 0 — DMATCR : Initial value : R/W : DMATCR is an 8-bit readable/writable register that controls enabling or disabling of DMAC transfer end pin output. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. DMATCR is initialized to H'00 by a reset, and in standby mode. Bits 7 and 6—Reserved: These bits cannot be modified and are always read as 0. Bit 5—Transfer End Enable 1 (TEE1): Enables or disables transfer end pin 1 (TEND1) output. Bit 5 TEE1 0 1 Description TEND1 pin output disabled TEND1 pin output enabled (Initial value) Bit 4—Transfer End Enable 0 (TEE0): Enables or disables transfer end pin 0 (TEND0) output. Bit 4 TEE0 0 1 Description TEND0 pin output disabled TEND0 pin output enabled (Initial value) The TEND pins are assigned only to channel B in short address mode. The transfer end signal indicates the transfer cycle in which the transfer counter reached 0, regardless of the transfer source. An exception is block transfer mode, in which the transfer end signal indicates the transfer cycle in which the block counter reached 0. Bits 3 to 0—Reserved: These bits cannot be modified and are always read as 0. Rev.6.00 Oct.28.2004 page 192 of 1016 REJ09B0138-0600H 7.4.3 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 9 8 7 6 5 4 3 2 1 0 Bit : 15 14 13 12 11 Initial value : R/W 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP15 bit in MSTPCR is set to 1, the DMAC operation stops at the end of the bus cycle and a transition is made to module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 15—Module Stop (MSTP15): Specifies the DMAC module stop mode. Bits 15 MSTP15 0 1 Description DMAC module stop mode cleared DMAC module stop mode set (Initial value) Rev.6.00 Oct.28.2004 page 193 of 1016 REJ09B0138-0600H 7.5 7.5.1 Operation Transfer Modes Table 7-5 lists the DMAC modes. Table 7-5 DMAC Transfer Modes Transfer Mode Short address mode Transfer Source TPU channel 0 to 5 compare match/input capture A interrupts SCI transmission data empty interrupt SCI reception data full • interrupt A/D converter conversion end interrupt External request • Remarks • • Up to 4 channels can operate independently External request applies to channel B only Single address mode applies to channel B only Modes (1), (2), and (3) can also be specified for single address mode Dual (1) Sequential mode • address (2) Idle mode mode (3) Repeat mode • • • • (4) Single address mode Full address (5) Normal mode mode • • External request Auto-request • Max. 2-channel operation, combining channels A and B With auto-request, burst mode transfer or cycle steal transfer can be selected • (6) Block transfer mode • TPU channel 0 to 5 compare match/input capture A interrupt SCI transmission data empty interrupt SCI reception data full interrupt A/D converter conversion end interrupt External request • • • • Rev.6.00 Oct.28.2004 page 194 of 1016 REJ09B0138-0600H Operation in each mode is summarized below. (1) Sequential mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. One address is specified as 24 bits, and the other as 16 bits. The transfer direction is programmable. (2) Idle mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. One address is specified as 24 bits, and the other as 16 bits. The transfer source address and transfer destination address are fixed. The transfer direction is programmable. (3) Repeat mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. When the specified number of transfers have been completed, the addresses and transfer counter are restored to their original settings, and operation is continued. No interrupt request is sent to the CPU or DTC. One address is specified as 24 bits, and the other as 16 bits. The transfer direction is programmable. (4) Single address mode In response to a single transfer request, the specified number of transfers are carried out between external memory and an external device, one byte or one word at a time. Unlike dual address mode, source and destination accesses are performed in parallel. Therefore, either the source or the destination is an external device which can be accessed with a strobe alone, using the DACK pin. One address is specified as 24 bits, and for the other, the pin is set automatically. The transfer direction is programmable. Modes (1), (2) and (3) can also be specified for single address mode. (5) Normal mode • Auto-request By means of register settings only, the DMAC is activated, and transfer continues until the specified number of transfers have been completed. An interrupt request can be sent to the CPU or DTC when transfer is completed. Both addresses are specified as 24 bits.  Cycle steal mode: The bus is released to another bus master every byte or word transfer.  Burst mode: The bus is held and transfer continued until the specified number of transfers have been completed. • External request In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. Both addresses are specified as 24 bits. (6) Block transfer mode In response to a single transfer request, a block transfer of the specified block size is carried out. This is repeated the specified number of times, once each time there is a transfer request. At the end of each single block transfer, one address is restored to its original setting. An interrupt request can be sent to the CPU or DTC when the specified number of block transfers have been completed. Both addresses are specified as 24 bits. Rev.6.00 Oct.28.2004 page 195 of 1016 REJ09B0138-0600H 7.5.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7-6 summarizes register functions in sequential mode. Table 7-6 Register Functions in Sequential Mode Function Register 23 MAR 23 H'FF 15 ETCR 15 IOAR DTDIR = 0 DTDIR = 1 Initial Setting 0 Source Operation address register address register Destination Start address of Incremented/ address transfer destination decremented every register or transfer source transfer address register Start address of Fixed transfer source or transfer destination Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 0 Destination Source 0 Transfer counter Legend: MAR: Memory address register IOAR: I/O address register ETCR: Transfer count register DTDIR:Data transfer direction bit MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. Rev.6.00 Oct.28.2004 page 196 of 1016 REJ09B0138-0600H Figure 7-3 illustrates operation in sequential mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID • (2DTSZ • (N–1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7-3 Operation in Sequential Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536. Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission data empty and reception data full interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can be set for channel B only. Rev.6.00 Oct.28.2004 page 197 of 1016 REJ09B0138-0600H Figure 7-4 shows an example of the setting procedure for sequential mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set transfer source and transfer destination addresses [2] [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Clear the RPE bit to 0 to select sequential mode. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts with the DTIE bit. • Set the DTE bit to 1 to enable transfer. Sequential mode setting Set DMABCRH Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Sequential mode Figure 7-4 Example of Sequential Mode Setting Procedure Rev.6.00 Oct.28.2004 page 198 of 1016 REJ09B0138-0600H 7.5.3 Idle Mode Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7-7 summarizes register functions in idle mode. Table 7-7 Register Functions in Idle Mode Function Register 23 MAR 23 H'FF 15 ETCR 15 IOAR DTDIR = 0 DTDIR = 1 Initial Setting 0 Source Operation address register address register Destination Start address of Fixed address transfer destination register or transfer source address register Start address of Fixed transfer source or transfer destination Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 0 Destination Source 0 Transfer counter Legend: MAR: Memory address register IOAR: I/O address register ETCR: Transfer count register DTDIR:Data transfer direction bit MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is neither incremented nor decremented each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. Figure 7-5 illustrates operation in idle mode. MAR Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Figure 7-5 Operation in Idle Mode Rev.6.00 Oct.28.2004 page 199 of 1016 REJ09B0138-0600H The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536. Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission data empty and reception data full interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can be set for channel B only. When the DMAC is used in single address mode, only channel B can be set. Figure 7-6 shows an example of the setting procedure for idle mode. Idle mode setting [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set DMABCRH Set transfer source and transfer destination addresses [2] Set number of transfers [3] [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Set the RPE bit to 1. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. • Set the DTIE bit to 1. • Set the DTE bit to 1 to enable transfer. Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Idle mode Figure 7-6 Example of Idle Mode Setting Procedure Rev.6.00 Oct.28.2004 page 200 of 1016 REJ09B0138-0600H 7.5.4 Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7-8 summarizes register functions in repeat mode. Table 7-8 Register Functions in Repeat Mode Function Register 23 MAR DTDIR = 0 DTDIR = 1 Initial Setting 0 Source Operation address register Destination Start address of Incremented/ address transfer destination decremented every register or transfer source transfer. Initial setting is restored when value reaches H'0000 address register Start address of Fixed transfer source or transfer destination Number of transfers Fixed 23 H'FF 15 IOAR 7 ETCRH 0 Destination Source address register transfers 0 Holds number of 7 ETCRL 0 Transfer counter Number of transfers Decremented every transfer. Loaded with ETCRH value when count reaches H'00 Legend: MAR: Memory address register IOAR: I/O address register ETCR: Transfer count register DTDIR:Data transfer direction bit MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. The number of transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when H'00 is set in both ETCRH and ETCRL, is 256. In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number of transfers. ETCRL is decremented by 1 each time a transfer is executed, and when its value reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR restoration operation is as shown below. MAR = MAR – (–1)DTID · 2DTSZ · ETCRH Rev.6.00 Oct.28.2004 page 201 of 1016 REJ09B0138-0600H The same value should be set in ETCRH and ETCRL. In repeat mode, operation continues until the DTE bit is cleared. To end the transfer operation, therefore, you should clear the DTE bit to 0. A transfer end interrupt request is not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the transfer after that terminated when the DTE bit was cleared. Figure 7-7 illustrates operation in repeat mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID • (2DTSZ • (N–1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7-7 Operation in Repeat mode Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission data empty and reception data full interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can be set for channel B only. Rev.6.00 Oct.28.2004 page 202 of 1016 REJ09B0138-0600H Figure 7-8 shows an example of the setting procedure for repeat mode. Repeat mode setting [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in both ETCRH and ETCRL. [2] [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Set the RPE bit to 1. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. • Clear the DTIE bit to 0. • Set the DTE bit to 1 to enable transfer. Set DMABCRH Set transfer source and transfer destination addresses Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Repeat mode Figure 7-8 Example of Repeat Mode Setting Procedure Rev.6.00 Oct.28.2004 page 203 of 1016 REJ09B0138-0600H 7.5.5 Single Address Mode Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCR to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR in DMACR. Table 7-9 summarizes register functions in single address mode. Table 7-9 Register Functions in Single Address Mode Function Register 23 MAR DTDIR = 0 DTDIR = 1 Initial Setting 0 Source Operation address register Write strobe Destination Start address of * address transfer destination register or transfer source Read strobe (Set automatically Strobe for external by SAE bit; IOAR is device invalid) Number of transfers * DACK pin 15 ETCR 0 Transfer counter Legend: MAR: Memory address register IOAR: I/O address register ETCR: Transfer count register DTDIR:Data transfer direction bit DACK: Data transfer acknowledge Note: * See the operation descriptions in sections 7.5.2, Sequential Mode, 7.5.3, Idle Mode, and 7.5.4, Repeat Mode. MAR specifies the start address of the transfer source or transfer destination as 24 bits. IOAR is invalid; in its place the strobe for external devices (DACK) is output. Rev.6.00 Oct.28.2004 page 204 of 1016 REJ09B0138-0600H Figure 7-9 illustrates operation in single address mode (when sequential mode is specified). Address T Transfer DACK 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID • (2DTSZ • (N–1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7-9 Operation in Single Address Mode (When Sequential Mode Is Specified) Rev.6.00 Oct.28.2004 page 205 of 1016 REJ09B0138-0600H Figure 7-10 shows an example of the setting procedure for single address mode (when sequential mode is specified). Single address mode setting Set DMABCRH [1] [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Set the SAE bit to 1 to select single address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [2] Set the transfer source address/transfer destination address in MAR. Set transfer source and transfer destination addresses [2] [3] Set the number of transfers in ETCR. [4] Set each bit in DMACR. • Set the transfer data size with the DTSZ bit. • Specify whether MAR is to be incremented or decremented with the DTID bit. • Clear the RPE bit to 0 to select sequential mode. • Specify the transfer direction with the DTDIR bit. • Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts with the DTIE bit. • Set the DTE bit to 1 to enable transfer. Set DMABCRL [6] Single address mode Figure 7-10 Example of Single Address Mode Setting Procedure (When Sequential Mode Is Specified) Rev.6.00 Oct.28.2004 page 206 of 1016 REJ09B0138-0600H 7.5.6 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB. Table 7-10 summarizes register functions in normal mode. Table 7-10 Register Functions in Normal Mode Register 23 MARA 23 MARB 15 ETCRA Function 0 Source address Initial Setting Start address of transfer source Operation Incremented/decremented every transfer, or fixed register 0 Destination address register 0 Transfer counter Start address of Incremented/decremented transfer destination every transfer, or fixed Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 Legend: MARA: Memory address register A MARB: Memory address register B ETCRA: Transfer count register A MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented each time a transfer is performed, and when its value reaches H'0000 the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536. Rev.6.00 Oct.28.2004 page 207 of 1016 REJ09B0138-0600H Figure 7-11 illustrates operation in normal mode. Address TA Transfer Address TB Address BA Legend: Address TA Address TB Address BA Address BB Where : LA LB N Address BB = LA = LB = LA + SAIDE • (–1)SAID • (2DTSZ • (N–1)) = LB + DAIDE • (–1)DAID • (2DTSZ • (N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRA Figure 7-11 Operation in Normal Mode Transfer requests (activation sources) are external requests and auto-requests. With auto-request, the DMAC is only activated by register setting, and the specified number of transfers are performed automatically. With auto-request, cycle steal mode or burst mode can be selected. In cycle steal mode, the bus is released to another bus master each time a transfer is performed. In burst mode, the bus is held continuously until transfer ends. Rev.6.00 Oct.28.2004 page 208 of 1016 REJ09B0138-0600H For setting details, see section 7.3.4, DMA Controller Register (DMACR). Figure 7-12 shows an example of the setting procedure for normal mode. Normal mode setting [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the number of transfers in ETCRA. Set DMABCRH Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] [4] Set each bit in DMACRA and DMACRB. • Set the transfer data size with the DTSZ bit. • Specify whether MARA is to be incremented, decremented, or fixed, with the SAID and SAIDE bits. • Clear the BLKE bit to 0 to select normal mode. • Specify whether MARB is to be incremented, decremented, or fixed, with the DAID and DAIDE bits. • Select the activation source with bits DTF3 to DTF0. [5] Read DTE = 0 and DTME = 0 in DMABCRL. Read DMABCRL [5] Set DMABCRL [6] [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts with the DTIE bit. • Set both the DTME bit and the DTE bit to 1 to enable transfer. Normal mode Figure 7-12 Example of Normal Mode Setting Procedure Rev.6.00 Oct.28.2004 page 209 of 1016 REJ09B0138-0600H 7.5.7 Block Transfer Mode In block transfer mode, transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in DMACRA to 1. In block transfer mode, a transfer of the specified block size is carried out in response to a single transfer request, and this is executed the specified number of times. The transfer source is specified by MARA, and the transfer destination by MARB. Either the transfer source or the transfer destination can be selected as a block area (an area composed of a number of bytes or words). Table 7-11 summarizes register functions in block transfer mode. Table 7-11 Register Functions in Block Transfer Mode Register 23 MARA 23 MARB 7 Function 0 Source address Initial Setting Start address of transfer source Operation Incremented/decremented every transfer, or fixed register 0 Destination address register 0 Holds block ETCRAH Start address of Incremented/decremented transfer destination every transfer, or fixed Block size Fixed size Block size Block size Decremented every transfer; ETCRH value copied when count reaches H'00 Decremented every block transfer; transfer ends when count reaches H'0000 7 ETCRAL 15 ETCRB 0 counter 0 Block transfer counter Number of block transfers Legend: MARA: Memory address register A MARB: Memory address register B ETCRA: Transfer count register A ETCRB: Transfer count register B MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in DMACRA. To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL, and N in ETCRB. Figure 7-13 illustrates operation in block transfer mode when MARB is designated as a block area. Rev.6.00 Oct.28.2004 page 210 of 1016 REJ09B0138-0600H Address TA 1st block Transfer Block area Address TB 2nd block Consecutive transfer of M bytes or words is performed in response to one request Address BB Nth block Address BA Legend: Address TA Address TB Address BA Address BB Where : LA LB N M = LA = LB = LA + SAIDE • (–1)SAID • (2DTSZ • (M•N–1)) = LB + DAIDE • (–1)DAID • (2DTSZ • (N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7-13 Operation in Block Transfer Mode (BLKDIR = 0) Rev.6.00 Oct.28.2004 page 211 of 1016 REJ09B0138-0600H Figure 7-14 illustrates operation in block transfer mode when MARA is designated as a block area. Address TA Block area Address BA Address TB Transfer Consecutive transfer of M bytes or words is performed in response to one request 2nd block 1st block Nth block Address BB Legend: Address TA Address TB Address BA Address BB Where : LA LB N M = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (N–1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (M·N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7-14 Operation in Block Transfer Mode (BLKDIR = 1) ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA is restored in accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR. ETCRB is decremented by 1 every block transfer, and when the count reaches H'0000 the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this point, an interrupt request is sent to the CPU or DTC. Figure 7-15 shows the operation flow in block transfer mode. Rev.6.00 Oct.28.2004 page 212 of 1016 REJ09B0138-0600H Start (DTE = DTME = 1) No Transfer request? Yes Acquire bus Read address specified by MARA MARA = MARA + SAIDE·(–1)SAID·2DTSZ Write to address specified by MARB MARB = MARB + DAIDE·(–1)DAID ·2DTSZ ETCRAL = ETCRAL–1 No ETCRAL = H'00 Yes Release bus ETCRAL = ETCRAH BLKDIR = 0 No Yes MARB = MARB – DAIDE·(–1)DAID·2DTSZ·ETCRAH MARA = MARA – SAIDE·(–1)SAID·2DTSZ·ETCRAH ETCRB = ETCRB – 1 No ETCRB = H'0000 Yes Clear DTE bit to 0 to end transfer Figure 7-15 Operation Flow in Block Transfer Mode Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission data empty and reception data full interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. For details, see section 7.3.4, DMA Control Register (DMACR). Figure 7-16 shows an example of the setting procedure for block transfer mode. Rev.6.00 Oct.28.2004 page 213 of 1016 REJ09B0138-0600H Block transfer mode setting [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the block size in both ETCRAH and ETCRAL. Set the number of transfers in ETCRB. [4] Set each bit in DMACRA and DMACRB. • Set the transfer data size with the DTSZ bit. • Specify whether MARA is to be incremented, decremented, or fixed, with the SAID and SAIDE bits. • Set the BLKE bit to 1 to select block transfer mode. • Specify whether the transfer source or the transfer destination is a block area with the BLKDIR bit. • Specify whether MARB is to be incremented, decremented, or fixed, with the DAID and DAIDE bits. • Select the activation source with bits DTF3 to DTF0. [5] Read DTE = 0 and DTME = 0 in DMABCRL. Set DMABCRH Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Block transfer mode [6] Set each bit in DMABCRL. • Specify enabling or disabling of transfer end interrupts to the CPU with the DTIE bit. • Set both the DTME bit and the DTE bit to 1 to enable transfer. Figure 7-16 Example of Block Transfer Mode Setting Procedure Rev.6.00 Oct.28.2004 page 214 of 1016 REJ09B0138-0600H 7.5.8 DMAC Activation Sources DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The activation sources that can be specified depend on the transfer mode and the channel, as shown in table 7-12. Table 7-12 DMAC Activation Sources Short Address Mode Channels 0A and 1A Channels 0B and 1B Full Address Mode Normal Mode × × × × × × × × × × × × × × × × Block Transfer Mode Activation Source Internal Interrupts ADI TXI0 RXI0 TXI1 RXI1 TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A External Requests DREQ pin falling edge input DREQ pin low-level input Auto-request Legend: : Can be specified × : Cannot be specified Activation by Internal Interrupt: An interrupt request selected as a DMAC activation source can be sent simultaneously to the CPU and DTC. For details, see section 5, Interrupt Controller. With activation by an internal interrupt, the DMAC accepts the request independently of the interrupt controller. Consequently, interrupt controller priority settings are not accepted. If the DMAC is activated by a CPU interrupt source or an interrupt source that is not used as a DTC activation source (DTA = 1), the interrupt source flag is cleared automatically by the DMA transfer. With ADI, TXI, and RXI interrupts, however, the interrupt source flag is not cleared unless the prescribed register is accessed in a DMA transfer. If the same interrupt is used as an activation source for more than one channel, the interrupt request flag is cleared when the highestpriority channel is activated first. Transfer requests for other channels are held pending in the DMAC, and activation is carried out in order of priority. When DTE = 0, such as after completion of a transfer, a request from the selected activation source is not sent to the DMAC, regardless of the DTA bit. In this case, the relevant interrupt request is sent to the CPU or DTC. In case of overlap with a CPU interrupt source or DTC activation source (DTA = 0), the interrupt request flag is not cleared by the DMAC. Rev.6.00 Oct.28.2004 page 215 of 1016 REJ09B0138-0600H Activation by External Request: If an external request (DREQ pin) is specified as an activation source, the relevant port should be set to input mode in advance. Level sensing or edge sensing can be used for external requests. External request operation in normal mode (short address mode or full address mode) is described below. When edge sensing is selected, a 1-byte or 1-word transfer is executed each time a high-to-low transition is detected on the DREQ pin. The next transfer may not be performed if the next edge is input before transfer is completed. When level sensing is selected, the DMAC stands by for a transfer request while the DREQ pin is held high. While the DREQ pin is held low, transfers continue in succession, with the bus being released each time a byte or word is transferred. If the DREQ pin goes high in the middle of a transfer, the transfer is interrupted and the DMAC stands by for a transfer request. Activation by Auto-Request: Auto-request activation is performed by register setting only, and transfer continues to the end. With auto-request activation, cycle steal mode or burst mode can be selected. In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is transferred. DMA and CPU cycles usually alternate. In burst mode, the DMAC keeps possession of the bus until the end of the transfer, and transfer is performed continuously. Single Address Mode: The DMAC can operate in dual address mode in which read cycles and write cycles are separate cycles, or single address mode in which read and write cycles are executed in parallel. In dual address mode, transfer is performed with the source address and destination address specified separately. In single address mode, on the other hand, transfer is performed between external space in which either the transfer source or the transfer destination is specified by an address, and an external device for which selection is performed by means of the DACK strobe, without regard to the address. Figure 7-17 shows the data bus in single address mode. RD HWR, LWR A23 to A0 Address bus (Read) External memory D15 to D0 (high impedance) Data bus H8S/2357 Group (Write) External device DACK Figure 7-17 Data Bus in Single Address Mode Rev.6.00 Oct.28.2004 page 216 of 1016 REJ09B0138-0600H When using the DMAC for single address mode reading, transfer is performed from external memory to the external device, and the DACK pin functions as a write strobe for the external device. When using the DMAC for single address mode writing, transfer is performed from the external device to external memory, and the DACK pin functions as a read strobe for the external device. Since there is no directional control for the external device, one or other of the above single directions should be used. Bus cycles in single address mode are in accordance with the settings of the bus controller for the external memory area. On the external device side, DACK is output in synchronization with the address strobe. For details of bus cycles, see section 7.5.11, DMAC Bus Cycles (Single Address Mode). Do not specify internal space for transfer addresses in single address mode. 7.5.9 Basic DMAC Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 7-18. In this example, word-size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations. As with CPU cycles, DMA cycles conform to the bus controller settings. CPU cycle T1 ø DMAC cycle (1-word transfer) T2 T1 T2 T3 T1 T2 T3 CPU cycle Source address Address bus RD HWR LWR Destination address Figure 7-18 Example of DMA Transfer Bus Timing The address is not output to the external address bus in an access to on-chip memory or an internal I/O register. Rev.6.00 Oct.28.2004 page 217 of 1016 REJ09B0138-0600H 7.5.10 DMAC Bus Cycles (Dual Address Mode) Short Address Mode: Figure 7-19 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead ø Address bus RD HWR LWR TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7-19 Example of Short Address Mode Transfer A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released one or more bus cycles are inserted by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. In repeat mode, when TEND output is enabled, TEND output goes low in the transfer cycle in which the transfer counter reaches 0. Rev.6.00 Oct.28.2004 page 218 of 1016 REJ09B0138-0600H Full Address Mode (Cycle Steal Mode): Figure 7-20 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. DMA read ø Address bus RD HWR LWR TEND DMA write DMA read DMA write DMA read DMA write DMA dead Bus release Bus release Bus release Last transfer cycle Bus release Figure 7-20 Example of Full Address Mode (Cycle Steal) Transfer A one-byte or one-word transfer is performed, and after the transfer the bus is released. While the bus is released one bus cycle is inserted by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. Rev.6.00 Oct.28.2004 page 219 of 1016 REJ09B0138-0600H Full Address Mode (Burst Mode): Figure 7-21 shows a transfer example in which TEND output is enabled and wordsize full address mode transfer (burst mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2state access space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead ø Address bus RD HWR LWR TEND Bus release Burst transfer Last transfer cycle Bus release Figure 7-21 Example of Full Address Mode (Burst Mode) Transfer In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. If a request from another higher-priority channel is generated after burst transfer starts, that channel has to wait until the burst transfer ends. If an NMI is generated while a channel designated for burst transfer is in the transfer enabled state, the DTME bit is cleared and the channel is placed in the transfer disabled state. If burst transfer has already been activated inside the DMAC, the bus is released on completion of a one-byte or one-word transfer within the burst transfer, and burst transfer is suspended. If the last transfer cycle of the burst transfer has already been activated inside the DMAC, execution continues to the end of the transfer even if the DTME bit is cleared. Rev.6.00 Oct.28.2004 page 220 of 1016 REJ09B0138-0600H Full Address Mode (Block Transfer Mode): Figure 7-22 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space. DMA read ø Address bus RD HWR LWR TEND Bus release DMA write DMA read DMA write DMA dead DMA read DMA write DMA read DMA write DMA dead Block transfer Bus release Last block transfer Bus release Figure 7-22 Example of Full Address Mode (Block Transfer Mode) Transfer A one-block transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released, one or more bus cycles are inserted by the CPU or DTC. In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. One block is transmitted without interruption. NMI generation does not affect block transfer operation. Rev.6.00 Oct.28.2004 page 221 of 1016 REJ09B0138-0600H DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7-23 shows an example of DREQ pin falling edge activated normal mode transfer. Bus release ø DREQ Address bus DMA control Channel Idle Request DMA read DMA write Bus release DMA read DMA write Bus release Transfer source Transfer destination Transfer source Transfer destination Read Write Idle Request Read Write Idle Request clear period Request clear period Minimum of 2 cycles [1] [2] [3] Minimum of 2 cycles [4] [5] [6] [7] Acceptance resumes Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of ø, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of ø starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the write cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of ø, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7-23 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next ø cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA write cycle ends, acceptance resumes after the end of the write cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev.6.00 Oct.28.2004 page 222 of 1016 REJ09B0138-0600H Figure 7-24 shows an example of DREQ pin falling edge activated block transfer mode transfer. 1 block transfer Bus release ø DREQ Address bus DMA control Channel Idle Request Transfer source Transfer destination 1 block transfer DMA Bus dead release DMA read DMA write DMA dead Bus release DMA read DMA write Transfer source Transfer destination Read Write Dead Idle Read Request Write Dead Idle Request clear period Request clear period Minimun of 2 cycles [1] [2] [3] Minimun of 2 cycles [4] [5] [6] [7] Acceptance resumes Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of ø, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of ø starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of ø, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7-24 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next ø cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA dead cycle ends, acceptance resumes after the end of the dead cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev.6.00 Oct.28.2004 page 223 of 1016 REJ09B0138-0600H DREQ Level Activation Timing (Normal Mode): Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7-25 shows an example of DREQ level activated normal mode transfer. Bus release ø DREQ Address bus DMA control Channel Idle Request DMA read DMA write Bus release DMA read DMA write Bus release Transfer source Transfer destination Transfer source Transfer destination Read Write Idle Request Read Write Idle Request clear period Request clear period Minimum of 2 cycles [1] [2] [3] Minimum of 2 cycles [4] [5] [6] [7] Acceptance resumes Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of ø, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMA cycle is started. [4] [7] Acceptance is resumed after the write cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of ø, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7-25 Example of DREQ Level Activated Normal Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next ø cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the write cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev.6.00 Oct.28.2004 page 224 of 1016 REJ09B0138-0600H Figure 7-26 shows an example of DREQ level activated block transfer mode transfer. 1 block transfer Bus release ø DREQ Address bus DMA control Channel Idle Request Transfer source Transfer destination 1 block transfer DMA Bus dead release DMA read DMA right DMA dead Bus release DMA read DMA right Transfer source Transfer destination Read Write Dead Idle Read Request Write Dead Idle Request clear period Request clear period Minimum of 2 cycles [1] [2] [3] Minimum of 2 cycles [4] [5] [6] [7] Acceptance resumes Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of ø, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMA cycle is started. [4] [7] Acceptance is resumed after the dead cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of ø, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7-26 Example of DREQ Level Activated Block Transfer Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next ø cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev.6.00 Oct.28.2004 page 225 of 1016 REJ09B0138-0600H 7.5.11 DMAC Bus Cycles (Single Address Mode) Single Address Mode (Read): Figure 7-27 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read ø Address bus RD DACK TEND DMA read DMA read DMA DMA read dead Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 7-27 Example of Single Address Mode (Byte Read) Transfer Figure 7-28 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read ø Address bus RD DACK TEND DMA read DMA read DMA dead Bus release Bus release Bus release Last transfer cycle Bus release Figure 7-28 Example of Single Address Mode (Word Read) Transfer A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released, one or more bus cycles are inserted by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. Rev.6.00 Oct.28.2004 page 226 of 1016 REJ09B0138-0600H Single Address Mode (Write): Figure 7-29 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write ø Address bus HWR LWR DACK TEND DMA write DMA write DMA DMA write dead Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 7-29 Example of Single Address Mode (Byte Write) Transfer Figure 7-30 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write ø Address bus HWR LWR DACK TEND DMA write DMA write DMA dead Bus release Bus release Bus release Last transfer cycle Bus release Figure 7-30 Example of Single Address Mode (Word Write) Transfer A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released one or more bus cycles are inserted by the CPU or DTC. Rev.6.00 Oct.28.2004 page 227 of 1016 REJ09B0138-0600H In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7-31 shows an example of DREQ pin falling edge activated single address mode transfer. Bus release ø DREQ Address bus DACK DMA single Bus release DMA single Bus release Transfer source/ destination Transfer source/ destination DMA control Idle Single Idle Single Idle Channel Request Minimum of 2 cycles Request clear period Request Minimum of 2 cycles Request clear period [1] [2] [3] [4] [5] [6] [7] Acceptance resumes [1] Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of ø, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of ø starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the single cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of ø, and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7-31 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next ø cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA single cycle ends, acceptance resumes after the end of the single cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev.6.00 Oct.28.2004 page 228 of 1016 REJ09B0138-0600H DREQ Pin Low Level Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7-32 shows an example of DREQ pin low level activated single address mode transfer. Bus release ø DREQ Address bus DACK DMA single Bus release DMA single Bus release Transfer source/ destination Transfer source/ destination DMA control Idle Single Idle Single Idle Channel Request Minimum of 2 cycles Request clear period Request Minimum of 2 cycles Request clear period [1] [2] [3] [4] [5] [6] [7] Acceptance resumes [1] Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of ø, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMAC cycle is started. [4] [7] Acceptance is resumed after the single cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of ø, and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7-32 Example of DREQ Pin Low Level Activated Single Address Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next ø cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. Rev.6.00 Oct.28.2004 page 229 of 1016 REJ09B0138-0600H 7.5.12 Write Data Buffer Function DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved. When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel. Internal accesses are independent of the bus master, and DMAC dead cycles are regarded as internal accesses. A low level can always be output from the TEND pin if the bus cycle in which a low level is to be output is an external bus cycle. However, a low level is not output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an internal bus cycle, and an external write cycle is executed in parallel with this cycle. Figure 7-33 shows an example of burst mode transfer from on-chip RAM to external memory using the write data buffer function. DMA read DMA write DMA read DMA write DMA read DMA write DMA read DMA write DMA dead ø Internal address Internal read signal External address HWR, LWR TEND Figure 7-33 Example of Dual Address Transfer Using Write Data Buffer Function Figure 7-34 shows an example of single address transfer using the write data buffer function. In this example, the CPU program area is in on-chip memory. Rev.6.00 Oct.28.2004 page 230 of 1016 REJ09B0138-0600H DMA read DMA single CPU read DMA single CPU read ø Internal address Internal read signal External address RD DACK Figure 7-34 Example of Single Address Transfer Using Write Data Buffer Function When the write data buffer function is activated, the DMAC recognizes that the bus cycle concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one state after the start of the DMA write cycle or single address transfer. 7.5.13 DMAC Multi-Channel Operation The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table 7-13 summarizes the priority order for DMAC channels. Table 7-13 DMAC Channel Priority Order Short Address Mode Channel 0A Channel 0B Channel 1A Channel 1B Channel 1 Low Full Address Mode Channel 0 Priority High Rev.6.00 Oct.28.2004 page 231 of 1016 REJ09B0138-0600H If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released the DMAC selects the highest-priority channel from among those issuing a request according to the priority order shown in table 7-13. During burst transfer, or when one block is being transferred in block transfer, the channel will not be changed until the end of the transfer. Figure 7-35 shows a transfer example in which transfer requests are issued simultaneously for channels 0A, 0B, and 1. DMA read ø Address bus RD HWR LWR DMA control Idle Read Channel 0A Channel 0B Channel 1 Bus release Write DMA write DMA read DMA write DMA read DMA DMA write read Idle Read Write Idle Read Write Read Request clear Request hold Request hold Selection Nonselection Request clear Request hold Bus release Selection Request clear Bus release Channel 1 transfer Channel 0A transfer Channel 0B transfer Figure 7-35 Example of Multi-Channel Transfer 7.5.14 Relation between External Bus Requests, Refresh Cycles, the DTC, and the DMAC There can be no break between a DMA cycle read and a DMA cycle write. This means that a refresh cycle, external bus release cycle, or DTC cycle is not generated between the external read and external write in a DMA cycle. In the case of successive read and write cycles, such as in burst transfer or block transfer, a refresh or external bus released state may be inserted after a write cycle. Since the DTC has a lower priority than the DMAC, the DTC does not operate until the DMAC releases the bus. When DMA cycle reads or writes are accesses to on-chip memory or internal I/O registers, these DMA cycles can be executed at the same time as refresh cycles or external bus release. However, simultaneous operation may not be possible when a write buffer is used. Rev.6.00 Oct.28.2004 page 232 of 1016 REJ09B0138-0600H 7.5.15 NMI Interrupts and DMAC When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and the DTME bit are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested. If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on completion of the 1-byte or 1word transfer in progress, then releases the bus, which passes to the CPU. The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again. Figure 7-36 shows the procedure for continuing transfer when it has been interrupted by an NMI interrupt on a channel designated for burst mode transfer. Resumption of transfer on interrupted channel [1] [2] [1] No Check that DTE = 1 and DTME = 0 in DMABCRL Write 1 to the DTME bit. DTE = 1 DTME = 0 Yes Set DTME bit to 1 [2] Transfer continues Transfer ends Figure 7-36 Example of Procedure for Continuing Transfer on Channel Interrupted by NMI Interrupt Rev.6.00 Oct.28.2004 page 233 of 1016 REJ09B0138-0600H 7.5.16 Forced Termination of DMAC Operation If the DTE bit for the channel currently operating is cleared to 0, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit. Figure 7-37 shows the procedure for forcibly terminating DMAC operation by software. Forced termination of DMAC [1] Clear the DTE bit in DMABCRL to 0. If you want to prevent interrupt generation after forced termination of DMAC operation, clear the DTIE bit to 0 at the same time. Clear DTE bit to 0 [1] Forced termination Figure 7-37 Example of Procedure for Forcibly Terminating DMAC Operation Rev.6.00 Oct.28.2004 page 234 of 1016 REJ09B0138-0600H 7.5.17 Clearing Full Address Mode Figure 7-38 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. Clearing full address mode Stop the channel [1] [1] Clear both the DTE bit and the DTME bit in DMABCRL to 0; or wait until the transfer ends and the DTE bit is cleared to 0, then clear the DTME bit to 0. Also clear the corresponding DTIE bit to 0 at the same time. [2] Clear all bits in DMACRA and DMACRB to 0. [3] Clear the FAE bit in DMABCRH to 0. Initialize DMACR [2] Clear FAE bit to 0 [3] Initialization; operation halted Figure 7-38 Example of Procedure for Clearing Full Address Mode Rev.6.00 Oct.28.2004 page 235 of 1016 REJ09B0138-0600H 7.6 Interrupts The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7-14 shows the interrupt sources and their priority order. Table 7-14 Interrupt Source Priority Order Interrupt Name DEND0A DEND0B DEND1A DEND1B Interrupt Source Short Address Mode Interrupt due to end of transfer on channel 0A Interrupt due to end of transfer on channel 0B Interrupt due to end of transfer on channel 1A Interrupt due to end of transfer on channel 1B Full Address Mode Interrupt due to end of transfer on channel 0 Interrupt due to break in transfer on channel 0 Interrupt due to end of transfer on channel 1 Interrupt due to break in transfer on channel 1 Low Interrupt Priority Order High Enabling or disabling of each interrupt source is set by means of the DTIE bit for the corresponding channel in DMABCR, and interrupts from each source are sent to the interrupt controller independently. The relative priority of transfer end interrupts on each channel is decided by the interrupt controller, as shown in table 714. Figure 7-39 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is always generated when the DTIE bit is set to 1 while DTE bit is cleared to 0. DTE/ DTME Transfer end/transfer break interrupt DTIE Figure 7-39 Block Diagram of Transfer End/Transfer Break Interrupt In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to o while DTIEB bit is set to 1. In both short address mode and full address mode, DMABCR should be set so as to prevent the occurrence of a combination that constitutes a condition for interrupt generation during setting. Rev.6.00 Oct.28.2004 page 236 of 1016 REJ09B0138-0600H 7.7 Usage Notes DMAC Register Access during Operation: Except for forced termination, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, the DMAC register should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below. (a) DMAC control starts one cycle before the bus cycle, with output of the internal address. Consequently, MAR is updated in the bus cycle before DMAC transfer. Figure 7-40 shows an example of the update timing for DMAC registers in dual address transfer mode. DMA transfer cycle DMA last transfer cycle DMA dead DMA read ø DMA Internal address DMA control DMA register operation Idle DMA write DMA read DMA write Transfer source Read Transfer destination Write Idle Transfer source Read Transfer destination Write Dead Idle [1] [2] [1] [2'] [3] [1] Transfer source address register MAR operation (incremented/decremented/fixed) Transfer counter ETCR operation (decremented) Block size counter ETCR operation (decremented in block transfer mode) [2] Transfer destination address register MAR operation (incremented/decremented/fixed) [2'] Transfer destination address register MAR operation (incremented/decremented/fixed) Block transfer counter ETCR operation (decremented, in last transfer cycle of a block in block transfer mode) [3] Transfer address register MAR restore operation (in block or repeat transfer mode) Transfer counter ETCR restore (in repeat transfer mode) Block size counter ETCR restore (in block transfer mode) Notes: 1. In single address transfer mode, the update timing is the same as [1]. 2. The MAR operation is post-incrementing/decrementing of the DMA internal address value. Figure 7-40 Example of DMAC Register Update Timing Rev.6.00 Oct.28.2004 page 237 of 1016 REJ09B0138-0600H (b) DMAC registers are read as shown in figure 7-41, when the DMAC transfer cycle occurs immediately after the DMAC register has been read. CPU longword read MAR upper word read ø DMA internal address DMA control DMA register operation Idle MAR lower word read DMA transfer cycle DMA read DMA write Transfer source Read Transfer destination Write Idle [1] [2] Note: The lower word of MAR is the updated value after the operation in [1]. Figure 7-41 Competition between Updating of DMAC Register and CPU Read Operations Module Stop: When the MSTP15 bit in MSTPCR is set to 1, the DMAC clock stops, and the module stop state is entered. However, 1 cannot be written to the MSTP15 bit if any of the DMAC channels is enabled. This setting should therefore be made when DMAC operation is stopped. When the DMAC clock stops, DMAC register accesses can no longer be made. Since the following DMAC register settings are valid even in the module stop state, they should be invalidated, if necessary, before a module stop. • Transfer end/suspend interrupt (DTE = 0 and DTIE = 1) • TEND pin enable (TEE = 1) • DACK pin enable (FAE = 0 and SAE = 1) Medium-Speed Mode: When the DTA bit is 0, internal interrupt signals specified as DMAC transfer sources are edgedetected. In medium-speed mode, the DMAC operates on a medium-speed clock, while on-chip supporting modules operate on a high-speed clock. Consequently, if the period in which the relevant interrupt source is cleared by the CPU, DTC, or another DMAC channel, and the next interrupt is generated, is less than one state with respect to the DMAC clock (bus master clock), edge detection may not be possible and the interrupt may be ignored. Also, in medium-speed mode, DREQ pin sampling is performed on the rising edge of the medium-speed clock. Write Data Buffer Function: When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel. (a) Write Data Buffer Function and DMAC Register Setting If the setting of is changed during execution of an external access by means of the write data buffer function, the external access may not be performed normally. The register that controls external accesses should only be manipulated when external reads, etc., are used with DMAC operation disabled, and the operation is not performed in parallel with external access. Rev.6.00 Oct.28.2004 page 238 of 1016 REJ09B0138-0600H (b) Write Data Buffer Function and DMAC Operation Timing The DMAC can start its next operation during external access using the write data buffer function. Consequently, the DREQ pin sampling timing, TEND output timing, etc., are different from the case in which the write data buffer function is disabled. Also, internal bus cycles maybe hidden, and not visible. (c) Write Data Buffer Function and TEND Output A low level is not output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an internal bus cycle, and an external write cycle is executed in parallel with this cycle. Note, for example, that a low level may not be output from the TEND pin if the write data buffer function is used when data transfer is performed between an internal I/O register and on-chip memory. If at least one of the DMAC transfer addresses is an external address, a low level is output from the TEND pin. Figure 7-42 shows an example in which a low level is not output at the TEND pin. DMA read ø Internal address Internal read signal Internal write signal External address HWR, LWR TEND Not output External write by CPU, etc. DMA write Figure 7-42 Example in Which Low Level is Not Output at TEND Pin Activation by Falling Edge on DREQ Pin: DREQ pin falling edge detection is performed in synchronization with DMAC internal operations. The operation is as follows: [1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and switches to [2]. [2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3]. [3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and switches to [1]. After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is enabled is performed by detection of a low level. Activation Source Acceptance: At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that occurs before execution of the DMABCRL write to enable transfer. Rev.6.00 Oct.28.2004 page 239 of 1016 REJ09B0138-0600H When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ pin low level remaining from the end of the previous transfer, etc. Internal Interrupt after End of Transfer: When the DTE bit is cleared to 0 by the end of transfer or an abort, the selected internal interrupt request will be sent to the CPU or DTC even if DTA is set to 1. Also, if internal DMAC activation has already been initiated when operation is aborted, the transfer is executed but flag clearing is not performed for the selected internal interrupt even if DTA is set to 1. An internal interrupt request following the end of transfer or an abort should be handled by the CPU as necessary. Channel Re-Setting: To reactivate a number of channels when multiple channels are enabled, use exclusive handling of transfer end interrupts, and perform DMABCR control bit operations exclusively. Note, in particular, that in cases where multiple interrupts are generated between reading and writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the DMABCR write data in the original interrupt handling routine will be incorrect, and the write may invalidate the results of the operations by the multiple interrupts. Ensure that overlapping DMABCR operations are not performed by multiple interrupts, and that there is no separation between read and write operations by the use of a bit-manipulation instruction. Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must first be read while cleared to 0 before the CPU can write 1 to them. Rev.6.00 Oct.28.2004 page 240 of 1016 REJ09B0138-0600H Section 8 Data Transfer Controller 8.1 Overview The H8S/2357 Group includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 8.1.1 Features The features of the DTC are: • Transfer possible over any number of channels  Transfer information is stored in memory  One activation source can trigger a number of data transfers (chain transfer) • Wide range of transfer modes  Normal, repeat, and block transfer modes available  Incrementing, decrementing, and fixing of source and destination addresses can be selected • Direct specification of 16-Mbyte address space possible  24-bit transfer source and destination addresses can be specified • Transfer can be set in byte or word units • A CPU interrupt can be requested for the interrupt that activated the DTC  An interrupt request can be issued to the CPU after one data transfer ends  An interrupt request can be issued to the CPU after the specified data transfers have completely ended • Activation by software is possible • Module stop mode can be set  The initial setting enables DTC registers to be accessed. DTC operation is halted by setting module stop mode. Rev.6.00 Oct.28.2004 page 241 of 1016 REJ09B0138-0600H 8.1.2 Block Diagram Figure 8-1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information and hence helping to increase processing speed. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1. Internal address bus Interrupt controller DTC Register information On-chip RAM DTC service request CPU interrupt request Legend: MRA, MRB: CRA, CRB: SAR: DAR: DTCERA to DTCERF: DTVECR: DTC mode registers A and B DTC transfer count registers A and B DTC source address register DTC destination address register DTC enable registers A to F DTC vector register Figure 8-1 Block Diagram of DTC Rev.6.00 Oct.28.2004 page 242 of 1016 REJ09B0138-0600H MRA MRB CRA CRB DAR SAR Interrupt request Control logic DTCERA to DTCERF DTVECR Internal data bus 8.1.3 Register Configuration Table 8-1 summarizes the DTC registers. Table 8-1 DTC Registers Name DTC mode register A DTC mode register B DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B DTC enable registers DTC vector register Module stop control register Abbreviation MRA MRB SAR DAR CRA CRB DTCER DTVECR MSTPCR R/W —* 2 —* 2 —* 2 —* 2 —* 2 —* 2 R/W R/W R/W Initial Value Undefined Undefined Undefined Undefined Undefined Undefined H'00 H'00 H'3FFF Address* 1 —* 3 —* 3 —* 3 —* 3 —* 3 —* 3 H'FF30 to H'FF35 H'FF37 H'FF3C Notes: 1. Lower 16 bits of the address. 2. Registers within the DTC cannot be read or written to directly. 3. Register information is located in on-chip RAM addresses H'F800 to H'FBFF. It cannot be located in external space. When the DTC is used, do not clear the RAME bit in SYSCR to 0. Rev.6.00 Oct.28.2004 page 243 of 1016 REJ09B0138-0600H 8.2 8.2.1 Bit Register Descriptions DTC Mode Register A (MRA) : 7 SM1 6 SM0 Undefined — 5 DM1 Undefined — 4 DM0 Undefined — 3 MD1 Undefined — 2 MD0 Undefined — 1 DTS Undefined — 0 Sz Undefined — Initial value : R/W : Undefined — MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer. Bit 7 SM1 0 1 Bit 6 SM0 — 0 1 Description SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented, decremented, or left fixed after a data transfer. Bit 5 DM1 0 1 Bit 4 DM0 — 0 1 Description DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 MD1 0 Bit 2 MD0 0 1 1 0 1 Description Normal mode Repeat mode Block transfer mode — Rev.6.00 Oct.28.2004 page 244 of 1016 REJ09B0138-0600H Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. Bit 1 DTS 0 1 Description Destination side is repeat area or block area Source side is repeat area or block area Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred. Bit 0 Sz 0 1 Description Byte-size transfer Word-size transfer 8.2.2 Bit DTC Mode Register B (MRB) : 7 CHNE 6 DISEL Undefined — 5 — Undefined — 4 — Undefined — 3 — Undefined — 2 — Undefined — 1 — Undefined — 0 — Undefined — Initial value : R/W : Undefined — MRB is an 8-bit register that controls the DTC operating mode. Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER is not performed. Bit 7 CHNE 0 1 Description End of DTC data transfer (activation waiting state is entered) DTC chain transfer (new register information is read, then data is transferred) Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are disabled or enabled after a data transfer. Bit 6 DISEL 0 1 Description After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 (the DTC clears the interrupt source flag of the activating interrupt to 0) After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the interrupt source flag of the activating interrupt to 0) Bits 5 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2357 Group, and should always be written with 0. Rev.6.00 Oct.28.2004 page 245 of 1016 REJ09B0138-0600H 8.2.3 Bit DTC Source Address Register (SAR) : 23 22 21 20 19 ––– ––– 4 3 2 1 0 Initial value : R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ––– ––– Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — — — — — — SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 8.2.4 Bit DTC Destination Address Register (DAR) : 23 22 21 20 19 ––– ––– 4 3 2 1 0 Initial value : R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ––– ––– Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — — — — — — DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. 8.2.5 Bit DTC Transfer Count Register A (CRA) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — — — — — — — ← CRAH → ← CRAL → CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is repeated. 8.2.6 Bit DTC Transfer Count Register B (CRB) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : R/W : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — — — — — — — Rev.6.00 Oct.28.2004 page 246 of 1016 REJ09B0138-0600H CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. 8.2.7 Bit DTC Enable Registers (DTCER) : 7 DTCE7 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTCE0 0 R/W Initial value : R/W : 0 R/W The DTC enable registers comprise six 8-bit readable/writable registers, DTCERA to DTCERF, with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or disable DTC service for the corresponding interrupt sources. The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode. Bit n—DTC Activation Enable (DTCEn) Bit n DTCEn 0 Description DTC activation by this interrupt is disabled [Clearing conditions] • • 1 When the DISEL bit is 1 and the data transfer has ended When the specified number of transfers have ended (Initial value) DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended (n = 7 to 0) A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources and DTCE bits is shown in table 8-4, together with the vector number generated for each interrupt controller. For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions such as BSET and BCLR. For the initial setting only, however, when multiple activation sources are set at one time, it is possible to disable interrupts and write after executing a dummy read on the relevant register. 8.2.8 Bit DTC Vector Register (DTVECR) : 7 6 5 4 3 2 1 0 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : R/W : 0 R/(W)* 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Note: * A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1 is read. DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. DTVECR is initialized to H'00 by a reset and in hardware standby mode. Rev.6.00 Oct.28.2004 page 247 of 1016 REJ09B0138-0600H Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. When clearing the SWDTE bit to 0 by software, write 0 to SWDTE after reading SWDTE set to 1. Bit 7 SWDTE 0 Description DTC software activation is disabled [Clearing condition] When the DISEL bit is 0 and the specified number of transfers have not ended 1 DTC software activation is enabled [Holding conditions] • • • When the DISEL bit is 1 and data transfer has ended When the specified number of transfers have ended During data transfer due to software activation (Initial value) Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + ((vector number) 1 output > 0 output. If compare matches occur simultaneously, the output changes according to the compare match with the higher priority. Timer output is disabled when bits OS3 to OS0 are all 0. After a reset, the timer output is 0 until the first compare match event occurs. Bit 3 OS3 0 Bit 2 OS2 0 1 1 0 1 Description No change when compare match B occurs 0 is output when compare match B occurs 1 is output when compare match B occurs Output is inverted when compare match B occurs (toggle output) (Initial value) Bit 1 OS1 0 Bit 0 OS0 0 1 Description No change when compare match A occurs 0 is output when compare match A occurs 1 is output when compare match A occurs Output is inverted when compare match A occurs (toggle output) (Initial value) 1 0 1 Rev.6.00 Oct.28.2004 page 440 of 1016 REJ09B0138-0600H 12.2.6 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 9 8 7 6 5 4 3 2 1 0 Bit : 15 14 13 12 11 Initial value : R/W 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP12 bit in MSTPCR is set to 1, the 8-bit timer operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 12—Module Stop (MSTP12): Specifies the 8-bit timer module stop mode. Bit 12 MSTP12 0 1 Description 8-bit timer module stop mode cleared 8-bit timer module stop mode set (Initial value) Rev.6.00 Oct.28.2004 page 441 of 1016 REJ09B0138-0600H 12.3 12.3.1 Operation TCNT Incrementation Timing TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (ø/8, ø/64, or ø/8192) divided from the system clock (ø) can be selected, by setting bits CKS2 to CKS0 in TCR. Figure 12-2 shows the count timing. ø Internal clock Clock input to TCNT TCNT N–1 N N+1 Figure 12-2 Count Timing for Internal Clock Input External Clock: Three incrementation methods can be selected by setting bits CKS2 to CKS0 in TCR: at the rising edge, the falling edge, and both rising and falling edges. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The counter will not increment correctly if the pulse width is less than these values. Figure 12-3 shows the timing of incrementation at both edges of an external clock signal. ø External clock input Clock input to TCNT TCNT N–1 N N+1 Figure 12-3 Count Timing for External Clock Input Rev.6.00 Oct.28.2004 page 442 of 1016 REJ09B0138-0600H 12.3.2 Compare Match Timing Setting of Compare Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare match signal is not generated until the next incrementation clock input. Figure 12-4 shows this timing. ø TCNT N N+1 TCOR Compare match signal N CMF Figure 12-4 Timing of CMF Setting Timer Output Timing: When compare match A or B occurs, the timer output changes a specified by bits OS3 to OS0 in TCSR. Depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. Figure 12-5 shows the timing when the output is set to toggle at compare match A. ø Compare match A signal Timer output pin Figure 12-5 Timing of Timer Output Timing of Compare Match Clear: The timer counter is cleared when compare match A or B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 12-6 shows the timing of this operation. ø Compare match signal TCNT N H'00 Figure 12-6 Timing of Compare Match Clear Rev.6.00 Oct.28.2004 page 443 of 1016 REJ09B0138-0600H 12.3.3 Timing of External RESET on TCNT TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 12-7 shows the timing of this operation. ø External reset input pin Clear signal TCNT N–1 N H'00 Figure 12-7 Timing of External Reset 12.3.4 Timing of Overflow Flag (OVF) Setting The OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure 12-8 shows the timing of this operation. ø TCNT H'FF H'00 Overflow signal OVF Figure 12-8 Timing of OVF Setting Rev.6.00 Oct.28.2004 page 444 of 1016 REJ09B0138-0600H 12.3.5 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B’100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit timer mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match counter mode). In this case, the timer operates as below. 16-Bit Counter Mode: When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. • Setting of compare match flags  The CMF flag in TCSR0 is set to 1 when a 16-bit compare match event occurs.  The CMF flag in TCSR1 is set to 1 when a lower 8-bit compare match event occurs. • Counter clear specification  If the CCLR1 and CCLR0 bits in TCR0 have been set for counter clear at compare match, the 16-bit counter (TCNT0 and TCNT1 together) is cleared when a 16-bit compare match event occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter clear by the TMRI0 pin has also been set.  The settings of the CCLR1 and CCLR0 bits in TCR1 are ignored. The lower 8 bits cannot be cleared independently. • Pin output  Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR0 is in accordance with the 16-bit compare match conditions.  Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR1 is in accordance with the lower 8-bit compare match conditions. Compare Match Counter Mode: When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts compare match A’s for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clear are in accordance with the settings for each channel. Note on Usage: If the 16-bit counter mode and compare match counter mode are set simultaneously, the input clock pulses for TCNT0 and TCNT1 are not generated and thus the counters will stop operating. Software should therefore avoid using both these modes. Rev.6.00 Oct.28.2004 page 445 of 1016 REJ09B0138-0600H 12.4 12.4.1 Interrupts Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 12-3. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR, and independent interrupt requests are sent for each to the interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts. Table 12-3 8-Bit Timer Interrupt Sources Channel 0 Interrupt Source CMIA0 CMIB0 OVI0 1 CMIA1 CMIB1 OVI1 Description Interrupt by CMFA Interrupt by CMFB Interrupt by OVF Interrupt by CMFA Interrupt by CMFB Interrupt by OVF DTC Activation Possible Possible Not possible Possible Possible Not possible Low Priority High Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. 12.4.2 A/D Converter Activation The A/D converter can be activated only by channel 0 compare match A. If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurrence of channel 0 compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. Rev.6.00 Oct.28.2004 page 446 of 1016 REJ09B0138-0600H 12.5 Sample Application In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 12-9. The control bits are set as follows: [1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA. [2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match. With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a pulse width determined by TCORB. No software intervention is required. TCNT H'FF TCORA TCORB H'00 Counter clear TMO Figure 12-9 Example of Pulse Output Rev.6.00 Oct.28.2004 page 447 of 1016 REJ09B0138-0600H 12.6 Usage Notes Application programmers should note that the following kinds of contention can occur in the 8-bit timer. 12.6.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 12-10 shows this operation. TCNT write cycle by CPU T1 T2 ø Address TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 12-10 Contention between TCNT Write and Clear Rev.6.00 Oct.28.2004 page 448 of 1016 REJ09B0138-0600H 12.6.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 12-11 shows this operation. TCNT write cycle by CPU T1 T2 ø Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12-11 Contention between TCNT Write and Increment Rev.6.00 Oct.28.2004 page 449 of 1016 REJ09B0138-0600H 12.6.3 Contention between TCOR Write and Compare Match During the T 2 state of a TCOR write cycle, the TCOR write has priority and the compare match signal is disabled even if a compare match event occurs. Figure 12-12 shows this operation. TCOR write cycle by CPU T1 T2 ø Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare match signal Prohibited Figure 12-12 Contention between TCOR Write and Compare Match 12.6.4 Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 12-4. Table 12-4 Timer Output Priorities Output Setting Toggle output 1 output 0 output No change Low Priority High Rev.6.00 Oct.28.2004 page 450 of 1016 REJ09B0138-0600H 12.6.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 12-5 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in case 3 in table 12-5, a TCNT clock pulse is generated on the assumption that the switchover is a falling edge. This increments TCNT. The erroneous incrementation can also happen when switching between internal and external clocks. Table 12-5 Switching of Internal Clock and TCNT Operation Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from low to low * 1 Clock before switchover Clock after switchover TCNT clock No. 1 TCNT N CKS bit write N+1 2 Switching from low to high* 2 Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit write 3 Switching from high to low* 3 Clock before switchover Clock after switchover *4 TCNT clock TCNT N N+1 CKS bit write N+2 Rev.6.00 Oct.28.2004 page 451 of 1016 REJ09B0138-0600H No. 4 Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from high to high Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit write Notes: 1. 2. 3. 4. Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented. 12.6.6 Interrupts and Module Stop Mode If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Rev.6.00 Oct.28.2004 page 452 of 1016 REJ09B0138-0600H Section 13 Watchdog Timer 13.1 Overview The H8S/2357 Group has a single-channel on-chip watchdog timer (WDT) for monitoring system operation. The WDT outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal for the H8S/2357 Group. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. 13.1.1 Features WDT features are listed below. • Switchable between watchdog timer mode and interval timer mode • WDTOVF output when in watchdog timer mode*1 If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether or not the entire H8S/2357 Group is reset at the same time. This internal reset can be a power-on reset or a manual reset.* 2 • Interrupt generation when in interval timer mode If the counter overflows, the WDT generates an interval timer interrupt. • Choice of eight counter clock sources. Notes: 1. The WDTOVF pin function is not available in the F-ZTAT versions, and the H8S/2398, H8S/2394, H8S/2392, and H8S/2390. 2. Manual reset is only supported in the H8S/2357 ZTAT. Rev.6.00 Oct.28.2004 page 453 of 1016 REJ09B0138-0600H 13.1.2 Block Diagram Figure 13-1 shows a block diagram of the WDT. Overflow WOVI (interrupt request signal) Interrupt control Clock Clock select WDTOVF*2 Internal reset signal*1 Reset control ø/2 ø/64 ø/128 ø/512 ø/2048 ø/8192 ø/32768 ø/131072 Internal clock sources Internal bus RSTCSR TCNT TSCR Module bus Bus interface WDT Legend: TCSR: Timer control/status register TCNT: Timer counter RSTCSR: Reset control/status register Notes: 1. The type of internal reset signal depends on a register setting. Either power-on reset or manual reset can be selected. Manual reset is only supported in the H8S/2357 ZTAT. 2. The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392, or H8S/2390. Figure 13-1 Block Diagram of WDT 13.1.3 Pin Configuration Table 13-1 describes the WDT output pin. Table 13-1 WDT Pin Name Watchdog timer overflow Symbol I/O Function Outputs counter overflow signal in watchdog timer mode WDTOVF* Output Note: * The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392 or H8S/2390. Rev.6.00 Oct.28.2004 page 454 of 1016 REJ09B0138-0600H 13.1.4 Register Configuration The WDT has three registers, as summarized in table 13-2. These registers control clock selection, WDT mode switching, and the reset signal. Table 13-2 WDT Registers Address* 1 Name Timer control/status register Timer counter Reset control/status register Abbreviation TCSR TCNT RSTCSR R/W R/(W)* R/W R/(W)* 3 3 Initial Value H'18 H'00 H'1F Write*2 H'FFBC H'FFBC H'FFBE Read H'FFBC H'FFBD H'FFBF Notes: 1. Lower 16 bits of the address. 2. For details of write operations, see section 13.2.4, Notes on Register Access. 3. Only a write of 0 is permitted to bit 7, to clear the flag. Rev.6.00 Oct.28.2004 page 455 of 1016 REJ09B0138-0600H 13.2 13.2.1 Bit Register Descriptions Timer Counter (TCNT) : 7 6 5 4 3 2 1 0 Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W TCNT is an 8-bit readable/writable*1 up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), either the watchdog timer overflow signal (WDTOVF)*2 or an interval timer interrupt (WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR. TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared to 0. It is not initialized in software standby mode. Notes: 1. TCNT is write-protected by a password to prevent accidental overwriting. For details see section 13.2.4, Notes on Register Access. 2. The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392 or H8S/2390. 13.2.2 Bit Timer Control/Status Register (TCSR) : 7 OVF 6 WT/IT 0 R/W 5 TME 0 R/W 4 — 1 — 3 — 1 — 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : 0 R/(W)* Note: * Can only be written with 0 for flag clearing. TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. TCR is initialized to H'18 by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see section 13.2.4, Notes on Register Access. Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00, when in interval timer mode. This flag cannot be set during watchdog timer operation. Bit 7 OVF 0 Description [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF 1 [Setting condition] Set when TCNT overflows (changes from H'FF to H'00) in interval timer mode Rev.6.00 Oct.28.2004 page 456 of 1016 REJ09B0138-0600H (Initial value) Bit 6—Timer Mode Select (WT/ IT ): Selects whether the WDT is used as a watchdog timer or interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request (WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates the WDTOVF signal*1 when TCNT overflows. Bit 6 WT/IT 0 1 Description Interval timer: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows (Initial value) Watchdog timer: Generates the WDTOVF signal* 1 when TCNT overflows* 2 Notes: 1. The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392 or H8S/2390. 2. For details of the case where TCNT overflows in watchdog timer mode, see section 13.2.3, Reset Control/Status Register (RSTCSR). Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted. Bit 5 TME 0 1 Description TCNT is initialized to H'00 and halted TCNT counts (Initial value) Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 1. Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources, obtained by dividing the system clock (ø), for input to TCNT. Description Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Clock ø/2 (Initial value) ø/64 ø/128 ø/512 ø/2048 ø/8192 ø/32768 ø/131072 Overflow Period (when ø = 20 MHz)* 25.6 µs 819.2 µs 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. 13.2.3 Bit Reset Control/Status Register (RSTCSR) : 7 WOVF 6 RSTE 0 R/W 5 RSTS 0 R/W 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Initial value : R/W : 0 R/(W)* Note: * Can only be written with 0 for flag clearing. Rev.6.00 Oct.28.2004 page 457 of 1016 REJ09B0138-0600H RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by overflows. Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details see section 13.2.4, Notes on Register Access. Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode. Bit 7 WOVF 0 Description [Clearing condition] Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF 1 [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer operation (Initial value) Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the H8S/2357 Group if TCNT overflows during watchdog timer operation. Bit 6 RSTE 0 1 Description Reset signal is not generated if TCNT overflows * Reset signal is generated if TCNT overflows (Initial value) Note: * The modules within the H8S/2357 Group are not reset, but TCNT and TCSR within the WDT are reset. Bit 5—Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows during watchdog timer operation. For details of the types of resets, see section 4, Exception Handling. Bit 5 RSTS 0 1 Description Power-on reset Manual reset* (Initial value) Note: * Manual reset is supported only in the H8S/2357 ZTAT. In the models except the H8S/2357 ZTAT, only 0 should be written to this bit. Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1. Rev.6.00 Oct.28.2004 page 458 of 1016 REJ09B0138-0600H 13.2.4 Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction. They cannot be written to with byte instructions. Figure 13-2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the same write address. For a write to TCNT, the upper byte of the written word must contain H'5A and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written word must contain H'A5 and the lower byte must contain the write data. This transfers the write data from the lower byte to TCNT or TCSR. TCNT write 15 Address: H'FFBC H'5A 87 Write data 0 TCSR write 15 Address: H'FFBC H'A5 87 Write data 0 Figure 13-2 Format of Data Written to TCNT and TCSR Writing to RSTCSR: RSTCSR must be written to by word transfer instruction to address H'FFBE. It cannot be written to with byte instructions. Figure 13-3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF bit differs from that for writing to the RSTE and RSTS bits. To write 0 to the WOVF bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0, but has no effect on the RSTE and RSTS bits. To write to the RSTE and RSTS bits, the upper byte must contain H'5A and the lower byte must contain the write data. This writes the values in bits 6 and 5 of the lower byte into the RSTE and RSTS bits, but has no effect on the WOVF bit. Writing 0 to WOVF bit 15 Address: H'FFBE H'A5 87 H'00 0 Writing to RSTE and RSTS bits 15 Address: H'FFBE H'5A 87 Write data 0 Figure 13-3 Format of Data Written to RSTCSR Reading TCNT, TCSR, and RSTCSR: These registers are read in the same way as other registers. The read addresses are H'FFBC for TCSR, H'FFBD for TCNT, and H'FFBF for RSTCSR. Rev.6.00 Oct.28.2004 page 459 of 1016 REJ09B0138-0600H 13.3 13.3.1 Operation Watchdog Timer Operation To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. This ensures that TCNT does not overflow while the system is operating normally. If TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal*1 is output. This is shown in figure 13-4. This WDTOVF signal*1 can be used to reset the system. The WDTOVF signal*1 is output for 132 states when RSTE = 1, and for 130 states when RSTE = 0. If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the H8S/2357 Group internally is generated at the same time as the WDTOVF signal*1. This reset can be selected as a power-on reset or a manual reset*2, depending on the setting of the RSTS bit in RSTCSR. The internal reset signal is output for 518 states. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. Notes: 1. In the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392, or H8S/2390, the WDTOVF pin function is not available. 2. Manual reset is only supported in the H8S/2357 ZTAT. TCNT count Overflow H'FF H'00 WT/IT=1 TME=1 H'00 written to TCNT WOVF=1 WDTOVF *3 and internal reset are generated WT/IT=1 TME=1 H'00 written to TCNT Time WDTOVF signal*3 132 states*2 Internal reset signal*1 518 states Legend: WT/IT: Timer mode select bit TME: Timer enable bit Notes: 1. The internal reset signal is generated only if the RSTE bit is set to 1. 2. 130 states when the RSTE bit is cleared to 0. 3. The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392, or H8S/2390. Figure 13-4 Watchdog Timer Operation Rev.6.00 Oct.28.2004 page 460 of 1016 REJ09B0138-0600H 13.3.2 Interval Timer Operation To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 13-5. This function can be used to generate interrupt requests at regular intervals. TCNT count H'FF Overflow Overflow Overflow Overflow H'00 WT/IT=0 TME=1 WOVI WOVI WOVI WOVI Time Legend: WOVI: Interval timer interrupt request generation Figure 13-5 Interval Timer Operation 13.3.3 Timing of Setting Overflow Flag (OVF) The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 13-6. ø TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 13-6 Timing of Setting of OVF Rev.6.00 Oct.28.2004 page 461 of 1016 REJ09B0138-0600H 13.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) The WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time, the WDTOVF signal* goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire H8S/2357 Group chip. Figure 13-7 shows the timing in this case. Note: * The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392, or H8S/2390. ø TCNT Overflow signal (internal signal) WOVF H'FF H'00 WDTOVF signal* Internal reset signal 132 states 518 states Note: * The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392, or H8S/2390. Figure 13-7 Timing of Setting of WOVF 13.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. Rev.6.00 Oct.28.2004 page 462 of 1016 REJ09B0138-0600H 13.5 13.5.1 Usage Notes Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 13-8 shows this operation. TCNT write cycle T1 T2 ø Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 13-8 Contention between TCNT Write and Increment 13.5.2 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0. 13.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. 13.5.4 System Reset by WDTOVF Signal If the WDTOVF output signal* is input to the RES pin of the H8S/2357 Group, the H8S/2357 Group will not be initialized correctly. Make sure that the WDTOVF signal* is not input logically to the RES pin. To reset the entire system by means of the WDTOVF signal*, use the circuit shown in figure 13-9. Note: * The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392 or H8S/2390. Rev.6.00 Oct.28.2004 page 463 of 1016 REJ09B0138-0600H H8S/2357 Group Reset input RES Reset signal to entire system WDTOVF* Note: * The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392 or H8S/2390. Figure 13-9 Circuit for System Reset by WDTOVF Signal (Example) 13.5.5 Internal Reset in Watchdog Timer Mode The H8S/2357 Group is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation, but TCNT and TSCR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal* is low. Also note that a read of the WOVF flag is not recognized during this period. To clear the WOVF falg, therefore, read RSTCSR after the WDTOVF signal* goes high, then write 0 to the WOVF flag. Note: * The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392 or H8S/2390. Rev.6.00 Oct.28.2004 page 464 of 1016 REJ09B0138-0600H Section 14 Serial Communication Interface (SCI) 14.1 Overview The H8S/2357 Group is equipped with a three-channel serial communication interface (SCI). All three channels have the same functions. The SCI can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). 14.1.1 Features SCI features are listed below. • Choice of asynchronous or clocked synchronous serial communication mode Asynchronous mode  Serial data communication executed using asynchronous system in which synchronization is achieved character by character  Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA)  A multiprocessor communication function is provided that enables serial data communication with a number of processors  Choice of 12 serial data transfer formats Data length : 7 or 8 bits Stop bit length : 1 or 2 bits Parity : Even, odd, or none Multiprocessor bit : 1 or 0  Receive error detection : Parity, overrun, and framing errors  Break detection : Break can be detected by reading the RxD pin level directly in case of a framing error Clocked Synchronous mode  Serial data communication synchronized with a clock  Serial data communication can be carried out with other chips that have a synchronous communication function  One serial data transfer format Data length : 8 bits  Receive error detection : Overrun errors detected • Full-duplex communication capability  The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously  Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data • Choice of LSB-first or MSB-first transfer  Can be selected regardless of the communication mode* (except in the case of 7-bit data asynchronous mode) • On-chip baud rate generator allows any bit rate to be selected • Choice of serial clock source  Internal clock from baud rate generator or external clock from SCK pin Rev.6.00 Oct.28.2004 page 465 of 1016 REJ09B0138-0600H • Four interrupt sources  Four interrupt sources — transmit-data-empty, transmit-end, receive-data-full, and receive error — that can issue requests independently  The transmit-data-empty interrupt and receive-data-full interrupt can activate the DMA controller (DMAC) or data transfer controller (DTC) to execute data transfer • Module stop mode can be set  As the initial setting, SCI operation is halted. Register access is enabled by exiting module stop mode. Note: * Descriptions in this section refer to LSB-first transfer. Rev.6.00 Oct.28.2004 page 466 of 1016 REJ09B0138-0600H 14.1.2 Block Diagram Figure 14-1 shows a block diagram of the SCI. Bus interface Module data bus Internal data bus RDR TDR RxD RSR TSR SCMR SSR SCR SMR Transmission/ reception control BRR ø Baud rate generator ø/4 ø/16 ø/64 Clock TxD Parity generation Parity check SCK External clock TEI TXI RXI ERI Legend: SCMR: RSR: RDR: TSR: TDR: SMR: SCR: SSR: BRR: Smart Card mode register Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Figure 14-1 Block Diagram of SCI 14.1.3 Pin Configuration Table 14-1 shows the serial pins for each SCI channel. Table 14-1 SCI Pins Channel 0 Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 1 Serial clock pin 1 Receive data pin 1 Transmit data pin 1 2 Serial clock pin 2 Receive data pin 2 Transmit data pin 2 Symbol SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 SCK2 RxD2 TxD2 I/O I/O Input Output I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output Rev.6.00 Oct.28.2004 page 467 of 1016 REJ09B0138-0600H 14.1.4 Register Configuration The SCI has the internal registers shown in table 14-2. These registers are used to specify asynchronous mode or clocked synchronous mode, the data format, and the bit rate, and to control transmitter/receiver. Table 14-2 SCI Registers Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Smart Card mode register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Smart Card mode register 1 2 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit data register 2 Serial status register 2 Receive data register 2 Smart Card mode register 2 All Module stop control register Abbreviation SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 SMR2 BRR2 SCR2 TDR2 SSR2 RDR2 SCMR2 MSTPCR R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W 2 2 2 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'3FFF Address* 1 H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF3C Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. Rev.6.00 Oct.28.2004 page 468 of 1016 REJ09B0138-0600H 14.2 14.2.1 Bit Register Descriptions Receive Shift Register (RSR) : 7 6 5 4 3 2 1 0 R/W : — — — — — — — — RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU. 14.2.2 Bit Receive Data Register (RDR) : 7 6 5 4 3 2 1 0 Initial value : R/W : 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R RDR is a register that stores received serial data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous receive operations to be performed. RDR is a read-only register, and cannot be written to by the CPU. RDR is initialized to H'00 by a reset, and in standby mode or module stop mode. 14.2.3 Bit Transmit Shift Register (TSR) : 7 6 5 4 3 2 1 0 R/W : — — — — — — — — TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not performed if the TDRE bit in SSR is set to 1. TSR cannot be directly read or written to by the CPU. Rev.6.00 Oct.28.2004 page 469 of 1016 REJ09B0138-0600H 14.2.4 Bit Transmit Data Register (TDR) : 7 6 5 4 3 2 1 0 Initial value : R/W : 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W TDR is an 8-bit register that stores data for serial transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to TDR during serial transmission of the data in TSR. TDR can be read or written to by the CPU at all times. TDR is initialized to H'FF by a reset, and in standby mode or module stop mode. 14.2.5 Bit Serial Mode Register (SMR) : 7 C/A 6 CHR 0 R/W 5 PE 0 R/W 4 O/ E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : 0 R/W SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset, and by putting the device in standby mode or module stop mode. In the H8S/2398, H8S/2394, H8S/2392, and H8S/2390, however, the value in SMR is initialized to H'00 by a reset, or in hardware standby mode, but SMR retains its current state when the device enters software standby mode or module stop mode. Bit 7—Communication Mode (C/A): Selects asynchronous mode or clocked synchronous mode as the SCI operating mode. Bit 7 C/A 0 1 Description Asynchronous mode Clocked synchronous mode (Initial value) Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In clocked synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting. Bit 6 CHR 0 1 Description 8-bit data 7-bit data * (Initial value) Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible to choose between LSB-first or MSB-first transfer. Rev.6.00 Oct.28.2004 page 470 of 1016 REJ09B0138-0600H Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In clocked synchronous mode and with a multiprocessor format, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5 PE 0 1 Description Parity bit addition and checking disabled Parity bit addition and checking enabled* (Initial value) Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is invalid in clocked synchronous mode, and when parity addition and checking is disabled in asynchronous mode. Bit 4 O/ E 0 1 Description Even parity* 1 Odd parity * 2 (Initial value) Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bits setting is only valid in asynchronous mode. If clocked synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP 0 1 Description 1 stop bit: In transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. (Initial value) 2 stop bits: In transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in clocked synchronous mode. Rev.6.00 Oct.28.2004 page 471 of 1016 REJ09B0138-0600H For details of the multiprocessor communication function, see section 14.3.3, Multiprocessor Communication Function. Bit 2 MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value) Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from ø, ø/4, ø/16, and ø/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 14.2.8, Bit Rate Register (BRR). Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 Description ø clock ø/4 clock ø/16 clock ø/64 clock (Initial value) 14.2.6 Bit Serial Control Register (SCR) : 7 TIE 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value : R/W : 0 R/W SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCR can be read or written to by the CPU at all times. SCR is initialized to H'00 by a reset, and by putting the device in standby mode or module stop mode. In the H8S/2398, H8S/2394, H8S/2392, and H8S/2390, however, the value in SCR is initialized to H'00 by a reset, or in hardware standby mode, but SCR retains its current state when the device enters software standby mode or module stop mode. Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit data empty interrupt (TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE flag in SSR is set to 1. Bit 7 TIE 0 1 Description Transmit data empty interrupt (TXI) requests disabled* Transmit data empty interrupt (TXI) requests enabled (Initial value) Note: * TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. Rev.6.00 Oct.28.2004 page 472 of 1016 REJ09B0138-0600H Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI) request and receive error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1. Bit 6 RIE 0 1 Description Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled * (Initial value) Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Note: * RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0. Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI. Bit 5 TE 0 1 Description Transmission disabled * 1 Transmission enabled* 2 (Initial value) Notes: 1. The TDRE flag in SSR is fixed at 1. 2. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transfer format before setting the TE bit to 1. Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI. Bit 4 RE 0 1 Description Reception disabled * 1 Reception enabled* 2 (Initial value) Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the transfer format before setting the RE bit to 1. Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1. Rev.6.00 Oct.28.2004 page 473 of 1016 REJ09B0138-0600H The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE 0 Description Multiprocessor interrupts disabled (normal reception performed) [Clearing conditions] • • 1 When the MPIE bit is cleared to 0 When MPB= 1 data is received (Initial value) Multiprocessor interrupts enabled* Receive data full interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR, is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. Bit 2—Transmit End Interrupt Enable (TEIE): Enables or disables transmit end interrupt (TEI) request generation when there is no valid transmit data in TDR in MSB data transmission. Bit 2 TEIE 0 1 Description Transmit end interrupt (TEI) request disabled* Transmit end interrupt (TEI) request enabled * (Initial value) Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0. Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in clocked synchronous mode, and in the case of external clock operation (CKE1 = 1). Note that the SCI’s operating mode must be decided using SMR before setting the CKE1 and CKE0 bits. Rev.6.00 Oct.28.2004 page 474 of 1016 REJ09B0138-0600H For details of clock source selection, see table 14-9 in section 14.3, Operation. Bit 1 CKE1 0 Bit 0 CKE0 0 Description Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode 1 0 Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode Internal clock/SCK pin functions as I/O port * 1 Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output * 2 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input* 3 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input* 3 External clock/SCK pin functions as serial clock input Notes: 1. Initial value 2. Outputs a clock of the same frequency as the bit rate. 3. Inputs a clock with a frequency 16 times the bit rate. 14.2.7 Bit Serial Status Register (SSR) : 7 TDRE 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value : R/W : 1 R/(W)* Note: * Only 0 can be written, to clear the flag. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified. SSR is initialized to H'84 by a reset, and by putting the device in standby mode or module stop mode. Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from TDR to TSR and the next serial data can be written to TDR. Bit 7 TDRE 0 Description [Clearing conditions] • • 1 • • When 0 is written to TDRE after reading TDRE = 1 When the DMAC or DTC is activated by a TXI interrupt and write data to TDR (Initial value) When the TE bit in SCR is 0 When data is transferred from TDR to TSR and data can be written to TDR [Setting conditions] Rev.6.00 Oct.28.2004 page 475 of 1016 REJ09B0138-0600H Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR. Description [Clearing conditions] (Initial value) • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC or DTC is activated by an RXI interrupt and read data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Bit 6 RDRF 0 Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5 ORER 0 Description [Clearing condition] When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1*2 Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. (Initial value)*1 Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4 FER 0 Description [Clearing condition] When 0 is written to FER after reading FER = 1 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 * 2 Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. (Initial value)*1 Rev.6.00 Oct.28.2004 page 476 of 1016 REJ09B0138-0600H Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 3 PER 0 1 Description [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR* 2 (Initial value)*1 Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2 TEND 0 Description [Clearing conditions] • • 1 • • When 0 is written to TDRE after reading TDRE = 1 When the DMAC or DTC is activated by a TXI interrupt and write data to TDR (Initial value) When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Setting conditions] Bit 1—Multiprocessor Bit (MPB): When reception is performed using multiprocessor format in asynchronous mode, MPB stores the multiprocessor bit in the receive data. MPB is a read-only bit, and cannot be modified. Bit 1 MPB 0 1 Description [Clearing condition] When data with a 0 multiprocessor bit is received (Initial value) * [Setting condition] When data with a 1 multiprocessor bit is received Note: * Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor format. Rev.6.00 Oct.28.2004 page 477 of 1016 REJ09B0138-0600H Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when multiprocessor format is not used, when not transmitting, and in clocked synchronous mode. Bit 0 MPBT 0 1 Description Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted (Initial value) 14.2.8 Bit Bit Rate Register (BRR) : 7 6 5 4 3 2 1 0 Initial value : R/W : 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset, and by putting the device in standby mode or module stop mode. In the H8S/2398, H8S/2394, H8S/2392, and H8S/2390, however, the value in BRR is initialized to H'FF by a reset, or in hardware standby mode, but BRR retains its current state when the device enters software standby mode or module stop mode. As baud rate generator control is performed independently for each channel, different values can be set for each channel. Table 14-3 shows sample BRR settings in asynchronous mode, and table 14-4 shows sample BRR settings in clocked synchronous mode. Table 14-3 BRR Settings for Various Bit Rates (Asynchronous Mode) ø = 2 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 — — 0.00 — ø = 2.097152 MHz Error (%) ø = 2.4576 MHz Error (%) ø = 3 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 –2.34 –2.34 –2.34 0.00 — n 1 1 0 0 0 0 0 0 0 0 0 N 141 103 207 103 51 25 12 6 2 1 1 n 1 1 0 0 0 0 0 0 0 0 0 N 148 108 217 108 54 26 13 6 2 1 1 n N 174 127 255 127 63 31 15 7 3 1 1 n N 212 155 77 155 77 38 19 9 4 2 — –0.04 1 0.21 0.21 0.21 1 0 0 –0.26 1 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 — 0.00 1 1 0 0 0 0 0 0 0 — –0.70 0 1.14 0 –2.48 0 –2.48 0 — — — 0 0 0 Rev.6.00 Oct.28.2004 page 478 of 1016 REJ09B0138-0600H ø = 3.6864 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 — 0.00 ø = 4 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 — 0.00 — ø = 4.9152 MHz Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ø = 5 MHz Error (%) –0.25 0.16 0.16 0.16 0.16 0.16 –1.36 1.73 1.73 0.00 1.73 n 2 1 1 0 0 0 0 0 0 — 0 N 64 191 95 191 95 47 23 11 5 — 2 n 2 1 1 0 0 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 6 3 2 n 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 n 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 –1.70 0 0.00 0 ø = 6 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) ø = 6.144 MHz Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 ø = 7.3728 MHz Error (%) ø = 8 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 — n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 n N 108 79 159 79 159 79 39 19 9 5 4 n 2 2 1 1 0 0 0 0 0 0 0 N 130 95 191 95 191 95 47 23 11 6 5 n N 141 103 207 103 207 103 51 25 12 7 6 –0.44 2 0.16 0.16 0.16 0.16 0.16 0.16 2 1 1 0 0 0 –0.07 2 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 — 0.00 2 1 1 0 0 0 0 0 0 0 –2.34 0 –2.34 0 0.00 0 –2.34 0 Rev.6.00 Oct.28.2004 page 479 of 1016 REJ09B0138-0600H ø = 9.8304 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) ø = 10 MHz Error (%) ø = 12 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 ø = 12.288 MHz Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 n N 177 129 64 129 64 129 64 32 15 9 7 n N 212 155 77 155 77 155 77 38 19 11 9 n 2 2 2 1 1 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 –0.26 2 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2 2 1 1 0 0 0 0 –0.25 2 0.16 0.16 0.16 0.16 0.16 0.16 2 2 1 1 0 0 –1.36 0 1.73 0.00 1.73 0 0 0 –2.34 0 0.00 0 –1.70 0 0.00 0 –2.34 0 ø = 14 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) ø = 14.7456 MHz Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ø = 16 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 ø = 17.2032 MHz Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 248 181 90 181 90 181 90 45 22 13 10 n N 64 191 95 191 95 191 95 47 23 14 11 n 3 2 2 1 1 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 n 3 2 2 1 1 0 0 0 0 0 0 N 75 223 111 223 111 223 111 55 27 16 13 –0.17 3 0.16 0.16 0.16 0.16 0.16 0.16 2 2 1 1 0 0 –0.93 0 –0.93 0 0.00 — 0 0 –1.70 0 0.00 0 Rev.6.00 Oct.28.2004 page 480 of 1016 REJ09B0138-0600H ø = 18 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) ø = 19.6608 MHz Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 ø = 20 MHz Error (%) –0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 –1.36 0.00 1.73 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 n N 86 255 127 255 127 255 127 63 31 19 15 n 3 3 2 2 1 1 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 –0.12 3 0.16 0.16 0.16 0.16 0.16 0.16 2 2 1 1 0 0 –0.69 0 1.02 0.00 0 0 –1.70 0 0.00 0 –2.34 0 Table 14-4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Bit Rate (bit/s) 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 5M n 3 2 1 1 0 0 0 0 0 0 0 0 ø = 2 MHz N 70 124 249 124 199 99 49 19 9 4 1 0* 2 2 1 1 0 0 0 0 0 0 0 0 249 124 249 99 199 99 39 19 9 3 1 0* 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* — — — 1 1 0 0 0 0 0 0 — — — 249 124 249 99 49 24 9 4 3 3 2 2 1 1 0 0 0 0 0 0 249 124 249 99 199 99 159 79 39 15 7 3 — — 2 1 1 0 0 0 0 0 0 0 0 — — 124 249 124 199 99 49 19 9 4 1 0* n ø = 4 MHz N n ø = 8 MHz N n ø = 10 MHz N n ø = 16 MHz N n ø = 20 MHz N Legend: Blank: Cannot be set. — : Can be set, but there will be a degree of error. * : Continuous transfer is not possible. Rev.6.00 Oct.28.2004 page 481 of 1016 REJ09B0138-0600H The BRR setting is found from the following formulas. Asynchronous mode: N= ø 64 × 2 2n–1 ×B × 10 6 – 1 Clocked synchronous mode: N= ø 8×2 2n–1 ×B × 10 6 – 1 Where B: N: ø: n: Bit rate (bit/s) BRR setting for baud rate generator (0 ≤ N ≤ 255) Operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SMR Setting n 0 1 2 3 Clock ø ø/4 ø/16 ø/64 CKS1 0 0 1 1 CKS0 0 1 0 1 The bit rate error in asynchronous mode is found from the following formula: Error (%) = { ø × 106 (N + 1) × B × 64 × 22n–1 – 1 } × 100 Rev.6.00 Oct.28.2004 page 482 of 1016 REJ09B0138-0600H Table 14-5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 14-6 and 14-7 show the maximum bit rates with external clock input. Table 14-5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ø (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 Maximum Bit Rate (bit/s) 62500 65536 76800 93750 115200 125000 153600 156250 187500 192000 230400 250000 307200 312500 375000 384000 437500 460800 500000 537600 562500 614400 625000 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev.6.00 Oct.28.2004 page 483 of 1016 REJ09B0138-0600H Table 14-6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ø (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 1.2500 1.5000 1.5360 1.8432 2.0000 2.4576 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 Maximum Bit Rate (bit/s) 31250 32768 38400 46875 57600 62500 76800 78125 93750 96000 115200 125000 153600 156250 187500 192000 218750 230400 250000 268800 281250 307200 312500 Table 14-7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) ø (MHz) 2 4 6 8 10 12 14 16 18 20 External Input Clock (MHz) 0.3333 0.6667 1.0000 1.3333 1.6667 2.0000 2.3333 2.6667 3.0000 3.3333 Maximum Bit Rate (bit/s) 333333.3 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3 Rev.6.00 Oct.28.2004 page 484 of 1016 REJ09B0138-0600H 14.2.9 Bit Smart Card Mode Register (SCMR) : 7 — 6 — 1 — 5 — 1 — 4 — 1 — 3 SDIR 0 R/W 2 SINV 0 R/W 1 — 1 — 0 SMIF 0 R/W Initial value : R/W : 1 — SCMR selects LSB-first or MSB-first by means of bit SDIR. Except in the case of asynchronous mode 7-bit data, LSBfirst or MSB-first can be selected regardless of the serial communication mode. The descriptions in this chapter refer to LSB-first transfer. For details of the other bits in SCMR, see section 15.2.1, Smart Card Mode Register (SCMR). SCMR is initialized to H'F2 by a reset, and by putting the device in standby mode or module stop mode. In the H8S/2398, H8S/2394, H8S/2392, and H8S/2390, however, the value in SCMR is initialized to H'F2 by a reset, or in hardware standby mode, but SCMR retains its current state when the device enters software standby mode or module stop mode. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1. Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. This bit is valid when 8-bit data is used as the transmit/receive format. Bit 3 SDIR 0 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) Bit 2—Smart Card Data Invert (SINV): When the Smart Card interface operates as a normal SCI, 0 should be written to this bit. Bit 1—Reserved: This bit cannot be modified always read as 1. Bit 0—Smart Card Interface Mode Select (SMIF): When the Smart Card interface operates as a normal SCI, 0 should be written to this bit. Rev.6.00 Oct.28.2004 page 485 of 1016 REJ09B0138-0600H 14.2.10 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 9 8 7 6 5 4 3 2 1 0 Bit : 15 14 13 12 11 Initial value : R/W 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the corresponding bit of bits MSTP7 to MSTP5 is set to 1, SCI operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Module Stop (MSTP7): Specifies the SCI channel 2 module stop mode. Bit 7 MSTP7 0 1 Description SCI channel 2 module stop mode cleared SCI channel 2 module stop mode set (Initial value) Bit 6—Module Stop (MSTP6): Specifies the SCI channel 1 module stop mode. Bit 6 MSTP6 0 1 Description SCI channel 1 module stop mode cleared SCI channel 1 module stop mode set (Initial value) Bit 5—Module Stop (MSTP5): Specifies the SCI channel 0 module stop mode. Bit 5 MSTP5 0 1 Description SCI channel 0 module stop mode cleared SCI channel 0 module stop mode set (Initial value) Rev.6.00 Oct.28.2004 page 486 of 1016 REJ09B0138-0600H 14.3 14.3.1 Operation Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and clocked synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or clocked synchronous mode and the transmission format is made using SMR as shown in table 14-8. The SCI clock is determined by a combination of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 14-9. Asynchronous Mode • Data length: Choice of 7 or 8 bits • Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) • Detection of framing, parity, and overrun errors, and breaks, during reception • Choice of internal or external clock as SCI clock source  When internal clock is selected: The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output  When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used) Clocked Synchronous Mode • Transfer format: Fixed 8-bit data • Detection of overrun errors during reception • Choice of internal or external clock as SCI clock source  When internal clock is selected: The SCI operates on the baud rate generator clock and a serial clock is output off-chip  When external clock is selected: The on-chip baud rate generator is not used, and the SCI operates on the input serial clock Rev.6.00 Oct.28.2004 page 487 of 1016 REJ09B0138-0600H Table 14-8 SMR Settings and Serial Transfer Format Selection SMR Settings Bit 7 C/A 0 Bit 6 CHR 0 Bit 2 MP 0 Bit 5 PE 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 0 1 — — 1 — — 1 — — — 0 1 0 1 — Clocked 8-bit data synchronous mode No Asynchronous mode (multiprocessor format) 8-bit data Yes No Yes 7-bit data No Mode Asynchronous mode Yes Data Length 8-bit data SCI Transfer Format Multi Processor Bit No Parity Bit No Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 7-bit data 1 bit 2 bits None Table 14-9 SMR and SCR Settings and SCI Clock Source Selection SMR SCR Setting Bit 7 C/A 0 CKE1 0 CKE0 0 1 1 0 1 1 0 0 1 1 0 1 Clocked synchronous mode Internal Bit 1 Mode Asynchronous mode Bit 0 Source Internal SCI Transmit/Receive Clock Clock SCK Pin Function SCI does not use SCK pin Outputs clock with same frequency as bit rate External Inputs clock with frequency of 16 times the bit rate Outputs serial clock External Inputs serial clock Rev.6.00 Oct.28.2004 page 488 of 1016 REJ09B0138-0600H 14.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 14-2 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 Parity bit 1 bit, or none 1 1 1 Stop bit Transmit/receive data 7 or 8 bits 1 or 2 bits One unit of transfer data (character or frame) Figure 14-2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Data Transfer Format: Table 14-10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. Rev.6.00 Oct.28.2004 page 489 of 1016 REJ09B0138-0600H Table 14-10 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 — — — — MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S Serial Transfer Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data STOP S STOP STOP S P STOP S P STOP STOP S S STOP STOP S P STOP S P STOP STOP S MPB STOP S MPB STOP STOP S MPB STOP S MPB STOP STOP Legend: S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Rev.6.00 Oct.28.2004 page 490 of 1016 REJ09B0138-0600H Clock: Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 14-9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 14-3. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 14-3 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Data Transfer Operations: • SCI initialization (asynchronous mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain. Rev.6.00 Oct.28.2004 page 491 of 1016 REJ09B0138-0600H Figure 14-4 shows a sample SCI initialization flowchart. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [4] Start initialization Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits Figure 14-4 Sample SCI Initialization Flowchart Rev.6.00 Oct.28.2004 page 492 of 1016 REJ09B0138-0600H • Serial data transmission (asynchronous mode) Figure 14-5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. Initialization Start transmission [1] Read TDRE flag in SSR [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. No TDRE=1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND= 1 Yes No Break output? Yes Clear DR to 0 and set DDR to 1 [4] Clear TE bit in SCR to 0 Figure 14-5 Sample Serial Transmission Flowchart In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. Rev.6.00 Oct.28.2004 page 493 of 1016 REJ09B0138-0600H [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. A format in which neither a parity bit nor a multiprocessor bit is output can also be selected. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark state” is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 14-6 shows an example of the operation for transmission in asynchronous mode. 1 Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and request generated TDRE flag cleared to 0 in TXI interrupt service routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 14-6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev.6.00 Oct.28.2004 page 494 of 1016 REJ09B0138-0600H • Serial data reception (asynchronous mode) Figure 14-7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Initialization Start reception [1] [2] [3] Receive error processing and break detection: Read ORER, PER, and If a receive error occurs, read the [2] FER flags in SSR ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error Yes processing, ensure that the PER∨FER∨ORER= 1 ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot No Error processing be resumed if any of these flags (Continued on next page) are set to 1. In the case of a framing error, a break can be detected by reading the value of [4] Read RDRF flag in SSR the input port corresponding to the RxD pin. No RDRF= 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] SCI status check and receive data read : Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] No All data received? Yes Clear RE bit in SCR to 0 [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. The RDRF flag is cleared automatically when the DMAC or DTC is activated by an RXI interrupt and the RDR value is read. Figure 14-7 Sample Serial Reception Data Flowchart Rev.6.00 Oct.28.2004 page 495 of 1016 REJ09B0138-0600H [3] Error processing No ORER= 1 Yes Overrun error processing No FER= 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 No PER= 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 14-7 Sample Serial Reception Data Flowchart (cont) Rev.6.00 Oct.28.2004 page 496 of 1016 REJ09B0138-0600H In serial reception, the SCI operates as described below. [1] The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. [a] Parity check: The SCI checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the O/E bit in SMR. [b] Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. [c] Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from RSR to RDR. If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error* is detected in the error check, the operation is as shown in table 14-11. Note: * Subsequent receive operations cannot be performed when a receive error has occurred. Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0. [4] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive error interrupt (ERI) request is generated. Rev.6.00 Oct.28.2004 page 497 of 1016 REJ09B0138-0600H Table 14-11 Receive Errors and Conditions for Occurrence Receive Error Overrun error Abbreviation ORER Occurrence Condition Data Transfer When the next data reception is Receive data is not completed while the RDRF flag transferred from RSR to in SSR is set to 1 RDR. When the stop bit is 0 Receive data is transferred from RSR to RDR. Framing error Parity error FER PER When the received data differs Receive data is transferred from the parity (even or odd) set from RSR to RDR. in SMR Figure 14-8 shows an example of the operation for reception in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ERI interrupt request generated by framing error 1 frame Figure 14-8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) Rev.6.00 Oct.28.2004 page 498 of 1016 REJ09B0138-0600H 14.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing transmission lines. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station , and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips the data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this way, data communication is carried out among a number of processors. Figure 14-9 shows an example of inter-processor communication using the multiprocessor format. Data Transfer Format: There are four data transfer formats. When the multiprocessor format is specified, the parity bit specification is invalid. For details, see table 14-10. Clock: See the section on asynchronous mode. Transmitting station Serial transmission line Receiving station A (ID= 01) Serial data Receiving station B (ID= 02) Receiving station C (ID= 03) Receiving station D (ID= 04) H'01 (MPB= 1) ID transmission cycle= receiving station specification H'AA (MPB= 0) Data transmission cycle= Data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 14-9 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Rev.6.00 Oct.28.2004 page 499 of 1016 REJ09B0138-0600H Data Transfer Operations: • Multiprocessor serial data transmission Figure 14-10 shows a sample flowchart for multiprocessor serial data transmission. The following procedure should be used for multiprocessor serial data transmission. Initialization Start transmission [1] [1] SCI initialization: Read TDRE flag in SSR [2] The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. No TDRE= 1 Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No TEND= 1 Yes No Break output? Yes [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is [3] possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to [4] 1, clear DR to 0, then clear the TE bit in SCR to 0. Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 Figure 14-10 Sample Multiprocessor Serial Transmission Flowchart Rev.6.00 Oct.28.2004 page 500 of 1016 REJ09B0138-0600H In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Multiprocessor bit One multiprocessor bit (MPBT value) is output. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a transmission end interrupt (TEI) request is generated. Figure 14-11 shows an example of SCI operation for transmission using the multiprocessor format. Multiprocessor Stop bit bit D7 0/1 1 1 Start bit 0 D0 D1 Data Start bit 0 D0 D1 Data D7 Multiproces- Stop 1 sor bit bit 0/1 1 Idle state (mark state) TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine 1 frame TXI interrupt request generated TEI interrupt request generated Figure 14-11 Example of SCI Operation in Transmission (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev.6.00 Oct.28.2004 page 501 of 1016 REJ09B0138-0600H • Multiprocessor serial data reception Figure 14-12 shows a sample flowchart for multiprocessor serial reception. The following procedure should be used for multiprocessor serial data reception. Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID. If the data is not this station’s ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station’s ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. Read MPIE bit in SCR Read ORER and FER flags in SSR FER∨ORER= 1 No Read RDRF flag in SSR No RDRF= 1 Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR [2] Yes [3] FER∨ORER= 1 No Read RDRF flag in SSR Yes [4] No RDRF= 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error processing (Continued on next page) Figure 14-12 Sample Multiprocessor Serial Reception Flowchart Rev.6.00 Oct.28.2004 page 502 of 1016 REJ09B0138-0600H [5] Error processing No ORER= 1 Yes Overrun error processing No FER= 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 14-12 Sample Multiprocessor Serial Reception Flowchart (cont) Rev.6.00 Oct.28.2004 page 503 of 1016 REJ09B0138-0600H Figure 14-13 shows an example of SCI operation for multiprocessor format reception. Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 D1 Data (Data1) MPB D7 0 Stop bit 1 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ID1 If not this station’s ID, RXI interrupt request is MPIE bit is set to 1 not generated, and RDR again retains its state (a) Data does not match station’s ID 1 Start bit 0 D0 D1 Data (ID2) MPB D7 1 Stop bit 1 Start bit 0 D0 Data (Data2) MPB D1 D7 0 Stop bit 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ID2 Matches this station’s ID, so reception continues, and data is received in RXI interrupt service routine Data2 MPIE bit set to 1 again (b) Data matches station’s ID Figure 14-13 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev.6.00 Oct.28.2004 page 504 of 1016 REJ09B0138-0600H 14.3.4 Operation in Clocked Synchronous Mode In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 14-14 shows the general format for clocked synchronous serial communication. One unit of transfer data (character or frame) * Serial clock LSB Serial data Don’t care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don’t care * Figure 14-14 Data Format in Synchronous Communication In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial clock. In clocked serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the transmission line holds the MSB state. In clocked synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock. Data Transfer Format: A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock: Either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 14-9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When only receive operations are performed, however, the serial clock is output until an overrun error occurs or the RE bit is cleared to 0. If you want to perform receive operations in units of one character, you should select an external clock as the clock source. Rev.6.00 Oct.28.2004 page 505 of 1016 REJ09B0138-0600H Data Transfer Operations: • SCI initialization (clocked synchronous mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. Figure 14-15 shows a sample SCI initialization flowchart. Start initialization [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. [2] Set the data transfer format in SMR and SCMR. Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Set data transfer format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 14-15 Sample SCI Initialization Flowchart Rev.6.00 Oct.28.2004 page 506 of 1016 REJ09B0138-0600H • Serial data transmission (clocked synchronous mode) Figure 14-16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. Initialization Start transmission [1] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Read TDRE flag in SSR [2] No TDRE= 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND= 1 Yes Clear TE bit in SCR to 0 Figure 14-16 Sample Serial Transmission Flowchart Rev.6.00 Oct.28.2004 page 507 of 1016 REJ09B0138-0600H In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been specified, data is output synchronized with the input clock. The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with the MSB (bit 7). [3] The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the TxD pin maintains its state. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. [4] After completion of serial transmission, the SCK pin is fixed. Figure 14-17 shows an example of SCI operation in transmission. Transfer direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt Data written to TDR request generated and TDRE flag cleared to 0 in TXI interrupt service routine 1 frame TXI interrupt request generated TEI interrupt request generated Figure 14-17 Example of SCI Operation in Transmission Rev.6.00 Oct.28.2004 page 508 of 1016 REJ09B0138-0600H • Serial data reception (clocked synchronous mode) Figure 14-18 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to clocked synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible. [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Initialization Start reception [1] Read ORER flag in SSR Yes ORER= 1 No [2] [3] Error processing (Continued below) [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. The RDRF flag is cleared automatically when the DMAC or DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read. Read RDRF flag in SSR [4] No RDRF= 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [3] [5] Error processing Overrun error processing Clear ORER flag in SSR to 0 Figure 14-18 Sample Serial Reception Flowchart Rev.6.00 Oct.28.2004 page 509 of 1016 REJ09B0138-0600H In serial reception, the SCI operates as described below. [1] The SCI performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error is detected in the error check, the operation is as shown in table 14-11. Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. [3] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive error interrupt (ERI) request is generated. Figure 14-19 shows an example of SCI operation in reception. Serial clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 14-19 Example of SCI Operation in Reception Rev.6.00 Oct.28.2004 page 510 of 1016 REJ09B0138-0600H • Simultaneous serial data transmission and reception (clocked synchronous mode) Figure 14-20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Initialization Start transmission/reception [1] Read TDRE flag in SSR No TDRE= 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error processing: Read ORER flag in SSR Yes [3] Error processing ORER= 1 No If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Read RDRF flag in SSR No RDRF= 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DMAC or DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read. No All data received? Yes [5] Clear TE and RE bits in SCR to 0 Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE and RE bits to 0, then set both these bits to 1 simultaneously. Figure 14-20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations Rev.6.00 Oct.28.2004 page 511 of 1016 REJ09B0138-0600H 14.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receivedata-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 14-12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of interrupt request is sent to the interrupt controller independently. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DMAC or DTC to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is performed by the DMAC or DTC. The DMAC and DTC cannot be activated by a TEI interrupt request. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DMAC or DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC or DTC. The DMAC and DTC cannot be activated by an ERI interrupt request. Also note that the DMAC cannot be activated by an SCI channel 2 interrupt. Rev.6.00 Oct.28.2004 page 512 of 1016 REJ09B0138-0600H Table 14-12 SCI Interrupt Sources Channel 0 Interrupt Source Description ERI RXI TXI TEI 1 ERI RXI TXI TEI 2 ERI RXI TXI TEI Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) DTC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible DMAC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Not possible Not possible Not possible Low Priority * High Note: * This table shows the initial state immediately after a reset. Relative priorities among channels can be changed by means of ICR and IPR. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt may be accepted first, with the result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be accepted in this case. Rev.6.00 Oct.28.2004 page 513 of 1016 REJ09B0138-0600H 14.5 Usage Notes The following points should be noted when using the SCI. Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to TDR. Operation when Multiple Receive Errors Occur Simultaneously If a number of receive errors occur at the same time, the state of the status flags in SSR is as shown in table 14-13. If there is an overrun error, data is not transferred from RSR to RDR, and the receive data is lost. Table 14-13 State of SSR Status Flags and Transfer of Receive Data SSR Status Flags RDRF 1 0 0 1 1 0 1 Notes: ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 × × × RSR to RDR × Receive Data Transfer Receive Error Status Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error : Receive data is transferred from RSR to RDR. ×: Receive data is not transferred from RSR to RDR. Rev.6.00 Oct.28.2004 page 514 of 1016 REJ09B0138-0600H Break Detection and Processing (Asynchronous Mode Only): When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. Sending a Break (Asynchronous Mode Only): The TxD pin has a dual function as an I/O port whose direction (input or output) is determined by DR and DDR. This can be used to send a break. Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced by the value of DR (the pin does not function as the TxD pin until the TE bit is set to 1). Consequently, DDR and DR for the port corresponding to the TxD pin are first set to 1. To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only): Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Receive Data Sampling Timing and Reception Margin in Asynchronous Mode: In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock. This is illustrated in figure 14-21. 16 clocks 8 clocks 0 Internal basic clock 7 15 0 7 15 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 14-21 Receive Data Sampling Timing in Asynchronous Mode Thus the reception margin in asynchronous mode is given by formula (1) below. M = | (0.5 – 1 2N ) – (L – 0.5) F – | D – 0.5 | N ... Formula (1) Rev.6.00 Oct.28.2004 page 515 of 1016 REJ09B0138-0600H (1 + F) | × 100% Where M N D L F : Reception margin (%) : Ratio of bit rate to clock (N = 16) : Clock duty (D = 0 to 1.0) : Frame length (L = 9 to 12) : Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by formula (2) below. When D = 0.5 and F = 0, M = (0.5 – 1 2 × 16 ) × 100% = 46.875% ... Formula (2) However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. Restrictions on Use of DMAC or DTC • When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 ø clock cycles after TDR is updated by the DMAC or DTC. Misoperation may occur if the transmit clock is input within 4 ø clocks after TDR is updated. (Figure 14-22) • When RDR is read by the DMAC or DTC, be sure to set the activation source to the relevant SCI reception data full interrupt (RXI). SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When operating on an external clock, set t >4 clocks. Figure 14-22 Example of Clocked Synchronous Transmission by DTC Operation before mode transition (for the H8S/2398, H8S/2394, H8S/2392, and H8S/2390) Before a mode transition to module stop mode or software standby mode, SCR should be initialized first, then SMR, BRR, and SCMR should be initialized. Rev.6.00 Oct.28.2004 page 516 of 1016 REJ09B0138-0600H Section 15 Smart Card Interface 15.1 Overview SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 15.1.1 Features Features of the Smart Card interface supported by the H8S/2357 Group are as follows. • Asynchronous mode  Data length: 8 bits  Parity bit generation and checking  Transmission of error signal (parity error) in receive mode  Error signal detection and automatic data retransmission in transmit mode  Direct convention and inverse convention both supported • On-chip baud rate generator allows any bit rate to be selected • Three interrupt sources  Three interrupt sources (transmit data empty, receive data full, and transmit/receive error) that can issue requests independently  The transmit data empty interrupt and receive data full interrupt can activate the DMA controller (DMAC) or data transfer controller (DTC) to execute data transfer Rev.6.00 Oct.28.2004 page 517 of 1016 REJ09B0138-0600H 15.1.2 Block Diagram Figure 15-1 shows a block diagram of the Smart Card interface. Bus interface Module data bus Internal data bus RDR TDR RxD RSR TSR SCMR SSR SCR SMR Transmission/ reception control BRR ø Baud rate generator ø/4 ø/16 ø/64 Clock TxD Parity generation Parity check SCK TXI RXI ERI Smart Card mode register Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Legend: SCMR: RSR: RDR: TSR: TDR: SMR: SCR: SSR: BRR: Figure 15-1 Block Diagram of Smart Card Interface 15.1.3 Pin Configuration Table 15-1 shows the Smart Card interface pin configuration. Table 15-1 Smart Card Interface Pins Channel 0 Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 1 Serial clock pin 1 Receive data pin 1 Transmit data pin 1 2 Serial clock pin 2 Receive data pin 2 Transmit data pin 2 Symbol SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 SCK2 RxD2 TxD2 I/O I/O Input Output I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output Rev.6.00 Oct.28.2004 page 518 of 1016 REJ09B0138-0600H 15.1.4 Register Configuration Table 15-2 shows the registers used by the Smart Card interface. Details of SMR, BRR, SCR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 14, Serial Communication Interface (SCI). Table 15-2 Smart Card Interface Registers Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Smart Card mode register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Smart Card mode register 1 2 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit data register 2 Serial status register 2 Receive data register 2 Smart Card mode register 2 All Module stop control register Abbreviation SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 SMR2 BRR2 SCR2 TDR2 SSR2 RDR2 SCMR2 MSTPCR R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W 2 2 2 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'3FFF Address* 1 H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF3C Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. Rev.6.00 Oct.28.2004 page 519 of 1016 REJ09B0138-0600H 15.2 Register Descriptions Registers added with the Smart Card interface and bits for which the function changes are described here. 15.2.1 Bit Smart Card Mode Register (SCMR) : 7 — 6 — 1 — 5 — 1 — 4 — 1 — 3 SDIR 0 R/W 2 SINV 0 R/W 1 — 1 — 0 SMIF 0 R/W Initial value : R/W : 1 — SCMR is an 8-bit readable/writable register that selects the Smart Card interface function. SCMR is initialized to H'F2 by a reset, and in standby mode or module stop mode. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1. Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3 SDIR 0 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the SDIR bit for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 15.3.4, Register Settings. Bit 2 SINV 0 Description TDR contents are transmitted as they are Receive data is stored as it is in RDR 1 TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR (Initial value) Bit 1—Reserved: This bit cannot be modified and is always read as 1. Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the Smart Card interface function. Bit 0 SMIF 0 1 Description Smart Card interface function is disabled Smart Card interface function is enabled (Initial value) Rev.6.00 Oct.28.2004 page 520 of 1016 REJ09B0138-0600H 15.2.2 Bit Serial Status Register (SSR) : 7 TDRE 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value : R/W : 1 R/(W)* Note: * Only 0 can be written to bits 7 to 3, to clear these flags. Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting conditions for bit 2, TEND, are also different. Bits 7 to 5—Operate in the same way as for the normal SCI. For details, see section 14.2.7, Serial Status Register (SSR). Bit 4—Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the error signal sent back from the receiving end in transmission. Framing errors are not detected in Smart Card interface mode. Bit 4 ERS 0 Description [Clearing conditions] • • 1 Upon reset, and in standby mode or module stop mode When 0 is written to ERS after reading ERS = 1 (Initial value) [Setting condition] When the low level of the error signal is sampled Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state. Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 14.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit, are as shown below. Bit 2 TEND 0 Description [Clearing conditions] • • 1 • • • • When 0 is written to TDRE after reading TDRE = 1 When the DMAC or DTC is activated by a TXI interrupt and write data to TDR (Initial value) [Setting conditions] Upon reset, and in standby mode or module stop mode When the TE bit in SCR is 0 and the ERS bit is also 0 When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when GM = 0 When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit) Rev.6.00 Oct.28.2004 page 521 of 1016 REJ09B0138-0600H 15.2.3 Bit Serial Mode Register (SMR) : 7 GM 6 CHR 0 0 R/W 5 PE 0 1 R/W 4 O/ E 0 O/ E R/W 3 STOP 0 1 R/W 2 MP 0 0 R/W 1 CKS1 0 CKS1 R/W 0 CKS0 0 CKS0 R/W Initial value : Set value * : R/W : 0 GM R/W Note: * When the Smart Card interface is used, be sure to make the 0 or 1 setting shown for bits 6, 5, 3, and 2. The function of bit 7 of SMR changes in Smart Card interface mode. Bit 7—GSM Mode (GM): Sets the Smart Card interface function to GSM mode. This bit is cleared to 0 when the normal Smart Card interface is used. In GSM mode, this bit is set to 1, the timing of setting of the TEND flag that indicates transmission completion is advanced and clock output control mode addition is performed. The contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control register (SCR). Bit 7 GM 0 Description Normal Smart Card interface mode operation • • 1 • • TEND flag generation 12.5 etu after beginning of start bit Clock output ON/OFF control only (Initial value) GSM mode Smart Card interface mode operation TEND flag generation 11.0 etu after beginning of start bit High/low fixing control possible in addition to clock output ON/OFF control (set by SCR) Note: etu: Elementary time unit (time for transfer of 1 bit) Bits 6 to 0—Operate in the same way as for the normal SCI. For details, see section 14.2.5, Serial Mode Register (SMR). Rev.6.00 Oct.28.2004 page 522 of 1016 REJ09B0138-0600H 15.2.4 Bit Serial Control Register (SCR) : 7 TIE 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value : R/W : 0 R/W In Smart Card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1. Bits 7 to 2—Operate in the same way as for the normal SCI. For details, see section 14.2.6, Serial Control Register (SCR). Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. In Smart Card interface mode, in addition to the normal switching between clock output enabling and disabling, the clock output can be specified as to be fixed high or low. SCMR SMIF 0 1 1 1 1 1 1 SMR C/A, GM See the SCI 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 1 0 1 Operates as port I/O pin Outputs clock as SCK output pin Operates as SCK output pin, with output fixed low Outputs clock as SCK output pin Operates as SCK output pin, with output fixed high Outputs clock as SCK output pin SCR Setting CKE1 CKE0 SCK Pin Function Rev.6.00 Oct.28.2004 page 523 of 1016 REJ09B0138-0600H 15.3 15.3.1 Operation Overview The main functions of the Smart Card interface are as follows. • • • • • One frame consists of 8-bit data plus a parity bit. In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of 1 bit) is left between the end of the parity bit and the start of the next frame. If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. If the error signal is sampled during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. Only asynchronous communication is supported; there is no clocked synchronous communication function. Pin Connections 15.3.2 Figure 15-2 shows a schematic diagram of Smart Card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected with the LSI pin. The data transmission line should be pulled up to the VCC power supply with a resistor. When the clock generated on the Smart Card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock. LSI port output is used as the reset signal. Other pins must normally be connected to the power supply or ground. VCC TxD I/O RxD SCK Rx (port) H8S/2357 Group Connected equipment Data line Clock line Reset line CLK RST IC card Figure 15-2 Schematic Diagram of Smart Card Interface Pin Connections Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. Rev.6.00 Oct.28.2004 page 524 of 1016 REJ09B0138-0600H 15.3.3 Data Format Figure 15-3 shows the Smart Card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. If an error signal is sampled during transmission, the same data is retransmitted. When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Transmitting station output Legend: Ds: Start bit D0 to D7: Data bits Dp: Parity bit DE: Error signal Receiving station output Figure 15-3 Smart Card Interface Data Format The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pull-up resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the Smart Card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. [4] The receiving station carries out a parity check. If there is no parity error and the data is received normally, the receiving station waits for reception of the next data. If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. [5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. If it does receive an error signal, however, it returns to step [2] and retransmits the erroneous data. Rev.6.00 Oct.28.2004 page 525 of 1016 REJ09B0138-0600H 15.3.4 Register Settings Table 15-3 shows a bit map of the registers used by the Smart Card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 15-3 Smart Card Interface Register Settings Bit Register SMR BRR SCR TDR SSR RDR SCMR Bit 7 GM BRR7 TIE TDR7 TDRE RDR7 — Bit 6 0 BRR6 RIE TDR6 RDRF RDR6 — Bit 5 1 BRR5 TE TDR5 ORER RDR5 — Bit 4 O/ E BRR4 RE TDR4 ERS RDR4 — Bit 3 1 BRR3 0 TDR3 PER RDR3 SDIR Bit 2 0 BRR2 0 TDR2 TEND RDR2 SINV Bit 1 CKS1 BRR1 CKE1 * TDR1 0 RDR1 — Bit 0 CKS0 BRR0 CKE0 TDR0 0 RDR0 SMIF Notes: — : Not used. * The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0. SMR Setting: The GM bit is cleared to 0 in normal Smart Card interface mode, and set to 1 in GSM mode. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section 15.3.5, Clock. BRR Setting: BRR is used to set the bit rate. See section 15.3.5, Clock, for the method of calculating the value to be set. SCR Setting: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI. For details, see section 14, Serial Communication Interface (SCI). Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in SMR is set to 1, clock output is performed. The clock output can also be fixed high or low. Smart Card Mode Register (SCMR) Setting: The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SMIF bit is set to 1 in the case of the Smart Card interface. Examples of register settings and the waveform of the start character are shown below for the two types of IC card (direct convention and inverse convention). Rev.6.00 Oct.28.2004 page 526 of 1016 REJ09B0138-0600H • Direct convention (SDIR = SINV = O/E = 0) (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. The parity bit is 1 since even parity is stipulated for the Smart Card. • Inverse convention (SDIR = SINV = O/ E = 1) (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. The parity bit is 0, corresponding to state Z, since even parity is stipulated for the Smart Card. With the H8S/2357 Group, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR is set to odd parity mode (the same applies to both transmission and reception). 15.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the Smart Card interface. The bit rate is set with BRR and the CKS1 and CKS0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 15-5 shows some sample bit rates. If clock output is selected by setting CKE0 to 1, a clock with a frequency of 372 times the bit rate is output from the SCK pin. B= ø 1488 × 2 2n–1 × (N + 1) × 10 6 Where: N = Value set in BRR (0 ≤ N ≤ 255) B = Bit rate (bit/s) ø = Operating frequency (MHz) n = See table 15-4 Table 15-4 Correspondence between n and CKS1, CKS0 n 0 1 2 3 1 CKS1 0 CKS0 0 1 0 1 Rev.6.00 Oct.28.2004 page 527 of 1016 REJ09B0138-0600H Table 15-5 Examples of Bit Rate B (bit/s) for Various BRR Settings (When n = 0) ø (MHz) N 0 1 2 10.00 13441 6720 4480 10.714 14400 7200 4800 13.00 17473 8737 5824 14.285 19200 9600 6400 16.00 21505 10753 7168 18.00 24194 12097 8065 20.00 26882 13441 8961 Note: Bit rates are rounded to the nearest whole number. The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 ≤ N ≤ 255, and the smaller error is specified. N= ø 1488 × 2 2n–1 ×B × 10 6 – 1 Table 15-6 Examples of BRR Settings for Bit Rate B (bit/s) (When n = 0) ø (MHz) 7.1424 bit/s 9600 N Error 0 0.00 10.00 N Error 1 30 10.7136 N Error 1 25 13.00 N Error 1 8.99 14.2848 N Error 1 0.00 16.00 N Error 1 18.00 N Error 20.00 N Error 6.60 12.01 2 15.99 2 Table 15-7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) ø (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 Maximum Bit Rate (bit/s) 9600 13441 14400 17473 19200 21505 24194 26882 N 0 0 0 0 0 0 0 0 n 0 0 0 0 0 0 0 0 The bit rate error is given by the following formula: Error (%) = ( ø 1488 × 2 2n–1 × B × (N + 1) × 106 – 1) × 100 Rev.6.00 Oct.28.2004 page 528 of 1016 REJ09B0138-0600H 15.3.6 Data Transfer Operations Initialization: Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0. [3] Set the O/E bit and CKS1 and CKS0 bits in SMR. Clear the C/A, CHR, and MP bits to 0, and set the STOP and PE bits to 1. [4] Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. [5] Set the value corresponding to the bit rate in BRR. [6] Set the CKE0 bit in SCR. Clear the TIE, RIE, TE, RE, MPIE, TEIE and CKE1 bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. [7] Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. Serial Data Transmission: As data transmission in Smart Card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 15-4 shows a flowchart for transmitting, and figure 15-5 shows the relation between a transmit operation and the internal registers. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ERS error flag in SSR is cleared to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the TEND flag in SSR is set to 1. [4] Write the transmit data to TDR, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. [5] When transmitting data continuously, go back to step [2]. [6] To end transmission, clear the TE bit to 0. With the above processing, interrupt servicing or data transfer by the DMAC or DTC is possible. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit data empty interrupt (TXI) request will be generated. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transfer error interrupt (ERI) request will be generated. The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag set timing is shown in figure 15-6. If the DMAC or DTC is activated by a TXI request, the number of bytes set in the DMAC or DTC can be transmitted automatically, including automatic retransmission. For details, see Interrupt Operations and Data Transfer Operation by DMAC or DTC below. Rev.6.00 Oct.28.2004 page 529 of 1016 REJ09B0138-0600H Start Initialization Start transmission ERS=0? Yes No Error processing No TEND=1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS=0? Yes Error processing No TEND=1? Yes Clear TE bit to 0 End Figure 15-4 Example of Transmission Processing Flow Rev.6.00 Oct.28.2004 page 530 of 1016 REJ09B0138-0600H TDR (1) Data write (2) Transfer from TDR to TSR (3) Serial data output Data 1 Data 1 Data 1 TSR (shift register) Data 1 ; Data remains in TDR Data 1 I/O signal line output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has been completed. Figure 15-5 Relation Between Transmit Operation and Internal Registers I/O data TXI (TEND interrupt) When GM = 0 Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Guard time 12.5 etu When GM = 1 11.0 etu Legend: Ds: Start bit D0 to D7: Data bits Dp: Parity bit DE: Error signal Note: etu: Elementary time unit (time for transfer of 1 bit) Figure 15-6 TEND Flag Generation Timing in Transmission Operation Rev.6.00 Oct.28.2004 page 531 of 1016 REJ09B0138-0600H Serial Data Reception: Data reception in Smart Card mode uses the same processing procedure as for the normal SCI. Figure 15-7 shows an example of the transmission processing flow. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either is set, perform the appropriate receive error processing, then clear both the ORER and the PER flag to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the RDRF flag is set to 1. [4] Read the receive data from RDR. [5] When receiving data continuously, clear the RDRF flag to 0 and go back to step [2]. [6] To end reception, clear the RE bit to 0. Start Initialization Start reception ORER = 0 and PER = 0 Yes No Error processing No RDRF=1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 15-7 Example of Reception Processing Flow With the above processing, interrupt servicing or data transfer by the DMAC or DTC is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transfer error interrupt (ERI) request will be generated. If the DMAC or DTC is activated by an RXI request, the receive data in which the error occurred is skipped, and only the number of bytes of receive data set in the DMAC or DTC are transferred. For details, see Interrupt Operation and Data Transfer Operation by DMAC or DTC below. Rev.6.00 Oct.28.2004 page 532 of 1016 REJ09B0138-0600H If a parity error occurs during reception and the PER is set to 1, the received data is still transferred to RDR, and therefore this data can be read. Mode Switching Operation: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE bit to 0 and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE bit to 0 and setting RE bit to 1. The TEND flag can be used to check that the transmit operation has been completed. Fixing Clock Output Level: When the GSM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 15-8 shows the timing for fixing the clock output level. In this example, GSM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled. Specified pulse width Specified pulse width SCK SCR write (CKE0 = 0) SCR write (CKE0 = 1) Figure 15-8 Timing for Fixing Clock Output Level Interrupt Operation: There are three interrupt sources in Smart Card interface mode: transmit data empty interrupt (TXI) requests, transfer error interrupt (ERI) requests, and receive data full interrupt (RXI) requests. The transmit end interrupt (TEI) request is not used in this mode. When the TEND flag in SSR is set to 1, a TXI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated. The relationship between the operating states and interrupt sources is shown in table 15-8. Table 15-8 Smart Card Mode Operating States and Interrupt Sources Operating State Transmit Mode Normal operation Error Receive Mode Normal operation Error Flag TEND ERS RDRF PER, ORER Enable Bit TIE RIE RIE RIE Interrupt DMAC Source Activation TXI ERI RXI ERI Possible DTC Activation Possible Not possible Not possible Possible Possible Not possible Not possible Data Transfer Operation by DMAC or DTC: In Smart Card mode, as with the normal SCI, transfer can be carried out using the DMAC or DTC. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DMAC or DTC activation source, the DMAC or DTC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE Rev.6.00 Oct.28.2004 page 533 of 1016 REJ09B0138-0600H and TEND flags are automatically cleared to 0 when data transfer is performed by the DMAC or DTC. In the event of an error, the SCI retransmits the same data automatically. The TEND flag remains cleared to 0 during this time, and the DMAC is not activated. Thus, the number of bytes specified by the SCI and DMAC are transmitted automatically even in retransmission following an error. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. When performing transfer using the DMAC or DTC, it is essential to set and enable the DMAC or DTC before carrying out SCI setting. For details of the DMAC and DTC setting procedures, see section 7, DMA Controller, and section 8, Data Transfer Controller. In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DMAC or DTC activation source, the DMAC or DTC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC or DTC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DMAC or DTC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared. 15.3.7 Operation in GSM Mode Switching the Mode: When switching between Smart Card interface mode and software standby mode, the following switching procedure should be followed in order to maintain the clock duty. • When changing from Smart Card interface mode to software standby mode [1] Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. [2] Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. [3] Write 0 to the CKE0 bit in SCR to halt the clock. [4] Wait for one serial clock period. During this interval, clock output is fixed at the specified level, with the duty preserved. [5] Write H'00 to SMR and SCMR. [6] Make the transition to the software standby state. • When returning to Smart Card interface mode from software standby mode [7] Exit the software standby state. [8] Set the CKE1 bit in SCR to the value for the fixed output state (current SCK pin state) when software standby mode is initiated. [9] Set Smart Card interface mode and output the clock. Signal generation is started with the normal duty. Rev.6.00 Oct.28.2004 page 534 of 1016 REJ09B0138-0600H Normal operation Software standby Normal operation [1] [2] [3] [4] [5] [6] [7] [8] [9] Figure 15-9 Clock Halt and Restart Procedure Powering On: To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. [2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR. [3] Set SMR and SCMR, and switch to Smart Card mode operation. [4] Set the CKE0 bit in SCR to 1 to start clock output. 15.4 Usage Notes The following points should be noted when using the SCI as a Smart Card interface. Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode: In Smart Card Interface mode, the SCI operates on a basic clock with a frequency of 372 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 186th pulse of the basic clock. This is illustrated in figure 15-10. 372 clocks 186 clocks 0 185 371 0 185 371 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 15-10 Receive Data Sampling Timing in Smart Card Mode Thus the reception margin in asynchronous mode is given by the following formula. Rev.6.00 Oct.28.2004 page 535 of 1016 REJ09B0138-0600H M = (0.5 – 1 2N ) – (L – 0.5) F –  D – 0.5 N (1 + F) × 100% Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 372) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0 and D = 0.5 in the above formula, the reception margin formula is as follows. When D = 0.5 and F = 0, M = (0.5 – 1/2 × 372) × 100% = 49.866% Retransfer Operations: Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. • Retransfer operation when SCI is in receive mode Figure 15-11 illustrates the retransfer operation when the SCI is in receive mode. [1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [2] The RDRF bit in SSR is not set for a frame in which an error has occurred. [3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1. [4] If no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is generated. If DMAC or DTC data transfer by an RXI source is enabled, the contents of RDR can be read automatically. When the RDR data is read by the DMAC or DTC, the RDRF flag is automatically cleared to 0. [5] When a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission. Transfer frame n+1 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1] Retransferred frame (DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 [4] [3] Figure 15-11 Retransfer Operation in SCI Receive Mode • Retransfer operation when SCI is in transmit mode Figure 15-12 illustrates the retransfer operation when the SCI is in transmit mode. [6] If an error signal is sent back from the receiving end after transmission of one frame is completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next parity bit is sampled. Rev.6.00 Oct.28.2004 page 536 of 1016 REJ09B0138-0600H [7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality is received. [8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. [9] If an error signal is not sent back from the receiving end, transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt request is generated. If data transfer by the DMAC or DTC by means of the TXI source is enabled, the next data can be written to TDR automatically. When data is written to TDR by the DMAC or DTC, the TDRE bit is automatically cleared to 0. Transfer frame n+1 (DE) Ds D0 D1 D2 D3 D4 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE TDRE Transfer to TSR from TDR TEND [7] FER/ERS [6] Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transfer to TSR from TDR Transfer to TSR from TDR [9] [8] Figure 15-12 Retransfer Operation in SCI Transmit Mode Rev.6.00 Oct.28.2004 page 537 of 1016 REJ09B0138-0600H Rev.6.00 Oct.28.2004 page 538 of 1016 REJ09B0138-0600H Section 16 A/D Converter 16.1 Overview The H8S/2357 Group incorporates a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. 16.1.1 Features A/D converter features are listed below • 10-bit resolution • Eight input channels • Settable analog conversion voltage range  Conversion of analog voltages with the reference voltage pin (Vref ) as the analog reference voltage • High-speed conversion  Minimum conversion time: 6.7 µs per channel (at 20 MHz operation) • Choice of single mode or scan mode  Single mode: Single-channel A/D conversion  Scan mode: Continuous A/D conversion on 1 to 4 channels • Four data registers  Conversion results are held in a 16-bit data register for each channel • Sample and hold function • Three kinds of conversion start  Choice of software or timer conversion start trigger (TPU or 8-bit timer), or ADTRG pin • A/D conversion end interrupt generation  A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion • Module stop mode can be set  As the initial setting, A/D converter operation is halted. Register access is enabled by exiting module stop mode. Rev.6.00 Oct.28.2004 page 539 of 1016 REJ09B0138-0600H 16.1.2 Block Diagram Figure 16-1 shows a block diagram of the A/D converter. Module data bus Bus interface A D D R A A D D R B A D D R C A D D R D A D C S R A D C R + Multiplexer – Comparator Sample-andhold circuit Control circuit Internal data bus AVCC Vref AVSS 10-bit D/A AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Successive approximations register ADI interrupt ADTRG 8-bit timer or conversion start trigger from TPU Legend: ADCR: A/D control register ADCSR : A/D control/status register ADDRA : A/D data register A ADDRB : A/D data register B ADDRC : A/D data register C ADDRD : A/D data register D Figure 16-1 Block Diagram of A/D Converter 16.1.3 Pin Configuration Table 16-1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). Rev.6.00 Oct.28.2004 page 540 of 1016 REJ09B0138-0600H Table 16-1 A/D Converter Pins Pin Name Analog power supply pin Analog ground pin Reference voltage pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Symbol AVCC AVSS Vref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 I/O Input Input Input Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Group 1 analog inputs Function Analog block power supply Analog block ground and A/D conversion reference voltage A/D conversion reference voltage Group 0 analog inputs A/D external trigger input pin ADTRG 16.1.4 Register Configuration Table 16-2 summarizes the registers of the A/D converter. Table 16-2 A/D Converter Registers Name A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Module stop control register Abbreviation ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR MSTPCR R/W R R R R R R R R R/(W)* R/W R/W 2 Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'3F H'3FFF Address* 1 H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FF3C Notes: 1. Lower 16 bits of the address. 2. Bit 7 can only be written with 0 for flag clearing. Rev.6.00 Oct.28.2004 page 541 of 1016 REJ09B0138-0600H 16.2 16.2.1 Bit Register Descriptions A/D Data Registers A to D (ADDRA to ADDRD) : 15 14 13 12 11 10 9 8 7 6 5 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R 0 — 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — Initial value : R/W : 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. Bits 5 to 0 are always read as 0. The correspondence between the analog input channels and ADDR registers is shown in table 16-3. ADDR can always be read by the CPU. The upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section 16.3, Interface to Bus Master. The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop mode. Table 16-3 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD 16.2.2 Bit A/D Control/Status Register (ADCSR) : 7 ADF 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Initial value : R/W : 0 R/(W)* Note: * Only 0 can be written to bit 7, to clear this flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations and shows the status of the operation. ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode. Rev.6.00 Oct.28.2004 page 542 of 1016 REJ09B0138-0600H Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion. Bit 7 ADF 0 Description [Clearing conditions] • • 1 When 0 is written to the ADF flag after reading ADF = 1 When the DTC is activated by an ADI interrupt and ADDR is read (Initial value) [Setting conditions] • • Single mode: When A/D conversion ends Scan mode: When A/D conversion ends on all specified channels Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests at the end of A/D conversion. Bit 6 ADIE 0 1 Description A/D conversion end interrupt (ADI) request disabled A/D conversion end interrupt (ADI) request enabled (Initial value) Bit 5—A/D Start (ADST): Selects starting or stopping on A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST 0 1 Description • • • A/D conversion stopped (Initial value) Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends. Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. Bit 4—Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating mode. See section 16.4, Operation, for single mode and scan mode operation. Only set the SCAN bit while conversion is stopped (ADST = 0). Bit 4 SCAN 0 1 Description Single mode Scan mode (Initial value) Bit 3—Clock Select (CKS): Sets the A/D conversion time. Only change the conversion time while conversion is stopped (ADST = 0). Bit 3 CKS 0 1 Description Conversion time = 266 states (max.) Conversion time = 134 states (max.) (Initial value) Rev.6.00 Oct.28.2004 page 543 of 1016 REJ09B0138-0600H Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input channels. Only set the input channel while conversion is stopped (ADST = 0). Group Selection CH2 0 Channel Selection CH1 0 CH0 0 1 1 0 1 1 0 0 1 1 0 1 Description Single Mode (SCAN=0) AN0 (Initial value) AN1 AN2 AN3 AN4 AN5 AN6 AN7 Scan Mode (SCAN=1) AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 16.2.3 Bit A/D Control Register (ADCR) : 7 TRGS1 6 TRGS0 0 R/W 5 — 1 — 4 — 1 — 3 — 1 2 — 1 1 — 1 — 0 — 1 — Initial value : R/W : 0 R/W —/(R/W)* —/(R/W)* Note: * Applies to the H8S/2398, H8S/2394, H8S/2392, and H8S/2390. ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations. ADCR is initialized to H'3F by a reset, and in standby mode or module stop mode. Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): Select enabling or disabling of the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped (ADST = 0). Bit 7 TRGS1 0 Bit 6 TRGS0 0 1 1 0 1 Description A/D conversion start by external trigger is disabled A/D conversion start by external trigger (TPU) is enabled A/D conversion start by external trigger (8-bit timer) is enabled A/D conversion start by external trigger pin ( ADTRG) is enabled (Initial value) (1) For H8S/2357 and H8S/2352 Bits 5 to 0—Reserved: They are always read as 1 and cannot be modified. (2) For H8S/2398, H8S/2394, H8S/2392, and H8S/2390 Bits 5, 4, 1, and 0—Reserved: They are always read as 1 and cannot be modified. Bits 3 and 2—Reserved: Should always be written with 1. Rev.6.00 Oct.28.2004 page 544 of 1016 REJ09B0138-0600H 16.2.4 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 9 8 7 6 5 4 3 2 1 0 Bit : 15 14 13 12 11 Initial value : R/W 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP9 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 9—Module Stop (MSTP9): Specifies the A/D converter module stop mode. Bit 9 MSTP9 0 1 Description A/D converter module stop mode cleared A/D converter module stop mode set (Initial value) Rev.6.00 Oct.28.2004 page 545 of 1016 REJ09B0138-0600H 16.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading ADDR. always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 16-2 shows the data flow for ADDR access. Upper byte read Bus master (H'AA) Bus interface Module data bus TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Lower byte read Bus master (H'40) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Figure 16-2 ADDR Access Operation (Reading H'AA40) 16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. 16.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1, according to the software or external trigger input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. Rev.6.00 Oct.28.2004 page 546 of 1016 REJ09B0138-0600H On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 16-3 shows a timing diagram for this example. [1] Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = 0, CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). [2] When A/D conversion is completed, the result is transferred to ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. [3] Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. [4] The A/D interrupt handling routine starts. [5] The routine reads ADCSR, then writes 0 to the ADF flag. [6] The routine reads and processes the connection result (ADDRB). [7] Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps [2] to [7] are repeated. Set* ADIE ADST ADF State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Idle Idle Idle Idle A/D conversion 1 A/D conversion starts Set* Clear* Set* Clear* Idle A/D conversion 2 Idle ADDRA ADDRB ADDRC ADDRD Read conversion result A/D conversion result 1 Read conversion result A/D conversion result 2 Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 16-3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Rev.6.00 Oct.28.2004 page 547 of 1016 REJ09B0138-0600H 16.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by a software, timer or external trigger input, A/D conversion starts on the first channel in the group (AN0). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDR registers corresponding to the channels. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described next. Figure 16-4 shows a timing diagram for this example. [1] Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1) [2] When A/D conversion of the first channel (AN0) is completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. [3] Conversion proceeds in the same way through the third channel (AN2). [4] When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. [5] Steps [2] to [4] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). Continuous A/D conversion execution Set*1 ADST ADF A/D conversion time State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Transfer ADDRA ADDRB ADDRC ADDRD Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. A/D conversion result 1 A/D conversion result 4 A/D conversion result 2 A/D conversion result 3 Idle Idle Idle A/D conversion 1 Clear*1 Clear*1 Idle A/D conversion 2 A/D conversion 4 Idle A/D conversion 5 *2 Idle A/D conversion 3 Idle Idle Idle Figure 16-4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) Rev.6.00 Oct.28.2004 page 548 of 1016 REJ09B0138-0600H 16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a on-chip sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 16-5 shows the A/D conversion timing. Table 16-4 indicates the A/D conversion time. As indicated in figure 16-5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 16-4. In scan mode, the values given in table 16-4 apply to the first conversion time. In the second and subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states when CKS = 1. (1) ø Address bus (2) Write signal Input sampling timing ADF tD t SPL t CONV Legend: (1): (2): tD: tSPL: tCONV: ADCSR write cycle ADCSR address A/D conversion start delay Input sampling time A/D conversion time Figure 16-5 A/D Conversion Timing Table 16-4 A/D Conversion Time (Single Mode) CKS = 0 Item A/D conversion start delay Input sampling time A/D conversion time Symbol tD t SPL t CONV Min 10 — 259 Typ — 63 — Max 17 — 266 Min 6 — 131 CKS = 1 Typ — 31 — Max 9 — 134 Note: Values in the table are the number of states. Rev.6.00 Oct.28.2004 page 549 of 1016 REJ09B0138-0600H 16.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit has been set to 1 by software. Figure 16-6 shows the timing. ø ADTRG Internal trigger signal ADST A/D conversion Figure 16-6 External Trigger Input Timing 16.5 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC or DMAC can be activated by an ADI interrupt. Having the converted data read by the DTC or DMAC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. The A/D converter interrupt source is shown in table 16-5. Table 16-5 A/D Converter Interrupt Source Interrupt Source ADI Description Interrupt due to end of conversion DTC or DMAC Activation Possible Rev.6.00 Oct.28.2004 page 550 of 1016 REJ09B0138-0600H 16.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins: (1) Analog input voltage range The voltage applied to analog input pins AN0 to AN7 during A/D conversion should be in the range AVSS ≤ ANn ≤ Vref. (2) Relation between AV CC, AVSS and V CC, VSS As the relationship between AVCC, AVSS and V CC, VSS, set AVSS = VSS . If the A/D converter is not used, the AVCC and AVSS pins must on no account be left open. (3) Vref input range The analog reference voltage input at the V ref pin set in the range Vref ≤ AVCC. Note:If conditions (1), (2), and (3) above are not met, the reliability of the device may be adversely affected. Notes on Board Design: In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), analog reference power supply (Vref), and analog power supply (AV CC) by the analog ground (AVSS ). Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS) on the board. Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) and analog reference power supply (Vref) should be connected between AVCC and AVSS as shown in figure 16-7. Also, the bypass capacitors connected to AVCC and Vref and the filter capacitor connected to AN0 to AN7 must be connected to AVSS . If a filter capacitor is connected as shown in figure 16-7, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. Rev.6.00 Oct.28.2004 page 551 of 1016 REJ09B0138-0600H AVCC Vref Rin* 2 *1 *1 0.1 µF 100 Ω AN0 to AN7 AVSS Notes: Values are reference values. 1. 10 µF 0.01 µF 2. Rin: Input impedance Figure 16-7 Example of Analog Input Protection Circuit A/D Conversion Precision Definitions: H8S/2357 Group A/D conversion precision definitions are given below. • Resolution The number of A/D converter digital output codes • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 16-9). • Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 16-9). • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16-8). • Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error. • Absolute precision The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Rev.6.00 Oct.28.2004 page 552 of 1016 REJ09B0138-0600H Digital output 111 110 101 100 011 010 001 000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 1024 1024 FS Analog input voltage Figure 16-8 A/D Conversion Precision Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 16-9 A/D Conversion Precision Definitions (2) Permissible Signal Source Impedance: H8S/2357 Group analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 kohm or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 kohm, charging may be insufficient and it may not be possible to guarantee the A/D conversion precision. Rev.6.00 Oct.28.2004 page 553 of 1016 REJ09B0138-0600H However, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 kohm, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/µs or greater). When converting a high-speed analog signal, a low-impedance buffer should be inserted. Influences on Absolute Precision: Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AV SS . Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. H8/2357 Group Sensor output impedance to 10 k Ω Sensor input Low-pass filter C to 0.1 µF Cin = 15 pF A/D converter equivalent circuit 10 kΩ 20 pF Note: Values are reference values. Figure 16-10 Example of Analog Input Circuit Rev.6.00 Oct.28.2004 page 554 of 1016 REJ09B0138-0600H Section 17 D/A Converter 17.1 Overview The H8S/2357 Group includes a two-channel D/A converter. 17.1.1 Features D/A converter features are listed below • • • • • • 8-bit resolution Two output channels Maximum conversion time of 10 µs (with 20 pF load) Output voltage of 0 V to Vref D/A output hold function in software standby mode Module stop mode can be set  As the initial setting, D/A converter operation is halted. Register access is enabled by exiting module stop mode. Block Diagram 17.1.2 Figure 17-1 shows a block diagram of the D/A converter. Module data bus Bus interface DACR Internal data bus Vref AVCC DADR0 8-bit DA1 D/A DA0 AVSS DADR1 Control circuit Legend: DACR: D/A control register DADR0,1: D/A data register 0, 1 Figure 17-1 Block Diagram of D/A Converter Rev.6.00 Oct.28.2004 page 555 of 1016 REJ09B0138-0600H 17.1.3 Pin Configuration Table 17-1 summarizes the input and output pins of the D/A converter. Table 17-1 Pin Configuration Pin Name Analog power pin Analog ground pin Analog output pin 0 Analog output pin 1 Reference voltage pin Symbol AVCC AVSS DA0 DA1 Vref I/O Input Input Output Output Input Function Analog power source Analog ground and reference voltage Channel 0 analog output Channel 1 analog output Analog reference voltage 17.1.4 Register Configuration Table 17-2 summarizes the registers of the D/A converter. Table 17-2 D/A Converter Registers Name D/A data register 0 D/A data register 1 D/A control register Module stop control register Note: * Lower 16 bits of the address. Abbreviation DADR0 DADR1 DACR MSTPCR R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'1F H'3FFF Address* H'FFA4 H'FFA5 H'FFA6 H'FF3C Rev.6.00 Oct.28.2004 page 556 of 1016 REJ09B0138-0600H 17.2 17.2.1 Bit Register Descriptions D/A Data Registers 0 and 1 (DADR0, DADR1) : 7 6 5 4 3 2 1 0 Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W DADR0 and DADR1 are 8-bit readable/writable registers that store data for conversion. Whenever output is enabled, the values in DADR0 and DADR1 are converted and output from the analog output pins. DADR0 and DADR1 are each initialized to H'00 by a reset and in hardware standby mode. 17.2.2 Bit D/A Control Register (DACR) : 7 DAOE1 6 DAOE0 0 R/W 5 DAE 0 R/W 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Initial value : R/W : 0 R/W DACR is an 8-bit readable/writable register that controls the operation of the D/A converter. DACR is initialized to H'1F by a reset and in hardware standby mode. Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output for channel 1. Bit 7 DAOE1 0 1 Description Analog output DA1 is disabled Channel 1 D/A conversion is enabled; analog output DA1 is enabled (Initial value) Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output for channel 0. Bit 6 DAOE0 0 1 Description Analog output DA0 is disabled Channel 0 D/A conversion is enabled; analog output DA0 is enabled (Initial value) Rev.6.00 Oct.28.2004 page 557 of 1016 REJ09B0138-0600H Bit 5—D/A Enable (DAE): The DAOE0 and DAOE1 bits both control D/A conversion. When the DAE bit is cleared to 0, the channel 0 and 1 D/A conversions are controlled independently. When the DAE bit is set to 1, the channel 0 and 1 D/A conversions are controlled together. Output of resultant conversions is always controlled independently by the DAOE0 and DAOE1 bits. Bit 7 DAOE1 0 Bit 6 DAOE0 0 1 Bit 5 DAE × 0 1 1 0 0 1 1 × Description Channel 0 and 1 D/A conversions disabled Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled Channel 0 and 1 D/A conversions enabled Channel 0 D/A conversion disabled Channel 1 D/A conversion enabled Channel 0 and 1 D/A conversions enabled Channel 0 and 1 D/A conversions enabled ×: Don’t care If the H8S/2357 Group enters software standby mode when D/A conversion is enabled, the D/A output is held and the analog power current is the same as during D/A conversion. When it is necessary to reduce the analog power current in software standby mode, clear both the DAOE0 and DAOE1 bits to 0 to disable D/A output. Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1. 17.2.3 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 15 14 13 12 11 10 9 8 7 6 5 MSTPCRL 4 3 2 1 0 Initial value : R/W 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP10 bit in MSTPCR is set to 1, D/A converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 21.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 10—Module Stop (MSTP10): Specifies the D/A converter module stop mode. Bit 10 MSTP10 0 1 Description D/A converter module stop mode cleared D/A converter module stop mode set (Initial value) Rev.6.00 Oct.28.2004 page 558 of 1016 REJ09B0138-0600H 17.3 Operation The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. D/A conversion is performed continuously while enabled by DACR. If either DADR0 or DADR1 is written to, the new data is immediately converted. The conversion result is output by setting the corresponding DAOE0 or DAOE1 bit to 1. The operation example described in this section concerns D/A conversion on channel 0. Figure 17-2 shows the timing of this operation. [1] Write the conversion data to DADR0. [2] Set the DAOE0 bit in DACR to 1. D/A conversion is started and the DA0 pin becomes an output pin. The conversion result is output after the conversion time has elapsed. The output value is expressed by the following formula: DADR contents 256 The conversion results are output continuously until DADR0 is written to again or the DAOE0 bit is cleared to 0. [3] If DADR0 is written to again, the new data is immediately converted. The new conversion result is output after the conversion time has elapsed. [4] If the DAOE0 bit is cleared to 0, the DA0 pin becomes an input pin. DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle × Vref ø Address DADR0 Conversion data 1 Conversion data 2 DAOE0 DA0 High-impedance state tDCONV Legend: tDCONV: D/A conversion time Conversion result 1 tDCONV Conversion result 2 Figure 17-2 Example of D/A Converter Operation Rev.6.00 Oct.28.2004 page 559 of 1016 REJ09B0138-0600H Rev.6.00 Oct.28.2004 page 560 of 1016 REJ09B0138-0600H Section 18 RAM 18.1 Overview The H8S/2357, H8S/2352, H8S/2398, and H8S/2392 have 8 kbytes of on-chip high-speed static RAM. The H8S/2394 has 32 kbytes of on-chip high-speed static RAM. The H8S/2390 has 4 kbytes of on-chip high-speed static RAM. The on-chip RAM is connected to the CPU by a 16-bit bus, and accessing both byte data and word data can be performed in a single state. Thus, high-speed transfer of word data is possible. The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR). 18.1.1 Block Diagram Figure 18-1 shows a block diagram of the 8-kbytes of on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FFDC00 H'FFDC02 H'FFDC04 H'FFDC01 H'FFDC03 H'FFDC05 H'FFFBFE H'FFFBFF Figure 18-1 Block Diagram of RAM (8 kbyte) 18.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 18-1 shows the address and initial value of SYSCR. Table 18-1 RAM Register Name System control register Note: * Lower 16 bits of the address. Abbreviation SYSCR R/W R/W Initial Value H'01 Address* H'FF39 Rev.6.00 Oct.28.2004 page 561 of 1016 REJ09B0138-0600H 18.2 18.2.1 Bit Register Descriptions System Control Register (SYSCR) : 7 — 6 — 0 — 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 — 0 — 1 — 0 R/W 0 RAME 1 R/W Initial value : R/W : 0 R/W The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in SYSCR, see section 3.2.2, System Control Register (SYSCR). Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) 18.3 Operation When the RAME bit is set to 1, accesses to addresses H'FFDC00 to H'FFFBFF* are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or word units. Each type of access can be performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address. Note: * Since the on-chip RAM capacitance differs according to each product, see section 3.5, Memory Map in Each Operating Mode. 18.4 Usage Note DTC register information can be located in addresses H'FFF800 to H'FFFBFF. When the DTC is used, the RAME bit must not be cleared to 0. Rev.6.00 Oct.28.2004 page 562 of 1016 REJ09B0138-0600H Section 19 ROM 19.1 Overview This series has 256, or 128 kbytes of flash memory, 256 or 128 kbytes of masked ROM, or 128 kbytes of PROM. The ROM is connected to the H8S/2000 CPU by a 16-bit data bus. The CPU accesses both byte data and word data in one state, making possible rapid instruction fetches and high-speed processing. The on-chip ROM is enabled or disabled by setting the mode pins (MD2, MD1, and MD0) and bit EAE in BCRL. The flash memory versions of the H8S/2357 Group can be erased and programmed on-board as well as with a PROM programmer. The PROM version of the H8S/2357 Group can be programmed with a PROM programmer, by setting PROM mode. 19.1.1 Block Diagram Figure 19-1 shows a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000002 H'000001 H'000003 H'01FFFE H'01FFFF Figure 19-1 Block Diagram of ROM (128 kbytes) 19.1.2 Register Configuration The H8S/2357’s on-chip ROM is controlled by the mode pins and register BCRL. The register configuration is shown in table 19-1. Table 19-1 ROM Register Name Mode control register Bus control register L Note: * Lower 16 bits of the address. Abbreviation MDCR BCRL R/W R/W R/W Initial Value Undefined Undefined Address* H'FF3B H'FED5 Rev.6.00 Oct.28.2004 page 563 of 1016 REJ09B0138-0600H 19.2 19.2.1 Bit Register Descriptions Mode Control Register (MDCR) : 7 — 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 MDS2 —* R 1 MDS1 —* R 0 MDS0 —* R Initial value : R/W : 1 — Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2357 Group. Bit 7—Reserved: This bit cannot be modified and is always read as 1. Bits 6 to 3—Reserved: These bits cannot be modified and are always read as 0. Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to MD0. MDS2 to MDS0 are read-only bits, and cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a power-on reset, but are retained after a manual reset*. Note: * Manual reset is only supported in the H8S/2357 ZTAT. 19.2.2 Bit Bus Control Register L (BCRL) : 7 BRLE 6 BREQOE 0 R/W 5 EAE 1 R/W 4 LCASS 1 R/W 3 DDS 1 R/W 2 — 1 R/W 1 WDBE 0 R/W 0 WAITE 0 R/W Initial value : R/W : 0 R/W Enabling or disabling of part of the H8S/2357’s on-chip ROM area can be selected by means of the EAE bit in BCRL. For details of the other bits in BCRL, see section 6.2.5, Bus Control Register L (BCRL). Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'01FFFF*2 are to be internal addresses or external addresses. Bit 5 EAE 0 1 Description Addresses H'010000 to H'01FFFF* 2 are in on-chip ROM Addresses H'010000 to H'01FFFF* 2 are external addresses (external expansion mode) or a reserved area * 1 (single-chip mode). (Initial value) Notes: 1. Reserved areas should not be accessed. 2. Addresses H'010000 to H'01FFFF are in the H8S/2357. Addresses H'010000 to H'03FFFF are in the H8S/2398. Rev.6.00 Oct.28.2004 page 564 of 1016 REJ09B0138-0600H 19.3 Operation The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. Word data must start at an even address. The on-chip ROM is enabled and disabled by setting the mode pins (MD 2, MD1, and MD0) and bit EAE in BCRL. These settings are shown in tables 19-2 and 19-3. Table 19-2 Operating Modes and ROM Area (H8S/2357 F-ZTAT) Mode Pin Operating Mode Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM disabled Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode 1 1 0 1 — FWE MD2 0 0 MD1 0 MD0 0 1 0 1 0 1 0 0 1 1 0 1 Mode 8 Mode 9 Mode 10 Boot mode (advanced expanded mode with onchip ROM enabled) * 3 Mode 11 Boot mode (advanced single-chip mode)* 4 Mode 12 — Mode 13 Mode 14 User program mode (advanced expanded mode with on-chip ROM enabled)* 3 Mode 15 User program mode (advanced single-chip mode)*4 1 1 0 1 — 1 0 0 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 Enabled (128 kbytes)* 1 Enabled (64 kbytes) Enabled (128 kbytes)* 1 Enabled (64 kbytes) — Enabled (128 kbytes)* 2 Enabled (64 kbytes) Enabled (128 kbytes)* 2 Enabled (64 kbytes) — — Enabled (128 kbytes)* 1 Enabled (64 kbytes) Enabled (128 kbytes)* 1 Enabled (64 kbytes) — — Disabled BCRL EAE — On-Chip ROM — Mode 7 Notes: 1. Note that in modes 6, 7, 14, and 15, the on-chip ROM that can be used after a power-on reset is the 64-kbyte area from H'000000 to H'00FFFF. 2. Note that in the mode 10 and mode 11 boot modes, the on-chip ROM that can be used immediately after all flash memory is erased by the boot program is the 64-kbyte area from H'000000 to H'00FFFF. 3. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced expanded mode with on-chip ROM enabled. 4. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced single-chip mode. Rev.6.00 Oct.28.2004 page 565 of 1016 REJ09B0138-0600H Table 19-3 Operating Modes and ROM Area (ZTAT or Masked ROM, ROMless, Versions H8S/2398F-ZTAT) Mode Pin Operating Mode Mode 0 Mode 1 Mode 2* Mode 3* Mode 4* 2 2 3 BCRL EAE — On-Chip ROM — MD2 0 MD1 0 MD0 0 1 — 1 0 1 Advanced expanded mode with on-chip ROM disabled 1 0 0 1 — Disabled Mode 5* 3 Advanced expanded mode with on-chip ROM disabled Mode 6 Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode 1 0 0 1 Enabled (128 kbytes)* 1 Enabled (64 kbytes) Enabled (128 kbytes)* 1 Enabled (64 kbytes) Mode 7 1 0 1 Notes: 1. Modes 6 and 7, the on-chip ROM available after a power-on reset is the 64-kbyte area comprising addresses H'000000 to H'00FFFF. Since the on-chip ROM area differs according to each product, see section 3.5, Memory Map in Each Operating Mode. 2. In the H8S/2398 F-ZTAT, modes 2 and 3 indicate boot mode. For details on boot mode of H8S/2398 F-ZTAT, refer to table 19-35 in section 19.17, On-Board Programming Modes. In addition, for details on user program mode, refer also to and 19-35 in section 19.17, On-Board Programming Modes. 3. In ROMless version, only modes 4 and 5 are available. 19.4 19.4.1 PROM Mode (H8S/2357 ZTAT) PROM Mode Setting The PROM version of the H8S/2357 suspends its microcontroller functions when placed in PROM mode, enabling the onchip PROM to be programmed. This programming can be done with a PROM programmer set up in the same way as for the HN27C101 EPROM (VPP = 12.5 V). Use of a 120/128-pin to 32-pin socket adapter enables programming with a commercial PROM programmer. Note that the PROM programmer should not be set to page mode as the H8S/2357 does not support page programming. Table 19-4 shows how PROM mode is selected. Table 19-4 Selecting PROM Mode Pin Names MD2, MD1, MD0 STBY PA2, PA1 High Setting Low Rev.6.00 Oct.28.2004 page 566 of 1016 REJ09B0138-0600H 19.4.2 Socket Adapter and Memory Map Programs can be written and verified by attaching a socket adapter to the PROM programmer to convert from a 120/128pin arrangement to a 32-pin arrangement. Table 19-5 gives ordering information for the socket adapter, and figure 19-2 shows the wiring of the socket adapter. Figure 19-3 shows the memory map in PROM mode. H8S/2357 TFP-120 73 43 44 45 46 48 49 50 51 2 3 4 5 7 8 9 10 11 74 13 14 16 17 18 19 20 86 12 87 1, 33, 52, 76, 81 93 94 21 22 6, 15, 24, 38, 47, 59, 79, 104 103 75 113 114 115 FP-128B 81 49 50 51 52 54 55 56 57 6 7 8 9 11 12 13 14 15 82 17 18 20 21 22 23 24 94 16 95 5, 39, 58, 84, 89 103 104 25 26 3, 10, 19, 28, 35, 36, 44, 53, 65, 67, 68, 87, 99,100,114 113 83 123 124 125 AVSS STBY MD0 MD1 MD2 Programming power supply (12.5 V) EO7 to EO0: Data input/output EA16 to EA0: Address input OE: Output enable CE: Chip enable PGM: Program VPP: Pin RES PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PB0 NMI PB2 PB3 PB4 PB5 PB6 PB7 PA0 PF2 PB1 PF1 VCC AVCC Vref PA1 PA2 VSS VSS 16 EPROM socket Pin VPP EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 EA16 CE OE PGM VCC HN27C101 (32 Pins) 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32 Note: Pins not shown in this figure should be left open. Figure 19-2 Wiring of 120/128B-Pin Socket Adapter Rev.6.00 Oct.28.2004 page 567 of 1016 REJ09B0138-0600H Table 19-5 Socket Adapter Microcontroller H8S/2357 Package 120 pin TQFP (TFP-120) 128 pin QFP (FP-128B) Socket Adapter HS2655ESNS1H HS2655ESHS1H Addresses in MCU mode H'000000 Addresses in PROM mode H'00000 On-chip PROM H'01FFFF H'1FFFF Figure 19-3 Memory Map in PROM Mode Rev.6.00 Oct.28.2004 page 568 of 1016 REJ09B0138-0600H 19.5 19.5.1 Programming (H8S/2357 ZTAT) Overview Table 19-6 shows how to select the program, verify, and program-inhibit modes in PROM mode. Table 19-6 Mode Selection in PROM Mode Pins Mode Program Verify Program-inhibit CE L L L L H H Legend: L: Low voltage level H: High voltage level VPP : VPP voltage level VCC: VCC voltage level OE H L L H L H PGM L H L H L H VPP VPP VPP VPP VCC VCC VCC VCC EO7 to EO0 Data input Data output High impedance EA 16 to EA0 Address input Address input Address input Programming and verification should be carried out using the same specifications as for the standard HN27C101 EPROM. However, do not set the PROM programmer to page mode, as the H8S/2357 does not support page programming. A PROM programmer that only supports page programming cannot be used. When choosing a PROM programmer, check that it supports high-speed programming in byte units. Always set addresses within the range H'00000 to H'1FFFF. Rev.6.00 Oct.28.2004 page 569 of 1016 REJ09B0138-0600H 19.5.2 Programming and Verification An efficient, high-speed programming procedure can be used to program and verify PROM data. This procedure writes data quickly without subjecting the chip to voltage stress or sacrificing data reliability. It leaves the data H'FF in unused addresses. Figure 19-4 shows the basic high-speed programming flowchart. Tables 19-7 and 19-8 list the electrical characteristics of the chip during programming. Figure 19-5 shows a timing chart. Start Set programming/verification mode VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V Address = 0 n=0 n + 1→ n Yes No n < 25 Program with tPW = 0.2 ms ± 5% Address + 1 → address No Verification OK? Yes Program with tOPW = 0.2n ms No Last address? Yes Set read mode VCC = 5.0 V ± 0.25 V VPP = VCC Fail No go All addresses read? Go End Figure 19-4 High-Speed Programming Flowchart Rev.6.00 Oct.28.2004 page 570 of 1016 REJ09B0138-0600H Table 19-7 DC Characteristics in PROM Mode Conditions: VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, VSS = 0 V, Ta = 25°C ± 5°C Item Input high voltage EO7 to EO 0, EA16 to EA 0, OE, CE , PGM EO7 to EO 0, EA16 to EA0, OE, CE , PGM Symbol Min VIH 2.4 Typ — Max VCC + 0.3 Test Unit Conditions V Input low voltage VIL –0.3 — 0.8 V Output high voltage EO7 to EO 0 Output low voltage Input leakage current VCC current VPP current EO7 to EO 0 EO7 to EO 0, EA16 to EA 0, OE, CE , PGM VOH VOL | ILI | 2.4 — — — — — — 0.45 2 V V µA I OH = –200 µA I OL = 1.6 mA Vin = 5.25 V/0.5 V I CC I PP — — — — 40 40 mA mA Table 19-8 AC Characteristics in PROM Mode Conditions: VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, T a = 25°C ± 5°C Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time VPP setup time Programming pulse width Symbol t AS t OES t DS t AH t DH t DF * t VPS t PW 3 2 Min 2 2 2 0 2 — 2 0.19 0.19 2 2 0 Typ — — — — — — — 0.20 — — — — Max — — — — — 130 — 0.21 5.25 — — 150 Unit µs µs µs µs µs ns µs ms ms µs µs ns Test Conditions Figure 19-5* 1 PGM pulse width for overwrite programming t OPW* VCC setup time CE setup time Data output delay time t VCS t CES t OE Notes: 1. Input pulse level: 0.8 V to 2.2 V Input rise time and fall time ≤ 20 ns Timing reference levels: Input: 1.0 V, 2.0 V Output: 0.8 V, 2.0 V 2. t DF is defined to be when output has reached the open state, and the output level can no longer be referenced. 3. t OPW is defined by the value shown in the flowchart. Rev.6.00 Oct.28.2004 page 571 of 1016 REJ09B0138-0600H Program Address tAS Data tDS VPP VCC VPP VCC VCC+1 VCC tVPS tVCS Input data tDH Verify tAH Output data tDF CE tCES PGM tPW OE tOPW* tOES tOE Note: * tOPW is defined by the value shown in the flowchart. Figure 19-5 PROM Programming/Verification Timing 19.5.3 Programming Precautions • Program using the specified voltages and timing. The programming voltage (VPP) in PROM mode is 12.5 V. If the PROM programmer is set to Renesas Technology HN27C101 specifications, VPP will be 12.5 V. Applied voltages in excess of the specified values can permanently destroy the MCU. Be particularly careful about the PROM programmer’s overshoot characteristics. • Before programming, check that the MCU is correctly mounted in the PROM programmer. Overcurrent damage to the MCU can result if the index marks on the PROM programmer, socket adapter, and MCU are not correctly aligned. • Do not touch the socket adapter or MCU while programming. Touching either of these can cause contact faults and programming errors. • The MCU cannot be programmed in page programming mode. Select the programming mode carefully. • The size of the H8S/2357 PROM is 128 kbytes. Always set addresses within the range H'00000 to H'1FFFF. During programming, write H'FF to unused addresses to avoid verification errors. Rev.6.00 Oct.28.2004 page 572 of 1016 REJ09B0138-0600H 19.5.4 Reliability of Programmed Data An effective way to assure the data retention characteristics of the programmed chips is to bake them at 150°C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to early failure. Figure 19-6 shows the recommended screening procedure. Program chip and verify data Bake chip for 24 to 48 hours at 125°C to 150°C with power off Read and check program Mount Figure 19-6 Recommended Screening Procedure If a series of programming errors occurs while the same PROM programmer is being used, stop programming and check the PROM programmer and socket adapter for defects. Please inform Renesas Technology of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking. Rev.6.00 Oct.28.2004 page 573 of 1016 REJ09B0138-0600H 19.6 19.6.1 Overview of Flash Memory (H8S/2357 F-ZTAT) Features The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode  Erase-verify mode • Programming/erase methods The flash memory is programmed 32 bytes at a time. Erasing is performed by block erase (in single-block units). When erasing multiple blocks, the individual blocks must be erased sequentially. Block erasing can be performed as required on 1-kbyte, 8-kbyte, 16-kbyte, 28-kbyte, and 32-kbyte blocks. • Programming/erase times (5 V version) The flash memory programming time is 10 ms (typ.) for simultaneous 32-byte programming, equivalent to 300 µs (typ.) per byte, and the erase time is 100 ms (typ.) per block. • Reprogramming capability The flash memory can be reprogrammed up to 100 times. • On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board  Boot mode  User program mode • Automatic bit rate adjustment With data transfer in boot mode, the bit rate of the H8S/2357 Group chip can be automatically adjusted to match the transfer bit rate of the host. • Flash memory emulation by RAM Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates in real time. • Protect modes There are three protect modes, hardware, software, and error protect, which allow protected status to be designated for flash memory program/erase/verify operations. • Programmer mode Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode. Rev.6.00 Oct.28.2004 page 574 of 1016 REJ09B0138-0600H 19.6.2 Block Diagram Internal address bus Internal data bus (16 bits) SYSCR2 FLMCR1 Module bus FLMCR2 EBR1 EBR2 RAMER Bus interface/controller Operating mode FWE pin Mode pins Flash memory (128 kbytes) Legend: SYSCR2: FLMCR1: FLMCR2: EBR1: EBR2: RAMER: System control register 2 Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Figure 19-7 Block Diagram of Flash Memory Rev.6.00 Oct.28.2004 page 575 of 1016 REJ09B0138-0600H 19.6.3 Flash Memory Operating Modes Mode Transitions: When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the MCU enters one of the operating modes shown in figure 19-8. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and programmer mode. MD2 = MD1 = 1 User mode with on-chip ROM enabled RES = 0 Reset state RES = 0 *1 RES = 0 *2 RES = 0 Programmer mode FWE = 1 FWE = 0 User program mode Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. MD2 = MD1 = MD0 = 0, P66 = 1, P65 = P64 = 0 2. NMI = 1, FWE = 1, MD2 = 0, MD1 = 1 Figure 19-8 Flash Memory Mode Transitions Rev.6.00 Oct.28.2004 page 576 of 1016 REJ09B0138-0600H On-Board Programming Modes • Boot mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the H8S/2357 chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host   
", !      ! Host Programming control program New application program New application program H8S/2357 Group chip Boot program H8S/2357 Group chip Boot program SCI SCI Flash memory RAM Flash memory RAM Boot program area Programming control program Application program (old version) Application program (old version) 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, entire flash memory erasure is performed, without regard to blocks. Host 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host New application program H8S/2357 Group chip Boot program H8S/2357 Group chip Boot program SCI SCI Flash memory RAM Flash memory RAM Boot program area Programming control program Boot program area Programming control program Flash memory erase New application program Program execution state Figure 19-9 Boot Mode Rev.6.00 Oct.28.2004 page 577 of 1016 REJ09B0138-0600H • User program mode 1. Initial state (1) The FWE assessment program that confirms that the FWE pin has been driven high, and (2) the program that will transfer the programming/ erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (3) The programming/erase control program should be prepared in the host or in the flash memory. Host Programming/ erase control program New application program 2. Programming/erase control program transfer When the FWE pin is driven high, user software confirms this fact, executes the transfer program in the flash memory, and transfers the programming/erase control program to RAM.  
 , , !  Host New application program H8S/2357 Group chip Boot program H8S/2357 Group chip Boot program SCI SCI Flash memory RAM Flash memory RAM FWE assessment program FWE assessment program Transfer program Transfer program Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. Host 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host New application program H8S/2357 Group chip Boot program H8S/2357 Group chip Boot program SCI SCI Flash memory RAM Flash memory RAM FWE assessment program Transfer program FWE assessment program Transfer program Programming/ erase control program Programming/ erase control program Flash memory erase New application program Program execution state Figure 19-10 User Program Mode (Example) Rev.6.00 Oct.28.2004 page 578 of 1016 REJ09B0138-0600H Flash Memory Emulation in RAM • Reading Overlap Data in User Mode and User Program Mode Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. SCI Flash memory Emulation block RAM Overlap RAM (emulation is performed on data written in RAM) Application program Execution state Figure 19-11 Reading Overlap Data in User Mode and User Program Mode • Writing Overlap Data in User Program Mode When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten. SCI Flash memory Programming data RAM Overlap RAM (programming data) Programming control program execution state Application program Figure 19-12 Writing Overlap Data in User Program Mode Rev.6.00 Oct.28.2004 page 579 of 1016 REJ09B0138-0600H Differences between Boot Mode and User Program Mode Table 19-9 Differences between Boot Mode and User Program Mode Boot Mode Entire memory erase Block erase Programming control program* Yes No Program/program-verify User Program Mode Yes Yes Program/program-verify Erase/erase-verify Note: * To be provided by the user, in accordance with the recommended algorithm. Block Configuration: The flash memory is divided into two 32-kbyte blocks, two 8-kbyte blocks, one 16-kbyte block, one 28-kbyte block, and four 1-kbyte blocks. Address H'00000 1 kbyte 1 kbyte 1 kbyte 1 kbyte 28 kbytes 16 kbytes 128 kbytes 8 kbytes 8 kbytes 32 kbytes 32 kbytes Address H'1FFFF Figure 19-13 Flash Memory Block Configuration Rev.6.00 Oct.28.2004 page 580 of 1016 REJ09B0138-0600H 19.6.4 Pin Configuration The flash memory is controlled by means of the pins shown in table 19-10. Table 19-10 Flash Memory Pins Pin Name Reset Flash write enable Mode 2 Mode 1 Mode 0 Port 66 Port 65 Port 64 Transmit data Receive data Abbreviation RES FWE MD2 MD1 MD0 P66 P65 P64 TxD1 RxD1 I/O Input Input Input Input Input Input Input Input Output Input Function Reset Flash program/erase protection by hardware Sets MCU operating mode Sets MCU operating mode Sets MCU operating mode Sets MCU operating mode in programmer mode Sets MCU operating mode in programmer mode Sets MCU operating mode in programmer mode Serial transmit data output Serial receive data input 19.6.5 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 19-11. In order for these registers to be accessed, the FLSHE bit must be set to 1 in SYSCR2 (except RAMER). Table 19-11 Flash Memory Registers Register Name Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 System control register 2 RAM emulation register Abbreviation R/W FLMCR1* 6 FLMCR2* 6 EBR1 * 6 EBR2 * 6 SYSCR2* 7 RAMER R/W*3 R/W*3 R/W*3 R/W*3 R/W R/W Initial Value H'00* 4 H'00* 5 H'00* 5 H'00* 5 H'00 H'00 Address* 1 H'FFC8 * 2 H'FFC9 * 2 H'FFCA * 2 H'FFCB * 2 H'FF42 H'FEDB Notes: 1. Lower 16 bits of the address. 2. Flash memory registers are selected by the FLSHE bit in system control register 2 (SYSCR2). 3. In modes in which the on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes are also disabled when the FWE bit is cleared to 0 in FLMCR1. 4. When a high level is input to the FWE pin, the initial value is H'80. 5. When a low level is input to the FWE pin, or if a high level is input and the SWE bit in FLMCR1 is not set, these registers are initialized to H'00. 6. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid for these registers, the access requiring 2 states. 7. SYSCR2 is available only in the F-ZTAT version. In the masked ROM and ZTAT versions, this register cannot be written to and will return an undefined value if read. Rev.6.00 Oct.28.2004 page 581 of 1016 REJ09B0138-0600H 19.7 19.7.1 Register Descriptions Flash Memory Control Register 1 (FLMCR1) Bit 7 FWE Initial value Read/Write —* R 6 SWE 0 R/W 5 — 0 — 4 — 0 — 3 EV 0 R/W 2 PV 0 R/W 1 E 0 R/W 0 P 0 R/W Note: * Determined by the state of the FWE pin. FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1. Program mode is entered by setting SWE to 1 when FWE = 1, then setting the PSU bit in FLMCR2, and finally setting the P bit. Erase mode is entered by setting SWE to 1 when FWE = 1, then setting the ESU bit in FLMCR2, and finally setting the E bit. FLMCR1 is initialized by a reset, and in hardware standby mode and software standby mode. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes to the SWE bit in FLMCR1 are enabled only when FWE = 1; writes to the EV and PV bits only when FWE=1 and SWE=1; writes to the E bit only when FWE = 1, SWE = 1, and ESU = 1; and writes to the P bit only when FWE = 1, SWE = 1, and PSU = 1. Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing. See section 19.14, Flash Memory Programming and Erasing Precautions, before using this bit. Bit 7 FWE 0 1 Description When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin Bit 6—Software Write Enable Bit (SWE): Enables or disables flash memory programming. SWE should be set before setting bits ESU, PSU, EV, PV, E, P, and EB9 to EB0, and should not be cleared at the same time as these bits. Bit 6 SWE 0 1 Description Writes disabled Writes enabled [Setting condition] When FWE = 1 (Initial value) Bits 5 and 4—Reserved: These bits cannot be modified and are always read as 0. Rev.6.00 Oct.28.2004 page 582 of 1016 REJ09B0138-0600H Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 EV 0 1 Description Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE = 1 (Initial value) Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time. Bit 2 PV 0 1 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] When FWE = 1 and SWE = 1 (Initial value) Bit 1—Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time. Bit 1 E 0 1 Description Erase mode cleared Transition to erase mode [Setting condition] When FWE = 1, SWE = 1, and ESU = 1 (Initial value) Bit 0—Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU, ESU, EV, PV, or E bit at the same time. Bit 0 P 0 1 Description Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 (Initial value) Rev.6.00 Oct.28.2004 page 583 of 1016 REJ09B0138-0600H 19.7.2 Flash Memory Control Register 2 (FLMCR2) Bit 7 FLER Initial value Read/Write 0 R 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 — 0 — 1 ESU 0 R/W 0 PSU 0 R/W FLMCR2 is an 8-bit register that monitors the presence or absence of flash memory program/erase protection (error protection) and performs setup for flash memory program/erase mode. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode. The ESU and PSU bits are cleared to 0 in software standby mode, hardware protect mode, and software protect mode. When on-chip flash memory is disabled, a read will return H'00. Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state. Bit 7 FLER 0 Description Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode 1 An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 19.10.3, Error Protection (Initial value) Bits 6 to 2—Reserved: These bits cannot be modified and are always read as 0. Bit 1—Erase Setup (ESU): Prepares for a transition to erase mode. Set this bit to 1 before setting the E bit to 1 in FLMCR1. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 1 ESU 0 1 Description Erase setup cleared Erase setup [Setting condition] When FWE = 1, and SWE = 1 (Initial value) Bit 0—Program Setup (PSU): Prepares for a transition to program mode. Set this bit to 1 before setting the P bit to 1 in FLMCR1. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time. Rev.6.00 Oct.28.2004 page 584 of 1016 REJ09B0138-0600H Bit 0 PSU 0 1 Description Program setup cleared Program setup [Setting condition] When FWE = 1, and SWE = 1 (Initial value) 19.7.3 Erase Block Registers 1 and 2 (EBR1, EBR2) Bit EBR1 Initial value Read/Write Bit EBR2 Initial value Read/Write 7 — 0 — 7 EB7 0 R/W 6 — 0 — 6 EB6 0 R/W 5 — 0 — 5 EB5 0 R/W 4 — 0 — 4 EB4 0 R/W 3 — 0 — 3 EB3 0 R/W 2 — 0 — 2 EB2 0 R/W 1 EB9 0 R/W 1 EB1 0 R/W 0 EB8 0 R/W 0 EB0 0 R/W EBR1 and EBR2 are registers that specify the flash memory erase area block by block; bits 1 and 2 in EBR1 and bits 7 to 0 in EBR2 are readable/writable bits. EBR1 and EBR2 are each initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set. When a bit in EBR1 or EBR2 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1 or EBR2 (more than one bit cannot be set). When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 19-12. Table 19-12 Flash Memory Erase Blocks Block (Size) EB0 (1 kbyte) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbyte) EB4 (28 kbytes) EB5 (16 kbytes) EB6 (8 kbytes) EB7 (8 kbytes) EB8 (32 kbytes) EB9 (32 kbytes) Address H'000000 to H'0003FF H'000400 to H'0007FF H'000800 to H'000BFF H'000C00 to H'000FFF H'001000 to H'007FFF H'008000 to H'00BFFF H'00C000 to H'00DFFF H'00E000 to H'00FFFF H'010000 to H'017FFF H'018000 to H'01FFFF Rev.6.00 Oct.28.2004 page 585 of 1016 REJ09B0138-0600H 19.7.4 System Control Register 2 (SYSCR2) Bit 7 — Initial value Read/Write 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 FLSHE 0 R/W 2 — 0 — 1 — 0 — 0 — 0 — SYSCR2 is an 8-bit readable/writable register that controls on-chip flash memory (in F-ZTAT versions). SYSCR2 is initialized to H'00 by a reset and in hardware standby mode. SYSCR2 is available only in the F-ZTAT version. In the masked ROM and ZTAT versions, this register cannot be written to and will return an undefined value if read. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0. Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Setting the FLSHE bit to 1 enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash memory control register contents are retained. Bit 3 FLSHE 0 1 Description Flash control registers deselected in area H'FFFFC8 to H'FFFFCB Flash control registers selected in area H'FFFFC8 to H'FFFFCB (Initial value) Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 0. 19.7.5 RAM Emulation Register (RAMER) RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. RAMER settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 19-13. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bit: 7 — 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 RAMS 0 R/W 1 RAM1 0 R/W 0 RAM0 0 R/W Initial value: R/W: 0 — Bits 7 to 3—Reserved: These bits are always read as 0. Rev.6.00 Oct.28.2004 page 586 of 1016 REJ09B0138-0600H Bit 2—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory block are program/erase-protected. Bit 2 RAMS 0 Description Emulation not selected Program/erase-protection of all flash memory blocks is disabled 1 Emulation selected Program/erase-protection of all flash memory blocks is enabled (Initial value) Bits 1 and 0—Flash Memory Area Selection (RAM1, RAM0): These bits are used together with bit 2 to select the flash memory area to be overlapped with RAM. (see table 19-13.) Table 19-13 Flash Memory Area Divisions Addresses H'FFDC00–H'FFDFFF H'000000–H'0003FF H'000400–H'0007FF H'000800–H'000BFF H'000C00–H'000FFF Block Name RAM area 1 kbyte EB0 (1 kbyte) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbyte) RAMS 0 1 1 1 1 RAM1 × 0 0 1 1 RAM0 × 0 1 0 1 ×: Don’t care Rev.6.00 Oct.28.2004 page 587 of 1016 REJ09B0138-0600H 19.8 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 19-14. For a diagram of the transitions to the various flash memory modes, see figure 19-8. Table 19-14 Setting On-Board Programming Modes Mode Mode Name Boot mode CPU Operating Mode Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode User program mode* Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode 1 1 1 FWE 1 MD2 0 MD1 1 MD0 0 1 0 1 Note: * Normally, user mode should be used. Set FWE to 1 to make a transition to user program mode before performing a program/erase/verify operation. 19.8.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2357 MCU’s pins have been set to boot mode, the boot program built into the MCU is started and the programming control program prepared in the host is serially transmitted to the MCU via the SCI. In the MCU, the programming control program received via the SCI is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 19-14, and the boot program mode execution procedure in figure 19-15. H8S/2357 chip Flash memory Host Write data reception Verify data transmission RxD1 SCI1 TxD1 On-chip RAM Figure 19-14 System Configuration in Boot Mode Rev.6.00 Oct.28.2004 page 588 of 1016 REJ09B0138-0600H Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate MCU measures low period of H'00 data transmitted by host MCU calculates bit rate and sets value in bit rate register After bit rate adjustment, MCU transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, MCU transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte MCU transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units MCU transmits received programming control program to host as verify data (echo-back) Transfer received programming control program to on-chip RAM No Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, MCU transmits one H'AA data byte to host Execute programming control program transferred to on-chip RAM n+1→n n = N? Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Figure 19-15 Boot Mode Execution Procedure Rev.6.00 Oct.28.2004 page 589 of 1016 REJ09B0138-0600H Automatic SCI Bit Rate Adjustment Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 19-16 Automatic SCI Bit Rate Adjustment When boot mode is initiated, the H8S/2357 MCU measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The MCU calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the MCU. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host’s transmission bit rate and the MCU’s system clock frequency, there will be a discrepancy between the bit rates of the host and the MCU. To ensure correct SCI operation, the host’s transfer bit rate should be set to (4,800, or 9,600) bps. Table 19-15 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the MCU’s bit rate is possible. The boot program should be executed within this system clock range. Table 19-15 System Clock Frequencies for which Automatic Adjustment of H8S/2357 Bit Rate is Possible Host Bit Rate 9600 bps 4800 bps System Clock Frequency for which Automatic Adjustment of H8S/2357 Bit Rate is Possible 8 to 20 MHz 4 to 20 MHz On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2 kbytes area from H'FFDC00 to H'FFE3FF is reserved for use by the boot program, as shown in figure 19-17. The area to which the programming control program is transferred is H'FFE400 to H'FFFB7F. The boot program area can be used when the programming control program transferred into RAM enters the execution state. A stack area should be set up as required. Rev.6.00 Oct.28.2004 page 590 of 1016 REJ09B0138-0600H H'FFDC00 H'FFE3FF Boot program area*1 (2 kbytes) Programming control program area (6 kbytes) H'FFFB7F H'FFFBFF (128 bytes)*2 Notes: 1. The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note that the boot program remains stored in this area after a branch is made to the programming control program. 2. The area from H'FFFB80 to H'FFFBFF (128 bytes) is used by the boot program. The area from H'FFE400 to H'FFFB7F can be used by the programming control program. Figure 19-17 RAM Areas in Boot Mode Notes on Use of User Mode: • When the chip comes out of reset in boot mode, it measures the low-level period of the input at the SCI’s RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period of the RxD1 pin. • In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. • Interrupts cannot be used while the flash memory is being programmed or erased. • The RxD1 and TxD1 pins should be pulled up on the board. • Before branching to the programming control program (RAM area H'FFE400), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD1, goes to the high-level output state (P31DDR = 1, P31DR = 1). The contents of the CPU’s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. Initial settings must also be made for the other on-chip registers. • Boot mode can be entered by making the pin settings shown in table 19-14 and executing a reset-start. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the FWE pin and mode pins, and executing reset release*1. Boot mode can also be cleared by a WDT overflow reset. Do not change the mode pin input levels in boot mode, and do not drive the FWE pin low while the boot program is being executed or while flash memory is being programmed or erased*2. Rev.6.00 Oct.28.2004 page 591 of 1016 REJ09B0138-0600H • If the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR) will change according to the change in the microcomputer’s operating mode*3. Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. Notes: 1. Mode pins and FWE pin input must satisfy the mode programming setup time (tMDS = 200 ns) with respect to the reset release timing, as shown in figures 19-33 to 19-35. 2. For further information on FWE application and disconnection, see section 19.14, Flash Memory Programming and Erasing Precautions. 3. See Appendix D, Pin States. 19.8.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing onboard means of FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary. To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7), and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7. The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM or external memory. Figure 19-18 shows the procedure for executing the program/erase control program when transferred to on-chip RAM. Rev.6.00 Oct.28.2004 page 592 of 1016 REJ09B0138-0600H Write the FWE assessment program and transfer program (and the program/erase control program if necessary) beforehand MD2, MD1, MD0 = 110, 111 Reset-start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area FWE = high* Execute program/erase control program (flash memory rewriting) Clear FWE* Branch to flash memory application program Notes: Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only when the flash memory is programmed or erased. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * For further information on FWE application and disconnection, see section 19.14, Flash Memory Programming and Erasing Precautions. Figure 19-18 User Program Mode Execution Procedure Rev.6.00 Oct.28.2004 page 593 of 1016 REJ09B0138-0600H 19.9 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased. Therefore, the program that controls flash memory programming/erasing (the programming control program) should be located and executed in on-chip RAM or external memory. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, EV, PV, E, and P bits in FLMCR1, and the ESU and PSU bits in FLMCR2, is executed by a program in flash memory. 2. When programming or erasing, set FWE to 1 (programming/erasing will not be executed if FWE = 0). 3. Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. 19.9.1 Program Mode Follow the procedure shown in the program/program-verify flowchart in figure 19-19 to write data or programs to flash memory. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 32 bytes at a time. The wait times (x, y, z, α, ß, γ, ε, η) after bits are set or cleared in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of programming operations (N) are shown in table 22.42 in section 22.7.6, Flash Memory Characteristics. Following the elapse of (x) µs or more after the SWE bit is set to 1 in flash memory control register 1 (FLMCR1), 32-byte program data is stored in the program data area and reprogram data area, and the 32-byte data in the reprogram data area written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. Thirty-two consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 32-byte data transfer must be performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than (y + z + α + ß) µs as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU bit in FLMCR2, and after the elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory programming time. Make a program setting so that the time for one programming operation is within the range of (z) µs. 19.9.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of a given programming time, the programming mode is exited (the P bit in FLMCR1 is cleared to 0, then the PSU bit in FLMCR2 is cleared to 0 at least (α) µs later). Next, the watchdog timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to program-verify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure Rev.6.00 Oct.28.2004 page 594 of 1016 REJ09B0138-0600H 19-19) and transferred to the reprogram data area. After 32 bytes of data have been verified, exit program-verify mode, wait for at least (η) µs, then clear the SWE bit in FLMCR1 to 0. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits. Start Set SWE bit in FLMCR1 Wait (x) µs Store 32-byte program data in program data area and reprogram data area n=1 m=0 Write 32-byte data in RAM reprogram data area consecutively to flash memory Enable WDT Set PSU bit in FLMCR2 Wait (y) µs Set P bit in FLMCR1 Wait (z) µs Clear P bit in FLMCR1 Wait (α) µs Clear PSU bit in FLMCR2 Wait (β) µs Disable WDT Set PV bit in FLMCR1 Wait (γ) µs H'FF dummy write to verify address Wait (ε) µs Read verify data Increment address Program data = verify data? OK Reprogram data computation Transfer reprogram data to reprogram data area NG End of 32-byte data verification? OK Clear PV bit in FLMCR1 Wait (η) µs m = 0? OK Clear SWE bit in FLMCR1 End of programming *5 *3 *5 *5 *5 *5 *1 *5 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. *4 n←n+1 Start of programming *5 End of programming *5 Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. A 32-byte data transfer must be performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (word) units. 3. Even bits for which programming has been completed in a 32-byte programming loop will be subjected to additional programming if the subsequent verify operation fails. 4. An area for storing program data (32 bytes) and reprogram data (32 bytes) must be provided in RAM. The contents of the latter are rewritten as programming progresses. 5. The values of x, y, z, α, β, γ, ε, η, and N are shown in section 22.7.6, Flash Memory Characteristics. Program Verify Reprogram Comments Data Data Data 0 0 1 Programmed bits are not reprogrammed 0 1 0 1 0 1 1 Programming incomplete; reprogram — Still in erased state; no action *2 1 NG m=1 *3 1 Note: The memory erased state is 1. Programming is performed on 0 reprogram data. RAM Program data storage area (32 bytes) *4 Reprogram data storage area (32 bytes) n ≥ N? *5 NG NG OK Clear SWE bit in FLMCR1 Programming failure Figure 19-19 Program/Program-Verify Flowchart Rev.6.00 Oct.28.2004 page 595 of 1016 REJ09B0138-0600H 19.9.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 19-20. The wait times (x, y, z, α, ß, γ, ε, η) after bits are set or cleared in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of programming operations (N) are shown in table 22.42 in section 22.7.6, Flash Memory Characteristics. To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in erase block register 1 or 2 (EBR1 or EBR2) at least (x) µs after setting the SWE bit to 1 in flash memory control register 1 (FLMCR1). Next, the watchdog timer is set to prevent overerasing in the event of program runaway, etc. Set a value greater than (y + z + α + ß) µs as the WDT overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the ESU bit in FLMCR2, and after the elapse of (y) µs or more, the operating mode is switched to erase mode by setting the E bit in FLMCR1. The time during which the E bit is set is the flash memory erase time. Ensure that the erase time does not exceed (z) ms. Note: With flash memory erasing, preprogramming (setting all data in the memory to be erased to 0) is not necessary before starting the erase procedure. 19.9.4 Erase-Verify Mode In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared to 0, then the ESU bit in FLMCR2 is cleared to 0 at least (α) µs later), the watchdog timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to erase-verify mode by setting the EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of ( γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data has not been erased, set erase mode again, and repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/eraseverify sequence is not repeated more than (N) times. When verification is completed, exit erase-verify mode, and wait for at least (η) µs. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1 to 0. If there are any unerased blocks, make a 1 bit setting in EBR1 or EBR2 for the flash memory area to be erased, and repeat the erase/eraseverify sequence in the same way. Rev.6.00 Oct.28.2004 page 596 of 1016 REJ09B0138-0600H Start *1 Set SWE bit in FLMCR1 Wait (x) µs n=1 Set EBR1, EBR2 Enable WDT Set ESU bit in FLMCR2 Wait (y) µs Set E bit in FLMCR1 Wait (z) ms Clear E bit in FLMCR1 Wait (α) µs Clear ESU bit in FLMCR2 Wait (β) µs Disable WDT Set EV bit in FLMCR1 Wait (γ) µs Set block start address to verify address *2 *2 *2 *4 *2 Start of erase *2 Halt erase *2 n←n+1 H'FF dummy write to verify address Wait (ε) µs Increment address Read verify data Verify data = all 1? OK NG Last address of block? OK Clear EV bit in FLMCR1 Wait (η) µs *2 *2 *3 NG Clear EV bit in FLMCR1 Wait (η) µs *2 *2 NG *5 End of erasing of all erase blocks? OK n ≥ N? OK Clear SWE bit in FLMCR1 Erase failure NG Clear SWE bit in FLMCR1 End of erasing Notes: 1. 2. 3. 4. 5. Preprogramming (setting erase block data to all 0) is not necessary. The values of x, y, z, α, β, γ, ε, η, and N are shown in section 22.7.6, Flash Memory Characteristics. Verify data is read in 16-bit (W) units. Set only one bit in EBR1or EBR2. More than one bit cannot be set. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially. Figure 19-20 Erase/Erase-Verify Flowchart (Single-Block Erase) Rev.6.00 Oct.28.2004 page 597 of 1016 REJ09B0138-0600H 19.10 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.10.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2). (See table 19-16.) Table 19-16 Hardware Protection Functions Item FWE pin protection Description • When a low level is input to the FWE pin, FLMCR1, FLMCR2 (excluding the FLER bit), EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. In a reset (including a WDT overflow reset) and in standby mode, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. Program Yes Erase Yes Reset/standby protection • Yes Yes • Rev.6.00 Oct.28.2004 page 598 of 1016 REJ09B0138-0600H 19.10.2 Software Protection Software protection can be implemented by setting the SWE bit in FLMCR1, erase block registers 1 and 2 (EBR1, EBR2), and the RAMS bit in RAMER. When software protection is in effect, setting the P or E bit in flash memory control register 1 (FLMCR1) does not cause a transition to program mode or erase mode. (See table 19-17.) Table 19-17 Software Protection Functions Item SWE bit protection Description • Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks. (Execute in on-chip RAM or external memory.) Block specification protection • Erase protection can be set for individual blocks by settings in erase block registers 1 and 2 (EBR1, EBR2). Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state. Setting the RAMS bit to 1 in the RAM emulation register (RAMER) places all blocks in the program/erase-protected state. Yes Yes — Yes Program Yes Erase Yes • Emulation protection • 19.10.3 Error Protection In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. FLER bit setting conditions are as follows: • • • • When flash memory is read during programming/erasing (including a vector read or instruction fetch) Immediately after exception handling (excluding a reset) during programming/erasing When a SLEEP instruction (including software standby) is executed during programming/erasing When the CPU loses the bus during programming/erasing Error protection is released only by a reset and in hardware standby mode. Figure 19-21 shows the flash memory state transition diagram. Rev.6.00 Oct.28.2004 page 599 of 1016 REJ09B0138-0600H Normal Operating mode Program mode Erase mode RES = 0 or STBY = 0 Reset or hardware standby (hardware protection) RD VF PR ER FLER = 0 Error occurrence (software standby) Error occurrence RES = 0 or STBY = 0 RD VF PR ER FLER = 0 FLMCR1, FLMCR2, EBR1, EBR2 initialization state RES = 0 or STBY = 0 Error protection mode RD VF PR ER FLER = 1 Software standby mode Software standby mode release Error protection mode (software standby) RD VF PR ER FLER = 1 FLMCR1, FLMCR2 (except FLER bit), EBR1, EBR2 initialization state Legend: RD: Memory read possible VF: Verify-read possible PR: Programming possible ER: Erasing possible RD: VF: PR: ER: Memory read not possible Verify-read not possible Programming not possible Erasing not possible Figure 19-21 Flash Memory State Transitions Rev.6.00 Oct.28.2004 page 600 of 1016 REJ09B0138-0600H 19.11 19.11.1 Flash Memory Emulation in RAM Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses can be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 19-22 shows an example of emulation of real-time flash memory programming. Start emulation program Set RAMER Write tuning data to overlap RAM Execute application program No Tuning OK? Yes Clear RAMER Write to flash memory emulation block End of emulation program Figure 19-22 Flowchart for Flash Memory Emulation in RAM Rev.6.00 Oct.28.2004 page 601 of 1016 REJ09B0138-0600H 19.11.2 RAM Overlap An example in which flash memory block area EB1 is overlapped is shown below. H'000000 H'000400 H'000800 H'000C00 EB0 EB1 EB2 EB3 This area can be accessed from both the RAM area and flash memory area Flash memory EB4 to EB9 H'FFDC00 H'FFDFFF On-chip RAM Figure 19.23 Example of RAM Overlap Operation Example in Which Flash Memory Block Area (EB1) is Overlapped 1. Set bits RAMS, RAM1, and RAM0 in RAMER to 1, 0, 1, to overlap part of RAM onto the area (EB1) for which realtime programming is required. 2. Real-time programming is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB1). Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of RAM1 and RAM0 (emulation protection). In this state, setting the P or E bit in flash memory control register 1 (FLMCR1) will not cause a transition to program mode or erase mode. When actually programming a flash memory area, the RAMS bit should be cleared to 0. 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 includes the vector table. When performing RAM emulation, the vector table is needed by the overlap RAM. Rev.6.00 Oct.28.2004 page 602 of 1016 REJ09B0138-0600H 19.12 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI interrupt is disabled when flash memory is being programmed or erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode* 1, to give priority to the program or erase operation. There are three reasons for this: 1. Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly*2, possibly resulting in MCU runaway. 3. If interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, in on-board programming mode alone there are conditions for disabling interrupt, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All requests, including NMI interrupt, must therefore be restricted inside and outside the MCU when programming or erasing flash memory. NMI interrupt is also disabled in the error-protection state while the P or E bit remains set in FLMCR1. Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming control program has completed programming. 2. The vector may not be read correctly in this case for the following two reasons: • If flash memory is read while being programmed or erased (while the P or E bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned). • If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. Rev.6.00 Oct.28.2004 page 603 of 1016 REJ09B0138-0600H 19.13 19.13.1 Flash Memory Programmer Mode Programmer Mode Setting Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports Renesas Technology microcomputer device types with 128-kbyte on-chip flash memory. Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. Table 19-18 shows programmer mode pin settings. Table 19-18 Programmer Mode Pin Settings Pin Names Mode pins: MD 2, MD1, MD0 Mode setting pins: P66, P65, P64 FWE pin STBY pin RES pin XTAL, EXTAL pins Other pins requiring setting: P51, P25 Settings/External Circuit Connection Low-level input High-level input to P66, low-level input to P65 and P64 High-level input (in auto-program and auto-erase modes) High-level input (do not select hardware standby mode) Power-on reset circuit Oscillator circuit High-level input to P51 and P25 19.13.2 Socket Adapters and Memory Map In programmer mode, a socket adapter is mounted on the PROM programmer to match the package concerned. Socket adapters are available for each writer manufacturer supporting the Renesas Technology microcomputer device type with 128-kbyte on-chip flash memory. Figure 19-24 shows the memory map in programmer mode. For pin names in programmer mode, see section 1.3.2, Pin Functions in Each Operating Mode. MCU mode H'000000 On-chip ROM area H'01FFFF H'1FFFF H8S/2357 F-ZTAT Programmer mode H'00000 Figure 19-24 Memory Map in Programmer Mode Rev.6.00 Oct.28.2004 page 604 of 1016 REJ09B0138-0600H 19.13.3 Programmer Mode Operation Table 19-19 shows how the different operating modes are set when using programmer mode, and table 19-20 lists the commands used in programmer mode. Details of each mode are given below. • Memory Read Mode Memory read mode supports byte reads. • Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of autoprogramming. • Auto-Erase Mode Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-erasing. • Status Read Mode Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the I/O6 signal. In status read mode, error information is output if an error occurs. Table 19-19 Settings for Each Operating Mode in Programmer Mode Pin Names Mode Read Output disable Command write Chip disable * 1 Legend: H: High level L: Low level Hi-Z: High impedance ×: Don’t care Notes: * 1 Chip disable is not a standby state; internally, it is an operation state. * 2 Ain indicates that there is also address input in auto-program mode. * 3 For command writes when making a transition to auto-program or auto-erase mode, input a high level to the FWE pin. FWE H or L H or L H or L* H or L 3 CE L L L H OE L H H × WE H H L × I/O0 to I/O7 Data output Hi-Z Data input Hi-Z A0 to A16 Ain × Ain* 2 × Rev.6.00 Oct.28.2004 page 605 of 1016 REJ09B0138-0600H Table 19-20 Programmer Mode Commands Number of Cycles 1+n 129 2 2 1st Cycle Mode Write Write Write Write Address Data × × × × H'00 H'40 H'20 H'71 Mode Read Write Write Write 2nd Cycle Address Data RA PA × × Dout Din H'20 H'71 Command Name Memory read mode Auto-program mode Auto-erase mode Status read mode Legend: RA: Read address PA: Program address ×: Don’t care Notes: 1. In auto-program mode. 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n). 19.13.4 Memory Read Mode • After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed. • Command writes can be performed in memory read mode, just as in the command wait state. • Once memory read mode has been entered, consecutive reads can be performed. • After power-on, memory read mode is entered. Table 19-21 AC Characteristics in Memory Read Mode Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol t nxtc t ceh t ces t dh t ds t wep tr tf Min 20 0 0 50 50 70 — — Max — — — — — — 30 30 Unit µs ns ns ns ns ns ns ns Rev.6.00 Oct.28.2004 page 606 of 1016 REJ09B0138-0600H Command write Address Memory read mode Address stable CE OE WE Data twep tceh tnxtc tces tf tr H'00 tdh tds Data Note: Data is latched on the rising edge of WE. Figure 19-25 Memory Read Mode Timing Waveforms after Command Write Table 19-22 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol t nxtc t ceh t ces t dh t ds t wep tr tf Min 20 0 0 50 50 70 — — Max — — — — — — 30 30 Unit µs ns ns ns ns ns ns ns Rev.6.00 Oct.28.2004 page 607 of 1016 REJ09B0138-0600H ×× mode command write Address Address stable CE OE WE Data tnxtc tces tf twep tceh tr H'×× tdh Data Note: Do not enable WE and OE at the same time. tds Figure 19-26 Timing Waveforms when Entering Another Mode from Memory Read Mode Table 19-23 AC Characteristics in Memory Read Mode Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C Item Access time CE output delay time OE output delay time Output disable delay time Data output hold time Symbol t acc t ce t oe t df t oh Min — — — — 5 Max 20 150 150 100 — Unit µs ns ns ns ns Address Address stable Address stable VIL tacc VIL VIH CE OE WE tacc Data Data toh Data toh Figure 19-27 Timing Waveforms for CE/OE Enable State Read Rev.6.00 Oct.28.2004 page 608 of 1016 REJ09B0138-0600H Address Address stable Address stable tacc CE tce toe tce toe VIH OE WE tacc Data tdf Data toh Data tdf toh Figure 19-28 Timing Waveforms for CE/OE Clocked Read 19.13.5 Auto-Program Mode AC Characteristics Table 19-24 AC Characteristics in Auto-Program Mode Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Address setup time Address hold time Memory write time WE rise time WE fall time Write setup time Write end setup time Symbol t nxtc t ceh t ces t dh t ds t wep t wsts t spa t as t ah t write tr tf t pns t pnh Min 20 0 0 50 50 70 1 — 0 60 1 — — 100 100 Max — — — — — — — 150 — — 3000 30 30 — — Unit µs ns ns ns ns ns ms ns ns ns ms ns ns ns ns Rev.6.00 Oct.28.2004 page 609 of 1016 REJ09B0138-0600H FWE Address tpns Address stable tpnh tceh CE tnxtc OE twep WE tces tf I/O7 tds tdh I/O6 Data H'40 tas tah tnxtc Data transfer 1 byte to 128 bytes twsts tspa twrite (1 to 3000 ms) Programming operation end identification signal tr Programming normal end identification signal Programming wait Data Data I/O0 to I/O5 = 0 Figure 19-29 Auto-Program Mode Timing Waveforms Notes on Use of Auto-Program Mode • In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. • A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. • The lower 8 bits of the transfer address must be H'00 or H'80. If a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. • Memory address transfer is performed in the second cycle (figure 19-29). Do not perform memory address transfer after the second cycle. • Do not perform a command write during a programming operation. • Perform one auto-programming operation for a 128-byte block for each address. Characteristics are not guaranteed for two or more programming operations. • Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-program operation end identification pin). • The status polling I/O6 and I/O7 pin information is retained until the next command write. Until the next command write is performed, reading is possible by enabling CE and OE. Rev.6.00 Oct.28.2004 page 610 of 1016 REJ09B0138-0600H 19.13.6 Auto-Erase Mode AC Characteristics Table 19-25 AC Characteristics in Auto-Erase Mode Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Memory erase time WE rise time WE fall time Erase setup time Erase end setup time Symbol t nxtc t ceh t ces t dh t ds t wep t ests t spa t erase tr tf t ens t enh Min 20 0 0 50 50 70 1 — 100 — — 100 100 Max — — — — — — — 150 40000 30 30 — — Unit µs ns ns ns ns ns ms ns ms ns ns ns ns FWE tens Address tces CE tspa OE WE I/O7 I/O6 CLin Data H'20 DLin H'20 I/O0 to I/O5 = 0 twep tf tds tdh tr tnxtc tests terase (100 to 40000 ms) Erase end identification signal Erase normal end confirmation signal tenh tceh tnxtc Figure 19-30 Auto-Erase Mode Timing Waveforms Notes on Use of Auto-Erase Mode • Auto-erase mode supports only entire memory erasing. • Do not perform a command write during auto-erasing. • Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O 7 status polling uses the auto-erase operation end identification pin). Rev.6.00 Oct.28.2004 page 611 of 1016 REJ09B0138-0600H • The status polling I/O6 and I/O7 pin information is retained until the next command write. Until the next command write is performed, reading is possible by enabling CE and OE. 19.13.7 Status Read Mode • Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. • The return code is retained until a command write for other than status read mode is performed. Table 19-26 AC Characteristics in Status Read Mode Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width OE output delay time Disable delay time CE output delay time WE rise time WE fall time Symbol t nxtc t ceh t ces t dh t ds t wep t oe t df t ce tr tf Min 20 0 0 50 50 70 — — — — — Max — — — — — — 150 100 150 30 30 Unit µs ns ns ns ns ns ns ns ns ns ns Address CE tce OE twep WE tces tf tds tdh Data H'71 tceh tr tnxtc tces tf tds tdh H'71 Data twep tceh tr tnxtc toe tnxtc tdf Note: I/O2 and I/O3 are undefined. Figure 19-31 Status Read Mode Timing Waveforms Rev.6.00 Oct.28.2004 page 612 of 1016 REJ09B0138-0600H Table 19-27 Status Read Mode Return Commands Pin Name I/O 7 Attribute I/O 6 I/O 5 Programming error I/O 4 Erase error I/O 3 — I/O 2 — I/O 1 I/O 0 Normal Command end error identification 0 Command error: 1 ProgramEffective ming or address error erase count exceeded 0 0 Initial value 0 Indications Normal end: 0 Abnormal end: 1 0 0 0 0 — ProgramErase — ming error: 1 Otherwise: 0 error: 1 Otherwise: 0 Otherwise: 0 Count Effective exceeded: 1 address Otherwise: 0 error: 1 Otherwise: 0 Note: I/O2 and I/O3 are undefined. 19.13.8 Status Polling • The I/O7 status polling flag indicates the operating status in auto-program or auto-erase mode. • The I/O6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase mode. Table 19-28 Status Polling Output Truth Table Pin Names I/O7 I/O6 I/O0 to I/O 5 Internal Operation in Progress 0 0 0 Abnormal End 1 0 0 — 0 1 0 Normal End 1 1 0 19.13.9 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 19-29 Command Wait State Transition Time Specifications Item Standby release (oscillation stabilization time) Programmer mode setup time VCC hold time Symbol t osc1 t bmv t dwn Min 10 10 0 Max — — — Unit ms ms ms Rev.6.00 Oct.28.2004 page 613 of 1016 REJ09B0138-0600H VCC RES FWE tosc1 tbmv Memory read Auto-program mode mode Auto-erase mode Command wait state tdwn Command Don't care wait state Normal/ abnormal end identification Don't care Note: Except in auto-program mode and auto-erase mode, drive the FWE input pin low. Figure 19-32 Oscillation Stabilization Time, Programmer Mode Setup Time, and Power Supply Fall Sequence 19.13.10 Notes on Memory Programming • When programming addresses which have previously been programmed, carry out auto-erasing before autoprogramming. • When performing programming using PROM mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. 19.14 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode, the RAM emulation function, and PROM mode are summarized below. Use the specified voltages and timing for programming and erasing: Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports Renesas Technology microcomputer device types with 128-kbyte on-chip flash memory. Do not select the HN28F101 setting for the PROM programmer, and only use the specified socket adapter. Incorrect use will result in damaging the device. Powering on and off (see figures 19-33 to 19-35): Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low before turning off VCC. When applying or disconnecting VCC, fix the FWE pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. FWE application/disconnection (see figures 19-33 to 19-35): FWE application should be carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection state. The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: • Apply FWE when the VCC voltage has stabilized within its rated voltage range. Apply FWE when oscillation has stabilized (after the elapse of the oscillation settling time). • In boot mode, apply and disconnect FWE during a reset. Rev.6.00 Oct.28.2004 page 614 of 1016 REJ09B0138-0600H • In user program mode, FWE can be switched between high and low level regardless of the reset state. FWE input can also be switched during program execution in flash memory. • Do not apply FWE if program runaway has occurred. • Disconnect FWE only when the SWE, ESU, PSU, EV, PV, P, and E bits in FLMCR1 and FLMCR2 are cleared. • Make sure that the SWE, ESU, PSU, EV, PV, P, and E bits are not set by mistake when applying or disconnecting FWE. Do not apply a constant high level to the FWE pin: Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. Use the recommended algorithm when programming and erasing flash memory: The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. Do not set or clear the SWE bit during program execution in flash memory: Clear the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten, but flash memory should only be accessed for verify operations (verification during programming/erasing). Similarly, when using the RAM emulation function while a high level is being input to the FWE pin, the SWE bit must be cleared before executing a program or reading data in flash memory. However, the RAM area overlapping flash memory space can be read and written to regardless of whether the SWE bit is set or cleared. Do not use interrupts while flash memory is being programmed or erased: All interrupt requests, including NMI, should be disabled during FWE application to give priority to program/erase operations. Do not perform additional programming. Erase the memory before reprogramming. In on-board programming, perform only one programming operation on a 32-byte programming unit block. In PROM mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. Before programming, check that the chip is correctly mounted in the PROM programmer. Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. Do not touch the socket adapter or chip during programming. Touching either of these can cause contact faults and write errors. Rev.6.00 Oct.28.2004 page 615 of 1016 REJ09B0138-0600H Wait time: x Programming and erase possible φ t OSC1 VCC min 0 µs FWE t MDS* 3 min 0 µs MD2 to MD0 * 1 t MDS* 3 RES SWE set SWE clear SWE bit Flash memory access disabled period (x: Wait time after SWE setting) * 2 Flash memory reprogrammable period (Flash memory program execution and data read, other than verify, are disabled.) Notes: Always fix the level by pulling down or pulling up the mode pins (MD2 to MD0) until powering off, except for mode switching. See section 22.7.6, Flash Memory Characteristics. Mode programming setup time tMDS (min) = 200 ns 1. 2. 3. Figure 19-33 Powering On/Off Timing (Boot Mode) Rev.6.00 Oct.28.2004 page 616 of 1016 REJ09B0138-0600H Wait time: x Programming and erase possible φ t OSC1 VCC min 0 µs FWE MD 2 to MD 0 * 1 t MDS* 3 RES SWE set SWE clear SWE bit Flash memory access disabled period (x: Wait time after SWE setting) * 2 Flash memory reprogrammable period (Flash memory program execution and data read, other than verify, are disabled.) Notes: Always fix the level by pulling down or pulling up the mode pins (MD2 to MD0) up to powering off, except for mode switching. See section 22.7.6, Flash Memory Characteristics. Mode programming setup time tMDS (min) = 200 ns 1. 2. 3. Figure 19-34 Powering On/Off Timing (User Program Mode) Rev.6.00 Oct.28.2004 page 617 of 1016 REJ09B0138-0600H Programming and Wait time: x erase possible Programming and Wait erase Wait time: x possible time: x Programming and erase possible Wait time: x Programming and erase possible φ t OSC1 VCC min 0µs FWE t MDS t MDS *2 MD 2 to MD 0 t MDS tRESW RES SWE set SWE clear SWE bit User program mode Mode switching * 1 Boot mode Mode User switching * 1 mode User program mode User mode Flash memory access disabled period (x: Wait time after SWE setting) * 3 Flash memory reprogammable period (Flash memory program execution and data read, other than verify, are disabled.) Notes: 1. In transition to the boot mode and transition from the boot mode to another mode, mode switching via RES input is necessary. During this switching period (period during which a low level is input to the RES pin), the state of the address dual port and bus control output signals (AS,RD,WR) changes. Therefore, do not use these pins as output signals during this switching period. 2. When making a transition from the boot mode to another mode, the mode programming setup time tMDS (min)= 200 ns relative to the RES clear timing is necessary. 3. See section 22.7.6, Flash Memory Characteristics. Figure 19-35 Mode Transition Timing (Example: Boot mode → User mode ↔ User program mode) Rev.6.00 Oct.28.2004 page 618 of 1016 REJ09B0138-0600H 19.15 19.15.1 Overview of Flash Memory (H8S/2398 F-ZTAT) Features The H8S/2398 F-ZTAT have 256 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode  Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in single-block units). To erase the entire flash memory, the individual blocks must be erased sequentially. Block erasing can be performed as required on 4-kbyte, 32-kbyte, and 64-kbyte blocks. • Programming/erase times The flash memory programming time is 10 ms (typ.) for simultaneous 128-byte programming, equivalent to 78 µs (typ.) per byte, and the erase time is 50 ms (typ.). • Reprogramming capability Depending on the product, the maximum number of times the flash memory can be reprogrammed is either 100 or 1,000.  Reprogrammable up to 100 times: HD64F2398TE, HD64F2398F  Reprogrammable up to 1,000 times: HD64F2398TET, HD64F2398FT • On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board:  Boot mode  User program mode • Automatic bit rate adjustment With data transfer in boot mode, the bit rate of the chip can be automatically adjusted to match the transfer bit rate of the host. • Flash memory emulation by RAM Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates in real time. • Protect modes There are three protect modes, hardware, software, and error protect, which allow protected status to be designated for flash memory program/erase/verify operations. • Programmer mode Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode. Rev.6.00 Oct.28.2004 page 619 of 1016 REJ09B0138-0600H 19.15.2 Overview Block Diagram Internal address bus Internal data bus (16 bits) Module bus FLMCR1 FLMCR2 EBR1 EBR2 RAMER SYSCR2 Flash memory (256 kbytes) Bus interface/controller Operating mode Mode pins Legend: FLMCR1: FLMCR2: EBR1: EBR2: RAMER: SYSCR2: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register System control register 2 Figure 19-36 Block Diagram of Flash Memory Rev.6.00 Oct.28.2004 page 620 of 1016 REJ09B0138-0600H 19.15.3 Flash Memory Operating Modes Mode Transitions: When the mode pins are set in the reset state and a reset-start is executed, the chip enters one of the operating modes shown in figure 19-37. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and PROM mode. MD1 = 1, MD2 = 1 User mode (on-chip ROM enabled) RES = 0 Reset state RES = 0 RES = 0 MD1 = 1, MD2 = 0 * RES = 0 SWE = 1 SWE = 0 Programmer mode User program mode Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. * MD0 = 0, MD1 = 0, MD2 = 0, P66 = 1, P65 = 0, P64 = 0 Figure 19-37 Flash Memory Mode Transitions Rev.6.00 Oct.28.2004 page 621 of 1016 REJ09B0138-0600H 19.15.4 On-Board Programming Modes • Boot mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host    ! ",    Host Programming control program New application program New application program Chip Chip Boot program SCI Boot program SCI Flash memory RAM Flash memory RAM Boot program area Programming control program Application program (old version) Application program (old version) 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, entire flash memory erasure is performed, without regard to blocks. Host 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host New application program Chip Chip Boot program SCI Boot program SCI Flash memory RAM Flash memory RAM Boot program area Programming control program Boot program area Programming control program Flash memory prewrite-erase New application program Program execution state Figure 19-38 Boot Mode Rev.6.00 Oct.28.2004 page 622 of 1016 REJ09B0138-0600H • User program mode 1. Initial state (1) The program that will transfer the programming/erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory. Host 2. Programming/erase control program transfer Executes the transfer program in the flash memory, and transfers the programming/erase control program to RAM.  
, 
, !  Host Programming/ erase control program New application program New application program Chip Chip Boot program SCI Boot program SCI Flash memory RAM Flash memory RAM Transfer program Transfer program Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. Host 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host New application program Chip Chip Boot program SCI Boot program SCI Flash memory RAM Flash memory RAM Transfer program Transfer program Programming/ erase control program Programming/ erase control program Flash memory erase New application program Program execution state Figure 19-39 User Program Mode (Example) Rev.6.00 Oct.28.2004 page 623 of 1016 REJ09B0138-0600H 19.15.5 Flash Memory Emulation in RAM Reading Overlap RAM Data in User Mode and User Program Mode: Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. SCI Flash memory Emulation block RAM Overlap RAM (emulation is performed on data written in RAM) Application program Execution state Figure 19-40 Reading Overlap RAM Data in User Mode and User Program Mode Writing Overlap RAM Data in User Program Mode: When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten. SCI Flash memory Programming data RAM Overlap RAM (programming data) Programming control program Execution state Application program Figure 19-41 Writing Overlap RAM Data in User Program Mode Rev.6.00 Oct.28.2004 page 624 of 1016 REJ09B0138-0600H 19.15.6 Differences between Boot Mode and User Program Mode Table 19-30 Differences between Boot Mode and User Program Mode Boot Mode Entire memory erase Block erase Programming control program* Yes No Program/program-verify User Program Mode Yes Yes Erase/erase-verify/program/ program-verify/emulation Note: * To be provided by the user, in accordance with the recommended algorithm. 19.15.7 Block Configuration Products include 256 kbytes of flash memory are divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4kbyte blocks. Address H'00000 4 kbytes × 8 32 kbytes 256 kbytes 64 kbytes 64 kbytes 64 kbytes Address H'3FFFF Figure 19-42 Flash Memory Block Configuration Rev.6.00 Oct.28.2004 page 625 of 1016 REJ09B0138-0600H 19.15.8 Pin Configuration The flash memory is controlled by means of the pins shown in table 19-31. Table 19-31 Flash Memory Pins Pin Name Reset Mode 2 Mode 1 Mode 0 Port 66 Port 65 Port 64 Transmit data Receive data Abbreviation RES MD2 MD1 MD0 P66 P65 P64 TxD1 RxD1 I/O Input Input Input Input Input Input Input Output Input Function Reset Sets MCU operating mode Sets MCU operating mode Sets MCU operating mode Sets MCU operating mode in programmer mode Sets MCU operating mode in programmer mode Sets MCU operating mode in programmer mode Serial transmit data output Serial receive data input 19.15.9 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 19-32. In order to access the FLMCR1, FLMCR2, EBR1, and EBR2 registers, the FLSHE bit must be set to 1 in SYSCR2 (except RAMER). Table 19-32 Flash Memory Registers Register Name Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 System control register 2 RAM emulation register Notes: 1. 2. 3. 4. 5. Abbreviation R/W FLMCR1* 5 FLMCR2* 5 EBR1 * 5 EBR2 * 5 SYSCR2* 6 RAMER R/W*3 R/W*3 R/W*3 R/W*3 R/W R/W Initial Value H'80 H'00* 4 H'00* 4 H'00* 4 H'00 H'00 Address* 1 H'FFC8 * 2 H'FFC9 * 2 H'FFCA * 2 H'FFCB * 2 H'FF42 H'FEDB Lower 16 bits of the address. Flash memory. Registers selection is performed by the FLSHE bit in system control register 2 (SYSCR2). In modes in which the on-chip flash memory is disabled, a read will return H'00, and writes are invalid. If a high level is input and the SWE bit in FLMCR1 is not set, these registers are initialized to H'00. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid for these registers, the access requiring 2 states. 6. The SYSCR2 register can only be used in the F-ZTAT version. In the masked ROM version this register will return an undefined value if read, and cannot be modified. Rev.6.00 Oct.28.2004 page 626 of 1016 REJ09B0138-0600H 19.16 19.16.1 Bit Register Descriptions Flash Memory Control Register 1 (FLMCR1) : 7 FWE 6 SWE 0 R/W 5 ESU 0 R/W 4 PSU 0 R/W 3 EV 0 R/W 2 PV 0 R/W 1 E 0 R/W 0 P 0 R/W Initial value : R/W : 1 R FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1, then setting the EV or PV bit. Program mode is entered by setting SWE to 1, then setting the PSU bit, and finally setting the P bit. Erase mode is entered by setting SWE to 1, then setting the ESU bit, and finally setting the E bit. FLMCR1 is initialized to H'80 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writing to bits ESU, PSU, EV, and PV in FLMCR1 is enabled only when SWE = 1; writing to the E bit is enabled only when SWE = 1, and ESU = 1; and writing to the P bit is enabled only when SWE = 1, and PSU = 1. Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing. These bits cannot be modified and are always read as 1 in this model. Bit 6—Software Write Enable Bit (SWE): Enables or disables flash memory programming and erasing. This bit should be set when setting bits 5 to 0, EBR1 bits 7 to 0, and EBR2 bits 3 to 0. When SWE = 1, the flash memory can only be read in program-verify or erase-verify mode. Bit 6 SWE 0 1 Description Writes disabled Writes enabled (Initial value) Bit 5—Erase Setup Bit (ESU): Prepares for a transition to erase mode. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 5 ESU 0 1 Description Erase setup cleared Erase setup [Setting condition] When SWE = 1 (Initial value) Bit 4—Program Setup Bit (PSU): Prepares for a transition to program mode. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time. Bit 4 PSU 0 1 Description Program setup cleared Program setup [Setting condition] When SWE = 1 (Initial value) Rev.6.00 Oct.28.2004 page 627 of 1016 REJ09B0138-0600H Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 EV 0 1 Description Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When SWE = 1 (Initial value) Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time. Bit 2 PV 0 1 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] When SWE = 1 (Initial value) Bit 1—Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time. Bit 1 E 0 1 Description Erase mode cleared Transition to erase mode [Setting condition] When SWE = 1, and ESU = 1 (Initial value) Bit 0—Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU, ESU, EV, PV, or E bit at the same time. Bit 0 P 0 1 Description Program mode cleared Transition to program mode [Setting condition] When SWE = 1, and PSU = 1 (Initial value) Rev.6.00 Oct.28.2004 page 628 of 1016 REJ09B0138-0600H 19.16.2 Bit Flash Memory Control Register 2 (FLMCR2) : 7 FLER 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 2 — 0 — 1 — 0 — 0 — 0 — Initial value : R/W : 0 R FLMCR2 is an 8-bit register that controls the flash memory operating modes. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00 and writes are invalid. Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state. Bit 7 FLER 0 Description Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode 1 An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 19.19.3, Error Protection (Initial value) Bits 6 to 0—Reserved: These bits cannot be modified and are always read as 0. 19.16.3 Bit EBR1 Initial value : R/W : Erase Block Register 1 (EBR1) : 7 EB7 0 R/W 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W 0 EB0 0 R/W EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1 and EBR2 together (setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0). When on-chip flash memory is disabled, a read will return H'00 and writes are invalid. The flash memory block configuration is shown in table 19-33. Rev.6.00 Oct.28.2004 page 629 of 1016 REJ09B0138-0600H 19.16.4 Bit EBR2 Erase Block Registers 2 (EBR2) : 7 — 0 — 6 — 0 — 5 — 0 — 4 — 0 — 3 EB11 0 R/W 2 EB10 0 R/W 1 EB9 0 R/W 0 EB8 0 R/W Initial value : R/W : EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, and the SWE bit in FLMCR1 is not set. When a bit in EBR2 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR2 and EBR1 together (setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0). Bits 4 to 7 are reserved; they are always read as 0 and cannot be modified. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 19-33. Table 19-33 Flash Memory Erase Blocks Block (Size) EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) EB8 (32 kbytes) EB9 (64 kbytes) EB10 (64 kbytes) EB11 (64 kbytes) Address H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF H'008000 to H'00FFFF H'010000 to H'01FFFF H'020000 to H'02FFFF H'030000 to H'03FFFF 19.16.5 Bit System Control Register 2 (SYSCR2) : 7 — 6 — 0 — 5 — 0 — 4 — 0 — 3 FLSHE 0 R/W 2 — 0 — 1 — 0 — 0 — 0 — Initial value : R/W : 0 — SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control. SYSCR2 is initialized to H'00 by a reset and in hardware standby mode. SYSCR2 can only be used in the F-ZTAT version. In the masked ROM version this register will return an undefined value if read, and cannot be modified. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0. Rev.6.00 Oct.28.2004 page 630 of 1016 REJ09B0138-0600H Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit enables the flash memory control registers to be read and written to. Clearing FLSHE to 0 designates these registers as unselected (the register contents are retained). Bit 3 FLSHE 0 1 Description Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB (Initial value) Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 0. 19.16.6 Bit RAM Emulation Register (RAMER) : 7 — 6 — 0 — 5 — 0 — 4 — 0 — 3 RAMS 0 R/W 2 RAM2 0 R/W 1 RAM1 0 R/W 0 RAM0 0 R/W Initial value : R/W : 0 — RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. RAMER settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 19-34. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0. Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory blocks are program/erase-protected. Bit 3 RAMS 0 Description Emulation not selected Program/erase-protection of all flash memory blocks is disabled 1 Emulation selected Program/erase-protection of all flash memory blocks is enabled (Initial value) Rev.6.00 Oct.28.2004 page 631 of 1016 REJ09B0138-0600H Bits 2 to 0—Flash Memory Area Selection (RAM2 to RAM0): These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM. (See table 19-34.) Table 19-34 Flash Memory Area Divisions RAM Area H'FFDC00 to H'FFEBFF H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF Block Name RAM area, 4 kbytes EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) RAMS 0 1 1 1 1 1 1 1 1 RAM2 × 0 0 0 0 1 1 1 1 RAM1 × 0 0 1 1 0 0 1 1 RAM0 × 0 1 0 1 0 1 0 1 ×: Don’t care 19.17 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 19-35. For a diagram of the transitions to the various flash memory modes, see figure 19-37. Table 19-35 Setting On-Board Programming Modes Mode MCU Mode Boot mode CPU Operating Mode Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode User program mode* Advanced expanded mode with on-chip ROM enabled Advanced single-chip mode 1 1 MD2 0 Pins MD1 1 MD0 0 1 0 1 Note: * Normally, user mode should be used. Set the SWE bit to 1 to make a transition to user program mode before performing a program/erase/verify operation. Rev.6.00 Oct.28.2004 page 632 of 1016 REJ09B0138-0600H 19.17.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2398 F-ZTAT chip’s pins have been set to boot mode, the boot program built into the chip is started and the programming control program prepared in the host is serially transmitted to the chip via the SCI. In the chip, the programming control program received via the SCI is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 19-43, and the boot program mode execution procedure in figure 19-44. Chip Flash memory Host Write data reception Verify data transmission RxD1 SCI1 TxD1 On-chip RAM Figure 19-43 System Configuration in Boot Mode Rev.6.00 Oct.28.2004 page 633 of 1016 REJ09B0138-0600H Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Chip measures low period of H'00 data transmitted by host Chip calculates bit rate and sets value in bit rate register After bit rate adjustment, chip transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, chip transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte Chip transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units Chip transmits received programming control program to host as verify data (echo-back) Transfer received programming control program to on-chip RAM No Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, chip transmits one H'AA data byte to host Execute programming control program transferred to on-chip RAM n+1→n n = N? Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Figure 19-44 Boot Mode Execution Procedure Rev.6.00 Oct.28.2004 page 634 of 1016 REJ09B0138-0600H Automatic SCI Bit Rate Adjustment: When boot mode is initiated, H8S/2398 F-ZTAT chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host’s transmission bit rate and the chip’s system clock frequency, there will be a discrepancy between the bit rates of the host and the chip. To ensure correct SCI operation, the host’s transfer bit rate should be set to 9,600 or 19,200 bps. Table 19-36 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the MCU’s bit rate is possible. The boot program should be executed within this system clock range. Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 19-45 Automatic SCI Bit Rate Adjustment Table 19-36 System Clock Frequencies for which Automatic Adjustment of H8S/2398 F-ZTAT Bit Rate is Possible Host Bit Rate 19,200 bps 9,600 bps System Clock Frequency for which Automatic Adjustment of H8S/2398 F-ZTAT Bit Rate Is Possible 16 to 20 MHz 10 to 20 MHz Rev.6.00 Oct.28.2004 page 635 of 1016 REJ09B0138-0600H On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2-kbyte area from H'FFDC00 to H'FFE3FF is reserved for use by the boot program, as shown in figure 19-46. The area to which the programming control program is transferred is H'FFE400 to H'FFFBFF. The boot program area can be used when the programming control program transferred into RAM enters the execution state. A stack area should be set up as required. H'FFDC00 H'FFE3FF Boot program area* (2 kbytes) Programming control program area (6 kbytes) H'FFFBFF Note: * The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note that the boot program remains stored in this area after a branch is made to the programming control program. Figure 19-46 RAM Areas in Boot Mode Notes on Use of Boot Mode • When the chip comes out of reset in boot mode, it measures the low-level period of the input at the SCI’s RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period of the RxD1 pin. • In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. • Interrupts cannot be used while the flash memory is being programmed or erased. • The RxD1 and TxD1 pins should be pulled up on the board. • Before branching to the programming control program (RAM area H'FFE400 to H'FFFBFF), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD1, goes to the high-level output state (P31DDR = 1, P31DR = 1). The contents of the CPU’s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. Initial settings must also be made for the other on-chip registers. • Boot mode can be entered by making the pin settings shown in table 19-35 and executing a reset-start. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the mode pins, and executing reset release*1. Boot mode can also be cleared by a WDT overflow reset. Rev.6.00 Oct.28.2004 page 636 of 1016 REJ09B0138-0600H Do not change the mode pin input levels in boot mode. • If the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR) will change according to the change in the microcomputer’s operating mode*2. Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. Notes: 1. Mode pins input must satisfy the mode programming setup time (tMDS = 200 ns) with respect to the reset release timing. 2. See Appendix D, Pin States. 19.17.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing onboard means supply of programming data, and storing a program/erase control program in part of the program area if necessary. To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7). In this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7. The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM or external memory. When the program is located in external memory, an instruction for programming the flash memory and the following instruction should be located in on-chip RAM. Figure 19-47 shows the procedure for executing the program/erase control program when transferred to on-chip RAM. Write the transfer program (and the program/erase control program if necessary) beforehand MD2, MD1, MD0 = 110, 111 Reset-start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area Execute program/erase control program (flash memory rewriting) Branch to flash memory application program Note: The watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. Figure 19-47 User Program Mode Execution Procedure Rev.6.00 Oct.28.2004 page 637 of 1016 REJ09B0138-0600H 19.18 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased. Therefore, the program that controls flash memory programming/erasing (the programming control program) should be located and executed in on-chip RAM or external memory. When the program is located in external memory, an instruction for programming the flash memory and the following instruction should be located in on-chip RAM. The DMAC or DTC should not be activated before or after the instruction for programming the flash memory is executed. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU, PSU, EV, PV, E, and P bits in FLMCR1 is executed by a program in flash memory. 2. Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. 19.18.1 Program Mode Follow the procedure shown in the program/program-verify flowchart in figure 19-48 to write data or programs to flash memory. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a time. For the wait times (x, y, z1, z2, z3 α, ß, γ, ε, η, and θ) after bits are set or cleared in flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N), see section 22.3.6, Flash Memory Characteristics. Following the elapse of (x) µs or more after the SWE bit is set to 1 in flash memory control register 1 (FLMCR1), 128byte program data is stored in the program data area and reprogram data area, and the 128-byte data in the reprogram data area is written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00 or H'80. 128 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than (y + z2 + α + β) µs as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU bit in FLMCR1, and after the elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory programming time. Set the programming time according to the table in the programming flowchart in figure 19-48. 19.18.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of a given programming time, the programming mode is exited (the P bit in FLMCR1 is cleared to 0, then the PSU bit is cleared to 0 at least (α) µs later). Next, the watchdog timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to program-verify mode by setting the PV bit in FLMCR1. Before reading in programverify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 19-48) and transferred to the reprogram data area. After 128 bytes of data have been verified, exit program-verify mode in FLMCR1 to 0, and wait again for at least (θ) µs. If reprogramming is necessary, set program mode again, and repeat the Rev.6.00 Oct.28.2004 page 638 of 1016 REJ09B0138-0600H program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits. Write pulse application subroutine Sub-routine write pulse Enable WDT Set PSU bit in FLMCR1 Wait (y) µs Set P bit in FLMCR1 n=1 Wait (z1) µs or (z2) µs or (z3) µs Clear P bit in FLMCR1 Wait (α) µs Clear PSU bit in FLMCR1 Wait (β) µs Disable WDT End sub *6 *6 *5*6 m=0 Write 128-byte data in RAM reprogram *1 data area consecutively to flash memory Sub-routine-call Write pulse (z1) µs or (z2) µs Set PV bit in FLMCR1 Wait (γ) µs H'FF dummy write to verify address Note: 7 Write Pulse Width Number of Writes (n) Write Time (z) µs 1 z1 2 z1 3 z1 4 z1 5 z1 6 z1 7 z2 8 z2 9 z2 10 z2 11 z2 12 z2 13 z2 . . . . . . 998 z2 999 z2 1000 z2 Note: Use a (z3) µs write pulse for additional programming. Increment address Wait (ε) µs Read verify data *6 *2 n←n+1 *6 See note 7 regarding pulse width switching. *6 *6 Start of programming Start Set SWE bit in FLMCR1 Wait (x) µs Store 128-byte program data in program data area and reprogram data area *6 *4 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. Read data = verify data? OK 6≥n? NG m=1 NG OK Additional program data computation Transfer additional program data to additional program data area Reprogram data computation Transfer reprogram data to reprogram data area 128-byte data verification completed? OK Clear PV bit in FLMCR1 Wait (η) µs *6 NG *4 *3 *4 NG RAM Program data area (128 bytes) Reprogram data area (128 bytes) 6≥n? Additional program data area (128 bytes) OK Sequentially write 128-byte data in additional program data area in RAM to flash memory Write Pulse (z3 µs additional write pulse) NG *1 *6 m = 0? OK Clear SWE bit in FLMCR1 Wait (θ) µs End of programming n ≥ N? OK Clear SWE bit in FLMCR1 *6 Wait (θ) µs Programming failure NG *6 Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (W) units. 3. Even bits for which programming has been completed in the 128-byte programming loop will be subjected to additional programming if they fail the subsequent verify operation. 4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional program data should be provided in RAM. The contents of the reprogram data and additional program data areas are modified as programming proceeds. 5. A write pulse of (z1) or (z2) µs should be applied according to the progress of programming. See note 7 for the pulse widths. When the additional program data is programmed, a write pulse of (z3) µs should be applied. Reprogram data X' stands for reprogram data to which a write pulse has been applied. 6. For the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N, see section 22.3.6, the Flash Memory Characteristics. Program Data Operation Chart Original Data (D) 0 1 Verify Data (V) 0 1 0 1 Reprogram Data (X) 1 0 1 Comments Programming completed Programming incomplete; reprogram Still in erased state; no action Additional Program Data Operation Chart Reprogram Data (X') 0 1 Verify Data (V) 0 1 0 1 Additional Program Data (Y) Comments 0 Additional programming executed Additional programming not executed 1 Additional programming not executed Additional programming not executed Figure 19-48 Program/Program-Verify Flowchart Rev.6.00 Oct.28.2004 page 639 of 1016 REJ09B0138-0600H 19.18.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 19-49. For the wait times (x, y, z, α, ß, γ, ε, η, θ) after bits are set or cleared in flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N), see section 22.3.6, Flash Memory Characteristics. To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in erase block register 1 or 2 (EBR1 or EBR2) at least (x) µs after setting the SWE bit to 1 in flash memory control register 1 (FLMCR1). Next, the watchdog timer is set to prevent overerasing in the event of program runaway, etc. Set a value greater than (y + z + α + ß) ms as the WDT overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the ESU bit in FLMCR1, and after the elapse of (y) µs or more, the operating mode is switched to erase mode by setting the E bit in FLMCR1. The time during which the E bit is set is the flash memory erase time. Ensure that the erase time does not exceed (z) ms. Note: With flash memory erasing, prewriting (setting all data in the memory to be erased to 0) is not necessary before starting the erase procedure. 19.18.4 Erase-Verify Mode In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared to 0, then the ESU bit in FLMCR1 is cleared to 0 at least (α) µs later), the watchdog timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to erase-verify mode by setting the EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of ( γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data has not been erased, set erase mode again, and repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/eraseverify sequence is not repeated more than (N) times. When verification is completed, exit erase-verify mode, and wait for at least (η) µs. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1 to 0 and wait for at least (θ) µs. If there are any unerased blocks, make a 1 bit setting for the flash memory area to be erased, and repeat the erase/erase-verify sequence in the same way. Rev.6.00 Oct.28.2004 page 640 of 1016 REJ09B0138-0600H Start *1 Set SWE bit in FLMCR1 Wait (x) µs n=1 Set EBR1, EBR2 Enable WDT Set ESU bit in FLMCR1 Wait (y) µs Set E bit in FLMCR1 Wait (z) ms Clear E bit in FLMCR1 Wait (α) µs Clear ESU bit in FLMCR1 Wait (β) µs Disable WDT Set EV bit in FLMCR1 Wait (γ) µs Set block start address to verify address *2 *2 *2 *4 *2 Start of erase *2 Halt erase *2 n←n+1 H'FF dummy write to verify address Wait (ε) µs Increment address Read verify data Verify data = all 1? OK NG Last address of block? OK Clear EV bit in FLMCR1 Wait (η) µs *2 *2 *3 NG Clear EV bit in FLMCR1 Wait (η) µs *2 *2 NG *5 End of erasing of all erase blocks? OK n ≥ N? OK Clear SWE bit in FLMCR1 Wait (θ) µs Erase failure NG Clear SWE bit in FLMCR1 Wait (θ) µs End of erasing Notes: 1. 2. 3. 4. 5. Prewriting (setting erase block data to all 0) is not necessary. The values of x, y, z, α, β, γ, ε, η, θ, and N are shown in section 22.3.6, Flash Memory Characteristics. Verify data is read in 16-bit (W) units. Set only one bit in EBR1or EBR2. More than one bit cannot be set. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially. Figure 19-49 Erase/Erase-Verify Flowchart Rev.6.00 Oct.28.2004 page 641 of 1016 REJ09B0138-0600H 19.19 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.19.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2) are reset. (See table 19-37.) Table 19-37 Hardware Protection Functions Item Reset/standby protection Description • In a reset (including a WDT overflow reset) and in standby mode, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. Program Yes Erase Yes • Rev.6.00 Oct.28.2004 page 642 of 1016 REJ09B0138-0600H 19.19.2 Software Protection Software protection can be implemented by setting the SWE bit in flash memory control register 1 (FLMCR1), erase block registers 1 and 2 (EBR1, EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode. (See table 19-38.) Table 19-38 Software Protection Functions Item SWE bit protection Description • Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks (Execute in on-chip RAM or external memory.) Block specification protection • Erase protection can be set for individual blocks by settings in erase block registers 1 and 2 (EBR1, EBR2). Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state. Setting the RAMS bit to 1 in the RAM emulation register (RAMER) places all blocks in the program/erase-protected state. Yes Yes — Yes Program Yes Erase Yes • Emulation protection • Rev.6.00 Oct.28.2004 page 643 of 1016 REJ09B0138-0600H 19.19.3 Error Protection In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. FLER bit setting conditions are as follows: • • • • When flash memory is read during programming/erasing (including a vector read or instruction fetch) Immediately after exception handling (excluding a reset) during programming/erasing When a SLEEP instruction (including software standby) is executed during programming/erasing When the CPU loses the bus during programming/erasing Error protection is released only by a reset and in hardware standby mode. Figure 19-50 shows the flash memory state transition diagram. Normal operating mode Program mode Erase mode RES = 0 or STBY = 0 Reset or hardware standby (hardware protection) RD VF PR ER FLER = 0 Error occurrence (software standby) Error occurrence RES = 0 or STBY = 0 RD VF PR ER FLER = 0 FLMCR1, FLMCR2, EBR1, EBR2 initialization state RES = 0 or STBY = 0 Error protection mode RD VF PR ER FLER = 1 Software standby mode Software standby mode release Error protection mode (software standby) RD VF PR ER FLER = 1 FLMCR1, FLMCR2 (except FLER bit), EBR1, EBR2 initialization state Legend: RD: Memory read possible VF: Verify-read possible PR: Programming possible ER: Erasing possible RD: VF: PR: ER: Memory read not possible Verify-read not possible Programming not possible Erasing not possible Figure 19-50 Flash Memory State Transitions Rev.6.00 Oct.28.2004 page 644 of 1016 REJ09B0138-0600H 19.20 19.20.1 Flash Memory Emulation in RAM Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses can be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 19-51 shows an example of emulation of real-time flash memory programming. Start of emulation program Set RAMER Write tuning data to overlap RAM Execute application program No Tuning OK? Yes Clear RAMER Write to flash memory emulation block End of emulation program Figure 19-51 Flowchart for Flash Memory Emulation in RAM Rev.6.00 Oct.28.2004 page 645 of 1016 REJ09B0138-0600H 19.20.2 RAM Overlap An example in which flash memory block area EB1 is overlapped is shown below. This area can be accessed from both the RAM area and flash memory area H'00000 EB0 H'01000 EB1 H'02000 EB2 H'03000 EB3 H'04000 EB4 H'05000 EB5 H'06000 EB6 H'07000 EB7 H'08000 H'FFDC00 Flash memory EB8 to EB11 On-chip RAM H'FFFBFF H'3FFFF H'FFEBFF Figure 19-52 Example of RAM Overlap Operation Example in Which Flash Memory Block Area EB1 is Overlapped 1. Set bits RAMS, RAM2, RAM1, and RAM0 in RAMER to 1, 0, 0, 1, to overlap part of RAM onto the area (EB1) for which real-time programming is required. 2. Real-time programming is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB1). Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of RAM2, RAM1, and RAM0 (emulation protection). In this state, setting the P or E bit in flash memory control register 1 (FLMCR1) will not cause a transition to program mode or erase mode. When actually programming a flash memory area, the RAMS bit should be cleared to 0. 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 includes the vector table. When performing RAM emulation, the vector table is needed by the overlap RAM. Rev.6.00 Oct.28.2004 page 646 of 1016 REJ09B0138-0600H 19.21 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input, are disabled when flash memory is being programmed or erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode* 1, to give priority to the program or erase operation. There are three reasons for this: 1. Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly*2, possibly resulting in MCU runaway. 3. If an interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, in on-board programming mode alone there are conditions for disabling interrupts, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All interrupt requests, including NMI, must therefore be restricted inside and outside the MCU when programming or erasing flash memory. The NMI interrupt is also disabled in the error-protection state while the P or E bit remains set in FLMCR1. Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming control program has completed programming. 2. The vector may not be read correctly in this case for the following two reasons: • If flash memory is read while being programmed or erased (while the P or E bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned). • If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. 19.22 19.22.1 Flash Memory Programmer Mode Programmer Mode Setting Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports the Renesas Technology microcomputer device type with 256-kbyte on-chip flash memory (FZTAT256V5A). Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. Table 19-39 shows programmer mode pin settings. Table 19-39 Programmer Mode Pin Settings Pin Names Mode pins: MD2, MD1, MD0 Mode setting pins: P66, P65, P64 STBY pin RES pin XTAL, EXTAL pins Other pins requiring setting: P32, P25 Settings/External Circuit Connection Low-level input High-level input to P66, low-level input to P65 and P64 High-level input (do not select hardware standby mode) Reset circuit Oscillator circuit High-level input to P32, low-level input to P25 Rev.6.00 Oct.28.2004 page 647 of 1016 REJ09B0138-0600H 19.22.2 Socket Adapters and Memory Map In programmer mode, a socket adapter is connected to the chip as shown in figure 19-54. Figure 19-53 shows the on-chip ROM memory map and figure 19-54 show the socket adapter pin assignments. H8S/2398 F-ZTAT MCU mode address H'00000000 Programmer mode address H'00000 On-chip ROM space (256 kbytes) H'0003FFFF H'3FFFF Figure 19-53 Memory Map in Programmer Mode Rev.6.00 Oct.28.2004 page 648 of 1016 REJ09B0138-0600H H8S/2398 F-ZTAT TFP-120 2 3 4 5 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 43 44 45 46 48 49 50 51 68 69 67 72 FP-128B 6 7 8 9 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 49 50 51 52 54 55 56 57 76 77 75 80 Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 D8 D9 D10 D11 D12 D13 D14 D15 CE OE WE VCL*3 VCC Socket Adapter (40-Pin Conversion) HN27C4096HG (40 Pins) Pin No. 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 10 19 18 17 16 15 14 13 12 2 20 3 Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CE OE WE FWE VCC VSS NC A20 A19 Data input/output Address input Chip enable Output enable Write enable Capacitor 4 1, 40 11, 30 5, 6, 7 8 1, 30, 33, 52, 55,74, 5, 34, 39, 58, 61, 82, 75, 76, 81, 93, 94 83, 84, 89, 103, 104 6, 15, 24, 31, 32, 38, 3, 10, 19, 28, 35, 36, 47, 59, 66, 79, 103, 37, 38, 44, 53, 65, 104, 113, 114, 115 67, 68, 74, 87, 99, 100, 113, 114, 123, 124, 125 73 81 77 78 Other pins 85 86 VSS *1 RES XTAL EXTAL NC (OPEN) Reset circuit Oscillation circuit *2 9 Legend: I/O7 to I/O0: A18 to A0: CE: OE: WE: Notes: 1. A reset oscillation stabilization time (tosc1) of at least 10 ms is required. 2. A 12 MHz crystal resonator should be used. 3. The VCL pin should be connected to VSS by using a capacitor of 0.47 µF. This figure shows pin assignments, and does not show the entire socket adapter circuit. Figure 19-54 H8S/2398 F-ZTAT Socket Adapter Pin Assignments Rev.6.00 Oct.28.2004 page 649 of 1016 REJ09B0138-0600H 19.22.3 Programmer Mode Operation Table 19-40 shows how the different operating modes are set when using programmer mode, and table 19-41 lists the commands used in programmer mode. Details of each mode are given below. Memory Read Mode: Memory read mode supports byte reads. Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. Auto-Erase Mode: Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-erasing. Status Read Mode: Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the I/O 6 signal. In status read mode, error information is output if an error occurs. Table 19-40 Settings for Each Operating Mode in Programmer Mode Pin Names Mode Read Output disable Command write Chip disable * 1 CE L L L H OE L H H × WE H H L × I/O7 to I/O0 Data output Hi-Z Data input Hi-Z A18 to A0 Ain × Ain* 2 × Legend: H: High level L: Low level Hi-Z: High impedance ×: Don’t care Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. Ain indicates that there is also address input in auto-program mode. Table 19-41 Programmer Mode Commands Number of Cycles 1+n 129 2 2 1st Cycle Mode Write Write Write Write Address Data × × × × H'00 H'40 H'20 H'71 Mode Read Write Write Write 2nd Cycle Address Data RA PA × × Dout Din H'20 H'71 Command Name Memory read mode Auto-program mode Auto-erase mode Status read mode Legend: RA: Read address PA: Program address ×: Don't care Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n). Rev.6.00 Oct.28.2004 page 650 of 1016 REJ09B0138-0600H 19.22.4 Memory Read Mode • After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed. • Command writes can be performed in memory read mode, just as in the command wait state. • Once memory read mode has been entered, consecutive reads can be performed. • After power-on, memory read mode is entered. Table 19-42 AC Characteristics in Memory Read Mode Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol t nxtc t ceh t ces t dh t ds t wep tr tf Min 20 0 0 50 50 70 — — Max — — — — — — 30 30 Unit µs ns ns ns ns ns ns ns Command write A18 to A0 Memory read mode Address stable CE OE WE Data twep tceh tnxtc tces tf tr H'00 tdh tds Data Note: Data is latched at the rising edge of WE. Figure 19-55 Memory Read Mode Timing Waveforms after Command Write Rev.6.00 Oct.28.2004 page 651 of 1016 REJ09B0138-0600H Table 19-43 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol t nxtc t ceh t ces t dh t ds t wep tr tf Min 20 0 0 50 50 70 — — Max — — — — — — 30 30 Unit µs ns ns ns ns ns ns ns Memory read mode A18 to A0 CE OE WE Address stable tnxtc Other mode command write tces tceh tf twep tr tds I/O7 to I/O0 Note: Do not enable WE and OE at the same time. tdh Figure 19-56 Timing Waveforms when Entering Another Mode from Memory Read Mode Table 19-44 AC Characteristics in Memory Read Mode Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C Item Access time CE output delay time OE output delay time Output disable delay time Data output hold time Symbol t acc t ce t oe t df t oh Min — — — — 5 Max 20 150 150 100 — Unit µs ns ns ns ns Rev.6.00 Oct.28.2004 page 652 of 1016 REJ09B0138-0600H A18 to A0 CE OE WE Address stable Address stable VIL VIL VIH tacc tacc toh toh I/O7 to I/O0 Figure 19-57 Timing Waveforms for CE/OE Enable State Read A18 to A0 CE Address stable tce Address stable tce toe OE WE VIH I/O7 to I/O0 tacc toh tacc tdf toe toh tdf Figure 19-58 Timing Waveforms for CE/OE Clocked Read 19.22.5 Auto-Program Mode • In auto-program mode, 128 bytes are programmed simultaneously. For this purpose, 128 consecutive byte data transfers should be performed. • A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. • The lower 7 bits of the transfer address must be held low. If an invalid address is input, memory programming will be started but a programming error will occur. • Memory address transfer is executed in the second cycle (figure 19-59). Do not perform transfer later than the second cycle. • Do not perform a command write during a programming operation. • Perform one auto-programming operation for a 128-byte block for each address. One or more additional programming operations cannot be carried out on address blocks that have already been programmed. • Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode can also be used for this purpose (the I/O 7 status polling pin is used to identify the end of an auto-program operation). • Status polling I/O6 and I/O7 information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. Rev.6.00 Oct.28.2004 page 653 of 1016 REJ09B0138-0600H AC Characteristics Table 19-45 AC Characteristics in Auto-Program Mode Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Address setup time Address hold time Memory write time WE rise time WE fall time Symbol t nxtc t ceh t ces t dh t ds t wep t wsts t spa t as t ah t write tr tf Min 20 0 0 50 50 70 1 — 0 60 1 — — Max — — — — — — — 150 — — 3000 30 30 Unit µs ns ns ns ns ns ms ns ns ns ms ns ns A18 to A0 tces CE OE tf WE tds I/O7 tdh twep tr tceh tnxtc Address stable tnxtc tas tah Data transfer 1 byte to 128 bytes twsts tspa twrite Programming operation end identification signal I/O6 Programming normal end identification signal I/O5 to I/O0 H'40 H'00 Figure 19-59 Auto-Program Mode Timing Waveforms Rev.6.00 Oct.28.2004 page 654 of 1016 REJ09B0138-0600H 19.22.6 Auto-Erase Mode • Auto-erase mode supports only total memory erasing. • Do not perform a command write during auto-erasing. • Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (the I/O7 status polling pin is used to identify the end of an auto-erase operation). • Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. AC Characteristics Table 19-46 AC Characteristics in Auto-Erase Mode Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Memory erase time WE rise time WE fall time Symbol t nxtc t ceh t ces t dh t ds t wep t ests t spa t erase tr tf Min 20 0 0 50 50 70 1 — 100 — — Max — — — — — — — 150 40000 30 30 Unit µs ns ns ns ns ns ms ns ms ns ns A18 to A0 tces CE OE WE tf twep tr tdh tests tspa terase Erase end identification signal Erase normal end confirmation signal tceh tnxtc tnxtc tds I/O7 I/O6 I/O5 to I/O0 H'20 H'20 H'00 Figure 19-60 Auto-Erase Mode Timing Waveforms Rev.6.00 Oct.28.2004 page 655 of 1016 REJ09B0138-0600H 19.22.7 Status Read Mode • Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. • The return code is retained until a command write for other than status read mode is performed. Table 19-47 AC Characteristics in Status Read Mode Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width OE output delay time Disable delay time CE output delay time WE rise time WE fall time Symbol t nxtc t ceh t ces t dh t ds t wep t oe t df t ce tr tf Min 20 0 0 50 50 70 — — — — — Max — — — — — — 150 100 150 30 30 Unit µs ns ns ns ns ns ns ns ns ns ns A18 to A0 tces CE tce OE WE tf twep tr tdh H'71 tf twep tr tdh H'71 toe tdf tceh tnxtc tces tceh tnxtc tnxtc tds I/O7 to I/O0 tds Note: I/O3 and I/O2 are undefined. Figure 19-61 Status Read Mode Timing Waveforms Rev.6.00 Oct.28.2004 page 656 of 1016 REJ09B0138-0600H Table 19-48 Status Read Mode Return Commands Pin Name I/O 7 Attribute I/O 6 I/O 5 Programming error I/O 4 Erase error I/O 3 — I/O 2 — I/O 1 I/O 0 Normal Command end error identification 0 Command error: 1 ProgramEffective ming or address error erase count exceeded 0 0 Initial value 0 Indications Normal end: 0 Abnormal end: 1 0 0 0 0 — ProgramErase — ming error: 1 Otherwise: 0 error: 1 Otherwise: 0 Otherwise: 0 Count Effective exceeded: 1 address Otherwise: 0 error: 1 Otherwise: 0 Note: I/O2 and I/O3 are undefined. 19.22.8 Status Polling • The I/O7 status polling flag indicates the operating status in auto-program or auto-erase mode. • The I/O6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase mode. Table 19-49 Status Polling Output Truth Table Pin Names I/O7 I/O6 I/O0 to I/O 5 Internal Operation in Progress 0 0 0 Abnormal End 1 0 0 — 0 1 0 Normal End 1 1 0 19.22.9 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the PROM mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 19-50 Command Wait State Transition Time Specifications Item Standby release (oscillation stabilization time) Programmer mode setup time VCC hold time Symbol t osc1 t bmv t dwn Min 30 10 0 Max — — — Unit ms ms ms tosc1 VCC RES tbmv Memory read mode Command wait state Auto-program mode Auto-erase mode Command wait state Normal/ abnormal end identification tdwn Command acceptance Figure 19-62 Oscillation Stabilization Time, PROM Mode Setup Time, and Power Supply Fall Sequence Rev.6.00 Oct.28.2004 page 657 of 1016 REJ09B0138-0600H 19.22.10 Notes on Memory Programming • When programming addresses which have previously been programmed, carry out auto-erasing before autoprogramming. • When performing programming using PROM mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. Additional programming cannot be carried out on address blocks that have already been programmed. 19.23 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode, the RAM emulation function, and programmer mode are summarized below. Use the specified voltages and timing for programming and erasing: Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas Technology microcomputer device type with 256-kbyte on-chip flash memory (FZTAT256V5A). Do not select the HN27C4096 setting for the PROM programmer, and only use the specified socket adapter. Failure to observe these points may result in damage to the device. Powering on and off: When applying or disconnecting VCC power, fix the RES pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. Use the recommended algorithm when programming and erasing flash memory: The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. Do not set or clear the SWE bit during execution of a program in flash memory: Wait for at least 100 µs after clearing the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten, but when SWE = 1, flash memory can only be read in program-verify or erase-verify mode. Access flash memory only for verify operations (verification during programming/erasing). Also, do not clear the SWE bit during programming, erasing, or verifying. Similarly, when using the RAM emulation function the SWE bit must be cleared before executing a program or reading data in flash memory. However, the RAM area overlapping flash memory space can be read and written to regardless of whether the SWE bit is set or cleared. Do not use interrupts while flash memory is being programmed or erased: When flash memory is programmed or erased, all interrupt requests, including NMI, should be disabled to give priority to program/erase operations. Do not perform additional programming. Erase the memory before reprogramming: In on-board programming, perform only one programming operation on a 128-byte programming unit block. In programmer mode, too, perform only Rev.6.00 Oct.28.2004 page 658 of 1016 REJ09B0138-0600H one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. Before programming, check that the chip is correctly mounted in the PROM programmer: Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. Do not touch the socket adapter or chip during programming: Touching either of these can cause contact faults and write errors. Rev.6.00 Oct.28.2004 page 659 of 1016 REJ09B0138-0600H Rev.6.00 Oct.28.2004 page 660 of 1016 REJ09B0138-0600H Section 20 Clock Pulse Generator 20.1 Overview The H8S/2357 Group has a on-chip clock pulse generator (CPG) that generates the system clock (ø), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a medium-speed clock divider, and a bus master clock selection circuit. 20.1.1 Block Diagram Figure 20-1 shows a block diagram of the clock pulse generator. SCKCR SCK2 to SCK0 Mediumspeed divider EXTAL Oscillator XTAL Duty adjustment circuit ø/2 to ø/32 Bus master clock selection circuit System clock to ø pin Internal clock to supporting modules Bus master clock to CPU, DTC, and DMAC Figure 20-1 Block Diagram of Clock Pulse Generator 20.1.2 Register Configuration The clock pulse generator is controlled by SCKCR. Table 20-1 shows the register configuration. Table 20-1 Clock Pulse Generator Register Name System clock control register Note: * Lower 16 bits of the address. Abbreviation SCKCR R/W R/W Initial Value H'00 Address* H'FF3A Rev.6.00 Oct.28.2004 page 661 of 1016 REJ09B0138-0600H 20.2 20.2.1 Bit Register Descriptions System Clock Control Register (SCKCR) : 7 PSTOP 6 — 0 R/W 5 — 0 —/(R/W)* 4 — 0 — 3 — 0 — 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W Initial value : R/W : 0 R/W SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium-speed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: * R/W in the H8S/2390, H8S/2392, H8S/2394 and H8S/2398. Bit 7—ø Clock Output Disable (PSTOP): Controls ø output. Description Bit 7 PSTOP 0 1 Normal Operation ø output (initial value) Fixed high Sleep Mode ø output Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance Bit 6—Reserved: This bit can be read or written to, but only 0 should be written. Bit 5—Reserved: In the H8S/2357 and H8S/2352, this bit cannot be modified and is always read as 0. Only 0 should be written. This bit is reserved in the H8S/2390, H8S/2392, H8S/2394, and H8S/2398. Only 0 should be written to this bit. Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 0. Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the clock for the bus master. Bit 2 SCK2 0 Bit 1 SCK1 0 Bit 0 SCK0 0 1 1 0 1 1 0 0 1 1 — Description Bus master is in high-speed mode Medium-speed clock is ø/2 Medium-speed clock is ø/4 Medium-speed clock is ø/8 Medium-speed clock is ø/16 Medium-speed clock is ø/32 — (Initial value) Rev.6.00 Oct.28.2004 page 662 of 1016 REJ09B0138-0600H 20.3 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 20.3.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 20-2. Select the damping resistance R d according to table 20-2. An AT-cut parallel-resonance crystal should be used. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF Figure 20-2 Connection of Crystal Resonator (Example) Table 20-2 Damping Resistance Value Frequency (MHz) Rd (Ω) 2 1k 4 500 8 200 10 0 12 0 16 0 20 0 Crystal Resonator: Figure 20-3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 20-3 and the same resonance frequency as the system clock (ø). CL L XTAL Rs EXTAL AT-cut parallel-resonance type C0 Figure 20-3 Crystal Resonator Equivalent Circuit Table 20-3 Crystal Resonator Parameters Frequency (MHz) RS max (Ω) C0 max (pF) 2 500 7 4 120 7 8 80 7 10 70 7 12 60 7 16 50 7 20 40 7 Rev.6.00 Oct.28.2004 page 663 of 1016 REJ09B0138-0600H Note on Board Design: When a crystal resonator is connected, the following points should be noted. Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 20-4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Avoid CL2 Signal A Signal B H8S/2357 Group XTAL EXTAL CL1 Figure 20-4 Example of Incorrect Board Design 20.3.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 20-5. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b) in fugure 20-5, make sure that the external clock is held high in standby mode. EXTAL XTAL Open External clock input (a) XTAL pin left open EXTAL XTAL External clock input (b) Complementary clock input at XTAL pin Figure 20-5 External Clock Input (Examples) External Clock: The external clock signal should have the same frequency as the system clock (ø). Rev.6.00 Oct.28.2004 page 664 of 1016 REJ09B0138-0600H Table 20-4 and figure 20-6 show the input conditions for the external clock. Table 20-4 External Clock Input Conditions VCC = 2.7 V to 5.5 V Item External clock input low pulse width External clock input high pulse width External clock rise time External clock fall time Clock low pulse width level Clock high pulse width level Symbol t EXL t EXH t EXr t EXf t CL Min 40 40 — — 0.4 80 t CH 0.4 80 Max — — 10 10 0.6 — 0.6 — VCC = 5.0 V ± 10% Min 20 20 — — 0.4 80 0.4 80 Max — — 5 5 0.6 — 0.6 — Unit ns ns ns ns t cyc ns t cyc ns ø ≥ 5 MHz ø < 5 MHz ø ≥ 5 MHz ø < 5 MHz Figure 22-4 Test Conditions Figure 20-6 tEXH tEXL EXTAL VCC × 0.5 tEXr tEXf Figure 20-6 External Clock Input Timing 20.4 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (ø). 20.5 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate ø/2, ø/4, ø/8, ø/16, and ø/32. 20.6 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock (ø) or one of the medium-speed clocks (ø/2, ø/4, or ø/8, ø/16, and ø/32) to be supplied to the bus master, according to the settings of the SCK2 to SCK0 bits in SCKCR. Rev.6.00 Oct.28.2004 page 665 of 1016 REJ09B0138-0600H Rev.6.00 Oct.28.2004 page 666 of 1016 REJ09B0138-0600H Section 21 Power-Down Modes 21.1 Overview In addition to the normal program execution state, the H8S/2357 Group has five power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. The H8S/2357 Group operating modes are as follows: (1) High-speed mode (2) Medium-speed mode (3) Sleep mode (4) Module stop mode (5) Software standby mode (6) Hardware standby mode Of these, (2) to (6) are power-down modes. Sleep mode is a CPU mode, medium-speed mode is a CPU and bus master mode, and module stop mode is an on-chip supporting module mode (including bus masters other than the CPU). A combination of these modes can be set. After a reset, the H8S/2357 Group is in high-speed mode. Table 21-1 shows the conditions for transition to the various modes, the status of the CPU, on-chip supporting modules, etc., and the method of clearing each mode. Table 21-1 Operating Modes Operating Mode High speed mode Transition Condition Control register Clearing Condition CPU Oscillator Functions Functions High speed Registers Functions High speed Modules Registers Functions I/O Ports High speed High speed MediumControl speed mode register Sleep mode Instruction Module stop Control mode register Software standby mode Hardware standby mode Instruction External interrupt Interrupt Medium Functions speed Halted Retained High/ Functions medium speed *1 High speed Halted Functions Retained/ reset *2 Retained/ reset *2 Reset Functions Functions High speed Retained High/ Functions medium speed Halted Retained Halted Halted Retained Pin Halted Halted Undefined Halted High impedance Notes: 1. The bus master operates on the medium-speed clock, and other on-chip supporting modules on the high-speed clock. 2. The SCI and A/D converter are reset, and other on-chip supporting modules retain their state. Rev.6.00 Oct.28.2004 page 667 of 1016 REJ09B0138-0600H 21.1.1 Register Configuration Power-down modes are controlled by the SBYCR, SCKCR, and MSTPCR registers. Table 21-2 summarizes these registers. Table 21-2 Power-Down Mode Registers Name Standby control register System clock control register Module stop control register H Module stop control register L Note: * Lower 16 bits of the address. Abbreviation SBYCR SCKCR MSTPCRH MSTPCRL R/W R/W R/W R/W R/W Initial Value H'08 H'00 H'3F H'FF Address* H'FF38 H'FF3A H'FF3C H'FF3D Rev.6.00 Oct.28.2004 page 668 of 1016 REJ09B0138-0600H 21.2 21.2.1 Bit Register Descriptions Standby Control Register (SBYCR) : 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 OPE 1 R/W 2 — 0 — 1 — 0 — 0 — 0 R/W Initial value : R/W : SBYCR is an 8-bit readable/writable register that performs software standby mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Software Standby (SSBY): Specifies a transition to software standby mode. Remains set to 1 when software standby mode is released by an external interrupt, and a transition is made to normal operation. The SSBY bit should be cleared by writing 0 to it. Bit 7 SSBY 0 1 Description Transition to sleep mode after execution of SLEEP instruction Transition to software standby mode after execution of SLEEP instruction (Initial value) Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the time the MCU waits for the clock to stabilize when software standby mode is cleared by an external interrupt. With crystal oscillation, refer to table 21-4 and make a selection according to the operating frequency so that the standby time is at least 8 ms (the oscillation stabilization time). With an external clock, any selection can be made*. Note: * Not available in the F-ZTAT version. Bit 6 STS2 0 Bit 5 STS1 0 Bit 4 STS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Standby time = 8,192 states Standby time = 16,384 states Standby time = 32,768 states Standby time = 65,536 states Standby time = 131,072 states Standby time = 262,144 states Reserved Standby time = 16 states* (Initial value) Note: * Not available in the F-ZTAT version. Rev.6.00 Oct.28.2004 page 669 of 1016 REJ09B0138-0600H Bit 3—Output Port Enable (OPE): Specifies whether the output of the address bus and bus control signals (CS0 to CS7, AS, RD, HWR, LWR, CAS ) is retained or set to the high-impedance state in software standby mode. Bit 3 OPE 0 1 Description In software standby mode, address bus and bus control signals are high-impedance In software standby mode, address bus and bus control signals retain output state (Initial value) Bits 2 and 1—Reserved: These bits cannot be modified and are always read as 0. Bit 0—Reserved: This bit can be read or written to, but only 0 should be written. 21.2.2 Bit System Clock Control Register (SCKCR) : 7 PSTOP 6 — 0 R/W 5 — 0 —/(R/W)* 4 — 0 — 3 — 0 — 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W Initial value : R/W : 0 R/W Note: * R/W in the H8S/2390, H8S/2392, H8S/2394, and H8S/2398. SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium-speed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—ø Clock Output Disable (PSTOP): Controls ø output. Description Bit 7 PSTOP 0 1 Normal Operating Mode ø output (initial value) Fixed high Sleep Mode ø output Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance Bits 6—Reserved: This bit can be read or written to, but only 0 should be written. Bit 5—Reserved: In the H8S/2357 and H8S/2352, this bit cannot be modified and is always read as 0. Only 0 should be written. This bit is reserved in the H8S/2390, H8S/2392, H8S/2394 and H8S/2398. Only 0 should be written to this bit. Bits 4 and 3—Reserved: These bits are always read as 0. Only 0 should be written to these bits. Rev.6.00 Oct.28.2004 page 670 of 1016 REJ09B0138-0600H Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the clock for the bus master. Bit 2 SCK2 0 Bit 1 SCK1 0 Bit 0 SCK0 0 1 1 0 1 1 0 0 1 1 — Description Bus master in high-speed mode Medium-speed clock is ø/2 Medium-speed clock is ø/4 Medium-speed clock is ø/8 Medium-speed clock is ø/16 Medium-speed clock is ø/32 — (Initial value) 21.2.3 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 9 8 7 6 5 4 3 2 1 0 Bit : 15 14 13 12 11 Initial value : R/W 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 15 to 0—Module Stop (MSTP 15 to MSTP 0): These bits specify module stop mode. See table 21-3 for the method of selecting on-chip supporting modules. Bits 15 to 0 MSTP15 to MSTP0 0 1 Description Module stop mode cleared Module stop mode set Rev.6.00 Oct.28.2004 page 671 of 1016 REJ09B0138-0600H 21.3 Medium-Speed Mode When the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (ø/2, ø/4, ø/8, ø/16, or ø/32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (the DMAC and DTC) also operate in mediumspeed mode. On-chip supporting modules other than the bus masters always operate on the high-speed clock (ø). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if ø/4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, a transition is made to software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is driven low, a transition is made to the reset state, and medium-speed mode is cleared. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, a transition is made to hardware standby mode. Figure 21-1 shows the timing for transition to and clearance of medium-speed mode. Medium-speed mode ø, supporting module clock Bus master clock Internal address bus SCKCR SCKCR Internal write signal Figure 21-1 Medium-Speed Mode Transition and Clearance Timing 21.4 Sleep Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers are retained. Other supporting modules do not stop. Sleep mode is cleared by a reset or any interrupt, and the CPU returns to the normal program execution state via the exception handling state. Sleep mode is not cleared if interrupts are disabled, or if interrupts other than NMI are masked by the CPU. When the STBY pin is driven low, a transition is made to hardware standby mode. Rev.6.00 Oct.28.2004 page 672 of 1016 REJ09B0138-0600H 21.5 21.5.1 Module Stop Mode Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 21-3 shows MSTP bits and the corresponding on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI and A/D converter are retained. After reset clearance, all modules other than DMAC and DTC are in module stop mode. When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. Do not make a transition to sleep mode with MSTPCR set to H'FFFF or H'EFFF, as this will halt operation of the bus controller. Table 21-3 MSTP Bits and Corresponding On-Chip Supporting Modules Register MSTPCRH Bit MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTPCRL MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Module DMA controller (DMAC) Data transfer controller (DTC) 16-bit timer pulse unit (TPU) 8-bit timer Programmable pulse generator (PPG) D/A converter A/D converter — Serial communication interface (SCI) channel 2 Serial communication interface (SCI) channel 1 Serial communication interface (SCI) channel 0 — — — — — Note: Bits 8, and 4 to 0 can be read or written to, but do not affect operation. Rev.6.00 Oct.28.2004 page 673 of 1016 REJ09B0138-0600H 21.5.2 Usage Notes DMAC/DTC Module Stop: Depending on the operating status of the DMAC or DTC, the MSTP15 and MSTP14 bits may not be set to 1. Setting of the DMAC or DTC module stop mode should be carried out only when the respective module is not activated. For details, refer to section 7, DMA Controller, and section 8, Data Transfer Controller. On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Writing to MSTPCR: MSTPCR should only be written to by the CPU. Rev.6.00 Oct.28.2004 page 674 of 1016 REJ09B0138-0600H 21.6 21.6.1 Software Standby Mode Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than the SCI and A/D converter, and I/O ports, are retained. Whether the address bus and bus control signals are placed in the high-impedance state or retain the output state can be specified by the OPE bit in SBYCR. In this mode the oscillator stops, and therefore power dissipation is significantly reduced. 21.6.2 Clearing Software Standby Mode Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ2), or by means of the RES pin or STBY pin. • Clearing with an interrupt When an NMI or IRQ0 to IRQ2 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to the entire H8S/2357 Group chip, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ2 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ2 is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. • Clearing with the RES pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire H8S/2357 Group chip. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling. • Clearing with the STBY pin When the STBY pin is driven low, a transition is made to hardware standby mode. 21.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time). Rev.6.00 Oct.28.2004 page 675 of 1016 REJ09B0138-0600H Table 21-4 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 21-4 Oscillation Stabilization Time Settings STS2 STS1 STS0 Standby Time 0 0 0 1 1 0 1 1 0 0 1 1 0 1 8,192 states 16,384 states 32,768 states 65,536 states 131,072 states 262,144 states Reserved 16 states 20 16 12 10 8 6 4 2 MHz MHz MHz MHz MHz MHz MHz MHz Unit 0.41 0.51 0.68 0.8 0.82 1.0 1.6 3.3 6.6 2.0 4.1 8.2 1.3 2.7 5.5 1.6 3.3 6.6 1.0 2.0 4.1 8.2 1.3 2.7 5.5 2.0 4.1 4.1 8.2 ms 8.2 16.4 10.9 16.4 32.8 10.9 13.1 16.4 21.8 32.8 65.5 13.1 16.4 21.8 26.2 32.8 43.6 65.6 131.2 — 0.8 — 1.0 — 1.3 — 1.6 — 2.0 — 2.7 — 4.0 — 8.0 — µs : Recommended time setting Using an External Clock: Any value can be set. Normally, use of the minimum time is recommended. Note: * The 16-state standby time cannot be used in the F-ZTAT version; a standby time of 8192 states or longer should be used. 21.6.4 Software Standby Mode Application Example Figure 21-2 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin. Rev.6.00 Oct.28.2004 page 676 of 1016 REJ09B0138-0600H Oscillator ø NMI NMIEG SSBY NMI exception Software standby mode handling (power-down mode) NMIEG=1 SSBY=1 SLEEP instruction Oscillation stabilization time tOSC2 NMI exception handling Figure 21-2 Software Standby Mode Application Example 21.6.5 Usage Notes I/O Port Status: In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus and bus control signal output is also retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. Current Dissipation during Oscillation Stabilization Wait Period: Current dissipation increases during the oscillation stabilization wait period. Write Data Buffer Function: The write data buffer function and software standby mode cannot be used at the same time. When the write data buffer function is used, the WDBE bit in BCRL should be cleared to 0 to cancel the write data buffer function before entering software standby mode. Also check that external writes have finished, by reading external addresses, etc., before executing a SLEEP instruction to enter software standby mode. See section 6.9, Write Data Buffer Function, for details of the write data buffer function. Rev.6.00 Oct.28.2004 page 677 of 1016 REJ09B0138-0600H 21.7 21.7.1 Hardware Standby Mode Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while the H8S/2357 Group is in hardware standby mode. Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator stabilizes (at least 8 ms—the oscillation stabilization time—when using a crystal oscillator). When the RES pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 21.7.2 Hardware Standby Mode Timing Figure 21-3 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation stabilization time, then changing the RES pin from low to high. Oscillator RES STBY Oscillation stabilization time Reset exception handling Figure 21-3 Hardware Standby Mode Timing (Example) Rev.6.00 Oct.28.2004 page 678 of 1016 REJ09B0138-0600H 21.8 ø Clock Output Disabling Function Output of the ø clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the ø clock stops at the end of the bus cycle, and ø output goes high. ø clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, ø clock output is disabled and input port mode is set. Table 21-5 shows the state of the ø pin in each processing state. Table 21-5 ø Pin State in Each Processing State DDR PSTOP Hardware standby mode Software standby mode Sleep mode Normal operating state 0 — High impedance High impedance High impedance High impedance Fixed high ø output ø output Fixed high Fixed high 1 0 1 Rev.6.00 Oct.28.2004 page 679 of 1016 REJ09B0138-0600H Rev.6.00 Oct.28.2004 page 680 of 1016 REJ09B0138-0600H Section 22 Electrical Characteristics 22.1 Electrical Characteristics of Masked ROM Version (H8S/2398) and ROMless Versions (H8S/2394, H8S/2392, and H8S/2390) Absolute Maximum Ratings 22.1.1 Table 22-1 Absolute Maximum Ratings Item Power supply voltage Input voltage (except port 4) Input voltage (port 4) Reference voltage Analog power supply voltage Analog input voltage Operating temperature Symbol VCC* Vin Vin Vref AVCC VAN Topr Value –0.3 to +7.0 –0.3 to + VCC +0.3 –0.3 to AVCC +0.3 –0.3 to AVCC +0.3 –0.3 to +7.0 –0.3 to AVCC +0.3 Regular specifications: –20 to +75 Wide-range specifications: –40 to +85 Storage temperature Tstg –55 to +125 Unit V V V V V V °C °C °C Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. Note: * Do not supply the power supply voltage to the V CL pin. Doing so could permanently damage the LSI. Connect an external capacitor between the VCL pin and the ground pin. Rev.6.00 Oct.28.2004 page 681 of 1016 REJ09B0138-0600H 22.1.2 DC Characteristics Table 22-2 lists the DC characteristics. Table 22-3 lists the permissible output currents. Table 22-2 DC Characteristics Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V*1, Ta = -20 to +75°C (regular specifications), Ta = -40 to +85°C (wide-range specifications) Item Schmitt trigger input voltage Input high voltage Port 2, P64 to P6 7, PA4 to PA 7 RES , STBY , NMI, MD2 to MD0 EXTAL Ports 1, 3, 5, B to G, P60 to P6 3, PA0 to PA 3 Port 4 Input low voltage RES , STBY , MD2 to MD0 NMI, EXTAL, Ports 1, 3 to 5, B to G, P60 to P6 3, PA0 to PA 3 Output high voltage Output low voltage Input leakage current All output pins VOH All output pins VOL Ports 1, A to C RES STBY , NMI, MD2 to MD0 Port 4 Ports 1 to 3, 5, 6, A to G I TSI | I in | VIL Symbol VT– VT+ VT – VT VIH + – Min 1.0 — 0.4 VCC – 0.7 Typ — — — — Max — Unit V Test Conditions VCC × 0.7 V — VCC + 0.3 V V VCC × 0.7 — 2.0 — VCC + 0.3 VCC + 0.3 V V 2.0 –0.3 –0.3 — — — AVCC + 0.3 V 0.5 0.8 V V VCC – 0.5 3.5 — — — — — — — — — — — — — — — — 0.4 1.0 10.0 1.0 1.0 1.0 V V V V µA µA µA µA I OH = –200 µA I OH = –1 mA I OL = 1.6 mA I OL = 10 mA Vin = 0.5 V to VCC – 0.5 V Vin = 0.5 V to AVCC – 0.5 V Vin = 0.5 V to VCC – 0.5 V Three-state leakage current (off state) MOS input Ports A to E pull-up current Input capacitance RES NMI All input pins except RES and NMI –I P Cin 50 — — — — — — — 300 80 50 15 µA pF pF pF Vin = 0 V Vin = 0 V f = 1 MHz T a = 25°C Rev.6.00 Oct.28.2004 page 682 of 1016 REJ09B0138-0600H Item Current dissipation * 2 Normal operation Sleep mode Standby mode * 3 Analog power supply current During A/D and D/A conversion Idle Reference current During A/D and D/A conversion Idle RAM standby voltage Symbol I CC * 4 Min — — — — Typ Max Unit mA mA µA mA Test Conditions f = 20 MHz f = 20 MHz Ta ≤ 50°C 50°C < Ta 46 69 (5.0 V) 37 56 (5.0 V) 0.01 — 10 80 Al CC — 0.8 2.0 (5.0 V) 0.01 5.0 — Al CC — µA mA 2.2 3.0 (5.0 V) 0.01 — 5.0 — — VRAM 2.0 µA V Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, AVSS, and V ref pins open. Connect AVCC and Vref to V CC pin, and connect AVSS to V SS pin. 2. Current dissipation values are for V IH min = VCC -0.2 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up MOS in the off state. 3. The values are for VRAM ≤ V CC < 4.5 V, VIH min = VCC × 0.9, and V IL max = 0.3 V. 4. I CC depends on VCC and f as follows: I CC max = 3.0 (mA) + 0.60 (mA/(MHz × V)) × V CC × f [normal mode] I CC max = 3.0 (mA) + 0.48 (mA/(MHz × V)) × V CC × f [sleep mode] Table 22-3 Permissible Output Currents Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Permissible output low current (per pin) Permissible output low current (total) Ports 1, A to C Other output pins Total of 32 pins including ports 1 and A to C Total of all output pins, including the above Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins –I OH ∑ –I OH ∑ I OL Symbol I OL Min — — — Typ — — — Max 10 2.0 80 Unit mA mA mA — — 120 mA — — — — 2.0 40 mA mA Notes: 1. To protect chip reliability, do not exceed the output current values in table 22-3. 2. When driving a darlington pair or LED directly, always insert a current-limiting resistor in the output line, as show in figures 22-1 and 22-2. Rev.6.00 Oct.28.2004 page 683 of 1016 REJ09B0138-0600H The chip 2 kΩ Port Darlington Pair Figure 22-1 Darlington Pair Drive Circuit (Example) The chip 600 Ω Ports 1, A to C LED Figure 22-2 LED Drive Circuit (Example) 22.1.3 AC Characteristics Figure 22-3 show, the test conditions for the AC characteristics. 5V RL LSI output pin C = 90 pF: Ports 1, A to F C = 30 pF: Ports 2, 3, 5, 6, G RL = 2.4 kΩ RH = 12 kΩ I/O timing test levels • Low level: 0.8 V • High level: 2.0 V C RH Figure 22-3 Output Load Circuit Rev.6.00 Oct.28.2004 page 684 of 1016 REJ09B0138-0600H (1) Clock Timing Table 22-4 lists the clock timing Table 22-4 Clock Timing Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 10 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Clock oscillator setting time at reset (crystal) Clock oscillator setting time in software standby (crystal) Symbol t cyc t CH t CL t Cr t Cf t OSC1 t OSC2 Min 50 20 20 — — 10 10 500 Max 100 — — 5 5 — — — Unit ns ns ns ns ns ms ms µs Figure 22-5 Figure 21-2 Figure 22-5 Test Conditions Figure 22-4 External clock output stabilization t DEXT delay time tcyc tCH ø tCL tCr tCf Figure 22-4 System Clock Timing Rev.6.00 Oct.28.2004 page 685 of 1016 REJ09B0138-0600H EXTAL tDEXT VCC tDEXT STBY NMI tOSC1 RES tOSC1 ø Figure 22-5 Oscillator Settling Timing (2) Control Signal Timing Table 22-5 lists the control signal timing. Table 22-5 Control Signal Timing Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 10 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (exiting software standby mode) IRQ setup time IRQ hold time IRQ pulse width (exiting software standby mode) Symbol t RESS t RESW t NMIS t NMIH t NMIW t IRQS t IRQH t IRQW Min 200 20 150 10 200 150 10 200 Max — — — — — — — — Unit ns t cyc ns ns ns ns ns ns Figure 22-7 Test Conditions Figure 22-6 Rev.6.00 Oct.28.2004 page 686 of 1016 REJ09B0138-0600H ø tRESS RES tRESW tRESS Figure 22-6 Reset Input Timing ø tNMIS NMI tNMIW tNMIH IRQ tIRQW tIRQS IRQ Edge input tIRQS IRQ Level input tIRQH Figure 22-7 Interrupt Input Timing Rev.6.00 Oct.28.2004 page 687 of 1016 REJ09B0138-0600H (3) Bus Timing Table 22-6 lists the bus timing. Table 22-6 Bus Timing Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø= 10 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition Item Address delay time Address setup time Address hold time Precharge time CS delay time 1 CS delay time 2 CS delay time 3 AS delay time RD delay time 1 RD delay time 2 CAS delay time Read data setup time Read data hold time Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Read data access time 5 WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time Write data hold time WR setup time Symbol t AD t AS t AH t PCH t CSD1 t CSD2 t CSD3 t ASD t RSD1 t RSD2 t CASD t RDS t RDH t ACC1 t ACC2 t ACC3 t ACC4 t ACC5 t WRD1 t WRD2 t WSW1 t WSW2 t WDD t WDS t WDH t WCS Min — 0.5 × t cyc – 15 0.5 × t cyc – 10 1.5 × t cyc – 20 — — — — — — — 15 0 — — — — — — — 1.0 × t cyc – 20 1.5 × t cyc – 20 — 0.5 × t cyc – 20 0.5 × t cyc – 10 0.5 × t cyc – 10 Max 20 — — — 20 20 25 20 20 20 20 — — 1.0 × t cyc – 25 1.5 × t cyc – 25 2.0 × t cyc – 25 2.5 × t cyc – 25 3.0 × t cyc – 25 20 20 — — 30 — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 22-8 to Figure 22-15 Rev.6.00 Oct.28.2004 page 688 of 1016 REJ09B0138-0600H Condition Item WR hold time CAS setup time WAIT setup time WAIT hold time BREQ setup time BACK delay time Bus-floating time BREQO delay time Symbol t WCH t CSR t WTS t WTH t BRQS t BACD t BZD t BRQOD Min 0.5 × t cyc – 10 0.5 × t cyc – 10 30 5 30 — — — Max — — — — — 15 50 30 Unit ns ns ns ns ns ns ns ns Test Conditions Figure 22-8 to Figure 22-15 Figure 22-12 Figure 22-10 Figure 22-16 Figure 22-17 T1 T2 ø tAD A23 to A0 tCSD1 CS7 to CS0 tAS tAH tASD AS tASD tRSD1 RD (read) tAS tACC2 tRSD2 tACC3 D15 to D0 (read) tWRD2 HWR, LWR (write) tRDS tRDH tWRD2 tAS tWDD tWSW1 tAH tWDH D15 to D0 (write) Figure 22-8 Basic Bus Timing (Two-State Access) Rev.6.00 Oct.28.2004 page 689 of 1016 REJ09B0138-0600H T1 T2 T3 ø tAD A23 to A0 tCSD1 CS7 to CS0 tAS tAH tASD AS tASD tRSD1 RD (read) tAS tACC4 tRSD2 tACC5 D15 to D0 (read) tRDS tRDH tWRD1 HWR, LWR (write) tWDD tWDS D15 to D0 (write) tWSW2 tWRD2 tAH tWDH Figure 22-9 Basic Bus Timing (Three-State Access) Rev.6.00 Oct.28.2004 page 690 of 1016 REJ09B0138-0600H T1 T2 TW T3 ø A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH WAIT tWTS tWTH Figure 22-10 Basic Bus Timing (Three-State Access with One Wait State) Rev.6.00 Oct.28.2004 page 691 of 1016 REJ09B0138-0600H Tp Tr TC1 TC2 ø tAD A23 to A0 tAS tPCH CS5 to CS2 (RAS) tCSD2 tAH tAD tACC4 tCSD3 tCASD tACC1 tCASD CAS tACC3 D15 to D0 (read) tWRD2 HWR, LWR (write) tWCS tWDD tWDS D15 to D0 (write) tWCH tWDH tWRD2 tRDS tRDH Figure 22-11 DRAM Bus Timing TRp TRr TRc1 TRc2 ø tCSD2 tCSD1 CS5 to CS2 (RAS) tCSR tCASD CAS tCASD Figure 22-12 CAS-Before-RAS Refresh Timing Rev.6.00 Oct.28.2004 page 692 of 1016 REJ09B0138-0600H TRp TRr TRc TRc ø tCSD2 tCSD2 CS5 to CS2 (RAS) tCASD CAS tCASD Figure 22-13 Self-Refresh Timing T1 T2 or T3 T1 T2 ø tAD A23 to A0 tAS tAH CS0 tASD tASD AS tRSD2 RD (read) tACC3 D15 to D0 (read) tRDS tRDH Figure 22-14 Burst ROM Access Timing (Two-State Access) Rev.6.00 Oct.28.2004 page 693 of 1016 REJ09B0138-0600H T1 ø T2 or T3 T1 tAD A23 to A0 CS0 AS tRSD2 RD (read) tACC1 D15 to D0 (read) tRDS tRDH Figure 22-15 Burst ROM Access Timing (One-State Access) ø tBRQS tBRQS BREQ tBACD BACK tBZD A23 to A0, CS7 to CS0, AS, RD, HWR, LWR, CAS tBACD tBZD Figure 22-16 External Bus Release Timing Rev.6.00 Oct.28.2004 page 694 of 1016 REJ09B0138-0600H ø tBRQOD tBRQOD BREQO Figure 22-17 External Bus Request Output Timing (4) DMAC Timing Table 22-7 lists the DMAC timing. Table 22-7 DMAC Timing Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 10 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition Item DREQ setup time DREQ hold time TEND delay time DACK delay time 1 DACK delay time 2 Symbol t DRQS t DRQH t TED t DACD1 t DACD2 Min 30 10 — — — Max — — 20 20 20 ns Figure 22-20 Figure 22-18, Figure 22-19 Unit ns Test Conditions Figure 22-21 Rev.6.00 Oct.28.2004 page 695 of 1016 REJ09B0138-0600H T1 T2 ø A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 DACK0 , DACK1 tDACD2 Figure 22-18 DMAC Single Address Transfer Timing (Two-State Access) Rev.6.00 Oct.28.2004 page 696 of 1016 REJ09B0138-0600H T1 ø T2 T3 A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 DACK0, DACK1 tDACD2 Figure 22-19 DMAC Single Address Transfer Timing (Three-State Access) T1 T2 or T3 ø tTED TEND0, TEND1 tTED Figure 22-20 DMAC TEND Output Timing ø tDRQS DREQ0, DREQ1 tDRQH Figure 22-21 DMAC DREQ Intput Timing Rev.6.00 Oct.28.2004 page 697 of 1016 REJ09B0138-0600H (5) Timing of On-Chip Supporting Modules Table 22-8 lists the timing of on-chip supporting modules. Table 22-8 Timing of On-Chip Supporting Modules Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 10 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition Item PORT Output data delay time Input data setup time Input data hold time TPU Symbol t PWD t PRS t PRH Min — 30 30 — — 30 30 1.5 2.5 — 30 30 1.5 2.5 4 6 t SCKW t SCKr t SCKf t TXD t RXS t RXH t TRGS 0.4 — — — 50 50 30 Max 50 — — 50 50 — — — — 50 — — — — — — 0.6 1.5 1.5 50 — — — ns ns ns ns Figure 22-31 Figure 22-30 t Scyc t cyc t cyc Figure 22-29 ns ns ns t cyc Figure 22-26 Figure 22-28 Figure 22-27 ns t cyc Figure 22-25 ns ns Figure 22-23 Figure 22-24 Unit ns Test Conditions Figure 22-22 PPG Pulse output delay time t POD Timer output delay time t TOCD Timer input setup time t TICS Timer clock input setup t TCKS time Timer clock pulse width Single edge Both edges t TCKWH t TCKWL TMR Timer output delay time t TMOD Timer reset input setup t TMRS time Timer clock input setup t TMCS time Timer clock pulse width Single edge Both edges SCI Input clock cycle t TMCWH t TMCWL Asynchro- t Scyc nous Synchronous Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) A/D Trigger input setup con- time verter Rev.6.00 Oct.28.2004 page 698 of 1016 REJ09B0138-0600H T1 ø T2 tPRS Ports 1 to 6, A to G (read) tPRH tPWD Ports 1 to 3, 5, 6, A to G (write) Figure 22-22 I/O Port Input/Output Timing ø tPOD PO15 to PO0 Figure 22-23 PPG Output Timing ø tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 22-24 TPU Input/Output Timing Rev.6.00 Oct.28.2004 page 699 of 1016 REJ09B0138-0600H ø tTCKS TCLKA to TCLKD tTCKWL tTCKWH tTCKS Figure 22-25 TPU Clock Input Timing ø tTMOD TMO0, TMO1 Figure 22-26 8-Bit Timer Output Timing ø tTMCS TMCI0, TMCI1 tTMCWL tTMCWH tTMCS Figure 22-27 8-Bit Timer Clock Input Timing ø tTMRS TMRI0, TMRI1 Figure 22-28 8-Bit Timer Reset Input Timing tSCKW SCK0 to SCK2 tSCKr tSCKf tScyc Figure 22-29 SCK Clock Input Timing Rev.6.00 Oct.28.2004 page 700 of 1016 REJ09B0138-0600H SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS RxD0 to RxD2 (receive data) tRXH Figure 22-30 SCI Input/Output Timing (Clock Synchronous Mode) ø tTRGS ADTRG Figure 22-31 A/D Converter External Trigger Input Timing 22.1.4 A/D Conversion Characteristics Table 22-9 lists the A/D conversion characteristics. Table 22-9 A/D Conversion Characteristics Conditions: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 10 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Min 10 6.7 — — — Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Notes: 1. φ ≤ 12 MHz 2. φ > 12 MHz — — — — — Typ 10 — — — — — — — — — Max 10 — 20 10* 5* 2 1 Unit bits µs pF kΩ ±3.5 ±3.5 ±3.5 ±0.5 ±4.0 LSB LSB LSB LSB LSB Rev.6.00 Oct.28.2004 page 701 of 1016 REJ09B0138-0600H 22.1.5 D/A Conversion Characteristics Table 22-10 lists the D/A conversion characteristics. Table 22-10 D/A Conversion Characteristics Conditions: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 10 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Resolution Conversion time Absolute accuracy Min 8 — — — Typ 8 — ±1.0 — Max 8 10 ±1.5 ±1.0 Unit bits µs LSB LSB 20-pF capacitive load 2-MΩ resistive load 4-MΩ resistive load Test Conditions 22.2 Usage Note (Internal Voltage Step Down for the H8S/2398, H8S/2394, H8S/2392, and H8S/2390) The H8S/2398, H8S/2394, H8S/2392, or H8S/2390 have a voltage step down circuit that automatically lowers the power supply voltage, inside the microcomputer, to an adequate level. A capacitor (one 0.47-µF capacitor or two 0.47-µF capacitors connected in parallel) should be connected between the VCL pin (a pin for internal voltage step down circuit) and VSS pin to stabilize the internal voltage. Figure 22-32 shows how to connect the capacitor. Do not connect the VCC power-supply to the VCL pin. Doing so could permanently damage the LSI. (Connect the VCC power-supply to the VCC pin, in the usual way.) An external capacitor to stabilize the internal voltage VCL One 0.47-µF capacitor or two 0.47-µF capacitors connected in parallel VSS Do not connect the VCC power-supply to the VCL pin. Doing so could permanently damage the LSI. (Connect the VCC power-supply to the other VCC pin in the usual way.) Use a multilayer ceramic capacitor (one 0.47-µF capacitor or two 0.47-µF capacitors connected in parallel) for this circuit, and place it/them near the VCL pin. Figure 22-32 VCL Capacitor Connection Method Rev.6.00 Oct.28.2004 page 702 of 1016 REJ09B0138-0600H 22.3 22.3.1 Electrical Characteristics of H8S/2398 F-ZTAT Absolute Maximum Ratings Table 22-11 Absolute Maximum Ratings Item Power supply voltage Input voltage (except port 4) Input voltage (port 4) Reference voltage Analog power supply voltage Analog input voltage Operating temperature Symbol VCC* Vin Vin Vref AVCC VAN Topr 1 Value –0.3 to +7.0 –0.3 to + VCC +0.3 –0.3 to AVCC +0.3 –0.3 to AVCC +0.3 –0.3 to +7.0 –0.3 to AVCC +0.3 Regular specifications: –20 to +75* 2 2 Unit V V V V V V °C °C °C Wide-range specifications: –40 to +85* Storage temperature Tstg –55 to +125 Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. Notes: 1. Do not supply the power supply voltage to the V CL pin. Doing so could permanently damage the LSI. Connect an external capacitor between the VCL pin and the ground pin. 2. The operating temperature ranges for flash memory programming/erasing are as follows: T a = 0 to +75°C (regular specifications), Ta = 0 to +85°C (wide-range specifications). Rev.6.00 Oct.28.2004 page 703 of 1016 REJ09B0138-0600H 22.3.2 DC Characteristics Table 22-12 lists the DC characteristics. Table 22-13 lists the permissible output currents. Table 22-12 DC Characteristics Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V*1, Ta = -20 to +75°C (regular specifications), T a = -40 to +85°C (wide-range specifications) Item Schmitt trigger input voltage Input high voltage Port 2, P64 to P6 7, PA4 to PA 7 RES , STBY , NMI, MD2 to MD0 EXTAL Ports 1, 3, 5, B to G, P60 to P6 3, PA0 to PA 3 Port 4 Input low voltage RES , STBY , MD2 to MD0 NMI, EXTAL, Ports 1, 3 to 5, B to G, P60 to P6 3, PA0 to PA 3 Output high voltage Output low voltage Input leakage current All output pins VOH All output pins VOL Ports 1, A to C RES STBY , NMI, MD2 to MD0 Port 4 Ports 1 to 3, 5, 6, A to G I TSI | I in | VIL Symbol VT– VT+ VT – VT VIH + – Min 1.0 — 0.4 VCC – 0.7 Typ — — — — Max — Unit V Test Conditions VCC × 0.7 V — VCC + 0.3 V V VCC × 0.7 — 2.0 — VCC + 0.3 VCC + 0.3 V V 2.0 –0.3 –0.3 — — — AVCC + 0.3 V 0.5 0.8 V V VCC – 0.5 3.5 — — — — — — — — — — — — — — — — 0.4 1.0 10.0 1.0 1.0 1.0 V V V V µA µA µA µA I OH = –200 µA I OH = –1 mA I OL = 1.6 mA I OL = 10 mA Vin = 0.5 V to VCC – 0.5 V Vin = 0.5 V to AVCC – 0.5 V Vin = 0.5 V to VCC – 0.5 V Three-state leakage current (off state) MOS input Ports A to E pull-up current Input capacitance RES NMI All input pins except RES and NMI –I P Cin 50 — — — — — — — 300 80 50 15 µA pF pF pF Vin = 0 V Vin = 0 V f = 1 MHz T a = 25°C Rev.6.00 Oct.28.2004 page 704 of 1016 REJ09B0138-0600H Item Current dissipation * 2 Normal operation Sleep mode Standby mode * 3 Analog power supply current During A/D and D/A conversion Idle Reference current During A/D and D/A conversion Idle RAM standby voltage Symbol I CC * 4 Min — — — — Typ Max Unit mA mA µA mA Test Conditions f = 20 MHz f = 20 MHz Ta ≤ 50°C 50°C < Ta 46 69 (5.0 V) 37 56 (5.0 V) 0.01 — 10 80 Al CC — 0.8 2.0 (5.0 V) 0.01 5.0 — Al CC — µA mA 2.2 3.0 (5.0 V) 0.01 — 5.0 — — VRAM 2.0 µA V Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, AVSS, and V ref pins open. Connect AVCC and Vref to V CC pin, and connect AVSS to V SS pin. 2. Current dissipation values are for V IH min = VCC -0.2 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up MOS in the off state. 3. The values are for VRAM ≤ V CC < 4.5 V, VIH min = VCC × 0.9, and V IL max = 0.3 V. 4. I CC depends on VCC and f as follows: I CC max = 3.0 (mA) + 0.60 (mA/(MHz × V)) × V CC × f [normal mode] I CC max = 3.0 (mA) + 0.48 (mA/(MHz × V)) × V CC × f [sleep mode] Table 22-13 Permissible Output Currents Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Permissible output low current (per pin) Permissible output low current (total) Ports 1, A to C Other output pins Total of 32 pins including ports 1 and A to C Total of all output pins, including the above Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins –I OH ∑ –I OH ∑ I OL Symbol I OL Min — — — Typ — — — Max 10 2.0 80 Unit mA mA mA — — 120 mA — — — — 2.0 40 mA mA Notes: 1. To protect chip reliability, do not exceed the output current values in table 22-13. 2. When driving a darlington pair or LED directly, always insert a current-limiting resistor in the output line, as show in figures 22-33 and 22-34. Rev.6.00 Oct.28.2004 page 705 of 1016 REJ09B0138-0600H The chip 2 kΩ Port Darlington Pair Figure 22-33 Darlington Pair Drive Circuit (Example) The chip 600 Ω Ports 1, A to C LED Figure 22-34 LED Drive Circuit (Example) 22.3.3 AC Characteristics Figure 22-35 show, the test conditions for the AC characteristics. 5V RL LSI output pin C = 90 pF: Ports 1, A to F C = 30 pF: Ports 2, 3, 5, 6, G RL = 2.4 kΩ RH = 12 kΩ I/O timing test levels • Low level: 0.8 V • High level: 2.0 V C RH Figure 22-35 Output Load Circuit Rev.6.00 Oct.28.2004 page 706 of 1016 REJ09B0138-0600H (1) Clock Timing Table 22-14 lists the clock timing Table 22-14 Clock Timing Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 10 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Clock oscillator setting time at reset (crystal) Clock oscillator setting time in software standby (crystal) Symbol t cyc t CH t CL t Cr t Cf t OSC1 t OSC2 Min 50 20 20 — — 10 10 500 Max 100 — — 5 5 — — — Unit ns ns ns ns ns ms ms µs Figure 22-37 Figure 21-2 Figure 22-37 Test Conditions Figure 22-36 External clock output stabilization t DEXT delay time tcyc tCH ø tCL tCr tCf Figure 22-36 System Clock Timing Rev.6.00 Oct.28.2004 page 707 of 1016 REJ09B0138-0600H EXTAL tDEXT VCC tDEXT STBY NMI tOSC1 RES tOSC1 ø Figure 22-37 Oscillator Settling Timing (2) Control Signal Timing Table 22-15 lists the control signal timing. Table 22-15 Control Signal Timing Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 10 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (exiting software standby mode) IRQ setup time IRQ hold time IRQ pulse width (exiting software standby mode) Symbol t RESS t RESW t NMIS t NMIH t NMIW t IRQS t IRQH t IRQW Min 200 20 150 10 200 150 10 200 Max — — — — — — — — Unit ns t cyc ns ns ns ns ns ns Figure 22-39 Test Conditions Figure 22-38 Rev.6.00 Oct.28.2004 page 708 of 1016 REJ09B0138-0600H ø tRESS RES tRESW tRESS Figure 22-38 Reset Input Timing ø tNMIS NMI tNMIW tNMIH IRQ tIRQW tIRQS IRQ Edge input tIRQS IRQ Level input tIRQH Figure 22-39 Interrupt Input Timing Rev.6.00 Oct.28.2004 page 709 of 1016 REJ09B0138-0600H (3) Bus Timing Table 22-16 lists the bus timing. Table 22-16 Bus Timing Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø= 10 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition Item Address delay time Address setup time Address hold time Precharge time CS delay time 1 CS delay time 2 CS delay time 3 AS delay time RD delay time 1 RD delay time 2 CAS delay time Read data setup time Read data hold time Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Read data access time 5 WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time Write data hold time WR setup time Symbol t AD t AS t AH t PCH t CSD1 t CSD2 t CSD3 t ASD t RSD1 t RSD2 t CASD t RDS t RDH t ACC1 t ACC2 t ACC3 t ACC4 t ACC5 t WRD1 t WRD2 t WSW1 t WSW2 t WDD t WDS t WDH t WCS Min — 0.5 × t cyc – 15 0.5 × t cyc – 10 1.5 × t cyc – 20 — — — — — — — 15 0 — — — — — — — 1.0 × t cyc – 20 1.5 × t cyc – 20 — 0.5 × t cyc – 20 0.5 × t cyc – 10 0.5 × t cyc – 10 Max 20 — — — 20 20 25 20 20 20 20 — — 1.0 × t cyc – 25 1.5 × t cyc – 25 2.0 × t cyc – 25 2.5 × t cyc – 25 3.0 × t cyc – 25 20 20 — — 30 — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 22-40 to Figure 22-47 Rev.6.00 Oct.28.2004 page 710 of 1016 REJ09B0138-0600H Condition Item WR hold time CAS setup time WAIT setup time WAIT hold time BREQ setup time BACK delay time Bus-floating time BREQO delay time Symbol t WCH t CSR t WTS t WTH t BRQS t BACD t BZD t BRQOD Min 0.5 × t cyc – 10 0.5 × t cyc – 10 30 5 30 — — — Max — — — — — 15 50 30 Unit ns ns ns ns ns ns ns ns Test Conditions Figure 22-40 to Figure 22-47 Figure 22-44 Figure 22-42 Figure 22-48 Figure 22-49 T1 T2 ø tAD A23 to A0 tCSD1 CS7 to CS0 tAS tAH tASD AS tASD tRSD1 RD (read) tAS tACC2 tRSD2 tACC3 D15 to D0 (read) tWRD2 HWR, LWR (write) tRDS tRDH tWRD2 tAS tWDD tWSW1 tAH tWDH D15 to D0 (write) Figure 22-40 Basic Bus Timing (Two-State Access) Rev.6.00 Oct.28.2004 page 711 of 1016 REJ09B0138-0600H T1 T2 T3 ø tAD A23 to A0 tCSD1 CS7 to CS0 tAS tAH tASD AS tASD tRSD1 RD (read) tAS tACC4 tRSD2 tACC5 D15 to D0 (read) tRDS tRDH tWRD1 HWR, LWR (write) tWDD tWDS D15 to D0 (write) tWSW2 tWRD2 tAH tWDH Figure 22-41 Basic Bus Timing (Three-State Access) Rev.6.00 Oct.28.2004 page 712 of 1016 REJ09B0138-0600H T1 T2 TW T3 ø A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH WAIT tWTS tWTH Figure 22-42 Basic Bus Timing (Three-State Access with One Wait State) Rev.6.00 Oct.28.2004 page 713 of 1016 REJ09B0138-0600H Tp Tr TC1 TC2 ø tAD A23 to A0 tAS tPCH CS5 to CS2 (RAS) tCSD2 tAH tAD tACC4 tCSD3 tCASD tACC1 tCASD CAS tACC3 D15 to D0 (read) tWRD2 HWR, LWR (write) tWCS tWDD tWDS D15 to D0 (write) tWCH tWDH tWRD2 tRDS tRDH Figure 22-43 DRAM Bus Timing TRp TRr TRc1 TRc2 ø tCSD2 tCSD1 CS5 to CS2 (RAS) tCSR tCASD CAS tCASD Figure 22-44 CAS-Before-RAS Refresh Timing Rev.6.00 Oct.28.2004 page 714 of 1016 REJ09B0138-0600H TRp TRr TRc TRc ø tCSD2 tCSD2 CS5 to CS2 (RAS) tCASD CAS tCASD Figure 22-45 Self-Refresh Timing T1 T2 or T3 T1 T2 ø tAD A23 to A0 tAS tAH CS0 tASD tASD AS tRSD2 RD (read) tACC3 D15 to D0 (read) tRDS tRDH Figure 22-46 Burst ROM Access Timing (Two-State Access) Rev.6.00 Oct.28.2004 page 715 of 1016 REJ09B0138-0600H T1 ø T2 or T3 T1 tAD A23 to A0 CS0 AS tRSD2 RD (read) tACC1 D15 to D0 (read) tRDS tRDH Figure 22-47 Burst ROM Access Timing (One-State Access) ø tBRQS tBRQS BREQ tBACD BACK tBZD A23 to A0, CS7 to CS0, AS, RD, HWR, LWR, CAS tBACD tBZD Figure 22-48 External Bus Release Timing Rev.6.00 Oct.28.2004 page 716 of 1016 REJ09B0138-0600H ø tBRQOD tBRQOD BREQO Figure 22-49 External Bus Request Output Timing (4) DMAC Timing Table 22-17 lists the DMAC timing. Table 22-17 DMAC Timing Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 10 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition Item DREQ setup time DREQ hold time TEND delay time DACK delay time 1 DACK delay time 2 Symbol t DRQS t DRQH t TED t DACD1 t DACD2 Min 30 10 — — — Max — — 20 20 20 ns Figure 22-52 Figure 22-50, Figure 22-51 Unit ns Test Conditions Figure 22-53 Rev.6.00 Oct.28.2004 page 717 of 1016 REJ09B0138-0600H T1 T2 ø A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 DACK0 , DACK1 tDACD2 Figure 22-50 DMAC Single Address Transfer Timing (Two-State Access) Rev.6.00 Oct.28.2004 page 718 of 1016 REJ09B0138-0600H T1 ø T2 T3 A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 DACK0, DACK1 tDACD2 Figure 22-51 DMAC Single Address Transfer Timing (Three-State Access) T1 T2 or T3 ø tTED TEND0, TEND1 tTED Figure 22-52 DMAC TEND Output Timing ø tDRQS DREQ0, DREQ1 tDRQH Figure 22-53 DMAC DREQ Intput Timing Rev.6.00 Oct.28.2004 page 719 of 1016 REJ09B0138-0600H (5) Timing of On-Chip Supporting Modules Table 22-18 lists the timing of on-chip supporting modules. Table 22-18 Timing of On-Chip Supporting Modules Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 10 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition Item PORT Output data delay time Input data setup time Input data hold time TPU Symbol t PWD t PRS t PRH Min — 30 30 — — 30 30 1.5 2.5 — 30 30 1.5 2.5 4 6 t SCKW t SCKr t SCKf t TXD t RXS t RXH t TRGS 0.4 — — — 50 50 30 Max 50 — — 50 50 — — — — 50 — — — — — — 0.6 1.5 1.5 50 — — — ns ns ns ns Figure 22-63 Figure 22-62 t Scyc t cyc t cyc Figure 22-61 ns ns ns t cyc Figure 22-58 Figure 22-60 Figure 22-59 ns t cyc Figure 22-57 ns ns Figure 22-55 Figure 22-56 Unit ns Test Conditions Figure 22-54 PPG Pulse output delay time t POD Timer output delay time t TOCD Timer input setup time t TICS Timer clock input setup t TCKS time Timer clock pulse width Single edge Both edges t TCKWH t TCKWL TMR Timer output delay time t TMOD Timer reset input setup t TMRS time Timer clock input setup t TMCS time Timer clock pulse width Single edge Both edges SCI Input clock cycle t TMCWH t TMCWL Asynchro- t Scyc nous Synchronous Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) A/D Trigger input setup con- time verter Rev.6.00 Oct.28.2004 page 720 of 1016 REJ09B0138-0600H T1 ø T2 tPRS Ports 1 to 6, A to G (read) tPRH tPWD Ports 1 to 3, 5, 6, A to G (write) Figure 22-54 I/O Port Input/Output Timing ø tPOD PO15 to PO0 Figure 22-55 PPG Output Timing ø tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 22-56 TPU Input/Output Timing Rev.6.00 Oct.28.2004 page 721 of 1016 REJ09B0138-0600H ø tTCKS TCLKA to TCLKD tTCKWL tTCKWH tTCKS Figure 22-57 TPU Clock Input Timing ø tTMOD TMO0, TMO1 Figure 22-58 8-Bit Timer Output Timing ø tTMCS TMCI0, TMCI1 tTMCWL tTMCWH tTMCS Figure 22-59 8-Bit Timer Clock Input Timing ø tTMRS TMRI0, TMRI1 Figure 22-60 8-Bit Timer Reset Input Timing tSCKW SCK0 to SCK2 tSCKr tSCKf tScyc Figure 22-61 SCK Clock Input Timing Rev.6.00 Oct.28.2004 page 722 of 1016 REJ09B0138-0600H SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS RxD0 to RxD2 (receive data) tRXH Figure 22-62 SCI Input/Output Timing (Clock Synchronous Mode) ø tTRGS ADTRG Figure 22-63 A/D Converter External Trigger Input Timing 22.3.4 A/D Conversion Characteristics Table 22-19 lists the A/D conversion characteristics. Table 22-19 A/D Conversion Characteristics Conditions: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 10 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Min 10 6.7 — — — Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Notes: 1. φ ≤ 12 MHz 2. φ > 12 MHz — — — — — Typ 10 — — — — — — — — — Max 10 — 20 10* 5* 2 1 Unit bits µs pF kΩ ±3.5 ±3.5 ±3.5 ±0.5 ±4.0 LSB LSB LSB LSB LSB Rev.6.00 Oct.28.2004 page 723 of 1016 REJ09B0138-0600H 22.3.5 D/A Conversion Characteristics Table 22-20 lists the D/A conversion characteristics. Table 22-20 D/A Conversion Characteristics Conditions: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 10 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Resolution Conversion time Absolute accuracy Min 8 — — — Typ 8 — ±1.0 — Max 8 10 ±1.5 ±1.0 Unit bits µs LSB LSB 20-pF capacitive load 2-MΩ resistive load 4-MΩ resistive load Test Conditions 22.3.6 Flash Memory Characteristics Table 22-21 Flash Memory Characteristics (HD64F2398F20, HD64F2398TE20) Conditions: VCC = 5.0 V ± 10%, AV CC = 5.0 V ± 10%, Vref = 4.5 V to AV CC, VSS = AVSS = 0V Ta = 0 to +75°C (Programming/erasing operating temperature, regular specifications), Ta = 0 to + 85°C (Programming/erasing operating temperature, wide-range specifications) Item Programming time*1* 2* 4 Erase time* 1* 3* 6 Reprogramming count Programming Wait time after SWE bit setting * 1 Wait time after PSU bit setting * 1 Wait time after P bit setting * 1* 4 Symbol Min tP tE NWEC x y z — — — 1 50 (z1) — (z2) — (z3) — Typ 10 50 — — — — — — Max 200 1000 100 — — 30 200 10 Unit ms/128 bytes ms/block Times µs µs µs µs µs 1≤n≤6 7 ≤ n ≤ 1000 Test Condition Additional programming wait Wait time after P bit clear*1 α Wait time after PSU bit clear*1 Wait time after PV bit setting * 1 β γ 5 5 4 2 2 — — — — — — — — — — µs µs µs µs µs Wait time after H'FF dummy ε write* 1 Wait time after PV bit clear * 1η Rev.6.00 Oct.28.2004 page 724 of 1016 REJ09B0138-0600H Item Symbol Min 100 — 1 100 — 10 10 20 2 4 100 — Typ — — — — — — — — — — — — Max — 5 Unit µs Test Condition Programming Wait time after SWE bit clear* 1 θ Maximum programming count* 1* 4 Erase Wait time after SWE bit setting * 1 Wait time after ESU bit setting * 1 N x y 1000* Times — — 10 — — — — — — 100 µs µs ms µs µs µs µs µs µs Times Erase time wait Wait time after E bit setting * 1* 6 z Wait time after E bit clear*1 Wait time after ESU bit clear* 1 1 α β γ ε η 1 Wait time after EV bit setting * Wait time after H’FF dummy write* 1 Wait time after EV bit clear * 1 Wait time after SWE bit clear* Maximum erase count * * 1 6 θ N Notes: 1. Settings of each time must comply with algorithm of writing/erasing. 2. Writing time for 128 bytes: indicates the total period in which bit P of flash memory control register 1 (FLMCR1) is set. Writing verification time is not included. 3. Erasing time for one block: indicates the period in which bit E of FLMCR1 is set. Erasing verification time is not included. 4. Maximum writing time: tP(max) = Σ wait time (z) after setting of bit P 5. The maximum writing count (N) must be set to the maximum writing time (tP(max)) or less according the actual set value (z). Wait time (z) must be switched after setting of bit P according to writing count (n). Writing count n 1≤n≤6 z = 30 µs 7 ≤ n ≤ 1000 z = 200 µs [In additional writing] Writing count n 1≤n≤6 z = 10 µs 6. Wait time (z) after setting of bit E and the maximum erasing count (N) have the following relationship to the maximum erasing time (tE(max)). t E(max) = wait time (z) after setting of bit E × maximum erasing count (N) Rev.6.00 Oct.28.2004 page 725 of 1016 REJ09B0138-0600H Table 22-22 Flash Memory Characteristics (HD64F2398F20T, HD64F2398TE20T) Conditions: VCC = 5.0 V ± 10%, AV CC = 5.0 V ± 10%, Vref = 4.5 V to AV CC, VSS = AVSS = 0V Ta = 0 to +75°C (Programming/erasing operating temperature, regular specifications), Ta = 0 to + 85°C (Programming/erasing operating temperature, wide-range specifications) Item Programming time*1* 2* 4 Erase time* 1* 3* 6 Reprogramming count 1 Symbol Min tP tE NWEC 1 Typ 10 50 — — — — — — Max 200 1000 1000 — — 30 200 10 Unit ms/128 bytes ms/block Times µs µs µ µs µs Test Condition — — — 1 50 — — — Programming Wait time after SWE bit setting* x Wait time after PSU bit setting* y Wait time after P bit setting * * 1 4 z (z1) (z2) (z3) s1 ≤ n ≤ 6 7 ≤ n ≤ 1000 Additional programming wait Wait time after P bit clear*1 Wait time after PSU bit clear* 1 1 α β γ ε η 1 5 5 4 2 2 100 — 1 100 — 10 10 20 2 4 100 — — — — — — — — — — — — — — — — — — — — — — — — 5 µs µs µs µs µs µs Wait time after PV bit setting * Wait time after H'FF dummy write* 1 Wait time after PV bit clear * 1 Wait time after SWE bit clear* Maximum programming count* 1* 4 Erase Wait time after SWE bit setting * 1 Wait time after ESU bit setting * 1 θ N x y 1000* Times — — 10 — — — — — — 100 µs µs ms µs µs µs µs µs µs Times Erase time wait Wait time after E bit setting * 1* 6 z Wait time after E bit clear*1 Wait time after ESU bit clear* 1 1 α β γ ε η 1 Wait time after EV bit setting * Wait time after H’FF dummy write* 1 Wait time after EV bit clear * 1 Wait time after SWE bit clear* Maximum erase count * * 1 6 θ N Notes: 1. Settings of each time must comply with algorithm of writing/erasing. 2. Writing time for 128 bytes: indicates the total period in which bit P of flash memory control register 1 (FLMCR1) is set. Writing verification time is not included. 3. Erasing time for one block: indicates the period in which bit E of FLMCR1 is set. Erasing verification time is not included. 4. Maximum writing time: tP(max) = Σ wait time (z) after setting of bit P Rev.6.00 Oct.28.2004 page 726 of 1016 REJ09B0138-0600H 5. The maximum writing count (N) must be set to the maximum writing time (tP(max)) or less according the actual set value (z). Wait time (z) must be switched after setting of bit P according to writing count (n). Writing count n 1≤n≤6 z = 30 µs 7 ≤ n ≤ 1000 z = 200 µs [In additional writing] Writing count n 1≤n≤6 z = 10 µs 6. Wait time (z) after setting of bit E and the maximum erasing count (N) have the following relationship to the maximum erasing time (tE(max)). t E(max) = wait time (z) after setting of bit E × maximum erasing count (N) 22.4 Notes on Use The F-ZTAT and masked ROM versions satisfy electrical characteristics described in this manual. However, actual electrical characteristics values, operation margins, and noise margins depend on differences in manufacturing processes, on-chip ROM, or layout patterns. If the system is evaluated using the F-ZTAT version, perform the same evaluation test of the system using the masked ROM version when switching to the masked ROM version. 22.5 Usage Note (Internal Voltage Step Down for the H8S/2398 F-ZTAT) The H8S/2398 F-ZTAT have a voltage step down circuit that automatically lowers the power supply voltage, inside the microcomputer, to an adequate level. A capacitor (one 0.47-µF capacitor or two 0.47-µF capacitors connected in parallel) should be connected between the VCL pin (a pin for internal voltage step down circuit) and VSS pin to stabilize the internal voltage. Figure 22-64 shows how to connect the capacitor. Do not connect the VCC power-supply to the VCL pin. Doing so could permanently damage the LSI. (Connect the V CC power-supply to the VCC pin, in the usual way.) An external capacitor to stabilize the internal voltage VCL One 0.47-µF capacitor or two 0.47-µF capacitors connected in parallel VSS Do not connect the VCC power-supply to the VCL pin. If connected, the LSI may be permanently damaged. Connect the VCC power-supply to the other VCC pin in the usual way. Use a multilayer ceramic capacitor (one 0.47-µF capacitor or two 0. 47-µF capacitors connected in parallel) for this circuit, and place it/them near the VCL pin. Figure 22-64 VCL Capacitor Connection Method Rev.6.00 Oct.28.2004 page 727 of 1016 REJ09B0138-0600H 22.6 Electrical Characteristics of H8S/2357 Masked ROM and ZTAT Versions, and H8S/2352 Absolute Maximum Ratings 22.6.1 Table 22-23 lists the absolute maximum ratings. Table 22-23 Absolute Maximum Ratings Item Power supply voltage Programming voltage * Input voltage (except port 4) Input voltage (port 4) Reference voltage Analog power supply voltage Analog input voltage Operating temperature Symbol VCC VPP Vin Vin Vref AVCC VAN Topr Value –0.3 to +7.0 –0.3 to +13.5 –0.3 to VCC +0.3 –0.3 to AVCC +0.3 –0.3 to AVCC +0.3 –0.3 to +7.0 –0.3 to AVCC +0.3 Regular specifications: –20 to +75 Wide-range specifications: –40 to +85 Storage temperature Tstg –55 to +125 Unit V V V V V V V °C °C °C Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded. Note: * ZTAT version only 22.6.2 DC Characteristics Table 22-24 lists the DC characteristics. Table 22-25 lists the permissible output currents. Table 22-24 DC Characteristics (1) Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20 to +75°C (regular specifications), T a = –40 to +85°C (wide-range specifications) Item Schmitt trigger input voltage Input high voltage Port 2, P64 to P6 7, PA4 to PA 7 RES , STBY , NMI, MD2 to MD0 EXTAL Ports 1, 3, 5, B to G, P60 to P6 3, PA0 to PA 3 Port 4 Symbol VT VT – + + – Min 1.0 — 0.4 VCC – 0.7 Typ — — — — Max — Unit V Test Conditions VCC × 0.7 V — VCC + 0.3 V V VT – VT VIH VCC × 0.7 — 2.0 — VCC + 0.3 VCC + 0.3 V V 2.0 — AVCC + 0.3 V Rev.6.00 Oct.28.2004 page 728 of 1016 REJ09B0138-0600H Item Input low voltage RES , STBY , MD2 to MD0 NMI, EXTAL, Ports 1, 3 to 5, B to G, P60 to P6 3, PA0 to PA 3 Output high voltage Output low voltage Input leakage current Symbol VIL Min –0.3 –0.3 Typ — — Max 0.5 0.8 Unit V V Test Conditions All output pins VOH All output pins VOL Ports 1, A to C RES STBY , NMI, MD2 to MD0 Port 4 Ports 1 to 3, 5, 6, A to G I TSI | I in | VCC – 0.5 3.5 — — — — — — — — — — — — — — — — 0.4 1.0 10.0 1.0 1.0 1.0 V V V V µA µA µA µA I OH = –200 µA I OH = –1 mA I OL = 1.6 mA I OL = 10 mA Vin = 0.5 V to VCC – 0.5 V Vin = 0.5 V to AVCC – 0.5 V Vin = 0.5 V to VCC – 0.5 V Three-state leakage current (off state) MOS input Ports A to E pull-up current Input capacitance RES NMI All input pins except RES and NMI Current dissipation * 2 Normal operation Sleep mode Standby mode * 3 Analog power supply current During A/D and D/A conversion Idle Reference current During A/D and D/A conversion Idle RAM standby voltage –I P Cin 50 — — — — — — — 300 80 50 15 µA pF pF pF Vin = 0 V Vin = 0 V f = 1 MHz T a = 25°C I CC * 4 — — — — 78 122 (5.0 V) 53 84 (5.0 V) 0.01 — 5.0 20.0 mA mA µA mA f = 20 MHz f = 20 MHz Ta ≤ 50°C 50°C < Ta Al CC — 0.8 2.0 (5.0 V) 0.01 5.0 — Al CC — µA mA 2.3 3.0 (5.0 V) 0.01 — 5.0 — — VRAM 2.0 µA V Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, AVSS, and V ref pins open. Connect AVCC and Vref to V CC, and connect AVSS to V SS . 2. Current dissipation values are for V IH min = VCC –0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM ≤ V CC < 4.5 V, VIH min = VCC × 0.9, and V IL max = 0.3 V. 4. I CC depends on VCC and f as follows: I CC max = 1.0 (mA) + 1.1 (mA/(MHz × V)) × V CC × f [normal mode] I CC max = 1.0 (mA) + 0.75 (mA/(MHz × V)) × V CC × f [sleep mode] Rev.6.00 Oct.28.2004 page 729 of 1016 REJ09B0138-0600H Table 22-24 DC Characteristics (2) Conditions: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Schmitt trigger input voltage Input high voltage Port 2, P64 to P6 7, PA4 to PA 7 RES , STBY , NMI, MD2 to MD0 EXTAL Ports 1, 3, 5, B to G, P60 to P6 3, PA0 to PA 3 Port 4 Input low voltage RES , STBY , MD2 to MD0 NMI, EXTAL, Ports 1, 3 to 5, B to G, P60 to P6 3, PA0 to PA 3 Output high voltage Output low voltage All output pins VOH VIL Symbol VT VT – + + – Min Typ Max — Unit V Test Conditions VCC × 0.2 — — — VCC × 0.07 — VCC × 0.9 — VCC × 0.7 V — VCC +0.3 V V VT – VT VIH VCC × 0.7 — VCC × 0.7 — VCC +0.3 VCC +0.3 V V VCC × 0.7 — –0.3 –0.3 — — AVCC +0.3 V VCC × 0.1 V VCC × 0.2 V VCC < 4.0 V 0.8 VCC – 0.5 VCC – 1.0 — — — — — — 0.4 1.0 V V V V VCC = 4.0 to 5.5 V I OH = –200 µA I OH = –1 mA I OL = 1.6 mA VCC ≤ 4.0 V I OL = 5 mA 4.0 < VCC ≤ 5.5 V I OL = 10 mA Vin = 0.5 V to VCC – 0.5 V Vin = 0.5 V to AVCC – 0.5 V Vin = 0.5 V to VCC –0.5 V All output pins VOL Ports 1, A to C — — Input leakage current RES STBY , NMI, MD2 to MD0 Port 4 | I in | — — — — — — — 10.0 1.0 1.0 1.0 µA µA µA µA Three-state leakage current (off state) Ports 1 to 3, 5, 6, A to G I TSI — MOS input Ports A to E pull-up current Input capacitance RES NMI All input pins except RES and NMI –I P Cin 10 — — — — — — — 300 80 50 15 µA pF pF pF VCC = 2.7 to 5.5 V, Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25°C Rev.6.00 Oct.28.2004 page 730 of 1016 REJ09B0138-0600H Item Current dissipation * 2 Normal operation Sleep mode Standby mode * 3 Analog power supply current During A/D and D/A conversion Idle Reference current During A/D and D/A conversion Idle RAM standby voltage Symbol I CC * 4 Min — — — — Typ Max Unit mA mA µA mA Test Conditions f = 10 MHz f = 10 MHz Ta ≤ 50°C 50°C < Ta 23 62 (3.0 V) 16 42 (3.0 V) 0.01 — 5.0 20.0 Al CC — 0.2 2.0 (3.0 V) 0.01 5.0 — Al CC — µA mA 1.4 3.0 (3.0 V) 0.01 — 5.0 — — VRAM 2.0 µA V Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, AVSS, and V ref pins open. Connect AVCC and Vref to V CC, and connect AVSS to V SS . 2. Current dissipation values are for V IH min = VCC –0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM ≤ V CC < 2.7 V, VIH min = VCC × 0.9, and V IL max = 0.3 V. 4. I CC depends on VCC and f as follows: I CC max = 1.0 (mA) + 1.1 (mA/(MHz × V)) × V CC × f [normal mode] I CC max = 1.0 (mA) + 0.75 (mA/(MHz × V)) × V CC × f [sleep mode] Table 22-24 DC Characteristics (3) Conditions: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Schmitt trigger input voltage Input high voltage Port 2, P64 to P6 7, PA4 to PA 7 RES , STBY , NMI, MD2 to MD0 EXTAL Ports 1, 3, 5, B to G, P60 to P6 3, PA0 to PA 3 Port 4 Input low voltage RES , STBY , MD2 to MD0 NMI, EXTAL, Ports 1, 3 to 5, B to G, P60 to P6 3, PA0 to PA 3 VIL Symbol VT VT – + + – Min Typ Max — Unit V Test Conditions VCC × 0.2 — — — VCC × 0.07 — VCC × 0.9 — VCC × 0.7 V — VCC +0.3 V V VT – VT VIH VCC × 0.7 — VCC × 0.7 — VCC +0.3 VCC +0.3 V V VCC × 0.7 — –0.3 –0.3 — — AVCC +0.3 V VCC × 0.1 V VCC × 0.2 V VCC < 4.0 V 0.8 VCC = 4.0 to 5.5 V Rev.6.00 Oct.28.2004 page 731 of 1016 REJ09B0138-0600H Item Output high voltage Output low voltage Symbol All output pins VOH Min VCC – 0.5 VCC – 1.0 Typ — — — — Max — — 0.4 1.0 Unit V V V V Test Conditions I OH = –200 µA I OH = –1 mA I OL = 1.6 mA VCC ≤ 4.0 V I OL = 5 mA 4.0 < VCC ≤ 5.5 V I OL = 10 mA Vin = 0.5 V to VCC – 0.5 V All output pins VOL Ports 1, A to C — — Input leakage current RES STBY , NMI, MD2 to MD0 Port 4 | I in | — — — — — — — 10.0 1.0 1.0 1.0 µA µA µA µA Vin = 0.5 V to AVCC – 0.5 V Vin = 0.5 V to VCC –0.5 V Three-state leakage current (off state) Ports 1 to 3, 5, 6, A to G I TSI — MOS input Ports A to E pull-up current Input capacitance RES NMI All input pins except RES and NMI Current dissipation * 2 Normal operation Sleep mode Standby mode * 3 Analog power supply current During A/D and D/A conversion Idle Reference current During A/D and D/A conversion Idle RAM standby voltage –I P Cin 10 — — — — — — — 300 80 50 15 µA pF pF pF VCC = 3.0 to 5.5 V, Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25°C I CC * 4 — — — — 32 80 (3.3 V) 22 55 (3.3 V) 0.01 — 5.0 20 mA mA µA mA f = 13 MHz f = 13 MHz Ta ≤ 50°C 50°C < Ta Al CC — 0.3 2.0 (3.3 V) 0.01 5.0 — Al CC — µA mA 1.6 3.0 (3.3 V) 0.01 — 5.0 — — VRAM 2.0 µA V Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, AVSS, and V ref pins open. Connect AVCC and Vref to V CC, and connect AVSS to V SS . 2. Current dissipation values are for VIH min = VCC –0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM ≤ V CC < 3.0 V, VIH min = VCC × 0.9, and V IL max = 0.3 V. 4. I CC depends on VCC and f as follows: I CC max = 1.0 (mA) + 1.1 (mA/(MHz × V)) × V CC × f [normal mode] I CC max = 1.0 (mA) + 0.75 (mA/(MHz × V)) × V CC × f [sleep mode] Rev.6.00 Oct.28.2004 page 732 of 1016 REJ09B0138-0600H Table 22-25 Permissible Output Currents Conditions: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 to AVCC, VSS = AVSS = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Permissible output low current (per pin) Permissible output low current (total) Ports 1, A to C Other output pins Total of 32 pins including ports 1 and A to C Total of all output pins, including the above Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins –I OH ∑ –I OH ∑ I OL Symbol I OL Min — — — Typ — — — Max 10 2.0 80 Unit mA mA mA — — 120 mA — — — — 2.0 40 mA mA Notes: 1. To protect chip reliability, do not exceed the output current values in table 22-25. 2. When driving a darlington pair or LED directly, always insert a current-limiting resistor in the output line, as show in figures 22-65 and 22-66. The chip 2 kΩ Port Darlington Pair Figure 22-65 Darlington Pair Drive Circuit (Example) The chip 600 Ω Ports 1, A to C LED Figure 22-66 LED Drive Circuit (Example) Rev.6.00 Oct.28.2004 page 733 of 1016 REJ09B0138-0600H 22.6.3 AC Characteristics Figure 22-67 show, the test conditions for the AC characteristics. 5V RL LSI output pin C = 90 pF: Ports 1, A to F C = 30 pF: Ports 2, 3, 5, 6, G RL = 2.4 kΩ RH = 12 kΩ I/O timing test levels • Low level: 0.8 V • High level: 2.0 V C RH Figure 22-67 Output Load Circuit (1) Clock Timing Table 22-26 lists the clock timing Table 22-26 Clock Timing Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 13 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Condition B Condition C Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Clock oscillator setting time at reset (crystal) Symbol Min t cyc t CH t CL t Cr t Cf t OSC1 100 35 35 — — 20 20 500 Max 500 — — 15 15 — — — Min 50 20 20 — — 10 10 500 Max 500 — — 5 5 — — — Min 76 23 23 — — 20 20 500 Test Max Unit Conditions 500 — — 15 15 — — — ns ns ns ns ns ms ms µs Figure 22-69 Figure 21-2 Figure 22-69 Figure 22-68 Clock oscillator setting time t OSC2 in software standby (crystal) External clock output stabilization delay time t DEXT Rev.6.00 Oct.28.2004 page 734 of 1016 REJ09B0138-0600H tcyc tCH ø tCL tCr tCf Figure 22-68 System Clock Timing EXTAL tDEXT VCC tDEXT STBY NMI tOSC1 RES tOSC1 ø Figure 22-69 Oscillator Settling Timing Rev.6.00 Oct.28.2004 page 735 of 1016 REJ09B0138-0600H (2) Control Signal Timing Table 22-27 lists the control signal timing. Table 22-27 Control Signal Timing Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 13 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Condition B Condition C Item RES setup time RES pulse width NMI reset setup time* NMI reset hold time* NMI setup time NMI hold time NMI pulse width (exiting software standby mode) IRQ setup time IRQ hold time IRQ pulse width (exiting software standby mode) Note: * Applies to the ZTAT version only. Symbol Min t RESS t RESW t NMIRS t NMIRH t NMIS t NMIH t NMIW t IRQS t IRQH t IRQW 200 20 250 200 250 10 200 250 10 200 Max — — — — — — — — — — Min 200 20 200 200 150 10 200 150 10 200 Max — — — — — — — — — — Min 200 20 250 200 250 10 200 250 10 200 Test Max Unit Conditions ns t cyc ns ns ns ns ns ns ns ns Figure 22-71 Figure 22-70 — — — — — — — — — — ø tRESS RES tRESW tNMIRS* NMI Note: * Applies to the ZTAT version only. tRESS tNMIRH* Figure 22-70 Reset Input Timing Rev.6.00 Oct.28.2004 page 736 of 1016 REJ09B0138-0600H ø tNMIS NMI tNMIW tNMIH IRQi (i= 0 to 2) tIRQS IRQ Edge input tIRQS IRQ Level input tIRQW tIRQH Figure 22-71 Interrupt Input Timing Rev.6.00 Oct.28.2004 page 737 of 1016 REJ09B0138-0600H (3) Bus Timing Table 22-28 lists the bus timing. Table 22-28 Bus Timing Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø= 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 13 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Item Address delay time Address setup time Address hold time Precharge time CS delay time 1 CS delay time 2 CS delay time 3 AS delay time RD delay time 1 RD delay time 2 CAS delay time Symbol Min t AD t AS t AH t PCH t CSD1 t CSD2 t CSD3 t ASD t RSD1 t RSD2 t CASD t RDH t ACC1 t ACC2 t ACC3 t ACC4 t ACC5 t WRD1 t WRD2 t WSW1 — Max 40 Condition B Min — Max 20 Condition C Min — Max 40 Test Unit Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 22-72 to Figure 22-79 0.5 × — t cyc – 30 0.5 × — t cyc – 20 1.5 × — t cyc – 40 — — — — — — — 30 0 — — — — — — — 40 40 40 40 40 40 40 — — 0.5 × — t cyc – 15 0.5 × — t cyc – 10 1.5 × — t cyc – 20 — — — — — — — 15 0 20 20 25 20 20 20 20 — — 0.5 × — t cyc – 30 0.5 × — t cyc – 20 1.5 × — t cyc – 40 — — — — — — — 30 0 40 40 40 40 40 40 40 — — Read data setup time t RDS Read data hold time Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Read data access time 5 WR delay time 1 WR delay time 2 WR pulse width 1 1.0 × — t cyc – 50 1.5 × — t cyc – 50 2.0 × — t cyc – 50 2.5 × — t cyc – 50 3.0 × — t cyc – 50 40 40 — — 1.0 × — t cyc – 25 1.5 × — t cyc – 25 2.0 × — t cyc – 25 2.5 × — t cyc – 25 3.0 × — t cyc – 25 20 20 — — 1.0 × ns t cyc – 50 1.5 × ns t cyc – 50 2.0 × ns t cyc – 50 2.5 × ns t cyc – 50 3.0 × ns t cyc – 50 40 40 ns ns ns 1.0 × — t cyc – 40 1.0 × — t cyc – 20 1.0 × — t cyc – 40 Rev.6.00 Oct.28.2004 page 738 of 1016 REJ09B0138-0600H Condition A Item WR pulse width 2 Symbol Min t WSW2 Max 1.5 × — t cyc – 40 — 60 Condition B Min Max 1.5 × — t cyc – 20 — 30 Condition C Min Max 1.5 × — t cyc – 40 — 60 Test Unit Conditions ns Figure 22-72 to Figure 22-79 Write data delay time t WDD Write data setup time t WDS Write data hold time WR setup time WR hold time CAS setup time WAIT setup time WAIT hold time BREQ setup time BACK delay time Bus-floating time BREQO delay time t WDH t WCS t WCH t CSR t WTS t WTH t BRQS t BACD t BZD t BRQOD ns ns ns ns ns ns ns ns ns ns ns ns Figure 22-81 Figure 22-80 Figure 22-76 Figure 22-74 0.5 × — t cyc – 40 0.5 × — t cyc – 20 0.5 × — t cyc – 20 0.5 × — t cyc – 20 0.5 × — t cyc – 20 60 10 60 — — — — — — 30 100 60 0.5 × — t cyc – 20 0.5 × — t cyc – 10 0.5 × — t cyc – 10 0.5 × — t cyc – 10 0.5 × — t cyc – 10 30 5 30 — — — — — — 15 50 30 0.5 × — t cyc – 33 0.5 × — t cyc – 20 0.5 × — t cyc – 20 0.5 × — t cyc – 20 0.5 × — t cyc – 20 60 10 60 — — — — — — 30 100 60 Rev.6.00 Oct.28.2004 page 739 of 1016 REJ09B0138-0600H T1 T2 ø tAD A23 to A0 tCSD1 CS7 to CS0 tAS tAH tASD AS tASD tRSD1 RD (read) tAS tACC2 tRSD2 tACC3 D15 to D0 (read) tWRD2 HWR, LWR (write) tRDS tRDH tWRD2 tAS tWDD tWSW1 tAH tWDH D15 to D0 (write) Figure 22-72 Basic Bus Timing (Two-State Access) Rev.6.00 Oct.28.2004 page 740 of 1016 REJ09B0138-0600H T1 T2 T3 ø tAD A23 to A0 tCSD1 CS7 to CS0 tAS tAH tASD AS tASD tRSD1 RD (read) tAS tACC4 tRSD2 tACC5 D15 to D0 (read) tRDS tRDH tWRD1 HWR, LWR (write) tWDD tWDS D15 to D0 (write) tWSW2 tWRD2 tAH tWDH Figure 22-73 Basic Bus Timing (Three-State Access) Rev.6.00 Oct.28.2004 page 741 of 1016 REJ09B0138-0600H T1 T2 TW T3 ø A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH WAIT tWTS tWTH Figure 22-74 Basic Bus Timing (Three-State Access with One Wait State) Rev.6.00 Oct.28.2004 page 742 of 1016 REJ09B0138-0600H Tp Tr TC1 TC2 ø tAD A23 to A0 tAS tPCH CS5 to CS2 (RAS) tCSD2 tAH tAD tACC4 tCSD3 tCASD tACC1 tCASD CAS tACC3 D15 to D0 (read) tWRD2 HWR, LWR (write) tWCS tWDD tWDS D15 to D0 (write) tWCH tWDH tWRD2 tRDS tRDH Figure 22-75 DRAM Bus Timing TRp TRr TRc1 TRc2 ø tCSD2 tCSD1 CS5 to CS2 (RAS) tCSR tCASD CAS tCASD Figure 22-76 CAS-Before-RAS Refresh Timing Rev.6.00 Oct.28.2004 page 743 of 1016 REJ09B0138-0600H TRp TRr TRc TRc ø tCSD2 tCSD2 CS5 to CS2 (RAS) tCASD CAS tCASD Figure 22-77 Self-Refresh Timing T1 T2 or T3 T1 T2 ø tAD A23 to A0 tAS tAH CS0 tASD tASD AS tRSD2 RD (read) tACC3 D15 to D0 (read) tRDS tRDH Figure 22-78 Burst ROM Access Timing (Two-State Access) Rev.6.00 Oct.28.2004 page 744 of 1016 REJ09B0138-0600H T1 ø T2 or T3 T1 tAD A23 to A0 CS0 AS tRSD2 RD (read) tACC1 D15 to D0 (read) tRDS tRDH Figure 22-79 Burst ROM Access Timing (One-State Access) ø tBRQS tBRQS BREQ tBACD BACK tBZD A23 to A0, CS7 to CS0, AS, RD, HWR, LWR, CAS tBACD tBZD Figure 22-80 External Bus Release Timing Rev.6.00 Oct.28.2004 page 745 of 1016 REJ09B0138-0600H ø tBRQOD tBRQOD BREQO Figure 22-81 External Bus Request Output Timing (4) DMAC Timing Table 22-29 lists the DMAC timing. Table 22-29 DMAC Timing Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0V, ø = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 13 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Condition B Condition C Item DREQ setup time DREQ hold time TEND delay time DACK delay time 1 DACK delay time 2 Symbol Min t DRQS t DRQH t TED t DACD1 t DACD2 40 10 — — — Max — — 40 40 40 Min 30 10 — — — Max — — 20 20 20 Min 40 10 — — — Max — — 40 40 40 ns Figure 22-84 Figure 22-82, Figure 22-83 Test Unit Conditions ns Figure 22-85 Rev.6.00 Oct.28.2004 page 746 of 1016 REJ09B0138-0600H T1 T2 ø A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 DACK0 , DACK1 tDACD2 Figure 22-82 DMAC Single Address Transfer Timing (Two-State Access) Rev.6.00 Oct.28.2004 page 747 of 1016 REJ09B0138-0600H T1 ø T2 T3 A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 DACK0, DACK1 tDACD2 Figure 22-83 DMAC Single Address Transfer Timing (Three-State Access) T1 T2 or T3 ø tTED TEND0, TEND1 tTED Figure 22-84 DMAC TEND Output Timing ø tDRQS DREQ0, DREQ1 tDRQH Figure 22-85 DMAC DREQ Intput Timing Rev.6.00 Oct.28.2004 page 748 of 1016 REJ09B0138-0600H (5) Timing of On-Chip Supporting Modules Table 22-30 lists the timing of on-chip supporting modules. Table 22-30 Timing of On-Chip Supporting Modules Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 10 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 13 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Condition B Condition C Item PORT Output data delay time Input data setup time Input data hold time TPU Symbol Min t PWD t PRS t PRH — 50 50 — — 50 50 1.5 2.5 — 50 50 1.5 2.5 — 4 6 t SCKW t SCKr t SCKf 0.4 — — Max 100 — — 100 100 — — — — 100 — — — — 100 — — 0.6 1.5 1.5 Min — 30 30 — — 30 30 1.5 2.5 — 30 30 1.5 2.5 — 4 6 0.4 — — Max 50 — — 50 50 — — — — 50 — — — — 50 — — 0.6 1.5 1.5 Min — 50 50 — — 50 50 1.5 2.5 — 50 50 1.5 2.5 — 4 6 0.4 — — 75 — — 75 75 — — — — 75 — — — — 75 — — 0.6 1.5 1.5 t Scyc t cyc ns t cyc Figure 22-93 Figure 22-94 ns ns ns t cyc Figure 22-90 Figure 22-92 Figure 22-91 ns t cyc Figure 22-89 ns ns Figure 22-87 Figure 22-88 Test Max Unit Conditions ns Figure 22-86 PPG Pulse output delay time t POD Timer output delay time t TOCD Timer input setup time t TICS Timer clock input setup t TCKS time Timer clock pulse width Single edge Both edges t TCKWH t TCKWL TMR Timer output delay time t TMOD Timer reset input setup t TMRS time Timer clock input setup t TMCS time Timer clock pulse width Single edge Both edges WDT Overflow output delay time SCI Input clock cycle t TMCWH t TMCWL t WOVD Asynchro- t Scyc nous Synchronous Input clock pulse width Input clock rise time Input clock fall time Rev.6.00 Oct.28.2004 page 749 of 1016 REJ09B0138-0600H Condition A Condition B Condition C Item SCI Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) A/D Trigger input setup con- time verter Symbol Min t TXD t RXS t RXH t TRGS — 100 100 50 Max 100 — — — Min — 50 50 30 Max 50 — — — Min — 75 75 50 75 — — — Test Max Unit Conditions ns ns ns ns Figure 22-96 Figure 22-95 T1 ø T2 tPRS Ports 1 to 6, A to G (read) tPRH tPWD Ports 1 to 3, 5, 6, A to G (write) Figure 22-86 I/O Port Input/Output Timing ø tPOD PO15 to PO0 Figure 22-87 PPG Output Timing Rev.6.00 Oct.28.2004 page 750 of 1016 REJ09B0138-0600H ø tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 22-88 TPU Input/Output Timing ø tTCKS TCLKA to TCLKD tTCKWL tTCKWH tTCKS Figure 22-89 TPU Clock Input Timing ø tTMOD TMO0, TMO1 Figure 22-90 8-Bit Timer Output Timing ø tTMCS TMCI0, TMCI1 tTMCWL tTMCWH tTMCS Figure 22-91 8-Bit Timer Clock Input Timing Rev.6.00 Oct.28.2004 page 751 of 1016 REJ09B0138-0600H ø tTMRS TMRI0, TMRI1 Figure 22-92 8-Bit Timer Reset Input Timing ø tWOVD WDTOVF tWOVD Figure 22-93 WDT Output Timing tSCKW SCK0 to SCK2 tSCKr tSCKf tScyc Figure 22-94 SCK Clock Input Timing SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS RxD0 to RxD2 (receive data) tRXH Figure 22-95 SCI Input/Output Timing (Clock Synchronous Mode) ø tTRGS ADTRG Figure 22-96 A/D Converter External Trigger Input Timing Rev.6.00 Oct.28.2004 page 752 of 1016 REJ09B0138-0600H 22.6.4 A/D Conversion Characteristics Table 22-31 lists the A/D conversion characteristics. Table 22-31 A/D Conversion Characteristics Condition A: VCC = AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 10 MHz, T a = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 20 MHz, T a = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 13 MHz, T a = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization Absolute accuracy Notes: 1. 2. 3. 4. 5. 4.0 V ≤ AV CC ≤ 5.5 V 2.7 V ≤ AV CC < 4.0 V ø ≤ 12 MHz ø > 12 MHz 3.0 V ≤ AV CC < 4.0 V Min 10 13.4 — — — — — — — — Typ 10 — — — — — — — — — Max 10 — 20 10* 5* 2 ±7.5 ±7.5 ±7.5 ±0.5 ±8.0 1 Condition B Min 10 6.7 — — — — — — — — Typ 10 — — — — — — — — — Max 10 — 20 10* 5* 4 3 Condition C Min 10 10.4 — — — — — — — — Typ 10 — — — — — — — — — Max 10 — 20 10* 5* 5 1 Unit bits µs pF kΩ ±3.5 ±3.5 ±3.5 ±0.5 ±4.0 ±7.5 ±7.5 ±7.5 ±0.5 ±8.0 LSB LSB LSB LSB LSB Rev.6.00 Oct.28.2004 page 753 of 1016 REJ09B0138-0600H 22.6.5 D/A Convervion Characteristics Table 22-32 lists the D/A conversion characteristics Table 22-32 D/A Conversion Characteristics Condition A: VCC = AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 10 MHz, T a = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 20 MHz, T a = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 13 MHz, T a = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition A Item Resolution Conversion time Condition B Condition C Min Typ Max Min Typ Max Min Typ Max Unit Test Conditions 8 — 8 — 8 10 8 — 8 — 8 10 8 — 8 — 8 10 bit µs 20-pF capacitive load Absolute accuracy — — ±2.0 ±3.0 — — ±2.0 — ±1.0 ±1.5 — — ±1.0 — ±2.0 ±3.0 LSB 2-MΩ resistive load — ±2.0 LSB 4-MΩ resistive load Rev.6.00 Oct.28.2004 page 754 of 1016 REJ09B0138-0600H 22.7 22.7.1 Electrical Characteristics of H8S/2357 F-ZTAT Version Absolute Maximum Ratings Table 22-33 lists the absolute maximum ratings. Table 22-33 Absolute Maximum Ratings Item Power supply voltage Input voltage (FWE)* 1 1 Symbol VCC Vin Vin Vin Vref AVCC VAN Topr 1 Value –0.3 to +7.0 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to AVCC +0.3 –0.3 to AVCC +0.3 –0.3 to +7.0 –0.3 to AVCC +0.3 Regular specifications: –20 to +75* 2 2 Unit V V V V V V V °C °C °C Input voltage (except port 4)* Input voltage (port 4)* Reference voltage Analog power supply voltage Analog input voltage Operating temperature Wide-range specifications: –40 to +85* Storage temperature Tstg –55 to +125 Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded. Notes: 1. 12 V must not be applied to any pin, as this will cause permanent damage to the chip. 2. The operating temperature ranges for flash memory programming/erasing are as follows: T a = 0 to +75°C (regular specifications), Ta = 0 to +85°C (wide-range specifications). 22.7.2 DC Characteristics Table 22-34 lists the DC characteristics. Table 22-35 lists the permissible output currents. Table 22-34 DC Characteristics (1) Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20 to +75°C (regular specifications), T a = –40 to +85°C (wide-range specifications) Item Schmitt trigger input voltage Input high voltage Port 2, P64 to P6 7, PA4 to PA 7 RES , STBY , NMI, MD2 to MD0, FWE EXTAL Ports 1, 3, 5, B to G, P60 to P6 3, PA0 to PA 3 Port 4 Input low voltage RES , STBY , MD2 to MD0, FWE VIL Symbol VT– VT+ VT – VT VIH + – Min 1.0 — 0.4 VCC – 0.7 Typ — — — — Max — Unit V Test Conditions VCC × 0.7 V — VCC + 0.3 V V VCC × 0.7 — 2.0 — VCC + 0.3 VCC + 0.3 V V 2.0 –0.3 — — AVCC + 0.3 V 0.5 V Rev.6.00 Oct.28.2004 page 755 of 1016 REJ09B0138-0600H Item Input low voltage Symbol NMI, EXTAL, VIL Ports 1, 3 to 5, B to G, P60 to P6 3, PA0 to PA 3 All output pins VOH All output pins VOL Ports 1, A to C RES STBY , NMI, MD2 to MD0, FWE Port 4 | I in | Min –0.3 Typ — Max 0.8 Unit V Test Conditions Output high voltage Output low voltage Input leakage current VCC – 0.5 3.5 — — — — — — — — — — — — 0.4 1.0 10.0 1.0 V V V V µA µA I OH = –200 µA I OH = –1 mA I OL = 1.6 mA I OL = 10 mA Vin = 0.5 V to VCC – 0.5 V — I TSI — — — 1.0 1.0 µA µA Vin = 0.5 V to AVCC – 0.5 V Vin = 0.5 V to VCC – 0.5 V Three-state leakage current (off state) Ports 1 to 3, 5, 6, A to G MOS input Ports A to E pull-up current Input capacitance RES NMI All input pins except RES and NMI Current dissipation * 2 Normal operation Sleep mode Standby mode * 3 Flash memory programming/ erasing Analog power supply current During A/D and D/A conversion Idle Reference current During A/D and D/A conversion Idle –I P Cin 50 — — — — — — — 300 80 50 15 µA pF pF pF Vin = 0 V Vin = 0 V f = 1 MHz T a = 25°C I CC * 4 — — — — — 78 122 (5.0 V) 53 84 (5.0 V) 0.01 — 5.0 20.0 mA mA µA mA f = 20 MHz f = 20 MHz Ta ≤ 50°C 50°C < Ta 0°C ≤ Ta ≤ 75°C f = 20 MHz 88 122 (5.0 V) 0.8 2.0 (5.0 V) 0.01 5.0 Al CC — mA — Al CC — µA mA 2.3 3.0 (5.0 V) 0.01 5.0 — µA RAM standby voltage VRAM 2.0 — — V Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, AVSS, and V ref pins open. Connect AVCC and Vref to V CC, and connect AVSS to V SS . 2. Current dissipation values are for V IH min = VCC –0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM ≤ V CC < 4.5 V, VIH min = VCC × 0.9, and V IL max = 0.3 V. 4. I CC depends on VCC and f as follows: I CC max = 1.0 (mA) + 1.1 (mA/(MHz × V)) × V CC × f [normal mode] I CC max = 1.0 (mA) + 0.75 (mA/(MHz × V)) × V CC × f [sleep mode] Rev.6.00 Oct.28.2004 page 756 of 1016 REJ09B0138-0600H Table 22-34 DC Characteristics (2) Conditions: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Schmitt trigger input voltage Input high voltage Port 2, P64 to P6 7, PA4 to PA 7 RES , STBY , NMI, MD2 to MD0, FWE EXTAL Ports 1, 3, 5, B to G, P60 to P6 3, PA0 to PA 3 Port 4 Input low voltage RES , STBY , MD2 to MD0, FWE NMI, EXTAL, Ports 1, 3 to 5, B to G, P60 to P6 3, PA0 to PA 3 Output high voltage Output low voltage All output pins VOH All output pins VOL Ports 1, A to C VIL Symbol VT– VT+ VT+ – VT– VIH Min — Typ — Max — Unit V Test Conditions VCC × 0.2 — VCC × 0.07 — VCC × 0.9 — VCC × 0.7 V — VCC +0.3 V V VCC × 0.7 — VCC × 0.7 — VCC +0.3 VCC +0.3 V V VCC × 0.7 — –0.3 — AVCC +0.3 V VCC × 0.1 V –0.3 — VCC × 0.2 V VCC < 4.0 V 0.8 VCC – 0.5 VCC – 1.0 — — — — — — — — 0.4 1.0 V V V V VCC = 4.0 to 5.5 V I OH = –200 µA I OH = –1 mA I OL = 1.6 mA VCC ≤ 4 V I OL = 5 mA 4.0 < VCC ≤ 5.5 V I OL = 10 mA Vin = 0.5 V to VCC – 0.5 V Input leakage current RES STBY , NMI, MD2 to MD0, FWE Port 4 Ports 1 to 3, 5, 6, A to G | I in | — — — — 10.0 1.0 µA µA — I TSI — — — 1.0 1.0 µA µA Vin = 0.5 V to AVCC – 0.5 V Vin = 0.5 V to VCC –0.5 V Three-state leakage current (off state) MOS input Ports A to E pull-up current Input capacitance RES NMI All input pins except RES and NMI –I P Cin 10 — — — — — — — 300 80 50 15 µA pF pF pF VCC = 3.0 to 5.5 V, Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25°C Rev.6.00 Oct.28.2004 page 757 of 1016 REJ09B0138-0600H Item Current dissipation * 2 Normal operation Sleep mode Standby mode * 3 Flash memory programming/ erasing Analog power supply current During A/D and D/A conversion Idle Reference current During A/D and D/A conversion Idle Notes: 1. 2. 3. 4. Symbol I CC * 4 Min — — — — — Typ Max Unit mA mA µA mA Test Conditions f = 13 MHz f = 13 MHz Ta ≤ 50°C 50°C < Ta 0°C ≤ Ta ≤ 75°C f = 13 MHz 32 80 (3.3 V) 22 55 (3.3 V) 0.01 — 5.0 20 42 80 (3.3 V) 0.3 2.0 (3.3 V) 0.01 5.0 Al CC — mA — Al CC — µA mA 1.6 3.0 (3.3 V) 0.01 5.0 — µA RAM standby voltage VRAM 2.0 — — V If the A/D and D/A converters are not used, do not leave the AVCC, AVSS, and V ref pins open. Connect AVCC and Vref to V CC, and connect AVSS to V SS . Current dissipation values are for V IH min = VCC –0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. The values are for VRAM ≤ V CC < 3.0 V, VIH min = VCC × 0.9, and V IL max = 0.3 V. I CC depends on VCC and f as follows: I CC max = 1.0 (mA) + 1.1 (mA/(MHz × V)) × V CC × f [normal mode] I CC max = 1.0 (mA) + 0.75 (mA/(MHz × V)) × V CC × f [sleep mode] Table 22-35 Permissible Output Currents Conditions: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Permissible output low current (per pin) Permissible output low current (total) Ports 1, A to C Other output pins Total of 32 pins including ports 1 and A to C Total of all output pins, including the above Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins –I OH ∑ –I OH ∑ I OL Symbol I OL Min — — — Typ — — — Max 10 2.0 80 Unit mA mA mA — — 120 mA — — — — 2.0 40 mA mA Notes: 1. To protect chip reliability, do not exceed the output current values in table 22-35. 2. When driving a darlington pair or LED directly, always insert a current-limiting resistor in the output line, as show in figures 22-65 and 22-66. Rev.6.00 Oct.28.2004 page 758 of 1016 REJ09B0138-0600H 22.7.3 AC Characteristics (1) Clock Timing Table 22-36 lists the clock timing Table 22-36 Clock Timing Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 13 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Clock oscillator setting time at reset (crystal) Clock oscillator setting time in software standby (crystal) External clock output stabilization delay time Symbol t cyc t CH t CL t Cr t Cf t OSC1 t OSC2 t DEXT Min 50 20 20 — — 10 10 500 Max 500 — — 5 5 — — — Condition C Min 76 23 23 — — 20 20 500 Max 500 — — 15 15 — — — Unit ns ns ns ns ns ms ms µs Figure 22-69 Figure 21-2 Figure 22-69 Test Conditions Figure 22-68 Rev.6.00 Oct.28.2004 page 759 of 1016 REJ09B0138-0600H (2) Control Signal Timing Table 22-37 lists the control signal timing. Table 22-37 Control Signal Timing Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 13 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (exiting software standby mode) IRQ setup time IRQ hold time IRQ pulse width (exiting software standby mode) Symbol t RESS t RESW t NMIS t NMIH t NMIW t IRQS t IRQH t IRQW Min 200 20 150 10 200 150 10 200 Max — — — — — — — — Condition C Min 200 20 250 10 200 250 10 200 Max — — — — — — — — ns ns ns ns Unit ns t cyc ns Figure 22-71 Test Conditions Figure 22-70 Rev.6.00 Oct.28.2004 page 760 of 1016 REJ09B0138-0600H (3) Bus Timing Table 22-38 lists the bus timing. Table 22-38 Bus Timing Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø= 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 3.0 to 5.5 V, AVCC = 3.0 to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 13 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B Item Address delay time Address setup time Address hold time Precharge time CS delay time 1 CS delay time 2 CS delay time 3 AS delay time RD delay time 1 RD delay time 2 CAS delay time Read data setup time Read data hold time Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Read data access time 5 WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Symbol t AD t AS t AH t PCH t CSD1 t CSD2 t CSD3 t ASD t RSD1 t RSD2 t CASD t RDS t RDH t ACC1 t ACC2 t ACC3 t ACC4 t ACC5 t WRD1 t WRD2 t WSW1 t WSW2 Min — Max 20 Condition C Min — Max 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 22-72 to Figure 22-79 0.5 × — t cyc – 15 0.5 × — t cyc – 10 1.5 × — t cyc – 20 — — — — — — — 15 0 — — — — — — — 20 20 25 20 20 20 20 — — 0.5 × — t cyc – 30 0.5 × — t cyc – 20 1.5 × — t cyc – 40 — — — — — — — 30 0 40 40 40 40 40 40 40 — — 1.0 × — t cyc – 25 1.5 × — t cyc – 25 2.0 × — t cyc – 25 2.5 × — t cyc – 25 3.0 × — t cyc – 25 20 20 — — 1.0 × ns t cyc – 50 1.5 × ns t cyc – 50 2.0 × ns t cyc – 50 2.5 × ns t cyc – 50 3.0 × ns t cyc – 50 40 40 ns ns ns ns 1.0 × — t cyc – 20 1.5 × — t cyc – 20 1.0 × — t cyc – 40 1.5 × — t cyc – 40 Rev.6.00 Oct.28.2004 page 761 of 1016 REJ09B0138-0600H Condition B Item Write data delay time Write data setup time Write data hold time WR setup time WR hold time CAS setup time WAIT setup time WAIT hold time BREQ setup time BACK delay time Bus-floating time BREQO delay time Symbol t WDD t WDS t WDH t WCS t WCH t CSR t WTS t WTH t BRQS t BACD t BZD t BRQOD Min — Max 30 Condition C Min — Max 60 Unit ns ns ns ns ns ns ns ns ns ns ns ns Figure 22-81 Figure 22-80 Figure 22-76 Figure 22-74 Test Conditions Figure 22-72 to Figure 22-79 0.5 × — t cyc – 20 0.5 × — t cyc – 10 0.5 × — t cyc – 10 0.5 × — t cyc – 10 0.5 × — t cyc – 10 30 5 30 — — — — — — 15 50 30 0.5 × — t cyc – 36 0.5 × — t cyc – 20 0.5 × — t cyc – 20 0.5 × — t cyc – 20 0.5 × — t cyc – 20 60 10 60 — — — — — — 30 100 60 (4) DMAC Timing Table 22-39 lists the DMAC timing. Table 22-39 DMAC Timing Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0V, ø = 2 to 13 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B Item DREQ setup time DREQ hold time TEND delay time DACK delay time 1 DACK delay time 2 Symbol t DRQS t DRQH t TED t DACD1 t DACD2 Min 30 10 — — — Max — — 20 20 20 Condition C Min 40 10 — — — Max — — 40 40 40 ns Figure 22-84 Figure 22-82 Figure 22-83 Unit ns Test Conditions Figure 22-85 Rev.6.00 Oct.28.2004 page 762 of 1016 REJ09B0138-0600H (5) Timing of On-Chip Supporting Modules Table 22-40 lists the timing of on-chip supporting modules. Table 22-40 Timing of On-Chip Supporting Modules Condition B: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 20 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 13 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B Item PORT Output data delay time Input data setup time Input data hold time PPG TPU Symbol Min t PWD t PRS t PRH — 30 30 — — 30 30 1.5 2.5 — 30 30 1.5 2.5 4 6 t SCKW t SCKr t SCKf 0.4 — — Max 50 — — 50 50 — — — — 50 — — — — — — 0.6 1.5 1.5 Condition C Min — 50 50 — — 50 50 1.5 2.5 — 50 50 1.5 2.5 4 6 0.4 — — Max 75 — — 75 75 — — — — 75 — — — — — — 0.6 1.5 1.5 t Scyc t cyc t cyc Figure 22-94 ns ns ns t cyc Figure 22-90 Figure 22-92 Figure 22-91 ns t cyc Figure 22-89 ns ns Figure 22-87 Figure 22-88 Unit ns Test Conditions Figure 22-86 Pulse output delay time t POD Timer output delay time t TOCD Timer input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges t TICS t TCKS t TCKWH t TCKWL TMR Timer output delay time t TMOD Timer reset input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges t TMRS t TMCS t TMCWH t TMCWL SCI Input clock cycle Asynchro- t Scyc nous Synchronous Input clock pulse width Input clock rise time Input clock fall time Rev.6.00 Oct.28.2004 page 763 of 1016 REJ09B0138-0600H Condition B Item SCI Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) A/D Trigger input setup converter time Symbol Min t TXD t RXS t RXH t TRGS — 50 50 30 Max 50 — — — Condition C Min — 75 75 50 Max 75 — — — Unit ns ns ns ns Test Conditions Figure 22-95 Figure 22-96 22.7.4 A/D Conversion Characteristics Table 22-41 lists the A/D conversion characteristics. Table 22-41 A/D Conversion Characteristics Condition B: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 20 MHz, T a = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = AVCC = 3.0 V to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 13 MHz, Ta = –20 to +75°C (regular specifications), T a = –40 to +85°C (wide-range specifications) Condition B Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization Absolute accuracy Notes: 1. 2. 3. 4. 4.0 V ≤ AV CC ≤ 5.5 V 3.0 V ≤ AV CC < 4.0 V ø ≤ 12 MHz ø > 12 MHz Min 10 6.7 — — — — — — — — Typ 10 — — — — — — — — — Max 10 — 20 10* 5* 4 3 Condition C Min 10 10.4 — — — — — — — — Typ 10 — — — — — — — — — Max 10 — 20 10* 5* 2 1 Unit bits µs pF kΩ ±3.5 ±3.5 ±3.5 ±0.5 ±4.0 ±7.5 ±7.5 ±7.5 ±0.5 ±8.0 LSB LSB LSB LSB LSB Rev.6.00 Oct.28.2004 page 764 of 1016 REJ09B0138-0600H 22.7.5 D/A Conversion Characteristics Table 22-42 lists the D/A conversion characteristics Table 22-42 D/A Conversion Characteristics Condition B: VCC = AVCC = 5.0 V ± 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 20 MHz, T a = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition C: VCC = AVCC = 3.0 V to 5.5 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, ø = 2 to 13 MHz, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Condition B Item Resolution Conversion time Absolute accuracy Min 8 — — — Typ 8 — ±1.0 — Max 8 10 ±1.5 ±1.0 Min 8 — — — Condition C Typ 8 — ±2.0 — Max 8 10 ±3.0 ±2.0 Unit bit µs LSB LSB 20-pF capacitive load 2-MΩ resistive load 4-MΩ resistive load Test Conditions 22.7.6 Flash Memory Characteristics Table 22-43 shows the flash memory characteristics. Table 22-43 Flash Memory Characteristics (1) Conditions: VCC = 5.0 V ± 10%, AV CC = 5.0 V ± 10%, Vref = 4.5 V to AV CC, VSS = AVSS = 0V Ta = 0 to +75°C (Programming/erasing operating temperature, regular specifications), Ta = 0 to + 85°C (Programming/erasing operating temperature, wide-range specifications) Item Programming time*1* 2* 4 Erase time* * * 1 3 5 Symbol Min tP tE NWEC x y z — — — 10 50 150 10 10 4 2 Typ 10 100 — — — — — — — — Max 200 1200 100 — — 200 — — — — Unit ms/32 bytes ms/block Times µs µs µs µs µs µs µs Test Condition Reprogramming count Programming Wait time after SWE bit setting * 1 Wait time after PSU bit setting * 1 Wait time after P bit setting * 1* 4 Wait time after P bit clear*1 α Wait time after PSU bit clear*1 Wait time after PV bit setting * 1 β γ Wait time after H'FF dummy ε write* 1 Rev.6.00 Oct.28.2004 page 765 of 1016 REJ09B0138-0600H Item Symbol Min 4 — 10 200 5 10 10 20 2 5 120 Typ — — — — — — — — — — — Max — 5 Unit µs Test Condition z = 200 µs Programming Wait time after PV bit clear * 1η Maximum programming count* 1* 4 Erase Wait time after SWE bit setting * 1 Wait time after ESU bit setting * 1 Wait time after E bit setting * 1* 6 N x y z 1000* Times — — 10 — — — — — 240 µs µs ms µs µs µs µs µs Times Wait time after E bit clear*1 α Wait time after ESU bit clear*1 Wait time after EV bit setting * 1 β γ Wait time after H’FF dummy ε write* 1 Wait time after EV bit clear * 1η Maximum erase count * * 1 6 N Notes: 1. Set the times according to the program/erase algorithms. 2. Programming time per 32 bytes (Shows the total time the flash memory control register 1 (FLMCR1) is set. It does not include the programming verification time.) 3. Block erase time (Shows the period the E bit in FLMCR1 is set. It does not include the erase verification time.) 4. Maximum programming time (tp (max)=wait time after P-bit setting (z) × maximum programming count (N)) 5. Number of times when the wait time after P bit setting (z) = 200 µs. The maximum number of writes (N) should be set according to the actual set value of z so as not to exceed the maximum programming time (tP(max)). 6. For the maximum erase time (tE(max)), the following relationship applies between the wait time after E bit setting (z) and the maximum number of erases (N): t E(max) = Wait time after E bit setting (z) × maximum number of erases (N) The values of z and N should be set so as to satisfy the above formula. Examples: When z = 5 [ms], N = 240 times When z = 10 [ms], N = 120 times Table 22-43 shows the flash memory characteristics. Table 22-43 Flash Memory Characteristics (2) Conditions: VCC = 3.0 to 3.6 V, AVCC = 3.0 to 3.6 V, Vref = 3.0 V to AV CC, VSS=AVSS=0V Ta=0 to +75°C (Programming/erasing operating temperature, regular specifications), Ta =0 to +85°C (Programming/erasing operating temperature, wide-range specifications) Item Programming time*1* 2* 4 Erase time* * * 1 3 5 Symbol Min tP tE NWEC — — — Typ 10 100 — Max 200 Unit ms/32 bytes Test Condition 1200 ms/block 100 Times Reprogramming count Rev.6.00 Oct.28.2004 page 766 of 1016 REJ09B0138-0600H Item Programming Wait time after SWE bit setting * 1 Wait time after PSU bit setting * 1 Wait time after P bit setting * 1* 4 Wait time after P bit clear*1 Wait time after PSU bit clear*1 Wait time after PV bit setting * 1 Symbol Min x y z α β γ 10 50 150 10 10 4 2 4 — 10 200 5 10 10 20 2 5 120 Typ — — — — — — — — — — — — — — — — — — Max — — 200 — — — — — Unit µs µs µs µs µs µs µs µs Test Condition Wait time after H'FF dummy ε write* 1 Wait time after PV bit clear * 1 η Maximum programming count* 1* 4 Erase Wait time after SWE bit setting * 1 Wait time after ESU bit setting * 1 Wait time after E bit setting * 1* 6 N x y z 1000 Times *5 — — 10 — — — — — 240 µs µs ms µs µs µs µs µs Times Z = 200 µs Wait time after E bit clear*1 α Wait time after ESU bit clear*1 Wait time after EV bit setting * 1 β γ Wait time after H'FF dummy ε write* 1 Wait time after EV bit clear * 1η Maximum erase count * * 1 6 N Notes: 1. Set the times according to the program/erase algorithms. 2. Programming time per 32 bytes (Shows the total time the flash memory control register (FLMCR) is set. It does not include the programming verification time.) 3. Block erase time (Shows the period the E bit in FLMCR is set. It does not include the erase verification time.) 4. Maximum programming time (tp (max)=wait time after P-bit setting (Z) × maximum programming count (N)) 5. Number of times when the wait time after P bit setting (z) = 200 µs. The maximum number of writes (N) should be set according to the actual set value of z so as not to exceed the maximum programming time (tP(max)). 6. For the maximum erase time (tE(max)), the following relationship applies between the wait time after E bit setting (z) and the maximum number of erases (N): t E(max) = Wait time after E bit setting (z) × maximum number of erases (N) The values of z and N should be set so as to satisfy the above formula. Examples: When z = 5 [ms], N = 240 times When z = 10 [ms], N = 120 times Rev.6.00 Oct.28.2004 page 767 of 1016 REJ09B0138-0600H 22.8 Usage Note Although the ZTAT, F-ZTAT, and masked ROM versions fully meet the electrical specifications listed in this manual, due to differences in the fabrication process, the on-chip ROM, and the layout patterns, there will be differences in the actual values of the electrical characteristics, the operating margins, the noise margins, and other aspects. Therefore, if a system is evaluated using the ZTAT and F-ZTAT versions, a similar evaluation should also be performed using the masked ROM version. Rev.6.00 Oct.28.2004 page 768 of 1016 REJ09B0138-0600H Appendix A Instruction Set A.1 Instruction List Operand Notation Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + – × ÷ ∧ ∨ ⊕ → ¬ ( ) :8/:16/:24/:32 General register (destination) * 1 General register (source)* 1 General register * 1 General register (32-bit register) Multiply-and-accumulate register (32-bit register)*2 Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Add Subtract Multiply Divide Logical AND Logical OR Logical exclusive OR Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Logical NOT (logical complement) Contents of operand 8-, 16-, 24-, or 32-bit length Notes: 1. General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). 2. The MAC register cannot be used in the H8S/2357 Group. Condition Code Notation Symbol Changes according to the result of instruction * 0 1 — Undetermined (no guaranteed value) Always cleared to 0 Always set to 1 Not affected by execution of the instruction Rev.6.00 Oct.28.2004 page 769 of 1016 REJ09B0138-0600H Table A-1 Instruction Set (1) Data Transfer Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code Operation #xx:8→Rd8 —— —— —— —— —— —— —— —— —— —— —— —— ERd32-1→ERd32,Rs8→@ERd —— Rs8→@aa:8 Rs8→@aa:16 Rs8→@aa:32 —— —— —— IHNZVC 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— No. of States*1 Advanced 1 1 2 3 5 3 2 3 4 2 3 5 3 2 3 4 Mnemonic MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd W 2 W 2 W4 B 6 B 4 B 2 B 2 B 8 B 4 B 2 Rs8→@ERd Rs8→@(d:16,ERd) Rs8→@(d:32,ERd) B 6 @aa:32→Rd8 B 4 @aa:16→Rd8 B 2 @aa:8→Rd8 B 2 B 8 @(d:32,ERs)→Rd8 @ERs→Rd8,ERs32+1→ERs32 B 4 @(d:16,ERs)→Rd8 B 2 @ERs→Rd8 B 2 Rs8→Rd8 B2 ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ —— Rs16→Rd16 @ERs→Rd16 —— —— ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ Rev.6.00 Oct.28.2004 page 770 of 1016 REJ09B0138-0600H Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — #xx:16→Rd16 0— 0— 0— 2 1 2 MOV Addressing Mode/ Instruction Length (Bytes) Condition Code Operation @(d:16,ERs)→Rd16 —— —— @(d:32,ERs)→Rd16 0— 0— 0— 0— 0— —— —— —— 0— 0— 0— 0— —— —— —— —— —— @(d:16,ERs)→ERd32 @(d:32,ERs)→ERd32 —— —— @ERs→ERd32,ERs32+4→@ERs32 —— 0— 0— 0— 0— 0— 0— 0— 0— IHNZVC No. of States*1 Advanced 3 5 3 3 4 2 3 5 3 3 4 3 1 4 5 7 5 Mnemonic MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd L L L 4 6 8 L 10 L 6 L 4 L 2 L6 W 6 W 4 Rs16→@aa:16 Rs16→@aa:32 #xx:32→ERd32 ERs32→ERd32 @ERs→ERd32 W 2 W 8 Rs16→@(d:32,ERd) W 4 Rs16→@(d:16,ERd) W 2 Rs16→@ERd W 6 @aa:32→Rd16 W 4 @aa:16→Rd16 —— —— W 2 @ERs→Rd16,ERs32+2→ERs32 — — W 8 W 4 MOV Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — ERd32-2→ERd32,Rs16→@ERd — — ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ —— @aa:32→ERd32 —— ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ @aa:16→ERd32 0— 0— 5 6 Rev.6.00 Oct.28.2004 page 771 of 1016 REJ09B0138-0600H Addressing Mode/ Instruction Length (Bytes) Condition Code Operation ERs32→@ERd —— —— —— 0— 0— 0— 0— 0— —— —— —— —— —— 0— 0— 0— 0— 0— —————— IHNZVC No. of States*1 Advanced 4 5 7 5 5 6 3 5 3 5 7/9/11 [1] Mnemonic MOV MOV.L ERs,@(d:16,ERd) L MOV.L ERs,@(d:32,ERd) L MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 POP POP.L ERn PUSH PUSH.L ERn LDM LDM @SP+,(ERm-ERn) L 4 L 4 PUSH.W Rn W 2 L 4 @SP→ERn32,SP+4→SP SP-2→SP,Rn16→@SP SP-4→SP,ERn32→@SP (@SP→ERn32,SP+4→SP) Repeated for each register restored STM STM (ERm-ERn),@-SP L 4 (SP-4→SP,ERn32→@SP) Repeated for each register saved MOVFPE MOVTPE MOVTPE Rs,@aa:16 MOVFPE @aa:16,Rd Cannot be used in the H8S/2357 Group Cannot be used in the H8S/2357 Group —————— POP.W Rn W 2 @SP→Rn16,SP+2→SP L 8 ERs32→@aa:32 L 6 ERs32→@aa:16 L 4 ERd32-4→ERd32,ERs32→@ERd — — —— 10 ERs32→@(d:32,ERd) 6 ERs32→@(d:16,ERd) ↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔ MOV.L ERs,@ERd L 4 Rev.6.00 Oct.28.2004 page 772 of 1016 REJ09B0138-0600H Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — 7/9/11 [1] [2] [2] (2) Arithmetic Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code Operation Rd8+#xx:8→Rd8 — — IHNZVC ↔ ↔ ↔ ↔ No. of States*1 Advanced 1 1 Mnemonic ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDX #xx:8,Rd ADDX Rs,Rd ADDS #1,ERd ADDS #2,ERd ADDS #4,ERd INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd DAA Rd SUB.B Rs,Rd SUB.W #xx:16,Rd W4 B 2 B 2 L 2 L 2 W 2 W 2 B 2 L 2 L 2 L 2 B 2 B2 Rd8+Rs8+C→Rd8 ERd32+1→ERd32 ERd32+2→ERd32 ERd32+4→ERd32 Rd8+1→Rd8 Rd16+1→Rd16 Rd16+2→Rd16 ERd32+1→ERd32 ERd32+2→ERd32 Rd8 decimal adjust→Rd8 Rd8-Rs8→Rd8 Rd16-#xx:16→Rd16 L 2 Rd8+#xx:8+C→Rd8 L6 ERd32+#xx:32→ERd32 ERd32+ERs32→ERd32 W 2 Rd16+Rs16→Rd16 W4 Rd16+#xx:16→Rd16 B 2 Rd8+Rs8→Rd8 B2 ADD Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — — [3] 2 — [3] 1 — [4] 3 — [4] — — 1 [5] 1 [5] 1 —— — —— — —— — —— — —— — —— — —— — —— — —— — —— — —— — —* — * 1 1 1 1 1 1 1 1 1 1 — [3] ↔ ↔ ↔ ↔ 2 ↔↔ ↔ ↔↔↔↔↔↔↔ ↔↔↔↔↔ ↔↔↔↔↔↔↔ ADDS INC Rev.6.00 Oct.28.2004 page 773 of 1016 REJ09B0138-0600H SUB ↔ ↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔ ↔ ↔↔↔↔↔ ↔↔ DAA ↔↔↔↔↔↔↔↔ ADDX Addressing Mode/ Instruction Length (Bytes) Condition Code Operation Rd16-Rs16→Rd16 — [3] — [4] — [4] — — ERd32-#xx:32→ERd32 IHNZVC No. of States*1 Advanced 1 3 1 Mnemonic SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBX #xx:8,Rd SUBX Rs,Rd SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DAS Rd MULXU.B Rs,Rd MULXU.W Rs,ERd W 2 B 2 B 2 L 2 L 2 W 2 Rd16-2→Rd16 ERd32-1→ERd32 ERd32-2→ERd32 Rd8 decimal adjust→Rd8 W 2 Rd16-1→Rd16 B 2 Rd8-1→Rd8 L 2 ERd32-4→ERd32 L 2 ERd32-2→ERd32 L 2 ERd32-1→ERd32 B 2 Rd8-Rs8-C→Rd8 B2 Rd8-#xx:8-C→Rd8 L 2 ERd32-ERs32→ERd32 [5] [5] L6 W 2 SUB Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — ↔↔ ↔↔↔↔↔ ↔↔↔ ↔↔↔↔↔ ↔↔↔↔↔ ↔↔↔↔↔↔ ↔↔↔↔↔↔ ↔↔↔↔↔ MULXS.W Rs,ERd W 4 Rd16×Rs16→ERd32 (signed multiplication) —— ↔↔ ↔↔ Rev.6.00 Oct.28.2004 page 774 of 1016 REJ09B0138-0600H 1 1 —————— —————— —————— —— —— —— —— —— —* — — — — — *— Rd8×Rs8→Rd16 (unsigned multiplication) — — — — — — Rd16×Rs16→ERd32 (unsigned multiplication) MULXS.B Rs,Rd B 4 Rd8×Rs8→Rd16 (signed multiplication) —— —— —— 13 21 —————— 1 1 1 1 1 1 1 1 1 12 20 SUBX SUBS DEC DAS MULXU MULXS Addressing Mode/ Instruction Length (Bytes) Condition Code Operation Rd16÷Rs8→Rd16 (RdH: remainder, — — [6] [7] — — RdL: quotient) (unsigned division) IHNZVC No. of States*1 Advanced 12 Mnemonic DIVXU.B Rs,Rd B 2 DIVXU Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — DIVXU.W Rs,ERd Rd: quotient) (unsigned division) divxs.B Rs,Rd RdL: quotient) (signed division) DIVXS.W Rs,ERd Rd8-#xx:8 2 Rd16-#xx:16 2 Rd16-Rs16 ERd32-#xx:32 2 2 2 2 2 2 ERd32-ERs32 0-Rd8→Rd8 0-Rd16→Rd16 0-ERd32→ERd32 0→( of Rd16) 0→( of ERd32) Rd8-Rs8 W 4 B 4 W 2 ERd32÷Rs16→ERd32 (Ed: remainder, — — [6] [7] — — 20 DIVXS Rd16÷Rs8→Rd16 (RdH: remainder, — — [8] [7] — — 13 ERd32÷Rs16→ERd32 (Ed: remainder, — — [8] [7] — — Rd: quotient) (signed division) 21 CMP CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd NEG.B Rd NEG.W Rd NEG.L ERd EXTU.W Rd EXTU.L ERd L W L W B L L6 W W4 B CMP.B #xx:8,Rd B2 — — 1 1 — [3] 2 — [3] 1 — [4] 3 — [4] — — — 1 1 1 1 —— 0 0— —— 0 0— 1 1 ↔↔↔ ↔↔ ↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔ Rev.6.00 Oct.28.2004 page 775 of 1016 REJ09B0138-0600H EXTU ↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔ NEG Addressing Mode/ Instruction Length (Bytes) Condition Code Operation ( of Rd16) ↔ ↔ ↔ ↔ ( of Rd16)→ —— 0— IHNZVC No. of States*1 Advanced 1 Mnemonic EXTS.W Rd W 2 EXTS EXTS.L ERd —— ( of ERd32) @ERd-0→CCR set, (1)→ ( of @ERd) MAC @ERn+, @ERm+ CLRMAC LDMAC ERs,MACH LDMAC ERs,MACL STMAC MACH,ERd STMAC MACL,ERd Cannot be used in the H8S/2357 Group Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — L 2 MAC ↔ ↔ Rev.6.00 Oct.28.2004 page 776 of 1016 REJ09B0138-0600H ( of ERd32)→ 4 0— 1 TAS @ERd*3 B —— 0— 4 [2] TAS CLRMAC LDMAC STMAC (3) Logical Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code Operation Rd8∧#xx:8→Rd8 —— —— —— —— —— —— —— —— —— —— —— ERd32∨ERs32→ERd32 Rd8⊕#xx:8→Rd8 —— —— Rd8⊕Rs8→Rd8 Rd16⊕#xx:16→Rd16 —— —— Rd16⊕Rs16→Rd16 ERd32⊕#xx:32→ERd32 —— —— ERd32⊕ERs32→ERd32 —— IHNZVC 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— 0— No. of States*1 Advanced 1 1 2 1 3 2 1 1 2 1 3 2 1 1 2 1 3 2 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — Mnemonic AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd NOT NOT.B Rd NOT.W Rd NOT.L ERd W L B L 4 2 2 2 L6 W 2 W4 B 2 B2 L 4 L6 W 2 W4 B 2 Rd8∨Rs8→Rd8 Rd16∨#xx:16→Rd16 Rd16∨Rs16→Rd16 ERd32∨#xx:32→ERd32 B2 Rd8∨#xx:8→Rd8 L 4 ERd32∧ERs32→ERd32 L6 ERd32∧#xx:32→ERd32 W 2 Rd16∧Rs16→Rd16 W4 Rd16∧#xx:16→Rd16 B 2 Rd8∧Rs8→Rd8 B2 ¬ Rd8→Rd8 ¬ Rd16→Rd16 ¬ ERd32→ERd32 —— —— —— 0— 0— 0— 1 1 1 ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ Rev.6.00 Oct.28.2004 page 777 of 1016 REJ09B0138-0600H (4) Shift Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code Operation —— —— 0 C MSB LSB —— —— —— —— —— —— —— MSB LSB C —— —— —— —— —— 0 C MSB LSB —— —— —— —— IHNZVC No. of States*1 Advanced 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Mnemonic SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd L 2 L 2 W 2 W 2 B 2 B 2 L 2 L 2 W 2 W 2 B 2 B 2 L 2 L 2 W 2 W 2 B 2 B 2 ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ Rev.6.00 Oct.28.2004 page 778 of 1016 REJ09B0138-0600H Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — SHAL SHAR SHLL Addressing Mode/ Instruction Length (Bytes) Condition Code Operation — — — 0 — — — — — — — C MSB — — — — — — MSB — — LSB C LSB MSB LSB C —— 0 —— 0 0 0 0 0 —— 0 —— —— —— —— —— —— —— —— —— —— —— —— 0 0 0 0 0 0 0 0 0 0 0 0 0 —— 0 0 IHNZVC No. of States*1 Advanced 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Mnemonic SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd L 2 L 2 W 2 W 2 B 2 B 2 L 2 L 2 W 2 W 2 B 2 B 2 L 2 L 2 W 2 W 2 —— 0 B 2 B 2 SHLR Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — —— 0 ROTXL ↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ ROTXR Rev.6.00 Oct.28.2004 page 779 of 1016 REJ09B0138-0600H Addressing Mode/ Instruction Length (Bytes) Condition Code Operation —— —— —— C MSB LSB —— —— —— — — — MSB — 1 LSB C —— —— —— —— —— —— 0 0 0 0 0 0 0 0 0 0 0 0 IHNZVC No. of States*1 Advanced 1 1 1 1 1 1 1 1 1 1 1 1 Mnemonic ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd L 2 L 2 W 2 W 2 B 2 B 2 L 2 L 2 W 2 W 2 B 2 B 2 ↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔ ↔↔↔↔↔↔↔↔↔↔↔↔ Rev.6.00 Oct.28.2004 page 780 of 1016 REJ09B0138-0600H Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — ROTL ROTR (5) Bit-Manipulation Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code Operation (#xx:3 of Rd8)←1 IHNZVC —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— (#xx:3 of @ERd)←0 —————— (#xx:3 of @aa:8)←0 (#xx:3 of @aa:16)←0 (#xx:3 of @aa:32)←0 —————— —————— —————— No. of States*1 Advanced 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 Mnemonic BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 B B B 4 4 6 B 2 B 8 B 6 B 4 B 4 B 2 B 8 B 6 B 4 B 4 (Rn8 of @ERd)←1 (Rn8 of @aa:8)←1 (Rn8 of @aa:16)←1 (Rn8 of @aa:32)←1 (#xx:3 of Rd8)←0 B 2 (Rn8 of Rd8)←1 B 8 (#xx:3 of @aa:32)←1 B 6 (#xx:3 of @aa:16)←1 B 4 (#xx:3 of @aa:8)←1 B 4 (#xx:3 of @ERd)←1 B 2 BSET BCLR Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — (Rn8 of Rd8)←0 (Rn8 of @ERd)←0 (Rn8 of @aa:8)←0 (Rn8 of @aa:16)←0 —————— —————— —————— —————— 1 4 4 5 Rev.6.00 Oct.28.2004 page 781 of 1016 REJ09B0138-0600H Addressing Mode/ Instruction Length (Bytes) Condition Code Operation (Rn8 of @aa:32)←0 —————— IHNZVC No. of States*1 Advanced 6 1 4 Mnemonic BCLR Rn,@aa:32 BNOT #xx:3,Rd BNOT #xx:3,@ERd [¬ (#xx:3 of @ERd)] BNOT #xx:3,@aa:8 [¬ (#xx:3 of @aa:8)] BNOT #xx:3,@aa:16 [¬ (#xx:3 of @aa:16)] BNOT #xx:3,@aa:32 B 8 (#xx:3 of @aa:32)← [¬ (#xx:3 of @aa:32)] BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 B 6 B 4 B 4 B 2 (Rn8 of Rd8)←[¬ (Rn8 of Rd8)] —————— —————— B 6 (#xx:3 of @aa:16)← —————— B 4 (#xx:3 of @aa:8)← —————— B 4 (#xx:3 of @ERd)← B 2 B 8 (#xx:3 of Rd8)←[¬ (#xx:3 of Rd8)] — — — — — — —————— BCLR BTST #xx:3,@aa:16 B 6 ↔↔↔↔ Rev.6.00 Oct.28.2004 page 782 of 1016 REJ09B0138-0600H Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — 4 5 6 1 4 4 —————— [¬ (Rn8 of @aa:16)] BNOT Rn,@aa:32 B 8 (Rn8 of @aa:32)← [¬ (Rn8 of @aa:32)] BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 B B 4 4 B 2 ¬ (#xx:3 of Rd8)→Z ¬ (#xx:3 of @ERd)→Z ¬ (#xx:3 of @aa:8)→Z ¬ (#xx:3 of @aa:16)→Z ——— ——— ——— ——— —— —— —— —— 1 3 3 4 —————— 6 5 (Rn8 of @ERd)←[¬ (Rn8 of @ERd)] — — — — — — (Rn8 of @aa:8)←[¬ (Rn8 of @aa:8)] — — — — — — (Rn8 of @aa:16)← BNOT BTST Addressing Mode/ Instruction Length (Bytes) Condition Code Operation ¬ (#xx:3 of @aa:32)→Z ——— ——— ——— ——— ——— ——— ¬ (Rn8 of Rd8)→Z —— —— —— —— —— —— ————— ————— ————— ————— ————— ————— ————— ————— ¬ (#xx:3 of @aa:16)→C ¬ (#xx:3 of @aa:32)→C C→(#xx:3 of Rd8) ————— ————— IHNZVC No. of States*1 Advanced 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 Mnemonic BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 B B 4 4 B 2 B 8 B 6 B 4 B 4 B 2 B 8 B 6 B 4 (#xx:3 of @aa:8)→C (#xx:3 of @aa:16)→C (#xx:3 of @aa:32)→C ¬ (#xx:3 of Rd8)→C ¬ (#xx:3 of @ERd)→C ¬ (#xx:3 of @aa:8)→C B 4 (#xx:3 of @ERd)→C B 2 (#xx:3 of Rd8)→C B 8 ¬ (Rn8 of @aa:32)→Z B 6 ¬ (Rn8 of @aa:16)→Z B 4 ¬ (Rn8 of @aa:8)→Z B 4 ¬ (Rn8 of @ERd)→Z B 2 ↔↔↔↔↔↔ B 8 BTST BLD BST —————— C→(#xx:3 of @ERd) C→(#xx:3 of @aa:8) —————— —————— ↔↔↔↔↔↔↔↔↔↔ BILD Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — 1 4 4 Rev.6.00 Oct.28.2004 page 783 of 1016 REJ09B0138-0600H Addressing Mode/ Instruction Length (Bytes) Condition Code Operation C→(#xx:3 of @aa:16) C→(#xx:3 of @aa:32) ¬ C→(#xx:3 of Rd8) —————— —————— —————— —————— —————— —————— —————— ————— ————— ————— ————— ————— ————— ————— C∧[¬ (#xx:3 of @aa:8)]→C C∧[¬ (#xx:3 of @aa:16)]→C C∧[¬ (#xx:3 of @aa:32)]→C ————— ————— ————— IHNZVC No. of States*1 Advanced 5 6 1 4 4 5 6 1 3 3 4 5 1 3 3 4 5 Mnemonic BST #xx:3,@aa:16 BST #xx:3,@aa:32 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd B 4 B 2 B 8 B 6 B 4 B 4 B 2 B 8 B 6 B 4 B 4 C∧(#xx:3 of @ERd)→C C∧(#xx:3 of @aa:8)→C C∧(#xx:3 of @aa:16)→C C∧(#xx:3 of @aa:32)→C C∧[¬ (#xx:3 of Rd8)]→C C∧[¬ (#xx:3 of @ERd)]→C B 2 C∧(#xx:3 of Rd8)→C B 8 ¬ C→(#xx:3 of @aa:32) B 6 ¬ C→(#xx:3 of @aa:16) B 4 ¬ C→(#xx:3 of @aa:8) B 4 ¬ C→(#xx:3 of @ERd) B 2 B 8 B 6 BST C∨(#xx:3 of @ERd)→C ————— ↔↔↔↔↔↔↔↔↔↔↔↔ ————— Rev.6.00 Oct.28.2004 page 784 of 1016 REJ09B0138-0600H Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — C∨(#xx:3 of Rd8)→C 1 3 BIST BAND BIAND BOR Addressing Mode/ Instruction Length (Bytes) Condition Code Operation C∨(#xx:3 of @aa:8)→C ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— ————— C⊕[¬ (#xx:3 of @ERd)]→C ————— C⊕[¬ (#xx:3 of @aa:8)]→C C⊕[¬ (#xx:3 of @aa:16)]→C ————— ————— C∨(#xx:3 of @aa:16)→C C∨(#xx:3 of @aa:32)→C C∨[¬ (#xx:3 of Rd8)]→C IHNZVC No. of States*1 Advanced 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 Mnemonic BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 B B 6 8 B 4 B 4 B 2 B 8 B 6 B 4 B 4 B 2 C⊕(#xx:3 of Rd8)→C C⊕(#xx:3 of @ERd)→C C⊕(#xx:3 of @aa:8)→C C⊕(#xx:3 of @aa:16)→C C⊕(#xx:3 of @aa:32)→C C⊕[¬ (#xx:3 of Rd8)]→C B 8 B 6 C∨[¬ (#xx:3 of @aa:16)]→C C∨[¬ (#xx:3 of @aa:32)]→C B 4 C∨[¬ (#xx:3 of @aa:8)]→C B 4 C∨[¬ (#xx:3 of @ERd)]→C B 2 B 8 B 6 B 4 BOR BIOR BXOR Rev.6.00 Oct.28.2004 page 785 of 1016 REJ09B0138-0600H C⊕[¬ (#xx:3 of @aa:32)]→C ————— ↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔ BIXOR Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — 5 (6) Branch Instructions Addressing Mode/ Instruction Length (Bytes) Operation Condition Code Branching Condition No. of States*1 Advanced 2 3 2 Mnemonic BRA d:8(BT d:8) BRA d:16(BT d:16) BRN d:8(BF d:8) BRN d:16(BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:B(BHS d:8) BCC d:16(BHS d:16) BCS d:8(BLO d:8) BCS d:16(BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 — — — — — 4 2 4 2 4 V=0 Z=1 — 2 — 4 Z=0 — 2 — 4 C=1 — 2 — 4 C=0 — 2 — 4 C∨Z=1 — 2 — 4 C∨Z=0 — 2 else next; Never — 4 PC←PC+d — 2 if condition is true then Always Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — IHNZVC —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— Rev.6.00 Oct.28.2004 page 786 of 1016 REJ09B0138-0600H 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 Bcc Addressing Mode/ Instruction Length (Bytes) Operation Condition Code Branching Condition No. of States*1 Advanced 2 3 2 3 2 Mnemonic BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 — 4 — 2 — 4 — 2 — 4 — 2 — 4 N⊕V=1 — 2 — 4 N⊕V=0 — 2 N=1 — 4 — 2 N=0 — 4 — 2 V=1 —————— —————— —————— —————— —————— —————— —————— —————— —————— —————— Z∨(N⊕V)=0 — — — — — — —————— Z∨(N⊕V)=1 — — — — — — —————— Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — IHNZVC Bcc 3 2 3 2 3 2 3 2 3 Rev.6.00 Oct.28.2004 page 787 of 1016 REJ09B0138-0600H Addressing Mode/ Instruction Length (Bytes) Condition Code Operation PC←ERn —————— —————— —————— —————— —————— —————— —————— —————— —————— IHNZVC No. of States*1 Advanced 2 3 5 4 5 4 5 6 5 Mnemonic JMP @ERn JMP @aa:24 JMP @@aa:8 BSR d:8 BSR d:16 JSR @ERn JSR @aa:24 JSR @@aa:8 RTS — 2 PC←@SP+ — 2 PC→@-SP,PC←@aa:8 — 4 PC→@-SP,PC←aa:24 — 2 PC→@-SP,PC←ERn — 4 PC→@-SP,PC←PC+d:16 — 2 PC→@-SP,PC←PC+d:8 — 2 PC←@aa:8 — 4 PC←aa:24 — 2 JMP Rev.6.00 Oct.28.2004 page 788 of 1016 REJ09B0138-0600H Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — BSR JSR RTS (7) System Control Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code Operation PC→@-SP,CCR→@-SP, EXR→@-SP,→PC ↔ No. of States*1 Advanced 8 [9] Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — Mnemonic TRAPA EXR←@SP+,CCR←@SP+, PC←@SP+ SLEEP LDC LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR W W W W W W 4 4 6 6 8 8 W 10 W 10 W 6 W 6 W 4 W 4 B 2 Rs8→EXR @ERs→CCR @ERs→EXR @(d:16,ERs)→CCR @(d:16,ERs)→EXR @(d:32,ERs)→CCR @(d:32,ERs)→EXR @ERs→CCR,ERs32+2→ERs32 @ERs→EXR,ERs32+2→ERs32 @aa:16→CCR @aa:16→EXR @aa:32→CCR @aa:32→EXR B 2 Rs8→CCR B4 #xx:8→EXR LDC #xx:8,CCR B2 #xx:8→CCR SLEEP — Transition to power-down state TRAPA #xx:2 — IHNZVC 1 ————— —————— ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ RTE RTE — 5 [9] 2 1 —————— ↔ ↔ ↔ ↔ ↔ ↔ 2 1 —————— ↔ ↔ ↔ ↔ ↔ ↔ 1 3 —————— ↔ ↔ ↔ ↔ ↔ ↔ 3 4 —————— ↔ ↔ ↔ ↔ ↔ ↔ 4 6 —————— ↔ ↔ ↔ ↔ ↔ ↔ 6 4 —————— ↔ ↔ ↔ ↔ ↔ ↔ 4 4 —————— ↔ ↔ ↔ ↔ ↔ ↔ 4 5 —————— 5 Rev.6.00 Oct.28.2004 page 789 of 1016 REJ09B0138-0600H Addressing Mode/ Instruction Length (Bytes) Condition Code Operation CCR→Rd8 EXR→Rd8 —————— —————— —————— —————— —————— —————— —————— —————— IHNZVC No. of States*1 Advanced 1 1 3 3 4 4 6 6 4 Mnemonic STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@-ERd STC EXR,@-ERd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 ANDC #xx:8,CCR ANDC #xx:8,EXR ORC #xx:8,CCR ORC #xx:8,EXR XORC #xx:8,CCR XORC #xx:8,EXR NOP — B4 B2 B4 B2 B4 B2 W 8 W 8 W 6 W 6 CCR→@aa:16 EXR→@aa:16 CCR→@aa:32 EXR→@aa:32 CCR∧#xx:8→CCR EXR∧#xx:8→EXR CCR∨#xx:8→CCR EXR∨#xx:8→EXR CCR⊕#xx:8→CCR EXR⊕#xx:8→EXR 2 PC←PC+2 W 4 W 4 W 10 EXR→@(d:32,ERd) W 10 CCR→@(d:32,ERd) W 6 EXR→@(d:16,ERd) W 6 CCR→@(d:16,ERd) W 4 EXR→@ERd W 4 CCR→@ERd B 2 B 2 ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Rev.6.00 Oct.28.2004 page 790 of 1016 REJ09B0138-0600H Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — ERd32-2→ERd32,CCR→@ERd — — — — — — ERd32-2→ERd32,EXR→@ERd —————— —————— —————— —————— —————— 4 4 4 5 5 1 —————— 2 1 —————— 2 1 —————— —————— 2 1 STC ANDC ORC XORC NOP (8) Block Transfer Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code Operation IHNZVC —————— No. of States*1 Advanced 4+2n *2 Mnemonic EEPMOV.B — 4 if R4L≠0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4L-1→R4L Until R4L=0 else next; 4 if R4≠0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4-1→R4 Until R4=0 else next; EEPMOV Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — EEPMOV.W — —————— 4+2n *2 Notes: 1. The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. 2. n is the initial value of R4L or R4. 3. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. [1] Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. [2] Cannot be used in the H8S/2357 Series. [3] Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. [4] Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. [5] Retains its previous value when the result is zero; otherwise cleared to 0. [6] Set to 1 when the divisor is negative; otherwise cleared to 0. [7] Set to 1 when the divisor is zero; otherwise cleared to 0. [8] Set to 1 when the quotient is negative; otherwise cleared to 0. [9] One additional state is required for execution when EXR is valid. Rev.6.00 Oct.28.2004 page 791 of 1016 REJ09B0138-0600H A.2 Table A-2 Instruction Codes Instruction Format Size 1st byte 8 rd 8 rd rd rd 0 erd IMM IMM 9 9 A A B B B rd E rd IMM rs rd rd rd 0 erd 0 IMM 4 1 IMM rd 0 7 0 0 disp 0 0 disp 1 0 disp disp abs abs 7 6 0 IMM 0 6 0 IMM 0 7 6 0 IMM 0 7 6 0 IMM 0 0 6 0 IMM 0 erd abs 1 3 6 6 0 ers 0 erd IMM IMM 6 rs 6 F rd 6 9 6 A 1 6 1 6 C E A A 0 8 1 8 rs IMM 9 0 erd 8 0 erd 0 0 erd 1 ers 0 erd 1 rs 1 rs 0 7 0 7 0 0 0 0 9 0 E 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4 5 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B W W L L L L L B B B B W W L L B B B B B B B — — — — Instruction Mnemonic ADD ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd Instruction Codes ADDS ADDS #1,ERd ADDS #2,ERd Table A-2 shows the instruction codes. Rev.6.00 Oct.28.2004 page 792 of 1016 REJ09B0138-0600H ADDS #4,ERd ADDX ADDX #xx:8,Rd ADDX Rs,Rd AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 Bcc BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) Instruction Mnemonic Size 1st byte 4 2 8 2 disp 3 disp 4 disp 5 disp 6 disp 7 disp 8 disp 9 disp A disp B disp C disp D disp E disp F 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 0 disp 3 8 4 8 5 8 6 8 7 8 8 8 9 8 A 8 B 8 C 8 D 8 E 8 F 8 0 disp 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 disp 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte — — — — — — — — — — — — — — — — — — — — — — — — — — — — BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 Instruction Format Bcc Rev.6.00 Oct.28.2004 page 793 of 1016 REJ09B0138-0600H Instruction Mnemonic Size 1st byte 7 2 rd 0 7 2 0 0 7 2 0 7 2 0 0 IMM abs 0 IMM 2 abs 0 IMM 7 8 8 rd 0 6 2 rn 0 0 6 2 rn 6 2 rn 0 0 abs rn abs 2 6 8 8 rd 0 7 6 0 0 7 6 0 7 6 1 IMM 0 abs 1 IMM 6 abs 1 IMM 7 0 0 rd 0 7 7 0 0 7 abs 7 1 IMM 0 7 7 1 IMM 0 7 abs 1 IMM 7 0 0 rd 0 7 4 0 0 7 abs 4 1 IMM 0 7 4 1 IMM 0 4 abs 1 IMM 7 0 0 1 IMM 1 IMM 1 IMM 0 IMM D F A 1 3 rn 0 erd abs 1 3 1 IMM 0 erd abs 1 3 1 IMM 0 erd abs 1 3 1 IMM 0 erd abs 1 3 A 2 D F A A 6 C E A A 7 C E A A 4 C E A A abs 0 erd 7 7 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 0 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B B B B B B B B B B B B B B B B B B B B B B B B BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 Instruction Format BCLR Rev.6.00 Oct.28.2004 page 794 of 1016 REJ09B0138-0600H BIAND BILD BIOR Instruction Mnemonic Size 1st byte 6 7 rd 0 6 7 0 0 6 7 0 6 7 0 1 IMM abs 1 IMM 7 abs 1 IMM 6 8 8 rd 0 7 5 0 0 7 5 0 7 5 1 IMM 0 abs 1 IMM 5 abs 1 IMM 7 0 0 rd 0 7 7 0 0 7 7 0 7 7 0 IMM 0 abs 0 IMM 7 abs 0 IMM 7 0 0 rd 0 7 1 0 0 7 abs 1 0 IMM 0 7 1 0 IMM 0 1 abs 0 IMM 7 8 8 rd 0 6 1 1 abs abs rn rn 6 8 8 0 0 6 1 rn 0 6 1 rn 0 0 IMM 0 IMM 1 IMM 1 IMM D F A 1 3 1 IMM 0 erd abs 1 3 0 IMM 0 erd abs 1 3 0 IMM 0 erd abs 1 3 rn 0 erd abs 1 3 A 5 C E A A 7 C E A A 1 D F A A 1 D F A A abs 0 erd 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 1 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B B B B B B B B B B B B B B B B B B B B B B B B BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 Instruction Format BIST BIXOR BLD BNOT Rev.6.00 Oct.28.2004 page 795 of 1016 REJ09B0138-0600H Instruction Mnemonic Size 1st byte 7 4 rd 0 7 4 0 0 7 4 0 7 4 0 0 IMM abs 0 IMM 4 abs 0 IMM 7 0 0 rd 0 7 0 0 0 7 0 0 7 0 0 IMM 0 abs 0 IMM 0 abs 0 IMM 7 8 8 rd 0 6 0 rn 0 0 6 0 0 6 0 rn 0 rn abs rn abs 0 6 8 8 disp 0 0 rd 0 6 7 0 0 6 abs 7 0 IMM 0 6 7 0 IMM 0 7 abs 0 IMM 6 8 8 rd 0 7 3 3 7 0 0 rd 0 6 3 rn 0 0 IMM 0 IMM abs abs 0 0 7 3 0 IMM 0 7 3 0 IMM 0 0 IMM 0 IMM 0 erd abs 1 3 0 IMM 0 erd abs 1 3 rn 0 erd disp 0 IMM 0 IMM C E A 1 3 0 IMM 0 erd abs 1 3 rn 0 erd abs 1 3 A 0 D F A A 0 D F A A 5 C 7 D F A A 3 C E A A 3 C abs 0 erd 7 7 6 6 7 7 7 6 6 6 7 7 6 6 5 5 6 7 7 6 6 7 7 7 6 6 6 7 0 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B B B B B B B B B B B B B B — — B B B B B B B B B B B B BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR d:8 BSR d:16 BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd Instruction Format BOR Rev.6.00 Oct.28.2004 page 796 of 1016 REJ09B0138-0600H BSET BSR BST BTST Instruction Mnemonic Size 1st byte 7 E 6 0 6 abs 6 3 rn 0 3 rn 0 0 rd 0 7 7 0 7 abs 7 5 0 IMM 0 5 0 0 abs 0 IMM 5 0 IMM 0 5 0 0 IMM abs 3 rn 0 A 1 3 0 IMM 0 erd abs 1 3 A 5 C E A A abs 6 6 7 7 7 6 6 Cannot be used in the H8S/2357 Group A rd C rs rd rd rd 0 erd IMM IMM 2 rs 2 1 ers 0 erd 0 rd rd rd rd rd 0 erd 0 erd 0 0 rd 0 erd C 4 5 5 9 9 8 8 F F 5 3 rs 5 1 rs rd 0 erd 0 0 5 D 7 F D D rs rs 5 D 9 D A F F F A B B B B 1 1 1 3 B B 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B B B B B B B — B B W W L L B B B W W L L B W B W — — BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 Instruction Format BTST BXOR CLRMAC CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd CMP DAA DAS DEC DIVXS DIVXU EEPMOV EEPMOV.B EEPMOV.W Rev.6.00 Oct.28.2004 page 797 of 1016 REJ09B0138-0600H Instruction Mnemonic Size 1st byte 1 7 D rd 0 erd rd 0 erd rd rd rd 0 erd 0 erd 0 abs abs 0 ern 0 abs abs IMM 4 1 0 7 rs rs 0 6 9 0 0 0 0 0 0 0 ers D D B 6 B 0 ers 0 0 0 0 0 0 disp 6 disp 1 6 6 B B disp disp 2 2 0 0 disp disp 9 F F 8 8 0 ers 0 ers 0 ers 0 ers 0 ers 6 6 6 7 7 6 6 1 0 1 0 1 0 1 0 0 ers 0 1 4 4 4 4 4 4 4 4 4 4 IMM F 5 7 0 5 D 7 F 0 ern 7 7 7 A B B B B 9 A B D E F 7 1 3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 5 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte W L W L B W W L L — — — — — — B B B B W W W W W W W W W W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd JMP @ERn JMP @aa:24 JMP @@aa:8 JSR @ERn JSR @aa:24 JSR @@aa:8 LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR Instruction Format EXTS EXTU INC Rev.6.00 Oct.28.2004 page 798 of 1016 REJ09B0138-0600H JMP JSR LDC Instruction Mnemonic Size 1st byte 0 1 4 0 6 B 2 2 7 7 7 0 ern+3 0 ern+2 0 ern+1 0 abs B D D D 6 6 6 6 1 0 0 0 4 1 2 3 1 1 1 1 0 0 0 0 Cannot be used in the H8S/2357 Group 0 abs 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte W W L L L L L — B rd C rs rd rd rd 0 6 A 2 rd rd disp disp 0 ers 0 ers 0 ers 0 ers abs 0 rd rd rs rs 0 6 A A rs rs disp disp abs 2 1 erd 1 erd 0 erd 1 erd abs 8 rs rs rd rd rd rd 0 6 B disp 2 rd disp IMM A 0 rs 0 ers 0 ers 0 ers abs abs abs 8 E 8 C rd A A 8 E 8 C rs A A 9 D 9 F 8 B B B B B B B B B B B B B B B W W W W W 7 6 6 0 7 6 6 3 6 7 6 6 6 6 2 6 7 6 6 0 F IMM LDC @aa:32,CCR LDC @aa:32,EXR LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC ERs,MACH LDMAC ERs,MACL MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa :16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd Instruction Format LDC LDM LDMAC MAC MOV Rev.6.00 Oct.28.2004 page 799 of 1016 REJ09B0138-0600H Instruction Mnemonic Size 1st byte 6 D rd rd rd rs rs 0 6 B A rs rs rs rs 0 erd IMM abs abs disp disp abs abs B 0 2 1 erd 1 erd 0 erd 1 erd 8 A 0 1 ers 0 erd 0 0 6 9 F 8 0 6 B 2 D B 0 2 1 erd 0 ers 1 erd 0 ers 0 erd 0 6 1 erd 0 ers 8 A 0 ers 0 ers abs abs B disp A 0 ers disp 0 erd B 9 F 8 D B B 0 erd abs abs 0 ers 0 erd 0 ers 0 erd 0 ers 0 erd disp disp 6 7 6 6 6 6 6 7 6 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ers 0 erd B 9 F 8 D B B A F 1 1 1 1 1 1 1 1 1 1 1 1 6 6 6 6 7 6 6 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 Cannot be used in the H8S/2357 Group 0 ers 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte W W W W W W W W W L L L L L L L L L L MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16 ,ERd MOV.L @aa:32 ,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd)*1 L MOV.L ERs,@-ERd L L L B B B 1 C 0 5 5 0 rd 0 erd C rs rs 1 0 2 W B W 5 5 0 0 0 2 rs rs rd 0 erd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 Instruction Format Rev.6.00 Oct.28.2004 page 800 of 1016 REJ09B0138-0600H MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd MOV MOVFPE MOVFPE @aa:16,Rd MOVTPE MOVTPE Rs,@aa:16 MULXS MULXU Instruction Mnemonic Size 1st byte 1 7 8 rd rd 0 erd 0 rd rd 0 erd IMM rs rd rd rd 0 erd 0 IMM 4 1 rn 0 rn 0 rd rd rd rd 0 erd 0 erd 6 D F 0 ern 6 D 7 0 ern 7 0 F 0 8 C 9 D B F 0 4 IMM 6 4 0 ers 0 erd IMM IMM 4 rs 4 F 9 B 0 0 1 3 7 7 0 7 7 7 rd 4 9 4 A 1 4 1 D 1 D 1 2 2 2 2 2 2 1 1 0 1 1 1 C 1 7 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B W L — B W L B B W W L L B B W L W L B B W W L L NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn ROTL.B Rd ROTL.B #2, Rd ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd ROTL.L #2, ERd Instruction Format NEG NOP NOT OR ORC POP PUSH ROTL Rev.6.00 Oct.28.2004 page 801 of 1016 REJ09B0138-0600H Instruction Mnemonic Size 1st byte 1 3 8 rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 0 rd rd rd rd 0 erd 0 erd C 9 D B F 0 4 1 5 3 7 0 4 1 5 3 7 7 7 8 C 9 D B F 3 3 3 3 3 2 2 2 2 2 2 3 3 3 3 3 3 6 4 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B W W L L B B W W L L B B W W L L — — B B W W L L ROTR.B Rd ROTR.B #2, Rd ROTR.W Rd ROTR.W #2, Rd ROTR.L ERd ROTR.L #2, ERd ROTXL.B Rd ROTXL.B #2, Rd ROTXL.W Rd ROTXL.W #2, Rd ROTXL.L ERd ROTXL.L #2, ERd ROTXR.B Rd ROTXR.B #2, Rd ROTXR.W Rd ROTXR.W #2, Rd ROTXR.L ERd ROTXR.L #2, ERd RTE RTS SHAL.B Rd SHAL.B #2, Rd SHAL.W Rd SHAL.W #2, Rd SHAL.L ERd SHAL.L #2, ERd Instruction Format ROTR Rev.6.00 Oct.28.2004 page 802 of 1016 REJ09B0138-0600H ROTXL ROTXR RTE RTS SHAL Instruction Mnemonic Size 1st byte 1 1 8 rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 rd rd 0 1 0 1 0 1 0 1 7 6 6 7 8 8 D D 6 F 6 F 6 9 1 erd 1 erd 1 erd 0 erd 0 erd 1 erd 1 erd 6 9 1 erd 0 0 0 0 0 0 0 0 6 6 B B disp disp A A 0 0 disp disp C 9 D B F 0 4 1 5 3 7 0 4 1 5 3 7 8 0 1 4 4 4 4 4 4 4 4 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B W W L L B B W W L L B B W W L L — B B W W SHAR.B Rd SHAR.B #2, Rd SHAR.W Rd SHAR.W #2, Rd SHAR.L ERd SHAR.L #2, ERd SHLL.B Rd SHLL.B #2, Rd SHLL.W Rd SHLL.W #2, Rd SHLL.L ERd SHLL.L #2, ERd SHLR.B Rd SHLR.B #2, Rd SHLR.W Rd SHLR.W #2, Rd SHLR.L ERd SHLR.L #2, ERd SLEEP STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) W STC.W EXR,@(d:16,ERd) W STC.W CCR,@(d:32,ERd) W STC.W EXR,@(d:32,ERd) W STC.W CCR,@-ERd W W STC.W EXR,@-ERd Instruction Format SHAR SHLL SHLR SLEEP STC Rev.6.00 Oct.28.2004 page 803 of 1016 REJ09B0138-0600H Instruction Mnemonic Size 1st byte 0 1 4 0 6 B 8 0 0 0 0 0 ern 0 ern 0 ern abs abs abs 8 A A F F F B B B D D D 6 6 6 6 6 6 1 0 1 0 0 0 4 4 4 1 2 3 1 1 1 1 1 1 abs 0 0 0 0 0 0 Cannot be used in the H8S/2357 Group 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte W W W W L L L L L B 8 rs rd rd rd 0 erd IMM IMM 3 rs 3 1 ers 0 erd 0 8 9 IMM rs rd 0 7 B C 0 0 erd E 00 IMM IMM rs rd rd rd 0 erd 0 6 5 IMM 0 ers 0 erd IMM 5 rs 5 F 0 erd 0 erd 0 erd 9 9 A A B B B rd E 1 7 rd 5 9 5 A 1 W W L L L L L B B B — B B W W L L 0 7 6 7 1 D 5 0 1 B 1 1 1 1 7 1 7 1 STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM.L(ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP STM.L (ERn-ERn+3), @-SP STMAC MACH,ERd STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd*2 TRAPA #x:2 XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd Instruction Format STC STM STMAC Rev.6.00 Oct.28.2004 page 804 of 1016 REJ09B0138-0600H SUB SUBS SUBX TAS TRAPA XOR Instruction Mnemonic Size 1st byte 0 0 1 4 1 0 5 IMM 5 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte B B XORC #xx:8,CCR XORC #xx:8,EXR Instruction Format XORC Notes: 1. Bit 7 of the 4th byte of the MOV.L ERs, @(d:32,ERd) instruction can be either 1 or 0. 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Immediate data (2, 3, 8, 16, or 32 bits) Absolute address (8, 16, 24, or 32 bits) Displacement (8, 16, or 32 bits) Register field (4 bits specifying an 8-bit or 16-bit register. The symbols rs, rd, and rn correspond to operand symbols Rs, Rd,and Rn.) Register field (3 bits specifying an address register or 32-bit register. The symbols ers, erd, ern, and erm correspond to operand symbols ERs, ERd, ERn, and ERm.) Legen: IMM: abs: disp: rs, rd, rn: ers, erd, ern, erm: The register fields specify general registers as follows. 16-Bit Register Register Field 0000 0001 • • • 0111 1000 1001 • • • 1111 R0 R1 • • • R7 E0 E1 • • • E7 0000 0001 • • • 0111 1000 1001 • • • 1111 R0H R1H • • • R7H R0L R1L • • • R7L General Register Register Field General Register 8-Bit Register Address Register 32-Bit Register General Register ER0 ER1 • • • ER7 Register Field 000 001 • • • 111 Rev.6.00 Oct.28.2004 page 805 of 1016 REJ09B0138-0600H A.3 Table A-3 Operation Code Map (1) Instruction when most significant bit of BH is 0. 1st byte AH AL BH BL Instruction when most significant bit of BH is 1. 2nd byte Operation Code Map Instruction code Rev.6.00 Oct.28.2004 page 806 of 1016 REJ09B0138-0600H 0 1 ORC XORC XOR MOV.B AND Table A.3(2) SUB ANDC OR LDC ADD MOV CMP 2 3 5 6 8 NOP Table A.3(2) 4 7 9 A B C D E ADDX SUBX F LDC Table STC * * A.3(2) STMAC LDMAC Table Table Table A.3(2) A.3(2) A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) BRA BRN DIVXU OR MOV Table A.3(2) XOR AND BST MOV BNOT BCLR BTST MULXU DIVXU RTS BSR RTE TRAPA Table A.3(2) JMP BHI BLS BCS BNE MULXU BSET BCC BEQ BVC BVS BPL BMI BGE BSR MOV EEPMOV Table A.3(3) BLT BGT JSR BLE BIST BXOR BAND BOR BLD BIXOR BIAND BIOR BILD ADD ADDX CMP SUBX OR XOR AND MOV Table A.3(2) Table A.3(2) AL Table A-3 shows the operation code map. AH 0 1 2 3 4 5 6 7 8 9 A B C D E F Note: * Cannot be used in the H8S/2357 Group. Table A-3 Operation Code Map (2) 1st byte AH AL BH BL 2nd byte Instruction code BH 0 1 3 STM STC LDC MAC* SLEEP CLRMAC * 4 LDM 2 MOV INC ADDS DAA SHLL SHLL SHLR ROTXL ROTXR NOT EXTU EXTU ROTXR ROTXL SHLR SHAR ROTL ROTR NEG NEG SHLR ROTXL ROTXR NOT DEC SUBS DAS BRA BRN BLS BCC Table * A.3(4) MOVFPE SUB SUB OR OR XOR XOR AND AND Table A.3(4) MOV CMP CMP ADD ADD BHI MOV MOV MOV BCS BNE BEQ BVC MOV BVS BPL MOV BMI DEC DEC SUBS SHLL SHAL INC ADDS INC 5 9 A 6 7 8 B 01 AH AL C Table A.3(3) ADD D Table A.3(3) E TAS F Table A.3(3) 0A 0B INC MOV SHAL SHAR ROTL ROTR EXTS SUB DEC CMP BGE MOVTPE* BLT BGT INC 0F 10 11 12 13 17 SHAL SHAR ROTL ROTR EXTS 1A 1B DEC 1F 58 BLE 6A 79 7A Rev.6.00 Oct.28.2004 page 807 of 1016 REJ09B0138-0600H Note: * Cannot be used in the H8S/2357 Group. Table A-3 Operation Code Map (3) 1st byte AH AL BH BL CH CL DH DL 2nd byte 3rd byte 4th byte Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. Rev.6.00 Oct.28.2004 page 808 of 1016 REJ09B0138-0600H CL 0 1 3 4 5 6 7 8 9 A MULXS DIVXS DIVXS OR BTST BTST BSET BCLR BCLR BTST BTST BSET BCLR BCLR BSET BNOT BNOT BSET BNOT BNOT XOR AND 2 MULXS B C D E F BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST Instruction code AH AL BH BL CH 01C05 01D05 01F06 7Cr06 *1 7Cr07 *1 7Dr06 *1 7Dr07 *1 7Eaa6 *2 7Eaa7 *2 7Faa6 *2 7Faa7 *2 Notes: 1. r is the register specification field. 2. aa is the absolute address specification. Table A-3 Operation Code Map (4) 1st byte AH AL BH BL CH CL DH DL EH EL FH FL Instruction when most significant bit of FH is 0. Instruction when most significant bit of FH is 1. EL 0 4 5 6 7 8 9 A BTST BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 1 2 3 B C D E F 2nd byte 3rd byte 4th byte 5th byte 6th byte Instruction code AHALBHBLCHCLDHDLEH 6A10aaaa6* 6A10aaaa7* 6A18aaaa6* BSET BNOT BCLR 6A18aaaa7* Instruction code AH AL BH BL CH CL DH DL EH 1st byte 2nd byte 3rd byte 4th byte 5th byte EL 6th byte FH FL 7th byte GH GL 8th byte HH HL Instruction when most significant bit of HH is 0. Instruction when most significant bit of HH is 1. GL 0 4 BTST 1 2 3 5 AHALBHBL ... FHFLGH 6 7 8 9 A B C D E F 6A30aaaaaaaa6* 6A30aaaaaaaa7* 6A38aaaaaaaa6* BSET BNOT BCLR BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 6A38aaaaaaaa7* Rev.6.00 Oct.28.2004 page 809 of 1016 REJ09B0138-0600H Note: * aa is the absolute address specification. A.4 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table A-5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A-4 indicates the number of states required for each cycle. The number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I × SI + J × SJ + K × SK + L ×S L + M × SM + N × SN Examples: Advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. BSET #0, @FFFFC7:8 From table A-5: I = L = 2, J = K = M = N = 0 From table A-4: S I = 4, SL = 2 Number of states required for execution = 2 × 4 + 2 × 2 = 12 2. JSR @@30 From table A-5: I = J = K = 2, L = M = N = 0 From table A-4: S I = SJ = SK = 4 Number of states required for execution = 2 × 4 + 2 × 4 + 2 × 4 = 24 Table A-4 Number of States per Cycle Access Conditions On-Chip Supporting Module Cycle Instruction fetch SI On-Chip 8-Bit Memory Bus 1 4 16-Bit Bus 2 External Device 8-Bit Bus 16-Bit Bus 2-State 3-State 2-State 3-State Access Access Access Access 4 6 + 2m 2 3+m Branch address read SJ Stack operation Byte data access Word data access Internal operation SK SL SM SN 1 2 4 1 1 2 4 1 3+m 6 + 2m 1 1 1 Legend: m: Number of wait states inserted into external device access Rev.6.00 Oct.28.2004 page 810 of 1016 REJ09B0138-0600H Table A-5 Number of Cycles in Instruction Execution Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction ADD Mnemonic ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS ADDX ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 I 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 2 1 2 2 3 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 J K L Word Data Access M Internal Operation N Rev.6.00 Oct.28.2004 page 811 of 1016 REJ09B0138-0600H Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction Bcc Mnemonic BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8 BIOR #xx:8,@aa:16 BIOR #xx:8,@aa:32 BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 I 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 J K L Word Data Access M Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 1 Rev.6.00 Oct.28.2004 page 812 of 1016 REJ09B0138-0600H Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction BIXOR Mnemonic BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR BSR d:8 BSR d:16 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 Advanced Advanced I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 2 2 1 2 2 3 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 J K L Word Data Access M Internal Operation N 1 Rev.6.00 Oct.28.2004 page 813 of 1016 REJ09B0138-0600H Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction BTST Mnemonic BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CMP CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAS DEC DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV EEPMOV.B EEPMOV.W EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 1 1 1 1 1 1 1 1 1 1 1 J K L Word Data Access M Internal Operation N Cannot be used in the H8S/2357 Group 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 2 2 1 1 1 1 1 1 1 2n+2*2 2n+2*2 11 19 11 19 Rev.6.00 Oct.28.2004 page 814 of 1016 REJ09B0138-0600H Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction JMP Mnemonic JMP @ERn JMP @aa:24 JMP @@aa:8 Advanced JSR JSR @ERn JSR @aa:24 Advanced Advanced I 2 2 2 2 2 2 1 2 1 1 2 2 3 3 5 5 2 2 3 3 4 4 2 2 2 4 6 8 2 2 2 2 2 J K L Word Data Access M Internal Operation N 1 1 1 JSR @@aa:8 Advanced LDC LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs,MACH LDMAC ERs,MACL MAC MOV MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Cannot be used in the H8S/2357 Group Cannot be used in the H8S/2357 Group 1 1 1 2 4 1 1 2 3 1 2 4 1 1 1 1 1 1 1 1 1 1 1 Rev.6.00 Oct.28.2004 page 815 of 1016 REJ09B0138-0600H Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction MOV Mnemonic MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVTPE MULXS MOVFPE @:aa:16,Rd MOVTPE Rs,@:aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOP 2 2 1 1 1 1 1 1 I 1 1 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 Can not be used in the H8S/2357 Group J K L 1 1 1 1 Word Data Access M Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 1 1 11 19 11 19 Rev.6.00 Oct.28.2004 page 816 of 1016 REJ09B0138-0600H Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction NOT Mnemonic NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC ORC #xx:8,CCR ORC #xx:8,EXR POP POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd RTE RTS RTE RTS Advanced I 1 1 1 1 1 2 1 3 2 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2/3*1 2 J K L Word Data Access M Internal Operation N 1 2 1 2 1 1 1 1 1 1 Rev.6.00 Oct.28.2004 page 817 of 1016 REJ09B0138-0600H Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction SHAL Mnemonic SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP STC SLEEP STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 J K L Word Data Access M Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 STC.W CCR,@(d:16,ERd) 3 STC.W EXR,@(d:16,ERd) 3 STC.W CCR,@(d:32,ERd) 5 STC.W EXR,@(d:32,ERd) 5 STC.W CCR,@-ERd STC.W EXR,@-ERd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 2 2 3 3 4 4 Rev.6.00 Oct.28.2004 page 818 of 1016 REJ09B0138-0600H Branch Byte Instruction Address Stack Data Fetch Read Operation Access Instruction STM Mnemonic STM.L (ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP STM.L (ERn-ERn+3), @-SP STMAC STMAC MACH,ERd STMAC MACL,ERd SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBX SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS TRAPA XOR TAS @ERd* 3 Word Data Access M Internal Operation N 1 1 1 I 2 2 2 J K 4 6 8 L Cannot be used in the H8S/2357 Group 1 2 1 3 1 1 1 1 2 2 1 1 2 1 3 2 1 2 2 2/3*1 2 2 TRAPA #x:2 Advanced XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC XORC #xx:8,CCR XORC #xx:8,EXR Notes: 1. 2 when EXR is invalid, 3 when EXR is valid. 2. When n bytes of data are transferred. 3. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev.6.00 Oct.28.2004 page 819 of 1016 REJ09B0138-0600H A.5 Bus States during Instruction Execution Table A-6 indicates the types of cycles that occur during instruction execution by the CPU. See table A-4 for the number of states per cycle. How to Read the Table: Order of execution Instruction JMP@aa:24 1 R:W 2nd 2 3 4 5 6 7 8 Internal operation R:W EA 1 state End of instruction Read effective address (word-size read) No read or write Read 2nd word of current instruction (word-size read) Legend R:B R:W W:B W:W :M 2nd 3rd 4th 5th NEXT EA VEC Byte-size read Word-size read Byte-size write Word-size write Transfer of the bus is not performed immediately after this cycle Address of 2nd word (3rd and 4th bytes) Address of 3rd word (5th and 6th bytes) Address of 4th word (7th and 8th bytes) Address of 5th word (9th and 10th bytes) Address of next instruction Effective address Vector address Rev.6.00 Oct.28.2004 page 820 of 1016 REJ09B0138-0600H Figure A-1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. ø Address bus RD HWR, LWR High level R:W 2nd Fetching 3rd byte of instruction Fetching 4th byte of instruction Internal operation R:W EA Fetching 1nd byte of instruction at jump address Fetching 2nd byte of instruction at jump address Figure A-1 Address Bus, RD, HWR, and LWR Timing (8-Bit Bus, Three-State Access, No Wait States) Rev.6.00 Oct.28.2004 page 821 of 1016 REJ09B0138-0600H Table A-6 Instruction Execution Cycles 2 3 4 5 6 7 8 9 R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W NEXT Rev.6.00 Oct.28.2004 page 822 of 1016 REJ09B0138-0600H Instruction ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 1 R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT 3 R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA Instruction BLE d:8 BRA d:16 (BT d:16) R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:B:M EA R:B:M EA R:W 3rd 1 R:W NEXT R:W 2nd 4 5 6 7 8 9 BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 2 R:W EA Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state R:W:M NEXT W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA Rev.6.00 Oct.28.2004 page 823 of 1016 REJ09B0138-0600H BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 2 R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA Rev.6.00 Oct.28.2004 page 824 of 1016 REJ09B0138-0600H 3 R:W 4th 4 R:B:M EA 5 6 R:W:M NEXT W:B EA 7 8 9 R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT Instruction BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd 2 R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:W EA Internal operation, 1 state R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:W:M stack (H) R:W EA W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA W:W stack (L) W:W:M stack (H) W:W stack (L) R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA Instruction BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 Advanced BSR d:8 Advanced BSR d:16 1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd 3 R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th 4 5 6 W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA 7 8 9 BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA Rev.6.00 Oct.28.2004 page 825 of 1016 REJ09B0138-0600H 4 R:W:M NEXT R:B EA R:W:M NEXT 5 6 7 8 9 R:W:M NEXT R:B EA R:W:M NEXT Rev.6.00 Oct.28.2004 page 826 of 1016 REJ09B0138-0600H 1 2 3 R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:W 3rd R:B EA R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:W 3rd R:B EA R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:W 3rd R:B EA R:W 2nd R:W 3rd R:W 4th Cannot be used in the H8S/2357 Group R:W:M NEXT R:B EA R:W:M NEXT R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Internal operation, 11 states R:W NEXT Internal operation, 19 states Internal operation, 11 states Internal operation, 19 states R:B EAd*1 R:B EAs*2 W:B EAd*2 R:B EAs*1 *1 *1 *2 R:B EAd R:B EAs W:B EAd*2 R:B EAs ← Repeated n times*2 → R:W NEXT R:W NEXT Instruction BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd Instruction INC.W #1/2,Rd INC.L #1/2,ERd JMP @ERn JMP @aa:24 R:W EA Internal operation, R:W EA 1 state R:W:M aa:8 R:W aa:8 Internal operation, R:W EA 1 state R:W EA W:W:M stack (H) W:W stack (L) Internal operation, R:W EA W:W:M stack (H) W:W stack (L) 1 state R:W:M aa:8 R:W aa:8 W:W:M stack (H) W:W stack (L) R:W EA 1 R:W NEXT R:W NEXT R:W NEXT R:W 2nd 2 3 4 5 6 7 8 9 JMP @@aa:8 Advanced R:W NEXT Advanced R:W NEXT Advanced R:W 2nd JSR @ERn JSR @aa:24 R:W NEXT JSR @@aa:8 Advanced LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W NEXT R:W EA R:W EA R:W 5th R:W 5th R:W EA R:W NEXT R:W NEXT R:W EA R:W EA R:W EA R:W EA R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W:M stack (H)*3 R:W stack (L)*3 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.L @SP+, (ERn–ERn+1) R:W EA R:W EA R:W NEXT R:W NEXT R:W 4th R:W 4th Internal operation, 1 state R:W NEXT Internal operation, 1 state R:W 3rd R:W NEXT R:W 3rd R:W NEXT R:W 3rd R:W 4th R:W 3rd R:W 4th R:W:M NEXT Internal operation, 1 state Rev.6.00 Oct.28.2004 page 827 of 1016 REJ09B0138-0600H Instruction LDM.L @SP+,(ERn–ERn+2) 1 R:W 2nd 2 R:W NEXT 6 7 8 9 LDM.L @SP+,(ERn–ERn+3) LDMAC ERs,MACH 3 4 5 Internal operation, R:W:M stack (H)*3 R:W stack (L)*3 1 state R:W 2nd R:W NEXT Internal operation, R:W:M stack (H)*3 R:W stack (L)*3 1 state Cannot be used in the H8S/2357 Group LDMAC ERs,MACL R:W NEXT R:W EAn R:W EAm Rev.6.00 Oct.28.2004 page 828 of 1016 REJ09B0138-0600H R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:B EA R:W 4th R:B EA R:W NEXT R:B EA R:B EA R:W NEXT R:B EA R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT W:B EA R:W 4th W:B EA R:W NEXT W:B EA R:B EA R:W NEXT R:W 3rd Internal operation, 1 state R:B EA R:W NEXT R:W 3rd W:B EA R:W NEXT R:W 3rd Internal operation, 1 state W:B EA R:W NEXT R:W 3rd R:W NEXT W:B EA R:W NEXT W:B EA R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W EA R:W 4th R:W EA R:W EA R:W NEXT R:W NEXT R:W EA R:W 2nd R:W 2nd R:W NEXT R:W EA R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd W:W EA R:B EA MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@–ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+, Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd 4 R:W NEXT W:W EA Instruction MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@–ERd 1 R:W 2nd R:W 2nd R:W NEXT 3 W:W EA R:E 4th W:W EA 5 6 7 8 9 2 R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd R:W 3rd W:W EA R:W NEXT R:W NEXT W:W EA MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd R:W:M NEXT R:W:M 3rd R:W:M 3rd R:W:M NEXT R:W EA+2 R:W NEXT R:W EA+2 R:W:M EA R:W EA+2 R:W EA+2 R:W:M EA R:W EA+2 R:W EA+2 R:W:M EA R:W 5th R:W:M EA R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@–ERd W:W EA+2 R:W NEXT W:W EA+2 W:W:M EA W:W EA+2 W:W:M EA W:W:M EA R:W NEXT R:W:M EA R:W NEXT W:W EA+2 W:W:M EA R:W 5th W:W:M EA W:W EA+2 R:W:M EA R:W NEXT R:W:M 4th Internal operation, 1 state R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W 4th R:W 2nd R:W:M NEXT W:W:M EA R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W:M 4th R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W 4th Cannot be used in the H8S/2357 Group W:W EA+2 R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Internal operation, 11 states R:W NEXT Internal operation, 19 states Internal operation, 11 states Internal operation, 19 states MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd Rev.6.00 Oct.28.2004 page 829 of 1016 REJ09B0138-0600H 2 R:W NEXT R:W 3rd R:W NEXT R:W NEXT Instruction OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT W:W EA+2 R:W EA+2 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT 3 4 5 6 7 8 9 POP.L ERn PUSH.W Rn Rev.6.00 Oct.28.2004 page 830 of 1016 REJ09B0138-0600H R:W NEXT Internal operation, R:W EA 1 state R:W:M NEXT Internal operation, R:W:M EA 1 state Internal operation, W:W EA 1 state R:W:M NEXT Internal operation, W:W:M EA 1 state PUSH.L ERn ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd 2 R:W stack (EXR) R:W stack (H) R:W:M stack (H) R:W stack (L) R:W stack (L) Instruction ROTXR.L #2,ERd RTE Advanced R:W NEXT Internal operation, R:W*4 1 state Internal operation, R:W*4 1 state 1 R:W NEXT R:W NEXT 3 4 5 6 7 8 9 RTS SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) Internal operation:M R:W NEXT R:W NEXT R:W 3rd W:W EA W:W EA R:W NEXT W:W EA R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd Rev.6.00 Oct.28.2004 page 831 of 1016 REJ09B0138-0600H 5 R:W NEXT R:W NEXT W:W EA W:W EA Instruction STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@–ERd W:W EA W:W EA W:W EA R:W NEXT W:W EA R:W NEXT W:W EA W:W:M stack (H)*3 W:W stack (L)*3 W:W:M stack (H)*3 W:W stack (L)*3 W:W:M stack (H)*3 W:W stack (L)*3 1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd 2 R:W 3rd R:W 3rd R:W 3rd R:W NEXT 4 W:W EA R:W 5th R:W 5th W:W EA 6 7 8 9 STC EXR,@–ERd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 STM.L(ERn–ERn+1),@–SP Rev.6.00 Oct.28.2004 page 832 of 1016 REJ09B0138-0600H 3 R:W NEXT R:W 4th R:W 4th Internal operation, 1 state R:W 2nd R:W NEXT Internal operation, 1 state R:W 2nd R:W 3rd R:W NEXT R:W 2nd R:W 3rd R:W NEXT R:W 2nd R:W 3rd R:W 4th R:W 2nd R:W 3rd R:W 4th R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W:M NEXT Internal operation, 1 state Cannot be used in the H8S/2357 Group R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:B:M EA Internal operation, W:W stack (L) 1 state W:B EA W:W stack (H) W:W stack (EXR) R:W:M VEC R:W VEC+2 Internal operation, R:W*7 1 state R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 3rd R:W NEXT STM.L(ERn–ERn+2),@–SP STM.L(ERn–ERn+3),@–SP STMAC MACH,ERd STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd*8 TRAPA #x:2 Advanced XOR.B #xx8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd 1 R:W 2nd R:W NEXT R:W 2nd R:W VEC R:W NEXT R:W VEC+2 Internal operation, R:W*5 1 state Internal operation, W:W stack (L) W:W stack (H) 1 state W:W stack (EXR) R:W:M VEC R:W VEC+2 Internal operation, R:W*7 1 state R:W*6 Instruction XOR.L ERs,ERd XORC #xx:8,CCR XORC #xx:8,EXR Advanced Reset exception handling Interrupt exception Advanced handling 2 R:W NEXT 3 4 5 6 7 8 9 Notes: 1. 2. 3. 4. 5. 6. 7. 8. EAs is the contents of ER5. EAd is the contents of ER6. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these bus cycles are not executed. Repeated two times to save or restore two registers, three times for three registers, or four times for four registers. Start address after return. Start address of the program. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read operation is replaced by an internal operation. Start address of the interrupt-handling routine. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev.6.00 Oct.28.2004 page 833 of 1016 REJ09B0138-0600H A.6 Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below. m= 31 for longword operands 15 for word operands 7 for byte operands Si Di Ri Dn — The i-th bit of the source operand The i-th bit of the destination operand The i-th bit of the result The specified bit in the destination operand Not affected Modified according to the result of the instruction (see definition) 0 1 * Z' C' Always cleared to 0 Always set to 1 Undetermined (no guaranteed value) Z flag before instruction execution C flag before instruction execution Rev.6.00 Oct.28.2004 page 834 of 1016 REJ09B0138-0600H Table A-7 Condition Code Modification Instruction ADD H N Z V C Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm ADDS ADDX ————— H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Z' · Rm · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm AND — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 ANDC Stores the corresponding bits of the result. No flags change when the operand is EXR. BAND Bcc BCLR BIAND BILD BIOR BIST BIXOR BLD BNOT BOR BSET BSR BST BTST BXOR CLRMAC CMP ———— ————— ————— ———— ———— ———— ————— ———— ———— ————— ———— ————— ————— ————— —— —— Z = Dn C = C' · Dn + C' · Dn Cannot be used in the H8S/2357 Group H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm C = C' + Dn C = C' · Dn + C' · Dn C = Dn C = C' · Dn C = Dn C = C' + Dn C = C' · Dn ———— Rev.6.00 Oct.28.2004 page 835 of 1016 REJ09B0138-0600H Instruction DAA H * N Z V * C Definition N = Rm Z = Rm · Rm–1 · ...... · R0 C: decimal arithmetic carry DAS * * N = Rm Z = Rm · Rm–1 · ...... · R0 C: decimal arithmetic borrow DEC — — N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Rm DIVXS — —— N = Sm · Dm + Sm · Dm Z = Sm · Sm–1 · ...... · S0 N = Sm Z = Sm · Sm–1 · ...... · S0 DIVXU — —— EEPMOV EXTS ————— — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 Z = Rm · Rm–1 · ...... · R0 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Rm EXTU INC —0 — 0 — — JMP JSR LDC ————— ————— Stores the corresponding bits of the result. No flags change when the operand is EXR. LDM LDMAC MAC MOV ————— Cannnot be used in the H8S/2357 Group — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 MOVFPE MOVTPE MULXS — —— Can not be used in the H8S/2357 Group N = R2m Z = R2m · R2m–1 · ...... · R0 MULXU NEG ————— H = Dm–4 + Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Rm C = Dm + Rm NOP ————— Rev.6.00 Oct.28.2004 page 836 of 1016 REJ09B0138-0600H Instruction NOT H — N Z V 0 C — Definition N = Rm Z = Rm · Rm–1 · ...... · R0 OR — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 ORC Stores the corresponding bits of the result. No flags change when the operand is EXR. POP — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 PUSH — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 ROTL — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTR — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) ROTXL — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTXR — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) RTE RTS SHAL ————— — Stores the corresponding bits of the result. N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Dm–1 + Dm · Dm–1 (1-bit shift) V = Dm · Dm–1 · Dm–2 · Dm · Dm–1 · Dm–2 (2-bit shift) C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) SHAR — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) SHLL — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) SHLR —0 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) SLEEP STC STM ————— ————— ————— Rev.6.00 Oct.28.2004 page 837 of 1016 REJ09B0138-0600H Instruction STMAC SUB H N Z V C Definition Cannot be used in the H8S/2357 Group H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm SUBS SUBX ————— H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Z' · Rm · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm TAS — 0 — N = Dm Z = Dm · Dm–1 · ...... · D0 TRAPA XOR ————— — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 XORC Stores the corresponding bits of the result. No flags change when the operand is EXR. Rev.6.00 Oct.28.2004 page 838 of 1016 REJ09B0138-0600H Appendix B Internal I/O Register B.1 Addresses Address Register (low) Name Bit 7 H’F800 to H’FBFF MRA SAR SM1 Bit 6 SM0 Bit 5 DM1 Bit 4 DM0 Bit 3 MD1 Bit 2 MD0 Bit 1 DTS Bit 0 Sz Module Name DTC Data Bus Width 16/32 * 1 bits MRB DAR CHNE DISEL — — — — — — CRA CRB H’FE80 H’FE81 H’FE82 H’FE83 H’FE84 H’FE85 H’FE86 H’FE87 H’FE88 H’FE89 H’FE8A H’FE8B H’FE8C H’FE8D H’FE8E H’FE8F H’FE90 H’FE91 H’FE92 H’FE94 H’FE95 H’FE96 H’FE97 H’FE98 H’FE99 H’FE9A H’FE9B TCR3 TMDR3 CCLR2 — CCLR1 — IOB2 IOD2 — — CCLR0 BFB IOB1 IOD1 — — CKEG1 CKEG0 TPSC2 BFA IOB0 IOD0 TCIEV TCFV MD3 IOA3 IOC3 TGIED TGFD MD2 IOA2 IOC2 TGIEC TGFC TPSC1 MD1 IOA1 IOC1 TGIEB TGFB TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TPU3 16 bits TIOR3H IOB3 TIOR3L TIER3 TSR3 TCNT3 IOD3 TTGE — TGR3A TGR3B TGR3C TGR3D TCR4 TMDR4 TIOR4 TIER4 TSR4 TCNT4 — — IOB3 TTGE TCFD CCLR1 — IOB2 — — CCLR0 — IOB1 TCIEU TCFU CKEG1 CKEG0 TPSC2 — IOB0 TCIEV TCFV MD3 IOA3 — — MD2 IOA2 — — TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU4 16 bits TGR4A TGR4B Rev.6.00 Oct.28.2004 page 839 of 1016 REJ09B0138-0600H Address Register (low) Name Bit 7 H’FEA0 H’FEA1 H’FEA2 H’FEA4 H’FEA5 H’FEA6 H’FEA7 H’FEA8 H’FEA9 H’FEAA H’FEAB H’FEB0 H’FEB1 H’FEB2 H’FEB4 H’FEB5 H’FEB9 H’FEBA H’FEBB H’FEBC H’FEBD H’FEBE H’FEBF H’FEC4 H’FEC5 H’FEC6 H’FEC7 H’FEC8 H’FEC9 H’FECA H’FECB H’FECC H’FECD H’FECE H’FED0 H’FED1 H’FED2 H’FED3 H’FED4 H’FED5 H’FED6 H’FED7 H’FED8 H’FED9 P1DDR P2DDR P3DDR P5DDR P6DDR PADDR 2 Bit 6 CCLR1 — IOB2 — — Bit 5 CCLR0 — IOB1 TCIEU TCFU Bit 4 Bit 3 Bit 2 Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA Module Name TPU5 Data Bus Width 16 bits TCR5 TMDR5 TIOR5 TIER5 TSR5 TCNT5 — — IOB3 TTGE TCFD CKEG1 CKEG0 TPSC2 — IOB0 TCIEV TCFV MD3 IOA3 — — MD2 IOA2 — — TGR5A TGR5B P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR — — — — P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR — — P53DDR P52DDR P51DDR P50DDR Port 8 bits P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR PBDDR* PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR PCDDR* 2 PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR PDDDR* 2 PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR PEDDR PFDDR PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR — IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 ABW6 AST6 W70 W30 ICIS0 — IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 ABW5 AST5 W61 W21 PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 ABW4 AST4 W60 W20 — — — — — — — — — — — ABW3 AST3 W51 W11 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 ABW2 AST2 W50 W10 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 ABW1 AST1 W41 W01 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 ABW0 AST0 W40 W00 Bus controller 8 bits Interrupt controller 8 bits PGDDR — IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK — — — — — — — — — — — ABWCR ABW7 ASTCR WCRH WCRL BCRH BCRL MCR AST7 W71 W31 ICIS1 BRLE TPC BRSTRM BRSTS1 BRSTS0 RMTS2 RMTS1 RMST0 WDBE RLW1 CKS1 WAITE RLW0 CKS0 BREQOE EAE LCASS CW2 DDS MXC1 CMIE — MXC0 CKS2 BE RCDM DRAMCR RFSHE RCW RTCNT RTCOR — — RMODE CMF H’FEDB* 7 RAMER — H’FEDB* 8 RAMER — — — — — — RAMS RAMS RAM2 RAM1 RAM1 RAM0 RAM0 Rev.6.00 Oct.28.2004 page 840 of 1016 REJ09B0138-0600H Address Register (low) Name Bit 7 H’FEE0 H’FEE1 H’FEE2 H’FEE3 H’FEE4 H’FEE5 H’FEE6 H’FEE7 H’FEE8 H’FEE9 H’FEEA H’FEEB H’FEEC H’FEED H’FEEE H’FEEF H’FEF0 H’FEF1 H’FEF2 H’FEF3 H’FEF4 H’FEF5 H’FEF6 H’FEF7 H’FEF8 H’FEF9 H’FEFA H’FEFB H’FEFC H’FEFD H’FEFE H’FEFF H’FF00 H’FF01 H’FF02 DMAWER— DMATCR — DMACR0A DTSZ Bit 6 — Bit 5 — Bit 4 — Bit 3 — Bit 2 — Bit 1 — Bit 0 — Module Name DMAC Data Bus Width 16 bits MAR0AH — MAR0AL IOAR0A ETCR0A MAR0BH — — — — — — — — MAR0BL IOAR0B ETCR0B MAR1AH — — — — — — — — DMAC 16 bits MAR1AL IOAR1A ETCR1A MAR1BH — — — — — — — — MAR1BL IOAR1B ETCR1B — — DTID SAID DTID DAID DTID SAID DTID DAID — TEE1 RPE SAIDE RPE DAIDE RPE SAIDE RPE DAIDE — TEE0 DTDIR WE1B — DTF3 WE1A — DTF2 — DTF2 DTF2 DTF2 — DTF2 DTF2 WE0B — DTF1 — DTF1 DTF1 DTF1 — DTF1 DTF1 WE0A — DTF0 — DTF0 DTF0 DTF0 — DTF0 DTF0 Short address mode Full address mode Short address mode Full address mode Short address mode Full address mode Short address mode Full address mode 8 bits 16 bits DTSZ H’FF03 DMACR0B DTSZ BLKDIR BLKE DTDIR — DTDIR DTF3 DTF3 DTF3 — H’FF04 DMACR1A DTSZ DTSZ H’FF05 DMACR1B DTSZ BLKDIR BLKE DTDIR — DTF3 DTF3 — Rev.6.00 Oct.28.2004 page 841 of 1016 REJ09B0138-0600H Address Register (low) Name Bit 7 H’FF06 DMABCRH FAE1 Bit 6 FAE0 FAE0 DTE1A Bit 5 SAE1 — DTE0B Bit 4 SAE0 — DTE0A Bit 3 DTA1B DTA1 Bit 2 DTA1A — Bit 1 DTA0B DTA0 Bit 0 DTA0A — Module Name Short address mode Full address mode Short address mode Full address mode Interrupt controller Data Bus Width 16 bits FAE1 H’FF07 DMABCRL DTE1B DTIE1B DTIE1A DTIE0B DTIE0A DTIE1B DTIE1A DTIE0B DTIE0A DTME1 DTE1 H’FF2C H’FF2D H’FF2E H’FF2F ISCRH ISCRL IER ISR DTME0 DTE0 IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA 8 bits IRQ7E IRQ7F DTCE7 IRQ6E IRQ6F DTCE6 IRQ5E IRQ5F DTCE5 IRQ4E IRQ4F DTCE4 IRQ3E IRQ3F DTCE3 IRQ2E IRQ2F DTCE2 IRQ1E IRQ1F DTCE1 IRQ0E IRQ0F DTCE0 DTC 8 bits H’FF30 to DTCER H’FF35 H’FF37 H’FF38 H’FF39 H’FF3A DTVECR SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 SBYCR SYSCR SCKCR SSBY — STS2 — STS1 INTM1 — STS0 INTM0 — OPE NMIEG — — — SCK2 — — SCK1 — RAME SCK0 Power-down mode MCU Clock pulse generator 8 bits 8 bits 8 bits PSTOP — H’FF3B H’FF3C H’FF3D H’FF42 MDCR — — — — — MDS2 MDS1 MDS0 MSTP8 MCU Power-down mode MCU 8 bits 8 bits MSTPCRH MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTPCRL MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 — — — FLSHE — — — SYSCR2 — *ç *8 8 bits H’FF44 H’FF45 H’FF46 H’FF47 H’FF48 H’FF49 H’FF4A H’FF4B Reserved — Reserved — PCR PMR NDERH NDERL — — — — — — — — — — — — — — Reserved Reserved — — 8 bits G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 PPG G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 POD14 POD6 NDR14 NDR6 — — P16 P26 — P46 — P66 PA6 PB6 PC6 PD6 PE6 POD13 POD5 NDR13 NDR5 — — P15 P25 P35 P45 — P65 PA5 PB5 PC5 PD5 PE5 POD12 POD4 NDR12 NDR4 — — P14 P24 P34 P44 — P64 PA4 PB4 PC4 PD4 PE4 POD11 POD3 NDR11 NDR3 NDR11 NDR3 P13 P23 P33 P43 P53 P63 PA3 PB3 PC3 PD3 PE3 POD10 POD2 NDR10 NDR2 NDR10 NDR2 P12 P22 P32 P42 P52 P62 PA2 PB2 PC2 PD2 PE2 POD9 POD1 NDR9 NDR1 NDR9 NDR1 P11 P21 P31 P41 P51 P61 PA1 PB1 PC1 PD1 PE1 POD8 POD0 NDR8 NDR0 NDR8 NDR0 P10 P20 P30 P40 P50 P60 PA0 PB0 PC0 PD0 PE0 Port 8 bits PODRH POD15 PODRL POD7 NDR15 NDR7 — — P17 P27 — P47 — P67 PA7 2 H’FF4C* 3 NDRH H’FF4D* NDRL H’FF4E * 3 NDRH H’FF4F*3 NDRL H’FF50 H’FF51 H’FF52 H’FF53 H’FF54 H’FF55 H’FF59 H’FF5A H’FF5B H’FF5C H’FF5D PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORTA 3 PORTB* PB7 PORTC*2 PC7 PORTD* PD7 PORTE PE7 2 Rev.6.00 Oct.28.2004 page 842 of 1016 REJ09B0138-0600H Address Register (low) Name Bit 7 H’FF5E H’FF5F H’FF60 H’FF61 H’FF62 H’FF64 H’FF65 H’FF69 H’FF6A H’FF6B H’FF6C H’FF6D H’FF6E H’FF6F H’FF70 H’FF71 H’FF72 H’FF73 H’FF74 H’FF76 H’FF77 H’FF78 PORTF PORTG P1DR P2DR P3DR P5DR P6DR PADR PF7 — P17DR P27DR — — P67DR Bit 6 PF6 — P16DR P26DR — — P66DR Bit 5 PF5 — P15DR P25DR P35DR — P65DR Bit 4 PF4 PG4 P14DR P24DR P34DR — P64DR Bit 3 PF3 PG3 P13DR P23DR P33DR P53DR P63DR Bit 2 PF2 PG2 P12DR P22DR P32DR P52DR P62DR Bit 1 PF1 PG1 P11DR P21DR P31DR P51DR P61DR Bit 0 PF0 PG0 P10DR P20DR P30DR P50DR P60DR Module Name Port Data Bus Width 8 bits PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR PBDR*2 PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR PCDR* 2 PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR PDDR* 2 PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR PEDR PFDR PGDR PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR PF7DR — PF6DR — PF5DR — PF4DR PF3DR PF2DR PF1DR PF0DR PG4DR PG3DR PG2DR PG1DR PG0DR PAPCR* 2 PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR PBPCR* 2 PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR PCPCR*2 PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR PDPCR*2 PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR PEPCR* 2 PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR P3ODR — — P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR PAODR* 2 PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR SMR0 C/A / GM* 4 CHR PE O/E STOP MP CKS1 CKS0 SCI0, Smart Card interface 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 8 bits H’FF79 H’FF7A H’FF7B H’FF7C BRR0 SCR0 TDR0 SSR0 TDRE RDRF ORER FER/ ERS*5 PER TEND MPB MPBT H’FF7D H’FF7E H’FF80 RDR0 SCMR0 SMR1 — C/A / GM* 4 — CHR — PE — O/E SDIR STOP SINV MP — CKS1 SMIF CKS0 SCI1, Smart Card interface 1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 8 bits H’FF81 H’FF82 H’FF83 H’FF84 BRR1 SCR1 TDR1 SSR1 TDRE RDRF ORER FER/ ERS*5 PER TEND MPB MPBT H’FF85 H’FF86 H’FF88 RDR1 SCMR1 SMR2 — C/A / GM* 4 — CHR — PE — O/E SDIR STOP SINV MP — CKS1 SMIF CKS0 SCI2, Smart Card interface 2 TIE RIE TE RE MPIE TEIE CKE1 CKE0 8 bits H’FF89 H’FF8A H’FF8B BRR2 SCR2 TDR2 Rev.6.00 Oct.28.2004 page 843 of 1016 REJ09B0138-0600H Address Register (low) Name Bit 7 H’FF8C SSR2 TDRE Bit 6 RDRF Bit 5 ORER Bit 4 FER/ ERS*5 Bit 3 PER Bit 2 TEND Bit 1 MPB Bit 0 MPBT Module Name SCI2, Smart Card interface 2 Data Bus Width 8 bits H’FF8D H’FF8E H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H’FFA4 H’FFA5 H’FFA6 H’FFAC H’FFB0 H’FFB1 H’FFB2 H’FFB3 H’FFB4 H’FFB5 H’FFB6 H’FFB7 H’FFB8 H’FFB9 H’FFBC (read) H’FFBD (read) H’FFBF (read) H’FFC0 H’FFC1 RDR2 SCMR2 — — AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE — AD7 — AD7 — AD7 — AD7 — ADST — AD6 — AD6 — AD6 — AD6 — SCAN — SDIR AD5 — AD5 — AD5 — AD5 — CKS — SINV AD4 — AD4 — AD4 — AD4 — — — — AD3 — AD3 — AD3 — AD3 — CH1 — SMIE AD2 — AD2 — AD2 — AD2 — CH0 — ADDRAH AD9 ADDRAL AD1 ADDRBH AD9 ADDRBL AD1 ADDRCH AD9 ADDRCL AD1 ADDRDH AD9 ADDRDL AD1 ADCSR ADCR DADR0 DADR1 DACR ADF A/D converter 8 bits TRGS1 TRGS0 — D/A converter 8 bits DAOE1 DAOE0 DAE — CMIEA CMIEA CMFA CMFA — OVIE OVIE OVF OVF — — CCLR1 CCLR1 ADTE — — — CCLR0 CCLR0 OS3 OS3 — — CKS2 CKS2 OS2 OS2 — — CKS1 CKS1 OS1 OS1 — — CKS0 CKS0 OS0 OS0 Reserved 8-bit timer channel 0, 1 — 16 bits Reserved — TCR0 TCR1 TCSR0 TCSR1 TCORA0 TCORA1 TCORB0 TCORB1 TCNT0 TCNT1 TCSR OVF CMIEB CMIEB CMFB CMFB WT/IT TME — — CKS2 CKS1 CKS0 WDT 16 bits TCNT RSTCSR WOVF RSTE RSTS * 6 — — — — — TSTR TSYR — — — — SWE — — EB6 SWE — EB6 — CST5 CST4 CST3 CST2 CST1 CST0 TPU 16 bits SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 — — — EB5 ESU — EB5 — — — — EB4 PSU — EB4 — EV — — EB3 EV — EB3 EB11 PV — — EB2 PV — EB2 EB10 E ESU EB9 EB1 E — EB1 EB9 P PSU EB8 EB0 P — EB0 EB8 FLASH (2398F-ZTAT) 8 bits FLASH (2357F-ZTAT) 8 bits H’FFC8* 7 FLMCR1 FWE H’FFC9* FLMCR2 FLER H’FFCA* 7 EBR1 H’FFCB* EBR2 7 7 — EB7 H’FFC8* 8 FLMCR1 FWE H’FFC9* FLMCR2 FLER H’FFCA* 8 EBR1 H’FFCB* 8 EBR2 EB7 — 8 Rev.6.00 Oct.28.2004 page 844 of 1016 REJ09B0138-0600H Address Register (low) Name Bit 7 H’FFD0 H’FFD1 H’FFD2 H’FFD3 H’FFD4 H’FFD5 H’FFD6 H’FFD7 H’FFD8 H’FFD9 H’FFDA H’FFDB H’FFDC H’FFDD H’FFDE H’FFDF H’FFE0 H’FFE1 H’FFE2 H’FFE4 H’FFE5 H’FFE6 H’FFE7 H’FFE8 H’FFE9 H’FFEA H’FFEB H’FFF0 H’FFF1 H’FFF2 H’FFF4 H’FFF5 H’FFF6 H’FFF7 H’FFF8 H’FFF9 H’FFFA H’FFFB TGR2B TGR2A TCR2 TMDR2 TIOR2 TIER2 TSR2 TCNT2 — — IOB3 TTGE TCFD TGR1B TGR1A TCR1 TMDR1 TIOR1 TIER1 TSR1 TCNT1 — — IOB3 TTGE TCFD TGR0D TGR0C TGR0B TGR0A TCR0 TMDR0 CCLR2 — Bit 6 CCLR1 — IOB2 IOD2 — — Bit 5 CCLR0 BFB IOB1 IOD1 — — Bit 4 Bit 3 Bit 2 Bit 1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB Bit 0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA Module Name TPU0 Data Bus Width 16 bits CKEG1 CKEG0 TPSC2 BFA IOB0 IOD0 TCIEV TCFV MD3 IOA3 IOC3 TGIED TGFD MD2 IOA2 IOC2 TGIEC TGFC TIOR0H IOB3 TIOR0L TIER0 TSR0 TCNT0 IOD3 TTGE — CCLR1 — IOB2 — — CCLR0 — IOB1 TCIEU TCFU CKEG1 CKEG0 TPSC2 — IOB0 TCIEV TCFV MD3 IOA3 — — MD2 IOA2 — — TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU1 16 bits CCLR1 — IOB2 — — CCLR0 — IOB1 TCIEU TCFU CKEG1 CKEG0 TPSC2 — IOB0 TCIEV TCFV MD3 IOA3 — — MD2 IOA2 — — TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU2 16 bits Notes: 1. Located in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as register information, and 16 bits otherwise. 2. Applies to the H8S/2357 and H8S/2398. 3. If the pulse output group 2 and pulse output group 3 output triggers are the same according to the PCR setting, the NDRH address will be H'FF4C, and if different, the address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C. Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the same according to the PCR setting, the NDRL address will be H'FF4D, and if different, the address of NDRL for group 0 will be H'FF4F, and that for group 1 will be H'FF4D. 4. Functions as C/A for SCI use, and as GM for Smart Card interface use. 5. Functions as FER for SCI use, and as ERS for Smart Card interface use. Rev.6.00 Oct.28.2004 page 845 of 1016 REJ09B0138-0600H 6. Applies to the H8S/2357 ZTAT only. 7. Applies to the H8S/2357 F-ZTAT only. 8. Applies to the H8S/2398 F-ZTAT only. Rev.6.00 Oct.28.2004 page 846 of 1016 REJ09B0138-0600H B.2 Functions H'F800—H'FBFF 7 SM1 Initial value : Read/Write : — 6 SM0 — 5 DM1 — 4 DM0 — 3 MD1 — 2 MD0 — 1 DTS — MRA—DTC Mode Register A Bit : DTC 0 Sz — Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined DTC Data Transfer Size 0 1 Byte-size transfer Word-size transfer DTC Transfer Mode Select 0 1 DTC Mode 0 0 1 1 0 1 Destination Address Mode 0 1 — 0 1 Source Address Mode 0 1 — 0 1 SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) Normal mode Repeat mode Block transfer mode — Destination side is repeat area or block area Source side is repeat area or block area Rev.6.00 Oct.28.2004 page 847 of 1016 REJ09B0138-0600H MRB—DTC Mode Register B Bit : 7 CHNE Initial value : Read/Write : — 6 DISEL — 5 H'F800—H'FBFF 4 — — 3 — — 2 — — DTC 1 — — 0 — — — — Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Reserved Only 0 should be written to these bits DTC Interrupt Select 0 1 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 After a data transfer ends, the CPU interrupt is enabled DTC Chain Transfer Enable 0 1 End of DTC data transfer DTC chain transfer SAR—DTC Source Address Register Bit : 23 22 21 20 19 H'F800—H'FBFF --------4 3 DTC 2 1 0 Initial value : Read/Write : Unde- Unde- Unde- Unde- Undefined fined fined fined fined Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — — — — — — Specifies transfer data source address DAR—DTC Destination Address Register Bit : 23 22 21 20 19 H'F800—H'FBFF --------4 3 DTC 2 1 0 Initial value : Read/Write : Unde- Unde- Unde- Unde- Undefined fined fined fined fined Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — — — — — — Specifies transfer data destination address CRA—DTC Transfer Count Register A Bit : 15 14 13 12 11 H'F800—H'FBFF 10 9 8 7 6 5 4 3 DTC 2 1 0 Initial value : Read/Write : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — — — — — — — CRAH CRAL Specifies the number of DTC data transfers Rev.6.00 Oct.28.2004 page 848 of 1016 REJ09B0138-0600H CRB—DTC Transfer Count Register B Bit : 15 14 13 12 11 H'F800—H'FBFF 10 9 8 7 6 5 4 3 DTC 2 1 0 Initial value : Read/Write : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — — — — — — — Specifies the number of DTC block data transfers TCR3—Timer Control Register 3 Bit : 7 CCLR2 Initial value : Read/Write : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W H'FE80 4 0 R/W 3 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPU3 CKEG1 CKEG0 TPSC0 0 R/W Timer Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Edge 0 0 1 1 Counter Clear 0 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation *1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture *2 TCNT cleared by TGRD compare match/input capture *2 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation *1 — Count at rising edge Count at falling edge Count at both edges Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input Internal clock: counts on ø/1024 Internal clock: counts on ø/256 Internal clock: counts on ø/4096 1 0 0 1 1 0 1 Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Rev.6.00 Oct.28.2004 page 849 of 1016 REJ09B0138-0600H TMDR3—Timer Mode Register 3 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 BFB 0 R/W H'FE81 4 BFA 0 R/W 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W TPU3 0 MD0 0 R/W Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 × × × Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — × : Don’t care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. Buffer Operation A 0 1 TGRA operates normally TGRA and TGRC used together for buffer operation Buffer Operation B 0 1 TGRB operates normally TGRB and TGRD used together for buffer operation Rev.6.00 Oct.28.2004 page 850 of 1016 REJ09B0138-0600H TIOR3H—Timer I/O Control Register 3H Bit : 7 IOB3 0 Read/Write : R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FE82 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W TPU3 Initial value : TGR3A I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 × × × TGR3A is input capture register Capture input source is TIOCA3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock × : Don’t care TGR3B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 × × × TGR3B is input capture register Capture input source is TIOCB3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT4 count-up/ count-down* × : Don’t care Note: * If bits TPSC2 to TPSC0 in TCR4 are set to B'000, and ø/1 is used as the TCNT4 count clock, this setting will be invalid and input capture will not occur. TGR3B Output disabled is output compare Initial output is register 0 output TGR3A Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Rev.6.00 Oct.28.2004 page 851 of 1016 REJ09B0138-0600H TIOR3L—Timer I/O Control Register 3L Bit : 7 IOD3 Initial value : Read/Write : 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W H'FE83 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W TPU3 TRG3C I/O Control 0 0 0 0 TGR3C Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR3C is input 1 capture × register × Capture input source is TIOCC3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock × : Don’t care Note: When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. TGR3D I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 × × × TGR3D is input capture register *2 Capture input source is TIOCD3 pin Capture input source is channel 4/count clock TGR3D Output disabled is output compare Initial output is 0 0 output at compare match register output 1 output at compare match *2 Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT4 count-up/ count-down*1 × : Don’t care Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 × Rev.6.00 Oct.28.2004 page 852 of 1016 REJ09B0138-0600H TIER3—Timer Interrupt Enable Register 3 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 — 0 — H'FE84 4 TCIEV 0 R/W 3 TGIED 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W TPU3 TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled TGR Interrupt Enable C 0 1 Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled TGR Interrupt Enable D 0 1 Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev.6.00 Oct.28.2004 page 853 of 1016 REJ09B0138-0600H TSR3—Timer Status Register 3 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 0 — H'FE85 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU3 Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT=TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Input Capture/Output Compare Flag C 0 [Clearing conditions] • When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] • When TCNT = TGRC while TGRC is functioning as output compare register • When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register 1 Input Capture/Output Compare Flag D 0 [Clearing conditions] • When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFD after reading TGFD = 1 [Setting conditions] • When TCNT = TGRD while TGRD is functioning as output compare register • When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register 1 Overflow Flag 0 1 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. TCNT3—Timer Counter 3 Bit : 15 0 14 0 13 0 12 0 11 0 H'FE86 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 TPU3 2 0 1 0 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter Rev.6.00 Oct.28.2004 page 854 of 1016 REJ09B0138-0600H TGR3A—Timer General Register 3A TGR3B—Timer General Register 3B TGR3C—Timer General Register 3C TGR3D—Timer General Register 3D Bit : 15 1 14 1 13 1 12 1 11 1 H'FE88 H'FE8A H'FE8C H'FE8E 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 TPU3 TPU3 TPU3 TPU3 2 1 1 1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCR4—Timer Control Register 4 Bit : 7 — Initial value : Read/Write : 0 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W H'FE90 4 0 R/W 3 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W TPU4 CKEG1 CKEG0 Timer Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on ø/1024 Counts on TCNT5 overflow/underflow Note: This setting is ignored when channel 4 is in phase counting mode. Clock Edge 0 0 1 1 — Count at rising edge Count at falling edge Count at both edges Counter Clear 0 0 1 1 0 1 Note: This setting is ignored when channel 4 is in phase counting mode. TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operating setting is performed by setting the SYNC bit TSYR to 1. Rev.6.00 Oct.28.2004 page 855 of 1016 REJ09B0138-0600H TMDR4—Timer Mode Register 4 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 0 — H'FE91 4 — 0 — 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W TPU4 0 MD0 0 R/W Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 × × × Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — × : Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev.6.00 Oct.28.2004 page 856 of 1016 REJ09B0138-0600H TIOR4—Timer I/O Control Register 4 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FE92 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W TPU4 TGR4A I/O Control 0 0 0 0 TGR4A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 × × × TGR4A is input capture register Capture input source is TIOCA4 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR3A TGR3A compare match/input compare match/ capture input capture × : Don’t care TGR4B I/O Control 0 0 0 0 TGR4B Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 × × × TGR4B is input capture register Capture input source is TIOCB4 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR3C TGR3C compare match/input compare match/ capture input capture × : Don’t care 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 output at compare match 1 output at compare match Toggle output at compare match 1 Rev.6.00 Oct.28.2004 page 857 of 1016 REJ09B0138-0600H TIER4—Timer Interrupt Enable Register 4 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 TCIEU 0 R/W H'FE94 4 TCIEV 0 R/W 3 — 0 — 2 — 0 — 1 TGIEB 0 R/W 0 TGIEA 0 R/W TPU4 TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev.6.00 Oct.28.2004 page 858 of 1016 REJ09B0138-0600H TSR4—Timer Status Register 4 Bit : 7 TCFD Initial value : Read/Write : 1 R 6 — 1 — 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* H'FE95 3 — 0 — 2 — 0 — 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU4 Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) Note: * Can only be written with 0 for flag clearing. TCNT4—Timer Counter 4 Bit : 15 0 14 0 13 0 12 0 11 0 H'FE96 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 TPU4 2 0 1 0 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. Rev.6.00 Oct.28.2004 page 859 of 1016 REJ09B0138-0600H TGR4A—Timer General Register 4A TGR4B—Timer General Register 4B Bit : 15 1 14 1 13 1 12 1 11 1 H'FE98 H'FE9A 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 TPU4 TPU4 2 1 1 1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCR5—Timer Control Register 5 Bit : 7 — Initial value : Read/Write : 0 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W H'FEA0 4 0 R/W 3 0 R/W 2 TPSC2 0 R/W Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 TPU5 1 TPSC1 0 R/W 0 TPSC0 0 R/W CKEG1 CKEG0 Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on ø/256 External clock: counts on TCLKD pin input Note: This setting is ignored when channel 5 is in phase counting mode. Clock Edge 0 0 1 1 — Count at rising edge Count at falling edge Count at both edges Note: This setting is ignored when channel 5 is in phase counting mode. Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operating setting is performed by setting the SYNC bit TSYR to 1. Rev.6.00 Oct.28.2004 page 860 of 1016 REJ09B0138-0600H TMDR5—Timer Mode Register 5 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 0 — H'FEA1 4 — 0 — 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W TPU5 0 MD0 0 R/W Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 × × × Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — × : Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev.6.00 Oct.28.2004 page 861 of 1016 REJ09B0138-0600H TIOR5—Timer I/O Control Register 5 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FEA2 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W TPU5 TGR5A I/O Control 0 0 0 0 TGR5A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 × 0 0 TGR5A is input 1 capture × register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at rising edge source is TIOCA5 Input capture at falling edge pin Input capture at both edges × : Don’t care TGR5B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 × 0 0 1 1 × TGR5B is input capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at rising edge source is TIOCB5 Input capture at falling edge pin Input capture at both edges × : Don’t care TGR5B Output disabled is output compare Initial output is 0 register output 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 0 output at compare match 1 output at compare match Toggle output at compare match Rev.6.00 Oct.28.2004 page 862 of 1016 REJ09B0138-0600H TIER5—Timer Interrupt Enable Register 5 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 TCIEU 0 R/W H'FEA4 4 TCIEV 0 R/W 3 — 0 — 2 — 0 — 1 TGIEB 0 R/W 0 TGIEA 0 R/W TPU5 TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev.6.00 Oct.28.2004 page 863 of 1016 REJ09B0138-0600H TSR5—Timer Status Register 5 Bit : 7 TCFD Initial value : Read/Write : 1 R 6 — 1 — 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 H'FEA5 2 — 0 — 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU5 — 0 — Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. TCNT5—Timer Counter 5 Bit : 15 0 14 0 13 0 12 0 11 0 H'FEA6 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 TPU5 2 0 1 0 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. Rev.6.00 Oct.28.2004 page 864 of 1016 REJ09B0138-0600H TGR5A—Timer General Register 5A TGR5B—Timer General Register 5B Bit : 15 1 14 1 13 1 12 1 11 1 H'FEA8 H'FEAA 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 TPU5 TPU5 2 1 1 1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W P1DDR—Port 1 Data Direction Register Bit : 7 0 W 6 0 W 5 0 H'FEB0 4 0 W 3 0 W 2 0 W Port 1 1 0 W 0 0 W P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : Read/Write : W Specify input or output for individual port 1 pins P2DDR—Port 2 Data Direction Register Bit : 7 0 W 6 0 W 5 0 H'FEB1 4 0 W 3 0 W 2 0 W Port 2 1 0 W 0 0 W P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : Read/Write : W Specify input or output for individual port 2 pins P3DDR—Port 3 Data Direction Register Bit : 7 — Initial value : Read/Write : — 6 — — 5 0 H'FEB2 4 0 W 3 0 W 2 0 W Port 3 1 0 W 0 0 W P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR W Undefined Undefined Specify input or output for individual port 3 pins P5DDR—Port 5 Data Direction Register Bit : 7 — Read/Write : — 6 — — 5 — — H'FEB4 4 — — 3 0 W 2 0 W 1 0 W Port 5 0 0 W P53DDR P52DDR P51DDR P50DDR Initial value : Undefined Undefined Undefined Undefined Specify input or output for individual port 5 pins Rev.6.00 Oct.28.2004 page 865 of 1016 REJ09B0138-0600H P6DDR—Port 6 Data Direction Register Bit : 7 0 W 6 0 W 5 0 W H'FEB5 4 0 W 3 0 W 2 0 W Port 6 1 0 W 0 0 W P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value : Read/Write : Specify input or output for individual port 6 pins PADDR—Port A Data Direction Register Bit Initial value Read/Write : : : 7 0 W 6 0 W H'FEB9 5 0 W 4 0 W 3 0 W 2 0 W Port A 1 0 W 0 0 W PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Specify input or output for individual port A pins PBDDR—Port B Data Direction Register H'FEBA Port B [On-chip ROM version Only] 4 0 3 0 W 2 0 W 1 0 W 0 0 W Bit Initial value Read/Write : : : 7 0 W 6 0 W 5 0 W PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR W Specify input or output for individual port B pins PCDDR—Port C Data Direction Register H'FEBB Port C [On-chip ROM version Only] 4 0 3 0 W 2 0 W 1 0 W 0 0 W Bit Initial value Read/Write : : : 7 0 W 6 0 W 5 0 W PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR W Specify input or output for individual port C pins Rev.6.00 Oct.28.2004 page 866 of 1016 REJ09B0138-0600H PDDDR—Port D Data Direction Register H'FEBC Port D [On-chip ROM version Only] 3 0 W 2 0 W 1 0 W 0 0 W Bit : 7 0 W 6 0 W 5 0 W 4 0 W PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : Read/Write : Specify input or output for individual port D pins PEDDR—Port E Data Direction Register Bit : 7 0 W 6 0 W 5 0 W H'FEBD 4 0 W 3 0 W 2 0 W Port E 1 0 W 0 0 W PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : Read/Write : Specify input or output for individual port E pins PFDDR—Port F Data Direction Register Bit Modes 4 to 6 Initial value Read/Write Mode 7 Initial value Read/Write : : 0 W 0 W : : 1 W 0 W : 7 6 H'FEBE 5 4 3 2 Port F 1 0 PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Specify input or output for individual port F pins PGDDR—Port G Data Direction Register Bit Modes 4, 5 Initial value Read/Write Modes 6, 7 Initial value Read/Write : 7 — 6 — H'FEBF 5 — 4 3 2 Port G 1 0 PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR 1 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W : Undefined Undefined Undefined : — — — : Undefined Undefined Undefined : — — — Specify input or output for individual port G pins Rev.6.00 Oct.28.2004 page 867 of 1016 REJ09B0138-0600H IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK — — — — — — — — — — — Interrupt Priority Register A Interrupt Priority Register B Interrupt Priority Register C Interrupt Priority Register D Interrupt Priority Register E Interrupt Priority Register F Interrupt Priority Register G Interrupt Priority Register H Interrupt Priority Register I Interrupt Priority Register J Interrupt Priority Register K Bit : 7 — Initial value : Read/Write : 0 — 6 IPR6 1 R/W 5 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE 4 IPR4 1 R/W 3 — 0 — Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller 2 IPR2 1 R/W 1 IPR1 1 R/W 0 IPR0 1 R/W IPR5 1 R/W Set priority (levels 7 to 0) for interrupt sources Correspondence between Interrupt Sources and IPR Settings Bits Register 6 to 4 IPRA IPRB IRQ0 IRQ2 IRQ3 IPRC IRQ6 IRQ7 IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK WDT —* TPU channel 0 TPU channel 2 TPU channel 4 8-bit timer channel 0 DMAC SCI channel 1 Refresh timer A/D converter TPU channel 1 TPU channel 3 TPU channel 5 8-bit timer channel 1 SCI channel 0 SCI channel 2 IRQ1 IRQ4 IRQ5 DTC 2 to 0 Note: * Reserved bits. These bits cannot be modified and are always read as 1. Rev.6.00 Oct.28.2004 page 868 of 1016 REJ09B0138-0600H ABWCR—Bus Width Control Register Bit : 7 ABW7 Modes 5 to 7 Initial value : R/W Mode 4 Initial value : Read/Write : 0 R/W 0 R/W 0 : 1 R/W 1 R/W 1 6 ABW6 5 H'FED0 4 ABW4 1 R/W 0 R/W 3 ABW3 1 R/W 0 R/W Bus Controller 2 ABW2 1 R/W 0 R/W 1 ABW1 1 R/W 0 R/W 0 ABW0 1 R/W 0 R/W ABW5 R/W R/W Area 7 to 0 Bus Width Control 0 1 Area n is designated for 16-bit access Area n is designated for 8-bit access (n = 7 to 0) Note: * Modes 6 and 7 are provided in the On-chip ROM version only. ASTCR—Access State Control Register Bit : 7 AST7 Initial value : Read/Write : 1 R/W 6 AST6 1 R/W 5 H'FED1 4 AST4 1 R/W 3 AST3 1 R/W Bus Controller 2 AST2 1 R/W 1 AST1 1 R/W 0 AST0 1 R/W AST5 1 R/W Area 7 to 0 Access State Control 0 Area n is designated for 2-state access Wait state insertion in area n external space is disabled 1 Area n is designated for 3-state access Wait state insertion in area n external space is enabled (n = 7 to 0) Rev.6.00 Oct.28.2004 page 869 of 1016 REJ09B0138-0600H WCRH—Wait Control Register H Bit : 7 W71 Initial value : Read/Write : 1 R/W 6 W70 1 R/W 5 W61 1 R/W H'FED2 4 W60 1 R/W 3 W51 1 R/W 2 W50 1 R/W Bus Controller 1 W41 1 R/W 0 W40 1 R/W Area 4 Wait Control 0 0 1 1 0 1 Area 5 Wait Control 0 0 1 1 0 1 Area 6 Wait Control 0 0 1 1 0 1 Area 7 Wait Control 0 0 1 1 0 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Rev.6.00 Oct.28.2004 page 870 of 1016 REJ09B0138-0600H WCRL—Wait Control Register L Bit : 7 W31 Initial value : Read/Write : 1 R/W 6 W30 1 R/W 5 W21 1 R/W H'FED3 4 W20 1 R/W 3 W11 1 R/W 2 W10 1 R/W Bus Controller 1 W01 1 R/W 0 W00 1 R/W Area 0 Wait Control 0 0 1 1 0 1 Area 1 Wait Control 0 0 1 1 0 1 Area 2 Wait Control 0 0 1 1 0 1 Area 3 Wait Control 0 0 1 1 0 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Rev.6.00 Oct.28.2004 page 871 of 1016 REJ09B0138-0600H BCRH—Bus Control Register H Bit : 7 ICIS1 Initial value : Read/Write : 1 R/W 6 ICIS0 1 R/W 5 0 R/W H'FED4 4 1 R/W 3 0 R/W 2 0 R/W Bus Controller 1 RMTS1 0 R/W 0 RMTS0 0 R/W BRSTRM BRSTS1 BRSTS0 RMTS2 RAM Type Select RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2 0 0 0 1 1 0 1 1 — — Normal space Normal space Normal space DRAM space DRAM space DRAM space — Note: When areas selected in DRAM space are all 8-bit space, the PF2 pin can be used as an I/O port, BREQO, or WAIT. Burst Cycle Select 0 0 1 Max. 4 words in burst access Max. 8 words in burst access Burst Cycle Select 1 0 1 Burst cycle comprises 1 state Burst cycle comprises 2 states Area 0 Burst ROM Enable 0 1 Area 0 is basic bus interface Area 0 is burst ROM interface Idle Cycle Insert 0 0 1 Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles Idle Cycle Insert 1 0 1 Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas Rev.6.00 Oct.28.2004 page 872 of 1016 REJ09B0138-0600H BCRL—Bus Control Register L Bit : 7 BRLE Initial value : Read/Write : 0 R/W 6 BREQOE 0 R/W 5 EAE 1 R/W H'FED5 4 LCASS 1 R/W 3 DDS 1 R/W 2 — 1 R/W 1 WDBE 0 R/W Bus Controller 0 WAITE 0 R/W WAIT Pin Enable 0 1 Wait input by WAIT pin disabled Wait input by WAIT pin enabled Write Data Buffer Enable 0 1 Write data buffer function not used Write data buffer function used Reserved Only 1 should be written to this bit DACK Timing Select 0 When DMAC single address transfer is performed in DRAM/PSRAM space, full access is always executed DACK signal goes low from Tr or T1 cycle Burst access is possible when DMAC single address transfer is performed in DRAM/PSRAM space DACK signal goes low from Tc1 or T2 cycle 1 LCAS Select Write 0 to this bit when using the DRAM interface External Addresses H'010000 to H'01FFFF*1 Enable 0 1 On-chip ROM External addresses (in external expansion mode) or reserved area*2 (in single-chip mode) Notes: 1. External addresses H'010000 to H'01FFFF for the H8S/2357 External addresses H'010000 to H'03FFFF for the H8S/2398 2. Do not access a reserved area. BREQO Pin Enable 0 1 BREQO output disabled BREQO output enabled Bus Release Enable 0 1 External bus release is disabled External bus release is enabled Rev.6.00 Oct.28.2004 page 873 of 1016 REJ09B0138-0600H MCR—Memory Control Register Bit : 7 TPC Initial value : Read/Write : 0 R/W 6 BE 0 R/W 5 RCDM 0 R/W H'FED6 4 CW2 0 R/W 3 MXC1 0 R/W 2 MXC0 0 R/W 1 Bus Controller 0 RLW0 0 R/W RLW1 0 R/W Refresh Cycle Wait Control 0 0 1 1 0 1 Multiplex Shift Count 0 0 1 1 0 1 2-CAS Method Select 0 1 16-bit DRAM space selected 8-bit DRAM space selected 8-bit shift 9-bit shift 10-bit shift — No wait state inserted 1 wait state inserted 2 wait states inserted 3 wait states inserted RAS/CS Down Mode 0 1 DRAM interface: RAS up mode selected DRAM interface: RAS down mode selected Burst Access Enable 0 1 TP Cycle Control 0 1 1-state precharge cycle is inserted 2-state precharge cycle is inserted Burst disabled (always full access) For DRAM space access, access in fast page mode Rev.6.00 Oct.28.2004 page 874 of 1016 REJ09B0138-0600H DRAMCR—DRAM Control Register Bit : 7 RFSHE Initial value : Read/Write : 0 R/W 6 RCW 0 R/W 5 RMODE 0 R/W H'FED7 4 CMF 0 R/W 3 CMIE 0 R/W 2 CKS2 0 R/W Bus Controller 1 CKS1 0 R/W 0 CKS0 0 R/W Refresh Counter Clock Select 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Count operation disabled Count uses ø/2 Count uses ø/8 Count uses ø/32 Count uses ø/128 Count uses ø/512 Count uses ø/2048 Count uses ø/4096 Compare Match Interrupt Enable 0 1 Interrupt request (CMI) by CMF flag disabled Interrupt request (CMI) by CMF flag enabled Compare Match Flag 0 [Clearing condition] Cleared by reading the CMF flag when CMF = 1, then writing 0 to the CMF flag [Setting condition] Set when RTCNT = RTCOR 1 Refresh Mode 0 1 RAS-CAS Wait 0 1 Wait state insertion in CAS-before-RAS refreshing disabled RAS falls in TRr cycle One wait state inserted in CAS-before-RAS refreshing RAS falls in TRc1 cycle DRAM interface: CAS-before-RAS refreshing used Self-refreshing used Refresh Control 0 1 Refresh control is not performed Refresh control is performed RTCNT—Refresh Timer Counter Bit : 7 0 R/W 6 0 R/W H'FED8 5 0 R/W 4 0 R/W 3 0 R/W Bus Controller 2 0 R/W 1 0 R/W 0 0 R/W Initial value : Read/Write : Internal clock count value Rev.6.00 Oct.28.2004 page 875 of 1016 REJ09B0138-0600H RTCOR—Refresh Time Constant Register Bit : 7 1 R/W 6 1 R/W H'FED9 5 1 R/W 4 1 R/W 3 1 R/W Bus Controller 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Sets the period for compare match operations with RTCNT RAMER—RAM Emulation Register H'FEDB Bus Controller [for H8S/2398F-ZTAT Only] 4 — 0 — 3 RAMS 0 R/W 2 RAM2 0 R/W 1 RAM1 0 R/W 0 RAM0 0 R/W Bit : 7 — 0 — 6 — 0 — 5 — 0 — Initial value : Read/Write : RAM Select, Flash Memory Area Select RAMS RAM2 RAM1 RAM0 0 1 1 1 1 1 1 1 1 × 0 0 0 0 1 1 1 1 × 0 0 1 1 0 0 1 1 × 0 1 0 1 0 1 0 1 RAM Area H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF Block Name EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes) ×: Don’t care H'FFDC00 to H'FFEBFF RAM area of 4 kbytes Rev.6.00 Oct.28.2004 page 876 of 1016 REJ09B0138-0600H RAMER—RAM Emulation Register H'FEDB Bus Controller (for H8S/2357F-ZTAT only) 3 — 0 — 2 RAMS 0 R/W 1 RAM1 0 R/W 0 RAM0 0 R/W Bit : 7 — 0 — 6 — 0 — 5 — 0 — 4 — 0 — Initial value : Read/Write : RAM Select, Flash Memory Area RAMS RAM1 RAM0 0 1 × 0 1 × 0 1 0 1 Area H'FFDC00 to H'FFDFFF H'000000 to H'0003FF H'000400 to H'0007FF H'000800 to H'000BFF H'000C00 to H'000FFF ×: Don’t care MAR0AH—Memory Address Register 0AH MAR0AL—Memory Address Register 0AL Bit MAR0AH : : 31 — 0 — 15 * 30 — 0 — 14 * 29 — 0 — 13 * 28 — 0 — 12 * 27 — 0 — 11 * H'FEE0 H'FEE2 26 — 0 — 10 * 25 — 0 — 9 * 24 — 0 * * * * 23 22 21 20 DMAC DMAC 19 * 18 * 17 * 16 * Initial value : Read/Write : Bit MAR0AL : : — R/W R/W R/W R/W R/W R/W R/W R/W 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Specifies transfer source address IOAR0A—I/O Address Register 0A Bit IOAR0A : : * * * * * 15 14 13 12 11 H'FEE4 10 * 9 * 8 * 7 * 6 * 5 * 4 * DMAC 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used Rev.6.00 Oct.28.2004 page 877 of 1016 REJ09B0138-0600H ETCR0A—Transfer Count Register 0A Bit ETCR0A : : * * * * * 15 14 13 12 11 H'FEE6 10 * 9 * 8 * 7 * 6 * 5 * 4 * DMAC 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Sequential mode Idle mode Normal mode Repeat mode Block transfer mode Transfer counter Transfer number storage register Block size storage register Transfer counter Block size counter * : Undefined MAR0BH—Memory Address Register 0BH MAR0BL—Memory Address Register 0BL Bit MAR0BH : : 31 — 0 — 15 * 30 — 0 — 14 * 29 — 0 — 13 * 28 — 0 — 12 * 27 — 0 — 11 * H'FEE8 H'FEEA 26 — 0 — 10 * 25 — 0 — 9 * 24 — 0 * * * * 23 22 21 20 DMAC DMAC 19 * 18 * 17 * 16 * Initial value : Read/Write : Bit MAR0BL : : — R/W R/W R/W R/W R/W R/W R/W R/W 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Specifies transfer destination address IOAR0B—I/O Address Register 0B Bit IOAR0B : : * * * * * 15 14 13 12 11 H'FEEC 10 * 9 * 8 * 7 * 6 * 5 * 4 * DMAC 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used Rev.6.00 Oct.28.2004 page 878 of 1016 REJ09B0138-0600H ETCR0B—Transfer Count Register 0B Bit ETCR0B : : * * * * * 15 14 13 12 11 H'FEEE 10 * 9 * 8 * 7 * 6 * 5 * 4 * DMAC 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Sequential mode and idle mode Repeat mode Transfer number storage register Block transfer mode Block transfer counter * : Undefined Note: Not used in normal mode. Transfer counter Transfer counter MAR1AH—Memory Address Register 1AH MAR1AL—Memory Address Register 1AL Bit MAR1AH : : 31 — 0 — 15 * 30 — 0 — 14 * 29 — 0 — 13 * 28 — 0 — 12 * 27 — 0 — 11 * H'FEF0 H'FEF2 26 — 0 — 10 * 25 — 0 — 9 * 24 — 0 * * * * 23 22 21 20 DMAC DMAC 19 * 18 * 17 * 16 * Initial value : Read/Write : Bit MAR1AL : : — R/W R/W R/W R/W R/W R/W R/W R/W 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Specifies transfer source address IOAR1A—I/O Address Register 1A Bit IOAR1A : : * * * * * 15 14 13 12 11 H'FEF4 10 * 9 * 8 * 7 * 6 * 5 * 4 * DMAC 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used Rev.6.00 Oct.28.2004 page 879 of 1016 REJ09B0138-0600H ETCR1A—Transfer Count Register 1A Bit ETCR1A : : * * * * 15 14 13 12 H'FEF6 11 * 10 * 9 * 8 * 7 * 6 * 5 * 4 * DMAC 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Sequential mode Idle mode Normal mode Repeat mode Transfer number storage register Block transfer mode Block size storage register Block size counter * : Undefined Transfer counter Transfer counter MAR1BH — Memory Address Register 1BH MAR1BL — Memory Address Register 1BL Bit MAR1BH : : 31 — 0 — 15 * 30 — 0 — 14 * 29 — 0 — 13 * 28 — 0 — 12 * 27 — 0 — 11 * H'FEF8 H'FEFA 26 — 0 — 10 * 25 — 0 — 9 * 24 — 0 * * * * 23 22 21 20 DMAC DMAC 19 * 18 * 17 * 16 * Initial value : Read/Write : Bit MAR1BL : : — R/W R/W R/W R/W R/W R/W R/W R/W 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Specifies transfer destination address Rev.6.00 Oct.28.2004 page 880 of 1016 REJ09B0138-0600H IOAR1B—I/O Address Register 1B Bit IOAR1B : : * * * * * 15 14 13 12 11 H'FEFC 10 * 9 * 8 * 7 * 6 * 5 * 4 * DMAC 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used ETCR1B—Transfer Count Register 1B Bit ETCR1B : : * * * * 15 14 13 12 H'FEFE 11 * 10 * 9 * 8 * 7 * 6 * 5 * 4 * DMAC 3 * 2 * 1 * 0 * Initial value : Read/Write : Sequential mode and idle mode Repeat mode R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter Transfer number storage register Transfer counter Block transfer mode Block transfer counter * : Undefined Note: Not used in normal mode. Rev.6.00 Oct.28.2004 page 881 of 1016 REJ09B0138-0600H DMAWER—DMA Write Enable Register Bit : 7 — 0 — 6 — 0 — 5 — 0 — H'FF00 4 — 0 — 3 WE1B 0 R/W 2 WE1A 0 R/W DMAC 1 WE0B 0 R/W 0 WE0A 0 R/W DMAWER : Initial value : Read/Write : Write Enable 0A 0 Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled 1 Write Enable 0B 0 Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are disabled Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are enabled 1 Write Enable 1A 0 1 Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are disabled Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are enabled Write Enable 1B 0 1 Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are disabled Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are enabled Rev.6.00 Oct.28.2004 page 882 of 1016 REJ09B0138-0600H DMATCR—DMA Terminal Control Register Bit DMATCR : : 7 — 0 — 6 — 0 — 5 H'FF01 4 TEE0 0 R/W 3 — 0 — 2 — 0 — DMAC 1 — 0 — 0 — 0 — TEE1 0 R/W Initial value : Read/Write : Transfer End Enable 0 0 1 TEND0 pin output disabled TEND0 pin output enabled Transfer End Enable 1 0 1 TEND1 pin output disabled TEND1 pin output enabled DMACR0A—DMA Control Register 0A DMACR0B—DMA Control Register 0B DMACR1A—DMA Control Register 1A DMACR1B—DMA Control Register 1B Full address mode Bit DMACRA : : 15 DTSZ 0 R/W 14 SAID 0 R/W 13 SAIDE 0 R/W H'FF02 H'FF03 H'FF04 H'FF05 DMAC DMAC DMAC DMAC 12 BLKDIR 0 R/W 11 BLKE 0 R/W 10 — 0 R/W 9 — 0 R/W 8 — 0 R/W Initial value : Read/Write : Block Direction/Block Enable 0 0 1 1 0 1 Reserved Only 0 should be written to this bit. Transfer in normal mode Transfer in block transfer mode, destination side is block area Transfer in normal mode Transfer in block transfer mode, source side is block area Source Address Increment/Decrement 0 0 1 1 0 1 Data Transfer Size 0 1 Byte-size transfer Word-size transfer MARA is fixed MARA is incremented after a data transfer MARA is fixed MARA is decremented after a data transfer Rev.6.00 Oct.28.2004 page 883 of 1016 REJ09B0138-0600H Full address mode (cont) Bit DMACRB : : 7 — 0 R/W 6 DAID 0 R/W 5 DAIDE 0 R/W 4 — 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W Initial value : Read/Write : Reserved Only 0 should be written to this bit. Reserved Only 0 should be written to this bit. Data Transfer Factor DTF DTF DTF DTF 3 210 0 000 — 1 1 0 Block Transfer Mode — — Normal Mode Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input Activated by DREQ pin falling edge input Activated by DREQ pin low-level input Activated by SCI channel 0 transmission data empty interrupt Activated by SCI channel 0 reception data full interrupt Activated by SCI channel 1 transmission data empty interrupt Activated by SCI channel 1 reception data full interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt Activated by DREQ pin low-level input 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 — — Auto-request (cycle steal) Auto-request (burst) — — — — — — — — — — Destination Address Increment/Decrement 0 0 1 1 0 1 MARB is fixed MARB is incremented after a data transfer MARB is fixed MARB is decremented after a data transfer Rev.6.00 Oct.28.2004 page 884 of 1016 REJ09B0138-0600H Short address mode Bit DMACR : : 7 DTSZ 0 R/W 6 DTID 0 R/W 5 RPE 0 R/W 4 DTDIR 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W Initial value : Read/Write : Data Transfer Factor Channel A Data Transfer Direction 0 Dual address mode: Transfer with MAR as source address and IOAR as destination address Single address mode: Transfer with MAR as source address and DACK pin as write strobe Dual address mode: Transfer with IOAR as source address and MAR as destination address Single address mode: Transfer with DACK pin as read strobe and MAR as destination address 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 — Activated by A/D converter conversion end interrupt — — Activated by DREQ pin falling edge input Activated by DREQ pin low-level input Channel B 1 Activated by SCI channel 0 transmission data empty interrupt Activated by SCI channel 0 reception data full interrupt Activated by SCI channel 1 transmission data empty interrupt Activated by SCI channel 1 reception data full interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt — — Repeat Enable 0 1 Transfer in sequential mode Transfer in repeat mode or idle mode Data Transfer Increment/Decrement 0 1 MAR is incremented after a data transfer MAR is decremented after a data transfer Data Transfer Size 0 1 Byte-size transfer Word-size transfer Rev.6.00 Oct.28.2004 page 885 of 1016 REJ09B0138-0600H DMABCRH — DMA Band Control Register DMABCRL — DMA Band Control Register Full address mode Bit : 15 FAE1 0 R/W 14 FAE0 0 R/W 13 — 0 R/W 12 — 0 R/W H'FF06 H'FF07 DMAC DMAC 11 DTA1 0 R/W 10 — 0 R/W 9 DTA0 0 R/W 8 — 0 R/W DMABCRH : Initial value : Read/Write : Reserved Only 0 should be written to this bit. Reserved Only 0 should be written to this bit. Reserved Only 0 should be written to this bit. Channel 0 Data Transfer Acknowledge 0 1 Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled Channel 1 Data Transfer Acknowledge 0 1 Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled Channel 0 Full Address Enable 0 1 Short address mode Full address mode Channel 1 Full Address Enable 0 1 Short address mode Full address mode (Continued on next page) Rev.6.00 Oct.28.2004 page 886 of 1016 REJ09B0138-0600H Full address mode (cont) Bit : 7 DTME1 0 R/W 6 DTE1 0 R/W 5 DTME0 0 R/W 4 DTE0 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Channel 0 Data Transfer Interrupt Enable A 0 1 Transfer end interrupt disabled Transfer end interrupt enabled DMABCRL : Initial value : Read/Write : DTIE1B DTIE1A DTIE0B DTIE0A Channel 0 Data Transfer Interrupt Enable B 0 1 Transfer suspended interrupt disabled Transfer suspended interrupt enabled Channel 1 Data Transfer Interrupt Enable A 0 1 Transfer end interrupt disabled Transfer end interrupt enabled Channel 1 Data Transfer Interrupt Enable B 0 1 Transfer suspended interrupt disabled Transfer suspended interrupt enabled Channel 0 Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled Channel 0 Data Transfer Master Enable 0 1 Data transfer disabled. In burst mode, cleared to 0 by an NMI interrupt Data transfer enabled Channel 1 Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled Channel 1 Data Transfer Master Enable 0 1 Data transfer disabled. In burst mode, cleared to 0 by an NMI interrupt Data transfer enabled (Continued on next page) Rev.6.00 Oct.28.2004 page 887 of 1016 REJ09B0138-0600H Short address mode Bit : 15 FAE1 0 R/W 14 FAE0 0 R/W 13 SAE1 0 R/W 12 SAE0 0 R/W 11 DTA1B 0 R/W 10 DTA1A 0 R/W 9 DTA0B 0 R/W 8 DTA0A 0 R/W DMABCRH : Initial value : Read/Write : Channel 0A Data Transfer Acknowledge 0 Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled 1 Channel 0B Data Transfer Acknowledge 0 1 Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled Channel 1A Data Transfer Acknowledge 0 1 Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled Channel 1B Data Transfer Acknowledge 0 1 Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled Channel 0B Single Address Enable 0 1 Transfer in dual address mode Transfer in single address mode Channel 1B Single Address Enable 0 1 Transfer in dual address mode Transfer in single address mode Channel 0 Full Address Enable 0 1 Short address mode Full address mode Channel 1 Full Address Enable 0 1 Short address mode Full address mode (Continued on next page) Rev.6.00 Oct.28.2004 page 888 of 1016 REJ09B0138-0600H Short address mode (cont) Bit : 7 DTE1B 0 R/W 6 DTE1A 0 R/W 5 DTE0B 0 R/W 4 DTE0A 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Channel 0A Data Transfer Interrupt Enable 0 1 Transfer end interrupt disabled Transfer end interrupt enabled DMABCRL : Initial value : Read/Write : DTIE1B DTIE1A DTIE0B DTIE0A Channel 0B Data Transfer Interrupt Enable 0 1 Transfer end interrupt disabled Transfer end interrupt enabled Channel 1A Data Transfer Interrupt Enable 0 1 Transfer end interrupt disabled Transfer end interrupt enabled Channel 1B Data Transfer Interrupt Enable 0 1 Transfer end interrupt disabled Transfer end interrupt enabled Channel 0A Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled Channel 0B Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled Channel 1A Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled Channel 1B Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled Rev.6.00 Oct.28.2004 page 889 of 1016 REJ09B0138-0600H ISCRH — IRQ Sense Control Register H ISCRL — IRQ Sense Control Register L ISCRH Bit : 15 0 R/W 14 0 R/W H'FF2C H'FF2D Interrupt Controller Interrupt Controller 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : Read/Write : IRQ7 to IRQ4 Sense Control ISCRL Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : Read/Write : IRQ3 to IRQ0 Sense Control IRQnSCB IRQnSCA 0 0 1 1 0 1 Interrupt Request Generation IRQn input low level Falling edge of IRQn input Rising edge of IRQn input Both falling and rising edges of IRQn input (n = 7 to 0) IER—IRQ Enable Register Bit : 7 IRQ7E Initial value : Read/Write : 0 R/W 6 IRQ6E 0 R/W 5 H'FF2E 4 IRQ4E 0 R/W 3 Interrupt Controller 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W IRQ5E 0 R/W IRQ3E 0 R/W IRQn Enable 0 1 IRQn interrupt disabled IRQn interrupt enabled (n = 7 to 0) Rev.6.00 Oct.28.2004 page 890 of 1016 REJ09B0138-0600H ISR—IRQ Status Register Bit : 7 IRQ7F Initial value : Read/Write : 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 H'FF2F 4 IRQ4F 0 R/(W)* 3 Interrupt Controller 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* IRQ5F 0 R/(W)* IRQ3F 0 R/(W)* Indicate the status of IRQ7 to IRQ0 interrupt requests Note: * Can only be written with 0 for flag clearing. DTCERA to DTCERF—DTC Enable Registers Bit : 7 DTCE7 Initial value : Read/Write : 0 R/W 6 DTCE6 0 R/W 5 H'FF30 to H'FF35 4 DTCE4 0 R/W 3 DTCE3 0 R/W 2 DTCE2 0 R/W DTC 1 DTCE1 0 R/W 0 DTCE0 0 R/W DTCE5 0 R/W DTC Activation Enable 0 DTC activation by this interrupt is disabled [Clearing conditions] • When the DISEL bit is 1 and data transfer has ended • When the specified number of transfers have ended DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended 1 Correspondence between Interrupt Sources and DTCER Bits Register DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF 7 IRQ0 — TGI2A — DMTEND0A RXI2 6 IRQ1 ADI TGI2B — DMTEND0B TXI2 5 IRQ2 TGI0A TGI3A TGI5A DMTEND1A — 4 IRQ3 TGI0B TGI3B TGI5B 3 IRQ4 TGI0C TGI3C CMIA0 2 IRQ5 TGI0D TGI3D CMIB0 TXI0 — 1 IRQ6 TGI1A TGI4A CMIA1 RXI1 — 0 IRQ7 TGI1B TGI4B CMIB1 TXI1 — DMTEND1B RXI0 — — Rev.6.00 Oct.28.2004 page 891 of 1016 REJ09B0138-0600H DTVECR—DTC Vector Register Bit : 7 0 R/(W)* 6 0 R/W 5 0 R/W H'FF37 4 0 R/W 3 0 R/W 2 0 R/W 1 0 DTC 0 0 R/W SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : Read/Write : R/W Sets vector number for DTC software activation DTC Software Activation Enable 0 DTC software activation is disabled [Clearing condition] When the DISEL bit is 0 and the specified number of transfers have not ended DTC software activation is enabled [Holding conditions] • When the DISEL bit is 1 and data transfer has ended • When the specified number of transfers have ended • During data transfer due to software activation 1 Note: * A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1 is read. Rev.6.00 Oct.28.2004 page 892 of 1016 REJ09B0138-0600H SBYCR—Standby Control Register Bit : 7 SSBY Initial value : Read/Write : 0 R/W 6 STS2 0 R/W 5 H'FF38 4 STS0 0 R/W 3 OPE 1 R/W Power-Down State 2 — 0 — 1 — 0 — 0 — 0 R/W STS1 0 R/W Reserved Only 0 should be written to this bit Output Port Enable 0 In software standby mode, address bus and bus control signals are high-impedance In software standby mode, address bus and bus control signals retain output state 1 Standby Timer Select 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Software Standby 0 1 Transition to sleep mode after execution of SLEEP instruction Transition to software standby mode after execution of SLEEP instruction Standby time = 8,192 states Standby time = 16,384 states Standby time = 32,768 states Standby time = 65,536 states Standby time = 131,072 states Standby time = 262,144 states Reserved Standby time = 16 states* Note: * Not available in the F-ZTAT version. Rev.6.00 Oct.28.2004 page 893 of 1016 REJ09B0138-0600H SYSCR—System Control Register Bit : 7 — Initial value : Read/Write : 0 R/W 6 — 0 — 5 H'FF39 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 — 0 —/(R/W) 1 — 0 R/W MCU 0 RAME 1 R/W INTM1 0 R/W RAM Enable 0 1 On-chip RAM disabled On-chip RAM enabled Reserved Only 0 should be written to this bit Reserved for H8S/2398, H8S/2394, H8S/2392, and H8S/2390. Only 0 should be written to this bit. NMI Input Edge Select 0 1 Falling edge Rising edge Interrupt Control Mode Selection 0 0 1 1 0 1 Interrupt control mode 0 Setting prohibited Interrupt control mode 2 Setting prohibited Reserved Only 0 should be written to this bit Rev.6.00 Oct.28.2004 page 894 of 1016 REJ09B0138-0600H SCKCR—System Clock Control Register Bit : 7 PSTOP Initial value : Read/Write : 0 R/W 6 — 0 R/W 5 — 0 —/(R/W) H'FF3A 4 — 0 — 3 — 0 — 2 Clock Pulse Generator 1 SCK1 0 R/W 0 SCK0 0 R/W SCK2 0 R/W Reserved for H8S/2398, H8S/2394, H8S/2392, and H8S/2390. Only 0 should be written to this bit. Reserved Only 0 should be written to this bit. ø Clock Output Control PSTOP 0 1 Normal Operation ø output Fixed high Bus Master Clock Select 0 0 0 1 1 0 1 1 0 0 1 1 — Bus master is in high-speed mode Medium-speed clock is ø/2 Medium-speed clock is ø/4 Medium-speed clock is ø/8 Medium-speed clock is ø/16 Medium-speed clock is ø/32 — Sleep Mode ø output Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance MDCR—Mode Control Register Bit : 7 — Initial value : Read/Write : 1 — 6 — 0 — 5 — 0 — H'FF3B 4 — 0 — 3 — 0 — 2 MDS2 —* R MCU 1 MDS1 —* R 0 MDS0 —* R Current mode pin operating mode Note: * Determined by pins MD2 to MD0 MSTPCRH — Module Stop Control Register H MSTPCRL — Module Stop Control Register L MSTPCRH Bit : 15 0 14 0 13 1 12 1 11 1 H'FF3C H'FF3D Power-Down State Power-Down State MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Specifies module stop mode 0 1 Module stop mode cleared Module stop mode set Rev.6.00 Oct.28.2004 page 895 of 1016 REJ09B0138-0600H SYSCR2—System Control Register 2 Bit : 7 — Initial value : Read/Write : 0 — 6 — 0 — H'FF42 5 — 0 — 4 — 0 — 3 FLSHE 0 R/W 2 — 0 — MCU [F-ZTAT version Only] 1 — 0 — 0 — 0 — Flash memory control register enable 0 1 Flash memory control register is not selected Flash memory control register is selected Note: SYSCR2 can only be accessed in the F-ZTAT version. In other versions, this register cannot be written to and will return an undefined value if read. Reserved Register Bit : 7 — Initial value : Read/Write : 0 — 6 — 0 — 5 H'FF44 4 — 0 — 3 — 0 — 2 — 0 — 1 — 0 — 0 — 0 — — 0 R/W Reserved Only 0 should be written to these bits Reserved Register Bit : 7 — Initial value : Read/Write : 0 R/W 6 — 0 R/W 5 H'FF45 4 — 0 R/W 3 — 1 R/W 2 — 1 R/W 1 — 1 R/W 0 — 1 R/W — 0 R/W Reserved Only 0 should be written to these bits Reserved Only 1 should be written to these bits Rev.6.00 Oct.28.2004 page 896 of 1016 REJ09B0138-0600H PCR—PPG Output Control Register Bit : 7 1 R/W 6 1 R/W 5 1 R/W H'FF46 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W PPG 0 1 R/W G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value : Read/Write : Output Trigger for Pulse Output Group 0 0 0 1 1 0 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 Output Trigger for Pulse Output Group 1 0 0 1 1 0 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 Output Trigger for Pulse Output Group 2 0 0 1 1 0 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 Output Trigger for Pulse Output Group 3 0 0 1 1 0 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 Rev.6.00 Oct.28.2004 page 897 of 1016 REJ09B0138-0600H PMR—PPG Output Mode Register Bit : 7 G3INV Initial value : Read/Write : 1 R/W 6 G2INV 1 R/W 5 H'FF47 4 G0INV 1 R/W 3 0 R/W 2 0 R/W PPG 1 0 R/W 0 0 R/W G1INV 1 R/W G3NOV G2NOV G1NOV G0NOV Pulse Output Group n Normal/Non-Overlap Operation Select 0 Normal operation in pulse output group n (output values updated at compare match A in the selected TPU channel) Non-overlapping operation in pulse output group n (independent 1 and 0 output at compare match A or B in the selected TPU channel) n=3 to 0 Pulse Output Group n Direct/Inverted Output 0 Inverted output for pulse output group n (low-level output at pin for a 1 in PODRH) Direct output for pulse output group n (high-level output at pin for a 1 in PODRH) n=3 to 0 1 1 Rev.6.00 Oct.28.2004 page 898 of 1016 REJ09B0138-0600H NDERH — Next Data Enable Registers H NDERL — Next Data Enable Registers L NDERH H'FF48 H'FF49 PPG PPG Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value : Read/Write : Pulse Output Enable/Disable 0 1 NDERL Pulse outputs PO15 to PO8 are disabled Pulse outputs PO15 to PO8 are enabled Bit : 7 NDER7 0 R/W 6 NDER6 0 R/W 5 NDER5 0 R/W 4 NDER4 0 R/W 3 NDER3 0 R/W 2 NDER2 0 R/W 1 0 R/W 0 0 R/W NDER1 NDER0 Initial value : Read/Write : Pulse Output Enable/Disable 0 1 Pulse outputs PO7 to PO0 are disabled Pulse outputs PO7 to PO0 are enabled Rev.6.00 Oct.28.2004 page 899 of 1016 REJ09B0138-0600H PODRH — Output Data Register H PODRL — Output Data Register L PODRH H'FF4A H'FF4B PPG PPG Bit : 7 POD15 0 R/(W)* 6 POD14 0 R/(W)* 5 POD13 0 R/(W)* 4 POD12 0 R/(W)* 3 POD11 0 R/(W)* 2 POD10 0 R/(W)* 1 POD9 0 R/(W)* 0 POD8 0 R/(W)* Initial value : Read/Write : Stores output data for use in pulse output PODRL Bit : 7 POD7 0 R/(W)* 6 POD6 0 R/(W)* 5 POD5 0 R/(W)* 4 POD4 0 R/(W)* 3 POD3 0 R/(W)* 2 POD2 0 R/(W)* 1 POD1 0 R/(W)* 0 POD0 0 R/(W)* Initial value : Read/Write : Stores output data for use in pulse output Note: * A bit that has been set for pulse output by NDER is read-only. Rev.6.00 Oct.28.2004 page 900 of 1016 REJ09B0138-0600H NDRH—Next Data Register H H'FF4C (FF4E) PPG (1) When pulse output group output triggers are the same (a) Address: H'FF4C Bit : 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Initial value : Read/Write : Stores the next data for pulse output groups 3 and 2 (b) Address: H'FF4E Bit : 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Initial value : Read/Write : (2) When pulse output group output triggers are different (a) Address: H'FF4C Bit : 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Initial value : Read/Write : Stores the next data for pulse output group 3 (b) Address: H'FF4E Bit : 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Initial value : Read/Write : Stores the next data for pulse output group 2 Rev.6.00 Oct.28.2004 page 901 of 1016 REJ09B0138-0600H NDRL—Next Data Register L H'FF4D (FF4F) PPG (1) When pulse output group output triggers are the same (a) Address: H'FF4D Bit : 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Initial value : Read/Write : Stores the next data for pulse output groups 1 and 0 (b) Address: H'FF4F Bit : 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Initial value : Read/Write : (2) When pulse output group output triggers are different (a) Address: H'FF4D Bit : 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 — 1 — 2 — 1 — 1 — 1 — 0 — 1 — Initial value : Read/Write : Stores the next data for pulse output group 1 (b) Address: H'FF4F Bit : 7 — 1 — 6 — 1 — 5 — 1 — 4 — 1 — 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Initial value : Read/Write : Stores the next data for pulse output group 0 Rev.6.00 Oct.28.2004 page 902 of 1016 REJ09B0138-0600H PORT1—Port 1 Register Bit : 7 P17 Initial value : Read/Write : —* R 6 P16 —* R 5 H'FF50 4 P14 —* R 3 P13 —* R 2 P12 —* R Port 1 1 P11 —* R 0 P10 —* R P15 —* R State of port 1 pins Note: * Determined by the state of pins P17 to P10. PORT2—Port 2 Register Bit : 7 P27 Initial value : Read/Write : —* R 6 P26 —* R 5 H'FF51 4 P24 —* R 3 P23 —* R 2 P22 —* R Port 2 1 P21 —* R 0 P20 —* R P25 —* R State of port 2 pins Note: * Determined by the state of pins P27 to P20. PORT3—Port 3 Register Bit : 7 — Read/Write : — 6 — — 5 H'FF52 4 P34 —* R 3 P33 —* R 2 P32 —* R Port 3 1 P31 —* R 0 P30 —* R P35 —* R Initial value : Undefined Undefined State of port 3 pins Note: * Determined by the state of pins P35 to P30. PORT4—Port 4 Register Bit : 7 P47 Initial value : Read/Write : —* R 6 P46 —* R 5 H'FF53 4 P44 —* R 3 P43 —* R 2 P42 —* R Port 4 1 P41 —* R 0 P40 —* R P45 —* R State of port 4 pins Note: * Determined by the state of pins P47 to P40. Rev.6.00 Oct.28.2004 page 903 of 1016 REJ09B0138-0600H PORT5—Port 5 Register Bit : 7 — Read/Write : — 6 — — 5 — — H'FF54 4 — — 3 P53 —* R 2 P52 —* R Port 5 1 P51 —* R 0 P50 —* R Initial value : Undefined Undefined Undefined Undefined State of port 5 pins Note: * Determined by the state of pins P53 to P50. PORT6—Port 6 Register Bit : 7 P67 Initial value : Read/Write : —* R 6 P66 —* R 5 H'FF55 4 P64 —* R 3 P63 —* R 2 P62 —* R Port 6 1 P61 —* R 0 P60 —* R P65 —* R State of port 6 pins Note: * Determined by the state of pins P67 to P60. PORTA—Port A Register Bit : 7 PA7 Initial value : Read/Write : —* R 6 PA6 —* R 5 H'FF59 4 PA4 —* R 3 PA3 —* R 2 PA2 —* R Port A 1 PA1 —* R 0 PA0 —* R PA5 —* R State of port A pins Note: * Determined by the state of pins PA7 to PA0. PORTB—Port B Register H'FF5A Port B [On-chip ROM version Only] 3 PB3 —* R 2 PB2 —* R 1 PB1 —* R 0 PB0 —* R Bit : 7 PB7 —* R 6 PB6 —* R 5 PB5 —* R 4 PB4 —* R Initial value : Read/Write : State of port B pins Note: * Determined by the state of pins PB7 to PB0. Rev.6.00 Oct.28.2004 page 904 of 1016 REJ09B0138-0600H PORTC—Port C Register H'FF5B Port C [On-chip ROM version Only)] 3 PC3 —* R 2 PC2 —* R 1 PC1 —* R 0 PC0 —* R Bit : 7 PC7 —* R 6 PC6 —* R 5 PC5 —* R 4 PC4 —* R Initial value : Read/Write : State of port C pins Note: * Determined by the state of pins PC7 to PC0. PORTD—Port D Register H'FF5C Port D [On-chip ROM version Only] 3 PD3 —* R 2 PD2 —* R 1 PD1 —* R 0 PD0 —* R Bit : 7 PD7 —* R 6 PD6 —* R 5 PD5 —* R 4 PD4 —* R Initial value : Read/Write : State of port D pins Note: * Determined by the state of pins PD7 to PD0. PORTE—Port E Register Bit : 7 PE7 Initial value : Read/Write : —* R 6 PE6 —* R 5 H'FF5D 4 PE4 —* R 3 PE3 —* R 2 PE2 —* R Port E 1 PE1 —* R 0 PE0 —* R PE5 —* R State of port E pins Note: * Determined by the state of pins PE7 to PE0. PORTF—Port F Register Bit : 7 PF7 Initial value : Read/Write : —* R 6 PF6 —* R 5 H'FF5E 4 PF4 —* R 3 PF3 —* R 2 PF2 —* R Port F 1 PF1 —* R 0 PF0 —* R PF5 —* R State of port F pins Note: * Determined by the state of pins PF7 to PF0. Rev.6.00 Oct.28.2004 page 905 of 1016 REJ09B0138-0600H PORTG—Port G Register Bit : 7 — Read/Write : — 6 — — 5 — — H'FF5F 4 PG4 —* R 3 PG3 —* R 2 PG2 —* R Port G 1 PG1 —* R 0 PG0 —* R Initial value : Undefined Undefined Undefined State of port G pins Note: * Determined by the state of pins PG4 to PG0. P1DR—Port 1 Data Register Bit : 7 P17DR Initial value : Read/Write : 0 R/W 6 P16DR 0 R/W 5 H'FF60 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W Port 1 1 P11DR 0 R/W 0 P10DR 0 R/W P15DR 0 R/W Stores output data for port 1 pins (P17 to P10) P2DR—Port 2 Data Register Bit : 7 P27DR Initial value : Read/Write : 0 R/W 6 P26DR 0 R/W 5 H'FF61 4 P24DR 0 R/W 3 P23DR 0 R/W 2 P22DR 0 R/W Port 2 1 P21DR 0 R/W 0 P20DR 0 R/W P25DR 0 R/W Stores output data for port 2 pins (P27 to P20) P3DR—Port 3 Data Register Bit : 7 — Read/Write : — 6 — — 5 H'FF62 4 P34DR 0 R/W 3 P33DR 0 R/W 2 P32DR 0 R/W Port 3 1 P31DR 0 R/W 0 P30DR 0 R/W P35DR 0 R/W Initial value : Undefined Undefined Stores output data for port 3 pins (P35 to P30) Rev.6.00 Oct.28.2004 page 906 of 1016 REJ09B0138-0600H P5DR—Port 5 Data Register Bit : 7 — Read/Write : — 6 — — 5 — — H'FF64 4 — — 3 P53DR 0 R/W 2 P52DR 0 R/W Port 5 1 P51DR 0 R/W 0 P50DR 0 R/W Initial value : Undefined Undefined Undefined Undefined Stores output data for port 5 pins (P53 to P50) P6DR—Port 6 Data Register Bit : 7 P67DR Initial value : Read/Write : 0 R/W 6 P66DR 0 R/W 5 H'FF65 4 P64DR 0 R/W 3 P63DR 0 R/W 2 P62DR 0 R/W Port 6 1 P61DR 0 R/W 0 P60DR 0 R/W P65DR 0 R/W Stores output data for port 6 pins (P67 to P60) PADR—Port A Data Register Bit : 7 PA7DR Initial value : Read/Write : 0 R/W 6 PA6DR 0 R/W 5 H'FF69 4 PA4DR 0 R/W 3 PA3DR 0 R/W 2 PA2DR 0 R/W Port A 1 PA1DR 0 R/W 0 PA0DR 0 R/W PA5DR 0 R/W Stores output data for port A pins (PA7 to PA0) PBDR—Port B Data Register Bit : 7 PB7DR Initial value : Read/Write : 0 R/W 6 PB6DR 0 R/W 5 H'FF6A 4 PB4DR 0 R/W 3 PB3DR 0 R/W 2 PB2DR 0 R/W Port B 1 PB1DR 0 R/W 0 PB0DR 0 R/W PB5DR 0 R/W Stores output data for port B pins (PB7 to PB0) Rev.6.00 Oct.28.2004 page 907 of 1016 REJ09B0138-0600H PCDR—Port C Data Register Bit : 7 PC7DR Initial value : Read/Write : 0 R/W 6 PC6DR 0 R/W 5 H'FF6B 4 PC4DR 0 R/W 3 PC3DR 0 R/W 2 PC2DR 0 R/W Port C 1 0 R/W 0 0 R/W PC5DR 0 R/W PC1DR PC0DR Stores output data for port C pins (PC7 to PC0) PDDR—Port D Data Register Bit : 7 PD7DR Initial value : Read/Write : 0 R/W 6 PD6DR 0 R/W 5 H'FF6C 4 PD4DR 0 R/W 3 PD3DR 0 R/W 2 PD2DR 0 R/W Port D 1 PD1DR 0 R/W 0 PD0DR 0 R/W PD5DR 0 R/W Stores output data for port D pins (PD7 to PD0) PEDR—Port E Data Register Bit : 7 PE7DR Initial value : Read/Write : 0 R/W 6 PE6DR 0 R/W 5 H'FF6D 4 PE4DR 0 R/W 3 PE3DR 0 R/W 2 PE2DR 0 R/W Port E 1 PE1DR 0 R/W 0 PE0DR 0 R/W PE5DR 0 R/W Stores output data for port E pins (PE7 to PE0) PFDR—Port F Data Register Bit : 7 PF7DR Initial value : Read/Write : 0 R/W 6 PF6DR 0 R/W 5 H'FF6E 4 PF4DR 0 R/W 3 PF3DR 0 R/W 2 PF2DR 0 R/W Port F 1 PF1DR 0 R/W 0 PF0DR 0 R/W PF5DR 0 R/W Stores output data for port F pins (PF7 to PF0) Rev.6.00 Oct.28.2004 page 908 of 1016 REJ09B0138-0600H PGDR—Port G Data Register Bit : 7 — Read/Write : — 6 — — 5 — — H'FF6F 4 0 R/W 3 0 R/W 2 0 R/W Port G 1 0 R/W 0 0 R/W PG4DR PG3DR PG2DR PG1DR PG0DR Initial value : Undefined Undefined Undefined Stores output data for port G pins (PG4 to PG0) PAPCR—Port A MOS Pull-Up Control Register H'FF70 Port A [On-chip ROM version Only] 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial value : Read/Write : Controls the MOS input pull-up function incorporated into port A on a bit-by-bit basis Note: Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390. PBPCR—Port B MOS Pull-Up Control Register H'FF71 Port B [On-chip ROM version Only] 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : Read/Write : Controls the MOS input pull-up function incorporated into port B on a bit-by-bit basis Note: Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390. PCPCR—Port C MOS Pull-Up Control Register H'FF72 Port C [On-chip ROM version Only] 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : Read/Write : Controls the MOS input pull-up function incorporated into port C on a bit-by-bit basis Note: Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390. Rev.6.00 Oct.28.2004 page 909 of 1016 REJ09B0138-0600H PDPCR—Port D MOS Pull-Up Control Register H'FF73 Port D [On-chip ROM version Only] 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : Read/Write : Controls the MOS input pull-up function incorporated into port D on a bit-by-bit basis Note: Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390. PEPCR—Port E MOS Pull-Up Control Register H'FF74 Port E [On-chip ROM version Only] 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : Read/Write : Controls the MOS input pull-up function incorporated into port E on a bit-by-bit basis Note: Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390. P3ODR—Port 3 Open Drain Control Register Bit : 7 — Read/Write : — 6 — — 5 0 H'FF76 4 0 R/W 3 0 R/W 2 0 R/W Port 3 1 0 R/W 0 0 R/W P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR R/W Initial value : Undefined Undefined Controls the PMOS on/off status for each port 3 pin (P35 to P30) PAODR—Port A Open Drain Control Register H'FF77 Port A [On-chip ROM version Only] 4 0 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Bit : 7 0 R/W 6 0 R/W 5 0 R/W PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial value : Read/Write : R/W Controls the PMOS on/off status for each port A pin (PA7 to PA0) Note: Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390. Rev.6.00 Oct.28.2004 page 910 of 1016 REJ09B0138-0600H SMR0—Serial Mode Register 0 Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W H'FF78 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W SCI0 0 CKS0 0 R/W Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected ø clock ø/4 clock ø/16 clock ø/64 clock Character Length 0 1 8-bit data 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode Rev.6.00 Oct.28.2004 page 911 of 1016 REJ09B0138-0600H SMR0—Serial Mode Register 0 Bit : 7 GM Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W H'FF78 4 O/E 0 R/W 3 STOP 0 R/W Smart Card Interface 0 2 MP 0 R/W 1 CKS1 0 R/W Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Multiprocessor function disabled Setting prohibited ø clock ø/4 clock ø/16 clock ø/64 clock 0 CKS0 0 R/W Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Setting prohibited Parity bit addition and checking enabled Even parity Odd parity Setting prohibited 2 stop bits Character Length 0 1 GSM Mode 0 Normal Smart Card interface mode operation • TEND flag generated 12.5 etu after beginning of start bit • Clock output on/off control only GSM mode Smart Card interface mode operation • TEND flag generated 11.0 etu after beginning of start bit • Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control 8-bit data Setting prohibited 1 Note: etu: Elementary time unit (time for transfer of 1 bit) Rev.6.00 Oct.28.2004 page 912 of 1016 REJ09B0138-0600H BRR0—Bit Rate Register 0 Bit : 7 1 R/W 6 1 R/W 5 1 H'FF79 4 1 R/W SCI0, Smart Card Interface 0 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : R/W Sets the serial transfer bit rate Note: See section 14.2.8, Bit Rate Register (BRR), for details. Rev.6.00 Oct.28.2004 page 913 of 1016 REJ09B0138-0600H SCR0—Serial Control Register 0 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W H'FF7A 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W Clock Enable 0 0 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode 0 CKE0 0 R/W SCI0 Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input 1 1 0 1 Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When MPB= 1 data is received Multiprocessor interrupts enabled Receive data full interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled Rev.6.00 Oct.28.2004 page 914 of 1016 REJ09B0138-0600H SCR0—Serial Control Register 0 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W H'FF7A 3 MPIE 0 R/W 2 TEIE 0 R/W 1 Smart Card Interface 0 0 CKE0 0 R/W CKE1 0 R/W Clock Enable SCMR SMR SCR setting CKE0 SMIF C/A,GM CKE1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 SCK pin function See SCI specification 0 1 0 1 0 1 Operates as port input pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When MPB= 1 data is received Multiprocessor interrupts enabled Receive data full interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled TDR0—Transmit Data Register 0 Bit : 7 1 R/W 6 1 R/W H'FF7B 5 1 R/W 4 1 SCI0, Smart Card Interface 0 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : R/W Stores data for serial transmission Rev.6.00 Oct.28.2004 page 915 of 1016 REJ09B0138-0600H SSR0—Serial Status Register 0 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* H'FF7C 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 SCI0 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received 1 Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing Error 0 1 [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR 1 Note: * Can only be written with 0 for flag clearing. Rev.6.00 Oct.28.2004 page 916 of 1016 REJ09B0138-0600H SSR0—Serial Status Register 0 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 H'FF7C 2 TEND 1 R 1 MPB 0 R Smart Card Interface 0 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted PER 0 R/(W)* Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • On reset, or in standby mode or module stop mode • When the TE bit in SCR is 0 and the ERS bit is 0 • When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after a 1-byte serial character is sent when GM = 0 • When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after a 1-byte serial character is sent when GM = 1 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit) Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Error Signal Status 0 [Clearing conditions] • On reset, or in standby mode or module stop mode • When 0 is written to ERS after reading ERS = 1 [Setting condition] When the error signal is sampled at the low level 1 Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state. Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR 1 Note: * Can only be written with 0 for flag clearing. Rev.6.00 Oct.28.2004 page 917 of 1016 REJ09B0138-0600H RDR0—Receive Data Register 0 Bit : 7 0 R 6 0 R H'FF7D 5 0 R 4 0 R SCI0, Smart Card Interface 0 3 0 R 2 0 R 1 0 R 0 0 R Initial value : Read/Write : Stores received serial data SCMR0—Smart Card Mode Register 0 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 1 — H'FF7E 4 — 1 — 3 SCI0, Smart Card Interface 0 2 SINV 0 R/W 1 — 1 — 0 SMIF 0 R/W SDIR 0 R/W Smart Card Interface Mode Select 0 1 Smart Card interface function is disabled Smart Card interface function is enabled Smart Card Data Invert 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Rev.6.00 Oct.28.2004 page 918 of 1016 REJ09B0138-0600H SMR1—Serial Mode Register 1 Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W H'FF80 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W SCI1 0 CKS0 0 R/W Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected ø clock ø/4 clock ø/16 clock ø/64 clock Character Length 0 1 8-bit data 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode Rev.6.00 Oct.28.2004 page 919 of 1016 REJ09B0138-0600H SMR1—Serial Mode Register 1 Bit : 7 GM Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W H'FF80 4 O/E 0 R/W 3 STOP 0 R/W Smart Card Interface 1 2 MP 0 R/W 1 CKS1 0 R/W Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Multiprocessor function disabled Setting prohibited ø clock ø/4 clock ø/16 clock ø/64 clock 0 CKS0 0 R/W Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Setting prohibited Parity bit addition and checking enabled Even parity Odd parity Setting prohibited 2 stop bits Character Length 0 1 GSM Mode 0 Normal Smart Card interface mode operation • TEND flag generated 12.5 etu after beginning of start bit • Clock output on/off control only GSM mode Smart Card interface mode operation • TEND flag generated 11.0 etu after beginning of start bit • Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control 8-bit data Setting prohibited 1 Note: etu: Elementary time unit (time for transfer of 1 bit) Rev.6.00 Oct.28.2004 page 920 of 1016 REJ09B0138-0600H BRR1—Bit Rate Register 1 Bit : 7 1 R/W 6 1 R/W 5 1 R/W H'FF81 4 1 R/W SCI1, Smart Card Interface 1 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Sets the serial transfer bit rate Note: See section 14.2.8, Bit Rate Register (BRR), for details. Rev.6.00 Oct.28.2004 page 921 of 1016 REJ09B0138-0600H SCR1—Serial Control Register 1 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W H'FF82 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W Clock Enable 0 0 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode 0 CKE0 0 R/W SCI1 Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input 1 1 0 1 Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When MPB= 1 data is received Multiprocessor interrupts enabled Receive data full interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled Rev.6.00 Oct.28.2004 page 922 of 1016 REJ09B0138-0600H SCR1—Serial Control Register 1 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W H'FF82 3 MPIE 0 R/W 2 TEIE 0 R/W 1 Smart Card Interface 1 0 CKE0 0 R/W CKE1 0 R/W Clock Enable SCMR SMR SCR setting CKE0 SMIF C/A,GM CKE1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 SCK pin function See SCI specification 0 1 0 1 0 1 Operates as port input pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When MPB= 1 data is received Multiprocessor interrupts enabled Receive data full interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled TDR1—Transmit Data Register 1 Bit : 7 1 R/W 6 1 R/W 5 1 H'FF83 4 1 SCI1, Smart Card Interface 1 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : R/W R/W Stores data for serial transmission Rev.6.00 Oct.28.2004 page 923 of 1016 REJ09B0138-0600H SSR1—Serial Status Register 1 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 H'FF84 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 SCI1 PER 0 R/(W)* Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received 1 Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing Error 0 1 [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR 1 Note: * Can only be written with 0 for flag clearing. Rev.6.00 Oct.28.2004 page 924 of 1016 REJ09B0138-0600H SSR1—Serial Status Register 1 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* H'FF84 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R Smart Card Interface 1 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • On reset, or in standby mode or module stop mode • When the TE bit in SCR is 0 and the ERS bit is 0 • When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after a 1-byte serial character is sent when GM = 0 • When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after a 1-byte serial character is sent when GM = 1 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit) Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Error Signal Status 0 [Clearing conditions] • On reset, or in standby mode or module stop mode • When 0 is written to ERS after reading ERS =1 [Setting condition] When the error signal is sampled at the low level 1 Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state. Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR 1 Note: * Can only be written with 0 for flag clearing. Rev.6.00 Oct.28.2004 page 925 of 1016 REJ09B0138-0600H RDR1—Receive Data Register 1 Bit : 7 0 R 6 0 R 5 0 R H'FF85 4 0 R SCI1, Smart Card Interface 1 3 0 R 2 0 R 1 0 R 0 0 R Initial value : Read/Write : Stores received serial data SCMR1—Smart Card Mode Register 1 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 1 — H'FF86 4 — 1 — 3 SCI1, Smart Card Interface 1 2 SINV 0 R/W 1 — 1 — 0 SMIF 0 R/W SDIR 0 R/W Smart Card Interface Mode Select 0 1 Smart Card interface function is disabled Smart Card interface function is enabled Smart Card Data Invert 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Rev.6.00 Oct.28.2004 page 926 of 1016 REJ09B0138-0600H SMR2—Serial Mode Register 2 Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W H'FF88 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W SCI2 0 CKS0 0 R/W Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected ø clock ø/4 clock ø/16 clock ø/64 clock Character Length 0 1 8-bit data 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode Rev.6.00 Oct.28.2004 page 927 of 1016 REJ09B0138-0600H SMR2—Serial Mode Register 2 Bit : 7 GM Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W H'FF88 4 O/E 0 R/W 3 STOP 0 R/W Smart Card Interface 2 2 MP 0 R/W 1 CKS1 0 R/W Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Multiprocessor function disabled Setting prohibited ø clock ø/4 clock ø/16 clock ø/64 clock 0 CKS0 0 R/W Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Setting prohibited Parity bit addition and checking enabled Even parity Odd parity Setting prohibited 2 stop bits Character Length 0 1 GSM Mode 0 Normal Smart Card interface mode operation • TEND flag generated 12.5 etu after beginning of start bit • Clock output on/off control only GSM mode Smart Card interface mode operation • TEND flag generated 11.0 etu after beginning of start bit • Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control 8-bit data Setting prohibited 1 Note: etu: Elementary time unit (time for transfer of 1 bit) Rev.6.00 Oct.28.2004 page 928 of 1016 REJ09B0138-0600H BRR2—Bit Rate Register 2 Bit : 7 1 R/W 6 1 R/W 5 1 R/W H'FF89 4 1 R/W SCI2, Smart Card Interface 2 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Sets the serial transfer bit rate Note: See section 14.2.8, Bit Rate Register (BRR), for details. Rev.6.00 Oct.28.2004 page 929 of 1016 REJ09B0138-0600H SCR2—Serial Control Register 2 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W H'FF8A 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W Clock Enable 0 0 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode 0 CKE0 0 R/W SCI2 Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input 1 1 0 1 Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When MPB= 1 data is received Multiprocessor interrupts enabled Receive data full interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled Rev.6.00 Oct.28.2004 page 930 of 1016 REJ09B0138-0600H SCR2—Serial Control Register 2 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W H'FF8A 3 MPIE 0 R/W 2 TEIE 0 R/W 1 Smart Card Interface 2 0 CKE0 0 R/W CKE1 0 R/W Clock Enable SCMR SMR SCR setting CKE0 SMIF C/A,GM CKE1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 SCK pin function See SCI specification 0 1 0 1 0 1 Operates as port input pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When MPB= 1 data is received Multiprocessor interrupts enabled Receive data full interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled TDR2—Transmit Data Register 2 Bit : 7 1 R/W 6 1 R/W 5 1 H'FF8B SCI2, Smart Card Interface 2 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : R/W Stores data for serial transmission Rev.6.00 Oct.28.2004 page 931 of 1016 REJ09B0138-0600H SSR2—Serial Status Register 2 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 H'FF8C 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 SCI2 PER 0 R/(W)* Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received 1 Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing Error 0 1 [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR 1 Note: * Can only be written with 0 for flag clearing. Rev.6.00 Oct.28.2004 page 932 of 1016 REJ09B0138-0600H SSR2—Serial Status Register 2 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* H'FF8C 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R Smart Card Interface 2 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • On reset, or in standby mode or module stop mode • When the TE bit in SCR is 0 and the ERS bit is 0 • When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after a 1-byte serial character is sent when GM = 0 • When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after a 1-byte serial character is sent when GM = 1 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received 1 Note: etu: Elementary Time Unit (time for transger of 1 bit) Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Error Signal Status 0 [Clearing conditions] • On reset, or in standby mode or module stop mode • When 0 is written to ERS after reading ERS =1 [Setting condition] When the error signal is sampled at the low level 1 Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state. Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit Data Register Empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR 1 Note: * Can only be written with 0 for flag clearing. Rev.6.00 Oct.28.2004 page 933 of 1016 REJ09B0138-0600H RDR2—Receive Data Register 2 Bit : 7 0 R 6 0 R 5 0 R H'FF8D SCI2, Smart Card Interface 2 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R Initial value : Read/Write : Stores received serial data SCMR2—Smart Card Mode Register 2 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 1 — H'FF8E SCI2, Smart Card Interface 2 4 — 1 — 3 SDIR 0 R/W 2 SINV 0 R/W 1 — 1 — 0 SMIF 0 R/W Smart Card Interface Mode Select 0 1 Smart Card interface function is disabled Smart Card interface function is enabled Smart Card Data Invert 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Rev.6.00 Oct.28.2004 page 934 of 1016 REJ09B0138-0600H ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL — — — — — — — — A/D Data Register AH A/D Data Register AL A/D Data Register BH A/D Data Register BL A/D Data Register CH A/D Data Register CL A/D Data Register DH A/D Data Register DL H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter Bit : 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R 0 — 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — Initial value : Read/Write : Stores the results of A/D conversion Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD Rev.6.00 Oct.28.2004 page 935 of 1016 REJ09B0138-0600H ADCSR—A/D Control/Status Register Bit : 7 ADF Initial value : Read/Write : 0 R/(W)* 6 ADIE 0 R/W 5 H'FF98 4 SCAN 0 R/W 3 CKS 0 R/W Channel Select Group select CH2 0 Channel select CH1 0 1 1 0 1 A/D Converter 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W ADST 0 R/W Single Mode Group Mode AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 CH0 0 1 0 1 0 1 0 1 Group Select 0 1 Scan Mode 0 1 A/D Start 0 1 A/D conversion stopped • Single mode: A/D conversion is started. Cleared to 0 automatically when conversion ends • Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or transition to standby mode or module stop mode Single mode Scan mode Conversion time= 266 states (max.) Conversion time= 134 states (max.) A/D Interrupt Enable 0 A/D End Flag 0 1 A/D conversion end interrupt (ADI) request disabled A/D conversion end interrupt (ADI) request enabled [Clearing conditions] • When 0 is written to the ADF flag after reading ADF = 1 • When the DTC is activated by an ADI interrupt, and ADDR is read [Setting conditions] • Single mode: When A/D conversion ends • Scan mode: When one round of conversion has been performed on all specified channels 1 Note: * Can only be written with 0 for flag clearing. Rev.6.00 Oct.28.2004 page 936 of 1016 REJ09B0138-0600H ADCR—A/D Control Register Bit : 7 TRGS1 Initial value : Read/Write : 0 R/W 6 TRGS0 0 R/W 5 H'FF99 4 — 1 — 3 — 1 2 — 1 A/D 1 — 1 — 0 — 1 — — 1 — —/(R/W)* —/(R/W)* Timer Trigger Select TRGS1 TRGS1 0 0 1 1 0 1 Description A/D conversion start by external trigger is disabled A/D conversion start by external trigger (TPU) is enabled A/D conversion start by external trigger (8-bit timer) is enabled A/D conversion start by external trigger pin (ADTRG) is enabled Note: * Applies to the H8S/2398, H8S/2394, H8S/2392, and H8S/2390. These bits are reserved, so should always be written with 1. DADR0—D/A Data Register 0 DADR1—D/A Data Register 1 Bit : 7 0 R/W 6 0 R/W 5 0 H'FFA4 H'FFA5 4 0 R/W 3 0 R/W 2 0 R/W D/A D/A 1 0 R/W 0 0 R/W Initial value : Read/Write : R/W Stores data for D/A conversion Rev.6.00 Oct.28.2004 page 937 of 1016 REJ09B0138-0600H DACR—D/A Control Register Bit : 7 DAOE1 Initial value : Read/Write : 0 R/W 6 DAOE0 0 R/W H'FFA6 5 DAE 0 R/W 4 — 1 — 3 — 1 — 2 — 1 — 1 — 1 — D/A 0 — 1 — D/A Output Enable 0 0 1 Analog output DA0 is disabled Channel 0 D/A conversion is enabled Analog output DA0 is enabled D/A Output Enable 1 0 1 Analog output DA1 is disabled Channel 1 D/A conversion is enabled Analog output DA1 is enabled D/A Conversion Control DAOE1 0 DAOE0 0 1 DAE × 0 Description Channel 0 and 1 D/A conversion disabled Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled 1 1 0 0 Channel 0 and 1 D/A conversions enabled Channel 0 D/A conversion disabled Channel 1 D/A conversion enabled 1 1 × Channel 0 and 1 D/A conversion enabled Channel 0 and 1 D/A conversion enabled × : Don’t care DACR—Reserved Register Bit : 7 — Initial value : Read/Write : 0 R/W 6 — 0 R/W 5 H'FFAC 4 — 1 R/W 3 — 0 R/W 2 — 0 R D/A 1 — 0 R 0 — 0 R — 1 R/W Reserved, so should always be written with 0. Reserved, so should Reserved, so should always be written with 1. always be written with 0. Rev.6.00 Oct.28.2004 page 938 of 1016 REJ09B0138-0600H TCR0—Time Control Register 0 TCR1—Time Control Register 1 Bit : 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W H'FFB0 H'FFB1 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 8-Bit Timer Channel 0 8-Bit Timer Channel 1 0 CKS0 0 R/W CKS1 0 R/W Initial value : Read/Write : Clock Select 0 0 0 1 1 0 1 1 0 0 Clock input disabled Internal clock: counted at falling edge of ø/8 Internal clock: counted at falling edge of ø/64 Internal clock: counted at falling edge of ø/8192 For channel 0: Count at TCNT1 overflow signal* For channel 1: Count at TCNT0 compare match A* External clock: counted at rising edge External clock: counted at falling edge External clock: counted at both rising and falling edges 1 1 0 1 Note: * If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting. Counter Clear 0 0 1 1 0 1 Clear is disabled Clear by compare match A Clear by compare match B Clear by rising edge of external reset input Timer Overflow Interrupt Enable 0 1 OVF interrupt requests (OVI) are disabled OVF interrupt requests (OVI) are enabled Compare Match Interrupt Enable A 0 1 CMFA interrupt requests (CMIA) are disabled CMFA interrupt requests (CMIA) are enabled Compare Match Interrupt Enable B 0 1 CMFB interrupt requests (CMIB) are disabled CMFB interrupt requests (CMIB) are enabled Rev.6.00 Oct.28.2004 page 939 of 1016 REJ09B0138-0600H TCSR0—Timer Control/Status Register 0 TCSR1—Timer Control/Status Register 1 TCSR0 Bit : 7 CMFB 0 R/(W)* 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 6 CMFA 0 R/(W)* H'FFB2 H'FFB3 5 OVF 0 R/(W)* 5 OVF 0 R/(W)* 4 ADTE 0 R/W 4 — 1 — 8-Bit Timer Channel 0 8-Bit Timer Channel 1 3 OS3 0 R/W 3 OS3 0 R/W 2 OS2 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W 0 OS0 0 R/W Initial value : Read/Write : TCSR1 Bit : Initial value : Read/Write : Output Select 0 0 1 1 0 1 No change when compare match A occurs 0 is output when compare match A occurs 1 is output when compare match A occurs Output is inverted when compare match A occurs (toggle output) Output Select 0 0 1 1 0 1 No change when compare match B occurs 0 is output when compare match B occurs 1 is output when compare match B occurs Output is inverted when compare match B occurs (toggle output) A/D Trigger Enable (TCSR0 only) 0 1 A/D converter start requests by compare match A are disabled A/D converter start requests by compare match A are enabled Timer Overflow Flag 0 1 [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 to OVF [Setting condition] Set when TCNT overflows (changes from H'FF to H'00) Compare Match Flag A 0 [Clearing conditions] • Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA • When the DTC is activated by a CMIA interrupt, while DISEL bit of MRB in DTC is 0. [Setting condition] Set when TCNT matches TCORA 1 Compare Match Flag B 0 [Clearing conditions] • Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB • When the DTC is activated by a CMIB interrupt, while DISEL bit of MRB in DTC is 0. [Setting condition] Set when TCNT matches TCORB 1 Note: * Only 0 can be written to bits 7 to 5, to clear these flags. Rev.6.00 Oct.28.2004 page 940 of 1016 REJ09B0138-0600H TCORA0—Time Constant Register A0 TCORA1—Time Constant Register A1 TCORA0 Bit : 15 1 14 1 13 1 12 1 11 1 H'FFB4 H'FFB5 8-Bit Timer Channel 0 8-Bit Timer Channel 1 TCORA1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB0—Time Constant Register B0 TCORB1—Time Constant Register B1 TCORB0 Bit : 15 1 14 1 13 1 12 1 11 1 H'FFB6 H'FFB7 8-Bit Timer Channel 0 8-Bit Timer Channel 1 TCORB1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT0—Timer Counter 0 TCNT1—Timer Counter 1 TCNT0 Bit : 15 0 14 0 13 0 12 0 11 0 H'FFB8 H'FFB9 8-Bit Timer Channel 0 8-Bit Timer Channel 1 TCNT1 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.6.00 Oct.28.2004 page 941 of 1016 REJ09B0138-0600H TCSR—Timer Control/Status Register Bit : 7 OVF Initial value : Read/Write : 0 R/(W)* 6 WT/IT 0 R/W 5 H'FFBC (W), H'FFBC (R) 4 — 1 — 3 — 1 — 2 CKS2 0 R/W 1 CKS1 0 R/W WDT 0 CKS0 0 R/W TME 0 R/W Clock Select CKS2 CKS1 CKS0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Clock Overflow period* (when ø = 20 MHz) 819.2µs 1.6ms 6.6ms 26.2ms 104.9ms 419.4ms 1.68s ø/2 (initial value) 25.6µs ø/64 ø/128 ø/512 ø/2,048 ø/8,192 ø/32,768 ø/131,072 Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. Timer Enable 0 1 TCNT is initialized to H'00 and halted TCNT counts Timer Mode Select 0 1 Interval timer mode: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows Watchdog timer mode: Generates the WDTOVF signal*1 when TCNT overflows*2 Notes: 1. The WDTOVF pin function is not available in the F-ZTAT version, H8S/2398, H8S/2394, H8S/2392, or H8S/2390. 2. For details of the case where TCNT overflows in watchdog time mode, see section 13.2.3, Reset Control/Status Register(RSTCSR). Overflow Flag 0 1 [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF [Setting condition] Set when TCNT overflows from H'FF to H'00 in interval timer mode The method for writing to TCSR is different from that for general registers to prevent accidental overwriting. For details see section 13.2.4, Notes on Register Access. Note: * Can only be written with 0 for flag clearing. Rev.6.00 Oct.28.2004 page 942 of 1016 REJ09B0138-0600H TCNT—Timer Counter Bit : 7 0 R/W 6 0 R/W 5 0 H'FFBC (W), H'FFBD (R) 4 0 R/W 3 0 R/W 2 0 R/W WDT 1 0 R/W 0 0 R/W Initial value : Read/Write : R/W TCNT is an 8-bit readable/writable* up-counter. Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details see section 13.2.4, Notes on Register Access. RSTCSR—Reset Control/Status Register Bit : 7 WOVF Initial value : Read/Write : 0 R/(W)* 6 RSTE 0 R/W 5 H'FFBE (W) , H'FFBF (R) 4 — 1 — 3 — 1 — 2 — 1 — WDT 1 — 1 — 0 — 1 — RSTS 0 R/W Reset Select 0 1 Power-on reset Manual reset* Note: * Manual reset is not supported in the H8S/2357 (F-ZTAT and masked ROM versions) or the H8S/2352, H8S/2398, H8S/2394, H8S/2392 and H8S/2390. In these models, only 0 should be written to this bit. Reset Enable 0 1 Reset signal is not generated if TCNT overflows* Reset signal is generated if TCNT overflows Note: * The modules H8S/2357 Group are not reset, but TCNT and TCSR in WDT are reset. Watchdog Timer Overflow Flag 0 1 [Clearing condition] Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer operation Note: * Can only be written with 0 for flag clearing. The method for writing to RSTCSR is different from that for general registers to prevent accidental overwriting. For details see section 13.2.4, Notes on Register Access. Rev.6.00 Oct.28.2004 page 943 of 1016 REJ09B0138-0600H TSTR—Timer Start Register Bit : 7 — Initial value : Read/Write : 0 — 6 — 0 — 5 H'FFC0 4 CST4 0 R/W 3 CST3 0 R/W 2 CST2 0 R/W 1 CST1 0 R/W TPU 0 CST0 0 R/W CST5 0 R/W Counter Start 0 1 TCNTn count operation is stopped TCNTn performs count operation (n = 5 to 0) Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. TSYR—Timer Synchro Register Bit : 7 — Initial value : Read/Write : 0 — 6 — 0 — 5 SYNC5 0 R/W H'FFC1 4 SYNC4 0 R/W 3 SYNC3 0 R/W 2 SYNC2 0 R/W 1 SYNC1 0 R/W TPU 0 SYNC0 0 R/W Timer Synchronization 0 1 TCNTn operates independently (TCNT presetting/ clearing is unrelated to other channels) TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible (n = 5 to 0) Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. 2. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. Rev.6.00 Oct.28.2004 page 944 of 1016 REJ09B0138-0600H FLMCR1—Flash Memory Control Register 1 H'FFC8 FLASH (For the H8S/2357 F-ZTAT) 3 EV 0 R/W 2 PV 0 R/W 1 E 0 R/W 0 P 0 R/W Bit : 7 FWE —* R 6 SWE 0 R/W 5 — 0 — 4 — 0 — Initial value : Read/Write : Program 0 1 Clears program mode Program mode is entered [Setting condition] FWE=1, SWE=1, and PSU=1 Erase 0 1 Clears erase mode Erase mode is entered [Setting condition] FWE=1, SWE=1, and ESU=1 Program Verify 0 1 Clears program verify mode Program verify mode is entered [Setting condition] FWE=1 and SWE=1 Erase Verify 0 1 Clears erase verify mode Erase verify mode is entered [Setting condition] FWE=1 and SWE=1 Software Write Enable 0 1 Writing disabled Writing enabled [Setting condition] FWE=1 Flash Write Enable 0 1 When a low level is input to the FWE pin (hardware protect state) When a high level is input to the FWE pin Note: * Determined by the state of the FWE pin. Rev.6.00 Oct.28.2004 page 945 of 1016 REJ09B0138-0600H FLMCR2—Flash Memory Control Register 2 H'FFC9 FLASH (For the H8S/2357 F-ZTAT) 3 — 0 — 2 — 0 — 1 ESU 0 R/W 0 PSU 0 R/W Bit : 7 FLER 0 R 6 — 0 — 5 — 0 — 4 — 0 — Initial value : Read/Write : Program Setup 0 1 Clears program setup Program setup [Setting condition] FWE=1 and SWE=1 Erase Setup 0 1 Clears erase setup Erase setup [Setting condition] FWE=1 and SWE=1 Flash Memory Error 0 Flash memory operates normally. Writing/erasing protect (error protect) to flash memory is disabled. [Clearing condition] Reset or hardware standby mode 1 Indicates that an error occurs in writing/erasing to flash memory. Writing/erasing protect (error protect) to flash memory is enabled. [Setting condition] See section 19.10.3, Error Protection Rev.6.00 Oct.28.2004 page 946 of 1016 REJ09B0138-0600H EBR1—Erase Block Specification Register 1 EBR2— Erase Block Specification Register 2 H'FFCA H'FFCB FLASH (For the H8S/2357 F-ZTAT) FLASH (For the H8S/2357 F-ZTAT) 3 — 0 — 3 EB3 0 R/W 2 — 0 — 2 EB2 0 R/W 1 EB9 0 R/W 1 EB1 0 R/W 0 EB8 0 R/W 0 EB0 0 R/W Bit EBR1 : 7 — 0 — 7 EB7 0 R/W 6 — 0 — 6 EB6 0 R/W 5 — 0 — 5 EB5 0 R/W 4 — 0 — 4 EB4 0 R/W Initial value : Read/Write : Bit EBR2 Initial value : Read/Write : : Deviding Erase Blocks Block (size) EB0 (1 kbyte) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbyte) EB4 (28 kbytes) EB5 (16 kbytes) EB6 (8 kbytes) EB7 (8 kbytes) EB8 (32 kbytes) EB9 (32 kbytes) Address H'000000 to H'0003FF H'000400 to H'0007FF H'000800 to H'000BFF H'000C00 to H'000FFF H'001000 to H'007FFF H'008000 to H'00BFFF H'00C000 to H'00DFFF H'00E000 to H'00FFFF H'010000 to H'017FFF H'018000 to H'01FFFF Rev.6.00 Oct.28.2004 page 947 of 1016 REJ09B0138-0600H FLMCR1—Flash Memory Control Register 1 H'FFC8 FLASH (For the H8S/2398 F-ZTAT) 3 EV 0 R/W 2 PV 0 R/W 1 E 0 R/W 0 P 0 R/W Bit : 7 FWE 1 R 6 SWE 0 R/W 5 ESU 0 R/W 4 PSU 0 R/W Initial value : Read/Write : Program 1* 0 1 Clears program mode Program mode is entered [Setting condition] SWE=1 and PSU=1 Erase 1* 0 1 Clears erase mode Erase mode is entered [Setting condition] SWE=1 and ESU=1 Program Verify 1* 0 1 Clears program verify mode Program verify mode is entered [Setting condition] SWE=1 Erase Verify 1* 0 1 Clears erase verify mode Erase verify mode is entered [Setting condition] SWE=1 Program Setup 1* 0 1 Clears program setup Program setup [Setting condition] SWE=1 Erase Setup 1* Software Write Enable 1* 0 1 Writing disabled Writing enabled 0 1 Clears erase setup Erase setup [Setting condition] SWE=1 Flash Write Enable Always read as 1. Writing is disabled. Note: * The target address is H'000000 to H'03FFFF. Rev.6.00 Oct.28.2004 page 948 of 1016 REJ09B0138-0600H FLMCR2—Flash Memory Control Register 2 H'FFC9 FLASH (For the H8S/2398 F-ZTAT) 3 — 0 — 2 — 0 — 1 — 0 — 0 — 0 — Bit : 7 FLER 0 R 6 — 0 — 5 — 0 — 4 — 0 — Initial value : Read/Write : Flash Memory Error 0 Flash memory operates normally. Writing/erasing protect (error protect) to flash memory is disabled. [Clearing condition] Reset or hardware standby mode 1 Indicates that an error occurs in writing/erasing to flash memory. Writing/erasing protect (error protect) to flash memory is enabled. [Setting condition] See section 19.19.3, Error Protection EBR1—Erase Block Specification Register 1 EBR2—Erase Block Specification Register 2 H'FFCA H'FFCB FLASH (For the H8S/2398 F-ZTAT) FLASH (For the H8S/2398 F-ZTAT) 3 EB3 0 R/W 3 EB11 0 R/W 2 EB2 0 R/W 2 EB10 0 R/W 1 EB1 0 R/W 1 EB9 0 R/W 0 EB0 0 R/W 0 EB8 0 R/W Bit EBR1 : 7 EB7 0 R/W 7 — 0 — 6 EB6 0 R/W 6 — 0 — 5 EB5 0 R/W 5 — 0 — 4 EB4 0 R/W 4 — 0 — Initial value : Read/Write : Bit EBR2 Initial value : Read/Write : : Rev.6.00 Oct.28.2004 page 949 of 1016 REJ09B0138-0600H TCR0—Timer Control Register 0 Bit : 7 CCLR2 Initial value : Read/Write : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W H'FFD0 4 0 R/W 3 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPU0 CKEG1 CKEG0 TPSC0 0 R/W Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Edge 0 0 1 1 Counter Clear 0 0 0 1 1 0 1 1 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel TCNT performing synchronous clearing/synchronous operation*1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture*2 TCNT cleared by TGRD compare match/input capture*2 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 — Count at rising edge Count at falling edge Count at both edges Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Rev.6.00 Oct.28.2004 page 950 of 1016 REJ09B0138-0600H TMDR0—Timer Mode Register 0 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 BFB 0 R/W H'FFD1 4 BFA 0 R/W 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W TPU0 0 MD0 0 R/W Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 × × × Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — × : Don’t care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. TGRA Buffer Operation 0 1 TGRA operates normally TGRA and TGRC used together for buffer operation TGRB Buffer Operation 0 1 TGRB operates normally TGRB and TGRD used together for buffer operation Rev.6.00 Oct.28.2004 page 951 of 1016 REJ09B0138-0600H TIOR0H—Timer I/O Control Register 0H Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FFD2 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W TPU0 TGR0A I/O Control 0 0 0 0 TGR0A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR0A is input 1 capture × register × Capture input source is TIOCA0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down 1/count clock × : Don’t care TGR0B Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR0B is input capture register Capture input source is TIOCB0 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down* 1/count clock × : Don’t care Note: * When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and ø/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 TGR0B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 × × × × Rev.6.00 Oct.28.2004 page 952 of 1016 REJ09B0138-0600H TIOR0L—Timer I/O Control Register 0L Bit : : Initial value : Read/Write : 7 IOD3 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W H'FFD3 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W TPU0 TGR0C I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 × × × TGR0C is input capture register Capture input source is TIOCC0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down 1/count clock TGR0C Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match × : Don’t care Note: When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. TGR0D I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 × × × TGR0D is input capture register *2 TGR0D Output disabled is output compare Initial output is register 0 output *2 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input source is TIOCD0 pin Capture input source is channel 1/count clock Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT1 count-up/ count-down*1 × : Don’t care Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and ø/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Rev.6.00 Oct.28.2004 page 953 of 1016 REJ09B0138-0600H TIER0—Timer Interrupt Enable Register 0 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 — 0 — H'FFD4 4 TCIEV 0 R/W 3 TGIED 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TPU0 TGIEA 0 R/W TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled TGR Interrupt Enable C 0 1 Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled TGR Interrupt Enable D 0 1 Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev.6.00 Oct.28.2004 page 954 of 1016 REJ09B0138-0600H TSR0—Timer Status Register 0 Bit : 7 — 1 — 6 — 1 — 5 — 0 — 4 TCFV 0 R/(W)* 3 H'FFD5 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU0 TGFD 0 R/(W)* Initial value : Read/Write : Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Input Capture/Output Compare Flag C 0 [Clearing conditions] • When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] • When TCNT = TGRC while TGRC is functioning as output compare register • When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register 1 Input Capture/Output Compare Flag D 0 [Clearing conditions] • When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFD after reading TGFD = 1 [Setting conditions] • When TCNT = TGRD while TGRD is functioning as output compare register • When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register 1 Overflow Flag 0 1 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. Rev.6.00 Oct.28.2004 page 955 of 1016 REJ09B0138-0600H TCNT0—Timer Counter 0 Bit : 15 0 14 0 13 0 12 0 11 0 H'FFD6 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 TPU0 2 0 1 0 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TGR0A—Timer General Register 0A TGR0B—Timer General Register 0B TGR0C—Timer General Register 0C TGR0D—Timer General Register 0D Bit : 15 1 14 1 13 1 12 1 11 1 H'FFD8 H'FFDA H'FFDC H'FFDE 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 TPU0 TPU0 TPU0 TPU0 2 1 1 1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.6.00 Oct.28.2004 page 956 of 1016 REJ09B0138-0600H TCR1—Timer Control Register 1 Bit : 7 — Initial value : Read/Write : 0 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W H'FFE0 4 0 R/W 3 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPU1 CKEG1 CKEG0 TPSC0 0 R/W Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on ø/256 Counts on TCNT2 overflow/underflow Note: This setting is ignored when channel 1 is in phase counting mode. Clock Edge 0 0 1 1 —* Count at rising edge Count at falling edge Count at both edges Note: * This setting is ignored when channel 1 is in phase counting mode. Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operating setting is performed by setting the SYNC bit in TSYR to 1. Rev.6.00 Oct.28.2004 page 957 of 1016 REJ09B0138-0600H TMDR1—Timer Mode Register 1 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 0 — H'FFE1 4 — 0 — 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W TPU1 0 MD0 0 R/W Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 × × × Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — × : Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev.6.00 Oct.28.2004 page 958 of 1016 REJ09B0138-0600H TIOR1—Timer I/O Control Register 1 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FFE2 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W TPU1 TGR1A I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 × × × TGR1A is input capture register Capture input source is TIOCA1 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR0A channel 0/TGR0A compare match/ compare match/ input capture input capture × : Don’t care TGR1B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 × × × TGR1B is input capture register Capture input source is TIOCB1 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR0C TGR0B compare match/input compare match/ capture input capture × : Don’t care TGR1B Output disabled is output compare Initial output is register 0 output TGR1A Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Rev.6.00 Oct.28.2004 page 959 of 1016 REJ09B0138-0600H TIER1—Timer Interrupt Enable Register 1 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 TCIEU 0 R/W H'FFE4 4 TCIEV 0 R/W 3 — 0 — 2 — 0 — 1 TGIEB 0 R/W 0 TGIEA 0 R/W TPU1 TGR Interrupt Enable A 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev.6.00 Oct.28.2004 page 960 of 1016 REJ09B0138-0600H TSR1—Timer Status Register 1 Bit : 7 TCFD 1 R 6 — 1 — 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* H'FFE5 3 — 0 — 2 — 0 — 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU1 Initial value : Read/Write : Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. TCNT1—Timer Counter 1 Bit : 15 0 14 0 13 0 12 0 11 0 H'FFE6 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 TPU1 2 0 1 0 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. Rev.6.00 Oct.28.2004 page 961 of 1016 REJ09B0138-0600H TGR1A—Timer General Register 1A TGR1B—Timer General Register 1B Bit : 15 1 14 1 13 1 12 1 11 1 H'FFE8 H'FFEA 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 TPU1 TPU1 2 1 1 1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCR2—Timer Control Register 2 Bit : 7 — Initial value : Read/Write : 0 — 6 CCLR1 0 R/W 5 CCLR0 0 R/W H'FFF0 4 0 R/W 3 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPU2 CKEG1 CKEG0 TPSC0 0 R/W Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on ø/1024 Note: This setting is ignored when channel 2 is in phase counting mode. Clock Edge 0 0 1 1 —* Count at rising edge Count at falling edge Count at both edges Note: * This setting is ignored when channel 2 is in phase counting mode. Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operating setting is performed by setting the SYNC bit TSYR to 1. Rev.6.00 Oct.28.2004 page 962 of 1016 REJ09B0138-0600H TMDR2—Timer Mode Register 2 Bit : 7 — Initial value : Read/Write : 1 — 6 — 1 — 5 — 0 — H'FFF1 4 — 0 — 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W TPU2 0 MD0 0 R/W Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 × × × Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — × : Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev.6.00 Oct.28.2004 page 963 of 1016 REJ09B0138-0600H TIOR2—Timer I/O Control Register 2 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'FFF2 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W TPU2 TGR2A I/O Control 0 0 0 0 TGR2A is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 × 0 0 TGR2A is input 1 capture × register Capture input source is TIOCA2 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges × : Don’t care TGR2B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 × 0 0 1 1 × TGR2B is input capture register Capture input source is TIOCB2 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges × : Don’t care TGR2B is output compare register Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 Rev.6.00 Oct.28.2004 page 964 of 1016 REJ09B0138-0600H TIER2—Timer Interrupt Enable Register 2 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 — 1 — 5 TCIEU 0 R/W H'FFF4 4 TCIEV 0 R/W 3 — 0 — 2 — 0 — 1 TGIEB 0 R/W 0 TGIEA 0 R/W TPU2 TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled Rev.6.00 Oct.28.2004 page 965 of 1016 REJ09B0138-0600H TSR2—Timer Status Register 2 Bit : 7 TCFD 1 R 6 — 1 — 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* H'FFF5 3 — 0 — 2 — 0 — 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU2 Initial value : Read/Write : Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 • When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 • When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. Rev.6.00 Oct.28.2004 page 966 of 1016 REJ09B0138-0600H TCNT2—Timer Counter 2 Bit : 15 0 14 0 13 0 12 0 11 0 H'FFF6 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 TPU2 2 0 1 0 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR2A—Timer General Register 2A TGR2B—Timer General Register 2B Bit : 15 1 14 1 13 1 12 1 11 1 H'FFF8 H'FFFA 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 TPU2 TPU2 2 1 1 1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.6.00 Oct.28.2004 page 967 of 1016 REJ09B0138-0600H Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagram Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1 P1n RDR1 RPOR1 Legend: WDDR1: Write to P1DDR WDR1: Write to P1DR RDR1: Read P1DR RPOR1: Read port 1 n = 0 or 1 Figure C-1 (a) Port 1 Block Diagram (Pins P10 and P11) Rev.6.00 Oct.28.2004 page 968 of 1016 REJ09B0138-0600H Internal data bus PPG module Pulse output enable Pulse output DMA controller DMA transfer acknowledge enable DMA transfer acknowledge TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1 P1n RDR1 RPOR1 Input capture input External clock input Legend: WDDR1: Write to P1DDR WDR1: Write to P1DR RDR1: Read P1DR RPOR1: Read port 1 n = 2, 3, 5, 7 Figure C-1 (b) Port 1 Block Diagram (Pins P12, P13, P15, and P17) Rev.6.00 Oct.28.2004 page 969 of 1016 REJ09B0138-0600H Internal data bus PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1 P1n RDR1 RPOR1 Input capture input Legend: WDDR1: Write to P1DDR WDR1: Write to P1DR RDR1: Read P1DR RPOR1: Read port 1 n = 4 or 6 Figure C-1 (c) Port 1 Block Diagram (Pins P14 and P16) Rev.6.00 Oct.28.2004 page 970 of 1016 REJ09B0138-0600H Internal data bus PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output C.2 Port 2 Block Diagram Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2 P2n RDR2 RPOR2 Input capture input Legend: WDDR2: Write to P2DDR WDR2: Write to P2DR RDR2: Read P2DR RPOR2: Read port 2 n = 0 or 1 Figure C-2 (a) Port 2 Block Diagram (Pins P20 and P21) Rev.6.00 Oct.28.2004 page 971 of 1016 REJ09B0138-0600H Internal data bus PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2 P2n RDR2 RPOR2 Internal data bus PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input 8-bit timer module Counter external reset input Legend: WDDR2: Write to P2DDR WDR2: Write to P2DR RDR2: Read P2DR RPOR2: Read port 2 n = 2 or 4 Figure C-2 (b) Port 2 Block Diagram (Pins P22 and P24) Rev.6.00 Oct.28.2004 page 972 of 1016 REJ09B0138-0600H Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2 P2n RDR2 RPOR2 Internal data bus PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input 8-bit timer module Counter external reset input Legend: WDDR2: Write to P2DDR WDR2: Write to P2DR RDR2: Read P2DR RPOR2: Read port 2 n = 3 or 5 Figure C-2 (c) Port 2 Block Diagram (Pins P23 and P25) Rev.6.00 Oct.28.2004 page 973 of 1016 REJ09B0138-0600H Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2 P2n RDR2 RPOR2 Legend: WDDR2: Write to P2DDR WDR2: Write to P2DR RDR2: Read P2DR RPOR2: Read port 2 n = 6 or 7 Figure C-2 (d) Port 2 Block Diagram (Pins P26 and P27) Rev.6.00 Oct.28.2004 page 974 of 1016 REJ09B0138-0600H Internal data bus PPG module Pulse output enable Pulse output 8-bit timer Compare-match output enable Compare-match output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input C.3 Port 3 Block Diagram Reset R Q D P3nDDR C WDDR3 *1 Reset R Q D P3nDR C WDR3 *2 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data RDR3 P3n RPOR3 Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: n = 0 or 1 Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal Figure C-3 (a) Port 3 Block Diagram (Pins P30 and P31) Rev.6.00 Oct.28.2004 page 975 of 1016 REJ09B0138-0600H Internal data bus Reset R Q D P3nDDR C *1 WDDR3 Reset P3n R Q D P3nDR C *2 WDR3 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial receive data enable RDR3 RPOR3 Internal data bus Serial receive data Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: n = 2 or 3 Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal Figure C-3 (b) Port 3 Block Diagram (Pins P32 and P33) Rev.6.00 Oct.28.2004 page 976 of 1016 REJ09B0138-0600H Reset R Q D P3nDDR C WDDR3 *1 Reset R Q D P3nDR C WDR3 *2 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial clock output enable Serial clock output RDR3 Serial clock input enable P3n RPOR3 Legend: WDDR3: Write to P3DDR WDR3: Write to P3DR WODR3: Write to P3ODR RDR3: Read P3DR RPOR3: Read port 3 RODR3: Read P3ODR n = 4 or 5 Notes: 1. Output enable signal 2. Open drain control signal Figure C-3 (c) Port 3 Block Diagram (Pins P34 and P35) Rev.6.00 Oct.28.2004 page 977 of 1016 REJ09B0138-0600H Internal data bus Serial clock input C.4 Port 4 Block Diagram Internal data bus A/D converter module Legend: RPOR4 : Read port 4 n = 0 to 5 Analog input Internal data bus A/D converter module Analog input D/A converter module Output enable Analog output RPOR4 P4n Figure C-4 (a) Port 4 Block Diagram (Pins P40 to P45) RPOR4 P4n Legend: RPOR4 : Read port 4 n = 6 or 7 Figure C-4 (b) Port 4 Block Diagram (Pins P46 and P47) Rev.6.00 Oct.28.2004 page 978 of 1016 REJ09B0138-0600H C.5 Port 5 Block Diagram Reset R Q D P50DDR C WDDR0 Reset R Q D P50DR C WDR5 SCI module Serial transmit data output enable Serial transmit data RDR5 P50 RPOR5 Legend: WDDR5: WDR5: RDR5: RPOR5: Write to P5DDR Write to P5DR Read P5DR Read port 5 Figure C-5 (a) Port 5 Block Diagram (Pin P50) Rev.6.00 Oct.28.2004 page 979 of 1016 REJ09B0138-0600H Internal data bus Reset R Q D P51DDR C WDDR5 Reset P51 R Q D P51DR C WDR5 RDR5 RPOR5 Legend: WDDR5: Write to P5DDR WDR5: Write to P5DR RDR5: Read P5DR RPOR5: Read port 5 Figure C-5 (b) Port 5 Block Diagram (Pin P51) Rev.6.00 Oct.28.2004 page 980 of 1016 REJ09B0138-0600H Internal data bus SCI module Serial receive data enable Serial receive data Reset R Q D P52DDR C WDDR5 Reset R Q D P52DR C WDR5 P52 RDR5 RPOR5 Legend: WDDR5: WDR5: RDR5: RPOR5: Write to P5DDR Write to P5DR Read P5DR Read port 5 Figure C-5 (c) Port 5 Block Diagram (Pin P52) Rev.6.00 Oct.28.2004 page 981 of 1016 REJ09B0138-0600H Internal data bus SCI module Serial clock output enable Serial clock output Serial clock input enable Serial clock input Reset R Q D P53DDR C WDDR5 Reset P53 R Q D P53DR C WDR5 RDR5 RPOR5 A/D converter A/D converter external trigger input Write to P5DDR Write to P5DR Read P5DR Read port 5 Legend: WDDR5: WDR5: RDR5: RPOR5: Figure C-5 (d) Port 5 Block Diagram (Pin P53) Rev.6.00 Oct.28.2004 page 982 of 1016 REJ09B0138-0600H Internal data bus C.6 Port 6 Block Diagram Reset R Q D P60DDR C WDDR6 Mode 7 P60 Mode 4/5/6 Reset R Q D P60DR C WDR6 Internal data bus Bus controller Chip select DMA controller DMA request input RDR6 RPOR6 Legend: WDDR6: WDR6: RDR6: RPOR6: Write to P6DDR Write to P6DR Read P6DR Read port 6 Figure C-6 (a) Port 6 Block Diagram (Pin P60) Rev.6.00 Oct.28.2004 page 983 of 1016 REJ09B0138-0600H Reset R Q D P61DDR C WDDR6 Mode 7 P61 Mode 4/5/6 Reset R Q D P61DR C WDR6 RDR6 RPOR6 Legend: WDDR6: Write to P6DDR WDR6: Write to P6DR RDR6: Read P6DR RPOR6: Read port 6 Figure C-6 (b) Port 6 Block Diagram (Pin P61) Rev.6.00 Oct.28.2004 page 984 of 1016 REJ09B0138-0600H Internal data bus Bus controller Chip select DMA controller DMA transfer end enable DMA transfer end Reset R Q D P62DDR C WDDR6 Reset P62 R Q D P62DR C WDR6 RDR6 RPOR6 DMA controller DMA request input Legend: WDDR6: Write to P6DDR WDR6: Write to P6DR RDR6: Read P6DR RPOR6: Read port 6 Figure C-6 (c) Port 6 Block Diagram (Pin P62) Rev.6.00 Oct.28.2004 page 985 of 1016 REJ09B0138-0600H Internal data bus Reset R Q D P63DDR C WDDR6 Reset R Q D P63DR C WDR6 DMA controller DMA transfer end enable DMA transfer end RDR6 P63 RPOR6 Legend: WDDR6: WDR6: RDR6: RPOR6: Write to P6DDR Write to P6DR Read P6DR Read port 6 Figure C-6 (d) Port 6 Block Diagram (Pin P63) Rev.6.00 Oct.28.2004 page 986 of 1016 REJ09B0138-0600H Internal data bus Reset R Q D P6nDDR C WDDR6 Reset P6n R Q D P6nDR C WDR6 RDR6 RPOR6 Interrupt controller IRQ interrupt input Legend: WDDR6: Write to P6DDR WDR6: Write to P6DR RDR6: Read P6DR RPOR6: Read port 6 n = 4 or 5 Figure C-6 (e) Port 6 Block Diagram (Pins P64 and P65) Rev.6.00 Oct.28.2004 page 987 of 1016 REJ09B0138-0600H Internal data bus Reset R Q D P6nDDR C WDDR6 Mode 7 P6n Mode 4/5/6 Reset R Q D P6nDR C WDR6 Internal data bus Bus controller Chip select Interrupt controller IRQ interrupt input RDR6 RPOR6 Legend: WDDR6: Write to P6DDR WDR6: Write to P6DR RDR6: Read P6DR RPOR6: Read port 6 n = 6 or 7 Figure C-6 (f) Port 6 Block Diagram (Pins P66 and P67) Rev.6.00 Oct.28.2004 page 988 of 1016 REJ09B0138-0600H C.7 Port A Block Diagram Reset R Q D PAnPCR C WPCRA RPCRA Mode 4/5 Reset R Q D PAnDDR C WDDRA *1 Reset R Q D PAnDR C WDRA *2 Reset R Q D PAnODR C WODRA RODRA PAn Mode 7 Mode 4/5/6 RDRA RPORA Legend: WDDRA: Write to PADDR WDRA: Write to PADR WODRA: Write to PAODR WPCRA: Write to PAPCR RDRA: Read PADR RPORA: Read port A RODRA: Read PAODR RPCRA: Read PAPCR n = 0 to 3 Notes: 1. Output enable signal 2. Open drain control signal Figure C-7 (a) Port A Block Diagram (Pins PA0 to PA 3) Rev.6.00 Oct.28.2004 page 989 of 1016 REJ09B0138-0600H Internal address bus Internal data bus Reset R Q D PA4PCR C WPCRA RPCRA Mode 4/5 Reset R Q D PA4DDR C WDDRA *1 Reset R Q D PA4DR C WDRA *2 Reset R Q D PA4ODR C WODRA RODRA PA4 Mode 7 Mode 4/5/6 RDRA RPORA Interrupt controller Legend: WDDRA: Write to PADDR WDRA: Write to PADR WODRA: Write to PAODR WPCRA: Write to PAPCR RDRA: Read PADR RPORA: Read port A RODRA: Read PAODR RPCRA: Read PAPCR IRQ interrupt input Notes: 1. Output enable signal 2. Open drain control signal Figure C-7 (b) Port A Block Diagram (Pin PA4) Rev.6.00 Oct.28.2004 page 990 of 1016 REJ09B0138-0600H Internal address bus Internal data bus Reset R Q D PAnPCR C WPCRA RPCRA Reset R Q D PAnDDR C WDDRA *1 Reset R Q D PAnDR C WDRA *2 Reset R Q D PAnODR C WODRA RODRA PAn Mode 7 Mode 4/5/6 RDRA RPORA Interrupt controller IRQ interrupt input Legend: WDDRA: Write to PADDR WDRA: Write to PADR WODRA: Write to PAODR WPCRA: Write to PAPCR RDRA: Read PADR RPORA: Read port A RODRA: Read PAODR RPCRA: Read PAPCR n = 5 to 7 Notes: 1. Output enable signal 2. Open drain control signal Figure C-7 (c) Port A Block Diagram (Pins PA5 to PA7) Rev.6.00 Oct.28.2004 page 991 of 1016 REJ09B0138-0600H Internal address bus Internal data bus C.8 Port B Block Diagram Reset R Q D PBnPCR C WPCRB RPCRB Mode 4/5 Reset R Q D PBnDDR C WDDRB Reset R Q D PBnDR C WDRB PBn Mode 7 Mode 4/5/6 RDRB RPORB Legend: WDDRB: Write to PBDDR WDRB: Write to PBDR WPCRB: Write to PBPCR RDRB: Read PBDR RPORB: Read port B RPCRB: Read PBPCR n = 0 to 7 Figure C-8 Port B Block Diagram (Pin PB0 to PB7) Rev.6.00 Oct.28.2004 page 992 of 1016 REJ09B0138-0600H Internal address bus Internal data bus C.9 Port C Block Diagram Reset R Q D PCnPCR C WPCRC RPCRC Internal data bus Mode 4/5 Reset R Q D PCnDDR C WDDRC Reset R Q D PCnDR C WDRC PCn Mode 7 Mode 4/5/6 RDRC RPORC Legend: WDDRC: Write to PCDDR WDRC: Write to PCDR WPCRC: Write to PCPCR RDRC: Read PCDR RPORC: Read port C RPCRC: Read PCPCR n = 0 to 7 Figure C-9 Port C Block Diagram (Pin PC0 to PC 7) Rev.6.00 Oct.28.2004 page 993 of 1016 REJ09B0138-0600H Internal address bus C.10 Port D Block Diagram Reset Internal upper data bus Internal lower data bus R Q D PDnPCR C WPCRD RPCRD Reset Mode 7 External address write Mode 4/5/6 R Q D PDnDDR C WDDRD Reset R Q D PDnDR C WDRD PDn Mode 7 Mode 4/5/6 External address upper write External address lower write RDRD RPORD Legend: WDDRD: Write to PDDDR WDRD: Write to PDDR WPCRD: Write to PDPCR RDRD: Read PDDR RPORD: Read port D RPCRD: Read PDPCR n = 0 to 7 External address upper read External address lower read Figure C-10 Port D Block Diagram (Pin PD0 to PD 7) Rev.6.00 Oct.28.2004 page 994 of 1016 REJ09B0138-0600H C.11 Port E Block Diagram Reset Internal upper data bus Internal lower data bus R Q D PEnPCR C WPCRE RPCRE Mode 7 Mode 4/5/6 8-bit bus mode Reset R Q D PEnDDR C WDDRE Reset R Q D PEnDR C WDRE External address write Mode 4/5/6 16-bit bus mode PEn Mode 7 Mode 4/5/6 RDRE RPORE Legend: WDDRE: Write to PEDDR WDRE: Write to PEDR WPCRE: Write to PEPCR RDRE: Read PEDR RPORE: Read port E RPCRE: Read PEPCR n = 0 to 7 External address lower read Figure C-11 Port E Block Diagram (Pin PE0 to PE7) Rev.6.00 Oct.28.2004 page 995 of 1016 REJ09B0138-0600H C.12 Port F Block Diagram Internal data bus Bus controller BRLE bit Bus request input Legend: WDDRF: Write to PFDDR WDRF: Write to PFDR RDRF: Read PFDR RPORF: Read port F Reset R Q D PF0DDR C Mode 4/5/6 WDDRF Reset PF0 R Q D PF0DR C WDRF RDRF RPORF Figure C-12 (a) Port F Block Diagram (Pin PF0) Rev.6.00 Oct.28.2004 page 996 of 1016 REJ09B0138-0600H Reset R Q D PF1DDR C WDDRF Reset R Q D PF1DR C WDRF Mode 4/5/6 PF1 RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C-12 (b) Port F Block Diagram (Pin PF1) Rev.6.00 Oct.28.2004 page 997 of 1016 REJ09B0138-0600H Internal data bus Bus controller BRLE output Bus request acknowledge output Reset R Q D PF2DDR C WDDRF Reset Mode 4/5/6 PF2 Mode 4/5/6 R Q D PF2DR C WDRF Mode 4/5/6 Internal data bus Bus controller Wait enable Bus request output enable Bus request output Wait input LCAS output enable LCAS output RDRF RPORF Legend: WDDRF: Write to PFDDR WDRF: Write to PFDR RDRF: Read PFDR RPORF: Read port F Figure C-12 (c) Port F Block Diagram (Pin PF2) Rev.6.00 Oct.28.2004 page 998 of 1016 REJ09B0138-0600H Reset R Q D PF3DDR C WDDRF Mode 7 PF3 Mode 4/5/6 Reset R Q D PF3DR C WDRF Mode 4/5/6 Internal data bus Bus controller LWR output RDRF RPORF Legend: WDDRF: Write to PFDDR WDRF: Write to PFDR RDRF: Read PFDR RPORF: Read port F Figure C-12 (d) Port F Block Diagram (Pin PF3) Rev.6.00 Oct.28.2004 page 999 of 1016 REJ09B0138-0600H Reset R Q D PF4DDR C WDDRF Mode 7 PF4 Mode 4/5/6 Reset R Q D PF4DR C WDRF Mode 4/5/6 Internal data bus Bus controller HWR output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C-12 (e) Port F Block Diagram (Pin PF4) Rev.6.00 Oct.28.2004 page 1000 of 1016 REJ09B0138-0600H Reset R Q D PF5DDR C WDDRF Mode 7 PF5 Mode 4/5/6 Reset R Q D PF5DR C WDRF Mode 4/5/6 RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C-12 (f) Port F Block Diagram (Pin PF5) Rev.6.00 Oct.28.2004 page 1001 of 1016 REJ09B0138-0600H Internal data bus Bus controller RD output Reset R Q D PF6DDR C WDDRF Mode 7 PF6 Mode 4/5/6 Reset R Q D PF6DR C WDRF Mode 4/5/6 RDRF RPORF Legend: WDDRF: Write to PFDDR WDRF: Write to PFDR RDRF: Read PFDR RPORF: Read port F Figure C-12 (g) Port F Block Diagram (Pin PF6) Rev.6.00 Oct.28.2004 page 1002 of 1016 REJ09B0138-0600H Internal data bus Bus controller AS output Mode 4/5/6 Reset WDDRF Reset PF7 R Q D PF7DR C WDRF RDRF RPORF Legend: WDDRF: Write to PFDDR WDRF: Write to PFDR RDRF: Read PFDR RPORF: Read port F Note: * Set priority Figure C-12 (h) Port F Block Diagram (Pin PF7) Rev.6.00 Oct.28.2004 page 1003 of 1016 REJ09B0138-0600H Internal data bus S* R Q D PF7DDR C ø C.13 Port G Block Diagram Reset R Q D PG0DDR C WDDRG Reset R Q D PG0DR C WDRG Mode 4/5/6 PG0 RDRG RPORG Legend: WDDRG: Write to PGDDR WDRG: Write to PGDR RDRG: Read PGDR RPORG: Read port G Figure C-13 (a) Port G Block Diagram (Pin PG0) Rev.6.00 Oct.28.2004 page 1004 of 1016 REJ09B0138-0600H Internal data bus Bus controller CAS enable CAS output Reset R Q D PGnDDR C WDDRG Mode 7 PGn Mode 4/5/6 Reset R Q D PGnDR C WDRG Internal data bus Bus controller Chip select RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: n = 1 to 3 Write to PGDDR Write to PGDR Read PGDR Read port G Figure C-13 (b) Port G Block Diagram (Pins PG1 to PG3) Rev.6.00 Oct.28.2004 page 1005 of 1016 REJ09B0138-0600H Mode Mode 4/5 6/7 Reset WDDRG Reset Mode 7 PG4 Mode 4/5/6 R Q D PG4DR C WDRG RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: Write to PGDDR Write to PGDR Read PGDR Read port G Figure C-13 (c) Port G Block Diagram (Pin PG4) Rev.6.00 Oct.28.2004 page 1006 of 1016 REJ09B0138-0600H Internal data bus Bus controller Chip select S R Q D PG4DDR C Appendix D Pin States D.1 Port States in Each Mode Table D-1 I/O Port States in Each Processing State MCU Port Name Operating Pin Name Mode Port 1 Port 2 Port 3 P47/DA1 4 to 7 4 to 7 4 to 7 4 to 7 PowerOn Reset T T T T Hardware Software Standby Standby Mode Mode T T T T kept kept kept [DAOE1 = 1] kept [DAOE1 = 0] T [DAOE0 = 1] kept [DAOE0 = 0] T T kept kept kept Bus Release State kept kept kept kept Program Execution State Sleep Mode I/O port I/O port I/O port I/O port Manual Reset*2 kept kept kept T P46/DA0 4 to 7 T T T kept I/O port P45 to P40 Port 5 P65 to P62 P67/CS7 P66/CS6 P61/CS5 P60/CS4 4 to 7 4 to 7 4 to 7 7 4 to 6 T T T T T T kept kept kept kept T T T T T T kept kept kept Input port I/O port I/O port I/O port [DDR = 0] Input port [DDR = 1] CS7 to CS4 [DDR = 0] Input port [DDR = 1] Address output [DDR = 0] Input port [DDR = 1] Address output I/O port Address output [DDR · OPE = 0] T T [DDR · OPE = 1] H [DDR · OPE = 0] T T [DDR · OPE = 1] kept [DDR · OPE = 0] T T [DDR · OPE = 1] kept kept [OPE = 0] T [OPE = 1] kept kept T PA 7/A 23 PA 6/A 22 PA 5/A 21 4, 5 T kept T 6 T kept T 7 PA 4/A 20 PA 3/A 19 PA 2/A 18 PA 1/A 17 PA 0/A 16 4, 5 T L kept kept T T 6 T kept T [DDR · OPE = 0] T T [DDR · OPE = 1] kept kept kept [DDR = 0] Input port [DDR = 1] Address output I/O port 7 T kept T Rev.6.00 Oct.28.2004 page 1007 of 1016 REJ09B0138-0600H MCU Port Name Operating Pin Name Mode Port B 4, 5 PowerOn Reset L Manual Reset*2 kept Hardware Software Standby Standby Mode Mode T [OPE = 0] T [OPE = 1] kept Bus Release State T Program Execution State Sleep Mode Address output 6 T kept T [DDR · OPE = 0] T T [DDR · OPE = 1] kept kept [OPE = 0] T [OPE = 1] kept kept T [DDR = 0] Input port [DDR = 1] Address output I/O port Address output 7 Port C 4, 5 T L kept kept T T 6 T kept T [DDR · OPE = 0] T T [DDR · OPE = 1] kept kept T kept kept T kept [DDR = 0] Input port [DDR = 1] H [DDR = 0] Input port [DDR = 1] H [OPE = 0] T [OPE = 1] H kept kept T kept kept T kept [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output T [DDR = 0] Input port [DDR = 1] Address output I/O port Data bus I/O port I/O port Data bus I/O port [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output AS , RD, HWR, LWR 7 Port D 4 to 6 7 Port E 4 to 6 8-bit bus T T T T kept T* 1 T T T T T T T kept kept T*1 kept [DDR = 0] T [DDR = 1] Clock output kept 16-bit T bus 7 PF7/ø 4 to 6 T Clock output 7 T T PF6/AS PF5/RD PF4/HWR PF3/LWR 4 to 6 H H*1 T 7 T kept T kept I/O port Rev.6.00 Oct.28.2004 page 1008 of 1016 REJ09B0138-0600H MCU Port Name Operating Pin Name Mode PF2/LCAS/ WAIT/ BREQO 4 to 6 PowerOn Reset T Manual Reset*2 Hardware Software Standby Standby Mode Mode [BREQOE + WAITE + LCASE = 0] kept [BREQOE = 1] kept [WAITE = 1] T [LCASE = 1, OPE = 0] T [LCASE = 1, OPE = 1] LCAS kept [BRLE = 0] kept [BRLE = 1] H kept [BRLE = 0] kept [BRLE = 1] T Bus Release State [BREQOE + WAITE + LCASE = 0] kept [BREQOE = 1] BREQO [WAITE = 1] T [LCASE = 1] T Program Execution State Sleep Mode [BREQOE + WAITE + LCASE= 0] I/O port [BREQOE = 1] BREQO [WAITE = 1] WAIT [LCASE = 1] LCAS [BREQOE + T WAITE + LCASE = 0] kept [BREQOE = 1] BREQO [WAITE = 1] T [LCASE = 1] H*1 7 PF1/BACK 4 to 6 T T kept [BRLE = 0] kept [BRLE = 1] BACK kept [BRLE = 0] kept [BRLE = 1] BREQ [DDR = 0] T [DDR = 1] H*1 kept kept [DDR = 0] T [DDR = 1] H*1 kept T T kept L I/O port [BRLE = 0] I/O port [BRLE = 1] BACK I/O port [BRLE = 0] I/O port [BRLE = 1] BREQ [DDR = 0] Input port [DDR = 1] CS0 I/O port I/O port [DDR = 0] Input port [DDR = 1] CS1 to CS3 I/O port [DRAME = 0] Input port [DRAME = 1] CAS 7 PF0/BREQ 4 to 6 T T T T kept T PG 4/CS0 4, 5 6 H T T [DDR · OPE = 0] T T [DDR · OPE = 1] H kept kept kept kept 7 PG 3/CS1 PG 2/CS2 PG 1/CS3 7 4 to 6 T T T T T T [DDR · OPE = 0] T T [DDR · OPE = 1] H kept [DRAME = 0] kept [OPE = 0] T [DRAME · OPE= 1] CAS kept T PG 0/CAS 7 4 to 6 T T T [DRAME = 0] T kept [DRAME = 1] H*1 Legend: H: L: T: kept: DDR: OPE: WAITE: BRLE: High level Low level High impedance Input port becomes high-impedance, output port retains state Data direction register Output port enable Wait input enable Bus release enable Rev.6.00 Oct.28.2004 page 1009 of 1016 REJ09B0138-0600H BREQOE: BREQO pin enable DRAME: DRAM space setting LCASE: DRAM space setting, CW2 = LCASS = 0 Notes: 1. Indicates the state after completion of the executing bus cycle. 2. Manual reset is only supported in the H8S/2357 ZTAT. Rev.6.00 Oct.28.2004 page 1010 of 1016 REJ09B0138-0600H Appendix E Pin States at Power-On Note that pin states at power-on depend on the state of the STBY pin and NMI pin. The case in which pins settle* from an indeterminate state at power-on, and the case in which pins settle* from the high-impedance state, are described below. After reset release, power-on reset exception handling is started. Note: * “Settle” refers to the pin states in a power-on reset in each MCU operating mode. E.1 When Pins Settle from an Indeterminate State at Power-On When the NMI pin level changes from low to high after powering on, the chip goes to the power-on reset state*2 after a high level is detected at the NMI pin. While the chip detects a low level at the NMI pin, the manual reset state*1 is established. The pin states are indeterminate during this interval. (Ports may output an internally determined value after powering on.) The NMI setup time (tNMIS) is necessary for the chip to detect a high level at the NMI pin. Notes: 1. Applies to the ZTAT version only. 2. Except for the H8S/2357 ZTAT, all resets are power-on resets, regardless of the level on the NMI pin. VCC tOSC1 STBY Manual reset*1 Power-on reset*2 NMI RES φ NMI = Low → NMI = High RES = Low Notes: 1. 2. Applies to the ZTAT version only. Except for the H8S/2357 ZTAT, all resets are power-on resets, regardless of the level on the NMI pin. Figure E-1 When Pins Settle from an Indeterminate State at Power-On Rev.6.00 Oct.28.2004 page 1011 of 1016 REJ09B0138-0600H E.2 When Pins Settle from the High-Impedance State at Power-On When the STBY pin level changes from low to high after powering on, the chip goes to the power-on reset state* after a high level is detected at the STBY pin. While the chip detects a low level at the STBY pin, it is in the hardware standby mode. During this interval, the pins are in the high-impedance state. After detecting a high level at the STBY pin, the chip starts oscillation. Note: * Excerpt for the H8S/2357 ZTAT, all resets are power-on resets, regardless of the level on the NMI pin. VCC tOSC1 STBY Hardware standby mode Power-on reset*1 NMI T1 RES Confirm t1min and tNMIS.*2 φ NMI = High RES = Low Notes: 1. Applies to the ZTAT version only. 2. Except for the H8S/2357 ZTAT, all resets are power-on resets, regardless of the level on the NMI pin. Figure E-2 When Pins Settle from the High-Impedance State at Power-On Rev.6.00 Oct.28.2004 page 1012 of 1016 REJ09B0138-0600H Appendix F Timing of Transition to and Recovery from Hardware Standby Mode F.1 Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at least 10 system clock cycles before the STBY signal goes low, as shown below. RES must remain low until STBY signal goes low (delay from STBY low to RES high: 0 ns or more). STBY t1≥10 tcyc RES t2≥0 ns Figure F-1 Timing of Transition to Hardware Standby Mode (2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained, RES does not have to be driven low as in (1). F.2 Timing of Recovery from Hardware Standby Mode Drive the RES signal low and the NMI signal high approximately 100 ns or more before STBY goes high to execute a power-on reset. STBY t≥100 ns RES tOSC tNMIRH NMI Figure F-2 Timing of Recovery from Hardware Standby Mode Rev.6.00 Oct.28.2004 page 1013 of 1016 REJ09B0138-0600H Appendix G Product Code Lineup Table G.1 H8S/2357, H8S/2352 Group Product Code Lineup Product Type H8S/2357 Masked ROM Product Code HD6432357 Mark Code HD6432357TE HD6432357F ZTAT HD6472357 HD6472357TE HD6472357F F-ZTAT HD64F2357 HD64F2357TE HD64F2357F H8S/2352 ROMless HD6412352 HD6412352TE HD6412352F Package (Hitachi Package Code) 120-pin TQFP (TFP-120) 128-pin QFP (FP-128B) 120-pin TQFP (TFP-120) 128-pin QFP (FP-128B) 120-pin TQFP (TFP-120) 128-pin QFP (FP-128B) 120-pin TQFP (TFP-120) 128-pin QFP (FP-128B) Table G.2 H8S/2398, H8S/2394, H8S/2392, H8S/2390 Group Product Code Lineup Product Type H8S/2398 Masked ROM Product Code HD6432398 Mark Code HD6432398TE * 1 HD6432398F * F-ZTAT HD64F2398 1 1 Package (Hitachi Package Code) 120-pin TQFP (TFP-120) 128-pin QFP (FP-128B) 120-pin TQFP (TFP-120) 128-pin QFP (FP-128B) 120-pin TQFP (TFP-120) 128-pin QFP (FP-128B) 1 HD64F2398TE* HD64F2398F* 1 HD64F2398TET HD64F2398FT H8S/2394 ROMless HD6412394 HD6412394TE * HD6412394F * H8S/2392 ROMless HD6412392 1 120-pin TQFP (TFP-120) 128-pin QFP (FP-128B) 120-pin TQFP (TFP-120) 128-pin QFP (FP-128B) 120-pin TQFP (TFP-120) 128-pin QFP (FP-128B) HD6412392TE HD6412392F H8S/2390 ROMless HD6412390 HD6412390TE HD6412390F Rev.6.00 Oct.28.2004 page 1014 of 1016 REJ09B0138-0600H Appendix H Package Dimensions Figures H-1 and H-2 show the TFP-120 and FP-128B package dimensions of the H8S/2357 Group. As of January, 2003 16.0 ± 0.2 14 90 91 61 60 Unit: mm 16.0 ± 0.2 120 1 *0.17 ± 0.05 0.15 ± 0.04 30 31 0.4 1.00 0.07 M 1.2 *0.17 ± 0.05 0.15 ± 0.04 1.20 Max 1.0 0˚ – 8˚ 0.5 ± 0.1 0.10 0.10 ± 0.10 *Dimension including the plating thickness Base material dimension Package Code JEDEC JEITA Mass (reference value) TFP-120 — Conforms 0.5 g Figure H-1 TFP-120 Package Dimension 22.0 ± 0.2 20 102 103 65 64 Unit: mm 16.0 ± 0.2 14 128 1 *0.22 ± 0.05 0.20 ± 0.04 0.10 M 0.75 38 39 3.15 Max 0.5 *0.17 ± 0.05 0.15 ± 0.04 2.70 1.0 0.75 +0.15 –0.10 0.10 0.10 0.5 ± 0.2 Package Code JEDEC JEITA Mass (reference value) FP-128B — Conforms 1.7 g 0° – 8° *Dimension including the plating thickness Base material dimension Figure H-2 FP-128B Package Dimension Rev.6.00 Oct.28.2004 page 1015 of 1016 REJ09B0138-0600H Rev.6.00 Oct.28.2004 page 1016 of 1016 REJ09B0138-0600H Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2357 Group, H8S/2357F-ZTATTM,H8S/2398F-ZTATTM Publication Date: 1st Edition, November, 1997 Rev.6.00, October 28, 2004 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. © 2004. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: 2265-6688, Fax: 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: (2) 2715-2888, Fax: (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: (21) 6472-1001, Fax: (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: 6213-0200, Fax: 6278-8001 http://www.renesas.com Colophon 2.0 H8S/2357 Group, H8S/2357F-ZTATTM, H8S/2398F-ZTATTM Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan