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HA12181FP

HA12181FP

  • 厂商:

    RENESAS(瑞萨)

  • 封装:

  • 描述:

    HA12181FP - AM Radio Noise Reduction System - Renesas Technology Corp

  • 数据手册
  • 价格&库存
HA12181FP 数据手册
HA12181FP AM Radio Noise Reduction System REJ03F0130-0200 (Previous: ADE-207-171A) Rev.2.00 Jun 15, 2005 Functions • • • • Buffer amp. for audio Linear approximate circuit for noise reduction IF Amp., detector, audio amp. and AGC circuit for noise detection Gate pulse generator Features • • • • • High noise cancelling capacity: 46 dB typ. Less gain loss: GV = –0.5 dB typ. Low total harmonic destortion and high signal-to noise ratio: THD = 0.06% typ., S/N = 75 dB typ. Operation supply voltage range: 7.0 V to 10 V (8.2 V typ.) Less external parts count Rev.2.00 Jun 15, 2005 page 1 of 19 HA12181FP Block Diagram R500 100 k IF AGC + C502 0.01µ 3.3µ Det. 1 14 C503 C504 0.22µ R502 22 k 12 15 R505 47 k AF AGC Rev.2.00 Jun 15, 2005 page 2 of 19 IF AGC OR HPF1 LPF IF Input 16 Pulse Det.(1) Gate pulse Gen. IF Amp. LPF Det. Pulse Det. HPF AF AGC Noise AGC Stabi. Volt. AF Amp. 2nd IFT 4 ANT R506 12 k 7 SW2 SW1 1st IFT C501 1000 p Pulse Det.(2) (1) (2) 13 VCC (8.2 V) Gate pulse (1) Gate pulse (2) SW4 + AF Input RF C513 1µ SW3 MIX IF Det. +3 Phase Circuit Hight-pass Amp. (waveform compensation) Buffer Amp. C506 100µ OSC AM-IC 2 5 Stabilized Voltage Circuit Level Diff. Det. Circuit Stabilized Current Circuit (waveform compensation) 6 8 SW5 10 9 11 C500 0.033µ Capacitor for Pahse C512 0.068µ Capacitor for Hold C511 0.033µ AF Output Capacitor C509 + for By-pass R503 0.033µ 180 k C508 C510 R504 1µ 0.033µ Capacitor 4.7 k for waveform compensation Gate Time Constant C507 2200 p Unit R:Ω C:F HA12181FP Table of Pin Description and External Parts External parts DC voltage (V) (No input) 2.7 Influence of External parts Larger than recommended value Longer time to stabilize AGC. Smaller than recommended value Longer distortion of recover. No. of pin 1 Name IF AGC Function Time constant for IF AGC. Equivalent circuit No. R500 C502 C502 3.3µ recommended value 100 K 3.3 µ 1 R500 100k + 2 Bias1 Bypass for voltage Stabi. 3.2 2 C500 0.033µ C500 0.033 µ — Increased noise. 3 AF input Input of AF. 3.3 20k C513 1µ — — 3 + C513 AF IN 4 Bias2 Decide the current of filter network. 1.3 4 R506 12 K Cut off frequency of L·P·F and H·P·F shifted lower. Cut off frequency of L·P·F and H·P·F shifted higher. 5 Phase Phase circuit 3.3 5 C512 0.068µ C512 0.068 µ Must be used on the recommended value. Rev.2.00 Jun 15, 2005 page 3 of 19 HA12181FP Table of Pin Description and External Parts (cont.) External parts DC voltage (V) (No input) 3.3 Influence of External parts Larger than recommended value Smaller than recommended value No. of pin 6 Name Hold Function Hold of level difference. Equivalent circuit No. C511 recommended value 0.033 µ Must be used on the recommended value. 6 C511 0.033µ 7 8 GND HighPass. GND HighPass AMP. (Waveform Compensation) Output of AF — 3.3 — C510 — 0.033 µ — — Must be used on the recommended value. 8 C510 0.033µ 9 AF out 3.3 C508 R504 1µ 4.7 K Output DC cut Output load 9 + C508 1µ R504 4.7k 10 Wave form Waveform Compensation 3.3 C509 0.033 µ Must be used on the recommended value. 10 C509 0.033µ Rev.2.00 Jun 15, 2005 page 4 of 19 HA12181FP Table of Pin Description and External Parts (cont.) External parts DC voltage (V) (No input) 4.5V Influence of External parts Larger than recommended value Gate pulse width become wider. No. of pin 11 Name Gate Function Gate pulse generation Equivalent circuit No. R503 C507 recommended value 180 K 2200 P Smaller than recommended value Gate pulse width become narrow. 0 11 C507 2200p R503 180k 12 Vth Determination of noise detection sensitivity VCC IF AGC detector 1.1 R502 22 K 12 R502 22k Higher noise detection sensitivity. Lower noise detection sensitivity. 13 14 VCC IF Det. 8.2 3.3 — — C503 — 0.01 µ — — — — 14 C503 0.01µ 13 15 AF AGC Time constant for AF AGC 0 R505 C504 47 K 0.22 µ Longer time to stabilize AGC. Missoperation in noise detector. 15 C504 0.22µ R505 47k 16 IF in IF input 1.3 30k IF Input — 16 C501 1000p IF IN Coupling Instability Rev.2.00 Jun 15, 2005 page 5 of 19 HA12181FP Absolute Maximum Ratings (Ta = 25°C) Item Supply voltage Power dissipation Operating temperature Storage temperature Note: 1. Value at Ta = 85°C VCC Pd Topr Tstg Symbol 16 400*1 –40 to +85 –55 to +125 Ratings V mW °C °C Unit Electrical Characteristics (Tentative) (VCC = 8.2 V, Ta = 25°C, Pin 3 input: Vin = 100 mVrms, f = 1 KHz, Pin 16 input: Vin = 74 dBµ, fc = 450 KHz, fm = 1 KHz, m = 30%) Item Supply current Output voltage Total harmonic distortion Signal-to-noise ratio Symbol ICC Vout THD1 S/N (1) Min — 70 — 60 Typ 11.0 95 0.06 75 Max — 120 0.3 — Unit mA mVrms % dB Pin 3 input Vin = 100 mVrms (Reference), Rg = 10 KΩ Pin 3 input Vin = 500 mVrms Pin 16 input only Test Conditions No input signal, IC only Pin 3 input only Strong input total harmonic distortion Recovered output voltage Recovered output signal-to-noise-ratio Noise suppression ratio THD2 VO (AF) S/N (2) NSR — 50 35 35 1.0 78 45 46 2.5 120 — — % mVrms dB dB Input the waveform below. Pin 3 input Vin = 100 mVrms (Reference) no input sine wave 100mV Pin 16 Input 2ms 10µs Figure 1 Input Waveform at Measurement of Noise Suppression Ratio Rev.2.00 Jun 15, 2005 page 6 of 19 HA12181FP Test Circuit VCC (8.2V) Det.Out B + A R505 C504 47k 0.22µ IF-IN PULSE-IN C501 1000p 50 AM-SG R502 R503 C507 C509 15k 180k 2200p 0.033µ C503 0.01µ + R504 4.7k C OUT + C508 1µ C506 100µ 16 15 14 13 12 11 10 9 1 AF-IN + 2 3 4 5 6 7 8 C513 1µ 50 R500 100k AF-SG + C502 3.3µ C500 0.033µ R506 12k C512 C511 0.068µ 0.033µ C510 0.033µ Unit R:Ω C:F Note: 1. Resistors tolerance are within ±5%. 2. Capacitors tolerance (C509 to C512) are within ±5%, other capacitor are within ±10%. Operation Principle Noise Detector 16 IF ANT. 1st IFT A B RF CONV. IF DET C 3 Processing Waveform Circuit 9 Out AM-IC HA12181FP D Figure 2 System Block Diagram of AM Radio Rev.2.00 Jun 15, 2005 page 7 of 19 HA12181FP A system block diagram of AM Radio using the HA12181FP is shown in Figure 2 and waveforms at each point in the system are illustrated in Figure 3. For AM wave with impulse noise from ANT, the pulse spreads its width each time when the AM wave passes through a selection filter. The pulse width becomes the order of several hundred microseconds at detector output (Point C). A radio without a noise canceller produces large noise to the audience. This IC perfectly detects every noise by using the signals from 1st IFT (Point B) in front of the narrow band filter. The wave process circuit approximates the voltage linearly at the pulse to reduce the noise in the output. The principle for wave processing follows. Further investigation make it clear that the pulse width of impulse noise is constant (several handred microseconds) and independent of the waveform or waveheight. Therefore the former and later voltage (VA, VB) of the pulse can be found at the same time (T1) by means of the wave and the delayed one for this time, as shown in the right figure. Each Point in the Figure Waveform including Noise A Narrower Pulse Width and Higher Wave Height B Point D VB Point C C Wider Pulse Width and Lower Wave Height VA T1 T2 D Noiseless Figure 3 Waveforms at Each Point in the System In an actual circuit, the differential voltage between input and output of phase shift circuit is changed to the capacitor C511 at pin 6. At the time of T1, when the switch turns to the noise processing mode (the switch positions in Figure 4 are inverted), the voltage difference (VA – VB) is held in C511. C509 at pin 10 is changed by the differential voltage between the held voltage and the output voltage at pin 9 (VA): VA – (VA – VB) = VB. Rev.2.00 Jun 15, 2005 page 8 of 19 HA12181FP As the initial voltage of C509 is equal to the output voltage (VA) before the switch change, the voltage between terminals of C509 is changed from VA to VB. The waveform which change up to C509 becomes the output, because the voltage of C509 appears at pin 9 through the buffer. The changed up waveform of C509 is almost linearly approximated because of the constant current change by the feedback from the output at pin 9. At the time of T2 when the awitches change to the normal mode (the switch position in Figure 4), the output recovers smoothly as the voltage of C509 is VB. However the unmatch of the wave delay time due to the pulse width or the phase circuit and the offset of circuit make a slight step difference on the waverform at the moment of switch change. LPF, consisting of R1 and C509 make it smooth. The frequency characteristics, which is detriorated by LPF in the normalmode, is compensated so that it might become flat. C509 and C510 should have the same capacity, and the tolerance must be within ±5%. 3 Phase Circuit HPFAmp. R1 Buffer 9 Out + Subtraction – Circuit + Constant Current – Circuit(Subtraction Circuit) R2 5 6 8 10 C512 C511 C510 C509 Figure 4 Waveform Processing Circuit Rev.2.00 Jun 15, 2005 page 9 of 19 HA12181FP Rev.2.00 Jun 15, 2005 page 10 of 19 R500 100 k IF AGC + C502 0.01µ 3.3µ Det. 1 14 15 12 C503 C504 0.22µ R505 47 k AF AGC R502 22 k IF AGC OR HPF1 LPF IF Input 16 Pulse Det.(1) Gate pulse Gen. IF Amp. LPF Det. Pulse Det. HPF AF Amp. AF AGC Stabi. Volt. Noise AGC 2nd IFT 1st IFT 4 C501 1000 p Pulse Det.(2) (1) (2) 13 VCC (8.2 V) Gate pulse (1) Gate pulse (2) + Two signals dummy ANT. R506 12 k 7 SW2 SW1 AF Input 50 Evaluation Circuit for Noise Reduction Effect Pulse SG. RF IF C513 1µ MIX Det. OSC AM-IC 2 5 Stabilized Voltage Circuit +3 Phase Circuit SW3 Hight-pass Amp. (waveform compensation) SW4 Buffer Amp. C506 100µ 50 AM SG. Level Diff. Det. Circuit Stabilized Current Circuit (waveform compensation) 6 8 SW5 C500 0.033µ Capacitor for Pahse C512 0.068µ Capacitor for Hold C511 0.033µ 10 9 11 Gate Time AF Output Capacitor C509 Constant + for By-pass R503 0.033µ C507 180 k C508 C510 2200 p 0.033µ Capacitor 1µ R504 for waveform 4.7 k Noise compensation Meter Unit R:Ω C:F HA12181FP Example of Noise Reduction Effect 20 10 0 Two Signals dummy ANT. VCC=8.2V AM SG : fc=999kHz, m=30%, fm=1kHz Pulse : No input Vout –10 50Ω Output (dB) NRoff 16Ω 16Ω 15p To ANT Pulse SG Output (EMF) 10µs 100mVP-P Pulse SG. 50Ω 16Ω 30Ω 65p –20 –30 –40 Pulse : No input AM SG. 2 µs NRon Noise Figure.2 AM SG : fc=999kHz, no mod. Pulse SG : Refer to Figure.2 –50 –60 0 10 20 30 40 50 60 70 80 AM SG Output (EMF) (dBµ) 90 100 110 120 20 10 0 Two Signals dummy ANT. VCC=8.2V AM SG : fc=999kHz, m=30%, fm=1kHz Pulse : No input Vout –10 50Ω Pulse SG. 50Ω AM SG. 16Ω 16Ω 15p To ANT Pulse SG Output (EMF) 10µs 100mVP-P 10µs Output (dB) –20 NRon NRoff 16Ω 30Ω 65p –30 –40 –50 –60 0 Figure.3 Noise AM SG : fc=999kHz, no mod. Pulse SG : Refer to Figure.2 10 20 30 40 50 60 70 80 AM SG Output (EMF) (dBµ) 90 100 110 120 Rev.2.00 Jun 15, 2005 page 11 of 19 HA12181FP PC Board Layout Pattern C507 VCC + C506 R503 R502 R504 C508 C504 R501 C503 C501 + C509 16 Vout IF in C513 R506 C502 R500 C505 C510 C511 + C512 AF in + HA12181FP (Top view) FN-8648 HA12181FP (Bottom view) Rev.2.00 Jun 15, 2005 page 12 of 19 HA12181FP Main Characteristics 10 0 -2 -4 -6 1.0 -8 -10 -12 0.5 Vin Max (THD ≥ 1.0%) Vin max (Vrms) Vout (dB) Vout : Vin = 100 mVrms const Vout (0 dB = 96 mVrms) 2.0 1.5 0 40 100 200 400 1k f (Hz) 2k 4k 10 k 20 k 50 k 0.5 Vin = 100 mVrms 0.4 THD (%) 0.3 0.2 0.1 0 40 100 200 400 f (Hz) 1k 2k 4k 10 k Rev.2.00 Jun 15, 2005 page 13 of 19 HA12181FP 10 Vo (AF) : 0 dB = 76 mVrms 0 -10 -20 Vout (dB) fc = 450 kHz, m = 30%, fm = 1kHz -30 -40 Noise (no modulation) -50 -60 -70 10 20 30 40 50 60 70 80 90 100 110 120 Vin (EMF) (dBm) 50 Pulse input at Gate ON 10µs V pulse 2ms 20 10 V pulse (mVp-p) 5 2 1 0.5 0.2 1k 5k 10 k R502 (Ω) 50 k 100 k Rev.2.00 Jun 15, 2005 page 14 of 19 HA12181FP Vout (mVrms) THD1 (%) 120 Vout 0.5 100 0.4 80 0.3 60 0.2 40 0.1 20 THD1 0 0 6 7 8 9 10 11 VCC (V) 12 13 14 15 16 THD2 (%) 120 1.0 100 S : 100 mVrms = 0 dB S/N1 (dB) 0.8 80 S/N1 N : no-input 0.6 60 0.4 40 THD2 (Vin = 500 mVrms, f = 1 kHz) 0.2 20 0 0 6 7 8 9 10 11 VCC (V) 12 13 14 15 16 Rev.2.00 Jun 15, 2005 page 15 of 19 HA12181FP Vo (AF) (mVrms) 60 120 S/N2 50 100 40 S/N2 (dB) 80 Vo (AF) 30 60 Vin = 74 dBµ fc = 450 kHz fm = 1 kHZ m = 30% 20 40 10 20 0 0 6 7 8 9 10 11 VCC (V) 12 13 14 15 16 NSR (dB) 60 50 ICC (mA) 60 50 NSR (pulse input) 40 40 30 30 20 20 ICC (no-input) 10 10 0 0 6 7 8 9 10 11 VCC (V) 12 13 14 15 16 Rev.2.00 Jun 15, 2005 page 16 of 19 HA12181FP V pulse (mVp-p) 1.0 0.8 V pulse (Pulse input level at Gate on) 0.6 0.4 0.2 0 6 7 8 9 10 11 VCC (V) Vout (AF) (mVrms) 12 13 14 15 16 0.5 100 Vout 0.4 80 0.3 THD1 (%) 60 VCC = 8.2 V Vin = 100 mVrms, f = 1 kHz 0.2 40 0.1 20 THD1 0 0 -40 -20 0 20 40 60 80 100 Ta (°C) Rev.2.00 Jun 15, 2005 page 17 of 19 HA12181FP NSR (dB) ICC (mA) 60 60 VCC = 8.2 V 50 50 NSR (pulse input) 40 40 30 30 20 20 ICC (no-input) 10 10 0 0 -40 -20 0 20 40 60 80 100 Ta (°C) Rev.2.00 Jun 15, 2005 page 18 of 19 HA12181FP Package Dimensions JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-A Previous Code FP-16DA MASS[Typ.] 0.24g *1 D F 16 9 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp b1 E HE c1 Index mark Reference Symbol *2 c Dimension in Millimeters Min Nom 10.06 5.5 Max 10.5 Terminal cross section 1 Z e *3 D E 8 bp A2 x M L1 A1 A b b c p 1 0.00 0.10 0.20 2.20 0.34 0.42 0.40 0.50 0.17 1 0.22 0.20 0.27 A c θ HE 0° 7.50 7.80 1.27 8° 8.00 θ A1 y L e x y 0.12 0.15 0.80 0.50 1 Detail F Z L L 0.70 1.15 0.90 Rev.2.00 Jun 15, 2005 page 19 of 19 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: 2265-6688, Fax: 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: (2) 2715-2888, Fax: (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: (21) 6472-1001, Fax: (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: 6213-0200, Fax: 6278-8001 http://www.renesas.com © 2005. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon 2.0
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