HA1630S01LPEL-E

Preliminary Data Sheet R2A20135SP R03DS0061EJ0301 Rev.3.01 Jan 08, 2016 LED Lighting Power Controller Description R2A20135 is LED lighting controller IC with dimming function. High accuracy LED current feed-back system makes more efficient LED performance. With non-Isolation step-down control makes it possible to reduce external parts and realize high power factor and efficiency. Moreover, this IC builds in the dimming function and can control many types dimming mode such as Triac, PWM, and DC dimming. Switching mode can chosen Zero Current detect Mode or Fixed Frequency Mode according to the required features. By the Constant On Time control, both modes have power factor correct function. Zero Current detect Mode is better performance for noise immunity, and Fixed Frequency Mode is for power factor correction and THD. Features • Absolute Maximum Ratings ⎯ Supply voltage Vcc: 24 V ⎯ Junction temperature Tj: –40 to +150°C • Electrical characteristics ⎯ UVLO operating start voltage VH: 12 V ± 0.8 V ⎯ UVLO operating shutdown voltage VL: 9.2 V ± 0.7 V ⎯ UVLO hysteresis voltage Hysuvl: 2.8 V ± 0.7 V • Functions ⎯ Dimming function (Triac, PWM, DC dimming) ⎯ Zero current detection mode (when Rrt is OPEN) ⎯ Fixed frequency mode (when Rrt is connected by GND) ⎯ Adjustable switching frequency (when Rrt is connected by GND) ⎯ Package lineup: Pb-free SOP-8 (JEDEC) Ordering Information Part No. R2A20135SP#W5 Package Name — R03DS0061EJ0301 Rev.3.01 Jan 08, 2016 Package Code PRSP0008DJ-A Package Abbreviation SP Taping Abbreviation (Quantity) W (2,500 pcs/reel) Page 1 of 11 R2A20135SP Preliminary Pin Arrangement FB 1 8 VCC COMP 2 7 OUT RT 3 6 GND FB+ 4 5 PWM (Top view) Pin Function Pin No. 1 2 3 4 5 6 7 8 Pin Name FB COMP RT Input/Output Input Output Input/Output Error amplifier input pin Error amplifier output pin A resistor connection pin for RAMP current setting FB+ PWM GND OUT VCC Input/Output Input — Output Input A conductor connection pin for PWM voltage stability and DC dimming Input PWM signal Ground Power MOSFET drive pin Supply voltage pin R03DS0061EJ0301 Rev.3.01 Jan 08, 2016 Function Page 2 of 11 R2A20135SP Preliminary Block Diagram · Rrt: OPEN (Zero Current Detection Mode) VREF: 5.02 V 1V 30 μA + – UVLO 8 VCC OFF: 9.2 V/ON: 12 V – + 8 mV 6 GND COMP 2 Logic Block 4.1 V – FB 1 0.204 V VREF + – 4V 7 OUT – + + + 0.75 μA PWM 5 Error Amp Ramp Control VREF 0.5 μA PWM 1 μA 3 RT 1V 2.7 V/2.5 V 10 pF FB+ 4 · Rrt: Connect to GND (Fixed Frequency Mode) VREF: 5.02 V UVLO 8 VCC OFF: 9.2 V/ON: 12 V 1V + – 6 GND – + COMP 2 4.1 V 1V 30 μA – FB 1 VREF 0.204 V + 0.75 μA PWM 5 4V + – + Error Amp 1V + – Logic Block Max Duty Detect + – 2V 7 OUT VREF PWM Ramp Control 3 2.7 V/2.5 V FB+ 4 R03DS0061EJ0301 Rev.3.01 Jan 08, 2016 RT Rrt 10 pF Page 3 of 11 R2A20135SP Preliminary Absolute Maximum Ratings (Ta = 25°C) Item Power supply voltage FB pin voltage COMP pin voltage RT pin voltage FB+ pin voltage PWM pin voltage OUT pin peak current OUT pin DC current RT pin current PWM pin current Power dissipation Operating ambient temperature Junction temperature Storage temperature Symbol VCC Vt-fb Vt-comp Vt-rt Vt-fb+ Vt-pwm Ipk-snk-out Ipk-src-out Idc-snk-out Idc-src-out Irt Ipwm Pt Ta-opr Tj Tstg Ratings –0.3 to +24 –0.3 to +5 –0.3 to +5 –0.3 to +5 –0.3 to +5 –0.3 to +5 0.9 –0.50 100 –50 –200 to +100 500 0.68 –40 to +125 –40 to +150 –55 to +150 Unit V V V V V V A Note 3 mA μA μA W °C °C °C 4 5 Notes: 1. 2. 3. 4. Rated voltages are with reference to the GND pin. For rated currents, inflow to the IC is indicated by (+), and outflow by (–). Shows the transient current when driving a capacitive load. In case of R2A20135SP: θja = 120°C/W This value is a thing mounting on 40 × 40 × 1.6 [mm], a glass epoxy board of wiring density 10%. 5. Stresses exceeding the absolute maximum ratings may damage the device. These are stress ratings only. Functional operation above the recommended operating ambient temperature range is not implied. Extended exposure to stresses above the absolute maximum ratings may affect device reliability. R03DS0061EJ0301 Rev.3.01 Jan 08, 2016 Page 4 of 11 R2A20135SP Preliminary Electrical Characteristics (Ta = 25°C, VCC = 15 V, FB = COMP, RRT = 200 kΩ) Supply Error amplifier Zero current detector Restart RT PWM FB+ OUT Item UVLO turn-on threshold UVLO turn-off threshold UVLO hysteresis Standby current Operating current Symbol Vuvlh Vuvll Hysuvl Istby Icc Min 11.2 8.5 2.1 — — Typ 12 9.2 2.8 130 2.2 Max 12.8 9.9 3.5 200 3.3 Unit V V V μA mA Feedback voltage Vfb Vfb_min 0.194 — 0.204 0 0.214 — V mV *3 Ifb Av Vclamp_comp –50 — 3.85 –30 63 4.10 –15 — 4.30 μA dB V Vfb = 13 mV — 0.9 — V FB = 0.4 V COMP: Open Minimum feedback voltage Input bias current Open loop gain Upper clamp voltage Test Conditions VCC = Vuvlh – 0.2 V FB = 0 V COMP: Open Low voltage Vl-comp Source current Isrc-comp –14 –9 –5 μA FB = 0 V COMP = 2.5 V Sink current Isnk-comp 12 20 27 μA FB = 1 V COMP = 2.5 V Transconductance gm 25 45 70 μs FB = 0.15 V ↔ 0.25 V COMP = 2.5 V ZCD threshold voltage Vzcd 2 8 14 mV Restart time delay Tstart 45 75 140 μs RAMP offset voltage RAMP amplitude RT voltage1 RT bias current Voffset_ramp dVramp V-rt1 Irt — 2.9 1.9 –0.7 1.0 3.1 2.0 –0.5 — 3.3 2.1 –0.2 V V V μA *2 RT-GND: 200 kΩ RT = 2.5 V Maximum input frequency Input bias current Upper clamp voltage Fpwm_max — — 100 kHz *1 Ipwm Vclamp_pwm –0.35 3.5 –0.75 4.0 –1.5 4.5 μA V Clamp current = 100 μA PWM high threshold voltage Vr_pwm 2.40 2.70 3.00 V PWM low threshold voltage Minimum output voltage Rise time Fall time OUT low voltage Vf_pwm 2.25 2.5 2.75 V Vfb+_lo tr-out tf-out Vol1-out Vol2-out Voh-out fout Dmax — — — — — 14.5 43 47 0 30 30 0.08 0.05 14.8 48 52 10 100 100 0.20 0.70 — 53 57 mV ns ns V V V kHz % OUT high voltage OUT frequency Maximum duty cycle FB = 0 V, COMP = 2.5 V, RT = Open Vpwm = 0 V CL = 1000 pF CL = 1000 pF Isink = 20 mA Isink = 10 mA, VCC = 5 V Isource = –20 mA RT-GND: 200 kΩ RT-GND: 200 kΩ Notes: *1 Design spec *2 dVramp = Vclamp_comp – Voff_ramp *3 There is the possibility of change for the standard value. R03DS0061EJ0301 Rev.3.01 Jan 08, 2016 Page 5 of 11 R2A20135SP Preliminary Waveforms (Zero Current Detection Mode/Fixed Frequency Mode common) 1. Start-up Timing (Zero Current Detection Mode/Fixed Frequency Mode common) 12 V (Vuvlh) VCC 5.02 V 3.6 V VREF VREF GOOD (Internal signal) FB COMP 0.9 V 1V OUT 2. Stop Timing (Zero Current Detection Mode/Fixed Frequency Mode common) 9.2 V (Vuvll) VCC OUT Normal operation R03DS0061EJ0301 Rev.3.01 Jan 08, 2016 Page 6 of 11 R2A20135SP Preliminary 3. Gate Drive Output (Zero Current Detection Mode) COMP RAMP+1V (Internal signal) RAMP (Internal signal) IL 0A FB 8 mV OUT Zero Current Detect Zoom-up COMP RAMP+1V (Internal signal) RAMP (Internal signal) IL 0A CS 8 mV 0.8 μs OUT R03DS0061EJ0301 Rev.3.01 Jan 08, 2016 Page 7 of 11 R2A20135SP Preliminary 4. Gate Drive Output (Fixed Frequency Mode) 4.1 Error Amp Control Mode RAMP+1V (Internal signal) 2V COMP 1V RAMP (Internal signal) IL 0A CS 0V OUT Max Duty 50% 5. PWM Characteristics FB+ (V) 3.23 0.87 0 17 65 100 17 65 100 PWM On Duty (%) Error Amp Ref. (V) 0.204 0 R03DS0061EJ0301 Rev.3.01 Jan 08, 2016 PWM On Duty (%) Page 8 of 11 R2A20135SP Preliminary System Diagram 1. Step-down Fixed Frequency Mode 1.1 Non Dimming Rcs Q1 filter D2 Q From OUT L1 D D3 D1 To FB and CS C1 + Ri1 Ri2 FB From D VCC Z1 Ccomp Rrt COMP OUT RT GND FB+ PWM To Q 1.2 Triac Dimming Rcs Q1 filter D2 Q From OUT L1 Iout D D3 D1 To FB and CS C1 + Ri1 Ri2 From D FB VCC COMP OUT RT GND FB+ PWM Z1 Ccomp Rrt To Q Cfb+ R03DS0061EJ0301 Rev.3.01 Jan 08, 2016 Page 9 of 11 R2A20135SP Preliminary 2. Step-down Zero Current Detection Mode 2.1 Non Dimming D2 Rcs Q1 filter Q From OUT L1 D D3 D1 To FB and CS C1 + Ri1 Ri2 FB From D VCC Z1 Ccomp COMP OUT RT GND FB+ PWM To Q 2.2 Triac Dimming D2 Rcs Q1 filter Q From OUT L1 Iout D D3 D1 To FB and CS C1 + Ri1 Ri2 From D FB VCC COMP OUT RT GND FB+ PWM Z1 Ccomp To Q Cfb+ R03DS0061EJ0301 Rev.3.01 Jan 08, 2016 Page 10 of 11 R2A20135SP Preliminary Package Dimensions JEITA Package Code P-SOP8-3.94x4.93-1.27 RENESAS Code PRSP0008DJ-A *1 Previous Code — MASS[Typ.] 0.073g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F D 8 5 c *2 E HE bp Terminal cross section Reference Symbol (Ni/Pd/Au plating) Index mark 1 Z 4 *3 e bp x M A L1 θ S A1 L y S R03DS0061EJ0301 Rev.3.01 Jan 08, 2016 Detail F D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Dimension in Millimeters Min Nom Max 4.80 4.93 4.98 3.81 3.94 3.99 1.47 0.10 0.15 0.25 1.73 0.35 0.41 0.49 0.19 0° 5.84 0.20 5.99 1.27 0.25 8° 6.20 0.25 0.10 0.41 0.56 0.64 1.03 0.89 Page 11 of 11 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. 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