HM62A16100LBPI-7SL

HM62A16100I Series Wide Temperature Range Version 16 M SRAM (1-Mword × 16-bit) REJ03C0053-0001Z Preliminary Rev. 0.01 Jun.02.2003 Description The Renesas HM62A16100I Series is 16-Mbit static RAM organized 1-Mword × 16-bit. HM62A16100I Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It has the package variations of 48-bump chip size package with 0.75 mm bump pitch for high density surface mounting. Features • Single 1.8 V supply: 1.65 V to 2.2 V • Fast access time: 70 ns (max) • Power dissipation:  Active: 3.6 mW/MHz (typ)  Standby: 0.9 µW (typ) • Completely static memory.  No clock or timing strobe required • Equal access and cycle times • Common data input and output.  Three state output • Battery backup operation.  2 chip selection for battery backup • Temperature range: −40 to +85°C Preliminary: The specification of this device are subject to change without notice. Please contact your nearest Renesas Technology’s Sales Dept. regarding specification. Rev.0.01, Jun.02.2003, page 1 of 17 HM62A16100I Series Ordering Information Type No. HM62A16100LBPI-7 HM62A16100LBPI-7SL Access time 70 ns 70 ns Package 48-bump CSP with 0.75 mm bump pitch (TBP-48F) Rev.0.01, Jun.02.2003, page 2 of 17 HM62A16100I Series Pin Arrangement 48-bumps CSP 1 A 2 3 A0 4 A1 5 A2 6 CS2 LB I/O8 OE UB I/O10 B A3 A4 CS1 I/O1 I/O0 C I/O9 A5 A6 I/O2 D VSS I/O11 A17 A7 I/O3 VCC E VCC I/O12 VSS A16 I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 A19 A12 A13 WE A11 I/O7 H A18 A8 A9 A10 NU (Top view) Pin Description Pin name A0 to A19 I/O0 to I/O15 CS1 CS2 WE OE LB UB VCC VSS NU* 1 Function Address input Data input/output Chip select 1 Chip select 2 Write enable Output enable Lower byte select Upper byte select Power supply Ground Not used (test mode pin) Note: 1. This pin should be connected to a ground (VSS), or not be connected (open). Rev.0.01, Jun.02.2003, page 3 of 17 HM62A16100I Series Block Diagram LSB A19 A8 A9 A10 A11 A12 A13 A14 A16 A18 A15 A3 MSB A6 V CC V SS Row decoder • • • • • Memory matrix 8,192 x 128 x 16 I/O0 Input data control I/O15 • • Column I/O Column decoder • • MSB A17 A7 A5 A4 A2 A1 A0 LSB • • CS1 LB UB WE OE CS2 Control logic Rev.0.01, Jun.02.2003, page 4 of 17 HM62A16100I Series Operation Table CS1 CS1 H × × L L L L L L L CS2 × L × H H H H H H H WE WE × × × H H H L L L H OE × × × L L L × × × H UB UB × × H L H L L H L × LB LB × × H L L H L L H × I/O0 to I/O7 High-Z High-Z High-Z Dout Dout High-Z Din Din High-Z High-Z I/O8 to I/O15 High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din High-Z Operation Standby Standby Standby Read Lower byte read Upper byte read Write Lower byte write Upper byte write Output disable Note: H: VIH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Power supply voltage relative to VSS Terminal voltage on any pin relative to VSS Power dissipation Storage temperature range Storage temperature range under bias Symbol VCC VT PT Tstg Tbias Value −0.3 to + 2.6 −0.3* to VCC + 0.3* 1 2 Unit V V W °C °C 1.0 −55 to +125 −40 to +85 Notes: 1. VT min: −2.0 V for pulse half-width ≤ 10 ns. 2. Maximum voltage is +2.6 V. DC Operating Conditions Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Ambient temperature range Note: VIH VIL Ta Min 1.65 0 −0.3 −40 Typ 1.8 0   Max 2.2 0 VCC + 0.3 85 Unit V V V 1 °C Note 0.75 × VCC  0.25 × VCC V 1. VIL min: −2.0 V for pulse half-width ≤ 10 ns. Rev.0.01, Jun.02.2003, page 5 of 17 HM62A16100I Series DC Characteristics Parameter Input leakage current Output leakage current Symbol Min |ILI| |ILO|   Typ*   1 Max 1 1 Unit µA µA Test conditions Vin = VSS to VCC CS1 = VIH or CS2 = VIL or OE = VIH or WE = VIL or LB = UB = VIH, VI/O = VSS to VCC CS1 = VIL, CS2 = VIH, Others = VIH/ VIL, II/O = 0 mA Min. cycle, duty = 100%, II/O = 0 mA, CS1 = VIL, CS2 = VIH, Others = VIH/VIL Cycle time = 1 µs, duty = 100%, II/O = 0 mA, CS1 ≤ 0.2 V, CS2 ≥ VCC − 0.2 V VIH ≥ VCC − 0.2 V, VIL ≤ 0.2 V CS2 = VIL 0 V ≤ Vin (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS1 ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V or (3) LB = UB ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1 ≤ 0.2 V Average value IOH = −100 µA IOL = 100 µA Operating current Average operating current ICC ICC1    20 8 30 mA mA ICC2  2 5 mA Standby current Standby current ISB ISB1* 2   0.1 0.5 0.5 25 mA µA ISB1* Output high voltage Output low voltage VOH VOL 3   0.5  8  0.2 µA V V VCC − 0.2  Notes: 1. Typical values are at VCC = 1.8 V, Ta = +25°C and not guaranteed. 2. This characteristic is guaranteed only for L-version. 3. This characteristic is guaranteed only for L-SL version. Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Min   Typ   Max 8 10 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V Note 1 1 1. This parameter is sampled and not 100% tested. Rev.0.01, Jun.02.2003, page 6 of 17 HM62A16100I Series AC Characteristics (Ta = −40 to +85°C, VCC = 1.65 V to 2.2 V, unless otherwise noted.) Test Conditions • Input pulse levels: VIL = 0.2 V, VIH = VCC − 0.2 V • Input rise and fall time: 3 ns • Input and output timing reference levels: 0.5 × VCC • Output load: See figures (Including scope and jig) VCC 3K Dout 30pF 3K Rev.0.01, Jun.02.2003, page 7 of 17 HM62A16100I Series Read Cycle HM62A16100I -7 Parameter Read cycle time Address access time Chip select access time Symbol tRC tAA tACS1 tACS2 Output enable to output valid Output hold from address change LB, UB access time Chip select to output in low-Z LB, UB enable to low-Z Output enable to output in low-Z Chip deselect to output in high-Z LB, UB disable to high-Z Output disable to output in high-Z tOE tOH tBA tCLZ1 tCLZ2 tBLZ tOLZ tCHZ1 tCHZ2 tBHZ tOHZ Min 70     10  10 10 5 5 0 0 0 0 Max  70 70 70 35  70     25 25 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2, 3 2, 3 2, 3 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Notes Write Cycle HM62A16100I -7 Parameter Write cycle time Address valid to end of write Chip selection to end of write Write pulse width LB, UB valid to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Output active from end of write Output disable to output in high-Z Write to output in high-Z Symbol tWC tAW tCW tWP tBW tAS tWR tDW tDH tOW tOHZ tWHZ Min 70 60 60 50 60 0 0 30 0 5 0 0 Max           25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns 2 1, 2 1, 2 6 7 5 4 Notes Rev.0.01, Jun.02.2003, page 8 of 17 HM62A16100I Series Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS1, a high CS2, a low WE and a low LB or a low UB. A write begins at the latest transition among CS1 going low, CS2 going high, WE going low and LB going low or UB going low. A write ends at the earliest transition among CS1 going high, CS2 going low, WE going high and LB going high or UB going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1 going low or CS2 going high to the end of write. 6. tAS is measured from the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write cycle. Rev.0.01, Jun.02.2003, page 9 of 17 HM62A16100I Series Timing Waveform Read Cycle t RC Address tAA tACS1 Valid address CS1 tCLZ1 tCHZ1 CS2 tACS2 tCLZ2 tCHZ2 tBHZ tBA LB, UB tBLZ tOE tOHZ OE tOLZ Dout High impedance Valid data tOH Rev.0.01, Jun.02.2003, page 10 of 17 HM62A16100I Series Write Cycle (1) (WE Clock) tWC Address Valid address tWR tCW CS1 tCW CS2 tBW LB, UB tAW tWP WE tAS tDW tDH Din tWHZ Valid data tOW High impedance Dout Rev.0.01, Jun.02.2003, page 11 of 17 HM62A16100I Series Write Cycle (2) (CS1, CS2 Clock, OE = VIH) tWC Address tAS Valid address tAW tCW tWR CS1 tAS CS2 tBW tCW LB, UB tWP WE tDW Din Valid data tDH Dout High impedance Rev.0.01, Jun.02.2003, page 12 of 17 HM62A16100I Series Write Cycle (3) (LB, UB Clock, OE = VIH) tWC Address Valid address tAW tCW CS1 tWR tCW CS2 tAS UB (LB) tBW tBW LB (UB) tWP WE tDW Din-UB (Din-LB) Valid data tDW tDH tDH Din-LB (Din-UB) Dout Valid data High impedance Rev.0.01, Jun.02.2003, page 13 of 17 HM62A16100I Series Low VCC Data Retention Characteristics (Ta = −40 to +85°C) Parameter VCC for data retention Symbol VDR Min 1.0 Typ*  4 Max 2.2 Unit V Test conditions* 3 Vin ≥ 0 V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ VCC − 0.2 V, CS1 ≥ VCC − 0.2 V or (3) LB = UB ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1 ≤ 0.2 V VCC = 1.5 V, Vin ≥ 0 V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ VCC − 0.2 V, CS1 ≥ VCC − 0.2 V or (3) LB = UB ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1 ≤ 0.2 V Average value Data retention current ICCDR* 1  0.5 25 µA ICCDR* Chip deselect to data retention time Operation recovery time tCDR tR 2  0 5 0.5   8   µA ns ms See retention waveforms Notes: 1. This characteristic is guaranteed only for L-version. 2. This characteristic is guaranteed only for L-SL version. 3. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, LB, UB buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE, OE, CS1, LB, UB, I/O) can be in the high impedance state. If CS1 controls data retention mode, CS2 must be CS2 ≥ VCC − 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The other input levels (address, WE, OE, LB, UB, I/O) can be in the high impedance state. 4. Typical values are at VCC = 1.5 V, Ta = +25°C and not guaranteed. Rev.0.01, Jun.02.2003, page 14 of 17 HM62A16100I Series Low VCC Data Retention Timing Waveform (1) (CS1 Controlled) t CDR V CC 1.65 V Data retention mode tR 0.75 × V CC V DR +5 0V CS1 ≥ VCC – 0.2 V Low VCC Data Retention Timing Waveform (2) (CS2 Controlled) t CDR V CC 1.65 V CS2 V DR 0.25 × V CC 0V 0 V < CS2 < 0.2 V Data retention mode tR Low VCC Data Retention Timing Waveform (3) (LB, UB Controlled) t CDR V CC 1.65 V Data retention mode tR 0.75 × V CC V DR LB, UB 0V LB, UB ≥ VCC – 0.2 V Rev.0.01, Jun.02.2003, page 15 of 17 HM62A16100I Series Package Dimensions HM62A16100LBPI Series (TBP-48F) As of January, 2003 Unit: mm 0.20 S B 0.20 S A 2.125 8.00 A 6 5 4 3 A 2 1 INDEX MARK Pin#1 INDEX A B C B 9.50 D E F G 0.75 H 4´ 0.15 0.75 2.125 0.2 S S 48 ´ f0.35 ± 0.05 f0.08 M S A B 0.10 S 0.25 ± 0.05 1.2 Max Details of the part A Package Code JEDEC JEITA Mass (reference value) TBP-48F – – 0.15 g Rev.0.01, Jun.02.2003, page 16 of 17 HM62A16100I Series Sales Strategic Planning Div. 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Renesas Technology Corporation, All rights reserved. Printed in Japan. Colophon 0.0 Rev.0.01, Jun.02.2003, page 17 of 17