HM64YLB36512BP-28

HM64YLB36512 Series 16M Synchronous Late Write Fast Static RAM (512-kword × 36-bit) REJ03C0270-0300 Rev.3.00 Jan.13.2006 Description The HM64YLB36512 is a synchronous fast static RAM organized as 512-kword × 36-bit. It has realized high speed access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119-bump BGA. Note: All power supply and ground pins must be connected for proper operation of the device. Features • • • • • • • • • • • • 2.5 V ± 5% operation and 1.5 V (VDDQ) 16M bit density Byte write control (4 byte write selects, one for each 9-bit) Optional ×18 configuration HSTL compatible I/O Programmable impedance output drivers Asynchronous G output control Asynchronous sleep mode FC-BGA 119pin package with SRAM JEDEC standard pinout Limited set of boundary scan JTAG IEEE 1149.1 compatible Mode selectable among late write, associative late write (late select) and register-latch Late select mode:  Synchronous register to register operation  Late SAS select, selects which half of 72-bit core data to return on reads  SAS serves as way select  Differential HSTL clock inputs • Late write mode:  Synchronous register to register operation  Differential HSTL clock inputs • Register-latch mode:  Synchronous register to latch operation  Differential pseudo-HSTL clock inputs Rev.3.00 Jan 13, 2006 page 1 of 29 HM64YLB36512 Series Ordering Information Type No. HM64YLB36512BP-28 Organization 512k × 36 Modes Access time Cycle time Package Late select mode 1.6 ns 2.8 ns 119-bump 1.27 mm Late write mode 14 mm × 22 mm BGA PRBG0119DB-A (BP-119E) HM64YLB36512BP-33 512k × 36 Late select mode 1.6 ns 3.3 ns Late write mode Register-latch mode 5.5 ns 6.5 ns Note: HM: Hitachi Memory prefix, 64: External Cache SRAM, Y: VDD = 2.5 V, L: Dual Mode SRAM, B: VDDQ = 1.5 V Pin Arrangement 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc7 DQc5 VDDQ DQc3 DQc1 VDDQ DQd1 DQd3 VDDQ DQd5 DQd7 NC NC VDDQ 2 SA14 SA15 SA16 DQc8 DQc6 DQc4 DQc2 DQc0 VDD DQd0 DQd2 DQd4 DQd6 DQd8 SA10 NC TMS 3 SA13 SA12 SA11 VSS VSS VSS SWEc VSS VREF VSS SWEd VSS VSS VSS M1 SA18 TDI 4 NC NC VDD ZQ SS G NC NC VDD K K SWE SA17 SAS/SA0 5 SA6 SA5 SA4 VSS VSS VSS SWEb VSS VREF VSS SWEa VSS VSS VSS M2 SA2 TDO 6 SA7 SA9 SA8 DQb8 DQb6 DQb4 DQb2 DQb0 VDD DQa0 DQa2 DQa4 DQa6 DQa8 SA1 NC NC 7 VDDQ NC NC DQb7 DQb5 VDDQ DQb3 DQb1 VDDQ DQa1 DQa3 VDDQ DQa5 DQa7 NC ZZ VDDQ VDD SA3 TCK (Top view) Note: 4P pin is SAS in both the late select mode and the late write mode, or is SA0 in the register-latch mode. Rev.3.00 Jan 13, 2006 page 2 of 29 HM64YLB36512 Series Block Diagram (Late Select Mode) SA1 to SA18 Read add. reg. Write add. reg. SA1 to SA18 compare 1 0 Memory array (way0) 256k × 36 Memory array (way1) 256k × 36 Match0 SAS Read add. reg. Write add. reg. 01 Match1 01 01 59-N (x: a to d) SWEx 1st reg. SWEx 2nd reg. Byte write control Output reg. Output reg. Din reg. 55 59K SS reg. SWE reg. Way select Output enable 01 / ZQ Impedance control DQxn (x: a to d, n: 0 to 8) Block Diagram (Late Write Mode) SAS SA1 to SA18 Read add. reg. Write add. reg. SAS SA1 to SA18 compare 1 0 Memory array (way0) 512k × 36 Match0 01 59-N (x: a to d) SWEx 1st reg. SWEx 2nd reg. Byte write control Output reg. Din reg. 55 59K SS reg. SWE reg. Output enable / ZQ Impedance control DQxn (x: a to d, n: 0 to 8) Rev.3.00 Jan 13, 2006 page 3 of 29 HM64YLB36512 Series Block Diagram (Register-Latch Mode) SA0 to SA18 Read add. reg. Write add. reg. SA0 to SA18 compare 1 0 Memory array (way0) 512k × 36 Match0 01 59-N (x: a to d) SWEx 1st reg. SWEx 2nd reg. Byte write control Output latch Din reg. 55 59K SS reg. SWE reg. Output enable / ZQ Impedance control DQxn (x: a to d, n: 0 to 8) Rev.3.00 Jan 13, 2006 page 4 of 29 HM64YLB36512 Series Pin Descriptions Name VDD VSS VDDQ VREF K K SS SWE SAn I/O type Supply Supply Supply Supply Input Input Input Input Input Descriptions Core power supply Ground Output power supply Input reference, provides input reference voltage Clock input, active high Clock input, active low Synchronous chip select Synchronous write enable Synchronous address input Notes SAS SWEx G ZZ ZQ DQxn M1, M2 TMS TCK TDI TDO NC M1 Input Input Input Input Input I/O Input Input Input Input Output  M2 Late select: Synchronous way select Late write: Synchronous address input Synchronous byte write enables Asynchronous output enable Power down mode select Output impedance control Synchronous data input/output Output protocol mode select Boundary scan test mode select Boundary scan test clock Boundary scan test data input Boundary scan test data output No connection n: 1 to 18 (Late select mode) (Late write mode) n: 0 to 18 (Register-latch mode) SA0 in the register-latch mode x: a to d 1 x: a to d n: 0 to 8 Protocol Notes VSS VSS Synchronous register to register operation (late select mode) 2 VSS VDD Synchronous register to register operation (late write mode) 3 VDD VSS Synchronous register to latch operation (register-latch mode) 2 Notes: 1. ZQ is to be connected to VSS via a resistance RQ where 175 Ω ≤ RQ ≤ 300 Ω. If ZQ = VDDQ or open, output buffer impedance will be maximum. 2. Mode control pins M1 and M2 are used to select different read protocols. These mode control input pins are set at power-up and will not change the states during the SRAM operates. Late select mode: Single clock, late SAS select, pipelined read protocol Late write mode: Single clock, pipelined read protocol Register-latch mode: Single differential clock register-latch mode protocol 3. Mode control pin M2 can be set to VDDQ instead of VDD. Rev.3.00 Jan 13, 2006 page 5 of 29 HM64YLB36512 Series Truth Table Late select mode Late write mode ZZ SS SS G SWE SWEa SWEb SWEc SWEd K K Operation DQ (n) DQ (n+1) DQ (n) DQ (n+1) Register-latch mode H L × H × × × × × × × × × × × × × L-H × H-L Sleep mode Dead (not selected) Dead (dummy read) Read High-Z × High-Z High-Z High-Z High-Z High-Z × L × H H × × × × × × High-Z × High-Z High-Z L L L H × × × × L-H H-L × DOUT (a, b, c, d) 0 to 8 DIN (a, b, c, d) 0 to 8 DIN (b, c, d) 0 to 8 DIN (a, c, d) 0 to 8 DIN (a, b, d) 0 to 8 DIN (a, b, c) 0 to 8 DIN (c, d) 0 to 8 DIN (a, d) 0 to 8 DIN (a, b) 0 to 8 DIN (b, c) 0 to 8 DIN (d) 0 to 8 DIN (c) 0 to 8 DIN (b) 0 to 8 DIN (a) 0 to 8 DOUT (a, b, c, d) 0 to 8 High-Z × L L × L L L L L L-H H-L Write a, b, c, d byte Write b, c, d byte Write a, c, d byte Write a, b, d byte Write a, b, c byte Write c, d byte Write a, d byte Write a, b byte Write b, c byte Write d byte Write c byte Write b byte Write a byte High-Z DIN (a, b, c, d) 0 to 8 DIN (b, c, d) 0 to 8 DIN (a, c, d) 0 to 8 DIN (a, b, d) 0 to 8 DIN (a, b, c) 0 to 8 DIN (c, d) 0 to 8 DIN (a, d) 0 to 8 DIN (a, b) 0 to 8 DIN (b, c) 0 to 8 DIN (d) 0 to 8 DIN (c) 0 to 8 DIN (b) 0 to 8 DIN (a) 0 to 8 L L × L H L L L L-H H-L High-Z High-Z L L × L L H L L L-H H-L High-Z High-Z L L × L L L H L L-H H-L High-Z High-Z L L × L L L L H L-H H-L High-Z High-Z L L × L H H L L L-H H-L High-Z High-Z L L × L L H H L L-H H-L High-Z High-Z L L × L L L H H L-H H-L High-Z High-Z L L × L H L L H L-H H-L High-Z High-Z L L L L L L L L × × × × L L L L H H H L H H L H H L H H L H H H L-H L-H L-H L-H H-L H-L H-L H-L High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Notes: 1. H: VIH, L: VIL, ×: VIH or VIL 2. SWE, SS, SWEa to SWEd, SA and SAS are sampled at the rising edge of K clock. Rev.3.00 Jan 13, 2006 page 6 of 29 HM64YLB36512 Series Programmable Impedance Output Drivers Output buffer impedance can be programmed by terminating the ZQ pin to VSS through a precision resistor (RQ). The value of RQ is five times the output impedance desired. The allowable value of RQ to guarantee impedance matching with a tolerance of 15% is 250 Ω. If the status of ZQ pin is open, output impedance is maximum value. Maximum impedance also occurs with ZQ connected to VDDQ. The impedance update of the output driver occurs when the SRAM is in high-Z. Write and deselect operations will synchronously switch the SRAM into and out of high-Z, therefore will trigger an update. At power up, the output buffer is in high-Z. It will take 4,096 cycles for the impedance to be completely updated. Absolute Maximum Ratings Parameter Symbol Input voltage on any pin VIN V Core supply voltage VDD V Output supply voltage VDDQ V Operating temperature TOPR °C Storage temperature TSTG °C Output short-circuit current IOUT mA Latch up current ILI mA Package junction to top thermal resistance θJ-top °C/W 5 Package junction to board thermal resistance θJ-board °C/W 5 Notes: 1. All voltage is referenced to VSS. 2. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted the operation conditions. Exposure to higher voltages than recommended voltages for extended periods of time could affect device reliability. 3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables after thermal equilibrium has been established. 4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN. Remember, according to the absolute maximum ratings table, VDDQ is not to exceed 2.1 V, whatever the instantaneous value of VDDQ. 5. See figure below. θJ-top θJ-board Rating −0.5 to VDDQ + 0.5 −0.5 to +3.13 −0.5 to +2.1 0 to +85 −55 to +125 25 200 6.5 12 Unit Notes 1, 4 1 1, 4 Thermocouple Thermo grease Teflon block Thermocouple Water Cold plate SRAM Water SRAM Water JEDEC/2S2P BGA Thermal board Cold plate JEDEC/2S2P Thermal board Water BGA Teflon block Thermo grease Rev.3.00 Jan 13, 2006 page 7 of 29 HM64YLB36512 Series Note: The following DC and AC specifications shown in the tables, this device is tested under the minimum transverse air flow exceeding 500 linear feet per minute. Recommended DC Operating Conditions (Ta = 0 to +85°C) Late select mode Late write mode Symbol Min Typ Max VDD 2.38 2.50 2.63 Register-latch mode Max 2.63 1.60 0.80 Unit Notes V V V 1 4 4 2, 3 3 Parameter Min Typ Power supply 2.38 2.50 voltage: core Power supply VDDQ 1.40 1.50 1.60 1.40 1.50 voltage: I/O Input reference VREF 0.60 0.75 0.90 0.70 0.75 voltage: I/O Input high voltage VIH VREF + 0.10  VDDQ + 0.30 VREF + 0.15  Input low voltage VIL −0.30  VREF − 0.10 −0.50  Clock differential VDIF 0.10  VDDQ + 0.30 0.10  voltage Clock common VCM 0.60  0.90 0.90  mode voltage Notes: 1. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF. 2. Minimum differential input voltage required for differential input clock operation. 3. See figure below. 4. VREF = 0.75 V (typ). VDDQ + 0.50 V VREF − 0.15 V VDDQ + 0.30 V 1.30 V Differential Voltage / Common Mode Voltage VDDQ VDIF VCM VSS Rev.3.00 Jan 13, 2006 page 8 of 29 HM64YLB36512 Series DC Characteristics (Ta = 0 to +85°C, VDD = 2.5 V ± 5%) Late select mode Late write mode Parameter Symbol Min Max Input leakage current ILI  2 Output leakage current ILO  5 Standby current ISBZZ  150 VDD operating current, excluding output drivers IDD  450 Quiescent active power supply current IDD2  200 Maximum power dissipation, including output drivers P  2.3 Parameter Output low voltage Output high voltage Register-latch mode Min Max  2  5  150  350  200  2.3 Unit µA µA mA mA mA W Notes 1 2 3 4 5 6 Symbol Min Typ Max Unit Notes VOL VSS  VSS + 0.4 V 7 VOH1 VDDQ − 0.4  VDDQ V 8 VOH2 1.3  VDDQ V 12 ZQ pin connect resistance RQ  250  Ω Output “Low” current IOL (VDDQ/2) / {(RQ/5) − 15%} (VDDQ/2) / {(RQ/5) + 15%} mA 9, 11 Output “High” current IOH (VDDQ/2) / {(RQ/5) + 15%} (VDDQ/2) / {(RQ/5) − 15%} mA 10, 11 Notes: 1. 0 ≤ VIN ≤ VDDQ for all input pins (except VREF, ZQ, M1, M2 pin) 2. 0 ≤ VOUT ≤ VDDQ, DQ in high-Z 3. All inputs (except clock) are held at either VIH or VIL, ZZ is held at VIH, IOUT = 0 mA. Specification is guaranteed at +75°C junction temperature. 4. IOUT = 0 mA, read 50% / write 50%, VDD = VDD max, frequency = min. cycle 5. IOUT = 0 mA, read 50% / write 50%, VDD = VDD max, frequency = 3 MHz 6. Output drives a 12 pF load and switches every cycle. This parameter should be used by the SRAM designer to determine electrical and package requirements for the SRAM device. 7. RQ = 250 Ω, IOL = 6.8 mA 8. RQ = 250 Ω, IOH = −6.8 mA 9. Measured at VOL = 1/2 VDDQ 10. Measured at VOH = 1/2 VDDQ 11. The total external capacitance of ZQ pin must be less than 7.5 pF. 12. RQ = 250 Ω, IOH = −100 µA Rev.3.00 Jan 13, 2006 page 9 of 29 HM64YLB36512 Series AC Characteristics (Ta = 0 to +85°C, VDD = 2.5 V ± 5%) Late Select Mode, Late Write Mode HM64YLB36512BP -28 -33 Min Max Min Max 2.8  3.3  1.2  1.3  1.2  1.3  0.3  0.3  0.3  0.3  0.6  0.6  0.6  0.6   1.6  1.6 0.65  0.65  0.65  0.65  0.65 2.0 0.65 2.0 0.1  0.1   2.0  2.0  2.0  2.0 20.0  20.0   15.0  15.0 Parameter CK clock cycle time CK clock high width CK clock low width Address setup time Data setup time Address hold time Data hold time Clock high to output valid Clock high to output hold Clock high to output low-Z (SS control) Clock high to output high-Z Output enable low to output low-Z Output enable low to output valid Output enable high to output high-Z Sleep mode recovery time Sleep mode enable time Symbol tKHKH tKHKL tKLKH tAVKH tDVKH tKHAX tKHDX tKHQV tKHQX tKHQX2 tKHQZ tGLQX tGLQV tGHQZ tZZR tZZE Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 2 2 1 1, 6 1, 4, 6 1, 3, 6 1, 4, 6 1, 4 1, 3 5 1, 3, 5 Register-Latch Mode HM64YLB36512BP -33 Min Max        5.5 2.3   2.3  2.3 2.3  15.0 Parameter Symbol Unit Notes CK clock cycle time tKHKH 6.5 ns CK clock high width tKHKL 1.2 ns CK clock low width tKLKH 1.2 ns Address setup time tAVKH 0.4 ns Data setup time tDVKH 0.4 ns Address hold time tKHAX 1.0 ns Data hold time tKHDX 1.0 ns Clock high to output valid tKHQV 1.7 ns Clock low to output valid tKLQV 0.5 ns Clock low to output hold tKLQX 0.5 ns Clock low to output low-Z (SS control) tKLQX2 0.5 ns Clock high to output high-Z tKHQZ 0.5 ns Output enable low to output low-Z tGLQX 0.1 ns Output enable low to output valid tGLQV  ns Output enable high to output high-Z tGHQZ  ns Sleep mode recovery time tZZR 20.0 ns Sleep mode enable time tZZE  ns Notes: 1. See figure in ”AC Test Conditions”. 2. Parameters may be guaranteed by design, i.e., without tester guardband. 3. Transitions are measured ±50 mV of output high impedance from output low impedance. 4. Transitions are measured ±50 mV from steady state voltage. 5. When ZZ is switching, clock input K must be at the same logic level for the reliable operation. 6. Minimum value is verified by design and tested without guardband. 2 2 1 1, 4, 6 1, 3, 6 1, 4, 6 1, 4 1, 3 5 1, 3, 5 Rev.3.00 Jan 13, 2006 page 10 of 29 HM64YLB36512 Series Timing Waveforms (Late Select Mode) Read Cycle-1 tKHKH K, tKHKL tKLKH K tAVKH tKHAX A2 A3 A4 A1 SA SAS A00 tAVKH A10 tKHAX A20 A30 SS SWE SWEx DQ tAVKH tKHAX tKHQX Q0 tKHQV Q1 Q2 Read Cycle-2 (SS Controlled) tKHKH K, K tKHAX SA A1 A3 tAVKH SAS A10 tAVKH tKHAX A30 A4 tKHAX tKHKL tKLKH SS tAVKH tKHAX SWE SWEx tKHQZ DQ Q0 Q1 tKHQX2 Q3 Notes: G, ZZ = VIL, x: a to d Rev.3.00 Jan 13, 2006 page 11 of 29 HM64YLB36512 Series Read Cycle-3 (G Controlled) tKHKH K, K tAVKH SA A1 A2 tKHAX A3 A4 tKHKL tKLKH SAS A00 tAVKH A10 tKHAX A20 A30 SS tAVKH tKHAX SWE SWEx G tGHQZ DQ Q0 Q1 tGLQV tGLQX Q3 Read operation (late select mode) During read cycle, N-1 bits of address (SA) are registered during the first rising clock edge. The Nth bit of address (SAS) is registered one clock edge later (the second edge). The setup time requirements for all address bits are the same. SAS is used as the Nth bit of address on both read and write. The internal array is read between this first edge and second edge, and data is captured in the output register at the second clock edge. This requires the Nth address bit (SAS) to be used as the MUX select before the output register. Alternatively, the Nth address bit can be registered, and used as the MUX select during the data drive cycle. In that case, the output drive should still have a monotonic edge transition (no glitches due to logic switch). Rev.3.00 Jan 13, 2006 page 12 of 29 HM64YLB36512 Series Write Cycle tKHKH K, K tAVKH SA A1 tAVKH SAS A10 tAVKH A20 tKHAX A2 tKHAX A30 A40 tKHAX A3 A4 tKHKL tKLKH SS tAVKH tKHAX tKHAX SWE tAVKH SWEx G tDVKH DQ D0 D1 tKHDX D2 D3 Notes: ZZ = VIL, x: a to d Write operation (late write and late select mode) During writes, the write data follows the write address by one cycle. All N bits of address are presented during the same cycle. Any subsequent read to this address should get the latest data. Because in the actual implementation the data will be written into the SRAM array only after the next write address is received, a one-entry buffer is needed to hold the write data and to allow bypassing of data from the write buffer to the output if there is a read of the same address. Rev.3.00 Jan 13, 2006 page 13 of 29 HM64YLB36512 Series Read-Write Cycle READ tKHKH K, K tAVKH SA SAS A1 tAVKH A10 tAVKH A30 tKHAX tKHAX tKHAX A3 tKHAX A40 A60 tKHAX A4 A6 A7 READ (G control) tKHKL tKLKH WRITE READ DEAD WRITE (SS control) SS tAVKH SWE tAVKH SWEx G DQ Q0 tKHQX tKHQV Q1 tGHQZ tDVKH tKHDX D3 tGLQX tGLQV Q4 tKHQZ D6 Notes: ZZ = VIL, x: a to d ZZ Control tKHKH K, K tAVKH SA SAS A1 tAVKH A10 tAVKH tAVKH tKHAX tKHAX tKHAX tKHAX tKHKL tKLKH SS SWE SWEx ZZ Sleep active DQ Sleep off Q1 tZZR tZZE Sleep active Notes: G = VIL, x: a to d W hen ZZ is switching, clock input K must be at the same logic level for the reliable operation. Rev.3.00 Jan 13, 2006 page 14 of 29 HM64YLB36512 Series Timing Waveforms (Late Write Mode) Read Cycle-1 tKHKH K, K tAVKH SA A1 tAVKH A2 tKHAX tKHAX A3 A4 tKHKL tKLKH SS SWE SWEx DQ tAVKH tKHAX tKHQX Q1 tKHQV Q2 Read Cycle-2 (SS Controlled) tKHKH K, K tAVKH SA A1 tAVKH A3 tKHAX tKHAX A4 tKHKL tKLKH SS tAVKH tKHAX SWE SWEx tKHQZ DQ Q0 Q1 tKHQX2 Q3 Rev.3.00 Jan 13, 2006 page 15 of 29 HM64YLB36512 Series Read Cycle-3 (G Controlled) tKHKH K, K tAVKH SA A1 tAVKH A2 tKHAX tKHAX A3 A4 tKHKL tKLKH SS tAVKH tKHAX SWE SWEx G tGHQZ DQ Q0 Q1 tGLQV tGLQX Q3 Read operation (late write mode) During read cycle, the address is registered during the first rising clock edge, the internal array is read between this first edge and second edge, and data is captured in the output register. Rev.3.00 Jan 13, 2006 page 16 of 29 HM64YLB36512 Series Write Cycle tKHKH K, K tAVKH SA A1 tAVKH A2 tKHAX tKHAX A3 A4 tKHKL tKLKH SS tAVKH tKHAX tKHAX SWE tAVKH SWEx G tDVKH DQ D0 D1 tKHDX D2 D3 Notes: ZZ = VIL, x: a to d Write operation (late write and late select mode) During write cycle, the write data follows the write address by one cycle. All N bits of address are presented during the same cycle. Any subsequent read to this address should get the latest data. Because in the actual implementation the data will be written into the SRAM array only after the next write address is received, a one-entry buffer is needed to hold the write data and to allow bypassing of data from the write buffer to the output if there is a read of the same address. Rev.3.00 Jan 13, 2006 page 17 of 29 HM64YLB36512 Series Read-Write Cycle READ tKHKH K, K tAVKH SA A1 tAVKH A3 tKHAX tKHAX tKHAX tKHAX A4 A6 A7 READ (G control) tKHKL tKLKH WRITE READ DEAD WRITE (SS control) SS tAVKH SWE tAVKH SWEx G DQ Q0 tKHQX tKHQV Q1 tGHQZ tDVKH tKHDX D3 tGLQX tGLQV Q4 tKHQZ D6 Notes: ZZ = VIL, x: a to d ZZ Control tKHKH K, K tAVKH SA A1 tAVKH tAVKH tKHAX tKHAX tKHAX tKHKL tKLKH SS SWE SWEx ZZ Sleep active DQ Sleep off Q1 tZZR tZZE Sleep active Notes: G = VIL, x: a to d W hen ZZ is switching, clock input K must be at the same logic level for the reliable operation. Rev.3.00 Jan 13, 2006 page 18 of 29 HM64YLB36512 Series Timing Waveforms (Register-Latch Mode) Read Cycle-1 tKHKH K, tKHKL tKLKH K tAVKH tKHAX A2 tAVKH tKHAX A3 A4 A1 SA SS tAVKH tKHAX SWE SWEx DQ Q0 tKHQV Q1 tKLQX tKLQV Q2 Q3 Note: ZZ = VIL Read Cycle-2 (SS Controlled) tKHKH K, K tAVKH SA A1 tKHAX A4 tKHKL tKLKH A3 tAVKH tKHAX SS SWE SWEx tKHQV DQ Q0 tKHQZ Q1 tAVKH tKHAX tKLQX2 Q3 Note: ZZ = VIL Rev.3.00 Jan 13, 2006 page 19 of 29 HM64YLB36512 Series Read Cycle-3 (G Controlled) tKHKH K, K tAVKH SA A1 tAVKH A2 tKHAX tKHAX A3 A4 tKHKL tKLKH SS tAVKH tKHAX SWE SWEx G tGHQZ DQ Q0 Q1 Q2 tGLQV tGLQX Q3 Note: ZZ = VIL Write Cycle tKHKH K, K tAVKH SA A1 tAVKH A2 tKHAX tKHAX A3 A4 tKHKL tKLKH SS tAVKH tKHAX tKHAX SWE tAVKH SWEx G tDVKH DQ D0 D1 tKHDX D2 D3 Note: ZZ = VIL Rev.3.00 Jan 13, 2006 page 20 of 29 HM64YLB36512 Series Read-Write Cycle-1 READ tKHKH K, K tAVKH SA A1 A2 tAVKH A3 tKHAX tKHAX tKHAX tKHAX A4 A6 A7 READ tKHKL tKLKH WRITE READ DEAD WRITE (SS control) SS tAVKH SWE tAVKH SWEx G DQ tKHQV Q0 tKLQX tKLQV Q1 tGHQZ tDVKH tKHDX tGLQV Q2 D3 Q4 tGLQX tKHQZ D6 Note: ZZ = VIL Read-Write Cycle-2 READ tKHKH K, K tAVKH SA A1 A2 tAVKH A3 tKHAX tKHAX tKHAX tKHAX A4 A5 A6 A7 READ tKHKL tKLKH WRITE READ DEAD WRITE (SS control) SS tAVKH SWE tAVKH SWEx G DQ Low fixed tKHQV Q0 tKLQX tKLQV Q1 tKHQZ tDVKH tKHDX Q2 D3 Q4 tKLQV tKHQZ D6 Note: G, ZZ = VIL During this period DQ pins are in the output state so that the input signal of opposite phase to the outputs must not be applied. Rev.3.00 Jan 13, 2006 page 21 of 29 HM64YLB36512 Series ZZ Control tKHKH K, K tAVKH SA tAVKH A1 tKHAX tKHAX tKHAX tKHKL tKLKH SS tAVKH SWE SWEx ZZ Sleep active DQ tZZR Sleep off Q1 tZZE Sleep active Rev.3.00 Jan 13, 2006 page 22 of 29 HM64YLB36512 Series Input Capacitance (VDD = 2.5 V, VDDQ = 1.5 V, Ta = +25°C, f = 1 MHz) Parameter Symbol Min Max Unit Pin name Input capacitance CIN  4 pF SAn, SAS, SS, SWE, SWEx Clock input capacitance CCLK  5 pF K, K I/O capacitance CIO  5 pF DQxn Notes: 1. This parameter is sampled and not 100% tested. 2. Exclude G 3. Connect pins to GND, except VDD, VDDQ, and the measured pin. Notes 1, 3 1, 2, 3 1, 3 AC Test Conditions Conditions Late select mode Register-latch mode Parameter Symbol Late write mode Input and output timing reference levels VREF 0.75 0.75 Input signal amplitude VIL, VIH 0.25 to 1.25 0.25 to 1.25 Input rise / fall time tr, tf 0.5 (10% to 90%) 0.5 (10% to 90%) Clock input timing reference level Differential cross point Differential cross point VDIF to clock 0.75 0.75 VCM to clock 0.75 1.10 Output loading conditions See figure below See figure below Note: Parameters are tested with RQ = 250 Ω and VDDQ = 1.5 V. Unit Note V V ns V V Output Loading Conditions 16.7 Ω 16.7 Ω DQ 16.7 Ω 50 Ω 5 pF 50 Ω 5 pF 50 Ω 0.75 V 50 Ω 0.75 V 0.75 V Rev.3.00 Jan 13, 2006 page 23 of 29 HM64YLB36512 Series Boundary Scan Test Access Port Operations Overview In order to perform the interconnect testing of the modules that include this SRAM, the serial boundary scan test access port (TAP) is designed to operate in a manner consistent with IEEE Standard 1149.1 - 1990. But does not implement all of the functions required for 1149.1 compliance. The HM64YLB series contains a TAP controller. Instruction register, boundary scans register, bypass register and ID register. Test Access Port Pins Symbol I/O Name TCK Test clock TMS Test mode select TDI Test data in TDO Test data out Note: This device does not have a TRST (TAP reset) pin. TRST is optional in IEEE 1149.1. To disable the TAP, TCK must be connected to VSS. TDO should be left unconnected. To test boundary scan, the ZZ pin needs to be kept below VREF − 0.4 V. TAP DC Operating Characteristics (Ta = 0 to +85°C) Parameter Boundary scan input high voltage Boundary scan input low voltage Boundary scan input leakage current Boundary scan output low voltage Boundary scan output high voltage Boundary scan output leakage current Notes: 1. 0 ≤ VIN ≤ 3.6 V for all logic input pins 2. IOL = 2 mA at VDD = 2.5 V. 3. IOH = −2 mA at VDD = 2.5 V. 4. 0 ≤ VOUT ≤ VDD, TDO in high-Z Symbol VIH VIL ILI VOL VOH ILO Min 1.4 V −0.3 V −10 µA  2.1 V −5 µA Max 3.6 V 0.8 V +10 µA 0.2 V  +5 µA Notes 1 2 3 4 Rev.3.00 Jan 13, 2006 page 24 of 29 HM64YLB36512 Series TAP AC Operating Characteristics (Ta = 0 to +85°C) Parameter Symbol Min Max Unit Test clock cycle time tTHTH 67  ns Test clock high pulse width tTHTL 30  ns Test clock low pulse width tTLTH 30  ns Test mode select setup tMVTH 10  ns Test mode select hold tTHMX 10  ns Capture setup tCS 10  ns Capture hold tCH 10  ns TDI valid to TCK high tDVTH 10  ns TCK high to TDI don’t care tTHDX 10  ns TCK low to TDO unknown tTLQX 0  ns TCK low to TDO valid tTLQV  20 ns Note: 1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture. Note 1 1 TAP AC Test Conditions (VDD = 2.5 V) Temperature Input timing measurement reference level Input pulse levels Input rise/fall time Output timing measurement reference level Test load termination supply voltage (VT) Output load Boundary Scan AC Test Load VT DUT 50 Ω Z0 = 5 0 Ω TDO 0°C ≤ Ta ≤ +85°C 1.1 V 0 to 2.5 V 1.5 ns typical (10% to 90%) 1.25 V 1.25 V See figure below Rev.3.00 Jan 13, 2006 page 25 of 29 HM64YLB36512 Series TAP Controller Timing Diagram tTHTH TCK tMVTH tTHMX TMS tDVTH tTHDX TDI tTLQV TDO tCS tCH RAM ADDRESS tTLQX tTHTL tTLTH Test Access Port Registers Register name Instruction register Bypass register ID register Boundary scan register Length 3 bits 1 bit 32 bits 70 bits Symbol IR [2:0] BP ID [31:0] BS [70:1] Note TAP Controller Instruction Set Instruction Operation 0 0 0 SAMPLE-Z Tristate all data drivers and capture the pad value 0 0 1 IDCODE 0 1 0 SAMPLE-Z Tristate all data drivers and capture the pad value 0 1 1 BYPASS 1 0 0 SAMPLE 1 0 1 BYPASS 1 1 0 PRIVATE Do not use. They are reserved for vendor use only 1 1 1 BYPASS Note: This device does not perform EXTEST, INTEST or the preload portion of the PRELOAD command in IEEE 1149.1. IR2 IR1 IR0 Rev.3.00 Jan 13, 2006 page 26 of 29 HM64YLB36512 Series Boundary Scan Order (HM64YLB36512) Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 5R 4P 4T 6R 5T 7T 6P 7P 6N 7N 6M 6L 7L 6K 7K 5L 4L 4K 4F 5G 7H 6H 7G 6G 6F 7E 6E 7D 6D 6A 6C 5C 5A 6B 5B Bump ID M2 SAS/SA0 SA3 SA1 SA2 ZZ DQa8 DQa7 DQa6 DQa5 DQa4 DQa2 DQa3 DQa0 DQa1 SWEa K K G SWEb DQb1 DQb0 DQb3 DQb2 DQb4 DQb5 DQb6 DQb7 DQb8 SA7 SA8 SA4 SA6 SA9 SA5 Signal name 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Bit # 3B 2B 3A 3C 2C 2A 2D 1D 2E 1E 2F 2G 1G 2H 1H 3G 4D 4E 4G 4H 4M 3L 1K 2K 1L 2L 2M 1N 2N 1P 2P 3T 2R 4N 3R Bump ID SA12 SA15 SA13 SA11 SA16 SA14 DQc8 DQc7 DQc6 DQc5 DQc4 DQc2 DQc3 DQc0 DQc1 SWEc ZQ SS NC NC SWE SWEd DQd1 DQd0 DQd3 DQd2 DQd4 DQd5 DQd6 DQd7 DQd8 SA18 SA10 SA17 M1 Signal name Notes: 1. Bit#1 is the first scan bit to exit the chip. 2. Bit#2 is SAS in both the late select mode and the late write mode, or is SA0 in the register-latch mode. 3. The NC pads listed in this table are indeed no connects, but are represented in the boundary scan register by a “Place Holder”. Place holder registers are internally connected to VSS. 4. In boundary scan mode, differential input K and K are referenced to each other and must be at the opposite logic levels for the reliable operation. 5. ZZ must remain VIL during boundary scan. 6. In boundary scan mode, ZQ must be driven to VDDQ or VSS supply rail to ensure consistent results. 7. M1 and M2 must be driven to VDD, VDDQ or VSS supply rail to ensure consistent results. Rev.3.00 Jan 13, 2006 page 27 of 29 HM64YLB36512 Series ID Register Revision number (31:28) 0000 Device density and configuration (27:18) 0011100100 Vendor definition (17:12) xxxxxx Vendor JEDEC code (11:1) 00000000111 Start bit (0) 1 Part HM64YLB36512 TAP Controller State Diagram 1 Test-logicreset 0 0 Run-test/ idle 1 SelectDR-scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 1 0 0 1 0 1 1 SelectIR-scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 0 0 1 0 1 Note: The value adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. No matter what the original state of the controller, it will enter Test-logic-reset when TMS is held high for at least five rising edges of TCK. Rev.3.00 Jan 13, 2006 page 28 of 29 HM64YLB36512 Series Package Dimensions HM64YLB36512BP Series (PRBG0119DB-A / Previous Code: BP-119E) JEITA Package Code P-BGA119-14x22-1.27 RENESAS Code PRBG0119DB-A Previous Code BP-119E MASS[Typ.] 1.1g D A 11.08 B 18.04 ×4 v y1 S S ( 0.15 ) E A1 A y S e U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 e Reference Symbol Dimension in Millimeters Min Nom 14.00 22.00 Max D E v w A A1 e b x y y1 SD φ× M S A B φ0.15 M S 0.20 1.80 0.61 0.82 2.02 0.69 1.27 0.88 0.94 0.30 0.20 0.35 2.24 0.77 φb SE ZD ZE Rev.3.00 Jan 13, 2006 page 29 of 29 Revision History HM64YLB36512 Series Data Sheet Description Summary Rev. 0.0 0.1 Date May. 6, 2002 Aug. 30, 2002 1.0 Feb. 7, 2003 2.00 Jul. 19, 2005 3.00 Jan. 13, 2006 Page  Initial issue Truth Table 5 Deletion of Notes3 Input Capacitance 18 Addition of Notes3 6 Change of Programmable Impedance Output Drivers Change format issued by Renesas Technology Corp.  The Former HM64YLB36512BP-33 and the former HM64YLB36514BP-6H are  integrated into the new HM64YLB36512BP-33 Change of Features, adding register-latch mode 1 Ordering Information 2 Addition of Modes Addition of Renesas package codes Pin Arrangement 2 4P: SAS to SAS/SA0 Addition of Note Addition of Block Diagram in register-latch mode 4 Pin Descriptions 5 Change of SAn, SAS Notes, adding register-latch mode Addition of M1, M2 Protocol in register-latch mode Change of Notes2, adding register-latch mode Truth Table: Addition of DQ (n), DQ (n+1) in register-latch mode 6 Change of 7 Programmable Impedance Output Drivers Recommended DC Operating Conditions 8 Addition of the values in register-latch mode DC Characteristics: Addition of the values in register-latch mode 9 AC Characteristics: Addition of the table in register-latch mode 10 19-22 Addition of Timing Waveforms in register-latch mode AC Test Conditions: Addition of the values in register-latch mode 23 Boundary Scan Order 27 Bit#2: SAS to SAS/SA0 Notes2-6 to Notes3-7 Addition of Notes2 Package Dimensions 29 Addition of Renesas package codes Changed to Renesas formats 9 DC Characteristics: VOH to VOH1, addition of VOH2 Sales Strategic Planning Div. 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