ICL7621DCPA

DATASHEET ICL7621 FN3403 Rev.5.00 Mar 4, 2010 Dual, Low Power CMOS Operational Amplifiers The ICL761X/762X series is a family of monolithic CMOS operational amplifiers. These devices provide the designer with high performance operation at low supply voltages and selectable quiescent currents. They are an ideal design tool when ultra low input current and low power dissipation are desired. Features The basic amplifier will operate at supply voltages ranging from 1V to 8V, and may be operated from a single Lithium cell. The output swing ranges to within a few millivolts of the supply voltages. • Available as Duals (Refer to ICL7611 for Singles) The quiescent supply current of these amplifiers is set to 100µA at the factory. This results in power consumption as low as 200µW per amplifier. • Portable Instruments Of particular significance is the extremely low (1pA) input current, input noise current of 0.01pA/Hz, and 1012 input impedance. These features optimize performance in very high source impedance applications. • Meter Amplifiers The inputs are internally protected. Outputs are fully protected against short circuits to ground or to either supply. Pinouts • Wide Operating Voltage Range . . . . . . . . . . . 1V to 8V • High Input Impedance . . . . . . . . . . . . . . . . . . . . . . . 1012 • Input Current Lower Than BIFETs . . . . . . . . . . . 1pA (Typ) • Output Voltage Swing . . . . . . . . . . . . . . . . . . . . V+ and V• Low Power Replacement for Many Standard Op Amps Applications • Telephone Headsets • Hearing Aid/Microphone Amplifiers • Medical Instruments • High Impedance Buffers TEMP. RANGE (°C) -INA 2 +INA 3 V- 4 - - 8 V+ 7 OUTB 6 -INB 5 +INB PKG. DWG. # PART NUMBER PART MARKING ICL7621DCPA 7621 DCPA ICL7621DCPAZ* (Note 2) E8.3 7621 DCPAZ 0 to +70 8 Ld PDIP D Grade - IQ = 100µA ICL7621DCBA (Note 1) 7621 DCBA ICL7621DCBAZ (Notes 1, 2) M8.15 7621 DCBAZ 0 to +70 8 Ld SOIC D Grade - IQ = 100µA PACKAGE 1 + Ordering Information OUTA + Because of the low power dissipation, junction temperature rise and drift are quite low. Applications utilizing these features may include stable instruments, extended life designs, or high density packages. ICL7621 (8 LD PDIP, SOIC) TOP VIEW 0 to +70 8 Ld PDIP E8.3 D Grade - IQ = 100µA M8.15 0 to +70 8 Ld SOIC D Grade - IQ = 100µA *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTES: 1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pbfree material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN3403 Rev.5.00 Mar 4, 2010 Page 1 of 9 ICL7621 Absolute Maximum Ratings Thermal Information Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.3 to V+ +0.3V Differential Input Voltage (Note 3) . . . . . . . . . [(V+ +0.3) - (V- -0.3)]V Duration of Output Short Circuit (Note 4). . . . . . . . . . . . . . Unlimited Thermal Resistance (Typical, Note 5) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C JA (°C/W) JC (°C/W) PDIP Package . . . . . . . . . . . . . . . . . . . 120 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 160 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. Long term offset voltage stability will be degraded if large input differential voltages are applied for long periods of time. 4. The outputs may be shorted to ground or to either supply, for VSUPPLY 10V. Care must be taken to insure that the dissipation rating is not exceeded. 5. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER Input Offset Voltage Temperature Coefficient of VOS Input Offset Current Input Bias Current VSUPPLY = 5V, Unless Otherwise Specified. SYMBOL VOS VOS/T TEST CONDITIONS RS  100k RS  100k IOS IBIAS TEMP. (°C) MIN MAX (Note 6) TYP (Note 6) UNITS +25 - - 15 mV Full - - 20 mV - - 25 - µV/oC +25 - 0.5 30 pA 0 to +70 - - 300 pA -55 to +125 - 800 pA +25 - 1.0 50 pA 0 to +70 - - 400 pA -55 to +125 - - 4000 pA Common Mode Voltage Range VCMR IQ = 100µA +25 4.2 - - V Output Voltage Swing VOUT IQ = 100µA, RL = 100k +25 4.9 - - V 0 to +70 4.8 - - V -55 to +125 4.5 - - V +25 80 102 - dB 0 to +70 75 - - dB -55 to +125 68 - - dB +25 - 0.48 - MHz +25 - 1012 -  Large Signal Voltage Gain Unity Gain Bandwidth Input Resistance AVOL GBW VO = 4.0V, RL = 100k, IQ = 100µA IQ = 100µA RIN Common Mode Rejection Ratio CMRR RS  100k IQ = 100µA +25 70 91 - dB Power Supply Rejection Ratio (VSUPPLY = 8V to 2V) PSRR RS  100k IQ = 100µA +25 80 86 - dB Input Referred Noise Voltage eN RS = 100, f = 1kHz +25 - 100 - nV/Hz Input Referred Noise Current iN RS = 100, f = 1kHz +25 - 0.01 - pA/Hz Supply Current (Per Amplifier) ISUPPLY No Signal, No Load, IQ = 100µA +25 - 0.1 0.25 mA Channel Separation VO1/VO2 AV = 100 +25 - 120 - dB FN3403 Rev.5.00 Mar 4, 2010 Page 2 of 9 ICL7621 VSUPPLY = 5V, Unless Otherwise Specified. (Continued) Electrical Specifications PARAMETER SYMBOL TEMP. (°C) TEST CONDITIONS MIN MAX (Note 6) TYP (Note 6) UNITS Slew Rate SR AV = 1, CL = 100pF, VIN = 8VP-P, IQ = 100µA, RL = 100k +25 - 0.16 - V/µs Rise Time tR VIN = 50mV, CL = 100pF, IQ = 100µA, RL = 100k +25 - 2 - µs Overshoot Factor OS VIN = 50mV, CL = 100pF, IQ = 100µA, RL = 100k +25 - 10 - % NOTE: 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Schematic Diagram IQ SETTING STAGE INPUT STAGE 3k C QP5 QP3 QP7 V- 100k QP2 V+ A 900k 3k QP1 OUTPUT STAGE QP6 QP4 6.3V QP8 V+ +INPUT QP9 QN1 QN2 CFF = 9pF OUTPUT VV+ CC = 33pF -INPUT QN9 QN7 QN4 V- TABLE OF JUMPERS ICL7621 C, E FN3403 Rev.5.00 Mar 4, 2010 IQ 100µA QN10 QN6 QN5 V+ QN3 QN8 QN11 6.3V E G V- Page 3 of 9 ICL7621 Application Information Static Protection Output Stage and Load Driving Considerations All devices are static protected by the use of input diodes. However, strong static fields should be avoided, as it is possible for the strong fields to cause degraded diode junction characteristics, which may result in increased input leakage currents. Each amplifiers’ quiescent current flows primarily in the output stage. This is approximately 70% of the IQ settings. This allows output swings to almost the supply rails for output loads of 1M, 100k, and 10k, using the output stage in a highly linear class A mode. In this mode, crossover distortion is avoided and the voltage gain is maximized. However, the output stage can also be operated in Class AB for higher output currents (see graphs in “Typical Performance Curves” beginning on page 6). During the transition from Class A to Class B operation, the output transfer characteristic is nonlinear and the voltage gain decreases. Latchup Avoidance Junction-isolated CMOS circuits employ configurations which produce a parasitic 4-layer (PNPN) structure. The 4-layer structure has characteristics similar to an SCR, and under certain circumstances may be triggered into a low impedance state resulting in excessive supply current. To avoid this condition, no voltage greater than 0.3V beyond the supply rails may be applied to any pin. In general, the op amp supplies must be established simultaneously with, or before any input signals are applied. If this is not possible, the drive circuits must limit input current flow to 2mA to prevent latchup. The ICL76XX are internally compensated, and are stable for closed loop gains as low as unity with capacitive loads up to 100pF. Typical Applications Choosing the Proper IQ Each device in the ICL76XX family has a similar IQ setup scheme, which allows the amplifier to be set to nominal quiescent currents of 10µA, 100µA or 1mA. These current settings change only very slightly over the entire supply voltage range. The ICL7611/12 have an external IQ control terminal, permitting user selection of each amplifiers’ quiescent current. The ICL7621 has a fixed IQ setting of 100µA. VIN Frequency Compensation The user is cautioned that, due to extremely high input impedances, care must be exercised in layout, construction, board cleanliness, and supply filtering to avoid hum and noise pickup. +5 ICL76XX + VOUT - +5 - VIN ICL76XX VOUT RL  10k + 100k TO CMOS OR LPTTL LOGIC 1M FIGURE 1. SIMPLE FOLLOWER FIGURE 2. LEVEL DETECTOR - 1/2 ICL7621 1M  VOUT + - 1/2 ICL7621 + 1µF + ICL76XX 1M + 1M VV+ DUTY CYCLE 680k WAVEFORM GENERATOR NOTE: Low leakage currents allow integration times up to several hours. FIGURE 3. PHOTOCURRENT INTEGRATOR FN3403 Rev.5.00 Mar 4, 2010 NOTE: Since the output range swings exactly from rail to rail, frequency and duty cycle are virtually independent of power supply variations. FIGURE 4. TRIANGLE/SQUARE WAVE GENERATOR Page 4 of 9 ICL7621 1M +8V VOH 0.5µF VIN 10k 20k 2.2M + 1/2 ICL7621 10µF TO SUCCEEDING INPUT STAGE 20k 1.8k = 5% SCALE ADJUST - + OUT - VOL V- - V+ 1/2 ICL7621 + COMMON TA = +125°C V+ -8V FIGURE 6. BURN-IN AND LIFE TEST CIRCUIT FIGURE 5. AVERAGING AC TO DC CONVERTER FOR A/D CONVERTERS SUCH AS ICL7106, ICL7107, ICL7109, ICL7116, ICL7117 0.2µF 0.2µF 30k 160k + 1/2 ICL7621 0.2µF 680k 100k 51k + 1/2 ICL7621 INPUT - 360k 0.1µF 360k 0.2µF NOTE 7 1M 0.1µF OUTPUT 1M NOTE 7 NOTES: 7. Small capacitors (25pF to 50pF) may be needed for stability in some cases. 8. The low bias currents permit high resistance and low capacitance values to be used to achieve low frequency cutoff. fC = 10Hz, AVCL = 4, Passband ripple = 0.1dB. FIGURE 7. FIFTH ORDER CHEBYCHEV MULTIPLE FEEDBACK LOW PASS FILTER FN3403 Rev.5.00 Mar 4, 2010 Page 5 of 9 ICL7621 Typical Performance Curves 10k 104 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) TA = +25°C NO LOAD NO SIGNAL 1k IQ = 100µA 100 10 1 0 2 4 6 8 10 SUPPLY VOLTAGE (V) 12 14 -25 10 1.0 -25 0 25 50 75 FREE-AIR TEMPERATURE (°C) 100 105 IQ = 100µA 103 102 10 10 100 1k 10k FREQUENCY (Hz) 100k 1M FIGURE 12. LARGE SIGNAL FREQUENCY RESPONSE FN3403 Rev.5.00 Mar 4, 2010 50 75 100 125 VSUPPLY = 10V VOUT = 8V 100 RL = 100k IQ = 100µA 10 1 -75 125 -50 -25 25 0 50 75 100 125 FIGURE 11. LARGE SIGNAL DIFFERENTIAL VOLTAGE GAIN vs FREE-AIR TEMPERATURE COMMON MODE REJECTION RATIO (dB) TA = +25°C VSUPPLY = 15V 1.0 25 FREE-AIR TEMPERATURE (°C) 107 104 0 FIGURE 9. SUPPLY CURRENT PER AMPLIFIER vs FREE-AIR TEMPERATURE DIFFERENTIAL VOLTAGE GAIN (kV/V) INPUT BIAS CURRENT (pA) 100 FIGURE 10. INPUT BIAS CURRENT vs TEMPERATURE DIFFERENTIAL VOLTAGE GAIN (V/V) 10 1000 VS = 5V 1 0.1 IQ = 100µA 102 FREE-AIR TEMPERATURE (°C) 1000 106 103 1 -50 16 FIGURE 8. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY VOLTAGE 0.1 -50 V+ - V- = 10V NO LOAD NO SIGNAL 105 VSUPPLY = 10V 100 95 IQ = 100µA 90 85 80 75 70 -75 -50 -25 0 25 50 75 100 125 FREE-AIR TEMPERATURE (°C) FIGURE 13. COMMON MODE REJECTION RATIO vs FREE-AIR TEMPERATURE Page 6 of 9 ICL7621 (Continued) EQUIVALENT INPUT NOISE VOLTAGE (nV/Hz) SUPPLY VOLTAGE REJECTION RATIO (dB) Typical Performance Curves 100 VSUPPLY = 10V 95 90 IQ = 100µA 85 80 75 70 65 -75 -50 -25 0 25 50 75 100 125 600 TA = +25°C 3V  VSUPPLY  16V 500 400 300 200 100 0 10 100 1k FREQUENCY (Hz) FREE-AIR TEMPERATURE (°C) FIGURE 14. POWER SUPPLY REJECTION RATIO vs FREE-AIR TEMPERATURE MAXIMUM OUTPUT SINK CURRENT (mA) MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE (VP-P) 0.01 VSUPPLY =8V TA = +25°C IQ = 100µA 12 10 8 VSUPPLY =5V 6 4 2 0 100 100k FIGURE 15. EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY 16 14 10k VSUPPLY =2V 1k 10k 100k FREQUENCY (Hz) 1M 10M 0.1 IQ = 100µA 1.0 10 0 2 4 6 8 10 12 14 FIGURE 17. OUTPUT SINK CURRENT vs SUPPLY VOLTAGE FIGURE 16. OUTPUT VOLTAGE vs FREQUENCY INPUT AND OUTPUT VOLTAGE (V) 8 6 TA = +25°C, VSUPPLY = 10V RL = 100k, CL = 100pF 4 2 OUTPUT 0 -2 INPUT -4 -6 0 20 40 60 80 100 120 TIME (µs) FIGURE 18. VOLTAGE FOLLOWER LARGE SIGNAL PULSE RESPONSE (IQ = 100µA) FN3403 Rev.5.00 Mar 4, 2010 16 SUPPLY VOLTAGE (V) Page 7 of 9 ICL7621 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- SEATING PLANE A2 A L D1 e B1 D1 B 0.010 (0.25) M A1 eC C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 C D 0.355 0.400 9.01 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC eB - L 0.115 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 5 D1 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 0.355 10.16 N 8 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 8 6 10.92 7 3.81 4 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN3403 Rev.5.00 Mar 4, 2010 Page 8 of 9 ICL7621 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M B S MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8° 0° N  NOTES: MILLIMETERS MAX A1 e  MIN 8 0° 8 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 7 8° Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. © Copyright Intersil Americas LLC 2001-2010. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN3403 Rev.5.00 Mar 4, 2010 Page 9 of 9