ICL7667CPAZ

DATASHEET ICL7667 FN2853 Rev 7.00 September 4, 2015 Dual Power MOSFET Driver The ICL7667 is a dual monolithic high-speed driver designed to convert TTL level signals into high current outputs at voltages up to 15V. Its high speed and current output enable it to drive large capacitive loads with high slew rates and low propagation delays. With an output voltage swing only millivolts less than the supply voltage and a maximum supply voltage of 15V, the ICL7667 is well suited for driving power MOSFETs in high frequency switched-mode power converters. The ICL7667’s high current outputs minimize power losses in the power MOSFETs by rapidly charging and discharging the gate capacitance. The ICL7667’s inputs are TTL compatible and can be directly driven by common pulse-width modulation control ICs. Features Ordering Information • Direct Interface with Common PWM Control ICs PART NUMBER (Note) PART MARKING TEMP. RANGE (°C) • Fast Rise and Fall Times - 30ns with 1000pF Load • Wide 15V Supply Voltage Range - V+ = +4.5V to +15V - V- = -15V to Ground (0V) • Low Power Consumption - 4mW with Inputs Low - 20mW with Inputs High • TTL/CMOS Input Compatible Power Driver - ROUT = 7 Typ • Pin Equivalent to DS0026/DS0056; TSC426 PACKAGE PKG. DWG. # 7667 CBA ICL7667CBA* (No longer available, recommended replacement: ICL7667CBAZA) 0 to 70 ICL7667CBAZA 7667 CBAZ 0 to 70 8 Ld SOIC (N) M8.15 (Pb-Free) ICL7667CPA* 7667 CPA 0 to 70 8 Ld PDIP E8.3 ICL7667CPAZ 7667 CPAZ 0 to 70 8 Ld PDIP** (Pb-Free) E8.3 8 Ld SOIC (N) M8.15 • Pb-Free Available (RoHS Compliant) Applications • Switching Power Supplies • DC/DC Converters • Motor Controllers Pinout ICL7667 (8 LD PDIP, SOIC) TOP VIEW *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. N/C 1 8 N/C **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. IN A 2 7 OUT A V- 3 6 V+ NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. IN B 4 5 OUT B Functional Diagram (Each Driver) V+  2mA OUT IN V- FN2853 Rev 7.00 September 4, 2015 Page 1 of 11 ICL7667 Absolute Maximum Ratings Thermal Information Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.3V to V+ +0.3V Package Dissipation, TA +25°C . . . . . . . . . . . . . . . . . . . . . . .500mW Thermal Resistance (Typical, Note 1, 2) Operating Conditions ICL7667C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to +70°C Supply Voltages: V+ = +4.5V to +15V; V- = Ground to -15V Logic Inputs: Logic Low = V- < Vin < 0.8V ; Logic High = 2.0V< Vin < V+ JA (°C/W) JC(°C/W) 8 Ld PDIP Package . . . . . . . . . . . . . . . 150 N/A 8 Ld SOIC Package . . . . . . . . . . . . . . . 170 N/A Maximum Storage Temperature Range . . . . . . . . . . . -65° to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C (SOIC - Lead Tips Only) Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air. 2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications PARAMETER Parameters with MIN and/or MAX limits are 100% tested at +25°C, V+ = 0V unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL TEST CONDITIONS ICL7667C, M ICL7667M TA = +25°C 0°C TA  +70°C MIN TYP MAX MIN TYP MAX UNITS DC SPECIFICATIONS Logic 1 Input Voltage VIH V+ = 4.5V 2.0 - - 2.0 - - V Logic 1 Input Voltage VIH V+V+ = 15V 2.0 - - 2.0 - - V Logic 0 Input Voltage VIL V+ = 4.5V - - 0.8 - - 0.5 V Logic 0 Input Voltage VIL V+ = 15V - - 0.8 - - 0.5 V Input Current IIL V+ = 15V, VIN = 0V and 15V -0.1 - 0.1 -0.1 - 0.1 µA Output Voltage High VOH V+ = 4.5V and 15V V+ -0.05 V+ - V+ -0.1 V+ - V Output Voltage Low VOL V+ = 4.5V and 15V - 0 0.05 - - 0.1 V Output Resistance ROUT VIN = VIL, IOUT = -10mA, V+ = 15V - 7 10 - - 12  Output Resistance ROUT VIN = VIH, IOUT = 10mA, V+ = 15V - 8 12 - - 13  Power Supply Current ICC V+ = 15V, VIN = 3V both inputs - 5 7 - - 8 mA Power Supply Current ICC V+ = 15V, VIN = 0V both inputs - 150 400 - - 400 µA SWITCHING SPECIFICATIONS Delay Time TD2 (Figure 3) - 35 50 - - 60 ns Rise Time TR (Figure 3) - 20 30 - - 40 ns Fall Time TF (Figure 3) - 20 30 - - 40 ns TD1 (Figure 3) - 20 30 - - 40 ns Delay Time FN2853 Rev 7.00 September 4, 2015 Page 2 of 11 ICL7667 Test Circuits V+ = 15V +5V + 4.7µF 90% INPUT 0.1µF 10% 0.4V INPUT TD1 OUTPUT CL = 1000pF ICL7667 INPUT RISE AND FALL TIMES  10ns TD2 tr tf 15V 90% 90% OUTPUT 10% 10% 0V Typical Performance Curves 1µs 100 V+ = 15V 90 TD1 AND TD2 (ns) 80 tr AND tf (ns) 100 tRISE 10 CL = 1nF V+ = 15V 70 60 TD2 50 40 TD1 30 20 tFALL 10 1 10 100 1000 10k 0 100k -55 CL (pF) FIGURE 1. RISE AND FALL TIMES vs CL 0 25 70 TEMPERATURE (°C) 125 FIGURE 2. TD1, TD2 vs TEMPERATURE 30 50 CL = 1nF V+ = 15V 40 V+ = 15V 200kHz 10 30 IV+ (mA) tr AND tf (ns) tr AND tf 20 20kHz 3.0 10 0 -55 0 25 70 TEMPERATURE (°C) FIGURE 3. tr , tf vs TEMPERATURE FN2853 Rev 7.00 September 4, 2015 125 1.0 10 100 1k CL (pF) 10k 100k FIGURE 4. IV+ vs CL Page 3 of 11 ICL7667 Typical Performance Curves (Continued) 100 100 IV+ (mA) IV+ (mA) V+ = 15V 10 V+ = 15V 10 V+ = 5V 1 1 V+ = 5V CL = 1nF 100µA 10k 100k 1M 10M CL = 10pF 100mA 10k 100k FREQUENCY (Hz) FIGURE 6. NO LOAD IV+ vs FREQUENCY 50 50 40 40 tr AND tD2 (ns) tD1 AND tf (ns) FIGURE 5. IV+ vs FREQUENCY 30 tf 20 tD1 CL = 1nF 10 V+ (V) 30 tr = TD2 20 10 10 0 5 10M 1M FREQUENCY (Hz) 15 CL = 10pF 0 5 FIGURE 7. DELAY AND FALL TIMES vs V+ 10 V+ (V) 15 FIGURE 8. RISE TIME vs V+ Detailed Description Input Stage The ICL7667 is a dual high-power CMOS inverter whose inputs respond to TTL levels while the outputs can swing as high as 15V. Its high output current enables it to rapidly charge and discharge the gate capacitance of power MOSFETs, minimizing the switching losses in switchmode power supplies. Since the output stage is CMOS, the output will swing to within millivolts of both V- and V+ without any external parts or extra power supplies as required by the DS0026/56 family. Although most specifications are at V+ = 15V, the propagation delays and specifications are almost independent of V+. The input stage is a large N-Channel FET with a P-Channel constant-current source. This circuit has a threshold of about 1.5V, relatively independent of the V+ voltage. This means that the inputs will be directly compatible with TTL over the entire 4.5V - 15V V+ range. Being CMOS, the inputs draw less than 1µA of current over the entire input voltage range of V- to V+. The quiescent current or no load supply current of the ICL7667 is affected by the input voltage, going to nearly zero when the inputs are at the 0 logic level and rising to 7mA maximum when both inputs are at the 1 logic level. A small amount of hysteresis, about 50mV to 100mV at the input, is generated by positive feedback around the second stage. In addition to power MOS drivers, the ICL7667 is well suited for other applications such as bus, control signal, and clock drivers on large memory of microprocessor boards, where the load capacitance is large and low propagation delays are required. Other potential applications include peripheral power drivers and charge-pump voltage inverters. FN2853 Rev 7.00 September 4, 2015 Output Stage The ICL7667 output is a high-power CMOS inverter, swinging between V- and V+. At V+ = 15V, the output impedance of the inverter is typically 7. The high peak current capability of the ICL7667 enables it to drive a 1000pF load with a rise time of Page 4 of 11 ICL7667 only 40ns. Because the output stage impedance is very low, up to 300mA will flow through the series N-Channel and PChannel output devices (from V+ to V-) during output transitions. This crossover current is responsible for a significant portion of the internal power dissipation of the ICL7667 at high frequencies. It can be minimized by keeping the rise and fall times of the input to the ICL7667 below 1µs. Application Notes Although the ICL7667 is simply a dual level-shifting inverter, there are several areas to which careful attention must be paid. Grounding Since the input and the high current output current paths both include the V- pin, it is very important to minimize and common impedance in the ground return. Since the ICL7667 is an inverter, any common impedance will generate negative feedback, and will degrade the delay, rise and fall times. Use a ground plane if possible, or use separate ground returns for the input and output circuits. To minimize any common inductance in the ground return, separate the input and output circuit ground returns as close to the ICL7667 as is possible. Bypassing The rapid charging and discharging of the load capacitance requires very high current spikes from the power supplies. A parallel combination of capacitors that has a low impedance over a wide frequency range should be used. A 4.7µF tantalum capacitor in parallel with a low inductance 0.1µF capacitor is usually sufficient bypassing. Output Damping Ringing is a common problem in any circuit with very fast rise or fall times. Such ringing will be aggravated by long inductive lines with capacitive loads. Techniques to reduce ringing include: • Reduce inductance by making printed circuit board traces as short as possible. • Reduce inductance by using a ground plane or by closely coupling the output lines to their return paths. • Use a 10 to 30 resistor in series with the output of the ICL7667. Although this reduces ringing, it will also slightly increase the rise and fall times. • Use good by-passing techniques to prevent supply voltage ringing. Power Dissipation The power dissipation of the ICL7667 has three main components: 1. Input inverter current loss As noted above, the input inverter current is input voltage dependent, with an IV+ of 0.1mA maximum with a logic 0 input and 6mA maximum with a logic 1 input. The output stage crowbar current is the current that flows through the series N-Channel and P-Channel devices that form the output. This current, about 300mA, occurs only during output transitions. Caution: The inputs should never be allowed to remain between VIL and VIH since this could leave the output stage in a high current mode, rapidly leading to destruction of the device. If only one of the drivers is being used, be sure to tie the unused input to V- or ground. NEVER leave an input floating. The average supply current drawn by the output stage is frequency dependent, as can be seen in Figure 5 (IV+ vs Frequency graph in the Typical Characteristics Graphs). The output stage I2R power dissipation is nothing more than the product of the output current times the voltage drop across the output device. In addition to the current drawn by any resistive load, there will be an output current due to the charging and discharging of the load capacitance. In most high frequency circuits the current used to charge and discharge capacitance dominates, and the power dissipation is approximately: (EQ. 1) P AC = CV V 2 f where C = Load Capacitance, f = Frequency In cases where the load is a power MOSFET and the gate drive requirement are described in terms of gate charge, the ICL7667 power dissipation will be: P AC = QGV V f (EQ. 2) where QG = Charge required to switch the gate, in Coulombs, f = Frequency. Power MOS Driver Circuits Power MOS Driver Requirements Because it has a very high peak current output, the ICL7667 the at driving the gate of power MOS devices. The high current output is important since it minimizes the time the power MOS device is in the linear region. Figure 9 is a typical curve of Charge vs Gate voltage for a power MOSFET. The flat region is caused by the Miller capacitance, where the drain-to-gate capacitance is multiplied by the voltage gain of the FET. This increase in capacitance occurs while the power MOSFET is in the linear region and is dissipating significant amounts of power. The very high current output of the ICL7667 is able to rapidly overcome this high capacitance and quickly turns the MOSFET fully on or off. 2. Output stage crossover current loss 3. Output stage I2R power loss The sum of the above must stay within the specified limits for reliable operation. FN2853 Rev 7.00 September 4, 2015 Page 5 of 11 ICL7667 Transformer Coupled Drive of MOSFETs 18 GATE TO SOURCE VOLTAGE Transformers are often used for isolation between the logic and control section and the power section of a switching regulator. The high output drive capability of the ICL7667 enables it to directly drive such transformers. Figure 11 shows a typical transformer coupled drive circuit. PWM ICs with either active high or active low output can be used in this circuit, since any inversion required can be obtained by reversing the windings on the secondaries. ID = 1A 16 14 VDD = 50V 12 10 VDD = 375V 680pF 8 6 VDD = 200V 4 630pF 2 Buffered Drivers for Multiple MOSFETs 212pF 0 In very high power applications which use a group of MOSFETs in parallel, the input capacitance may be very large and it can be difficult to charge and discharge quickly. Figure 13 shows a circuit which works very well with very large capacitance loads. When the input of the driver is zero, Q1 is held in conduction by the lower half of the ICL7667 and Q2 is clamped off by Q1. When the input goes positive, Q1 is turned off and a current pulse is applied to the gate of Q2 by the upper half of the ICL7667 through the transformer, T1. After about 20ns, T1 saturates and Q2 is held on by its own CGS and the bootstrap circuit of C1, D1 and R1. This bootstrap circuit may not be needed at frequencies greater than 10kHz since the input capacitance of Q2 discharges slowly. -2 0 2 4 6 8 10 12 14 16 18 GATE CHARGE - QG (NANO-COULOMBS) 20 FIGURE 9. MOSFET GATE DYNAMIC CHARACTERISTICS Direct Drive of MOSFETs Figure 11 shows interfaces between the ICL7667 and typical switching regulator ICs. Note that unlike the DS0026, the ICL7667 does not need a dropping resistor and speedup capacitor between it and the regulator IC. The ICL7667, with its high slew rate and high voltage drive can directly drive the gate of the MOSFET. The SG1527 IC is the same as the SG1525 IC, except that the outputs are inverted. This inversion is needed since ICL7667 is an inverting buffer. 15V +165VDC IRF730 V+ +VC A ICL7667 SG1527 IRF730 B GND V- FIGURE 10A. 15V +165VDC 1k +VC V+ IRF730 VOUT C1 E1 ICL7667 TL494 IRF730 C2 GND E2 1k V- +15V FIGURE 10B. FIGURE 10. DIRECT DRIVE OF MOSFET GATES FN2853 Rev 7.00 September 4, 2015 Page 6 of 11 ICL7667 18V CA VIN CB V+ 1µF +165V IRF730 EA 0V 470 ICL7667 CA1524 1µF IRF730 EB -165V 470 V- VOUT FIGURE 11. TRANSFORMER COUPLED DRIVE CIRCUIT V+ 0.1µF 0.1µF 4.7µF IN914 D1 + 4.7F R1 10k 1000pF C1 Q2 1/2 ICL7667 0V - 5V INPUT FROM PWM IC 2200pF FF10 IRFF120 5FF10 1/2 ICL7667 ZL IRFF120 Q1 FIGURE 12. VERY HIGH SPEED DRIVER -4 f = 10kHz -6 +15V + 1/2 ICL7667 - -8 IN4001 -13.5V 10µF IN4001 47µF + VOUT (V) 1kHz - 250kHz SQUARE WAVE IN TTL LEVELS SLOPE = 60 -10 -12 -14 5 FIGURE 13A. FN2853 Rev 7.00 September 4, 2015 20 40 60 IOUT (mA) 80 100 FIGURE 13B. OUTPUT CURRENT vs OUTPUT VOLTAGE FIGURE 13. VOLTAGE INVERTER Page 7 of 11 ICL7667 Other Applications Relay and Lamp Drivers The ICL7667 is suitable for converting low power TTL or CMOS signals into high current, high voltage outputs for relays, lamps and other loads. Unlike many other level translator/driver ICs, the ICL7667 will both source and sink current. The continuous output current is limited to 200mA by the I2R power dissipation in the output FETs. Charge Pump or Voltage Inverters and Doublers The low output impedance and wide V+ range of the ICL7667 make it well suited for charge pump circuits. Figure 13A shows a typical charge pump voltage inverter circuit and a typical performance curve. A common use of this circuit is to provide a low current negative supply for analog circuitry or RS232 drivers. With an input voltage of +15V, this circuit will deliver 20mA at -12.6V. By increasing the size of the capacitors, the current capability can be increased and the voltage loss decreased. The practical range of the input frequency is 500Hz to 250kHz. As the frequency goes up, the charge pump capacitors can be made smaller, but the internal losses in the ICL7667 will rise, reducing the circuit efficiency. Clock Driver Some microprocessors (such as the CDP68HC05 families) use a clock signal to control the various LSI peripherals of the family. The ICL7667s combination of low propagation delay, high current drive capability and wide voltage swing make it attractive for this application. Although the ICL7667 is primarily intended for driving power MOSFET gates at 15V, the ICL7667 also works well as a 5V high-speed buffer. Unlike standard 4000 series CMOS, the ICL7667 uses short channel length FETs and the ICL7667 is only slightly slower at 5V than at 15V. +15 +15V 1kHz - 250kHz SQUARE WAVE IN TTL LEVELS IN4001 + 1/2 ICL7667 - 10µF 28.5V IN4001 + 47µF FIGURE 14. VOLTAGE DOUBLER Figure 14, a voltage doubler, is very similar in both circuitry and performance. A potential use of Figure 13 would be to supply the higher voltage needed for EEPROM or EPROM programming. FN2853 Rev 7.00 September 4, 2015 Page 8 of 11 ICL7667 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE September 4, 2015 FN2853.7 Updated the Ordering Information table on page 1. Added Revision History and About Intersil sections. Updated Package Outlind Drawing M8.15 to the latest revision. -Rev 1 to Rev 2 changes - Updated to new POD format by removing table and moving dimensions onto drawing and adding land pattern -Rev 2 to Rev 3 changes - Changed in Typical Recommended Land Pattern the following: 2.41(0.095) to 2.20(0.087) 0.76 (0.030) to 0.60(0.023) 0.200 to 5.20(0.205) -Rev 3 to Rev 4 changes - Changed Note 1 "1982" to "1994" About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. FN2853 Rev 7.00 September 4, 2015 Page 9 of 11 ICL7667 Package Outline Drawing M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) 5.80 (0.228) AREA 0.50 (0.20) x 45° 0.25 (0.01) 4.00 (0.157) 3.80 (0.150) 1 2 8° 0° 3 0.25 (0.010) 0.19 (0.008) SIDE VIEW “B” TOP VIEW 2.20 (0.087) SEATING PLANE 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 1 8 2 7 0.60 (0.023) 1.27 (0.050) 3 6 4 5 -C- 1.27 (0.050) 0.51(0.020) 0.33(0.013) SIDE VIEW “A 0.25(0.010) 0.10(0.004) 5.20(0.205) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. FN2853 Rev 7.00 September 4, 2015 Page 10 of 11 ICL7667 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- SEATING PLANE A2 A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 C D 0.355 0.400 9.01 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - L 0.115 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 0.355 10.16 N 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 8 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 8 6 10.92 7 3.81 4 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). © Copyright Intersil Americas LLC 1999-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2853 Rev 7.00 September 4, 2015 Page 11 of 11