DATASHEET
ICS2059-02
CLOCK MULTIPLIER AND JITTER ATTENUATOR
Description
Features
The ICS2059-02 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock multiplier and jitter attenuator
designed for system clock distribution applications.
This monolithic IC, combined with an external
inexpensive quartz crystal, can be used to replace a
more costly hybrid VCXO retiming module. A dual input
mux is also provided.
• Excellent jitter attenuation for telecom and video
By controlling the VCXO frequency within a
phase-locked loop (PLL), the output clock is phase and
frequency locked to the input clock. Through selection
of external loop filter components, the PLL loop
bandwidth and damping factor can be tailored to meet
system clock requirements. A loop bandwidth down to
the Hz range is possible.
• Output clock is phase and frequency locked to the
clocks
• 2:1 Input MUX for input reference clocks
• No switching glitches on output
• VCXO-based clock generation offers very low jitter
and phase noise generation
selected input reference clock
• Fixed input to output phase relationship
• +115 ppm minimum crystal frequency pullability
range, using recommended crystal
•
•
•
•
Industrial temperature range
Low power CMOS technology
16-pin TSSOP package
Single 3.3 V power supply
Block Diagram
Pullable Crystal
X1
ISET
Input Clock ICLK2
Input Clock ICLK1
1
0
Phase
Detector
VDD
X2
VCXO
3
Selectable
Divider
CLK
Charge
Pump
ISEL
SEL1:0
VDD
2
VIN
CHGP
IDT™ / ICS™ CLOCK MULTIPLIER AND JITTER ATTENUATOR
1
GND
2
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VCXO AND SYNTHESIZERS
Pin Assignment
Output Frequency Select Table
X1
1
16
X2
VDD
2
15
ISEL
VDD
3
14
ICLK1
VDD
4
13
ICLK2
VIN
5
12
SEL0
Input
GND
6
11
CLK
GND
7
10
SEL1
CHGP
8
9
ISET
SEL1 SEL0
8 kHz
8 kHz
15.625 kHz
15.734265 kHz
151.875 kHz
27 MHz
0
0
1
1
M
M
0
1
0
1
0
1
N
1296
2430
1728
1716
128
1
Output Clock Crystal Used
(MHz)
(MHz)
10.368
20.736
19.44
19.44
27
27
27
27
19.44
19.44
27
27
Note: For SEL input pin programming:
0 = GND, 1 = VDD, M = Floating
16- pin ( 173 mil) TSSOP
Pin Descriptions
Pin
Number
1
2
3
4
5
Pin
Name
X1
VDD
VDD
VDD
VIN
Pin
Type
—
Power
Power
Power
Input
6
7
8
GND
GND
CHGP
Power
Power
Output
9
10
ISET
SEL1
—
Input
11
12
CLK
SEL0
Output
Input
13
ICLK2
Input
14
ICLK1
Input
15
ISEL
Input
16
X2
—
Pin Description
Crystal Input. Connect this pin to the specified crystal.
Power Supply. Connect to +3.3 V.
Power Supply. Connect to +3.3 V.
Power Supply. Connect to +3.3 V.
VCXO Control Voltage Input. Connect this pin to CHGP pin and the
external loop filter as shown in this data sheet.
Connect to ground.
Connect to ground.
Charge Pump Output. Connect this pin to the external loop filter and to
pin VIN.
Charge pump current setting node, connection for setting resistor.
Output Frequency Selection Pin 1. Determines output frequency as
per table above. Includes mid-level input.
Clock Output.
Output Frequency Selection Pin 0. Determines output frequency as
per table above. Internal pull-up resistor.
Input Clock Connection 2. Connect an input reference clock to this pin.
If unused, connect to ground.
Input Clock Connection 1. Connect an input reference clock to this pin.
If unused, connect to ground.
Input Selection. Used to select which reference input clock is active.
Low input level selects ICLK1, high input level selects ICLK2. Internal
pull-up resistor.
Crystal Output. Connect this pin to the specified crystal.
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Functional Description
generated due to the “fly-wheel” effect of the VCXO (the
quartz crystal is a high-Q tuned circuit). When the input
clocks are not phase aligned, the phase of the output
clock will change to reflect the phase of the newly
selected input at a controlled phase slope (rate of phase
change) as influenced by the PLL loop characteristics.
The ICS2059-02 is a clock generator IC that generates
an output clock directly from an internal VCXO circuit
which works in conjunction with an external quartz
crystal. The VCXO is controlled by an internal PLL
(Phase-Locked Loop) circuit, enabling the device to
perform clock regeneration from an input reference
clock. The ICS2059-02 is configured to provide an
output clock that is the same frequency as the input
clock. There are 12 selectable input / output frequency
ranges, each of which is a submultiple of the supported
quartz crystal frequency range. Please refer to the
Output Clock Selection Table on Page 2.
Quartz Crystal
It is important that the correct type of quartz crystal is
used with the ICS2059-02. Failure to do so may result
in reduced frequency pullability range, inability of the
loop to lock, or excessive output phase jitter.
The ICS2059-02 operates by phase-locking the VCXO
circuit to the input signal of the selected ICLK input. The
VCXO consists of the external crystal and the
integrated VCXO oscillator circuit. To achieve the best
performance and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the PCB
Layout Recommendations section must be followed.
Most typical PLL clock devices use an internal VCO
(Voltage Controlled Oscillator) for output clock
generation. By using a VCXO with an external crystal,
the ICS2059-02 is able to generate a low jitter, low
phase-noise output clock within a low bandwidth PLL.
This serves to provide input clock jitter attenuation and
enables stable operation with a low-frequency
reference clock.
The frequency of oscillation of a quartz crystal is
determined by its cut and by the external load
capacitance. The ICS2059-02 incorporates variable
load capacitors on-chip which “pull”, or change, the
frequency of the crystal. The crystals specified for use
with the ICS2059-02 are designed to have zero
frequency error when the total of on-chip + stray
capacitance is 14 pF. To achieve this, the layout should
use short traces between the ICS2059-02 and the
crystal.
The VCXO circuit requires an external pullable crystal
for operation. External loop filter components enable a
PLL configuration with low loop bandwidth.
Application Information
Input / Output Frequency Configuration
The ICS2059-02 is configured to generate an output
frequency that is equal to the input reference frequency.
Clock frequencies that are supported are those which
fall into the ranges listed in the Output Clock Selection
Table on Page 2. Input bits SEL2:0 are set according to
this table, as is the external crystal frequency. Other
input/output frequency combinations can be used if the
necessary integer multiplication factor “N” appears in
the Output Frequency Select table. fro example, 20
MHz can be generated from 156.25 kHz by using select
M0, as N=128.
A complete description of the recommended crystal
parameters is in application note MAN05.
PLL Loop Filter Components
All analog PLL circuits use a loop filter to establish
operating stability. The ICS2059-02 uses external loop
filter components for the following reasons:
1) Larger loop filter capacitor values can be used,
allowing a lower loop bandwidth. This enables the use
of lower input clock reference frequencies and also
input clock jitter attenuation capabilities. Larger loop
filter capacitors also allow higher loop damping factors
when less passband peaking is desired.
Input Mux
The Input Mux serves to select between two alternate
input reference clocks. Upon reselection of the input
clock, clock glitches on the output clock will not be
IDT™ / ICS™ CLOCK MULTIPLIER AND JITTER ATTENUATOR
2) The loop filter values can be user selected to
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External Component Schematic
optimize loop response characteristics for a given
application.
CL
Referencing the External Component Schematic on this
page, the external loop filter is made up of the
components RZ, C1 and C2. RSET establishes PLL
charge pump current and therefore influences loop filter
characteristics.
CL
(Refer to Crystal
Tuning section)
Crystal
X1
RS
P
CS
1
X2
16
VDD
2
15
VDD
3
14
ICLK1
VDD
VIN
4
13
ICLK2
5
12
SEL0
GND
6
11
CLK
GND
7
10
SEL1
8
9
CHGP
ISEL
16-pin (173 mil) TSSOP
ISET
R SET
Recommended Loop Filter Values Vs. Output Frequency Range Selection
Crystal
SEL1 SEL0 Multiplier
0
0
1
1
M
M
0
1
0
1
0
1
(N)
2592
2430
1728
1716
128
1
RSET
RS
CS
CP
180 kΩ
120 kΩ
330 kΩ
330 kΩ
120 kΩ
1 MΩ
820 kΩ
560 kΩ
680 kΩ
680 kΩ
330 kΩ
22 kΩ
0.47 µF
0.68 µF
0.68 µF
0.68 µF
1 µF
1 µF
1.8 nF
3.3 nF
3.9 nF
3.9 nF
3.3 nF
3.3 nF
Loop
Bandwidth
Damping
Factor
(-3dB point)
11.2 Hz
11.8 Hz
11.5 Hz
11.5 Hz
14.5 Hz
204.2 Hz
3.00
2.97
3.17
3.18
3.16
3.08
Note: For SEL input pin programming: 0 = GND, 1 = VDD, M = Floating
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A “normalized” PLL loop bandwidth may be calculated
as follows:
Charge Pump Current Table
R S × I CP ×345
575
NBW = ----------------------------------------N
RSET
1.4 MΩ
680 kΩ
540 kΩ
120 kΩ
The “normalized” bandwidth equation above does not
take into account the effects of damping factor or the
second pole. However, it does provide a useful
approximation of filter performance.
Special considerations must be made in choosing loop
components CS and CP. Series Termination Resistor
The loop damping factor is calculated as follows:
Damping Factor = R S ×
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω. (The optional series termination resistor
is not shown in the External Component Schematic.)
375
625 × I CP × C S
------------------------------------------N
Where:
RS = Value of resistor in loop filter (Ohms)
ICP = Charge pump current (amps)
(refer to Charge Pump Current Table, below)
N = Crystal multiplier shown in the above
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS2059-02 must be isolated from system power
supply noise to perform optimally.
table
CS = Value of capacitor C1 in loop filter (Farads)
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To
further guard against interfering system supply noise,
the ICS2059-02 should use one common connection to
the PCB power plane as shown in the diagram on the
next page. The ferrite bead and bulk capacitor help
reduce lower frequency noise in the supply that can
lead to output clock phase modulation.
As a general rule, the following relationship should be
maintained between components C1 and C2 in the loop
filter:
C
CP
Charge Pump Current
(ICP)
10 µA
20 µA
25 µA
100 µA
= -----S20
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Recommended Power Supply Connection for
Optimal Device Performance
trace to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via. Distance of the
ferrite bead and bulk decoupling from the device is less
critical.
V D D P in
C onnection to 3.3V
P ow er P lane
Ferrite
Bead
B ulk D ecoupling C apacitor
(such as 1 F Tantalum )
0.01
2) The loop filter components must also be placed close
to the CHGP and VIN pins. CP should be closest to the
device. Coupling of noise from other system signal
traces should be minimized by keeping traces short and
away from active signal traces. Use of vias should be
avoided.
V D D P in
V D D P in
3) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
F D ecoupling C apacitors
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground, shown as CL in the External Component
Schematic. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device.
4) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
5) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS2059-02.
This includes signal traces just underneath the device,
or on layers adjacent to the ground plane layer used by
the device.
In most cases the load capacitors will not be required.
They should not be stuffed on the prototype evaluation
board as the indiscriminate use of these trim capacitors
will typically cause more crystal centering error than
their absence. If the need for the load capacitors is later
determined, the values will fall within the 1-4 pf range.
The need for, and value of, these trim capacitors can
only be determined at prototype evaluation. Please
refer to MAN05 for the procedure to determine the
component values.
The IDT Applications Note MAN05 may also be
referenced for additional suggestions on layout of the
crystal section.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed. Please also refer to the Recommended PCB
Layout drawing on page 7.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
IDT™ / ICS™ CLOCK MULTIPLIER AND JITTER ATTENUATOR
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Recommended PCB Layout
For minimum output clock jitter,
remove ground and power plane
within this entire area. Also route
all other traces away from this area.
G
For minimum output clock jitter,
device VDD connections should
be made to common bulk
decoupling device (see text).
1
2
3
4
5
6
7
8
G
G
G
16
15
14
13
12
11
10
9
G
G
G
G
Legend:
G
= Ground
Connection
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS2059-02. These ratings,
which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
-40 to +85° C
Storage Temperature
-65 to +150° C
Junction Temperature
125° C
Soldering Temperature
260° C
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Recommended Operation Conditions
Parameter
Min.
Ambient Operating Temperature
Typ.
Max.
Units
+85
°C
+3.45
V
-40
Power Supply Voltage (measured in respect to GND)
+3.15
+3.3
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
3.15
3.3
3.45
V
10
15
mA
Operating Voltage
VDD
Supply Current
IDD
Input High Voltage, SEL1
VIH
Input Low Voltage, SEL1
VIL
Input High Voltage, ISEL,
SEL0
VIH
Input Low Voltage, ISEL, SEL0
VIL
Input High Voltage, ICLK1, 2
VIH
Input Low Voltage, ICLK1, 2
VIL
Input High Current
IIH
VIH = VDD
Input Low Current
IIL
VIL = 0
Input Capacitance, except X1
CIN
Output High Voltage (CMOS
Level)
VOH
IOH = -4 mA
VDD-0.4
V
Output High Voltage
VOH
IOH = -8 mA
2.4
V
Output Low Voltage
VOL
IOL = 8 mA
Short Circuit Current
IOS
VIN, VCXO Control Voltage
VXC
Nominal Output Impedance
ZOUT
IDT™ / ICS™ CLOCK MULTIPLIER AND JITTER ATTENUATOR
Clock outputs
unloaded, VDD = 3.3 V
VDD-0.5
V
0.5
2
V
0.8
V
V
VDD/2+1
VDD/2-1
V
-10
+10
µA
-10
+10
µA
7
pF
0.4
±50
0
V
mA
VDD
V
Ω
20
8
V
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CLOCK MULTIPLIER AND JITTER ATTENUATOR
VCXO AND SYNTHESIZERS
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
VCXO Crystal Pull Range
fXP
VCXO Crystal Nominal
Frequency
fX
Input Jitter Tolerance
tji
Input pulse width (1)
tpi
Output Frequency Error
Conditions
Using recommended
crystal
Min.
Typ. Max. Units
-115
+115
ppm
8.5
27
MHz
0.4
UI
10
FOUT
ICLK = 0 ppm error
0
Output Duty Cycle
(% high time)
tOD
Measured at VDD/2,
CL=15 pF
40
Output Rise Time
tOR
Output Fall Time
ns
0
0
ppm
60
%
0.8 to 2.0V , CL=15 pF
1.5
ns
tOF
2.0 to 0.8 V, CL=15 pF
1.5
ns
Skew, Input to Output Clock
tIO
27 MHz output, rising
edges, CL=15 pF
+5
ns
Cycle Jitter (short term jitter)
tja
150
ps p-p
Timing Jitter, Filtered
500 Hz-1.3 MHz (OC-3)
tjf
210
ps p-p
Timing Jitter, Filtered
65 kHz-1.3 MHz (OC-3)
tjf
150
ps p-p
Typ.
Max. Units
-5
Note 1: Minimum high or low time of input clock.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Thermal Resistance Junction to
Ambient
θ JA
Still air
78
° C/W
θ JA
1 m/s air flow
70
° C/W
θ JA
3 m/s air flow
68
° C/W
Thermal Resistance Junction to Case
θ JC
37
° C/W
IDT™ / ICS™ CLOCK MULTIPLIER AND JITTER ATTENUATOR
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Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
16
Millimeters
Symbol
E1
A
A1
A2
b
C
D
E
E1
e
L
α
aaa
E
IN D EX
AR EA
1
2
D
A
2
Min
Inches
Max
Min
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
4.90
5.1
6.40 BASIC
4.30
4.50
0.65 Basic
0.45
0.75
0°
8°
-0.10
Max
-0.047
0.002
0.006
0.032
0.041
0.007
0.012
0.0035 0.008
0.193
0.201
0.252 BASIC
0.169
0.177
0.0256 Basic
0.018
0.030
0°
8°
-0.004
A
A
1
c
-C e
S E A TIN G
P LA N E
b
L
aaa C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
2059GI-02LF
2059GI-02LFT
Temperature
2059GI02L
Tubes
16-pin TSSOP
-40 to +85° C
2059GI02L
Tape and Reel
16-pin TSSOP
-40 to +85° C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration andare RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result
from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any
circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or
critical medical instruments.
IDT™ / ICS™ CLOCK MULTIPLIER AND JITTER ATTENUATOR
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Revision History
Rev.
Originator
Date
Description of Change
A
P.Griffith
11/19/04
New device/datasheet. Change proposal number from 4MPG019 to ICS2059-02. Move
from Advance to Preliminary.
B
P.Griffith
11/29/04
Updated values for “Loop Bandwidth” and” Damping Factor” in “Recommended Loop
Filter Values vs Output Frequency Range Selection” table;
C
P.Griffith
03/16/05
Released to Final and standard, general purpose device.
D
R.W.
08/11/09
Added EOL note for non-green parts per PDN U-09-01.
E
R.W.
05/13/10
Removed EOL note for non-green parts per PDN U-09-01.
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