ICS276PG

DATASHEET TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER Description Features The ICS276 field programmable VCXO clock synthesizer generates up to three high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency crystal input. It is designed to replace crystals and crystal oscillators in most electronic systems. • • • • • • • • • • • Using IDT’s VersaClockTM software to configure PLLs and outputs, the ICS276 contains a One-Time Programmable (OTP) ROM for field programmability. Programming features include VCXO and eight selectable configuration registers. Each of the outputs are powered by a single VDDO voltage. VDDO may vary from 1.8 V to VDD. Using Phase-Locked Loop (PLL) techniques, the device runs from a standard fundamental mode, inexpensive crystal, or clock. It can replace VCXOs, multiple crystals and oscillators, saving board space and cost. ICS276 Packaged as 16-pin TSSOP Eight addressable registers Replaces multiple crystals and oscillators Output frequencies up to 200 MHz at 3.3 V Input crystal frequency of 5 to 27 MHz Up to three reference outputs Operating voltages of 3.3 V VDDO output control from 1.8 V to 3.3 V Controllable output drive levels Advanced, low-power CMOS process Available in Pb (lead) free packaging NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 The ICS276 is also available in factory programmed custom versions for high-volume applications. Block Diagram VDD S2:S0 3 OTP ROM with PLL Values 3 VDDO PLL1 CLK1 Divide Logic and Output Enable Control PLL2 VIN PLL3 X1 Crystal X2 External capacitors are required. CLK2 CLK3 Voltage Controlled Crystal Oscillator GND 2 PDTS IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER 1 ICS276 REV D 081809 ICS276 TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER EPROM AND VCXO SYNTHESIZER Pin Assignment VIN VDDO CLK1 GND 1 2 3 4 5 6 7 16 15 14 13 12 11 10 X1/ICLK 8 9 S0 S1 VDD S2 VDD PDTS GND CLK3 CLK2 VDD X2 16 pin (173 mil) TSSOP Pin Descriptions Pin Number Pin Name Pin Type 1 VIN Input 2 S0 Input 3 S1 Input 4 VDD Power Select pin 1. Internal pull-up resistor. Connect to +3.3 V. 5 VDDO Power Power supply for outputs. 6 CLK1 Output Output clock 1. Weak internal pull-down when tri-state. 7 GND Power Connect to ground. Pin Description Voltage input to VCXO. Zero to 3.3 V signal which controls the VCXO frequency Select pin 0. Internal pull-up resistor. 8 X1 XI Crystal input. Connect this pin to a crystal. 9 X2 XO 10 VDD Power Crystal Output. Connect this pin to a crystal. Connect to +3.3 V. 11 CLK2 Output Output clock 2. Weak internal pull-down when tri-state. 12 CLK3 Output Output clock 3. Weak internal pull-down when tri-state. 13 GND Power Connect to ground. 14 PDTS Input 15 VDD Power Power-down tri-state. Powers down entire chip and tri-states clock outputs when low. Internal pull-up resistor. Connect to +3.3 V. 16 S2 Input Select pin 2. Internal pull-up resistor. IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER 2 ICS276 REV D 081809 ICS276 TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER External Components The ICS276 requires a minimum number of external components for proper operation. Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Decoupling Capacitors As with any high-performance mixed-signal IC, the ICS276 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias on the decoupling circuit. Quartz Crystal The ICS276 VCXO function consists of the external crystal and the integrated VCXO oscillator circuit. To assure the best system performance (frequency pull range) and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the following section shown must be followed. The frequency of oscillation of a quartz crystal is determined by its “cut” and by the load capacitors connected to it. The ICS276 incorporates on-chip variable load capacitors that “pull” (change) the frequency of the crystal. The crystal specified for use with the ICS276 is designed to have zero frequency error when the total of on-chip + stray capacitance is 14 pF. Recommended Crystal Parameters: Initial Accuracy at 25° C Temperature Stability Aging Load Capacitance Shunt Capacitance, C0 C0/C1 Ratio Equivalent Series Resistance ±20 ppm ±30 ppm ±20 ppm 14 pf 7 pF Max 250 Max 35Ω Max EPROM AND VCXO SYNTHESIZER The external crystal must be connected as close to the chip as possible and should be on the same side of the PCB as the ICS276. There should be no via’s between the crystal pins and the X1 and X2 device pins. There should be no signal traces underneath or close to the crystal. See application note MAN05. Crystal Tuning Load Capacitors The crystal traces should include pads for small fixed capacitors, one between X1 and ground, and another between X2 and ground. Stuffing of these capacitors on the PCB is optional. The need for these capacitors is determined at system prototype evaluation, and is influenced by the particular crystal used (manufacture and frequency) and by PCB layout. The typical required capacitor value is 1 to 4 pF. To determine the need for and value of the crystal adjustment capacitors, you will need a PC board of your final layout, a frequency counter capable of about 1 ppm resolution and accuracy, two power supplies, and some samples of the crystals which you plan to use in production, along with measured initial accuracy for each crystal at the specified crystal load capacitance, CL. To determine the value of the crystal capacitors: 1. Connect VDD of the ICS276 to 3.3 V. Connect pin 1 of the ICS276 to the second power supply. Adjust the voltage on pin 1 to 0V. Measure and record the frequency of the CLK output. 2. Adjust the voltage on pin 1 to 3.3 V. Measure and record the frequency of the same output. To calculate the centering error: 6 ( f3.0V – ft arg et ) + ( f0V – ft arg et ) Error = 10 x ----------------------------------------------------------------------- – errorxtal ft arg et Where: ftarget = nominal crystal frequency IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER 3 ICS276 REV D 081809 ICS276 TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER errorxtal =actual initial accuracy (in ppm) of the crystal being measured If the centering error is less than ±25 ppm, no adjustment is needed. If the centering error is more than 25 ppm negative, the PC board has excessive stray capacitance and a new PCB layout should be considered to reduce stray capacitance. (Alternately, the crystal may be re-specified to a higher load capacitance. Contact IDT for details.) If the centering error is more than 25 ppm positive, add identical fixed centering capacitors from each crystal pin to ground. The value for each of these caps (in pF) is given by: External Capacitor = 2 x (centering error)/(trim sensitivity) Trim sensitivity is a parameter which can be supplied by your crystal vendor. If you do not know the value, assume it is 30 ppm/pF. After any changes, repeat the measurement to verify that the remaining error is acceptably low (typically less than ±25 ppm). EPROM AND VCXO SYNTHESIZER Each output frequency can be represented as: OutputFreq = REFFreq ⋅ M ----N Output Drive Control The ICS276 has two output drive settings. For VDDO=VDD, low drive should be selected when outputs are less than 100 MHz. High drive should be selected when outputs are greater than 100 MHz. For VDDO