ICS342MPT

DATASHEET FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER ICS342 Description Features The ICS342 is a low cost, dual-output, field programmable clock synthesizer. The ICS342 can generate two output frequencies from 250 kHz to 200 MHz, using up to two independently configurable PLLs. The outputs may employ Spread Spectrum techniques to reduce system electro-magnetic interference (EMI). • 8-pin SOIC package • Highly accurate frequency generation • M/N Multiplier PLL: M = 1...2048, N = 1...1024 • Output clock frequencies up to 200 MHz • Two ROM locations for frequency and spread selection • Spread spectrum capability for lower system EMI • Center or Down Spread up to 4% total • Selectable 32 kHz or 120 kHz modulation • Input crystal frequency from 5 to 27 MHz • Input clock frequency from 2 to 50 MHz • Operating voltage of 3.3 V • Advanced, low power CMOS process • For one output clock, use the ICS341. For three output Using ICS’ VersaClockTM software to configure the PLL and output, the ICS342 contains a One-Time Programmable (OTP) ROM to allow field programmability. Programming features include 2 selectable configuration registers. Using Phase-Locked Loop (PLL) techniques, the device runs from a standard fundamental mode, inexpensive crystal, or clock. It can replace multiple crystals and oscillators, saving board space and cost. The device also has a power down feature that tri-states the clock outputs and turns off the PLLs when the PDTS pin is taken low. The ICS342 is also available in factory programmed custom versions for high-volume applications. • clocks, see the ICS343. For more than three outputs, see the ICS345 or ICS348. Available in Pb (lead) free packaging NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 Block Diagram VDD SEL OTP ROM with PLL Divider Values Crystal or clock input CLK1 PLL Clock Synthesis, Spred Spectrum and Control Circuitry X1/ICLK Crystal Oscillator CLK2 X2 External capacitors are required with a crystal input. GND PDTS (both outputs and PLL) IDT™ / ICS™ FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 1 ICS342 REV L 092109 ICS342 FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER Pin Assignment EPROM CLOCK SYNTHESIZER Output Clock Selection Table X1/ I CLK 1 8 X2 VDD 2 7 PDTS GND 3 6 SEL CLK1 4 5 CLK2 SEL CLK1 (MHz) CLK2 (MHz) 0 1 User Configurable User Configurable User Configurable User Configurable Spread Percentage User Configurable User Configurable 8-pin (150 mil) SOIC Pin Description Pin Number Pin Name Pin Type 1 X1/ICLK XI Pin Description Connect this pin to a crystal or external clock input. 2 VDD Power Connect to +3.3 V. 3 GND Power Connect to ground. 4 CLK1 Output Clock output. Weak internal pull-down when tri-state. 5 CLK2 Output Clock output. Weak internal pull-down when tri-state. 6 SEL Input 7 PDTS Input 8 X2 XO Select for frequency selection on CLK1 and CLK2. Internal pull-up resistor. Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up resistor. Connect this pin to a crystal, or float for clock input. External Components Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Decoupling Capacitor the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. As with any high-performance mixed-signal IC, the ICS342 must be isolated from system power supply noise to perform optimally. The value (in pF) of these crystal caps should equal (CL -6 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2] = 20. A decoupling capacitor of 0.01µF must be connected between VDD and the PCB ground plane. PCB Layout Recommendations Crystal Load Capacitors For optimum device performance and lowest output phase noise, the following guidelines should be observed. The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of 1) The 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as IDT™ / ICS™ FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 2 ICS342 REV L 092109 ICS342 FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS342. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. ICS342 Configuration Capabilities The architecture of the ICS342 allows the user to easily configure the device to a wide range of output frequencies, for a given input reference frequency. The frequency multiplier PLL provides a high degree of precision. The M/N values (the multiplier/divide values available to generate the target VCO frequency) can be set within the range of M = 1 to 2048 and N = 1 to 1024. The ICS342 also provides separate output divide values, from 2 through 20, to allow the two output clock banks to support widely differing frequency values from the same PLL. Each output frequency can be represented as: OutputFreq = REFFreq -------------------------------------OutputDivide ⋅ M ----N IDT VersaClock Software IDT applies years of PLL optimization experience into a user friendly software that accepts the user’s target reference clock and output frequencies and generates the lowest jitter, lowest power configuration, with only a press of a button. The user does not need to have prior PLL experience or determine the optimal VCO frequency to support multiple EPROM CLOCK SYNTHESIZER output frequencies. VersaClock software quickly evaluates accessible VCO frequencies with available output divide values and provides an easy to understand, bar code rating for the target output frequencies. The user may evaluate output accuracy, performance trade-off scenarios in seconds. Spread Spectrum Modulation The ICS342 utilizes frequency modulation (FM) to distribute energy over a range of frequencies. By modulating the output clock frequencies, the device effectively lowers energy across a broader range of frequencies; thus, lowering a system’s electromagnetic interference (EMI). The modulation rate is the time from transitioning from a minimum frequency to a maximum frequency and then back to the minimum. Spread Spectrum Modulation can be applied as either “center spread” or “down spread”. During center spread modulation, the deviation from the target frequency is equal in the positive and negative directions. The effective average frequency is equal to the target frequency. In applications where the clock is driving a component with a maximum frequency rating, down spread should be applied. In this case, the maximum frequency, including modulation, is the target frequency. The effective average frequency is less than the target frequency. The ICS342 operates in both center spread and down spread modes. For center spread, the frequency can be modulated between +/- 0.125% to +/-2.0%. For down spread, the frequency can be modulated between -0.25% to -4.0%. Both output frequency banks will utilize identical spread spectrum percentage deviations and modulation rates, if a common VCO frequency can be identified. Spread Spectrum Modulation Rate The spread spectrum modulation frequency applied to the output clock frequency may occur at a variety of rates. For applications requiring the driving of “down-circuit” PLLs, Zero Delay Buffers, or those adhering to PCI standards, the spread spectrum modulation rate should be set to 30-33 kHz. For other applications, a 120 kHz modulation option is available. IDT™ / ICS™ FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 3 ICS342 REV L 092109 ICS342 FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS342. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Parameter Condition Min. Supply Voltage, VDD Referenced to GND Inputs Referenced to GND Clock Outputs Referenced to GND Storage Temperature Soldering Temperature Typ. Max. Units 7 V -0.5 VDD+ 0.5 V -0.5 VDD+ 0.5 V -65 150 °C 260 °C 125 °C Max 10 seconds Junction Temperature Recommended Operation Conditions Parameter Min. Typ. Max. Units Ambient Operating Temperature (ICS342M) 0 +70 °C Ambient Operating Temperature (ICS342MI) -40 +85 °C +3.45 V 4 ms Power Supply Voltage (measured in respect to GND) +3.15 Power Supply Ramp Time IDT™ / ICS™ FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 4 +3.3 ICS342 REV L 092109 ICS342 FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER DC Electrical Characteristics Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C Parameter Operating Voltage Symbol Conditions VDD Min. Typ. Max. Units 3.15 3.3 3.45 V Configuration Dependent - See VersaClockTM Estimates Operating Supply Current Input High Voltage IDD mA Two 33.3333 MHz outputs, PDTS = 1, no load, Note 1 13 mA 20 µA V Input High Voltage VIH PDTS = 0 SEL pin Input Low Voltage VIL SEL pin Input High Voltage, PDTS VIH Input Low Voltage, PDTS VIL Input High Voltage VIH ICLK Input Low Voltage VIL ICLK Output High Voltage (CMOS High) VOH IOH = -4 mA VDD-0.4 V Output High Voltage VOH IOH = -12 mA 2.4 V Output Low Voltage VOL IOL = 12mA Short Circuit Current IOS ±70 mA Nominal Output Impedance ZO 20 Ω 2 0.4 VDD-0.5 V V 0.4 VDD/2+1 V V VDD/2-1 0.4 V V Internal pull-up resistor RPUP SEL, PDTS pins 250 kΩ Internal pull-down resistor RPD CLK output 525 kΩ Input Capacitance CIN Inputs 4 pF Note 1: Example with 25 MHz crystal input with two outputs of 33.3 MHz, no load, and VDD = 3.3 V. IDT™ / ICS™ FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 5 ICS342 REV L 092109 ICS342 FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER AC Electrical Characteristics Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C Parameter Symbol Input Frequency FIN Conditions Min. Typ. Max. Units Fundamental Crystal 5 27 MHz Input Clock 2 50 MHz 0.25 200 MHz Output Frequency Output Rise Time tOR 20% to 80%, Note 1 1 ns Output Fall Time tOF 80% to 20%, Note 1 1 ns Duty Cycle Note 2 Output Frequency Synthesis Error Configuration Dependent Power-up time PLL lock time from power-up, Note 3 One Sigma Clock Period Jitter Maximum Absolute Jitter tja 40 49-51 60 TBD % ppm 4 10 ms PDTS goes high until stable CLK output, Spread Spectrum Off, Note 3 0.2 2 ms PDTS goes high until stable CLK output, Spread Spectrum On, Note 3 4 7 ms Configuration Dependent 50 ps Deviation from Mean. Configuration Dependent +200 ps Note 1: Measured with 15 pF load. Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%. Note 3: ICS test mode output occurs for first 170 clock cycles on CLK2 for each PLL powered up. PDTS transition high on select address change. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol Conditions Min. Typ. Max. Units θ JA Still air 150 ° C/W θ JA 1 m/s air flow 140 ° C/W θ JA 3 m/s air flow 120 ° C/W 40 ° C/W θ JC IDT™ / ICS™ FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 6 ICS342 REV L 092109 ICS342 FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 8 Millimeters Symbol E Min A A1 B C D E e H h L α H INDEX AREA 1 2 D A Inches Max Min 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0° 8° Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0° 8° h x 45 A1 C -Ce B SEATING PLANE L .10 (.004) C IDT™ / ICS™ FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 7 ICS342 REV L 092109 ICS342 FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 342MP* 342MPT* 342MIP* 342MIPT* 342MPLF 342MPLFT 342MIPLF 342MIPLFT 342M-XX* 342M-XXT* 342MI-XX* 342MI-XXT* 342M-XXLF 342M-XXLFT 342MI-XXLF 342MI-XXLFT 342MP 342MP 342MIP 342MIP 342MPLF 342MPLF 342MIPLF 342MIPLF 342M-XX 342M-XX 342MI-XX 342MI-XX 342MXXLF 342MXXLF 342MIXXL 342MIXXL Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C *NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. The 342M-XX, 342M-XXLF, 342MI-XX, and 342MI-XXLF are factory programmed versions of the 342MP, 342MPLF, 342MIP, and 342MIPLF. A unique “-XX” suffix is assigned by the factory for each custom configuration, and a separate data sheet is kept on file. For more information on custom part numbers programmed at the factory, please contact your local IDT sales and marketing representative. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. IDT™ / ICS™ FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 8 ICS342 REV L 092109 ICS342 FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA