ICS487G-25

DATASHEET ICS487-25 QUAD PLL FOR DTV Description Features The ICS487-25 generates five high-quality, high-frequency clock outputs. It is designed to replace crystals and crystal oscillators in DTV applications. Using IDT’s patented Phase Locked Loop (PLL) techniques, the device runs from a lower frequency crystal or clock input. • • • • • • • Because there is zero ppm frequency synthesis error on the audio clocks, the audio will remain locked to the video. Packaged in 16-pin TSSOP (Pb-free) Replaces multiple crystals and oscillators Input crystal or clock frequency of 27 MHz Zero ppm frequency synthesis error Duty cycle of 45/55 Operating voltage of 3.3 V Advanced, low power CMOS process Block Diagram VDD 3 2 S1:0 PLL1 ACLK 20M PLL2 48M 27 MHz clock or crystal input X1/ICLK X2 External capacitors may be required. IDT™ / ICS™ QUAD PLL FOR DTV Crystal Oscillator/ Clock Buffer PLL3 33.0M PLL4 24.576M 3 GND 1 PDTS (all outputs and PLLs) ICS487-25 REV B 092109 ICS487-25 QUAD PLL FOR DTV CLOCK SYNTHESIZER Pin Assignment ACLK Output Selection Table S1 S0 ACLK (MHz) X1/ICLK 1 16 X2 0 0 18.432 S0 2 15 VDD 0 1 16.9344 S1 3 14 PDTS 1 0 12.288 48M 4 13 GND 1 1 18.432 VDD GND 5 12 6 11 VDD GND 20M 7 10 33.0M 24.576M 8 9 ACLK Note: When S1 and S0 are switched, all other output clocks will remain stable throughout the transition. 16 pin (173 mil) TSSOP Pin Descriptions Pin Number Pin Name Pin Type 1 X1/ICLK Input Crystal connection. Connect to 27 MHz crystal or clock input. 2 S0 Input Select pin 0. Determines ACLK output frequency per table above. Internal pull up resistor. 3 S1 Input Select pin 1. Determines ACLK output frequency per table above. Internal pull up resistor. 4 48M Output 48 MHz clcok output. Weak internal pull-down when tri-state. 5 VDD Power Connect to +3.3 V. 6 GND Power Connect to ground. 7 20M Output 20 MHz clock output. Weak internal pull-down when tri-state. 8 24.576M Output 24.576 MHz clock output. Weak internal pull-down when tri-state. 9 ACLK Output Audio clock output. Determined by table above. Weak internal pull-down when tri-state 10 33.0M Output 33.0 MHz clock output. Weak internal pull-down when tri-state. 11 GND Power Connect to ground. 12 VDD Power Connect to +3.3 V. 13 GND Power Connect to ground. PDTS Input Powers down entire chip and tri-states outputs when low. Internal pull-up resistor. 15 VDD Power Connect to +3.3 V. 16 X2 Input Connect to 27 MHz crystal or float for clock input. 14 IDT™ / ICS™ QUAD PLL FOR DTV Pin Description 2 ICS487-25 REV B 092109 ICS487-25 QUAD PLL FOR DTV CLOCK SYNTHESIZER External Components -6 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2] = 20. Decoupling Capacitor As with any high-performance mixed-signal IC, the ICS487-25 must be isolated from system power supply noise to perform optimally. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. A decoupling capacitor of 0.01µF must be connected between each VDD and the PCB ground plane. Series Termination Resistor 1) The 0.01µF decoupling capacitors should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to VDD pins should be kept as short as possible, as should the PCB trace to the ground via. Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. 3) To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS487-25. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. The value (in pF) of these crystal caps should equal (CL Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS487-25. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70° C IDT™ / ICS™ QUAD PLL FOR DTV 3 ICS487-25 REV B 092109 ICS487-25 QUAD PLL FOR DTV CLOCK SYNTHESIZER Item Rating Storage Temperature -65 to +150° C Junction Temperature 125° C Soldering Temperature 260° C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Typ. Max. Units +70 °C +3.465 V 0 Power Supply Voltage (measured in respect to GND) +3.135 +3.3 DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C Parameter Symbol Conditions Min. Typ. Max. Units 3.135 3.3 3.465 V Operating Voltage VDD Supply Current IDD No load, PDTS=1 35 mA IDDPD No load, PDTS=0 20 µA Power Down Current Input High Voltage VIH Input Low Voltage VIL Output High Voltage VOH IOH = -4 mA VDD-0.4 V Output High Voltage VOH IOH = -12 mA 2.4 V Output Low Voltage VOL IOL = 12 mA Short Circuit Current IOS Clock outputs Input Capacitance, inputs 2 V 0.8 0.4 V V ±70 mA CIN 5 pF Nominal Output Impedance ZOUT 20 Ω Internal Pull-up Resistor RPU S1, S0, PDTS pins 360 kΩ Internal Pull-down Resistor RPD Clock outputs 510 kΩ IDT™ / ICS™ QUAD PLL FOR DTV 4 ICS487-25 REV B 092109 ICS487-25 QUAD PLL FOR DTV CLOCK SYNTHESIZER AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C Parameter Symbol Input Frequency fIN Output Rise Time tOR Output Fall Time tOF Conditions Min. Typ. Max. Units 27 MHz 20% to 80%, Note 1 1.2 ns 80% to 20%, Note 1 1.0 ns Output Clock Duty Cycle at VDD/2, Note 1 Absolute Clock Period Jitter Note 1 Frequency Synthesis Error All outputs 45 50 55 % ±175 ps 0 ppm Output Enable Time tOE PDTS high to output locked to ±1% 250 µs Output Disable Time tOD PDTS low to tri-state 20 ns Time from a change in S1 or S0 until output stable within ±1% 50 µs Audio Clock Stabilization Time Note 1: Measured with a 15 pF load. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case IDT™ / ICS™ QUAD PLL FOR DTV Symbol Conditions Min. Typ. Max. Units θJA Still air 78 ° C/W θJA 1 m/s air flow 70 ° C/W θJA 3 m/s air flow 68 ° C/W 37 ° C/W θJC 5 ICS487-25 REV B 092109 ICS487-25 QUAD PLL FOR DTV CLOCK SYNTHESIZER Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 16 Symbol E1 A A1 A2 b C D E E1 e L α aaa E IN D EX AR EA 1 2 D A 2 Min Inches Max -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° -0.10 Min Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° -0.004 A A 1 c -C e S E A T IN G P LA N E b L aaa C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 487G-25LF 487G-25LFT 487G-25LF (1st line) YYWW$$ (3rd line) Tubes Tape and Reel 16-pin TSSOP 16-pin TSSOP 0 to +70 ° C 0 to +70 ° C “LF” suffix to the part number denotes Pb free configuration and RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ QUAD PLL FOR DTV 6 ICS487-25 REV B 092109 ICS487-25 QUAD PLL FOR DTV CLOCK SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. 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