ICS650R-14LFT

DATASHEET ICS650-14 NETWORKING SYSTEM CLOCK Description Features The ICS650-14 is a low-cost, low-jitter, high-performance clock synthesizer customized for networking systems applications. Using analog/digital Phase-Locked Loop (PLL) techniques, the device accepts a 25 MHz clock or fundamental mode crystal input to produce multiple output clocks of one fixed 25 MHz, a four (plus one) frequency selectable bank, and two frequency selectable clocks. All output clocks are frequency locked together. All of the ICS650-14 outputs have zero ppm synthesis error. • • • • • • • • • • • • Packaged in 20-pin (150 mil) SSOP (QSOP) 25 MHz fundamental crystal clock or clock input One fixed output clock of 25 MHz One bank of four frequency selectable output clocks Three frequency selectable clocks outputs Zero ppm synthesis error in all clocks Ideal for networking systems Full CMOS output swing Advanced, low-power sub-micron CMOS process Operating voltage of 3.3 V or 5 V Industrial temperature range available Pb-free, RoHS compliant package Block Diagram VDD 2 S E L A 0 :1 S E L B 0 :1 2 4 C lo ck S ynth e sis an d C o n tro l C ircu itry S ELC X 1 /IC L K 25 M H z C rystal or C lock C L K A 1 :4 2 X2 CLKA5 C LKB C LKC C rysta l B u ffe r/ C rysta l O scillator 25 M H z 2 O p tional crystal capacitors are show n and m a y be re q u ired fo r tuning of in itia l a ccura cy (determ ined o n c e p e r b o a rd ) IDT™ / ICS™ NETWORKING SYSTEM CLOCK GND 1 O E (a ll o u tp u ts) ICS650-14 REV H 051310 ICS650-14 NETWORKING SYSTEM CLOCK CLOCK SYNTHESIZER Pin Assignment Table 1 SELB0 1 20 SELC SELA1 SELA0 CLKA1:4 CLKA5 X2 2 19 SELA0 0 0 33.33 66.66 X1/ICLK 3 18 CLKA2 0 M 50 75 VDD 4 17 CLKA3 SELB1 5 16 VDD GND 6 15 SELA1 CLKB 7 14 GND 1 66.67 133.33 0 100 33.33 M M 33.33 83.33 1 50 125 8 13 CLKA4 M 9 12 CLKA1 1 0 33.33 100 10 11 OE 1 M 25 75 1 1 66.67 100 CLKC CLKA5 25M 0 M 20-pin (150 mil) SSOP Table 3 Table 2 SELC CLKC 30 0 CLKB/4 62.5 125 SELB1 SELB0 CLKB 0 0 0 M 27 M 0 1 48 1 1 0 83.33 1 M 19.44 1 1 80 0 = connect directly to ground 1 = connect directly to VDD M = leave unconnected (floating) Pin Descriptions Pin Number Pin Name Pin Type 1 SELB0 TI Select pin for CLKB. See table 2. 2 X2 XO Crystal connection. Connect to a 25 MHz crystal or leave unconnected for clock input. 3 X1/ICLK XI Crystal connection. Connect to a 25 MHz fundamental crystal or clock input. 4 VDD P Connect to 3.3 V or 5 V. Must be same as other VDDs. 5 SELB1 I(Pu) 6 GND P Connect to ground. 7 CLKB O Selectable clock output. See table 2. 8 CLKC O Selectable clock output. See table 3. 9 CLKA5 O Selectable clock output. See table 1. 10 25M Ou 25 MHz clock output. 11 OE I(Pu) 12 CLKA1 O IDT™ / ICS™ NETWORKING SYSTEM CLOCK Pin Description Select pin for CLK B. See table 2. Output enable. Tri-states all outputs when low. Internal pull-up. Selectable clock output. See table 1. 2 ICS650-14 REV H 051310 ICS650-14 NETWORKING SYSTEM CLOCK CLOCK SYNTHESIZER Pin Number Pin Name Pin Type Pin Description 13 CLKA4 O Selectable clock output. See table 1. 14 GND P Connect to ground. 15 SELA1 TI Select pin for CLKA1:4 and CLKA5 outputs. See table 1. 16 VDD P Connect to 3.3 Vor 5 V. Must be same as other VDDs. 17 CLKA3 O Selectable clock output. See table 1. 18 CLKA2 O Selectable clock output. See table 1. 19 SELA0 TI Select pin for CLKA1:4 and CLKA5 outputs. See table 1. 20 SELC TI Select pin for CLKC output. See table 3. Key: XI, XO = crystal connections; I = input; I(Pu) = input with pull-up; O = output; P = power supply connection; TI = tri-level input External Components Crystal Information The ICS650-14 requires a minimum number of external components for proper operation. The crystal used should be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is given by the following equation: Crystal caps (pF) = (CL - 6) x 2 Decoupling Capacitor Decoupling capacitors of 0.01µF must be connected between each VDD and GND (pins 4 and 6, pins 16 and 14), as close to the device as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. In the equation, CL is the crystal load capacitance. For a crystal with a 16 pF load capacitance, two 20 pF [(16-6) x 2] capacitors should be used. Series Termination Resistor When the PCB trace between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance) place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. IDT™ / ICS™ NETWORKING SYSTEM CLOCK 3 ICS650-14 REV H 051310 ICS650-14 NETWORKING SYSTEM CLOCK CLOCK SYNTHESIZER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS650-14. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD (referecned to GND) 7V Inputs and Outputs (referecned to GND) -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70° C Ambient Operating Temperature (industrial “I” version) -40 to 85° C Soldering Temperature (max. of 20 seconds) -65 to +150° C Storage Temperature 260° C DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature 0 to +70° C Parameter Operating Voltage Symbol Conditions VDD Min. Typ. 3.0 Max. Units 5.5 V Input High Voltage (X1 pin only) VIH Clock input Input Low Voltage (X1 pin only) VIL Clock input Input High Voltage (SEL pins only) VIH Input Low Voltage (SEL pins only) VIL Input High Voltage (OE pin only) VIH Input Low Voltage (OE pin only) VIL Output High Voltage VOH IOH = -12 mA 2.4 V Output High Voltage (CMOS level) VOH IOH = -8 mA VDD-0.4 V Output Low Voltage VOL IOL = 12 mA Operating Supply Current IDD No load, VDD = 3.3 V 32 mA Each output ±50 mA Short Circuit Current IDT™ / ICS™ NETWORKING SYSTEM CLOCK VDD/2+1 V VDD/2-1 VDD-0.5 V 0.5 2.0 V V 0.8 4 V 0.4 ICS650-14 V V REV H 051310 ICS650-14 NETWORKING SYSTEM CLOCK CLOCK SYNTHESIZER AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature 0 to +70° C Parameter Symbol Conditions Min. Input Frequency Typ. Max. Units 25 MHz Output Clock Rise Time tOR 0.8 to 2.0 V 1.5 ns Output Clock Fall Time tOF 2.0 to 0.8 V 1.5 ns 55 % 0 ppm Output Clock Duty Cycle At VDD/2 Frequency Error All clocks Absolute Jitter, short term CLKB = 27M ±250 ps CLKC = 62.5M ±300 ps Other Clocks ±350 ps Marking Diagram (ICS650R-14ILF) 11 20 650R-14ILF ###### YYWW 1 50 Marking Diagram (ICS650R-14LF) 11 20 45 650R-14LF ###### YYWW 10 1 10 Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year, and the week number that the part was assembled. 3. ”LF” denotes Pb-free, RoHS compliant package. 4. “I” denotes industrial grade device. 5. Bottom marking: country of origin. IDT™ / ICS™ NETWORKING SYSTEM CLOCK 5 ICS650-14 REV H 051310 ICS650-14 NETWORKING SYSTEM CLOCK CLOCK SYNTHESIZER Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 20 Symbol E1 A A1 A2 b c D E E1 e L α E INDEX AREA 1 2 D A 2 Min Inches Max 1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 8.55 8.75 5.80 6.20 3.80 4.00 0.635 Basic 0.40 1.27 0° 8° Min Max 0.053 0.069 0.004 0.010 -0.059 0.008 0.012 0.007 0.010 0.337 0.344 0.228 0.244 0.150 0.157 0.025 Basic 0.016 0.050 0° 8° A A 1 c -Ce b SEATING PLANE L .10 (.004) C Ordering Information Part / Order Number Marking Shipping Packaging Package 650R-14LF 650R-14LFT 650R-14ILF 650R-14ILFT see page 5 Tubes Tape and Reel Tubes Tape and Reel 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP Temperature 0 to +70° 0 to +70° -40 to 85° -40 to 85° C C C C "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ NETWORKING SYSTEM CLOCK 6 ICS650-14 REV H 051310 ICS650-14 NETWORKING SYSTEM CLOCK CLOCK SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. 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