ICS663MILF

DATASHEET ICS663 PLL BUILDING BLOCK Description Features The ICS663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO) and an output buffer. Through the use of external reference and VCO dividers (implemented with the ICS674-01, for example), the user can easily configure the device to lock to a wide variety of input frequencies. • Packaged in 8-pin SOIC (Pb free) • Output clock range 1 MHz to 100 MHz (3.3 V), 1 MHz to 120 MHz (5 V) • External PLL loop filter enables configuration for a wide range of input frequencies • Ability to accept an input clock in the kHz range (video Hsync, for example) • • • • The phase detector and VCO functions of the device can also be used independently. This enables the configuration of other PLL circuits. For example, the ICS663 phase detector can be used to control a VCXO circuit such as the MK3754. 25 mA output drive capability at TTL levels Lower power CMOS process +3.3 V ±5% or +5 V ±10% operating voltage Used along with the ICS674-01, forms a complete PLL circuit • Phase detector and VCO blocks can be used For applications requiring Power Down or Output Enable features, please refer to the ICS673-01. independently for other PLL configurations • Industrial temperature version available • For better jitter performance, use the MK1575 Block Diagram LF LFR VDD I cp C lock Input R E FIN FB IN UP P hase/ Frequency D etector 1 VCO MUX DOW N 4 2 C LK 0 I cp SEL External Feedback D ivider (such as the IC S674-01) IDT™ / ICS™ PLL BUILDING BLOCK 1 ICS663 REV E 012006 ICS663 PLL BUILDING BLOCK PLL BUILDING BLOCK Pin Assignment VCO Post Divide Select Table FBIN 1 8 REFIN VDD 2 7 CLK GND 3 6 SEL LF 4 5 LFR SEL VCO Post Divide 0 8 1 2 0 = connect pin directly to ground 1 = connect pin directly to VDD 8 Pin (150 mil) SOIC Pin Descriptions Pin Number Pin Name Pin Type 1 FBIN Input Feedback clock input. Connect the output of the feedback divider to this pin. Falling edge triggered. 2 VDD Power VDD. Connect to +3.3 V or +5 V. 3 GND Power Connect to ground. 4 LF Input Loop filter connection (refer to Figure 1 on Page 5). When using the phase detector block only, this pin serves as the charge pump output. When using the VCO block only, this pin serves as VCO input control voltage. 5 LFR Input Loop filter return (refer to Figure 1 on Page 5). 6 SEL Input Select pin for VCO post divide, as per above table. 7 CLK Output 8 REFIN Input IDT™ / ICS™ PLL BUILDING BLOCK Pin Description Clock output. Reference clock input. Connect the input clock to this pin. Falling edge triggered. 2 ICS663 REV E 012006 ICS663 PLL BUILDING BLOCK PLL BUILDING BLOCK Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS663. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5V to VDD+0.5V Ambient Operating Temperature 0 to +70° C Industrial Temperature -40 to +85° C Storage Temperature -65 to +150° C Soldering Temperature 260° C Recommended Operation Conditions Parameter Min. Max. Units -40 +85 °C +3.13 +5.5 V Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Typ. DC Electrical Characteristics VDD=3.3 V ±5% or 5.0 V ±10%, Ambient temperature -40 to +85° C, unless stated otherwise Parameter Operating Voltage Symbol Conditions VDD Typ. 3.13 Logic Input High Voltage VIH REFIN, FBIN, SEL Logic Input Low Voltage VIL REFIN, FBIN, SEL LF Input Voltage Range VI VOH IOH = -25 mA Output Low Voltage VOL IOL = 25 mA Output High Voltage, CMOS level VOH IOH = -8 mA Operating Supply Current IDD VDD = 5.0 V, No load, 40 MHz Short Circuit Current IOS Input Capacitance CI Max. Units 5.5 V 2 V 0 Output High Voltage IDT™ / ICS™ PLL BUILDING BLOCK Min. 0.8 V VDD V 2.4 V 0.4 V VDD-0.4 15 mA CLK ±100 mA SEL 5 pF 3 ICS663 REV E 012006 ICS663 PLL BUILDING BLOCK PLL BUILDING BLOCK AC Electrical Characteristics VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C, unless stated otherwise Parameter Symbol Conditions Output Clock Frequency (from pin CLK) fCLK Input Clock Frequency (into pins REFIN or FBIN) fREF Output Rise Time tOR 0.8 to 2.0V Output Fall Time tOF 2.0 to 0.8V Output Clock Duty Cycle tDC At VDD/2 Min. Typ. Max. Units SEL = 1 1 100 MHz SEL = 0 0.25 25 MHz Note 1 8 MHz 1.2 2 ns 0.75 1.5 ns 50 60 % 40 Jitter, Absolute peak-to-peak tJ 250 ps VCO Gain KO 200 MHz/V Charge Pump Current Icp 2.5 µA VDD = 5.0 V ±10%, Ambient Temperature -40 to +85° C, unless stated otherwise Parameter Symbol Conditions Output Clock Frequency (from pin CLK) fCLK Input Clock Frequency (into pins REFIN or FBIN) fREF Output Rise Time tOR 0.8 to 2.0 V Output Fall Time tOF 2.0 to 0.8 V Output Clock Duty Cycle tDC At VDD/2 Min. Typ. Max. Units SEL = 1 1 120 MHz SEL = 0 0.25 30 MHz Note 1 8 MHz 0.5 1 ns 0.5 1 ns 50 55 % 45 Jitter, Absolute peak-to-peak tJ 150 ps VCO Gain KO 200 MHz/V Charge Pump Current Icp 2.5 µA Note 1: Minimum input frequency is limited by loop filter design. 1 kHz is a practical minimum limit. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case IDT™ / ICS™ PLL BUILDING BLOCK Symbol Conditions Min. Typ. Max. Units θJA Still air 150 ° C/W θJA 1 m/s air flow 140 ° C/W θJA 3 m/s air flow 120 ° C/W 40 ° C/W θJC 4 ICS663 REV E 012006 ICS663 PLL BUILDING BLOCK PLL BUILDING BLOCK External Components Avoiding PLL Lockup The ICS663 requires a minimum number of external components for proper operation. A decoupling capacitor of 0.01µF should be connected between VDD and GND as close to the ICS663 as possible. A series termination resistor of 33Ω may be used at the clock output. In some applications, the ICS663 can “lock up” at the maximum VCO frequency. The way to avoid this problem is to use an external divider that always operates correctly regardless of the CLK output frequency. The CLK output frequency may be up to 2x the maximum Output Clock Frequency listed in the AC Electrical Characteristics above when the device is in an unlocked condition. Make sure that the external divider can operate up to this frequency. Special considerations must be made in choosing loop components C1 and C2: Explanation of Operation 1) The loop capacitors should be a low-leakage type to avoid leakage-induced phase noise. For this reason, DO NOT use any type of polarized or electrolytic capacitors. The ICS663 is a PLL building block circuit that includes an integrated VCO with a wide operating range. The device uses external PLL loop filter components which through proper configuration allow for low input clock reference frequencies, such as a 15.7 kHz Hsync input. 2) Microphonics (mechanical board vibration) can also induce output phase noise when the loop bandwidth is less than 1 kHz. For this reason, ceramic capacitors should have C0G or NP0 dielectric. Avoid high-K dielectrics like Z5U and X7R. These and some other ceramics have piezoelectric properties that convert mechanical vibration into voltage noise that interferes with VCXO operation. The phase/frequency detector compares the falling edges of the clocks inputted to FBIN and REFIN. It then generates an error signal to the charge pump, which produces a charge proportional to this error. The external loop filter integrates this charge, producing a voltage that then controls the frequency of the VCO. This process continues until the edges of FBIN are aligned with the edges of the REFIN clock, at which point the output frequency will be locked to the input frequency. For larger loop capacitor values such as 0.1µF or 1µF, PPS film types made by Panasonic, or metal poly types made by Murata or Cornell Dubilier are recommended. For questions or changes regarding loop filter characteristics, please contact your sales area FAE, or IDT Applications. Figure 1. Example Configuration -- Generating a 20 MHz clock from a 200 kHz reference +3.3 or 5 V C2 0.01 µ F RZ VDD SEL C1 LFR LF 200 kH z R E FIN IC S 6 6 3 C LK 20 M H z F B IN GND 200 kH z 100 D igital D ivider such as IC S 674-01 IDT™ / ICS™ PLL BUILDING BLOCK 5 ICS663 REV E 012006 ICS663 PLL BUILDING BLOCK PLL BUILDING BLOCK Determining the Loop Filter Values Choosing a damping factor of 0.7 (a minimal damping factor than can be used to ensure fast lock time), damping factor equation becomes: The loop filter components consist of C1, C2, and RZ. Calculating these values is best illustrated by an example. Using the example in Figure 1, we can synthesize 20 MHz from a 200 kHz input. 25, 000 200 ⋅ 2.5 ⋅ C .7 = ------------------- -----------------------------------2 200 The phase locked loop may be approximately described by the following equations: and C1 = 1.25 nF (1.2 nF is the nearest standard value). The capacitor C2 is used to damp transients from the charge pump and should be approximately 1/20th the size of C1, i.e., ( R Z ⋅ K O ⋅ I CP ) Bandwidth= -----------------------------------------2π ⋅ N C 2 ≅ C 1 ⁄ 20 R Z K O ⋅ I CP ⋅ C 1 Damping factor,ζ = ------ -----------------------------------2 N Therefore, C2 = 60 pF (56 pF nearest standard value). To summarize, the loop filter components are: C1 = 1.2 nf C2 = 56 pf Rz = 25 kΩ where: KO = VCO gain (MHz/Volt) Icp = Charge pump current (µA) N = Total feedback divide from VCO, including the internal VCO post divider C1 = Loop filter capacitor (Farads) RZ = Loop filter resistor (Ohms) As a general rule, the bandwidth should be at least 20 times less than the reference frequency, i.e., BW ≤( REFIN ) ⁄ 20 In this example, using the above equation, bandwidth should be less than or equal to 10 kHz. By setting the bandwith to 10kHz and using the first equation, RZ can be determined since all other variables are known. In the example of Figure 1, N = 200, comprising the divide by 2 on the chip (VCO post divider) and the external divide by 100. Therefore, the bandwidth equation becomes: R Z ⋅ 200 ⋅ 2.5 0,000 = ------------------------------------2π ⋅ 200 and RZ = 25 kΩ IDT™ / ICS™ PLL BUILDING BLOCK 6 ICS663 REV E 012006 ICS663 PLL BUILDING BLOCK PLL BUILDING BLOCK Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 8 E H INDEX AREA 1 2 D Symbol A A1 B C D E e H h L α A Millimeters Inches Min Max 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0° 8° Min Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0° 8° h x 45 A1 C -Ce B SEATING PLANE L .10 (.004) C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 663MLF 663MLFT 663MILF 663MILFT 663MLF 663MLF 663MILF 663MILF Tubes Tape and Reel Tubes Tape and Reel 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ PLL BUILDING BLOCK 7 ICS663 REV E 012006 ICS663 PLL BUILDING BLOCK PLL BUILDING BLOCK Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. 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