ICS670M-04I

DATASHEET LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER Description Features The ICS670-04 is a high speed, low phase noise, Zero Delay Buffer (ZDB) which integrates IDT’s proprietary analog/digital Phase Locked Loop (PLL) techniques. It is identical to the ICS670-02, but with an increased maximum output frequency of 210 MHz. There are two identical outputs on the chip. The FBCLK should be used to connect to the FBIN. Each output has its own output enable pin. • • • • • • • • • • • • The ICS670-04 is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to video. By allowing off-chip feedback paths, the chip can eliminate the delay through other devices. The 15 different on-chip multipliers work in a variety of applications. For other multipliers, including functional multipliers, see the ICS527. ICS670-04 Packaged in 16-pin SOIC – Pb (lead) free Clock inputs from 5 to 210 MHz (see page 2) Patented PLL with low phase noise Output clocks up to 210 MHz at 3.3 V 15 selectable on-chip multipliers Power down mode available Low phase noise: -111 dBc/Hz at 10 kHz Output enable function tri-states outputs Low jitter 15 ps one sigma Advanced, low power, sub-micron CMOS process Operating voltage of 3.3 V or 5 V Industrial temperature grade NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 Block Diagram VDD OE1 3 IC L K Divide by N F B IN S 3 :S 0 Phase Detector, Charge Pump, and Loop Filter Voltage Controlled Oscillator FBCLK CLK2 4 3 GND OE2 E x te rn a l F e e d b a c k fro m F B C L K is re c o m m e n d e d . IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 1 ICS670-04 REV D 110409 ICS670-04 LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER Pin Assignment ZDB AND MULTIPLIER Multiplier Select Table S3 S2 S1 S0 CLK2 (and FBCLK) Input Range (MHz) 0 0 0 0 Low (Power down entire chip) — GND 0 0 0 1 Input x1.333 18 - 157.5 0 1 0 Input x6 5 - 35 VDD 1 16 GND VDD 2 15 GND VDD 3 14 CLK2 4 13 S0 0 OE2 5 12 S1 0 0 1 1 Input x1.5 16.67 - 140 1 0 0 Input x3.333 7.5 - 63 FBCLK 6 11 S2 0 OE1 7 10 S3 0 1 0 1 Input x2.50 10 - 84 ICLK 0 1 1 0 Input x4 6 - 52.5 0 1 1 1 Input x1 25 - 210 1 0 0 0 Input x2.333 11 - 90 1 0 0 1 Input x2.666 10 - 78.75 1 0 1 0 Input x12 5 - 17.5 1 0 1 1 Input x3 8 - 70 1 1 0 0 Input x10 5 - 21 1 1 0 1 Input x5 6 - 42 1 1 1 0 Input x8 5 - 26.25 1 1 1 1 Input x2 12 - 105 9 8 FBIN Pin Descriptions Pin Number Pin Name Pin Type Pin Description 1-3 VDD Input 4 CLK2 5 OE2 6 FBCLK 7 OE1 Input Output clock enable 1. Tri-states the feedback clock output when low. 8 FBIN Input Feedback clock input. 9 ICLK Input Clock input. Connect to a 5 - 210 MHz clock. 10 S3 Input Multiplier select pin 3. Determines outputs per table above. Internal pull-up. 11 S2 Input Multiplier select pin 2. Determines outputs per table above. Internal pull-up. 12 S1 Input Multiplier select pin 1. Determines outputs per table above. Internal pull-up. 13 S0 Input Multiplier select pin 0. Determines outputs per table above. Internal pull-up. 14 - 16 GND Power Connect to ground. Power supply. Connect both pins to the same voltage (either 3.3 V or 5 V). Output Clock output from VCO. Output frequency equals the input frequency times multiplier. Input Output clock enable 2. Tri-states the clock 2 output when low. Output Clock output from VCO. Output frequency equals the input frequency times multiplier. IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 2 ICS670-04 REV D 110409 ICS670-04 LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER External Components The ICS670-04 requires a minimum number of external components for proper operation. Tie all VDD pins together, all ground pins together, and connect a 0.01µF decoupling capacitor between them. A series termination resistor of 33Ω must be used on each clock output. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS670-04. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature -40 to +85° C Storage Temperature -65 to +150° C Junction Temperature 150° C Soldering Temperature 260° C Recommended Operation Conditions Parameter Min. Typ. Max. Units Ambient Operating Temperature -40 +85 °C Power Supply Voltage (measured in respect to GND) +3.0 +5.5 V DC Electrical Characteristics VDD=3.3 V ±10%, Ambient temperature -40 to +85° C, unless stated otherwise Parameter Symbol Conditions Min. Operating Voltage VDD 3.0 Input High Voltage VIH 2 Input Low Voltage VIL Output High Voltage VOH IOH = -12 mA Output Low Voltage VOL IOL = 12 mA Output High Voltage, CMOS level VOH IOH = -4 mA Operating Supply Current IDD No Load Typ. Max. Units 5.5 V V 0.8 IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 3 2.4 V V 0.4 VDD-0.4 V V 35 mA ICS670-04 REV D 110409 ICS670-04 LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER Parameter Symbol ZDB AND MULTIPLIER Conditions Min. Typ. Max. Units Short Circuit Current IOS Each output ±50 mA Internal Pull-up Resistor RPU OE, select pins 200 kΩ Input Capacitance CIN OE, select pins 5 pF AC Electrical Characteristics VDD = 3.3V ±10%, Ambient Temperature -40 to +85° C, unless stated otherwise Parameter Input Clock Frequency Symbol fIN Conditions See table on page 2 Min. Typ. 5 Output Clock Frequency Max. Units 210 MHz 210 MHz Output Rise Time tOR 0.8 to 2.0 V, no load 1.5 ns Output Fall Time tOF 2.0 to 0.8 V, no load 1.5 ns Output Clock Duty Cycle tDC measured at VDD/2 55 % 45 50 Input to Output Skew Note 1 ±100 ps Maximum Absolute Jitter short term ±45 ps Maximum Jitter one sigma 15 ps Phase Noise, relative to carrier, 125 MHz (x5) 100 Hz offset -103 dBc/Hz 1 kHz offset -117 dBc/Hz 10 kHz -111 dBc/Hz 200 kHz -88 dBc/Hz Note 1: Rising edge of ICLK compared with rising edge of CLK2, with FBCLK connected to FBIN, and 15 pF load on CLK2. Note for OE1 The OE1 pin is intended to facilitate board test. Note that disabling the FBLK will open the loop, causing a high-frequency to be output from CLK2. Therefore, set OE1 low only if the chip is in power-down (S3:S0 = 0). Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol Conditions Min. Typ. Max. Units θJA Still air 120 ° C/W θJA 1 m/s air flow 115 ° C/W θJA 3 m/s air flow 105 ° C/W 58 ° C/W θJC IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 4 ICS670-04 REV D 110409 ICS670-04 LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER Phase Noise for 125 MHz output, 25 MHz clock input (VDD = 3.3 V) 0 -20 -40 ICS670-02 phase noise 3.3 V, 25 in 125 out -60 -80 -100 -120 -140 10E+0 100E+0 1E+3 10E+3 IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 5 100E+3 1E+6 10E+6 ICS670-04 REV D 110409 ICS670-04 LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER Package Outline and Package Dimensions (16-pin SOIC, 150 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 16 Symbol E Min A A1 B C D E e H h L α H INDEX AREA 1 2 D A Inches Max Min 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0° 8° Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .3859 .3937 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0° 8° h x 45 A1 C -Ce B SEATING PLANE L .10 (.004) C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 670M-04I* 670M-04IT* 670M-04ILF 670M-04ILFT ICS670M-04I ICS670M-04I 670M-04ILF 670M-04ILF Tubes Tape and Reel Tubes Tape and Reel 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC -40 to +85° C -40 to +85° C -40 to +85° C -40 to +85° C *NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 “LF” denotes Pb (lead) free package. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 6 ICS670-04 REV D 110409 ICS670-04 LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA